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Generate the Verilog code corresponding to this FIRRTL code module MulRawFN_17 :
output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
inst mulFullRaw of MulFullRawFN_17
connect mulFullRaw.io.a.sig, io.a.sig
connect mulFullRaw.io.a.sExp, io.a.sExp
connect mulFullRaw.io.a.sign, io.a.sign
connect mulFullRaw.io.a.isZero, io.a.isZero
connect mulFullRaw.io.a.isInf, io.a.isInf
connect mulFullRaw.io.a.isNaN, io.a.isNaN
connect mulFullRaw.io.b.sig, io.b.sig
connect mulFullRaw.io.b.sExp, io.b.sExp
connect mulFullRaw.io.b.sign, io.b.sign
connect mulFullRaw.io.b.isZero, io.b.isZero
connect mulFullRaw.io.b.isInf, io.b.isInf
connect mulFullRaw.io.b.isNaN, io.b.isNaN
connect io.invalidExc, mulFullRaw.io.invalidExc
connect io.rawOut, mulFullRaw.io.rawOut
node _io_rawOut_sig_T = shr(mulFullRaw.io.rawOut.sig, 22)
node _io_rawOut_sig_T_1 = bits(mulFullRaw.io.rawOut.sig, 21, 0)
node _io_rawOut_sig_T_2 = orr(_io_rawOut_sig_T_1)
node _io_rawOut_sig_T_3 = cat(_io_rawOut_sig_T, _io_rawOut_sig_T_2)
connect io.rawOut.sig, _io_rawOut_sig_T_3 | module MulRawFN_17( // @[MulRecFN.scala:75:7]
input io_a_isNaN, // @[MulRecFN.scala:77:16]
input io_a_isInf, // @[MulRecFN.scala:77:16]
input io_a_isZero, // @[MulRecFN.scala:77:16]
input io_a_sign, // @[MulRecFN.scala:77:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:77:16]
input io_b_isNaN, // @[MulRecFN.scala:77:16]
input io_b_isInf, // @[MulRecFN.scala:77:16]
input io_b_isZero, // @[MulRecFN.scala:77:16]
input io_b_sign, // @[MulRecFN.scala:77:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:77:16]
output io_invalidExc, // @[MulRecFN.scala:77:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:77:16]
output io_rawOut_isInf, // @[MulRecFN.scala:77:16]
output io_rawOut_isZero, // @[MulRecFN.scala:77:16]
output io_rawOut_sign, // @[MulRecFN.scala:77:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16]
output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16]
);
wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28]
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7]
wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7]
wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7]
wire io_invalidExc_0; // @[MulRecFN.scala:75:7]
wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15]
wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37]
wire _io_rawOut_sig_T_2 = |_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}]
assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}]
assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10]
MulFullRawFN_17 mulFullRaw ( // @[MulRecFN.scala:84:28]
.io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7]
.io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7]
.io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7]
.io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7]
.io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7]
.io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7]
.io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7]
.io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7]
.io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7]
.io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7]
.io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7]
.io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7]
.io_invalidExc (io_invalidExc_0),
.io_rawOut_isNaN (io_rawOut_isNaN_0),
.io_rawOut_isInf (io_rawOut_isInf_0),
.io_rawOut_isZero (io_rawOut_isZero_0),
.io_rawOut_sign (io_rawOut_sign_0),
.io_rawOut_sExp (io_rawOut_sExp_0),
.io_rawOut_sig (_mulFullRaw_io_rawOut_sig)
); // @[MulRecFN.scala:84:28]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_44 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4))
node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3)
node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3)
node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit)
node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2)
node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T)
node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit)
node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2)
node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1)
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2)
node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2)
node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit)
node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2)
node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4)
node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit)
node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2)
node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5)
node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit)
node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2)
node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6)
node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit)
node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2)
node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_eq_8 = and(mask_sub_4_2, mask_nbit)
node _mask_acc_T_8 = and(mask_size, mask_eq_8)
node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_4_2, mask_bit)
node _mask_acc_T_9 = and(mask_size, mask_eq_9)
node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_5_2, mask_nbit)
node _mask_acc_T_10 = and(mask_size, mask_eq_10)
node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_5_2, mask_bit)
node _mask_acc_T_11 = and(mask_size, mask_eq_11)
node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_6_2, mask_nbit)
node _mask_acc_T_12 = and(mask_size, mask_eq_12)
node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_6_2, mask_bit)
node _mask_acc_T_13 = and(mask_size, mask_eq_13)
node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_7_2, mask_nbit)
node _mask_acc_T_14 = and(mask_size, mask_eq_14)
node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_7_2, mask_bit)
node _mask_acc_T_15 = and(mask_size, mask_eq_15)
node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15)
node mask_lo_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo)
node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8)
node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10)
node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo)
node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14)
node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = or(UInt<1>(0h0), _T_20)
node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_29 = cvt(_T_28)
node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000)))
node _T_31 = asSInt(_T_30)
node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0)))
node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_27, _T_32)
node _T_64 = or(_T_63, _T_37)
node _T_65 = or(_T_64, _T_42)
node _T_66 = or(_T_65, _T_47)
node _T_67 = or(_T_66, _T_52)
node _T_68 = or(_T_67, _T_57)
node _T_69 = or(_T_68, _T_62)
node _T_70 = and(_T_22, _T_69)
node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_72 = or(UInt<1>(0h0), _T_71)
node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_74 = cvt(_T_73)
node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000)))
node _T_76 = asSInt(_T_75)
node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0)))
node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_79 = cvt(_T_78)
node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000)))
node _T_81 = asSInt(_T_80)
node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0)))
node _T_83 = or(_T_77, _T_82)
node _T_84 = and(_T_72, _T_83)
node _T_85 = or(UInt<1>(0h0), _T_70)
node _T_86 = or(_T_85, _T_84)
node _T_87 = and(_T_21, _T_86)
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_87, UInt<1>(0h1), "") : assert_2
node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_93 = and(_T_91, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_116 = cvt(_T_115)
node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000)))
node _T_118 = asSInt(_T_117)
node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0)))
node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_121 = cvt(_T_120)
node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000)))
node _T_123 = asSInt(_T_122)
node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_126 = cvt(_T_125)
node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000)))
node _T_128 = asSInt(_T_127)
node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_141 = cvt(_T_140)
node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000)))
node _T_143 = asSInt(_T_142)
node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0)))
node _T_145 = or(_T_99, _T_104)
node _T_146 = or(_T_145, _T_109)
node _T_147 = or(_T_146, _T_114)
node _T_148 = or(_T_147, _T_119)
node _T_149 = or(_T_148, _T_124)
node _T_150 = or(_T_149, _T_129)
node _T_151 = or(_T_150, _T_134)
node _T_152 = or(_T_151, _T_139)
node _T_153 = or(_T_152, _T_144)
node _T_154 = and(_T_94, _T_153)
node _T_155 = or(UInt<1>(0h0), _T_154)
node _T_156 = and(UInt<1>(0h0), _T_155)
node _T_157 = asUInt(reset)
node _T_158 = eq(_T_157, UInt<1>(0h0))
when _T_158 :
node _T_159 = eq(_T_156, UInt<1>(0h0))
when _T_159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_156, UInt<1>(0h1), "") : assert_3
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_163 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_163, UInt<1>(0h1), "") : assert_5
node _T_167 = asUInt(reset)
node _T_168 = eq(_T_167, UInt<1>(0h0))
when _T_168 :
node _T_169 = eq(is_aligned, UInt<1>(0h0))
when _T_169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_171 = asUInt(reset)
node _T_172 = eq(_T_171, UInt<1>(0h0))
when _T_172 :
node _T_173 = eq(_T_170, UInt<1>(0h0))
when _T_173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_170, UInt<1>(0h1), "") : assert_7
node _T_174 = not(io.in.a.bits.mask)
node _T_175 = eq(_T_174, UInt<1>(0h0))
node _T_176 = asUInt(reset)
node _T_177 = eq(_T_176, UInt<1>(0h0))
when _T_177 :
node _T_178 = eq(_T_175, UInt<1>(0h0))
when _T_178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_175, UInt<1>(0h1), "") : assert_8
node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(_T_179, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_179, UInt<1>(0h1), "") : assert_9
node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_183 :
node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_188 = and(_T_186, _T_187)
node _T_189 = or(UInt<1>(0h0), _T_188)
node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_202 = cvt(_T_201)
node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000)))
node _T_204 = asSInt(_T_203)
node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0)))
node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_227 = cvt(_T_226)
node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000)))
node _T_229 = asSInt(_T_228)
node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0)))
node _T_231 = or(_T_195, _T_200)
node _T_232 = or(_T_231, _T_205)
node _T_233 = or(_T_232, _T_210)
node _T_234 = or(_T_233, _T_215)
node _T_235 = or(_T_234, _T_220)
node _T_236 = or(_T_235, _T_225)
node _T_237 = or(_T_236, _T_230)
node _T_238 = and(_T_190, _T_237)
node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_240 = or(UInt<1>(0h0), _T_239)
node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = or(_T_245, _T_250)
node _T_252 = and(_T_240, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_238)
node _T_254 = or(_T_253, _T_252)
node _T_255 = and(_T_189, _T_254)
node _T_256 = asUInt(reset)
node _T_257 = eq(_T_256, UInt<1>(0h0))
when _T_257 :
node _T_258 = eq(_T_255, UInt<1>(0h0))
when _T_258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_255, UInt<1>(0h1), "") : assert_10
node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_261 = and(_T_259, _T_260)
node _T_262 = or(UInt<1>(0h0), _T_261)
node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_264 = cvt(_T_263)
node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000)))
node _T_266 = asSInt(_T_265)
node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0)))
node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_269 = cvt(_T_268)
node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000)))
node _T_271 = asSInt(_T_270)
node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0)))
node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_274 = cvt(_T_273)
node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000)))
node _T_276 = asSInt(_T_275)
node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0)))
node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_279 = cvt(_T_278)
node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000)))
node _T_281 = asSInt(_T_280)
node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0)))
node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_284 = cvt(_T_283)
node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000)))
node _T_286 = asSInt(_T_285)
node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0)))
node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_289 = cvt(_T_288)
node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000)))
node _T_291 = asSInt(_T_290)
node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0)))
node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_294 = cvt(_T_293)
node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000)))
node _T_296 = asSInt(_T_295)
node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0)))
node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = or(_T_267, _T_272)
node _T_314 = or(_T_313, _T_277)
node _T_315 = or(_T_314, _T_282)
node _T_316 = or(_T_315, _T_287)
node _T_317 = or(_T_316, _T_292)
node _T_318 = or(_T_317, _T_297)
node _T_319 = or(_T_318, _T_302)
node _T_320 = or(_T_319, _T_307)
node _T_321 = or(_T_320, _T_312)
node _T_322 = and(_T_262, _T_321)
node _T_323 = or(UInt<1>(0h0), _T_322)
node _T_324 = and(UInt<1>(0h0), _T_323)
node _T_325 = asUInt(reset)
node _T_326 = eq(_T_325, UInt<1>(0h0))
when _T_326 :
node _T_327 = eq(_T_324, UInt<1>(0h0))
when _T_327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_324, UInt<1>(0h1), "") : assert_11
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_331 = geq(io.in.a.bits.size, UInt<3>(0h4))
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_331, UInt<1>(0h1), "") : assert_13
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(is_aligned, UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_338, UInt<1>(0h1), "") : assert_15
node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_342, UInt<1>(0h1), "") : assert_16
node _T_346 = not(io.in.a.bits.mask)
node _T_347 = eq(_T_346, UInt<1>(0h0))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_347, UInt<1>(0h1), "") : assert_17
node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_351, UInt<1>(0h1), "") : assert_18
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_360 = and(_T_358, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_361, UInt<1>(0h1), "") : assert_19
node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_367 = and(_T_365, _T_366)
node _T_368 = or(UInt<1>(0h0), _T_367)
node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_370 = cvt(_T_369)
node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000)))
node _T_372 = asSInt(_T_371)
node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0)))
node _T_374 = and(_T_368, _T_373)
node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_377 = and(_T_375, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_380 = cvt(_T_379)
node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000)))
node _T_382 = asSInt(_T_381)
node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0)))
node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_385 = cvt(_T_384)
node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000)))
node _T_387 = asSInt(_T_386)
node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0)))
node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_420 = cvt(_T_419)
node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000)))
node _T_422 = asSInt(_T_421)
node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0)))
node _T_424 = or(_T_383, _T_388)
node _T_425 = or(_T_424, _T_393)
node _T_426 = or(_T_425, _T_398)
node _T_427 = or(_T_426, _T_403)
node _T_428 = or(_T_427, _T_408)
node _T_429 = or(_T_428, _T_413)
node _T_430 = or(_T_429, _T_418)
node _T_431 = or(_T_430, _T_423)
node _T_432 = and(_T_378, _T_431)
node _T_433 = or(UInt<1>(0h0), _T_374)
node _T_434 = or(_T_433, _T_432)
node _T_435 = asUInt(reset)
node _T_436 = eq(_T_435, UInt<1>(0h0))
when _T_436 :
node _T_437 = eq(_T_434, UInt<1>(0h0))
when _T_437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_434, UInt<1>(0h1), "") : assert_20
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(is_aligned, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_445 = asUInt(reset)
node _T_446 = eq(_T_445, UInt<1>(0h0))
when _T_446 :
node _T_447 = eq(_T_444, UInt<1>(0h0))
when _T_447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_444, UInt<1>(0h1), "") : assert_23
node _T_448 = eq(io.in.a.bits.mask, mask)
node _T_449 = asUInt(reset)
node _T_450 = eq(_T_449, UInt<1>(0h0))
when _T_450 :
node _T_451 = eq(_T_448, UInt<1>(0h0))
when _T_451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_448, UInt<1>(0h1), "") : assert_24
node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_452, UInt<1>(0h1), "") : assert_25
node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_456 :
node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_459 = and(_T_457, _T_458)
node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_461 = and(_T_459, _T_460)
node _T_462 = or(UInt<1>(0h0), _T_461)
node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_465 = and(_T_463, _T_464)
node _T_466 = or(UInt<1>(0h0), _T_465)
node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = and(_T_466, _T_471)
node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_475 = and(_T_473, _T_474)
node _T_476 = or(UInt<1>(0h0), _T_475)
node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_478 = cvt(_T_477)
node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000)))
node _T_480 = asSInt(_T_479)
node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0)))
node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_483 = cvt(_T_482)
node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000)))
node _T_485 = asSInt(_T_484)
node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0)))
node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_488 = cvt(_T_487)
node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000)))
node _T_490 = asSInt(_T_489)
node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0)))
node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_493 = cvt(_T_492)
node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000)))
node _T_495 = asSInt(_T_494)
node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0)))
node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_498 = cvt(_T_497)
node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000)))
node _T_500 = asSInt(_T_499)
node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0)))
node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_503 = cvt(_T_502)
node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000)))
node _T_505 = asSInt(_T_504)
node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0)))
node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_508 = cvt(_T_507)
node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000)))
node _T_510 = asSInt(_T_509)
node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0)))
node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_513 = cvt(_T_512)
node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000)))
node _T_515 = asSInt(_T_514)
node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0)))
node _T_517 = or(_T_481, _T_486)
node _T_518 = or(_T_517, _T_491)
node _T_519 = or(_T_518, _T_496)
node _T_520 = or(_T_519, _T_501)
node _T_521 = or(_T_520, _T_506)
node _T_522 = or(_T_521, _T_511)
node _T_523 = or(_T_522, _T_516)
node _T_524 = and(_T_476, _T_523)
node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = and(_T_525, _T_530)
node _T_532 = or(UInt<1>(0h0), _T_472)
node _T_533 = or(_T_532, _T_524)
node _T_534 = or(_T_533, _T_531)
node _T_535 = and(_T_462, _T_534)
node _T_536 = asUInt(reset)
node _T_537 = eq(_T_536, UInt<1>(0h0))
when _T_537 :
node _T_538 = eq(_T_535, UInt<1>(0h0))
when _T_538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_535, UInt<1>(0h1), "") : assert_26
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_542 = asUInt(reset)
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(is_aligned, UInt<1>(0h0))
when _T_544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_546 = asUInt(reset)
node _T_547 = eq(_T_546, UInt<1>(0h0))
when _T_547 :
node _T_548 = eq(_T_545, UInt<1>(0h0))
when _T_548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_545, UInt<1>(0h1), "") : assert_29
node _T_549 = eq(io.in.a.bits.mask, mask)
node _T_550 = asUInt(reset)
node _T_551 = eq(_T_550, UInt<1>(0h0))
when _T_551 :
node _T_552 = eq(_T_549, UInt<1>(0h0))
when _T_552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_549, UInt<1>(0h1), "") : assert_30
node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_553 :
node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_556 = and(_T_554, _T_555)
node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_558 = and(_T_556, _T_557)
node _T_559 = or(UInt<1>(0h0), _T_558)
node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_562 = and(_T_560, _T_561)
node _T_563 = or(UInt<1>(0h0), _T_562)
node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_565 = cvt(_T_564)
node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000)))
node _T_567 = asSInt(_T_566)
node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0)))
node _T_569 = and(_T_563, _T_568)
node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_572 = and(_T_570, _T_571)
node _T_573 = or(UInt<1>(0h0), _T_572)
node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_575 = cvt(_T_574)
node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000)))
node _T_577 = asSInt(_T_576)
node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0)))
node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_585 = cvt(_T_584)
node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000)))
node _T_587 = asSInt(_T_586)
node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0)))
node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_590 = cvt(_T_589)
node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000)))
node _T_592 = asSInt(_T_591)
node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0)))
node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_600 = cvt(_T_599)
node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000)))
node _T_602 = asSInt(_T_601)
node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0)))
node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = or(_T_578, _T_583)
node _T_615 = or(_T_614, _T_588)
node _T_616 = or(_T_615, _T_593)
node _T_617 = or(_T_616, _T_598)
node _T_618 = or(_T_617, _T_603)
node _T_619 = or(_T_618, _T_608)
node _T_620 = or(_T_619, _T_613)
node _T_621 = and(_T_573, _T_620)
node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_624 = cvt(_T_623)
node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000)))
node _T_626 = asSInt(_T_625)
node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0)))
node _T_628 = and(_T_622, _T_627)
node _T_629 = or(UInt<1>(0h0), _T_569)
node _T_630 = or(_T_629, _T_621)
node _T_631 = or(_T_630, _T_628)
node _T_632 = and(_T_559, _T_631)
node _T_633 = asUInt(reset)
node _T_634 = eq(_T_633, UInt<1>(0h0))
when _T_634 :
node _T_635 = eq(_T_632, UInt<1>(0h0))
when _T_635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_632, UInt<1>(0h1), "") : assert_31
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(is_aligned, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_642, UInt<1>(0h1), "") : assert_34
node _T_646 = not(mask)
node _T_647 = and(io.in.a.bits.mask, _T_646)
node _T_648 = eq(_T_647, UInt<1>(0h0))
node _T_649 = asUInt(reset)
node _T_650 = eq(_T_649, UInt<1>(0h0))
when _T_650 :
node _T_651 = eq(_T_648, UInt<1>(0h0))
when _T_651 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_648, UInt<1>(0h1), "") : assert_35
node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_652 :
node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_655 = and(_T_653, _T_654)
node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_657 = and(_T_655, _T_656)
node _T_658 = or(UInt<1>(0h0), _T_657)
node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_661 = and(_T_659, _T_660)
node _T_662 = or(UInt<1>(0h0), _T_661)
node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_669 = cvt(_T_668)
node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000)))
node _T_671 = asSInt(_T_670)
node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0)))
node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_674 = cvt(_T_673)
node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000)))
node _T_676 = asSInt(_T_675)
node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0)))
node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_679 = cvt(_T_678)
node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000)))
node _T_681 = asSInt(_T_680)
node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0)))
node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_684 = cvt(_T_683)
node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000)))
node _T_686 = asSInt(_T_685)
node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0)))
node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_689 = cvt(_T_688)
node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000)))
node _T_691 = asSInt(_T_690)
node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0)))
node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_694 = cvt(_T_693)
node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000)))
node _T_696 = asSInt(_T_695)
node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0)))
node _T_698 = or(_T_667, _T_672)
node _T_699 = or(_T_698, _T_677)
node _T_700 = or(_T_699, _T_682)
node _T_701 = or(_T_700, _T_687)
node _T_702 = or(_T_701, _T_692)
node _T_703 = or(_T_702, _T_697)
node _T_704 = and(_T_662, _T_703)
node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_707 = cvt(_T_706)
node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000)))
node _T_709 = asSInt(_T_708)
node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0)))
node _T_711 = and(_T_705, _T_710)
node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_714 = and(_T_712, _T_713)
node _T_715 = or(UInt<1>(0h0), _T_714)
node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_717 = cvt(_T_716)
node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000)))
node _T_719 = asSInt(_T_718)
node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0)))
node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_722 = cvt(_T_721)
node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000)))
node _T_724 = asSInt(_T_723)
node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0)))
node _T_726 = or(_T_720, _T_725)
node _T_727 = and(_T_715, _T_726)
node _T_728 = or(UInt<1>(0h0), _T_704)
node _T_729 = or(_T_728, _T_711)
node _T_730 = or(_T_729, _T_727)
node _T_731 = and(_T_658, _T_730)
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(_T_731, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_731, UInt<1>(0h1), "") : assert_36
node _T_735 = asUInt(reset)
node _T_736 = eq(_T_735, UInt<1>(0h0))
when _T_736 :
node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_737 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(is_aligned, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(_T_741, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_741, UInt<1>(0h1), "") : assert_39
node _T_745 = eq(io.in.a.bits.mask, mask)
node _T_746 = asUInt(reset)
node _T_747 = eq(_T_746, UInt<1>(0h0))
when _T_747 :
node _T_748 = eq(_T_745, UInt<1>(0h0))
when _T_748 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_745, UInt<1>(0h1), "") : assert_40
node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_749 :
node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_752 = and(_T_750, _T_751)
node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_754 = and(_T_752, _T_753)
node _T_755 = or(UInt<1>(0h0), _T_754)
node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_758 = and(_T_756, _T_757)
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_761 = cvt(_T_760)
node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000)))
node _T_763 = asSInt(_T_762)
node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0)))
node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_766 = cvt(_T_765)
node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000)))
node _T_768 = asSInt(_T_767)
node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0)))
node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_771 = cvt(_T_770)
node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000)))
node _T_773 = asSInt(_T_772)
node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0)))
node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_776 = cvt(_T_775)
node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000)))
node _T_778 = asSInt(_T_777)
node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0)))
node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_781 = cvt(_T_780)
node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000)))
node _T_783 = asSInt(_T_782)
node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0)))
node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_786 = cvt(_T_785)
node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000)))
node _T_788 = asSInt(_T_787)
node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0)))
node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_791 = cvt(_T_790)
node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000)))
node _T_793 = asSInt(_T_792)
node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0)))
node _T_795 = or(_T_764, _T_769)
node _T_796 = or(_T_795, _T_774)
node _T_797 = or(_T_796, _T_779)
node _T_798 = or(_T_797, _T_784)
node _T_799 = or(_T_798, _T_789)
node _T_800 = or(_T_799, _T_794)
node _T_801 = and(_T_759, _T_800)
node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_804 = cvt(_T_803)
node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000)))
node _T_806 = asSInt(_T_805)
node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0)))
node _T_808 = and(_T_802, _T_807)
node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4))
node _T_811 = and(_T_809, _T_810)
node _T_812 = or(UInt<1>(0h0), _T_811)
node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_814 = cvt(_T_813)
node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000)))
node _T_816 = asSInt(_T_815)
node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0)))
node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_819 = cvt(_T_818)
node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000)))
node _T_821 = asSInt(_T_820)
node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0)))
node _T_823 = or(_T_817, _T_822)
node _T_824 = and(_T_812, _T_823)
node _T_825 = or(UInt<1>(0h0), _T_801)
node _T_826 = or(_T_825, _T_808)
node _T_827 = or(_T_826, _T_824)
node _T_828 = and(_T_755, _T_827)
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(_T_828, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_828, UInt<1>(0h1), "") : assert_41
node _T_832 = asUInt(reset)
node _T_833 = eq(_T_832, UInt<1>(0h0))
when _T_833 :
node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_834 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(is_aligned, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_839 = asUInt(reset)
node _T_840 = eq(_T_839, UInt<1>(0h0))
when _T_840 :
node _T_841 = eq(_T_838, UInt<1>(0h0))
when _T_841 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_838, UInt<1>(0h1), "") : assert_44
node _T_842 = eq(io.in.a.bits.mask, mask)
node _T_843 = asUInt(reset)
node _T_844 = eq(_T_843, UInt<1>(0h0))
when _T_844 :
node _T_845 = eq(_T_842, UInt<1>(0h0))
when _T_845 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_842, UInt<1>(0h1), "") : assert_45
node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_846 :
node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_849 = and(_T_847, _T_848)
node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_851 = and(_T_849, _T_850)
node _T_852 = or(UInt<1>(0h0), _T_851)
node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_855 = and(_T_853, _T_854)
node _T_856 = or(UInt<1>(0h0), _T_855)
node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_858 = cvt(_T_857)
node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000)))
node _T_860 = asSInt(_T_859)
node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0)))
node _T_862 = and(_T_856, _T_861)
node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_865 = cvt(_T_864)
node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000)))
node _T_867 = asSInt(_T_866)
node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0)))
node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_870 = cvt(_T_869)
node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000)))
node _T_872 = asSInt(_T_871)
node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0)))
node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_880 = cvt(_T_879)
node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000)))
node _T_882 = asSInt(_T_881)
node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0)))
node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_885 = cvt(_T_884)
node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000)))
node _T_887 = asSInt(_T_886)
node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0)))
node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_890 = cvt(_T_889)
node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000)))
node _T_892 = asSInt(_T_891)
node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0)))
node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_895 = cvt(_T_894)
node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000)))
node _T_897 = asSInt(_T_896)
node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0)))
node _T_899 = or(_T_868, _T_873)
node _T_900 = or(_T_899, _T_878)
node _T_901 = or(_T_900, _T_883)
node _T_902 = or(_T_901, _T_888)
node _T_903 = or(_T_902, _T_893)
node _T_904 = or(_T_903, _T_898)
node _T_905 = and(_T_863, _T_904)
node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_908 = and(_T_906, _T_907)
node _T_909 = or(UInt<1>(0h0), _T_908)
node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_911 = cvt(_T_910)
node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000)))
node _T_913 = asSInt(_T_912)
node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0)))
node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_916 = cvt(_T_915)
node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000)))
node _T_918 = asSInt(_T_917)
node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0)))
node _T_920 = or(_T_914, _T_919)
node _T_921 = and(_T_909, _T_920)
node _T_922 = or(UInt<1>(0h0), _T_862)
node _T_923 = or(_T_922, _T_905)
node _T_924 = or(_T_923, _T_921)
node _T_925 = and(_T_852, _T_924)
node _T_926 = asUInt(reset)
node _T_927 = eq(_T_926, UInt<1>(0h0))
when _T_927 :
node _T_928 = eq(_T_925, UInt<1>(0h0))
when _T_928 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_925, UInt<1>(0h1), "") : assert_46
node _T_929 = asUInt(reset)
node _T_930 = eq(_T_929, UInt<1>(0h0))
when _T_930 :
node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_931 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_932 = asUInt(reset)
node _T_933 = eq(_T_932, UInt<1>(0h0))
when _T_933 :
node _T_934 = eq(is_aligned, UInt<1>(0h0))
when _T_934 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_936 = asUInt(reset)
node _T_937 = eq(_T_936, UInt<1>(0h0))
when _T_937 :
node _T_938 = eq(_T_935, UInt<1>(0h0))
when _T_938 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_935, UInt<1>(0h1), "") : assert_49
node _T_939 = eq(io.in.a.bits.mask, mask)
node _T_940 = asUInt(reset)
node _T_941 = eq(_T_940, UInt<1>(0h0))
when _T_941 :
node _T_942 = eq(_T_939, UInt<1>(0h0))
when _T_942 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_939, UInt<1>(0h1), "") : assert_50
node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_944 = asUInt(reset)
node _T_945 = eq(_T_944, UInt<1>(0h0))
when _T_945 :
node _T_946 = eq(_T_943, UInt<1>(0h0))
when _T_946 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_943, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_948 = asUInt(reset)
node _T_949 = eq(_T_948, UInt<1>(0h0))
when _T_949 :
node _T_950 = eq(_T_947, UInt<1>(0h0))
when _T_950 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_947, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10))
node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_951 :
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_955 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(_T_955, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_955, UInt<1>(0h1), "") : assert_54
node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(_T_959, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_959, UInt<1>(0h1), "") : assert_55
node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_T_963, UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_963, UInt<1>(0h1), "") : assert_56
node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_968 = asUInt(reset)
node _T_969 = eq(_T_968, UInt<1>(0h0))
when _T_969 :
node _T_970 = eq(_T_967, UInt<1>(0h0))
when _T_970 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_967, UInt<1>(0h1), "") : assert_57
node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_971 :
node _T_972 = asUInt(reset)
node _T_973 = eq(_T_972, UInt<1>(0h0))
when _T_973 :
node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_974 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_975 = asUInt(reset)
node _T_976 = eq(_T_975, UInt<1>(0h0))
when _T_976 :
node _T_977 = eq(sink_ok, UInt<1>(0h0))
when _T_977 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_978 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_979 = asUInt(reset)
node _T_980 = eq(_T_979, UInt<1>(0h0))
when _T_980 :
node _T_981 = eq(_T_978, UInt<1>(0h0))
when _T_981 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_978, UInt<1>(0h1), "") : assert_60
node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_983 = asUInt(reset)
node _T_984 = eq(_T_983, UInt<1>(0h0))
when _T_984 :
node _T_985 = eq(_T_982, UInt<1>(0h0))
when _T_985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_982, UInt<1>(0h1), "") : assert_61
node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_987 = asUInt(reset)
node _T_988 = eq(_T_987, UInt<1>(0h0))
when _T_988 :
node _T_989 = eq(_T_986, UInt<1>(0h0))
when _T_989 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_986, UInt<1>(0h1), "") : assert_62
node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_990, UInt<1>(0h1), "") : assert_63
node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_995 = or(UInt<1>(0h1), _T_994)
node _T_996 = asUInt(reset)
node _T_997 = eq(_T_996, UInt<1>(0h0))
when _T_997 :
node _T_998 = eq(_T_995, UInt<1>(0h0))
when _T_998 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_995, UInt<1>(0h1), "") : assert_64
node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_999 :
node _T_1000 = asUInt(reset)
node _T_1001 = eq(_T_1000, UInt<1>(0h0))
when _T_1001 :
node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(sink_ok, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1006 = geq(io.in.d.bits.size, UInt<3>(0h4))
node _T_1007 = asUInt(reset)
node _T_1008 = eq(_T_1007, UInt<1>(0h0))
when _T_1008 :
node _T_1009 = eq(_T_1006, UInt<1>(0h0))
when _T_1009 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67
node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68
node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69
node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1019 = or(_T_1018, io.in.d.bits.corrupt)
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(_T_1019, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70
node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1024 = or(UInt<1>(0h1), _T_1023)
node _T_1025 = asUInt(reset)
node _T_1026 = eq(_T_1025, UInt<1>(0h0))
when _T_1026 :
node _T_1027 = eq(_T_1024, UInt<1>(0h0))
when _T_1027 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71
node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(_T_1032, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73
node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74
node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1041 = or(UInt<1>(0h1), _T_1040)
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(_T_1041, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75
node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1045 :
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77
node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1054 = or(_T_1053, io.in.d.bits.corrupt)
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78
node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1059 = or(UInt<1>(0h1), _T_1058)
node _T_1060 = asUInt(reset)
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(_T_1059, UInt<1>(0h0))
when _T_1062 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79
node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1063 :
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1068 = asUInt(reset)
node _T_1069 = eq(_T_1068, UInt<1>(0h0))
when _T_1069 :
node _T_1070 = eq(_T_1067, UInt<1>(0h0))
when _T_1070 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81
node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1072 = asUInt(reset)
node _T_1073 = eq(_T_1072, UInt<1>(0h0))
when _T_1073 :
node _T_1074 = eq(_T_1071, UInt<1>(0h0))
when _T_1074 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82
node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1076 = or(UInt<1>(0h1), _T_1075)
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<128>(0h0)
connect _WIRE.bits.mask, UInt<16>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<128>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(_T_1084, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_4.bits.sink, UInt<4>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(_T_1088, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1092 = eq(a_first, UInt<1>(0h0))
node _T_1093 = and(io.in.a.valid, _T_1092)
when _T_1093 :
node _T_1094 = eq(io.in.a.bits.opcode, opcode)
node _T_1095 = asUInt(reset)
node _T_1096 = eq(_T_1095, UInt<1>(0h0))
when _T_1096 :
node _T_1097 = eq(_T_1094, UInt<1>(0h0))
when _T_1097 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87
node _T_1098 = eq(io.in.a.bits.param, param)
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_T_1098, UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88
node _T_1102 = eq(io.in.a.bits.size, size)
node _T_1103 = asUInt(reset)
node _T_1104 = eq(_T_1103, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = eq(_T_1102, UInt<1>(0h0))
when _T_1105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89
node _T_1106 = eq(io.in.a.bits.source, source)
node _T_1107 = asUInt(reset)
node _T_1108 = eq(_T_1107, UInt<1>(0h0))
when _T_1108 :
node _T_1109 = eq(_T_1106, UInt<1>(0h0))
when _T_1109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90
node _T_1110 = eq(io.in.a.bits.address, address)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91
node _T_1114 = and(io.in.a.ready, io.in.a.valid)
node _T_1115 = and(_T_1114, a_first)
when _T_1115 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1116 = eq(d_first, UInt<1>(0h0))
node _T_1117 = and(io.in.d.valid, _T_1116)
when _T_1117 :
node _T_1118 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1119 = asUInt(reset)
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
when _T_1120 :
node _T_1121 = eq(_T_1118, UInt<1>(0h0))
when _T_1121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92
node _T_1122 = eq(io.in.d.bits.param, param_1)
node _T_1123 = asUInt(reset)
node _T_1124 = eq(_T_1123, UInt<1>(0h0))
when _T_1124 :
node _T_1125 = eq(_T_1122, UInt<1>(0h0))
when _T_1125 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93
node _T_1126 = eq(io.in.d.bits.size, size_1)
node _T_1127 = asUInt(reset)
node _T_1128 = eq(_T_1127, UInt<1>(0h0))
when _T_1128 :
node _T_1129 = eq(_T_1126, UInt<1>(0h0))
when _T_1129 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94
node _T_1130 = eq(io.in.d.bits.source, source_1)
node _T_1131 = asUInt(reset)
node _T_1132 = eq(_T_1131, UInt<1>(0h0))
when _T_1132 :
node _T_1133 = eq(_T_1130, UInt<1>(0h0))
when _T_1133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95
node _T_1134 = eq(io.in.d.bits.sink, sink)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96
node _T_1138 = eq(io.in.d.bits.denied, denied)
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97
node _T_1142 = and(io.in.d.ready, io.in.d.valid)
node _T_1143 = and(_T_1142, d_first)
when _T_1143 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<8>
connect a_sizes_set, UInt<8>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1144 = and(io.in.a.valid, a_first_1)
node _T_1145 = and(_T_1144, UInt<1>(0h1))
when _T_1145 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1146 = and(io.in.a.ready, io.in.a.valid)
node _T_1147 = and(_T_1146, a_first_1)
node _T_1148 = and(_T_1147, UInt<1>(0h1))
when _T_1148 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1149 = dshr(inflight, io.in.a.bits.source)
node _T_1150 = bits(_T_1149, 0, 0)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
node _T_1152 = asUInt(reset)
node _T_1153 = eq(_T_1152, UInt<1>(0h0))
when _T_1153 :
node _T_1154 = eq(_T_1151, UInt<1>(0h0))
when _T_1154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<8>
connect d_sizes_clr, UInt<8>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1155 = and(io.in.d.valid, d_first_1)
node _T_1156 = and(_T_1155, UInt<1>(0h1))
node _T_1157 = eq(d_release_ack, UInt<1>(0h0))
node _T_1158 = and(_T_1156, _T_1157)
when _T_1158 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1159 = and(io.in.d.ready, io.in.d.valid)
node _T_1160 = and(_T_1159, d_first_1)
node _T_1161 = and(_T_1160, UInt<1>(0h1))
node _T_1162 = eq(d_release_ack, UInt<1>(0h0))
node _T_1163 = and(_T_1161, _T_1162)
when _T_1163 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1164 = and(io.in.d.valid, d_first_1)
node _T_1165 = and(_T_1164, UInt<1>(0h1))
node _T_1166 = eq(d_release_ack, UInt<1>(0h0))
node _T_1167 = and(_T_1165, _T_1166)
when _T_1167 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1168 = dshr(inflight, io.in.d.bits.source)
node _T_1169 = bits(_T_1168, 0, 0)
node _T_1170 = or(_T_1169, same_cycle_resp)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1176 = or(_T_1174, _T_1175)
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(_T_1176, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100
node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101
else :
node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1186 = or(_T_1184, _T_1185)
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102
node _T_1190 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103
node _T_1194 = and(io.in.d.valid, d_first_1)
node _T_1195 = and(_T_1194, a_first_1)
node _T_1196 = and(_T_1195, io.in.a.valid)
node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1198 = and(_T_1196, _T_1197)
node _T_1199 = eq(d_release_ack, UInt<1>(0h0))
node _T_1200 = and(_T_1198, _T_1199)
when _T_1200 :
node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1202 = or(_T_1201, io.in.a.ready)
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104
node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1207 = orr(a_set_wo_ready)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
node _T_1209 = or(_T_1206, _T_1208)
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(_T_1209, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_88
node _T_1213 = orr(inflight)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1216 = or(_T_1214, _T_1215)
node _T_1217 = lt(watchdog, plusarg_reader.out)
node _T_1218 = or(_T_1216, _T_1217)
node _T_1219 = asUInt(reset)
node _T_1220 = eq(_T_1219, UInt<1>(0h0))
when _T_1220 :
node _T_1221 = eq(_T_1218, UInt<1>(0h0))
when _T_1221 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1222 = and(io.in.a.ready, io.in.a.valid)
node _T_1223 = and(io.in.d.ready, io.in.d.valid)
node _T_1224 = or(_T_1222, _T_1223)
when _T_1224 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<128>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<128>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<8>
connect c_sizes_set, UInt<8>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<128>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1225 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<128>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1228 = and(_T_1226, _T_1227)
node _T_1229 = and(_T_1225, _T_1228)
when _T_1229 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<128>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1231 = and(_T_1230, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<128>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1234 = and(_T_1232, _T_1233)
node _T_1235 = and(_T_1231, _T_1234)
when _T_1235 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<128>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1237 = bits(_T_1236, 0, 0)
node _T_1238 = eq(_T_1237, UInt<1>(0h0))
node _T_1239 = asUInt(reset)
node _T_1240 = eq(_T_1239, UInt<1>(0h0))
when _T_1240 :
node _T_1241 = eq(_T_1238, UInt<1>(0h0))
when _T_1241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<8>
connect d_sizes_clr_1, UInt<8>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1242 = and(io.in.d.valid, d_first_2)
node _T_1243 = and(_T_1242, UInt<1>(0h1))
node _T_1244 = and(_T_1243, d_release_ack_1)
when _T_1244 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1245 = and(io.in.d.ready, io.in.d.valid)
node _T_1246 = and(_T_1245, d_first_2)
node _T_1247 = and(_T_1246, UInt<1>(0h1))
node _T_1248 = and(_T_1247, d_release_ack_1)
when _T_1248 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1249 = and(io.in.d.valid, d_first_2)
node _T_1250 = and(_T_1249, UInt<1>(0h1))
node _T_1251 = and(_T_1250, d_release_ack_1)
when _T_1251 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1252 = dshr(inflight_1, io.in.d.bits.source)
node _T_1253 = bits(_T_1252, 0, 0)
node _T_1254 = or(_T_1253, same_cycle_resp_1)
node _T_1255 = asUInt(reset)
node _T_1256 = eq(_T_1255, UInt<1>(0h0))
when _T_1256 :
node _T_1257 = eq(_T_1254, UInt<1>(0h0))
when _T_1257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<128>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1259 = asUInt(reset)
node _T_1260 = eq(_T_1259, UInt<1>(0h0))
when _T_1260 :
node _T_1261 = eq(_T_1258, UInt<1>(0h0))
when _T_1261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109
else :
node _T_1262 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1263 = asUInt(reset)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
when _T_1264 :
node _T_1265 = eq(_T_1262, UInt<1>(0h0))
when _T_1265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110
node _T_1266 = and(io.in.d.valid, d_first_2)
node _T_1267 = and(_T_1266, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<128>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1268 = and(_T_1267, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<128>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1270 = and(_T_1268, _T_1269)
node _T_1271 = and(_T_1270, d_release_ack_1)
node _T_1272 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1273 = and(_T_1271, _T_1272)
when _T_1273 :
node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<128>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1275 = or(_T_1274, _WIRE_23.ready)
node _T_1276 = asUInt(reset)
node _T_1277 = eq(_T_1276, UInt<1>(0h0))
when _T_1277 :
node _T_1278 = eq(_T_1275, UInt<1>(0h0))
when _T_1278 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111
node _T_1279 = orr(c_set_wo_ready)
when _T_1279 :
node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1281 = asUInt(reset)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
when _T_1282 :
node _T_1283 = eq(_T_1280, UInt<1>(0h0))
when _T_1283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_89
node _T_1284 = orr(inflight_1)
node _T_1285 = eq(_T_1284, UInt<1>(0h0))
node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1287 = or(_T_1285, _T_1286)
node _T_1288 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1289 = or(_T_1287, _T_1288)
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v4/common/tile.scala:139:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<128>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1294 = and(io.in.d.ready, io.in.d.valid)
node _T_1295 = or(_T_1293, _T_1294)
when _T_1295 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_44( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28]
wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [7:0] a_first_beats1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] a_first_count = 8'h0; // @[Edges.scala:234:25]
wire [7:0] a_first_beats1_1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] a_first_count_1 = 8'h0; // @[Edges.scala:234:25]
wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59]
wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27]
wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25]
wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [7:0] mask_lo = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] mask_hi = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28]
wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28]
wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7]
wire [3:0] _mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [15:0] io_in_a_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7]
wire [15:0] mask = 16'hFFFF; // @[Misc.scala:222:10]
wire [127:0] io_in_a_bits_data = 128'h0; // @[Monitor.scala:36:7]
wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [3:0] mask_lo_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_lo_hi = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] mask_hi_hi = 4'hF; // @[Misc.scala:222:10]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59]
wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51]
wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [7:0] a_first_beats1_decode = 8'h3; // @[Edges.scala:220:59]
wire [7:0] a_first_beats1_decode_1 = 8'h3; // @[Edges.scala:220:59]
wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46]
wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46]
wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76]
wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76]
wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76]
wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71]
wire [1:0] mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [3:0] mask_sizeOH = 4'h5; // @[Misc.scala:202:81]
wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26]
wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T_2 = mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38]
wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_sub_acc_T_3 = mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38]
wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38]
wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38]
wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38]
wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38]
wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38]
wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38]
wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38]
wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
reg [7:0] a_first_counter; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] _a_first_counter_T = a_first ? 8'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [31:0] address; // @[Monitor.scala:391:22]
wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [3:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
reg [7:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] _a_first_counter_T_1 = a_first_1 ? 8'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_0 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_0; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_0; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_0; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _GEN_1 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:641:65]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:641:65, :681:99]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:641:65, :750:67]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:641:65, :791:99]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35]
assign a_opcodes_set_interm = a_set ? 4'h9 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28]
assign a_sizes_set_interm = a_set ? 5'hD : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_2 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_2; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_2; // @[Monitor.scala:673:46, :783:46]
wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_3 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1194 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1163 = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :673:46, :674:74, :678:{25,70}]
assign d_clr = _T_1163 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1163 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1163 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46]
wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [7:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28]
wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_1248 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :783:46, :788:{25,70}]
assign d_clr_1 = _T_1248 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1248 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1248 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_99 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_99( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_14 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, virt_channel_id : UInt<4>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1)
reg flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}, clock
inst q of Queue3_EgressFlit_14
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.valid, io.in[0].valid
connect q.io.enq.bits.head, io.in[0].bits.head
connect q.io.enq.bits.tail, io.in[0].bits.tail
node _q_io_enq_bits_ingress_id_T = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1)
node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4)
node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7)
node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10)
node _q_io_enq_bits_ingress_id_T_12 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h4), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_13 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h7), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_14 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0ha), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_15 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0hd), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_16 = or(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13)
node _q_io_enq_bits_ingress_id_T_17 = or(_q_io_enq_bits_ingress_id_T_16, _q_io_enq_bits_ingress_id_T_14)
node _q_io_enq_bits_ingress_id_T_18 = or(_q_io_enq_bits_ingress_id_T_17, _q_io_enq_bits_ingress_id_T_15)
wire _q_io_enq_bits_ingress_id_WIRE : UInt<5>
connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_18
connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE
connect q.io.enq.bits.payload, io.in[0].bits.payload
connect io.out.bits, q.io.deq.bits
connect io.out.valid, q.io.deq.valid
connect q.io.deq.ready, io.out.ready
node _T = eq(q.io.enq.ready, UInt<1>(0h0))
node _T_1 = and(q.io.enq.valid, _T)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0))
connect io.credit_available[0], _io_credit_available_0_T
node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0))
connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T
connect io.channel_status[0].flow, flow
node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail)
when _T_6 :
connect channel_empty, UInt<1>(0h1)
when io.allocs[0].alloc :
connect channel_empty, UInt<1>(0h0)
connect flow, io.allocs[0].flow | module EgressUnit_14( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_10 = io_in_0_bits_flow_ingress_node_id == 3'h1; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to this FIRRTL code module ScratchpadBank :
output auto : { flip xbar_anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst xbar of TLXbar_i1_o1_a28d64s8k1z3u
connect xbar.clock, childClock
connect xbar.reset, childReset
inst ram of TLRAM_ScratchpadBank
connect ram.clock, childClock
connect ram.reset, childReset
inst fragmenter of TLFragmenter_ScratchpadBank
connect fragmenter.clock, childClock
connect fragmenter.reset, childReset
inst buffer of TLBuffer_a28d64s8k1z3u_1
connect buffer.clock, childClock
connect buffer.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect buffer.auto.in, xbar.auto.anon_out
connect ram.auto.in, fragmenter.auto.anon_out
connect fragmenter.auto.anon_in, buffer.auto.out
connect clockNodeIn, auto.clock_in
connect xbar.auto.anon_in, auto.xbar_anon_in
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module ScratchpadBank( // @[ClockDomain.scala:14:9]
output auto_xbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_xbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_xbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_xbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_xbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_xbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_xbar_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_xbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_xbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_xbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [7:0] xbar_in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [7:0] xbar_in_0_a_bits_source; // @[Xbar.scala:159:18]
wire xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire [7:0] xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [1:0] xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28]
wire [27:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28]
wire _fragmenter_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34]
wire [7:0] _fragmenter_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_auto_anon_in_d_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34]
wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34]
wire [11:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34]
wire [27:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34]
wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34]
wire _ram_auto_in_a_ready; // @[Scratchpad.scala:33:25]
wire _ram_auto_in_d_valid; // @[Scratchpad.scala:33:25]
wire [2:0] _ram_auto_in_d_bits_opcode; // @[Scratchpad.scala:33:25]
wire [1:0] _ram_auto_in_d_bits_size; // @[Scratchpad.scala:33:25]
wire [11:0] _ram_auto_in_d_bits_source; // @[Scratchpad.scala:33:25]
wire [63:0] _ram_auto_in_d_bits_data; // @[Scratchpad.scala:33:25]
wire auto_xbar_anon_in_a_valid_0 = auto_xbar_anon_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_opcode_0 = auto_xbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_param_0 = auto_xbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_size_0 = auto_xbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [7:0] auto_xbar_anon_in_a_bits_source_0 = auto_xbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [27:0] auto_xbar_anon_in_a_bits_address_0 = auto_xbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_xbar_anon_in_a_bits_mask_0 = auto_xbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_xbar_anon_in_a_bits_data_0 = auto_xbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_a_bits_corrupt_0 = auto_xbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_ready_0 = auto_xbar_anon_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire xbar__addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire xbar__addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire xbar__addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire xbar__addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire xbar__addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire xbar__addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire xbar__requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire xbar__requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire xbar__requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire xbar__requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire xbar__requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire xbar__requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10]
wire xbar__requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire xbar__requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire xbar__requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire xbar__requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire xbar__requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire xbar__requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire xbar__beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire xbar__beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire xbar__beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire xbar__beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire xbar__beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire xbar__beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire xbar__beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire xbar__beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire xbar__beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire xbar__beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire xbar__beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire xbar__beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire xbar__beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire xbar_beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire xbar__beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire xbar__beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire xbar__beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire xbar__beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire xbar__beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire xbar__beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire xbar__portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire xbar__portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire xbar__portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire xbar__portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire xbar__portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire xbar__portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire xbar_portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire xbar__portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire xbar__portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire xbar__portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire xbar__portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire xbar__portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire xbar__portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire xbar__portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire xbar_portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire xbar__portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire xbar__portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire xbar__portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire xbar__portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire xbar__portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire xbar__portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire xbar__portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire xbar_portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24]
wire xbar__portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire [1:0] xbar__requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] xbar__requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] xbar__beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] xbar__beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] xbar__portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] xbar__portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] xbar_portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire xbar_beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire [63:0] xbar__addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] xbar__addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] xbar__requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] xbar__requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] xbar__beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] xbar__beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] xbar__beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] xbar__beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] xbar__portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] xbar__portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] xbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [63:0] xbar__portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] xbar__portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] xbar_portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire [27:0] xbar__addressC_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] xbar__addressC_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] xbar__requestCIO_T = 28'h0; // @[Parameters.scala:137:31]
wire [27:0] xbar__requestBOI_WIRE_bits_address = 28'h0; // @[Bundles.scala:264:74]
wire [27:0] xbar__requestBOI_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:264:61]
wire [27:0] xbar__beatsBO_WIRE_bits_address = 28'h0; // @[Bundles.scala:264:74]
wire [27:0] xbar__beatsBO_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:264:61]
wire [27:0] xbar__beatsCI_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] xbar__beatsCI_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] xbar__portsBIO_WIRE_bits_address = 28'h0; // @[Bundles.scala:264:74]
wire [27:0] xbar__portsBIO_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:264:61]
wire [27:0] xbar_portsBIO_filtered_0_bits_address = 28'h0; // @[Xbar.scala:352:24]
wire [27:0] xbar__portsCOI_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] xbar__portsCOI_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] xbar_portsCOI_filtered_0_bits_address = 28'h0; // @[Xbar.scala:352:24]
wire [7:0] xbar__addressC_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] xbar__addressC_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] xbar__requestBOI_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] xbar__requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] xbar__requestBOI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] xbar__requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] xbar__requestBOI_uncommonBits_T = 8'h0; // @[Parameters.scala:52:29]
wire [7:0] xbar_requestBOI_uncommonBits = 8'h0; // @[Parameters.scala:52:56]
wire [7:0] xbar__beatsBO_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] xbar__beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] xbar__beatsBO_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] xbar__beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] xbar__beatsCI_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] xbar__beatsCI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] xbar__portsBIO_WIRE_bits_source = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] xbar__portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] xbar__portsBIO_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] xbar__portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] xbar_portsBIO_filtered_0_bits_source = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] xbar_portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24]
wire [7:0] xbar__portsCOI_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] xbar__portsCOI_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] xbar_portsCOI_filtered_0_bits_source = 8'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar__addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar_beatsBO_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] xbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] xbar__beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar_beatsCI_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] xbar_beatsCI_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] xbar__portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] xbar__portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar__portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] xbar_portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar_portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar__portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] xbar__portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar__portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] xbar_portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar_portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] xbar_portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24]
wire [5:0] xbar__beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] xbar__beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] xbar__beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [5:0] xbar__beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] xbar__beatsBO_decode_T = 13'h3F; // @[package.scala:243:71]
wire [12:0] xbar__beatsCI_decode_T = 13'h3F; // @[package.scala:243:71]
wire xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9]
wire [28:0] xbar__requestAIO_T_2 = 29'h0; // @[Parameters.scala:137:46]
wire [28:0] xbar__requestAIO_T_3 = 29'h0; // @[Parameters.scala:137:46]
wire [28:0] xbar__requestCIO_T_1 = 29'h0; // @[Parameters.scala:137:41]
wire [28:0] xbar__requestCIO_T_2 = 29'h0; // @[Parameters.scala:137:46]
wire [28:0] xbar__requestCIO_T_3 = 29'h0; // @[Parameters.scala:137:46]
wire xbar_auto_anon_in_a_valid = auto_xbar_anon_in_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_a_bits_opcode = auto_xbar_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_a_bits_param = auto_xbar_anon_in_a_bits_param_0; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_a_bits_size = auto_xbar_anon_in_a_bits_size_0; // @[Xbar.scala:74:9]
wire [7:0] xbar_auto_anon_in_a_bits_source = auto_xbar_anon_in_a_bits_source_0; // @[Xbar.scala:74:9]
wire [27:0] xbar_auto_anon_in_a_bits_address = auto_xbar_anon_in_a_bits_address_0; // @[Xbar.scala:74:9]
wire [7:0] xbar_auto_anon_in_a_bits_mask = auto_xbar_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_in_a_bits_data = auto_xbar_anon_in_a_bits_data_0; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_a_bits_corrupt = auto_xbar_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_ready = auto_xbar_anon_in_d_ready_0; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9]
wire [7:0] xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9]
wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_xbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire xbar_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_a_ready_0 = xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9]
wire xbar_anonIn_a_valid = xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_a_bits_opcode = xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_a_bits_param = xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_a_bits_size = xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9]
wire [7:0] xbar_anonIn_a_bits_source = xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9]
wire [27:0] xbar_anonIn_a_bits_address = xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] xbar_anonIn_a_bits_mask = xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] xbar_anonIn_a_bits_data = xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9]
wire xbar_anonIn_a_bits_corrupt = xbar_auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_ready = xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_valid_0 = xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_opcode_0 = xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_param_0 = xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_size_0 = xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9]
wire [7:0] xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_source_0 = xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_sink_0 = xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_denied_0 = xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_data_0 = xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_xbar_anon_in_d_bits_corrupt_0 = xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_anonOut_a_ready = xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire xbar_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [27:0] xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire xbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire xbar_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire xbar_anonOut_d_valid = xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonOut_d_bits_opcode = xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_anonOut_d_bits_param = xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonOut_d_bits_size = xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [7:0] xbar_anonOut_d_bits_source = xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_anonOut_d_bits_sink = xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_anonOut_d_bits_denied = xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_anonOut_d_bits_data = xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_anonOut_d_bits_corrupt = xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9]
wire [7:0] xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9]
wire [27:0] xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_a_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9]
wire xbar_out_0_a_ready = xbar_anonOut_a_ready; // @[Xbar.scala:216:19]
wire xbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_valid = xbar_anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_opcode = xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_param = xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_size = xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [7:0] xbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_source = xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [27:0] xbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_address = xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_mask = xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] xbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_data = xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_corrupt = xbar_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_out_0_d_ready; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_d_ready = xbar_anonOut_d_ready; // @[Xbar.scala:74:9]
wire xbar_out_0_d_valid = xbar_anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] xbar_out_0_d_bits_opcode = xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] xbar_out_0_d_bits_param = xbar_anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [2:0] xbar_out_0_d_bits_size = xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [7:0] xbar_out_0_d_bits_source = xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire xbar__out_0_d_bits_sink_T = xbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire xbar_out_0_d_bits_denied = xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] xbar_out_0_d_bits_data = xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire xbar_out_0_d_bits_corrupt = xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire xbar_in_0_a_ready; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_a_ready = xbar_anonIn_a_ready; // @[Xbar.scala:74:9]
wire xbar_in_0_a_valid = xbar_anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_a_bits_opcode = xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_a_bits_param = xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_a_bits_size = xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [7:0] xbar__in_0_a_bits_source_T = xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [27:0] xbar_in_0_a_bits_address = xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] xbar_in_0_a_bits_mask = xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] xbar_in_0_a_bits_data = xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire xbar_in_0_a_bits_corrupt = xbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire xbar_in_0_d_ready = xbar_anonIn_d_ready; // @[Xbar.scala:159:18]
wire xbar_in_0_d_valid; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_valid = xbar_anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_opcode = xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_param = xbar_anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_size = xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [7:0] xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign xbar_auto_anon_in_d_bits_source = xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_sink = xbar_anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_denied = xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_data = xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_corrupt = xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign xbar_anonIn_a_ready = xbar_in_0_a_ready; // @[Xbar.scala:159:18]
wire xbar__portsAOI_filtered_0_valid_T_1 = xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] xbar_portsAOI_filtered_0_bits_opcode = xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] xbar_portsAOI_filtered_0_bits_param = xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] xbar_portsAOI_filtered_0_bits_size = xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [7:0] xbar_portsAOI_filtered_0_bits_source = xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [27:0] xbar__requestAIO_T = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [27:0] xbar_portsAOI_filtered_0_bits_address = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] xbar_portsAOI_filtered_0_bits_mask = xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] xbar_portsAOI_filtered_0_bits_data = xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsAOI_filtered_0_bits_corrupt = xbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsDIO_filtered_0_ready = xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_valid = xbar_in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_opcode = xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_param = xbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [2:0] xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_size = xbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [7:0] xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
assign xbar__anonIn_d_bits_source_T = xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18]
wire xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_sink = xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_denied = xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_data = xbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
wire xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_corrupt = xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign xbar_in_0_a_bits_source = xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign xbar_anonIn_d_bits_source = xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign xbar_portsAOI_filtered_0_ready = xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24]
wire xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign xbar_anonOut_a_valid = xbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_opcode = xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_param = xbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_size = xbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_source = xbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_address = xbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_mask = xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_data = xbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_corrupt = xbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign xbar_anonOut_d_ready = xbar_out_0_d_ready; // @[Xbar.scala:216:19]
wire xbar__portsDIO_filtered_0_valid_T_1 = xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40]
assign xbar_portsDIO_filtered_0_bits_opcode = xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_param = xbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_size = xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [7:0] xbar__requestDOI_uncommonBits_T = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19]
assign xbar_portsDIO_filtered_0_bits_source = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_sink = xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_denied = xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_data = xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_corrupt = xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_d_bits_sink = xbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
wire [28:0] xbar__requestAIO_T_1 = {1'h0, xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [7:0] xbar_requestDOI_uncommonBits = xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [12:0] xbar__beatsAI_decode_T = 13'h3F << xbar_in_0_a_bits_size; // @[package.scala:243:71]
wire [5:0] xbar__beatsAI_decode_T_1 = xbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] xbar__beatsAI_decode_T_2 = ~xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] xbar_beatsAI_decode = xbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46]
wire xbar__beatsAI_opdata_T = xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire xbar_beatsAI_opdata = ~xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] xbar_beatsAI_0 = xbar_beatsAI_opdata ? xbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [12:0] xbar__beatsDO_decode_T = 13'h3F << xbar_out_0_d_bits_size; // @[package.scala:243:71]
wire [5:0] xbar__beatsDO_decode_T_1 = xbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] xbar__beatsDO_decode_T_2 = ~xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] xbar_beatsDO_decode = xbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46]
wire xbar_beatsDO_opdata = xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] xbar_beatsDO_0 = xbar_beatsDO_opdata ? xbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
assign xbar_in_0_a_ready = xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign xbar_out_0_a_valid = xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_opcode = xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_param = xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_size = xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_source = xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_address = xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_mask = xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_data = xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_corrupt = xbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsAOI_filtered_0_valid = xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign xbar_out_0_d_ready = xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
assign xbar_in_0_d_valid = xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_opcode = xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_param = xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_size = xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_source = xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_sink = xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_denied = xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_data = xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_corrupt = xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign xbar_portsDIO_filtered_0_valid = xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17]
TLRAM_ScratchpadBank ram ( // @[Scratchpad.scala:33:25]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (_ram_auto_in_a_ready),
.auto_in_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34]
.auto_in_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34]
.auto_in_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34]
.auto_in_d_valid (_ram_auto_in_d_valid),
.auto_in_d_bits_opcode (_ram_auto_in_d_bits_opcode),
.auto_in_d_bits_size (_ram_auto_in_d_bits_size),
.auto_in_d_bits_source (_ram_auto_in_d_bits_source),
.auto_in_d_bits_data (_ram_auto_in_d_bits_data)
); // @[Scratchpad.scala:33:25]
TLFragmenter_ScratchpadBank fragmenter ( // @[Fragmenter.scala:345:34]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_a_ready (_fragmenter_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_buffer_auto_out_a_valid), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_opcode (_buffer_auto_out_a_bits_opcode), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_param (_buffer_auto_out_a_bits_param), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_size (_buffer_auto_out_a_bits_size), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_source (_buffer_auto_out_a_bits_source), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_address (_buffer_auto_out_a_bits_address), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_mask (_buffer_auto_out_a_bits_mask), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_data (_buffer_auto_out_a_bits_data), // @[Buffer.scala:75:28]
.auto_anon_in_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), // @[Buffer.scala:75:28]
.auto_anon_in_d_ready (_buffer_auto_out_d_ready), // @[Buffer.scala:75:28]
.auto_anon_in_d_valid (_fragmenter_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_size (_fragmenter_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_fragmenter_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_data (_fragmenter_auto_anon_in_d_bits_data),
.auto_anon_out_a_ready (_ram_auto_in_a_ready), // @[Scratchpad.scala:33:25]
.auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid),
.auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode),
.auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param),
.auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size),
.auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source),
.auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address),
.auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask),
.auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data),
.auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt),
.auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready),
.auto_anon_out_d_valid (_ram_auto_in_d_valid), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_opcode (_ram_auto_in_d_bits_opcode), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_size (_ram_auto_in_d_bits_size), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_source (_ram_auto_in_d_bits_source), // @[Scratchpad.scala:33:25]
.auto_anon_out_d_bits_data (_ram_auto_in_d_bits_data) // @[Scratchpad.scala:33:25]
); // @[Fragmenter.scala:345:34]
TLBuffer_a28d64s8k1z3u_1 buffer ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (xbar_auto_anon_out_a_ready),
.auto_in_a_valid (xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9]
.auto_in_a_bits_opcode (xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9]
.auto_in_a_bits_param (xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9]
.auto_in_a_bits_size (xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9]
.auto_in_a_bits_source (xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9]
.auto_in_a_bits_address (xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9]
.auto_in_a_bits_mask (xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9]
.auto_in_a_bits_data (xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9]
.auto_in_a_bits_corrupt (xbar_auto_anon_out_a_bits_corrupt), // @[Xbar.scala:74:9]
.auto_in_d_ready (xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9]
.auto_in_d_valid (xbar_auto_anon_out_d_valid),
.auto_in_d_bits_opcode (xbar_auto_anon_out_d_bits_opcode),
.auto_in_d_bits_param (xbar_auto_anon_out_d_bits_param),
.auto_in_d_bits_size (xbar_auto_anon_out_d_bits_size),
.auto_in_d_bits_source (xbar_auto_anon_out_d_bits_source),
.auto_in_d_bits_sink (xbar_auto_anon_out_d_bits_sink),
.auto_in_d_bits_denied (xbar_auto_anon_out_d_bits_denied),
.auto_in_d_bits_data (xbar_auto_anon_out_d_bits_data),
.auto_in_d_bits_corrupt (xbar_auto_anon_out_d_bits_corrupt),
.auto_out_a_ready (_fragmenter_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34]
.auto_out_a_valid (_buffer_auto_out_a_valid),
.auto_out_a_bits_opcode (_buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_buffer_auto_out_a_bits_param),
.auto_out_a_bits_size (_buffer_auto_out_a_bits_size),
.auto_out_a_bits_source (_buffer_auto_out_a_bits_source),
.auto_out_a_bits_address (_buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask (_buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data (_buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready (_buffer_auto_out_d_ready),
.auto_out_d_valid (_fragmenter_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34]
.auto_out_d_bits_data (_fragmenter_auto_anon_in_d_bits_data) // @[Fragmenter.scala:345:34]
); // @[Buffer.scala:75:28]
assign auto_xbar_anon_in_a_ready = auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_valid = auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_opcode = auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_param = auto_xbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_size = auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_source = auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_sink = auto_xbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_denied = auto_xbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_data = auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_corrupt = auto_xbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Queue1_RegMapperInput_i9_m8 :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}}}, count : UInt<1>}
cmem ram : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<14>, size : UInt<2>}}} [1]
wire enq_ptr_value : UInt
connect enq_ptr_value, UInt<1>(0h0)
wire deq_ptr_value : UInt
connect deq_ptr_value, UInt<1>(0h0)
regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0)
node ptr_match = eq(enq_ptr_value, deq_ptr_value)
node _empty_T = eq(maybe_full, UInt<1>(0h0))
node empty = and(ptr_match, _empty_T)
node full = and(ptr_match, maybe_full)
node _do_enq_T = and(io.enq.ready, io.enq.valid)
wire do_enq : UInt<1>
connect do_enq, _do_enq_T
node _do_deq_T = and(io.deq.ready, io.deq.valid)
wire do_deq : UInt<1>
connect do_deq, _do_deq_T
when do_enq :
wire _WIRE : UInt
connect _WIRE, UInt<1>(0h0)
infer mport MPORT = ram[_WIRE], clock
connect MPORT.extra, io.enq.bits.extra
connect MPORT.mask, io.enq.bits.mask
connect MPORT.data, io.enq.bits.data
connect MPORT.index, io.enq.bits.index
connect MPORT.read, io.enq.bits.read
when do_deq :
skip
node _T = neq(do_enq, do_deq)
when _T :
connect maybe_full, do_enq
when UInt<1>(0h0) :
connect enq_ptr_value, UInt<1>(0h0)
connect deq_ptr_value, UInt<1>(0h0)
connect maybe_full, UInt<1>(0h0)
node _io_deq_valid_T = eq(empty, UInt<1>(0h0))
connect io.deq.valid, _io_deq_valid_T
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
connect io.enq.ready, _io_enq_ready_T
wire _io_deq_bits_WIRE : UInt
connect _io_deq_bits_WIRE, UInt<1>(0h0)
infer mport io_deq_bits_MPORT = ram[_io_deq_bits_WIRE], clock
connect io.deq.bits, io_deq_bits_MPORT
node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value)
node ptr_diff = tail(_ptr_diff_T, 1)
node _io_count_T = and(maybe_full, ptr_match)
node _io_count_T_1 = mux(_io_count_T, UInt<1>(0h1), UInt<1>(0h0))
node _io_count_T_2 = or(_io_count_T_1, ptr_diff)
connect io.count, _io_count_T_2 | module Queue1_RegMapperInput_i9_m8( // @[RegMapper.scala:71:32]
input clock, // @[RegMapper.scala:71:32]
input reset, // @[RegMapper.scala:71:32]
output io_enq_ready, // @[Decoupled.scala:255:14]
input io_enq_valid, // @[Decoupled.scala:255:14]
input io_enq_bits_read, // @[Decoupled.scala:255:14]
input [8:0] io_enq_bits_index, // @[Decoupled.scala:255:14]
input [63:0] io_enq_bits_data, // @[Decoupled.scala:255:14]
input [7:0] io_enq_bits_mask, // @[Decoupled.scala:255:14]
input [13:0] io_enq_bits_extra_tlrr_extra_source, // @[Decoupled.scala:255:14]
input [1:0] io_enq_bits_extra_tlrr_extra_size, // @[Decoupled.scala:255:14]
input io_deq_ready, // @[Decoupled.scala:255:14]
output io_deq_valid, // @[Decoupled.scala:255:14]
output io_deq_bits_read, // @[Decoupled.scala:255:14]
output [8:0] io_deq_bits_index, // @[Decoupled.scala:255:14]
output [63:0] io_deq_bits_data, // @[Decoupled.scala:255:14]
output [7:0] io_deq_bits_mask, // @[Decoupled.scala:255:14]
output [13:0] io_deq_bits_extra_tlrr_extra_source, // @[Decoupled.scala:255:14]
output [1:0] io_deq_bits_extra_tlrr_extra_size // @[Decoupled.scala:255:14]
);
wire io_enq_valid_0 = io_enq_valid; // @[RegMapper.scala:71:32]
wire io_enq_bits_read_0 = io_enq_bits_read; // @[RegMapper.scala:71:32]
wire [8:0] io_enq_bits_index_0 = io_enq_bits_index; // @[RegMapper.scala:71:32]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[RegMapper.scala:71:32]
wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[RegMapper.scala:71:32]
wire [13:0] io_enq_bits_extra_tlrr_extra_source_0 = io_enq_bits_extra_tlrr_extra_source; // @[RegMapper.scala:71:32]
wire [1:0] io_enq_bits_extra_tlrr_extra_size_0 = io_enq_bits_extra_tlrr_extra_size; // @[RegMapper.scala:71:32]
wire io_deq_ready_0 = io_deq_ready; // @[RegMapper.scala:71:32]
wire ptr_match = 1'h1; // @[Decoupled.scala:260:33]
wire [1:0] _ptr_diff_T = 2'h0; // @[Decoupled.scala:309:32]
wire enq_ptr_value = 1'h0; // @[Counter.scala:61:73]
wire deq_ptr_value = 1'h0; // @[Counter.scala:61:73]
wire _io_enq_ready_T; // @[Decoupled.scala:286:19]
wire _io_deq_bits_WIRE = 1'h0; // @[Decoupled.scala:293:23]
wire ptr_diff = 1'h0; // @[Decoupled.scala:309:32]
wire _io_deq_valid_T; // @[Decoupled.scala:285:19]
wire _io_count_T_2; // @[Decoupled.scala:312:62]
wire io_enq_ready_0; // @[RegMapper.scala:71:32]
wire [13:0] io_deq_bits_extra_tlrr_extra_source_0; // @[RegMapper.scala:71:32]
wire [1:0] io_deq_bits_extra_tlrr_extra_size_0; // @[RegMapper.scala:71:32]
wire io_deq_bits_read_0; // @[RegMapper.scala:71:32]
wire [8:0] io_deq_bits_index_0; // @[RegMapper.scala:71:32]
wire [63:0] io_deq_bits_data_0; // @[RegMapper.scala:71:32]
wire [7:0] io_deq_bits_mask_0; // @[RegMapper.scala:71:32]
wire io_deq_valid_0; // @[RegMapper.scala:71:32]
wire io_count; // @[RegMapper.scala:71:32]
reg [97:0] ram; // @[Decoupled.scala:256:91]
assign io_deq_bits_read_0 = ram[0]; // @[Decoupled.scala:256:91]
assign io_deq_bits_index_0 = ram[9:1]; // @[Decoupled.scala:256:91]
assign io_deq_bits_data_0 = ram[73:10]; // @[Decoupled.scala:256:91]
assign io_deq_bits_mask_0 = ram[81:74]; // @[Decoupled.scala:256:91]
assign io_deq_bits_extra_tlrr_extra_source_0 = ram[95:82]; // @[Decoupled.scala:256:91]
assign io_deq_bits_extra_tlrr_extra_size_0 = ram[97:96]; // @[Decoupled.scala:256:91]
reg maybe_full; // @[Decoupled.scala:259:27]
wire full = maybe_full; // @[Decoupled.scala:259:27, :262:24]
wire _io_count_T = maybe_full; // @[Decoupled.scala:259:27, :312:32]
wire _empty_T = ~maybe_full; // @[Decoupled.scala:259:27, :261:28]
wire empty = _empty_T; // @[Decoupled.scala:261:{25,28}]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35, :263:27]
wire _do_deq_T = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35]
wire do_deq = _do_deq_T; // @[Decoupled.scala:51:35, :264:27]
assign _io_deq_valid_T = ~empty; // @[Decoupled.scala:261:25, :285:19]
assign io_deq_valid_0 = _io_deq_valid_T; // @[Decoupled.scala:285:19]
assign _io_enq_ready_T = ~full; // @[Decoupled.scala:262:24, :286:19]
assign io_enq_ready_0 = _io_enq_ready_T; // @[Decoupled.scala:286:19]
wire _io_count_T_1 = _io_count_T; // @[Decoupled.scala:312:{20,32}]
assign _io_count_T_2 = _io_count_T_1; // @[Decoupled.scala:312:{20,62}]
assign io_count = _io_count_T_2; // @[Decoupled.scala:312:62]
always @(posedge clock) begin // @[RegMapper.scala:71:32]
if (do_enq) // @[Decoupled.scala:263:27]
ram <= {io_enq_bits_extra_tlrr_extra_size_0, io_enq_bits_extra_tlrr_extra_source_0, io_enq_bits_mask_0, io_enq_bits_data_0, io_enq_bits_index_0, io_enq_bits_read_0}; // @[Decoupled.scala:256:91]
if (reset) // @[RegMapper.scala:71:32]
maybe_full <= 1'h0; // @[Decoupled.scala:259:27]
else if (~(do_enq == do_deq)) // @[Decoupled.scala:259:27, :263:27, :264:27, :276:{15,27}, :277:16]
maybe_full <= do_enq; // @[Decoupled.scala:259:27, :263:27]
always @(posedge)
assign io_enq_ready = io_enq_ready_0; // @[RegMapper.scala:71:32]
assign io_deq_valid = io_deq_valid_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_read = io_deq_bits_read_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_index = io_deq_bits_index_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_data = io_deq_bits_data_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_mask = io_deq_bits_mask_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_extra_tlrr_extra_source = io_deq_bits_extra_tlrr_extra_source_0; // @[RegMapper.scala:71:32]
assign io_deq_bits_extra_tlrr_extra_size = io_deq_bits_extra_tlrr_extra_size_0; // @[RegMapper.scala:71:32]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_356 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_100
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_356( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_100 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MiniDCache_4 :
input clock : Clock
input reset : Reset
output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
output io : { flip cpu : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[0], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}}, errors : { bus : { valid : UInt<1>, bits : UInt<32>}}, tlb_port : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, s1_resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip s2_kill : UInt<1>}}
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
reg clock_en_reg : UInt<1>, clock
connect io.cpu.clock_enabled, clock_en_reg
inst tlb of DTLB_10
connect tlb.clock, clock
connect tlb.reset, reset
inst pma_checker of DTLB_11
connect pma_checker.clock, clock
connect pma_checker.reset, reset
wire replace : UInt<1>
connect replace, UInt<1>(0h0)
inst lfsr_prng of MaxPeriodFibonacciLFSR_7
connect lfsr_prng.clock, clock
connect lfsr_prng.reset, reset
connect lfsr_prng.io.seed.valid, UInt<1>(0h0)
invalidate lfsr_prng.io.seed.bits[0]
invalidate lfsr_prng.io.seed.bits[1]
invalidate lfsr_prng.io.seed.bits[2]
invalidate lfsr_prng.io.seed.bits[3]
invalidate lfsr_prng.io.seed.bits[4]
invalidate lfsr_prng.io.seed.bits[5]
invalidate lfsr_prng.io.seed.bits[6]
invalidate lfsr_prng.io.seed.bits[7]
invalidate lfsr_prng.io.seed.bits[8]
invalidate lfsr_prng.io.seed.bits[9]
invalidate lfsr_prng.io.seed.bits[10]
invalidate lfsr_prng.io.seed.bits[11]
invalidate lfsr_prng.io.seed.bits[12]
invalidate lfsr_prng.io.seed.bits[13]
invalidate lfsr_prng.io.seed.bits[14]
invalidate lfsr_prng.io.seed.bits[15]
connect lfsr_prng.io.increment, replace
node lfsr_lo_lo_lo = cat(lfsr_prng.io.out[1], lfsr_prng.io.out[0])
node lfsr_lo_lo_hi = cat(lfsr_prng.io.out[3], lfsr_prng.io.out[2])
node lfsr_lo_lo = cat(lfsr_lo_lo_hi, lfsr_lo_lo_lo)
node lfsr_lo_hi_lo = cat(lfsr_prng.io.out[5], lfsr_prng.io.out[4])
node lfsr_lo_hi_hi = cat(lfsr_prng.io.out[7], lfsr_prng.io.out[6])
node lfsr_lo_hi = cat(lfsr_lo_hi_hi, lfsr_lo_hi_lo)
node lfsr_lo = cat(lfsr_lo_hi, lfsr_lo_lo)
node lfsr_hi_lo_lo = cat(lfsr_prng.io.out[9], lfsr_prng.io.out[8])
node lfsr_hi_lo_hi = cat(lfsr_prng.io.out[11], lfsr_prng.io.out[10])
node lfsr_hi_lo = cat(lfsr_hi_lo_hi, lfsr_hi_lo_lo)
node lfsr_hi_hi_lo = cat(lfsr_prng.io.out[13], lfsr_prng.io.out[12])
node lfsr_hi_hi_hi = cat(lfsr_prng.io.out[15], lfsr_prng.io.out[14])
node lfsr_hi_hi = cat(lfsr_hi_hi_hi, lfsr_hi_hi_lo)
node lfsr_hi = cat(lfsr_hi_hi, lfsr_hi_lo)
node lfsr = cat(lfsr_hi, lfsr_lo)
inst metaArb of Arbiter8_DCacheMetadataReq_5
connect metaArb.clock, clock
connect metaArb.reset, reset
smem rerocc_tile_dcache_tag_array : UInt<26>[4] [4]
inst data of DCacheDataArray_5
connect data.clock, clock
connect data.reset, reset
inst dataArb of Arbiter4_DCacheDataReq_5
connect dataArb.clock, clock
connect dataArb.reset, reset
connect dataArb.io.in[1].bits.wdata, dataArb.io.in[0].bits.wdata
connect dataArb.io.in[2].bits.wdata, dataArb.io.in[0].bits.wdata
connect dataArb.io.in[3].bits.wdata, dataArb.io.in[0].bits.wdata
connect data.io.req.bits, dataArb.io.out.bits
connect data.io.req.valid, dataArb.io.out.valid
connect dataArb.io.out.ready, UInt<1>(0h1)
connect metaArb.io.out.ready, clock_en_reg
wire tl_out_a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
wire nodeOut_a_deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect nodeOut_a_deq.valid, tl_out_a.valid
connect nodeOut_a_deq.bits, tl_out_a.bits
connect tl_out_a.ready, nodeOut_a_deq.ready
connect nodeOut.a, nodeOut_a_deq
node _s1_valid_T = and(io.cpu.req.ready, io.cpu.req.valid)
regreset s1_valid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s1_valid, _s1_valid_T
node _s1_probe_T = and(nodeOut.b.ready, nodeOut.b.valid)
regreset s1_probe : UInt<1>, clock, reset, UInt<1>(0h0)
connect s1_probe, _s1_probe_T
node _probe_bits_T = and(nodeOut.b.ready, nodeOut.b.valid)
reg probe_bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock
when _probe_bits_T :
connect probe_bits, nodeOut.b.bits
wire s1_nack : UInt<1>
connect s1_nack, UInt<1>(0h0)
node _s1_valid_masked_T = eq(io.cpu.s1_kill, UInt<1>(0h0))
node s1_valid_masked = and(s1_valid, _s1_valid_masked_T)
node _s1_valid_not_nacked_T = eq(s1_nack, UInt<1>(0h0))
node s1_valid_not_nacked = and(s1_valid, _s1_valid_not_nacked_T)
node _s1_tlb_req_valid_T = and(io.tlb_port.req.ready, io.tlb_port.req.valid)
regreset s1_tlb_req_valid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s1_tlb_req_valid, _s1_tlb_req_valid_T
regreset s2_tlb_req_valid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s2_tlb_req_valid, s1_tlb_req_valid
node _s0_clk_en_T = eq(metaArb.io.out.bits.write, UInt<1>(0h0))
node s0_clk_en = and(metaArb.io.out.valid, _s0_clk_en_T)
wire s0_req : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}
connect s0_req, io.cpu.req.bits
node _s0_req_addr_T = shr(metaArb.io.out.bits.addr, 6)
node _s0_req_addr_T_1 = bits(io.cpu.req.bits.addr, 5, 0)
node _s0_req_addr_T_2 = cat(_s0_req_addr_T, _s0_req_addr_T_1)
connect s0_req.addr, _s0_req_addr_T_2
node _T = eq(metaArb.io.in[7].ready, UInt<1>(0h0))
when _T :
connect s0_req.phys, UInt<1>(0h1)
reg s1_req : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock
when s0_clk_en :
connect s1_req, s0_req
node _s1_vaddr_T = shr(s1_req.addr, 8)
node _s1_vaddr_T_1 = bits(s1_req.addr, 7, 0)
node s1_vaddr = cat(_s1_vaddr_T, _s1_vaddr_T_1)
wire s0_tlb_req : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}
connect s0_tlb_req, io.tlb_port.req.bits
node _T_1 = and(io.tlb_port.req.ready, io.tlb_port.req.valid)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
connect s0_tlb_req.passthrough, s0_req.phys
connect s0_tlb_req.vaddr, s0_req.addr
connect s0_tlb_req.size, s0_req.size
connect s0_tlb_req.cmd, s0_req.cmd
connect s0_tlb_req.prv, s0_req.dprv
connect s0_tlb_req.v, s0_req.dv
node _s1_tlb_req_T = or(s0_clk_en, io.tlb_port.req.valid)
reg s1_tlb_req : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}, clock
when _s1_tlb_req_T :
connect s1_tlb_req, s0_tlb_req
node _s1_read_T = eq(s1_req.cmd, UInt<1>(0h0))
node _s1_read_T_1 = eq(s1_req.cmd, UInt<5>(0h10))
node _s1_read_T_2 = eq(s1_req.cmd, UInt<3>(0h6))
node _s1_read_T_3 = eq(s1_req.cmd, UInt<3>(0h7))
node _s1_read_T_4 = or(_s1_read_T, _s1_read_T_1)
node _s1_read_T_5 = or(_s1_read_T_4, _s1_read_T_2)
node _s1_read_T_6 = or(_s1_read_T_5, _s1_read_T_3)
node _s1_read_T_7 = eq(s1_req.cmd, UInt<3>(0h4))
node _s1_read_T_8 = eq(s1_req.cmd, UInt<4>(0h9))
node _s1_read_T_9 = eq(s1_req.cmd, UInt<4>(0ha))
node _s1_read_T_10 = eq(s1_req.cmd, UInt<4>(0hb))
node _s1_read_T_11 = or(_s1_read_T_7, _s1_read_T_8)
node _s1_read_T_12 = or(_s1_read_T_11, _s1_read_T_9)
node _s1_read_T_13 = or(_s1_read_T_12, _s1_read_T_10)
node _s1_read_T_14 = eq(s1_req.cmd, UInt<4>(0h8))
node _s1_read_T_15 = eq(s1_req.cmd, UInt<4>(0hc))
node _s1_read_T_16 = eq(s1_req.cmd, UInt<4>(0hd))
node _s1_read_T_17 = eq(s1_req.cmd, UInt<4>(0he))
node _s1_read_T_18 = eq(s1_req.cmd, UInt<4>(0hf))
node _s1_read_T_19 = or(_s1_read_T_14, _s1_read_T_15)
node _s1_read_T_20 = or(_s1_read_T_19, _s1_read_T_16)
node _s1_read_T_21 = or(_s1_read_T_20, _s1_read_T_17)
node _s1_read_T_22 = or(_s1_read_T_21, _s1_read_T_18)
node _s1_read_T_23 = or(_s1_read_T_13, _s1_read_T_22)
node s1_read = or(_s1_read_T_6, _s1_read_T_23)
node _s1_write_T = eq(s1_req.cmd, UInt<1>(0h1))
node _s1_write_T_1 = eq(s1_req.cmd, UInt<5>(0h11))
node _s1_write_T_2 = or(_s1_write_T, _s1_write_T_1)
node _s1_write_T_3 = eq(s1_req.cmd, UInt<3>(0h7))
node _s1_write_T_4 = or(_s1_write_T_2, _s1_write_T_3)
node _s1_write_T_5 = eq(s1_req.cmd, UInt<3>(0h4))
node _s1_write_T_6 = eq(s1_req.cmd, UInt<4>(0h9))
node _s1_write_T_7 = eq(s1_req.cmd, UInt<4>(0ha))
node _s1_write_T_8 = eq(s1_req.cmd, UInt<4>(0hb))
node _s1_write_T_9 = or(_s1_write_T_5, _s1_write_T_6)
node _s1_write_T_10 = or(_s1_write_T_9, _s1_write_T_7)
node _s1_write_T_11 = or(_s1_write_T_10, _s1_write_T_8)
node _s1_write_T_12 = eq(s1_req.cmd, UInt<4>(0h8))
node _s1_write_T_13 = eq(s1_req.cmd, UInt<4>(0hc))
node _s1_write_T_14 = eq(s1_req.cmd, UInt<4>(0hd))
node _s1_write_T_15 = eq(s1_req.cmd, UInt<4>(0he))
node _s1_write_T_16 = eq(s1_req.cmd, UInt<4>(0hf))
node _s1_write_T_17 = or(_s1_write_T_12, _s1_write_T_13)
node _s1_write_T_18 = or(_s1_write_T_17, _s1_write_T_14)
node _s1_write_T_19 = or(_s1_write_T_18, _s1_write_T_15)
node _s1_write_T_20 = or(_s1_write_T_19, _s1_write_T_16)
node _s1_write_T_21 = or(_s1_write_T_11, _s1_write_T_20)
node s1_write = or(_s1_write_T_4, _s1_write_T_21)
node s1_readwrite = or(s1_read, s1_write)
node _s1_sfence_T = eq(s1_req.cmd, UInt<5>(0h14))
node _s1_sfence_T_1 = eq(s1_req.cmd, UInt<5>(0h15))
node _s1_sfence_T_2 = or(_s1_sfence_T, _s1_sfence_T_1)
node _s1_sfence_T_3 = eq(s1_req.cmd, UInt<5>(0h16))
node s1_sfence = or(_s1_sfence_T_2, _s1_sfence_T_3)
node _s1_flush_line_T = eq(s1_req.cmd, UInt<3>(0h5))
node _s1_flush_line_T_1 = bits(s1_req.size, 0, 0)
node s1_flush_line = and(_s1_flush_line_T, _s1_flush_line_T_1)
reg s1_flush_valid : UInt<1>, clock
wire s1_waw_hazard : UInt<1>
regreset flushed : UInt<1>, clock, reset, UInt<1>(0h1)
regreset flushing : UInt<1>, clock, reset, UInt<1>(0h0)
reg flushing_req : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock
regreset cached_grant_wait : UInt<1>, clock, reset, UInt<1>(0h0)
regreset resetting : UInt<1>, clock, reset, UInt<1>(0h0)
regreset flushCounter : UInt<4>, clock, reset, UInt<4>(0hc)
regreset release_ack_wait : UInt<1>, clock, reset, UInt<1>(0h0)
reg release_ack_addr : UInt<32>, clock
regreset release_state : UInt<4>, clock, reset, UInt<4>(0h0)
reg refill_way : UInt, clock
wire any_pstore_valid : UInt<1>
node _inWriteback_T = eq(release_state, UInt<4>(0h1))
node _inWriteback_T_1 = eq(release_state, UInt<4>(0h2))
node inWriteback = or(_inWriteback_T, _inWriteback_T_1)
wire releaseWay : UInt
node _io_cpu_req_ready_T = eq(release_state, UInt<4>(0h0))
node _io_cpu_req_ready_T_1 = eq(cached_grant_wait, UInt<1>(0h0))
node _io_cpu_req_ready_T_2 = and(_io_cpu_req_ready_T, _io_cpu_req_ready_T_1)
node _io_cpu_req_ready_T_3 = eq(s1_nack, UInt<1>(0h0))
node _io_cpu_req_ready_T_4 = and(_io_cpu_req_ready_T_2, _io_cpu_req_ready_T_3)
connect io.cpu.req.ready, _io_cpu_req_ready_T_4
wire _uncachedInFlight_WIRE : UInt<1>[1]
connect _uncachedInFlight_WIRE[0], UInt<1>(0h0)
regreset uncachedInFlight : UInt<1>[1], clock, reset, _uncachedInFlight_WIRE
reg uncachedReqs : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}[1], clock
wire uncachedResp : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}
invalidate uncachedResp.mask
invalidate uncachedResp.data
invalidate uncachedResp.no_xcpt
invalidate uncachedResp.no_alloc
invalidate uncachedResp.no_resp
invalidate uncachedResp.phys
invalidate uncachedResp.dv
invalidate uncachedResp.dprv
invalidate uncachedResp.signed
invalidate uncachedResp.size
invalidate uncachedResp.cmd
invalidate uncachedResp.tag
invalidate uncachedResp.addr
node _s0_read_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h0))
node _s0_read_T_1 = eq(io.cpu.req.bits.cmd, UInt<5>(0h10))
node _s0_read_T_2 = eq(io.cpu.req.bits.cmd, UInt<3>(0h6))
node _s0_read_T_3 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _s0_read_T_4 = or(_s0_read_T, _s0_read_T_1)
node _s0_read_T_5 = or(_s0_read_T_4, _s0_read_T_2)
node _s0_read_T_6 = or(_s0_read_T_5, _s0_read_T_3)
node _s0_read_T_7 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _s0_read_T_8 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _s0_read_T_9 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _s0_read_T_10 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _s0_read_T_11 = or(_s0_read_T_7, _s0_read_T_8)
node _s0_read_T_12 = or(_s0_read_T_11, _s0_read_T_9)
node _s0_read_T_13 = or(_s0_read_T_12, _s0_read_T_10)
node _s0_read_T_14 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _s0_read_T_15 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _s0_read_T_16 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _s0_read_T_17 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _s0_read_T_18 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _s0_read_T_19 = or(_s0_read_T_14, _s0_read_T_15)
node _s0_read_T_20 = or(_s0_read_T_19, _s0_read_T_16)
node _s0_read_T_21 = or(_s0_read_T_20, _s0_read_T_17)
node _s0_read_T_22 = or(_s0_read_T_21, _s0_read_T_18)
node _s0_read_T_23 = or(_s0_read_T_13, _s0_read_T_22)
node s0_read = or(_s0_read_T_6, _s0_read_T_23)
node _dataArb_io_in_3_valid_res_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h1))
node _dataArb_io_in_3_valid_res_T_1 = eq(io.cpu.req.bits.cmd, UInt<2>(0h3))
node _dataArb_io_in_3_valid_res_T_2 = or(_dataArb_io_in_3_valid_res_T, _dataArb_io_in_3_valid_res_T_1)
node _dataArb_io_in_3_valid_res_T_3 = eq(_dataArb_io_in_3_valid_res_T_2, UInt<1>(0h0))
node _dataArb_io_in_3_valid_res_T_4 = lt(io.cpu.req.bits.size, UInt<1>(0h0))
node dataArb_io_in_3_valid_res = or(_dataArb_io_in_3_valid_res_T_3, _dataArb_io_in_3_valid_res_T_4)
node _dataArb_io_in_3_valid_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h0))
node _dataArb_io_in_3_valid_T_1 = eq(io.cpu.req.bits.cmd, UInt<5>(0h10))
node _dataArb_io_in_3_valid_T_2 = eq(io.cpu.req.bits.cmd, UInt<3>(0h6))
node _dataArb_io_in_3_valid_T_3 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _dataArb_io_in_3_valid_T_4 = or(_dataArb_io_in_3_valid_T, _dataArb_io_in_3_valid_T_1)
node _dataArb_io_in_3_valid_T_5 = or(_dataArb_io_in_3_valid_T_4, _dataArb_io_in_3_valid_T_2)
node _dataArb_io_in_3_valid_T_6 = or(_dataArb_io_in_3_valid_T_5, _dataArb_io_in_3_valid_T_3)
node _dataArb_io_in_3_valid_T_7 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _dataArb_io_in_3_valid_T_8 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _dataArb_io_in_3_valid_T_9 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _dataArb_io_in_3_valid_T_10 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _dataArb_io_in_3_valid_T_11 = or(_dataArb_io_in_3_valid_T_7, _dataArb_io_in_3_valid_T_8)
node _dataArb_io_in_3_valid_T_12 = or(_dataArb_io_in_3_valid_T_11, _dataArb_io_in_3_valid_T_9)
node _dataArb_io_in_3_valid_T_13 = or(_dataArb_io_in_3_valid_T_12, _dataArb_io_in_3_valid_T_10)
node _dataArb_io_in_3_valid_T_14 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _dataArb_io_in_3_valid_T_15 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _dataArb_io_in_3_valid_T_16 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _dataArb_io_in_3_valid_T_17 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _dataArb_io_in_3_valid_T_18 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _dataArb_io_in_3_valid_T_19 = or(_dataArb_io_in_3_valid_T_14, _dataArb_io_in_3_valid_T_15)
node _dataArb_io_in_3_valid_T_20 = or(_dataArb_io_in_3_valid_T_19, _dataArb_io_in_3_valid_T_16)
node _dataArb_io_in_3_valid_T_21 = or(_dataArb_io_in_3_valid_T_20, _dataArb_io_in_3_valid_T_17)
node _dataArb_io_in_3_valid_T_22 = or(_dataArb_io_in_3_valid_T_21, _dataArb_io_in_3_valid_T_18)
node _dataArb_io_in_3_valid_T_23 = or(_dataArb_io_in_3_valid_T_13, _dataArb_io_in_3_valid_T_22)
node _dataArb_io_in_3_valid_T_24 = or(_dataArb_io_in_3_valid_T_6, _dataArb_io_in_3_valid_T_23)
node _dataArb_io_in_3_valid_T_25 = eq(io.cpu.req.bits.cmd, UInt<1>(0h1))
node _dataArb_io_in_3_valid_T_26 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _dataArb_io_in_3_valid_T_27 = or(_dataArb_io_in_3_valid_T_25, _dataArb_io_in_3_valid_T_26)
node _dataArb_io_in_3_valid_T_28 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _dataArb_io_in_3_valid_T_29 = or(_dataArb_io_in_3_valid_T_27, _dataArb_io_in_3_valid_T_28)
node _dataArb_io_in_3_valid_T_30 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _dataArb_io_in_3_valid_T_31 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _dataArb_io_in_3_valid_T_32 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _dataArb_io_in_3_valid_T_33 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _dataArb_io_in_3_valid_T_34 = or(_dataArb_io_in_3_valid_T_30, _dataArb_io_in_3_valid_T_31)
node _dataArb_io_in_3_valid_T_35 = or(_dataArb_io_in_3_valid_T_34, _dataArb_io_in_3_valid_T_32)
node _dataArb_io_in_3_valid_T_36 = or(_dataArb_io_in_3_valid_T_35, _dataArb_io_in_3_valid_T_33)
node _dataArb_io_in_3_valid_T_37 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _dataArb_io_in_3_valid_T_38 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _dataArb_io_in_3_valid_T_39 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _dataArb_io_in_3_valid_T_40 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _dataArb_io_in_3_valid_T_41 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _dataArb_io_in_3_valid_T_42 = or(_dataArb_io_in_3_valid_T_37, _dataArb_io_in_3_valid_T_38)
node _dataArb_io_in_3_valid_T_43 = or(_dataArb_io_in_3_valid_T_42, _dataArb_io_in_3_valid_T_39)
node _dataArb_io_in_3_valid_T_44 = or(_dataArb_io_in_3_valid_T_43, _dataArb_io_in_3_valid_T_40)
node _dataArb_io_in_3_valid_T_45 = or(_dataArb_io_in_3_valid_T_44, _dataArb_io_in_3_valid_T_41)
node _dataArb_io_in_3_valid_T_46 = or(_dataArb_io_in_3_valid_T_36, _dataArb_io_in_3_valid_T_45)
node _dataArb_io_in_3_valid_T_47 = or(_dataArb_io_in_3_valid_T_29, _dataArb_io_in_3_valid_T_46)
node _dataArb_io_in_3_valid_T_48 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _dataArb_io_in_3_valid_T_49 = lt(io.cpu.req.bits.size, UInt<1>(0h0))
node _dataArb_io_in_3_valid_T_50 = or(_dataArb_io_in_3_valid_T_48, _dataArb_io_in_3_valid_T_49)
node _dataArb_io_in_3_valid_T_51 = and(_dataArb_io_in_3_valid_T_47, _dataArb_io_in_3_valid_T_50)
node _dataArb_io_in_3_valid_T_52 = or(_dataArb_io_in_3_valid_T_24, _dataArb_io_in_3_valid_T_51)
node _dataArb_io_in_3_valid_T_53 = eq(_dataArb_io_in_3_valid_T_52, UInt<1>(0h0))
node _dataArb_io_in_3_valid_T_54 = or(_dataArb_io_in_3_valid_T_53, dataArb_io_in_3_valid_res)
node _dataArb_io_in_3_valid_T_55 = asUInt(reset)
node _dataArb_io_in_3_valid_T_56 = eq(_dataArb_io_in_3_valid_T_55, UInt<1>(0h0))
when _dataArb_io_in_3_valid_T_56 :
node _dataArb_io_in_3_valid_T_57 = eq(_dataArb_io_in_3_valid_T_54, UInt<1>(0h0))
when _dataArb_io_in_3_valid_T_57 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:1186 assert(!needsRead(req) || res)\n") : dataArb_io_in_3_valid_printf
assert(clock, _dataArb_io_in_3_valid_T_54, UInt<1>(0h1), "") : dataArb_io_in_3_valid_assert
node _dataArb_io_in_3_valid_T_58 = and(io.cpu.req.valid, dataArb_io_in_3_valid_res)
connect dataArb.io.in[3].valid, _dataArb_io_in_3_valid_T_58
connect dataArb.io.in[3].bits.way_en, dataArb.io.in[1].bits.way_en
connect dataArb.io.in[3].bits.eccMask, dataArb.io.in[1].bits.eccMask
connect dataArb.io.in[3].bits.wordMask, dataArb.io.in[1].bits.wordMask
connect dataArb.io.in[3].bits.wdata, dataArb.io.in[1].bits.wdata
connect dataArb.io.in[3].bits.write, dataArb.io.in[1].bits.write
connect dataArb.io.in[3].bits.addr, dataArb.io.in[1].bits.addr
connect dataArb.io.in[3].bits.write, UInt<1>(0h0)
node _dataArb_io_in_3_bits_addr_T = shr(io.cpu.req.bits.addr, 8)
node _dataArb_io_in_3_bits_addr_T_1 = bits(io.cpu.req.bits.addr, 7, 0)
node _dataArb_io_in_3_bits_addr_T_2 = cat(_dataArb_io_in_3_bits_addr_T, _dataArb_io_in_3_bits_addr_T_1)
connect dataArb.io.in[3].bits.addr, _dataArb_io_in_3_bits_addr_T_2
node _dataArb_io_in_3_bits_wordMask_T = mux(UInt<1>(0h1), UInt<8>(0hff), UInt<8>(0h0))
connect dataArb.io.in[3].bits.wordMask, _dataArb_io_in_3_bits_wordMask_T
node _dataArb_io_in_3_bits_eccMask_T = not(UInt<8>(0h0))
connect dataArb.io.in[3].bits.eccMask, _dataArb_io_in_3_bits_eccMask_T
node _dataArb_io_in_3_bits_way_en_T = not(UInt<4>(0h0))
connect dataArb.io.in[3].bits.way_en, _dataArb_io_in_3_bits_way_en_T
node _T_3 = eq(dataArb.io.in[3].ready, UInt<1>(0h0))
node _T_4 = and(_T_3, s0_read)
when _T_4 :
connect io.cpu.req.ready, UInt<1>(0h0)
node _s1_did_read_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h0))
node _s1_did_read_T_1 = eq(io.cpu.req.bits.cmd, UInt<5>(0h10))
node _s1_did_read_T_2 = eq(io.cpu.req.bits.cmd, UInt<3>(0h6))
node _s1_did_read_T_3 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _s1_did_read_T_4 = or(_s1_did_read_T, _s1_did_read_T_1)
node _s1_did_read_T_5 = or(_s1_did_read_T_4, _s1_did_read_T_2)
node _s1_did_read_T_6 = or(_s1_did_read_T_5, _s1_did_read_T_3)
node _s1_did_read_T_7 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _s1_did_read_T_8 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _s1_did_read_T_9 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _s1_did_read_T_10 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _s1_did_read_T_11 = or(_s1_did_read_T_7, _s1_did_read_T_8)
node _s1_did_read_T_12 = or(_s1_did_read_T_11, _s1_did_read_T_9)
node _s1_did_read_T_13 = or(_s1_did_read_T_12, _s1_did_read_T_10)
node _s1_did_read_T_14 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _s1_did_read_T_15 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _s1_did_read_T_16 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _s1_did_read_T_17 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _s1_did_read_T_18 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _s1_did_read_T_19 = or(_s1_did_read_T_14, _s1_did_read_T_15)
node _s1_did_read_T_20 = or(_s1_did_read_T_19, _s1_did_read_T_16)
node _s1_did_read_T_21 = or(_s1_did_read_T_20, _s1_did_read_T_17)
node _s1_did_read_T_22 = or(_s1_did_read_T_21, _s1_did_read_T_18)
node _s1_did_read_T_23 = or(_s1_did_read_T_13, _s1_did_read_T_22)
node _s1_did_read_T_24 = or(_s1_did_read_T_6, _s1_did_read_T_23)
node _s1_did_read_T_25 = eq(io.cpu.req.bits.cmd, UInt<1>(0h1))
node _s1_did_read_T_26 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _s1_did_read_T_27 = or(_s1_did_read_T_25, _s1_did_read_T_26)
node _s1_did_read_T_28 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _s1_did_read_T_29 = or(_s1_did_read_T_27, _s1_did_read_T_28)
node _s1_did_read_T_30 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _s1_did_read_T_31 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _s1_did_read_T_32 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _s1_did_read_T_33 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _s1_did_read_T_34 = or(_s1_did_read_T_30, _s1_did_read_T_31)
node _s1_did_read_T_35 = or(_s1_did_read_T_34, _s1_did_read_T_32)
node _s1_did_read_T_36 = or(_s1_did_read_T_35, _s1_did_read_T_33)
node _s1_did_read_T_37 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _s1_did_read_T_38 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _s1_did_read_T_39 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _s1_did_read_T_40 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _s1_did_read_T_41 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _s1_did_read_T_42 = or(_s1_did_read_T_37, _s1_did_read_T_38)
node _s1_did_read_T_43 = or(_s1_did_read_T_42, _s1_did_read_T_39)
node _s1_did_read_T_44 = or(_s1_did_read_T_43, _s1_did_read_T_40)
node _s1_did_read_T_45 = or(_s1_did_read_T_44, _s1_did_read_T_41)
node _s1_did_read_T_46 = or(_s1_did_read_T_36, _s1_did_read_T_45)
node _s1_did_read_T_47 = or(_s1_did_read_T_29, _s1_did_read_T_46)
node _s1_did_read_T_48 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _s1_did_read_T_49 = lt(io.cpu.req.bits.size, UInt<1>(0h0))
node _s1_did_read_T_50 = or(_s1_did_read_T_48, _s1_did_read_T_49)
node _s1_did_read_T_51 = and(_s1_did_read_T_47, _s1_did_read_T_50)
node _s1_did_read_T_52 = or(_s1_did_read_T_24, _s1_did_read_T_51)
node _s1_did_read_T_53 = and(io.cpu.req.valid, _s1_did_read_T_52)
node _s1_did_read_T_54 = and(dataArb.io.in[3].ready, _s1_did_read_T_53)
reg s1_did_read : UInt<1>, clock
when s0_clk_en :
connect s1_did_read, _s1_did_read_T_54
reg s1_read_mask : UInt<1>, clock
when s0_clk_en :
connect s1_read_mask, dataArb.io.in[3].bits.wordMask
connect metaArb.io.in[7].valid, io.cpu.req.valid
connect metaArb.io.in[7].bits.write, UInt<1>(0h0)
node _metaArb_io_in_7_bits_idx_T = bits(dataArb.io.in[3].bits.addr, 7, 6)
connect metaArb.io.in[7].bits.idx, _metaArb_io_in_7_bits_idx_T
connect metaArb.io.in[7].bits.addr, io.cpu.req.bits.addr
connect metaArb.io.in[7].bits.way_en, metaArb.io.in[4].bits.way_en
connect metaArb.io.in[7].bits.data, metaArb.io.in[4].bits.data
node _T_5 = eq(metaArb.io.in[7].ready, UInt<1>(0h0))
when _T_5 :
connect io.cpu.req.ready, UInt<1>(0h0)
node _s1_cmd_uses_tlb_T = or(s1_readwrite, s1_flush_line)
node _s1_cmd_uses_tlb_T_1 = eq(s1_req.cmd, UInt<5>(0h17))
node s1_cmd_uses_tlb = or(_s1_cmd_uses_tlb_T, _s1_cmd_uses_tlb_T_1)
connect tlb.io.ptw.customCSRs, io.ptw.customCSRs
connect tlb.io.ptw.gstatus, io.ptw.gstatus
connect tlb.io.ptw.hstatus, io.ptw.hstatus
connect tlb.io.ptw.status, io.ptw.status
connect tlb.io.ptw.vsatp, io.ptw.vsatp
connect tlb.io.ptw.hgatp, io.ptw.hgatp
connect tlb.io.ptw.ptbr, io.ptw.ptbr
connect tlb.io.ptw.resp, io.ptw.resp
connect io.ptw.req.bits, tlb.io.ptw.req.bits
connect io.ptw.req.valid, tlb.io.ptw.req.valid
connect tlb.io.ptw.req.ready, io.ptw.req.ready
node _tlb_io_kill_T = and(s2_tlb_req_valid, io.tlb_port.s2_kill)
node _tlb_io_kill_T_1 = or(io.cpu.s2_kill, _tlb_io_kill_T)
connect tlb.io.kill, _tlb_io_kill_T_1
node _tlb_io_req_valid_T = eq(io.cpu.s1_kill, UInt<1>(0h0))
node _tlb_io_req_valid_T_1 = and(s1_valid, _tlb_io_req_valid_T)
node _tlb_io_req_valid_T_2 = and(_tlb_io_req_valid_T_1, s1_cmd_uses_tlb)
node _tlb_io_req_valid_T_3 = or(s1_tlb_req_valid, _tlb_io_req_valid_T_2)
connect tlb.io.req.valid, _tlb_io_req_valid_T_3
connect tlb.io.req.bits.v, s1_tlb_req.v
connect tlb.io.req.bits.prv, s1_tlb_req.prv
connect tlb.io.req.bits.cmd, s1_tlb_req.cmd
connect tlb.io.req.bits.size, s1_tlb_req.size
connect tlb.io.req.bits.passthrough, s1_tlb_req.passthrough
connect tlb.io.req.bits.vaddr, s1_tlb_req.vaddr
node _T_6 = eq(tlb.io.req.ready, UInt<1>(0h0))
node _T_7 = eq(tlb.io.ptw.resp.valid, UInt<1>(0h0))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.cpu.req.bits.phys, UInt<1>(0h0))
node _T_10 = and(_T_8, _T_9)
when _T_10 :
connect io.cpu.req.ready, UInt<1>(0h0)
node _T_11 = eq(s1_tlb_req_valid, UInt<1>(0h0))
node _T_12 = and(_T_11, s1_valid)
node _T_13 = and(_T_12, s1_cmd_uses_tlb)
node _T_14 = and(_T_13, tlb.io.resp.miss)
when _T_14 :
connect s1_nack, UInt<1>(0h1)
node _tlb_io_sfence_valid_T = eq(io.cpu.s1_kill, UInt<1>(0h0))
node _tlb_io_sfence_valid_T_1 = and(s1_valid, _tlb_io_sfence_valid_T)
node _tlb_io_sfence_valid_T_2 = and(_tlb_io_sfence_valid_T_1, s1_sfence)
connect tlb.io.sfence.valid, _tlb_io_sfence_valid_T_2
node _tlb_io_sfence_bits_rs1_T = bits(s1_req.size, 0, 0)
connect tlb.io.sfence.bits.rs1, _tlb_io_sfence_bits_rs1_T
node _tlb_io_sfence_bits_rs2_T = bits(s1_req.size, 1, 1)
connect tlb.io.sfence.bits.rs2, _tlb_io_sfence_bits_rs2_T
connect tlb.io.sfence.bits.asid, io.cpu.s1_data.data
connect tlb.io.sfence.bits.addr, s1_req.addr
node _tlb_io_sfence_bits_hv_T = eq(s1_req.cmd, UInt<5>(0h15))
connect tlb.io.sfence.bits.hv, _tlb_io_sfence_bits_hv_T
node _tlb_io_sfence_bits_hg_T = eq(s1_req.cmd, UInt<5>(0h16))
connect tlb.io.sfence.bits.hg, _tlb_io_sfence_bits_hg_T
connect io.tlb_port.req.ready, clock_en_reg
connect io.tlb_port.s1_resp, tlb.io.resp
node _T_15 = and(s1_tlb_req_valid, s1_valid)
node _T_16 = and(s1_req.phys, s1_req.no_xcpt)
node _T_17 = eq(_T_16, UInt<1>(0h0))
node _T_18 = and(_T_15, _T_17)
when _T_18 :
connect s1_nack, UInt<1>(0h1)
invalidate pma_checker.io.kill
invalidate pma_checker.io.ptw.gstatus.uie
invalidate pma_checker.io.ptw.gstatus.sie
invalidate pma_checker.io.ptw.gstatus.hie
invalidate pma_checker.io.ptw.gstatus.mie
invalidate pma_checker.io.ptw.gstatus.upie
invalidate pma_checker.io.ptw.gstatus.spie
invalidate pma_checker.io.ptw.gstatus.ube
invalidate pma_checker.io.ptw.gstatus.mpie
invalidate pma_checker.io.ptw.gstatus.spp
invalidate pma_checker.io.ptw.gstatus.vs
invalidate pma_checker.io.ptw.gstatus.mpp
invalidate pma_checker.io.ptw.gstatus.fs
invalidate pma_checker.io.ptw.gstatus.xs
invalidate pma_checker.io.ptw.gstatus.mprv
invalidate pma_checker.io.ptw.gstatus.sum
invalidate pma_checker.io.ptw.gstatus.mxr
invalidate pma_checker.io.ptw.gstatus.tvm
invalidate pma_checker.io.ptw.gstatus.tw
invalidate pma_checker.io.ptw.gstatus.tsr
invalidate pma_checker.io.ptw.gstatus.zero1
invalidate pma_checker.io.ptw.gstatus.sd_rv32
invalidate pma_checker.io.ptw.gstatus.uxl
invalidate pma_checker.io.ptw.gstatus.sxl
invalidate pma_checker.io.ptw.gstatus.sbe
invalidate pma_checker.io.ptw.gstatus.mbe
invalidate pma_checker.io.ptw.gstatus.gva
invalidate pma_checker.io.ptw.gstatus.mpv
invalidate pma_checker.io.ptw.gstatus.zero2
invalidate pma_checker.io.ptw.gstatus.sd
invalidate pma_checker.io.ptw.gstatus.v
invalidate pma_checker.io.ptw.gstatus.prv
invalidate pma_checker.io.ptw.gstatus.dv
invalidate pma_checker.io.ptw.gstatus.dprv
invalidate pma_checker.io.ptw.gstatus.isa
invalidate pma_checker.io.ptw.gstatus.wfi
invalidate pma_checker.io.ptw.gstatus.cease
invalidate pma_checker.io.ptw.gstatus.debug
invalidate pma_checker.io.ptw.hstatus.zero1
invalidate pma_checker.io.ptw.hstatus.vsbe
invalidate pma_checker.io.ptw.hstatus.gva
invalidate pma_checker.io.ptw.hstatus.spv
invalidate pma_checker.io.ptw.hstatus.spvp
invalidate pma_checker.io.ptw.hstatus.hu
invalidate pma_checker.io.ptw.hstatus.zero2
invalidate pma_checker.io.ptw.hstatus.vgein
invalidate pma_checker.io.ptw.hstatus.zero3
invalidate pma_checker.io.ptw.hstatus.vtvm
invalidate pma_checker.io.ptw.hstatus.vtw
invalidate pma_checker.io.ptw.hstatus.vtsr
invalidate pma_checker.io.ptw.hstatus.zero5
invalidate pma_checker.io.ptw.hstatus.vsxl
invalidate pma_checker.io.ptw.hstatus.zero6
invalidate pma_checker.io.ptw.status.uie
invalidate pma_checker.io.ptw.status.sie
invalidate pma_checker.io.ptw.status.hie
invalidate pma_checker.io.ptw.status.mie
invalidate pma_checker.io.ptw.status.upie
invalidate pma_checker.io.ptw.status.spie
invalidate pma_checker.io.ptw.status.ube
invalidate pma_checker.io.ptw.status.mpie
invalidate pma_checker.io.ptw.status.spp
invalidate pma_checker.io.ptw.status.vs
invalidate pma_checker.io.ptw.status.mpp
invalidate pma_checker.io.ptw.status.fs
invalidate pma_checker.io.ptw.status.xs
invalidate pma_checker.io.ptw.status.mprv
invalidate pma_checker.io.ptw.status.sum
invalidate pma_checker.io.ptw.status.mxr
invalidate pma_checker.io.ptw.status.tvm
invalidate pma_checker.io.ptw.status.tw
invalidate pma_checker.io.ptw.status.tsr
invalidate pma_checker.io.ptw.status.zero1
invalidate pma_checker.io.ptw.status.sd_rv32
invalidate pma_checker.io.ptw.status.uxl
invalidate pma_checker.io.ptw.status.sxl
invalidate pma_checker.io.ptw.status.sbe
invalidate pma_checker.io.ptw.status.mbe
invalidate pma_checker.io.ptw.status.gva
invalidate pma_checker.io.ptw.status.mpv
invalidate pma_checker.io.ptw.status.zero2
invalidate pma_checker.io.ptw.status.sd
invalidate pma_checker.io.ptw.status.v
invalidate pma_checker.io.ptw.status.prv
invalidate pma_checker.io.ptw.status.dv
invalidate pma_checker.io.ptw.status.dprv
invalidate pma_checker.io.ptw.status.isa
invalidate pma_checker.io.ptw.status.wfi
invalidate pma_checker.io.ptw.status.cease
invalidate pma_checker.io.ptw.status.debug
invalidate pma_checker.io.ptw.vsatp.ppn
invalidate pma_checker.io.ptw.vsatp.asid
invalidate pma_checker.io.ptw.vsatp.mode
invalidate pma_checker.io.ptw.hgatp.ppn
invalidate pma_checker.io.ptw.hgatp.asid
invalidate pma_checker.io.ptw.hgatp.mode
invalidate pma_checker.io.ptw.ptbr.ppn
invalidate pma_checker.io.ptw.ptbr.asid
invalidate pma_checker.io.ptw.ptbr.mode
invalidate pma_checker.io.ptw.resp.bits.gpa_is_pte
invalidate pma_checker.io.ptw.resp.bits.gpa.bits
invalidate pma_checker.io.ptw.resp.bits.gpa.valid
invalidate pma_checker.io.ptw.resp.bits.homogeneous
invalidate pma_checker.io.ptw.resp.bits.fragmented_superpage
invalidate pma_checker.io.ptw.resp.bits.level
invalidate pma_checker.io.ptw.resp.bits.pte.v
invalidate pma_checker.io.ptw.resp.bits.pte.r
invalidate pma_checker.io.ptw.resp.bits.pte.w
invalidate pma_checker.io.ptw.resp.bits.pte.x
invalidate pma_checker.io.ptw.resp.bits.pte.u
invalidate pma_checker.io.ptw.resp.bits.pte.g
invalidate pma_checker.io.ptw.resp.bits.pte.a
invalidate pma_checker.io.ptw.resp.bits.pte.d
invalidate pma_checker.io.ptw.resp.bits.pte.reserved_for_software
invalidate pma_checker.io.ptw.resp.bits.pte.ppn
invalidate pma_checker.io.ptw.resp.bits.pte.reserved_for_future
invalidate pma_checker.io.ptw.resp.bits.hx
invalidate pma_checker.io.ptw.resp.bits.hw
invalidate pma_checker.io.ptw.resp.bits.hr
invalidate pma_checker.io.ptw.resp.bits.gf
invalidate pma_checker.io.ptw.resp.bits.pf
invalidate pma_checker.io.ptw.resp.bits.ae_final
invalidate pma_checker.io.ptw.resp.bits.ae_ptw
invalidate pma_checker.io.ptw.resp.valid
invalidate pma_checker.io.ptw.req.bits.bits.stage2
invalidate pma_checker.io.ptw.req.bits.bits.vstage1
invalidate pma_checker.io.ptw.req.bits.bits.need_gpa
invalidate pma_checker.io.ptw.req.bits.bits.addr
invalidate pma_checker.io.ptw.req.bits.valid
invalidate pma_checker.io.ptw.req.valid
invalidate pma_checker.io.ptw.req.ready
invalidate pma_checker.io.sfence.bits.hg
invalidate pma_checker.io.sfence.bits.hv
invalidate pma_checker.io.sfence.bits.asid
invalidate pma_checker.io.sfence.bits.addr
invalidate pma_checker.io.sfence.bits.rs2
invalidate pma_checker.io.sfence.bits.rs1
invalidate pma_checker.io.sfence.valid
invalidate pma_checker.io.resp.cmd
invalidate pma_checker.io.resp.size
invalidate pma_checker.io.resp.prefetchable
invalidate pma_checker.io.resp.must_alloc
invalidate pma_checker.io.resp.cacheable
invalidate pma_checker.io.resp.ma.inst
invalidate pma_checker.io.resp.ma.st
invalidate pma_checker.io.resp.ma.ld
invalidate pma_checker.io.resp.ae.inst
invalidate pma_checker.io.resp.ae.st
invalidate pma_checker.io.resp.ae.ld
invalidate pma_checker.io.resp.gf.inst
invalidate pma_checker.io.resp.gf.st
invalidate pma_checker.io.resp.gf.ld
invalidate pma_checker.io.resp.pf.inst
invalidate pma_checker.io.resp.pf.st
invalidate pma_checker.io.resp.pf.ld
invalidate pma_checker.io.resp.gpa_is_pte
invalidate pma_checker.io.resp.gpa
invalidate pma_checker.io.resp.paddr
invalidate pma_checker.io.resp.miss
invalidate pma_checker.io.req.bits.v
invalidate pma_checker.io.req.bits.prv
invalidate pma_checker.io.req.bits.cmd
invalidate pma_checker.io.req.bits.size
invalidate pma_checker.io.req.bits.passthrough
invalidate pma_checker.io.req.bits.vaddr
invalidate pma_checker.io.req.valid
invalidate pma_checker.io.req.ready
connect pma_checker.io.req.bits.passthrough, UInt<1>(0h1)
connect pma_checker.io.req.bits.vaddr, s1_req.addr
connect pma_checker.io.req.bits.size, s1_req.size
connect pma_checker.io.req.bits.cmd, s1_req.cmd
connect pma_checker.io.req.bits.prv, s1_req.dprv
connect pma_checker.io.req.bits.v, s1_req.dv
node _s1_paddr_T = bits(s1_req.addr, 31, 12)
node _s1_paddr_T_1 = shr(tlb.io.resp.paddr, 12)
node _s1_paddr_T_2 = mux(s1_tlb_req_valid, _s1_paddr_T, _s1_paddr_T_1)
node _s1_paddr_T_3 = bits(s1_req.addr, 11, 0)
node s1_paddr = cat(_s1_paddr_T_2, _s1_paddr_T_3)
wire s1_victim_way : UInt
node _T_19 = and(metaArb.io.out.valid, metaArb.io.out.bits.write)
when _T_19 :
node wmask_0 = bits(metaArb.io.out.bits.way_en, 0, 0)
node wmask_1 = bits(metaArb.io.out.bits.way_en, 1, 1)
node wmask_2 = bits(metaArb.io.out.bits.way_en, 2, 2)
node wmask_3 = bits(metaArb.io.out.bits.way_en, 3, 3)
wire _WIRE : UInt<26>[4]
connect _WIRE[0], metaArb.io.out.bits.data
connect _WIRE[1], metaArb.io.out.bits.data
connect _WIRE[2], metaArb.io.out.bits.data
connect _WIRE[3], metaArb.io.out.bits.data
write mport MPORT = rerocc_tile_dcache_tag_array[metaArb.io.out.bits.idx], clock
when wmask_0 :
connect MPORT[0], _WIRE[0]
when wmask_1 :
connect MPORT[1], _WIRE[1]
when wmask_2 :
connect MPORT[2], _WIRE[2]
when wmask_3 :
connect MPORT[3], _WIRE[3]
node _s1_meta_T = eq(metaArb.io.out.bits.write, UInt<1>(0h0))
node _s1_meta_T_1 = and(metaArb.io.out.valid, _s1_meta_T)
wire _s1_meta_WIRE : UInt<2>
invalidate _s1_meta_WIRE
when _s1_meta_T_1 :
connect _s1_meta_WIRE, metaArb.io.out.bits.idx
read mport s1_meta = rerocc_tile_dcache_tag_array[_s1_meta_WIRE], clock
wire s1_meta_uncorrected_0 : { coh : { state : UInt<2>}, tag : UInt<24>}
wire _s1_meta_uncorrected_WIRE : UInt<26>
connect _s1_meta_uncorrected_WIRE, s1_meta[0]
node _s1_meta_uncorrected_T = bits(_s1_meta_uncorrected_WIRE, 23, 0)
connect s1_meta_uncorrected_0.tag, _s1_meta_uncorrected_T
node _s1_meta_uncorrected_T_1 = bits(_s1_meta_uncorrected_WIRE, 25, 24)
connect s1_meta_uncorrected_0.coh.state, _s1_meta_uncorrected_T_1
wire s1_meta_uncorrected_1 : { coh : { state : UInt<2>}, tag : UInt<24>}
wire _s1_meta_uncorrected_WIRE_1 : UInt<26>
connect _s1_meta_uncorrected_WIRE_1, s1_meta[1]
node _s1_meta_uncorrected_T_2 = bits(_s1_meta_uncorrected_WIRE_1, 23, 0)
connect s1_meta_uncorrected_1.tag, _s1_meta_uncorrected_T_2
node _s1_meta_uncorrected_T_3 = bits(_s1_meta_uncorrected_WIRE_1, 25, 24)
connect s1_meta_uncorrected_1.coh.state, _s1_meta_uncorrected_T_3
wire s1_meta_uncorrected_2 : { coh : { state : UInt<2>}, tag : UInt<24>}
wire _s1_meta_uncorrected_WIRE_2 : UInt<26>
connect _s1_meta_uncorrected_WIRE_2, s1_meta[2]
node _s1_meta_uncorrected_T_4 = bits(_s1_meta_uncorrected_WIRE_2, 23, 0)
connect s1_meta_uncorrected_2.tag, _s1_meta_uncorrected_T_4
node _s1_meta_uncorrected_T_5 = bits(_s1_meta_uncorrected_WIRE_2, 25, 24)
connect s1_meta_uncorrected_2.coh.state, _s1_meta_uncorrected_T_5
wire s1_meta_uncorrected_3 : { coh : { state : UInt<2>}, tag : UInt<24>}
wire _s1_meta_uncorrected_WIRE_3 : UInt<26>
connect _s1_meta_uncorrected_WIRE_3, s1_meta[3]
node _s1_meta_uncorrected_T_6 = bits(_s1_meta_uncorrected_WIRE_3, 23, 0)
connect s1_meta_uncorrected_3.tag, _s1_meta_uncorrected_T_6
node _s1_meta_uncorrected_T_7 = bits(_s1_meta_uncorrected_WIRE_3, 25, 24)
connect s1_meta_uncorrected_3.coh.state, _s1_meta_uncorrected_T_7
node s1_tag = shr(s1_paddr, 8)
node _s1_meta_hit_way_T = gt(s1_meta_uncorrected_0.coh.state, UInt<2>(0h0))
node _s1_meta_hit_way_T_1 = eq(s1_meta_uncorrected_0.tag, s1_tag)
node _s1_meta_hit_way_T_2 = and(_s1_meta_hit_way_T, _s1_meta_hit_way_T_1)
node _s1_meta_hit_way_T_3 = gt(s1_meta_uncorrected_1.coh.state, UInt<2>(0h0))
node _s1_meta_hit_way_T_4 = eq(s1_meta_uncorrected_1.tag, s1_tag)
node _s1_meta_hit_way_T_5 = and(_s1_meta_hit_way_T_3, _s1_meta_hit_way_T_4)
node _s1_meta_hit_way_T_6 = gt(s1_meta_uncorrected_2.coh.state, UInt<2>(0h0))
node _s1_meta_hit_way_T_7 = eq(s1_meta_uncorrected_2.tag, s1_tag)
node _s1_meta_hit_way_T_8 = and(_s1_meta_hit_way_T_6, _s1_meta_hit_way_T_7)
node _s1_meta_hit_way_T_9 = gt(s1_meta_uncorrected_3.coh.state, UInt<2>(0h0))
node _s1_meta_hit_way_T_10 = eq(s1_meta_uncorrected_3.tag, s1_tag)
node _s1_meta_hit_way_T_11 = and(_s1_meta_hit_way_T_9, _s1_meta_hit_way_T_10)
node s1_meta_hit_way_lo = cat(_s1_meta_hit_way_T_5, _s1_meta_hit_way_T_2)
node s1_meta_hit_way_hi = cat(_s1_meta_hit_way_T_11, _s1_meta_hit_way_T_8)
node s1_hit_way = cat(s1_meta_hit_way_hi, s1_meta_hit_way_lo)
node _s1_meta_hit_state_T = eq(s1_meta_uncorrected_0.tag, s1_tag)
node _s1_meta_hit_state_T_1 = eq(s1_flush_valid, UInt<1>(0h0))
node _s1_meta_hit_state_T_2 = and(_s1_meta_hit_state_T, _s1_meta_hit_state_T_1)
node _s1_meta_hit_state_T_3 = mux(_s1_meta_hit_state_T_2, s1_meta_uncorrected_0.coh.state, UInt<1>(0h0))
node _s1_meta_hit_state_T_4 = eq(s1_meta_uncorrected_1.tag, s1_tag)
node _s1_meta_hit_state_T_5 = eq(s1_flush_valid, UInt<1>(0h0))
node _s1_meta_hit_state_T_6 = and(_s1_meta_hit_state_T_4, _s1_meta_hit_state_T_5)
node _s1_meta_hit_state_T_7 = mux(_s1_meta_hit_state_T_6, s1_meta_uncorrected_1.coh.state, UInt<1>(0h0))
node _s1_meta_hit_state_T_8 = eq(s1_meta_uncorrected_2.tag, s1_tag)
node _s1_meta_hit_state_T_9 = eq(s1_flush_valid, UInt<1>(0h0))
node _s1_meta_hit_state_T_10 = and(_s1_meta_hit_state_T_8, _s1_meta_hit_state_T_9)
node _s1_meta_hit_state_T_11 = mux(_s1_meta_hit_state_T_10, s1_meta_uncorrected_2.coh.state, UInt<1>(0h0))
node _s1_meta_hit_state_T_12 = eq(s1_meta_uncorrected_3.tag, s1_tag)
node _s1_meta_hit_state_T_13 = eq(s1_flush_valid, UInt<1>(0h0))
node _s1_meta_hit_state_T_14 = and(_s1_meta_hit_state_T_12, _s1_meta_hit_state_T_13)
node _s1_meta_hit_state_T_15 = mux(_s1_meta_hit_state_T_14, s1_meta_uncorrected_3.coh.state, UInt<1>(0h0))
node _s1_meta_hit_state_T_16 = or(_s1_meta_hit_state_T_3, _s1_meta_hit_state_T_7)
node _s1_meta_hit_state_T_17 = or(_s1_meta_hit_state_T_16, _s1_meta_hit_state_T_11)
node _s1_meta_hit_state_T_18 = or(_s1_meta_hit_state_T_17, _s1_meta_hit_state_T_15)
wire s1_meta_hit_state_meta : { state : UInt<2>}
connect s1_meta_hit_state_meta.state, UInt<2>(0h0)
wire s1_hit_state : { state : UInt<2>}
wire _s1_meta_hit_state_WIRE : UInt<2>
connect _s1_meta_hit_state_WIRE, _s1_meta_hit_state_T_18
node _s1_meta_hit_state_T_19 = bits(_s1_meta_hit_state_WIRE, 1, 0)
connect s1_hit_state.state, _s1_meta_hit_state_T_19
node _s1_data_way_T = mux(inWriteback, releaseWay, s1_hit_way)
wire s1_data_way : UInt
connect s1_data_way, _s1_data_way_T
node _tl_d_data_encoded_T = bits(nodeOut.d.bits.data, 7, 0)
node _tl_d_data_encoded_T_1 = bits(nodeOut.d.bits.data, 15, 8)
node _tl_d_data_encoded_T_2 = bits(nodeOut.d.bits.data, 23, 16)
node _tl_d_data_encoded_T_3 = bits(nodeOut.d.bits.data, 31, 24)
node _tl_d_data_encoded_T_4 = bits(nodeOut.d.bits.data, 39, 32)
node _tl_d_data_encoded_T_5 = bits(nodeOut.d.bits.data, 47, 40)
node _tl_d_data_encoded_T_6 = bits(nodeOut.d.bits.data, 55, 48)
node _tl_d_data_encoded_T_7 = bits(nodeOut.d.bits.data, 63, 56)
node tl_d_data_encoded_lo_lo = cat(_tl_d_data_encoded_T_1, _tl_d_data_encoded_T)
node tl_d_data_encoded_lo_hi = cat(_tl_d_data_encoded_T_3, _tl_d_data_encoded_T_2)
node tl_d_data_encoded_lo = cat(tl_d_data_encoded_lo_hi, tl_d_data_encoded_lo_lo)
node tl_d_data_encoded_hi_lo = cat(_tl_d_data_encoded_T_5, _tl_d_data_encoded_T_4)
node tl_d_data_encoded_hi_hi = cat(_tl_d_data_encoded_T_7, _tl_d_data_encoded_T_6)
node tl_d_data_encoded_hi = cat(tl_d_data_encoded_hi_hi, tl_d_data_encoded_hi_lo)
node _tl_d_data_encoded_T_8 = cat(tl_d_data_encoded_hi, tl_d_data_encoded_lo)
wire tl_d_data_encoded : UInt<64>
wire s1_all_data_ways : UInt<64>[5]
connect s1_all_data_ways[0], data.io.resp[0]
connect s1_all_data_ways[1], data.io.resp[1]
connect s1_all_data_ways[2], data.io.resp[2]
connect s1_all_data_ways[3], data.io.resp[3]
connect s1_all_data_ways[4], tl_d_data_encoded
wire s1_mask_xwr_size : UInt<2>
connect s1_mask_xwr_size, s1_req.size
node _s1_mask_xwr_upper_T = bits(s1_req.addr, 0, 0)
node _s1_mask_xwr_upper_T_1 = mux(_s1_mask_xwr_upper_T, UInt<1>(0h1), UInt<1>(0h0))
node _s1_mask_xwr_upper_T_2 = geq(s1_mask_xwr_size, UInt<1>(0h1))
node _s1_mask_xwr_upper_T_3 = mux(_s1_mask_xwr_upper_T_2, UInt<1>(0h1), UInt<1>(0h0))
node s1_mask_xwr_upper = or(_s1_mask_xwr_upper_T_1, _s1_mask_xwr_upper_T_3)
node _s1_mask_xwr_lower_T = bits(s1_req.addr, 0, 0)
node s1_mask_xwr_lower = mux(_s1_mask_xwr_lower_T, UInt<1>(0h0), UInt<1>(0h1))
node _s1_mask_xwr_T = cat(s1_mask_xwr_upper, s1_mask_xwr_lower)
node _s1_mask_xwr_upper_T_4 = bits(s1_req.addr, 1, 1)
node _s1_mask_xwr_upper_T_5 = mux(_s1_mask_xwr_upper_T_4, _s1_mask_xwr_T, UInt<1>(0h0))
node _s1_mask_xwr_upper_T_6 = geq(s1_mask_xwr_size, UInt<2>(0h2))
node _s1_mask_xwr_upper_T_7 = mux(_s1_mask_xwr_upper_T_6, UInt<2>(0h3), UInt<1>(0h0))
node s1_mask_xwr_upper_1 = or(_s1_mask_xwr_upper_T_5, _s1_mask_xwr_upper_T_7)
node _s1_mask_xwr_lower_T_1 = bits(s1_req.addr, 1, 1)
node s1_mask_xwr_lower_1 = mux(_s1_mask_xwr_lower_T_1, UInt<1>(0h0), _s1_mask_xwr_T)
node _s1_mask_xwr_T_1 = cat(s1_mask_xwr_upper_1, s1_mask_xwr_lower_1)
node _s1_mask_xwr_upper_T_8 = bits(s1_req.addr, 2, 2)
node _s1_mask_xwr_upper_T_9 = mux(_s1_mask_xwr_upper_T_8, _s1_mask_xwr_T_1, UInt<1>(0h0))
node _s1_mask_xwr_upper_T_10 = geq(s1_mask_xwr_size, UInt<2>(0h3))
node _s1_mask_xwr_upper_T_11 = mux(_s1_mask_xwr_upper_T_10, UInt<4>(0hf), UInt<1>(0h0))
node s1_mask_xwr_upper_2 = or(_s1_mask_xwr_upper_T_9, _s1_mask_xwr_upper_T_11)
node _s1_mask_xwr_lower_T_2 = bits(s1_req.addr, 2, 2)
node s1_mask_xwr_lower_2 = mux(_s1_mask_xwr_lower_T_2, UInt<1>(0h0), _s1_mask_xwr_T_1)
node s1_mask_xwr = cat(s1_mask_xwr_upper_2, s1_mask_xwr_lower_2)
node _s1_mask_T = eq(s1_req.cmd, UInt<5>(0h11))
node s1_mask = mux(_s1_mask_T, io.cpu.s1_data.mask, s1_mask_xwr)
node _T_20 = eq(s1_req.cmd, UInt<5>(0h11))
node _T_21 = and(s1_valid_masked, _T_20)
node _T_22 = eq(_T_21, UInt<1>(0h0))
node _T_23 = not(io.cpu.s1_data.mask)
node _T_24 = or(s1_mask_xwr, _T_23)
node _T_25 = andr(_T_24)
node _T_26 = or(_T_22, _T_25)
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
node _T_29 = eq(_T_26, UInt<1>(0h0))
when _T_29 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:329 assert(!(s1_valid_masked && s1_req.cmd === M_PWR) || (s1_mask_xwr | ~io.cpu.s1_data.mask).andR)\n") : printf
assert(clock, _T_26, UInt<1>(0h1), "") : assert
node _s2_valid_T = eq(s1_sfence, UInt<1>(0h0))
node _s2_valid_T_1 = and(s1_valid_masked, _s2_valid_T)
regreset s2_valid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s2_valid, _s2_valid_T_1
node _s2_valid_no_xcpt_T = cat(io.cpu.s2_xcpt.ae.ld, io.cpu.s2_xcpt.ae.st)
node _s2_valid_no_xcpt_T_1 = cat(io.cpu.s2_xcpt.gf.ld, io.cpu.s2_xcpt.gf.st)
node _s2_valid_no_xcpt_T_2 = cat(io.cpu.s2_xcpt.pf.ld, io.cpu.s2_xcpt.pf.st)
node _s2_valid_no_xcpt_T_3 = cat(io.cpu.s2_xcpt.ma.ld, io.cpu.s2_xcpt.ma.st)
node s2_valid_no_xcpt_lo = cat(_s2_valid_no_xcpt_T_1, _s2_valid_no_xcpt_T)
node s2_valid_no_xcpt_hi = cat(_s2_valid_no_xcpt_T_3, _s2_valid_no_xcpt_T_2)
node _s2_valid_no_xcpt_T_4 = cat(s2_valid_no_xcpt_hi, s2_valid_no_xcpt_lo)
node _s2_valid_no_xcpt_T_5 = orr(_s2_valid_no_xcpt_T_4)
node _s2_valid_no_xcpt_T_6 = eq(_s2_valid_no_xcpt_T_5, UInt<1>(0h0))
node s2_valid_no_xcpt = and(s2_valid, _s2_valid_no_xcpt_T_6)
regreset s2_probe : UInt<1>, clock, reset, UInt<1>(0h0)
connect s2_probe, s1_probe
node _releaseInFlight_T = or(s1_probe, s2_probe)
node _releaseInFlight_T_1 = neq(release_state, UInt<4>(0h0))
node releaseInFlight = or(_releaseInFlight_T, _releaseInFlight_T_1)
node _s2_not_nacked_in_s1_T = eq(s1_nack, UInt<1>(0h0))
reg s2_not_nacked_in_s1 : UInt<1>, clock
connect s2_not_nacked_in_s1, _s2_not_nacked_in_s1_T
node s2_valid_not_nacked_in_s1 = and(s2_valid, s2_not_nacked_in_s1)
node s2_valid_masked = and(s2_valid_no_xcpt, s2_not_nacked_in_s1)
node _s2_valid_not_killed_T = eq(io.cpu.s2_kill, UInt<1>(0h0))
node s2_valid_not_killed = and(s2_valid_masked, _s2_valid_not_killed_T)
reg s2_req : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock
node _s2_cmd_flush_all_T = eq(s2_req.cmd, UInt<3>(0h5))
node _s2_cmd_flush_all_T_1 = bits(s2_req.size, 0, 0)
node _s2_cmd_flush_all_T_2 = eq(_s2_cmd_flush_all_T_1, UInt<1>(0h0))
node s2_cmd_flush_all = and(_s2_cmd_flush_all_T, _s2_cmd_flush_all_T_2)
node _s2_cmd_flush_line_T = eq(s2_req.cmd, UInt<3>(0h5))
node _s2_cmd_flush_line_T_1 = bits(s2_req.size, 0, 0)
node s2_cmd_flush_line = and(_s2_cmd_flush_line_T, _s2_cmd_flush_line_T_1)
reg s2_tlb_xcpt : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, clock
reg s2_pma : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, clock
reg s2_uncached_resp_addr : UInt<40>, clock
node _T_30 = or(s1_valid_not_nacked, s1_flush_valid)
when _T_30 :
connect s2_req, s1_req
connect s2_req.addr, s1_paddr
connect s2_tlb_xcpt, tlb.io.resp
node _s2_pma_T = mux(s1_tlb_req_valid, pma_checker.io.resp, tlb.io.resp)
connect s2_pma, _s2_pma_T
node _s2_vaddr_T = or(s1_valid_not_nacked, s1_flush_valid)
reg s2_vaddr_r : UInt<40>, clock
when _s2_vaddr_T :
connect s2_vaddr_r, s1_vaddr
node _s2_vaddr_T_1 = shr(s2_vaddr_r, 8)
node _s2_vaddr_T_2 = bits(s2_req.addr, 7, 0)
node s2_vaddr = cat(_s2_vaddr_T_1, _s2_vaddr_T_2)
node _s2_read_T = eq(s2_req.cmd, UInt<1>(0h0))
node _s2_read_T_1 = eq(s2_req.cmd, UInt<5>(0h10))
node _s2_read_T_2 = eq(s2_req.cmd, UInt<3>(0h6))
node _s2_read_T_3 = eq(s2_req.cmd, UInt<3>(0h7))
node _s2_read_T_4 = or(_s2_read_T, _s2_read_T_1)
node _s2_read_T_5 = or(_s2_read_T_4, _s2_read_T_2)
node _s2_read_T_6 = or(_s2_read_T_5, _s2_read_T_3)
node _s2_read_T_7 = eq(s2_req.cmd, UInt<3>(0h4))
node _s2_read_T_8 = eq(s2_req.cmd, UInt<4>(0h9))
node _s2_read_T_9 = eq(s2_req.cmd, UInt<4>(0ha))
node _s2_read_T_10 = eq(s2_req.cmd, UInt<4>(0hb))
node _s2_read_T_11 = or(_s2_read_T_7, _s2_read_T_8)
node _s2_read_T_12 = or(_s2_read_T_11, _s2_read_T_9)
node _s2_read_T_13 = or(_s2_read_T_12, _s2_read_T_10)
node _s2_read_T_14 = eq(s2_req.cmd, UInt<4>(0h8))
node _s2_read_T_15 = eq(s2_req.cmd, UInt<4>(0hc))
node _s2_read_T_16 = eq(s2_req.cmd, UInt<4>(0hd))
node _s2_read_T_17 = eq(s2_req.cmd, UInt<4>(0he))
node _s2_read_T_18 = eq(s2_req.cmd, UInt<4>(0hf))
node _s2_read_T_19 = or(_s2_read_T_14, _s2_read_T_15)
node _s2_read_T_20 = or(_s2_read_T_19, _s2_read_T_16)
node _s2_read_T_21 = or(_s2_read_T_20, _s2_read_T_17)
node _s2_read_T_22 = or(_s2_read_T_21, _s2_read_T_18)
node _s2_read_T_23 = or(_s2_read_T_13, _s2_read_T_22)
node s2_read = or(_s2_read_T_6, _s2_read_T_23)
node _s2_write_T = eq(s2_req.cmd, UInt<1>(0h1))
node _s2_write_T_1 = eq(s2_req.cmd, UInt<5>(0h11))
node _s2_write_T_2 = or(_s2_write_T, _s2_write_T_1)
node _s2_write_T_3 = eq(s2_req.cmd, UInt<3>(0h7))
node _s2_write_T_4 = or(_s2_write_T_2, _s2_write_T_3)
node _s2_write_T_5 = eq(s2_req.cmd, UInt<3>(0h4))
node _s2_write_T_6 = eq(s2_req.cmd, UInt<4>(0h9))
node _s2_write_T_7 = eq(s2_req.cmd, UInt<4>(0ha))
node _s2_write_T_8 = eq(s2_req.cmd, UInt<4>(0hb))
node _s2_write_T_9 = or(_s2_write_T_5, _s2_write_T_6)
node _s2_write_T_10 = or(_s2_write_T_9, _s2_write_T_7)
node _s2_write_T_11 = or(_s2_write_T_10, _s2_write_T_8)
node _s2_write_T_12 = eq(s2_req.cmd, UInt<4>(0h8))
node _s2_write_T_13 = eq(s2_req.cmd, UInt<4>(0hc))
node _s2_write_T_14 = eq(s2_req.cmd, UInt<4>(0hd))
node _s2_write_T_15 = eq(s2_req.cmd, UInt<4>(0he))
node _s2_write_T_16 = eq(s2_req.cmd, UInt<4>(0hf))
node _s2_write_T_17 = or(_s2_write_T_12, _s2_write_T_13)
node _s2_write_T_18 = or(_s2_write_T_17, _s2_write_T_14)
node _s2_write_T_19 = or(_s2_write_T_18, _s2_write_T_15)
node _s2_write_T_20 = or(_s2_write_T_19, _s2_write_T_16)
node _s2_write_T_21 = or(_s2_write_T_11, _s2_write_T_20)
node s2_write = or(_s2_write_T_4, _s2_write_T_21)
node s2_readwrite = or(s2_read, s2_write)
reg s2_flush_valid_pre_tag_ecc : UInt<1>, clock
connect s2_flush_valid_pre_tag_ecc, s1_flush_valid
node _s1_meta_clk_en_T = or(s1_valid_not_nacked, s1_flush_valid)
node s1_meta_clk_en = or(_s1_meta_clk_en_T, s1_probe)
reg s2_meta_correctable_errors_r : UInt<1>, clock
when s1_meta_clk_en :
connect s2_meta_correctable_errors_r, UInt<1>(0h0)
reg s2_meta_correctable_errors_r_1 : UInt<1>, clock
when s1_meta_clk_en :
connect s2_meta_correctable_errors_r_1, UInt<1>(0h0)
reg s2_meta_correctable_errors_r_2 : UInt<1>, clock
when s1_meta_clk_en :
connect s2_meta_correctable_errors_r_2, UInt<1>(0h0)
reg s2_meta_correctable_errors_r_3 : UInt<1>, clock
when s1_meta_clk_en :
connect s2_meta_correctable_errors_r_3, UInt<1>(0h0)
node s2_meta_correctable_errors_lo = cat(s2_meta_correctable_errors_r_1, s2_meta_correctable_errors_r)
node s2_meta_correctable_errors_hi = cat(s2_meta_correctable_errors_r_3, s2_meta_correctable_errors_r_2)
node s2_meta_correctable_errors = cat(s2_meta_correctable_errors_hi, s2_meta_correctable_errors_lo)
reg s2_meta_uncorrectable_errors_r : UInt<1>, clock
when s1_meta_clk_en :
connect s2_meta_uncorrectable_errors_r, UInt<1>(0h0)
reg s2_meta_uncorrectable_errors_r_1 : UInt<1>, clock
when s1_meta_clk_en :
connect s2_meta_uncorrectable_errors_r_1, UInt<1>(0h0)
reg s2_meta_uncorrectable_errors_r_2 : UInt<1>, clock
when s1_meta_clk_en :
connect s2_meta_uncorrectable_errors_r_2, UInt<1>(0h0)
reg s2_meta_uncorrectable_errors_r_3 : UInt<1>, clock
when s1_meta_clk_en :
connect s2_meta_uncorrectable_errors_r_3, UInt<1>(0h0)
node s2_meta_uncorrectable_errors_lo = cat(s2_meta_uncorrectable_errors_r_1, s2_meta_uncorrectable_errors_r)
node s2_meta_uncorrectable_errors_hi = cat(s2_meta_uncorrectable_errors_r_3, s2_meta_uncorrectable_errors_r_2)
node s2_meta_uncorrectable_errors = cat(s2_meta_uncorrectable_errors_hi, s2_meta_uncorrectable_errors_lo)
node s2_meta_error_uncorrectable = orr(s2_meta_uncorrectable_errors)
reg s2_meta_corrected_r : UInt<26>, clock
when s1_meta_clk_en :
connect s2_meta_corrected_r, s1_meta[0]
wire s2_meta_corrected_0 : { coh : { state : UInt<2>}, tag : UInt<24>}
wire _s2_meta_corrected_WIRE : UInt<26>
connect _s2_meta_corrected_WIRE, s2_meta_corrected_r
node _s2_meta_corrected_T = bits(_s2_meta_corrected_WIRE, 23, 0)
connect s2_meta_corrected_0.tag, _s2_meta_corrected_T
node _s2_meta_corrected_T_1 = bits(_s2_meta_corrected_WIRE, 25, 24)
connect s2_meta_corrected_0.coh.state, _s2_meta_corrected_T_1
reg s2_meta_corrected_r_1 : UInt<26>, clock
when s1_meta_clk_en :
connect s2_meta_corrected_r_1, s1_meta[1]
wire s2_meta_corrected_1 : { coh : { state : UInt<2>}, tag : UInt<24>}
wire _s2_meta_corrected_WIRE_1 : UInt<26>
connect _s2_meta_corrected_WIRE_1, s2_meta_corrected_r_1
node _s2_meta_corrected_T_2 = bits(_s2_meta_corrected_WIRE_1, 23, 0)
connect s2_meta_corrected_1.tag, _s2_meta_corrected_T_2
node _s2_meta_corrected_T_3 = bits(_s2_meta_corrected_WIRE_1, 25, 24)
connect s2_meta_corrected_1.coh.state, _s2_meta_corrected_T_3
reg s2_meta_corrected_r_2 : UInt<26>, clock
when s1_meta_clk_en :
connect s2_meta_corrected_r_2, s1_meta[2]
wire s2_meta_corrected_2 : { coh : { state : UInt<2>}, tag : UInt<24>}
wire _s2_meta_corrected_WIRE_2 : UInt<26>
connect _s2_meta_corrected_WIRE_2, s2_meta_corrected_r_2
node _s2_meta_corrected_T_4 = bits(_s2_meta_corrected_WIRE_2, 23, 0)
connect s2_meta_corrected_2.tag, _s2_meta_corrected_T_4
node _s2_meta_corrected_T_5 = bits(_s2_meta_corrected_WIRE_2, 25, 24)
connect s2_meta_corrected_2.coh.state, _s2_meta_corrected_T_5
reg s2_meta_corrected_r_3 : UInt<26>, clock
when s1_meta_clk_en :
connect s2_meta_corrected_r_3, s1_meta[3]
wire s2_meta_corrected_3 : { coh : { state : UInt<2>}, tag : UInt<24>}
wire _s2_meta_corrected_WIRE_3 : UInt<26>
connect _s2_meta_corrected_WIRE_3, s2_meta_corrected_r_3
node _s2_meta_corrected_T_6 = bits(_s2_meta_corrected_WIRE_3, 23, 0)
connect s2_meta_corrected_3.tag, _s2_meta_corrected_T_6
node _s2_meta_corrected_T_7 = bits(_s2_meta_corrected_WIRE_3, 25, 24)
connect s2_meta_corrected_3.coh.state, _s2_meta_corrected_T_7
node _s2_meta_error_T = or(s2_meta_uncorrectable_errors, s2_meta_correctable_errors)
node s2_meta_error = orr(_s2_meta_error_T)
node _s2_flush_valid_T = eq(s2_meta_error, UInt<1>(0h0))
node s2_flush_valid = and(s2_flush_valid_pre_tag_ecc, _s2_flush_valid_T)
node _s2_data_en_T = or(s1_valid, inWriteback)
node s2_data_en = or(_s2_data_en_T, io.cpu.replay_next)
node _s2_data_word_en_T = mux(s1_did_read, s1_read_mask, UInt<1>(0h0))
node s2_data_word_en = mux(inWriteback, UInt<1>(0h1), _s2_data_word_en_T)
node s2_data_s1_way_words_0_0 = bits(s1_all_data_ways[0], 63, 0)
node s2_data_s1_way_words_1_0 = bits(s1_all_data_ways[1], 63, 0)
node s2_data_s1_way_words_2_0 = bits(s1_all_data_ways[2], 63, 0)
node s2_data_s1_way_words_3_0 = bits(s1_all_data_ways[3], 63, 0)
node s2_data_s1_way_words_4_0 = bits(s1_all_data_ways[4], 63, 0)
node _s2_data_s1_word_en_T = eq(io.cpu.replay_next, UInt<1>(0h0))
node s2_data_s1_word_en = mux(_s2_data_s1_word_en_T, s2_data_word_en, UInt<1>(0h1))
node _s2_data_T = bits(s2_data_s1_word_en, 0, 0)
node _s2_data_T_1 = mux(_s2_data_T, s1_data_way, UInt<1>(0h0))
node _s2_data_T_2 = bits(_s2_data_T_1, 0, 0)
node _s2_data_T_3 = bits(_s2_data_T_1, 1, 1)
node _s2_data_T_4 = bits(_s2_data_T_1, 2, 2)
node _s2_data_T_5 = bits(_s2_data_T_1, 3, 3)
node _s2_data_T_6 = bits(_s2_data_T_1, 4, 4)
node _s2_data_T_7 = mux(_s2_data_T_2, s2_data_s1_way_words_0_0, UInt<1>(0h0))
node _s2_data_T_8 = mux(_s2_data_T_3, s2_data_s1_way_words_1_0, UInt<1>(0h0))
node _s2_data_T_9 = mux(_s2_data_T_4, s2_data_s1_way_words_2_0, UInt<1>(0h0))
node _s2_data_T_10 = mux(_s2_data_T_5, s2_data_s1_way_words_3_0, UInt<1>(0h0))
node _s2_data_T_11 = mux(_s2_data_T_6, s2_data_s1_way_words_4_0, UInt<1>(0h0))
node _s2_data_T_12 = or(_s2_data_T_7, _s2_data_T_8)
node _s2_data_T_13 = or(_s2_data_T_12, _s2_data_T_9)
node _s2_data_T_14 = or(_s2_data_T_13, _s2_data_T_10)
node _s2_data_T_15 = or(_s2_data_T_14, _s2_data_T_11)
wire _s2_data_WIRE : UInt<64>
connect _s2_data_WIRE, _s2_data_T_15
reg s2_data : UInt<64>, clock
when s2_data_en :
connect s2_data, _s2_data_WIRE
reg s2_probe_way : UInt<4>, clock
when s1_probe :
connect s2_probe_way, s1_hit_way
reg s2_probe_state : { state : UInt<2>}, clock
when s1_probe :
connect s2_probe_state, s1_hit_state
reg s2_hit_way : UInt<4>, clock
when s1_valid_not_nacked :
connect s2_hit_way, s1_hit_way
node _s2_hit_state_T = or(s1_valid_not_nacked, s1_flush_valid)
reg s2_hit_state : { state : UInt<2>}, clock
when _s2_hit_state_T :
connect s2_hit_state, s1_hit_state
reg s2_waw_hazard : UInt<1>, clock
when s1_valid_not_nacked :
connect s2_waw_hazard, s1_waw_hazard
wire s2_store_merge : UInt<1>
node s2_hit_valid = gt(s2_hit_state.state, UInt<2>(0h0))
node _r_c_cat_T = eq(s2_req.cmd, UInt<1>(0h1))
node _r_c_cat_T_1 = eq(s2_req.cmd, UInt<5>(0h11))
node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1)
node _r_c_cat_T_3 = eq(s2_req.cmd, UInt<3>(0h7))
node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3)
node _r_c_cat_T_5 = eq(s2_req.cmd, UInt<3>(0h4))
node _r_c_cat_T_6 = eq(s2_req.cmd, UInt<4>(0h9))
node _r_c_cat_T_7 = eq(s2_req.cmd, UInt<4>(0ha))
node _r_c_cat_T_8 = eq(s2_req.cmd, UInt<4>(0hb))
node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6)
node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7)
node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8)
node _r_c_cat_T_12 = eq(s2_req.cmd, UInt<4>(0h8))
node _r_c_cat_T_13 = eq(s2_req.cmd, UInt<4>(0hc))
node _r_c_cat_T_14 = eq(s2_req.cmd, UInt<4>(0hd))
node _r_c_cat_T_15 = eq(s2_req.cmd, UInt<4>(0he))
node _r_c_cat_T_16 = eq(s2_req.cmd, UInt<4>(0hf))
node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13)
node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14)
node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15)
node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16)
node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20)
node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21)
node _r_c_cat_T_23 = eq(s2_req.cmd, UInt<1>(0h1))
node _r_c_cat_T_24 = eq(s2_req.cmd, UInt<5>(0h11))
node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24)
node _r_c_cat_T_26 = eq(s2_req.cmd, UInt<3>(0h7))
node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26)
node _r_c_cat_T_28 = eq(s2_req.cmd, UInt<3>(0h4))
node _r_c_cat_T_29 = eq(s2_req.cmd, UInt<4>(0h9))
node _r_c_cat_T_30 = eq(s2_req.cmd, UInt<4>(0ha))
node _r_c_cat_T_31 = eq(s2_req.cmd, UInt<4>(0hb))
node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29)
node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30)
node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31)
node _r_c_cat_T_35 = eq(s2_req.cmd, UInt<4>(0h8))
node _r_c_cat_T_36 = eq(s2_req.cmd, UInt<4>(0hc))
node _r_c_cat_T_37 = eq(s2_req.cmd, UInt<4>(0hd))
node _r_c_cat_T_38 = eq(s2_req.cmd, UInt<4>(0he))
node _r_c_cat_T_39 = eq(s2_req.cmd, UInt<4>(0hf))
node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36)
node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37)
node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38)
node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39)
node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43)
node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44)
node _r_c_cat_T_46 = eq(s2_req.cmd, UInt<2>(0h3))
node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46)
node _r_c_cat_T_48 = eq(s2_req.cmd, UInt<3>(0h6))
node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48)
node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49)
node _r_T = cat(r_c, s2_hit_state.state)
node _r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_2 = cat(_r_T_1, UInt<2>(0h3))
node _r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_4 = cat(_r_T_3, UInt<2>(0h2))
node _r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_6 = cat(_r_T_5, UInt<2>(0h1))
node _r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_8 = cat(_r_T_7, UInt<2>(0h3))
node _r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_10 = cat(_r_T_9, UInt<2>(0h2))
node _r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_12 = cat(_r_T_11, UInt<2>(0h3))
node _r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_14 = cat(_r_T_13, UInt<2>(0h2))
node _r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_16 = cat(_r_T_15, UInt<2>(0h0))
node _r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_18 = cat(_r_T_17, UInt<2>(0h1))
node _r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_20 = cat(_r_T_19, UInt<2>(0h0))
node _r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_22 = cat(_r_T_21, UInt<2>(0h1))
node _r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_24 = cat(_r_T_23, UInt<2>(0h0))
node _r_T_25 = eq(_r_T_24, _r_T)
node _r_T_26 = mux(_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_27 = mux(_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_28 = eq(_r_T_22, _r_T)
node _r_T_29 = mux(_r_T_28, UInt<1>(0h0), _r_T_26)
node _r_T_30 = mux(_r_T_28, UInt<2>(0h2), _r_T_27)
node _r_T_31 = eq(_r_T_20, _r_T)
node _r_T_32 = mux(_r_T_31, UInt<1>(0h0), _r_T_29)
node _r_T_33 = mux(_r_T_31, UInt<2>(0h1), _r_T_30)
node _r_T_34 = eq(_r_T_18, _r_T)
node _r_T_35 = mux(_r_T_34, UInt<1>(0h0), _r_T_32)
node _r_T_36 = mux(_r_T_34, UInt<2>(0h2), _r_T_33)
node _r_T_37 = eq(_r_T_16, _r_T)
node _r_T_38 = mux(_r_T_37, UInt<1>(0h0), _r_T_35)
node _r_T_39 = mux(_r_T_37, UInt<2>(0h0), _r_T_36)
node _r_T_40 = eq(_r_T_14, _r_T)
node _r_T_41 = mux(_r_T_40, UInt<1>(0h1), _r_T_38)
node _r_T_42 = mux(_r_T_40, UInt<2>(0h3), _r_T_39)
node _r_T_43 = eq(_r_T_12, _r_T)
node _r_T_44 = mux(_r_T_43, UInt<1>(0h1), _r_T_41)
node _r_T_45 = mux(_r_T_43, UInt<2>(0h3), _r_T_42)
node _r_T_46 = eq(_r_T_10, _r_T)
node _r_T_47 = mux(_r_T_46, UInt<1>(0h1), _r_T_44)
node _r_T_48 = mux(_r_T_46, UInt<2>(0h2), _r_T_45)
node _r_T_49 = eq(_r_T_8, _r_T)
node _r_T_50 = mux(_r_T_49, UInt<1>(0h1), _r_T_47)
node _r_T_51 = mux(_r_T_49, UInt<2>(0h3), _r_T_48)
node _r_T_52 = eq(_r_T_6, _r_T)
node _r_T_53 = mux(_r_T_52, UInt<1>(0h1), _r_T_50)
node _r_T_54 = mux(_r_T_52, UInt<2>(0h1), _r_T_51)
node _r_T_55 = eq(_r_T_4, _r_T)
node _r_T_56 = mux(_r_T_55, UInt<1>(0h1), _r_T_53)
node _r_T_57 = mux(_r_T_55, UInt<2>(0h2), _r_T_54)
node _r_T_58 = eq(_r_T_2, _r_T)
node s2_hit = mux(_r_T_58, UInt<1>(0h1), _r_T_56)
node s2_grow_param = mux(_r_T_58, UInt<2>(0h3), _r_T_57)
wire s2_new_hit_state : { state : UInt<2>}
connect s2_new_hit_state.state, s2_grow_param
node _T_31 = bits(s2_data, 7, 0)
node _T_32 = bits(s2_data, 15, 8)
node _T_33 = bits(s2_data, 23, 16)
node _T_34 = bits(s2_data, 31, 24)
node _T_35 = bits(s2_data, 39, 32)
node _T_36 = bits(s2_data, 47, 40)
node _T_37 = bits(s2_data, 55, 48)
node _T_38 = bits(s2_data, 63, 56)
node _s2_data_error_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_1 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_2 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_3 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_4 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_5 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_6 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_7 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_8 = or(_s2_data_error_T, _s2_data_error_T_1)
node _s2_data_error_T_9 = or(_s2_data_error_T_8, _s2_data_error_T_2)
node _s2_data_error_T_10 = or(_s2_data_error_T_9, _s2_data_error_T_3)
node _s2_data_error_T_11 = or(_s2_data_error_T_10, _s2_data_error_T_4)
node _s2_data_error_T_12 = or(_s2_data_error_T_11, _s2_data_error_T_5)
node _s2_data_error_T_13 = or(_s2_data_error_T_12, _s2_data_error_T_6)
node s2_data_error = or(_s2_data_error_T_13, _s2_data_error_T_7)
node _s2_data_error_uncorrectable_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_uncorrectable_T_1 = or(_s2_data_error_uncorrectable_T, UInt<1>(0h0))
node _s2_data_error_uncorrectable_T_2 = or(_s2_data_error_uncorrectable_T_1, UInt<1>(0h0))
node _s2_data_error_uncorrectable_T_3 = or(_s2_data_error_uncorrectable_T_2, UInt<1>(0h0))
node _s2_data_error_uncorrectable_T_4 = or(_s2_data_error_uncorrectable_T_3, UInt<1>(0h0))
node _s2_data_error_uncorrectable_T_5 = or(_s2_data_error_uncorrectable_T_4, UInt<1>(0h0))
node s2_data_error_uncorrectable = or(_s2_data_error_uncorrectable_T_5, UInt<1>(0h0))
node s2_data_corrected_lo_lo = cat(_T_32, _T_31)
node s2_data_corrected_lo_hi = cat(_T_34, _T_33)
node s2_data_corrected_lo = cat(s2_data_corrected_lo_hi, s2_data_corrected_lo_lo)
node s2_data_corrected_hi_lo = cat(_T_36, _T_35)
node s2_data_corrected_hi_hi = cat(_T_38, _T_37)
node s2_data_corrected_hi = cat(s2_data_corrected_hi_hi, s2_data_corrected_hi_lo)
node s2_data_corrected = cat(s2_data_corrected_hi, s2_data_corrected_lo)
node s2_data_uncorrected_lo_lo = cat(_T_32, _T_31)
node s2_data_uncorrected_lo_hi = cat(_T_34, _T_33)
node s2_data_uncorrected_lo = cat(s2_data_uncorrected_lo_hi, s2_data_uncorrected_lo_lo)
node s2_data_uncorrected_hi_lo = cat(_T_36, _T_35)
node s2_data_uncorrected_hi_hi = cat(_T_38, _T_37)
node s2_data_uncorrected_hi = cat(s2_data_uncorrected_hi_hi, s2_data_uncorrected_hi_lo)
node s2_data_uncorrected = cat(s2_data_uncorrected_hi, s2_data_uncorrected_lo)
node _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T = eq(s2_meta_error, UInt<1>(0h0))
node _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 = and(s2_valid_masked, _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T)
node s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = and(_s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1, s2_hit)
node _s2_valid_hit_pre_data_ecc_and_waw_T = and(s2_valid_hit_maybe_flush_pre_data_ecc_and_waw, s2_readwrite)
node _s2_valid_hit_pre_data_ecc_and_waw_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node s2_valid_hit_pre_data_ecc_and_waw = and(_s2_valid_hit_pre_data_ecc_and_waw_T, _s2_valid_hit_pre_data_ecc_and_waw_T_1)
node s2_valid_flush_line = and(s2_valid_hit_maybe_flush_pre_data_ecc_and_waw, s2_cmd_flush_line)
node _s2_valid_hit_pre_data_ecc_T = eq(s2_waw_hazard, UInt<1>(0h0))
node _s2_valid_hit_pre_data_ecc_T_1 = or(_s2_valid_hit_pre_data_ecc_T, s2_store_merge)
node s2_valid_hit_pre_data_ecc = and(s2_valid_hit_pre_data_ecc_and_waw, _s2_valid_hit_pre_data_ecc_T_1)
node s2_valid_data_error = and(s2_valid_hit_pre_data_ecc_and_waw, s2_data_error)
node _s2_valid_hit_T = eq(s2_data_error, UInt<1>(0h0))
node s2_valid_hit = and(s2_valid_hit_pre_data_ecc, _s2_valid_hit_T)
node _s2_valid_miss_T = and(s2_valid_masked, s2_readwrite)
node _s2_valid_miss_T_1 = eq(s2_meta_error, UInt<1>(0h0))
node _s2_valid_miss_T_2 = and(_s2_valid_miss_T, _s2_valid_miss_T_1)
node _s2_valid_miss_T_3 = eq(s2_hit, UInt<1>(0h0))
node s2_valid_miss = and(_s2_valid_miss_T_2, _s2_valid_miss_T_3)
node _s2_uncached_T = eq(s2_pma.cacheable, UInt<1>(0h0))
node _s2_uncached_T_1 = eq(s2_pma.must_alloc, UInt<1>(0h0))
node _s2_uncached_T_2 = and(s2_req.no_alloc, _s2_uncached_T_1)
node _s2_uncached_T_3 = eq(s2_hit_valid, UInt<1>(0h0))
node _s2_uncached_T_4 = and(_s2_uncached_T_2, _s2_uncached_T_3)
node s2_uncached = or(_s2_uncached_T, _s2_uncached_T_4)
node _s2_valid_cached_miss_T = eq(s2_uncached, UInt<1>(0h0))
node _s2_valid_cached_miss_T_1 = and(s2_valid_miss, _s2_valid_cached_miss_T)
node _s2_valid_cached_miss_T_2 = orr(uncachedInFlight[0])
node _s2_valid_cached_miss_T_3 = eq(_s2_valid_cached_miss_T_2, UInt<1>(0h0))
node s2_valid_cached_miss = and(_s2_valid_cached_miss_T_1, _s2_valid_cached_miss_T_3)
node _s2_want_victimize_T = or(s2_valid_cached_miss, s2_valid_flush_line)
node _s2_want_victimize_T_1 = or(_s2_want_victimize_T, s2_valid_data_error)
node _s2_want_victimize_T_2 = or(_s2_want_victimize_T_1, s2_flush_valid)
node s2_want_victimize = and(UInt<1>(0h1), _s2_want_victimize_T_2)
node _s2_cannot_victimize_T = eq(s2_flush_valid, UInt<1>(0h0))
node s2_cannot_victimize = and(_s2_cannot_victimize_T, io.cpu.s2_kill)
node _s2_victimize_T = eq(s2_cannot_victimize, UInt<1>(0h0))
node s2_victimize = and(s2_want_victimize, _s2_victimize_T)
node _s2_valid_uncached_pending_T = and(s2_valid_miss, s2_uncached)
node _s2_valid_uncached_pending_T_1 = andr(uncachedInFlight[0])
node _s2_valid_uncached_pending_T_2 = eq(_s2_valid_uncached_pending_T_1, UInt<1>(0h0))
node s2_valid_uncached_pending = and(_s2_valid_uncached_pending_T, _s2_valid_uncached_pending_T_2)
node _s2_victim_way_T = or(s1_valid_not_nacked, s1_flush_valid)
reg s2_victim_way_r : UInt, clock
when _s2_victim_way_T :
connect s2_victim_way_r, s1_victim_way
node s2_victim_way = dshl(UInt<1>(0h1), s2_victim_way_r)
node s2_victim_or_hit_way = mux(s2_hit_valid, s2_hit_way, s2_victim_way)
node _s2_victim_tag_T = or(s2_valid_data_error, s2_valid_flush_line)
node _s2_victim_tag_T_1 = bits(s2_req.addr, 31, 8)
node _s2_victim_tag_T_2 = bits(s2_victim_way, 0, 0)
node _s2_victim_tag_T_3 = bits(s2_victim_way, 1, 1)
node _s2_victim_tag_T_4 = bits(s2_victim_way, 2, 2)
node _s2_victim_tag_T_5 = bits(s2_victim_way, 3, 3)
wire _s2_victim_tag_WIRE : { coh : { state : UInt<2>}, tag : UInt<24>}
node _s2_victim_tag_T_6 = mux(_s2_victim_tag_T_2, s2_meta_corrected_0.tag, UInt<1>(0h0))
node _s2_victim_tag_T_7 = mux(_s2_victim_tag_T_3, s2_meta_corrected_1.tag, UInt<1>(0h0))
node _s2_victim_tag_T_8 = mux(_s2_victim_tag_T_4, s2_meta_corrected_2.tag, UInt<1>(0h0))
node _s2_victim_tag_T_9 = mux(_s2_victim_tag_T_5, s2_meta_corrected_3.tag, UInt<1>(0h0))
node _s2_victim_tag_T_10 = or(_s2_victim_tag_T_6, _s2_victim_tag_T_7)
node _s2_victim_tag_T_11 = or(_s2_victim_tag_T_10, _s2_victim_tag_T_8)
node _s2_victim_tag_T_12 = or(_s2_victim_tag_T_11, _s2_victim_tag_T_9)
wire _s2_victim_tag_WIRE_1 : UInt<24>
connect _s2_victim_tag_WIRE_1, _s2_victim_tag_T_12
connect _s2_victim_tag_WIRE.tag, _s2_victim_tag_WIRE_1
wire _s2_victim_tag_WIRE_2 : { state : UInt<2>}
node _s2_victim_tag_T_13 = mux(_s2_victim_tag_T_2, s2_meta_corrected_0.coh.state, UInt<1>(0h0))
node _s2_victim_tag_T_14 = mux(_s2_victim_tag_T_3, s2_meta_corrected_1.coh.state, UInt<1>(0h0))
node _s2_victim_tag_T_15 = mux(_s2_victim_tag_T_4, s2_meta_corrected_2.coh.state, UInt<1>(0h0))
node _s2_victim_tag_T_16 = mux(_s2_victim_tag_T_5, s2_meta_corrected_3.coh.state, UInt<1>(0h0))
node _s2_victim_tag_T_17 = or(_s2_victim_tag_T_13, _s2_victim_tag_T_14)
node _s2_victim_tag_T_18 = or(_s2_victim_tag_T_17, _s2_victim_tag_T_15)
node _s2_victim_tag_T_19 = or(_s2_victim_tag_T_18, _s2_victim_tag_T_16)
wire _s2_victim_tag_WIRE_3 : UInt<2>
connect _s2_victim_tag_WIRE_3, _s2_victim_tag_T_19
connect _s2_victim_tag_WIRE_2.state, _s2_victim_tag_WIRE_3
connect _s2_victim_tag_WIRE.coh, _s2_victim_tag_WIRE_2
node s2_victim_tag = mux(_s2_victim_tag_T, _s2_victim_tag_T_1, _s2_victim_tag_WIRE.tag)
node _s2_victim_state_T = bits(s2_victim_way, 0, 0)
node _s2_victim_state_T_1 = bits(s2_victim_way, 1, 1)
node _s2_victim_state_T_2 = bits(s2_victim_way, 2, 2)
node _s2_victim_state_T_3 = bits(s2_victim_way, 3, 3)
wire _s2_victim_state_WIRE : { coh : { state : UInt<2>}, tag : UInt<24>}
node _s2_victim_state_T_4 = mux(_s2_victim_state_T, s2_meta_corrected_0.tag, UInt<1>(0h0))
node _s2_victim_state_T_5 = mux(_s2_victim_state_T_1, s2_meta_corrected_1.tag, UInt<1>(0h0))
node _s2_victim_state_T_6 = mux(_s2_victim_state_T_2, s2_meta_corrected_2.tag, UInt<1>(0h0))
node _s2_victim_state_T_7 = mux(_s2_victim_state_T_3, s2_meta_corrected_3.tag, UInt<1>(0h0))
node _s2_victim_state_T_8 = or(_s2_victim_state_T_4, _s2_victim_state_T_5)
node _s2_victim_state_T_9 = or(_s2_victim_state_T_8, _s2_victim_state_T_6)
node _s2_victim_state_T_10 = or(_s2_victim_state_T_9, _s2_victim_state_T_7)
wire _s2_victim_state_WIRE_1 : UInt<24>
connect _s2_victim_state_WIRE_1, _s2_victim_state_T_10
connect _s2_victim_state_WIRE.tag, _s2_victim_state_WIRE_1
wire _s2_victim_state_WIRE_2 : { state : UInt<2>}
node _s2_victim_state_T_11 = mux(_s2_victim_state_T, s2_meta_corrected_0.coh.state, UInt<1>(0h0))
node _s2_victim_state_T_12 = mux(_s2_victim_state_T_1, s2_meta_corrected_1.coh.state, UInt<1>(0h0))
node _s2_victim_state_T_13 = mux(_s2_victim_state_T_2, s2_meta_corrected_2.coh.state, UInt<1>(0h0))
node _s2_victim_state_T_14 = mux(_s2_victim_state_T_3, s2_meta_corrected_3.coh.state, UInt<1>(0h0))
node _s2_victim_state_T_15 = or(_s2_victim_state_T_11, _s2_victim_state_T_12)
node _s2_victim_state_T_16 = or(_s2_victim_state_T_15, _s2_victim_state_T_13)
node _s2_victim_state_T_17 = or(_s2_victim_state_T_16, _s2_victim_state_T_14)
wire _s2_victim_state_WIRE_3 : UInt<2>
connect _s2_victim_state_WIRE_3, _s2_victim_state_T_17
connect _s2_victim_state_WIRE_2.state, _s2_victim_state_WIRE_3
connect _s2_victim_state_WIRE.coh, _s2_victim_state_WIRE_2
node s2_victim_state = mux(s2_hit_valid, s2_hit_state, _s2_victim_state_WIRE.coh)
node _r_T_59 = cat(probe_bits.param, s2_probe_state.state)
node _r_T_60 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _r_T_61 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _r_T_62 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _r_T_63 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _r_T_64 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _r_T_65 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _r_T_66 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _r_T_67 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _r_T_68 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _r_T_69 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _r_T_70 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _r_T_71 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _r_T_72 = eq(_r_T_71, _r_T_59)
node _r_T_73 = mux(_r_T_72, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_74 = mux(_r_T_72, UInt<3>(0h5), UInt<1>(0h0))
node _r_T_75 = mux(_r_T_72, UInt<2>(0h0), UInt<1>(0h0))
node _r_T_76 = eq(_r_T_70, _r_T_59)
node _r_T_77 = mux(_r_T_76, UInt<1>(0h0), _r_T_73)
node _r_T_78 = mux(_r_T_76, UInt<3>(0h2), _r_T_74)
node _r_T_79 = mux(_r_T_76, UInt<2>(0h0), _r_T_75)
node _r_T_80 = eq(_r_T_69, _r_T_59)
node _r_T_81 = mux(_r_T_80, UInt<1>(0h0), _r_T_77)
node _r_T_82 = mux(_r_T_80, UInt<3>(0h1), _r_T_78)
node _r_T_83 = mux(_r_T_80, UInt<2>(0h0), _r_T_79)
node _r_T_84 = eq(_r_T_68, _r_T_59)
node _r_T_85 = mux(_r_T_84, UInt<1>(0h1), _r_T_81)
node _r_T_86 = mux(_r_T_84, UInt<3>(0h1), _r_T_82)
node _r_T_87 = mux(_r_T_84, UInt<2>(0h0), _r_T_83)
node _r_T_88 = eq(_r_T_67, _r_T_59)
node _r_T_89 = mux(_r_T_88, UInt<1>(0h0), _r_T_85)
node _r_T_90 = mux(_r_T_88, UInt<3>(0h5), _r_T_86)
node _r_T_91 = mux(_r_T_88, UInt<2>(0h0), _r_T_87)
node _r_T_92 = eq(_r_T_66, _r_T_59)
node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_89)
node _r_T_94 = mux(_r_T_92, UInt<3>(0h4), _r_T_90)
node _r_T_95 = mux(_r_T_92, UInt<2>(0h1), _r_T_91)
node _r_T_96 = eq(_r_T_65, _r_T_59)
node _r_T_97 = mux(_r_T_96, UInt<1>(0h0), _r_T_93)
node _r_T_98 = mux(_r_T_96, UInt<3>(0h0), _r_T_94)
node _r_T_99 = mux(_r_T_96, UInt<2>(0h1), _r_T_95)
node _r_T_100 = eq(_r_T_64, _r_T_59)
node _r_T_101 = mux(_r_T_100, UInt<1>(0h1), _r_T_97)
node _r_T_102 = mux(_r_T_100, UInt<3>(0h0), _r_T_98)
node _r_T_103 = mux(_r_T_100, UInt<2>(0h1), _r_T_99)
node _r_T_104 = eq(_r_T_63, _r_T_59)
node _r_T_105 = mux(_r_T_104, UInt<1>(0h0), _r_T_101)
node _r_T_106 = mux(_r_T_104, UInt<3>(0h5), _r_T_102)
node _r_T_107 = mux(_r_T_104, UInt<2>(0h0), _r_T_103)
node _r_T_108 = eq(_r_T_62, _r_T_59)
node _r_T_109 = mux(_r_T_108, UInt<1>(0h0), _r_T_105)
node _r_T_110 = mux(_r_T_108, UInt<3>(0h4), _r_T_106)
node _r_T_111 = mux(_r_T_108, UInt<2>(0h1), _r_T_107)
node _r_T_112 = eq(_r_T_61, _r_T_59)
node _r_T_113 = mux(_r_T_112, UInt<1>(0h0), _r_T_109)
node _r_T_114 = mux(_r_T_112, UInt<3>(0h3), _r_T_110)
node _r_T_115 = mux(_r_T_112, UInt<2>(0h2), _r_T_111)
node _r_T_116 = eq(_r_T_60, _r_T_59)
node s2_prb_ack_data = mux(_r_T_116, UInt<1>(0h1), _r_T_113)
node s2_report_param = mux(_r_T_116, UInt<3>(0h3), _r_T_114)
node r_3 = mux(_r_T_116, UInt<2>(0h2), _r_T_115)
wire probeNewCoh : { state : UInt<2>}
connect probeNewCoh.state, r_3
node _r_T_117 = eq(UInt<5>(0h10), UInt<5>(0h10))
node _r_T_118 = mux(_r_T_117, UInt<2>(0h2), UInt<2>(0h2))
node _r_T_119 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _r_T_120 = mux(_r_T_119, UInt<2>(0h1), _r_T_118)
node _r_T_121 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _r_T_122 = mux(_r_T_121, UInt<2>(0h0), _r_T_120)
node _r_T_123 = cat(_r_T_122, s2_victim_state.state)
node _r_T_124 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _r_T_125 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _r_T_126 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _r_T_127 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _r_T_128 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _r_T_129 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _r_T_130 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _r_T_131 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _r_T_132 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _r_T_133 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _r_T_134 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _r_T_135 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _r_T_136 = eq(_r_T_135, _r_T_123)
node _r_T_137 = mux(_r_T_136, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_138 = mux(_r_T_136, UInt<3>(0h5), UInt<1>(0h0))
node _r_T_139 = mux(_r_T_136, UInt<2>(0h0), UInt<1>(0h0))
node _r_T_140 = eq(_r_T_134, _r_T_123)
node _r_T_141 = mux(_r_T_140, UInt<1>(0h0), _r_T_137)
node _r_T_142 = mux(_r_T_140, UInt<3>(0h2), _r_T_138)
node _r_T_143 = mux(_r_T_140, UInt<2>(0h0), _r_T_139)
node _r_T_144 = eq(_r_T_133, _r_T_123)
node _r_T_145 = mux(_r_T_144, UInt<1>(0h0), _r_T_141)
node _r_T_146 = mux(_r_T_144, UInt<3>(0h1), _r_T_142)
node _r_T_147 = mux(_r_T_144, UInt<2>(0h0), _r_T_143)
node _r_T_148 = eq(_r_T_132, _r_T_123)
node _r_T_149 = mux(_r_T_148, UInt<1>(0h1), _r_T_145)
node _r_T_150 = mux(_r_T_148, UInt<3>(0h1), _r_T_146)
node _r_T_151 = mux(_r_T_148, UInt<2>(0h0), _r_T_147)
node _r_T_152 = eq(_r_T_131, _r_T_123)
node _r_T_153 = mux(_r_T_152, UInt<1>(0h0), _r_T_149)
node _r_T_154 = mux(_r_T_152, UInt<3>(0h5), _r_T_150)
node _r_T_155 = mux(_r_T_152, UInt<2>(0h0), _r_T_151)
node _r_T_156 = eq(_r_T_130, _r_T_123)
node _r_T_157 = mux(_r_T_156, UInt<1>(0h0), _r_T_153)
node _r_T_158 = mux(_r_T_156, UInt<3>(0h4), _r_T_154)
node _r_T_159 = mux(_r_T_156, UInt<2>(0h1), _r_T_155)
node _r_T_160 = eq(_r_T_129, _r_T_123)
node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_157)
node _r_T_162 = mux(_r_T_160, UInt<3>(0h0), _r_T_158)
node _r_T_163 = mux(_r_T_160, UInt<2>(0h1), _r_T_159)
node _r_T_164 = eq(_r_T_128, _r_T_123)
node _r_T_165 = mux(_r_T_164, UInt<1>(0h1), _r_T_161)
node _r_T_166 = mux(_r_T_164, UInt<3>(0h0), _r_T_162)
node _r_T_167 = mux(_r_T_164, UInt<2>(0h1), _r_T_163)
node _r_T_168 = eq(_r_T_127, _r_T_123)
node _r_T_169 = mux(_r_T_168, UInt<1>(0h0), _r_T_165)
node _r_T_170 = mux(_r_T_168, UInt<3>(0h5), _r_T_166)
node _r_T_171 = mux(_r_T_168, UInt<2>(0h0), _r_T_167)
node _r_T_172 = eq(_r_T_126, _r_T_123)
node _r_T_173 = mux(_r_T_172, UInt<1>(0h0), _r_T_169)
node _r_T_174 = mux(_r_T_172, UInt<3>(0h4), _r_T_170)
node _r_T_175 = mux(_r_T_172, UInt<2>(0h1), _r_T_171)
node _r_T_176 = eq(_r_T_125, _r_T_123)
node _r_T_177 = mux(_r_T_176, UInt<1>(0h0), _r_T_173)
node _r_T_178 = mux(_r_T_176, UInt<3>(0h3), _r_T_174)
node _r_T_179 = mux(_r_T_176, UInt<2>(0h2), _r_T_175)
node _r_T_180 = eq(_r_T_124, _r_T_123)
node s2_victim_dirty = mux(_r_T_180, UInt<1>(0h1), _r_T_177)
node s2_shrink_param = mux(_r_T_180, UInt<3>(0h3), _r_T_178)
node r_3_1 = mux(_r_T_180, UInt<2>(0h2), _r_T_179)
wire voluntaryNewCoh : { state : UInt<2>}
connect voluntaryNewCoh.state, r_3_1
node _s2_update_meta_T = eq(s2_hit_state.state, s2_new_hit_state.state)
node s2_update_meta = eq(_s2_update_meta_T, UInt<1>(0h0))
node s2_dont_nack_uncached = and(s2_valid_uncached_pending, tl_out_a.ready)
node _s2_dont_nack_misc_T = eq(s2_meta_error, UInt<1>(0h0))
node _s2_dont_nack_misc_T_1 = and(s2_valid_masked, _s2_dont_nack_misc_T)
node _s2_dont_nack_misc_T_2 = and(UInt<1>(0h0), s2_cmd_flush_all)
node _s2_dont_nack_misc_T_3 = and(_s2_dont_nack_misc_T_2, flushed)
node _s2_dont_nack_misc_T_4 = eq(flushing, UInt<1>(0h0))
node _s2_dont_nack_misc_T_5 = and(_s2_dont_nack_misc_T_3, _s2_dont_nack_misc_T_4)
node _s2_dont_nack_misc_T_6 = and(UInt<1>(0h0), s2_cmd_flush_line)
node _s2_dont_nack_misc_T_7 = eq(s2_hit, UInt<1>(0h0))
node _s2_dont_nack_misc_T_8 = and(_s2_dont_nack_misc_T_6, _s2_dont_nack_misc_T_7)
node _s2_dont_nack_misc_T_9 = or(_s2_dont_nack_misc_T_5, _s2_dont_nack_misc_T_8)
node _s2_dont_nack_misc_T_10 = eq(s2_req.cmd, UInt<5>(0h17))
node _s2_dont_nack_misc_T_11 = or(_s2_dont_nack_misc_T_9, _s2_dont_nack_misc_T_10)
node s2_dont_nack_misc = and(_s2_dont_nack_misc_T_1, _s2_dont_nack_misc_T_11)
node _io_cpu_s2_nack_T = eq(s2_dont_nack_uncached, UInt<1>(0h0))
node _io_cpu_s2_nack_T_1 = and(s2_valid_no_xcpt, _io_cpu_s2_nack_T)
node _io_cpu_s2_nack_T_2 = eq(s2_dont_nack_misc, UInt<1>(0h0))
node _io_cpu_s2_nack_T_3 = and(_io_cpu_s2_nack_T_1, _io_cpu_s2_nack_T_2)
node _io_cpu_s2_nack_T_4 = eq(s2_valid_hit, UInt<1>(0h0))
node _io_cpu_s2_nack_T_5 = and(_io_cpu_s2_nack_T_3, _io_cpu_s2_nack_T_4)
connect io.cpu.s2_nack, _io_cpu_s2_nack_T_5
node _T_39 = and(s2_valid_hit_pre_data_ecc_and_waw, s2_update_meta)
node _T_40 = or(io.cpu.s2_nack, _T_39)
when _T_40 :
connect s1_nack, UInt<1>(0h1)
node _s2_first_meta_corrected_T = bits(s2_meta_correctable_errors, 0, 0)
node _s2_first_meta_corrected_T_1 = bits(s2_meta_correctable_errors, 1, 1)
node _s2_first_meta_corrected_T_2 = bits(s2_meta_correctable_errors, 2, 2)
node _s2_first_meta_corrected_T_3 = bits(s2_meta_correctable_errors, 3, 3)
node _s2_first_meta_corrected_T_4 = mux(_s2_first_meta_corrected_T_2, s2_meta_corrected_2, s2_meta_corrected_3)
node _s2_first_meta_corrected_T_5 = mux(_s2_first_meta_corrected_T_1, s2_meta_corrected_1, _s2_first_meta_corrected_T_4)
node s2_first_meta_corrected = mux(_s2_first_meta_corrected_T, s2_meta_corrected_0, _s2_first_meta_corrected_T_5)
node _metaArb_io_in_1_valid_T = or(s2_valid_masked, s2_flush_valid_pre_tag_ecc)
node _metaArb_io_in_1_valid_T_1 = or(_metaArb_io_in_1_valid_T, s2_probe)
node _metaArb_io_in_1_valid_T_2 = and(s2_meta_error, _metaArb_io_in_1_valid_T_1)
connect metaArb.io.in[1].valid, _metaArb_io_in_1_valid_T_2
connect metaArb.io.in[1].bits.write, UInt<1>(0h1)
node _metaArb_io_in_1_bits_way_en_T = bits(s2_meta_correctable_errors, 0, 0)
node _metaArb_io_in_1_bits_way_en_T_1 = bits(s2_meta_correctable_errors, 1, 1)
node _metaArb_io_in_1_bits_way_en_T_2 = bits(s2_meta_correctable_errors, 2, 2)
node _metaArb_io_in_1_bits_way_en_T_3 = bits(s2_meta_correctable_errors, 3, 3)
node _metaArb_io_in_1_bits_way_en_T_4 = mux(_metaArb_io_in_1_bits_way_en_T_3, UInt<4>(0h8), UInt<4>(0h0))
node _metaArb_io_in_1_bits_way_en_T_5 = mux(_metaArb_io_in_1_bits_way_en_T_2, UInt<4>(0h4), _metaArb_io_in_1_bits_way_en_T_4)
node _metaArb_io_in_1_bits_way_en_T_6 = mux(_metaArb_io_in_1_bits_way_en_T_1, UInt<4>(0h2), _metaArb_io_in_1_bits_way_en_T_5)
node _metaArb_io_in_1_bits_way_en_T_7 = mux(_metaArb_io_in_1_bits_way_en_T, UInt<4>(0h1), _metaArb_io_in_1_bits_way_en_T_6)
node _metaArb_io_in_1_bits_way_en_T_8 = mux(s2_meta_error_uncorrectable, UInt<1>(0h0), _metaArb_io_in_1_bits_way_en_T_7)
node _metaArb_io_in_1_bits_way_en_T_9 = or(s2_meta_uncorrectable_errors, _metaArb_io_in_1_bits_way_en_T_8)
connect metaArb.io.in[1].bits.way_en, _metaArb_io_in_1_bits_way_en_T_9
node _metaArb_io_in_1_bits_idx_T = bits(probe_bits.address, 7, 6)
node _metaArb_io_in_1_bits_idx_T_1 = bits(s2_vaddr, 7, 6)
node _metaArb_io_in_1_bits_idx_T_2 = mux(s2_probe, _metaArb_io_in_1_bits_idx_T, _metaArb_io_in_1_bits_idx_T_1)
connect metaArb.io.in[1].bits.idx, _metaArb_io_in_1_bits_idx_T_2
node _metaArb_io_in_1_bits_addr_T = shr(io.cpu.req.bits.addr, 8)
node _metaArb_io_in_1_bits_addr_T_1 = shl(metaArb.io.in[1].bits.idx, 6)
node _metaArb_io_in_1_bits_addr_T_2 = cat(_metaArb_io_in_1_bits_addr_T, _metaArb_io_in_1_bits_addr_T_1)
connect metaArb.io.in[1].bits.addr, _metaArb_io_in_1_bits_addr_T_2
wire metaArb_io_in_1_bits_data_new_meta : { coh : { state : UInt<2>}, tag : UInt<24>}
connect metaArb_io_in_1_bits_data_new_meta, s2_first_meta_corrected
when s2_meta_error_uncorrectable :
wire metaArb_io_in_1_bits_data_new_meta_coh_meta : { state : UInt<2>}
connect metaArb_io_in_1_bits_data_new_meta_coh_meta.state, UInt<2>(0h0)
connect metaArb_io_in_1_bits_data_new_meta.coh, metaArb_io_in_1_bits_data_new_meta_coh_meta
node _metaArb_io_in_1_bits_data_T = cat(metaArb_io_in_1_bits_data_new_meta.coh.state, metaArb_io_in_1_bits_data_new_meta.tag)
connect metaArb.io.in[1].bits.data, _metaArb_io_in_1_bits_data_T
node _metaArb_io_in_2_valid_T = and(s2_valid_hit_pre_data_ecc_and_waw, s2_update_meta)
connect metaArb.io.in[2].valid, _metaArb_io_in_2_valid_T
node _metaArb_io_in_2_bits_write_T = eq(io.cpu.s2_kill, UInt<1>(0h0))
connect metaArb.io.in[2].bits.write, _metaArb_io_in_2_bits_write_T
connect metaArb.io.in[2].bits.way_en, s2_victim_or_hit_way
node _metaArb_io_in_2_bits_idx_T = bits(s2_vaddr, 7, 6)
connect metaArb.io.in[2].bits.idx, _metaArb_io_in_2_bits_idx_T
node _metaArb_io_in_2_bits_addr_T = shr(io.cpu.req.bits.addr, 8)
node _metaArb_io_in_2_bits_addr_T_1 = bits(s2_vaddr, 7, 0)
node _metaArb_io_in_2_bits_addr_T_2 = cat(_metaArb_io_in_2_bits_addr_T, _metaArb_io_in_2_bits_addr_T_1)
connect metaArb.io.in[2].bits.addr, _metaArb_io_in_2_bits_addr_T_2
node _metaArb_io_in_2_bits_data_T = shr(s2_req.addr, 8)
wire metaArb_io_in_2_bits_data_meta : { coh : { state : UInt<2>}, tag : UInt<24>}
connect metaArb_io_in_2_bits_data_meta.tag, _metaArb_io_in_2_bits_data_T
connect metaArb_io_in_2_bits_data_meta.coh, s2_new_hit_state
node _metaArb_io_in_2_bits_data_T_1 = cat(metaArb_io_in_2_bits_data_meta.coh.state, metaArb_io_in_2_bits_data_meta.tag)
connect metaArb.io.in[2].bits.data, _metaArb_io_in_2_bits_data_T_1
node _s2_lr_T = eq(s2_req.cmd, UInt<3>(0h6))
node s2_lr = and(UInt<1>(0h0), _s2_lr_T)
node _s2_sc_T = eq(s2_req.cmd, UInt<3>(0h7))
node s2_sc = and(UInt<1>(0h0), _s2_sc_T)
regreset lrscCount : UInt, clock, reset, UInt<1>(0h0)
node lrscValid = gt(lrscCount, UInt<2>(0h3))
node _lrscBackingOff_T = gt(lrscCount, UInt<1>(0h0))
node _lrscBackingOff_T_1 = eq(lrscValid, UInt<1>(0h0))
node lrscBackingOff = and(_lrscBackingOff_T, _lrscBackingOff_T_1)
reg lrscAddr : UInt, clock
node _lrscAddrMatch_T = shr(s2_req.addr, 6)
node lrscAddrMatch = eq(lrscAddr, _lrscAddrMatch_T)
node _s2_sc_fail_T = and(lrscValid, lrscAddrMatch)
node _s2_sc_fail_T_1 = eq(_s2_sc_fail_T, UInt<1>(0h0))
node s2_sc_fail = and(s2_sc, _s2_sc_fail_T_1)
node _T_41 = and(s2_valid_hit, s2_lr)
node _T_42 = eq(cached_grant_wait, UInt<1>(0h0))
node _T_43 = and(_T_41, _T_42)
node _T_44 = or(_T_43, s2_valid_cached_miss)
node _T_45 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _T_46 = and(_T_44, _T_45)
when _T_46 :
node _lrscCount_T = mux(s2_hit, UInt<5>(0h13), UInt<1>(0h0))
connect lrscCount, _lrscCount_T
node _lrscAddr_T = shr(s2_req.addr, 6)
connect lrscAddr, _lrscAddr_T
node _T_47 = gt(lrscCount, UInt<1>(0h0))
when _T_47 :
node _lrscCount_T_1 = sub(lrscCount, UInt<1>(0h1))
node _lrscCount_T_2 = tail(_lrscCount_T_1, 1)
connect lrscCount, _lrscCount_T_2
node _T_48 = and(s2_valid_not_killed, lrscValid)
when _T_48 :
connect lrscCount, UInt<2>(0h3)
when s1_probe :
connect lrscCount, UInt<1>(0h0)
node _s2_correct_T = eq(any_pstore_valid, UInt<1>(0h0))
node _s2_correct_T_1 = and(s2_data_error, _s2_correct_T)
node _s2_correct_T_2 = or(any_pstore_valid, s2_valid)
reg s2_correct_REG : UInt<1>, clock
connect s2_correct_REG, _s2_correct_T_2
node _s2_correct_T_3 = eq(s2_correct_REG, UInt<1>(0h0))
node _s2_correct_T_4 = and(_s2_correct_T_1, _s2_correct_T_3)
node s2_correct = and(_s2_correct_T_4, UInt<1>(0h0))
node _s2_valid_correct_T = and(s2_valid_hit_pre_data_ecc_and_waw, s2_correct)
node _s2_valid_correct_T_1 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node s2_valid_correct = and(_s2_valid_correct_T, _s2_valid_correct_T_1)
node _pstore1_cmd_T = and(s1_valid_not_nacked, s1_write)
reg pstore1_cmd : UInt<5>, clock
when _pstore1_cmd_T :
connect pstore1_cmd, s1_req.cmd
node _pstore1_addr_T = and(s1_valid_not_nacked, s1_write)
reg pstore1_addr : UInt<40>, clock
when _pstore1_addr_T :
connect pstore1_addr, s1_vaddr
node _pstore1_data_T = and(s1_valid_not_nacked, s1_write)
reg pstore1_data : UInt<64>, clock
when _pstore1_data_T :
connect pstore1_data, io.cpu.s1_data.data
node _pstore1_way_T = and(s1_valid_not_nacked, s1_write)
reg pstore1_way : UInt<4>, clock
when _pstore1_way_T :
connect pstore1_way, s1_hit_way
node _pstore1_mask_T = and(s1_valid_not_nacked, s1_write)
reg pstore1_mask : UInt<8>, clock
when _pstore1_mask_T :
connect pstore1_mask, s1_mask
wire pstore1_storegen_data : UInt
connect pstore1_storegen_data, pstore1_data
node _pstore1_rmw_T = eq(s1_req.cmd, UInt<1>(0h0))
node _pstore1_rmw_T_1 = eq(s1_req.cmd, UInt<5>(0h10))
node _pstore1_rmw_T_2 = eq(s1_req.cmd, UInt<3>(0h6))
node _pstore1_rmw_T_3 = eq(s1_req.cmd, UInt<3>(0h7))
node _pstore1_rmw_T_4 = or(_pstore1_rmw_T, _pstore1_rmw_T_1)
node _pstore1_rmw_T_5 = or(_pstore1_rmw_T_4, _pstore1_rmw_T_2)
node _pstore1_rmw_T_6 = or(_pstore1_rmw_T_5, _pstore1_rmw_T_3)
node _pstore1_rmw_T_7 = eq(s1_req.cmd, UInt<3>(0h4))
node _pstore1_rmw_T_8 = eq(s1_req.cmd, UInt<4>(0h9))
node _pstore1_rmw_T_9 = eq(s1_req.cmd, UInt<4>(0ha))
node _pstore1_rmw_T_10 = eq(s1_req.cmd, UInt<4>(0hb))
node _pstore1_rmw_T_11 = or(_pstore1_rmw_T_7, _pstore1_rmw_T_8)
node _pstore1_rmw_T_12 = or(_pstore1_rmw_T_11, _pstore1_rmw_T_9)
node _pstore1_rmw_T_13 = or(_pstore1_rmw_T_12, _pstore1_rmw_T_10)
node _pstore1_rmw_T_14 = eq(s1_req.cmd, UInt<4>(0h8))
node _pstore1_rmw_T_15 = eq(s1_req.cmd, UInt<4>(0hc))
node _pstore1_rmw_T_16 = eq(s1_req.cmd, UInt<4>(0hd))
node _pstore1_rmw_T_17 = eq(s1_req.cmd, UInt<4>(0he))
node _pstore1_rmw_T_18 = eq(s1_req.cmd, UInt<4>(0hf))
node _pstore1_rmw_T_19 = or(_pstore1_rmw_T_14, _pstore1_rmw_T_15)
node _pstore1_rmw_T_20 = or(_pstore1_rmw_T_19, _pstore1_rmw_T_16)
node _pstore1_rmw_T_21 = or(_pstore1_rmw_T_20, _pstore1_rmw_T_17)
node _pstore1_rmw_T_22 = or(_pstore1_rmw_T_21, _pstore1_rmw_T_18)
node _pstore1_rmw_T_23 = or(_pstore1_rmw_T_13, _pstore1_rmw_T_22)
node _pstore1_rmw_T_24 = or(_pstore1_rmw_T_6, _pstore1_rmw_T_23)
node _pstore1_rmw_T_25 = eq(s1_req.cmd, UInt<1>(0h1))
node _pstore1_rmw_T_26 = eq(s1_req.cmd, UInt<5>(0h11))
node _pstore1_rmw_T_27 = or(_pstore1_rmw_T_25, _pstore1_rmw_T_26)
node _pstore1_rmw_T_28 = eq(s1_req.cmd, UInt<3>(0h7))
node _pstore1_rmw_T_29 = or(_pstore1_rmw_T_27, _pstore1_rmw_T_28)
node _pstore1_rmw_T_30 = eq(s1_req.cmd, UInt<3>(0h4))
node _pstore1_rmw_T_31 = eq(s1_req.cmd, UInt<4>(0h9))
node _pstore1_rmw_T_32 = eq(s1_req.cmd, UInt<4>(0ha))
node _pstore1_rmw_T_33 = eq(s1_req.cmd, UInt<4>(0hb))
node _pstore1_rmw_T_34 = or(_pstore1_rmw_T_30, _pstore1_rmw_T_31)
node _pstore1_rmw_T_35 = or(_pstore1_rmw_T_34, _pstore1_rmw_T_32)
node _pstore1_rmw_T_36 = or(_pstore1_rmw_T_35, _pstore1_rmw_T_33)
node _pstore1_rmw_T_37 = eq(s1_req.cmd, UInt<4>(0h8))
node _pstore1_rmw_T_38 = eq(s1_req.cmd, UInt<4>(0hc))
node _pstore1_rmw_T_39 = eq(s1_req.cmd, UInt<4>(0hd))
node _pstore1_rmw_T_40 = eq(s1_req.cmd, UInt<4>(0he))
node _pstore1_rmw_T_41 = eq(s1_req.cmd, UInt<4>(0hf))
node _pstore1_rmw_T_42 = or(_pstore1_rmw_T_37, _pstore1_rmw_T_38)
node _pstore1_rmw_T_43 = or(_pstore1_rmw_T_42, _pstore1_rmw_T_39)
node _pstore1_rmw_T_44 = or(_pstore1_rmw_T_43, _pstore1_rmw_T_40)
node _pstore1_rmw_T_45 = or(_pstore1_rmw_T_44, _pstore1_rmw_T_41)
node _pstore1_rmw_T_46 = or(_pstore1_rmw_T_36, _pstore1_rmw_T_45)
node _pstore1_rmw_T_47 = or(_pstore1_rmw_T_29, _pstore1_rmw_T_46)
node _pstore1_rmw_T_48 = eq(s1_req.cmd, UInt<5>(0h11))
node _pstore1_rmw_T_49 = lt(s1_req.size, UInt<1>(0h0))
node _pstore1_rmw_T_50 = or(_pstore1_rmw_T_48, _pstore1_rmw_T_49)
node _pstore1_rmw_T_51 = and(_pstore1_rmw_T_47, _pstore1_rmw_T_50)
node _pstore1_rmw_T_52 = or(_pstore1_rmw_T_24, _pstore1_rmw_T_51)
node _pstore1_rmw_T_53 = and(s1_valid_not_nacked, s1_write)
reg pstore1_rmw_r : UInt<1>, clock
when _pstore1_rmw_T_53 :
connect pstore1_rmw_r, _pstore1_rmw_T_52
node pstore1_rmw = and(UInt<1>(0h0), pstore1_rmw_r)
node _pstore1_merge_likely_T = and(s2_valid_not_nacked_in_s1, s2_write)
node pstore1_merge_likely = and(_pstore1_merge_likely_T, s2_store_merge)
node _pstore1_merge_T = and(s2_valid_hit, s2_write)
node _pstore1_merge_T_1 = eq(s2_sc_fail, UInt<1>(0h0))
node _pstore1_merge_T_2 = and(_pstore1_merge_T, _pstore1_merge_T_1)
node _pstore1_merge_T_3 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _pstore1_merge_T_4 = and(_pstore1_merge_T_2, _pstore1_merge_T_3)
node pstore1_merge = and(_pstore1_merge_T_4, s2_store_merge)
regreset pstore2_valid : UInt<1>, clock, reset, UInt<1>(0h0)
node _pstore_drain_opportunistic_res_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h1))
node _pstore_drain_opportunistic_res_T_1 = eq(io.cpu.req.bits.cmd, UInt<2>(0h3))
node _pstore_drain_opportunistic_res_T_2 = or(_pstore_drain_opportunistic_res_T, _pstore_drain_opportunistic_res_T_1)
node _pstore_drain_opportunistic_res_T_3 = eq(_pstore_drain_opportunistic_res_T_2, UInt<1>(0h0))
node _pstore_drain_opportunistic_res_T_4 = lt(io.cpu.req.bits.size, UInt<1>(0h0))
node pstore_drain_opportunistic_res = or(_pstore_drain_opportunistic_res_T_3, _pstore_drain_opportunistic_res_T_4)
node _pstore_drain_opportunistic_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h0))
node _pstore_drain_opportunistic_T_1 = eq(io.cpu.req.bits.cmd, UInt<5>(0h10))
node _pstore_drain_opportunistic_T_2 = eq(io.cpu.req.bits.cmd, UInt<3>(0h6))
node _pstore_drain_opportunistic_T_3 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _pstore_drain_opportunistic_T_4 = or(_pstore_drain_opportunistic_T, _pstore_drain_opportunistic_T_1)
node _pstore_drain_opportunistic_T_5 = or(_pstore_drain_opportunistic_T_4, _pstore_drain_opportunistic_T_2)
node _pstore_drain_opportunistic_T_6 = or(_pstore_drain_opportunistic_T_5, _pstore_drain_opportunistic_T_3)
node _pstore_drain_opportunistic_T_7 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _pstore_drain_opportunistic_T_8 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _pstore_drain_opportunistic_T_9 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _pstore_drain_opportunistic_T_10 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _pstore_drain_opportunistic_T_11 = or(_pstore_drain_opportunistic_T_7, _pstore_drain_opportunistic_T_8)
node _pstore_drain_opportunistic_T_12 = or(_pstore_drain_opportunistic_T_11, _pstore_drain_opportunistic_T_9)
node _pstore_drain_opportunistic_T_13 = or(_pstore_drain_opportunistic_T_12, _pstore_drain_opportunistic_T_10)
node _pstore_drain_opportunistic_T_14 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _pstore_drain_opportunistic_T_15 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _pstore_drain_opportunistic_T_16 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _pstore_drain_opportunistic_T_17 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _pstore_drain_opportunistic_T_18 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _pstore_drain_opportunistic_T_19 = or(_pstore_drain_opportunistic_T_14, _pstore_drain_opportunistic_T_15)
node _pstore_drain_opportunistic_T_20 = or(_pstore_drain_opportunistic_T_19, _pstore_drain_opportunistic_T_16)
node _pstore_drain_opportunistic_T_21 = or(_pstore_drain_opportunistic_T_20, _pstore_drain_opportunistic_T_17)
node _pstore_drain_opportunistic_T_22 = or(_pstore_drain_opportunistic_T_21, _pstore_drain_opportunistic_T_18)
node _pstore_drain_opportunistic_T_23 = or(_pstore_drain_opportunistic_T_13, _pstore_drain_opportunistic_T_22)
node _pstore_drain_opportunistic_T_24 = or(_pstore_drain_opportunistic_T_6, _pstore_drain_opportunistic_T_23)
node _pstore_drain_opportunistic_T_25 = eq(io.cpu.req.bits.cmd, UInt<1>(0h1))
node _pstore_drain_opportunistic_T_26 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _pstore_drain_opportunistic_T_27 = or(_pstore_drain_opportunistic_T_25, _pstore_drain_opportunistic_T_26)
node _pstore_drain_opportunistic_T_28 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _pstore_drain_opportunistic_T_29 = or(_pstore_drain_opportunistic_T_27, _pstore_drain_opportunistic_T_28)
node _pstore_drain_opportunistic_T_30 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _pstore_drain_opportunistic_T_31 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _pstore_drain_opportunistic_T_32 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _pstore_drain_opportunistic_T_33 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _pstore_drain_opportunistic_T_34 = or(_pstore_drain_opportunistic_T_30, _pstore_drain_opportunistic_T_31)
node _pstore_drain_opportunistic_T_35 = or(_pstore_drain_opportunistic_T_34, _pstore_drain_opportunistic_T_32)
node _pstore_drain_opportunistic_T_36 = or(_pstore_drain_opportunistic_T_35, _pstore_drain_opportunistic_T_33)
node _pstore_drain_opportunistic_T_37 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _pstore_drain_opportunistic_T_38 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _pstore_drain_opportunistic_T_39 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _pstore_drain_opportunistic_T_40 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _pstore_drain_opportunistic_T_41 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _pstore_drain_opportunistic_T_42 = or(_pstore_drain_opportunistic_T_37, _pstore_drain_opportunistic_T_38)
node _pstore_drain_opportunistic_T_43 = or(_pstore_drain_opportunistic_T_42, _pstore_drain_opportunistic_T_39)
node _pstore_drain_opportunistic_T_44 = or(_pstore_drain_opportunistic_T_43, _pstore_drain_opportunistic_T_40)
node _pstore_drain_opportunistic_T_45 = or(_pstore_drain_opportunistic_T_44, _pstore_drain_opportunistic_T_41)
node _pstore_drain_opportunistic_T_46 = or(_pstore_drain_opportunistic_T_36, _pstore_drain_opportunistic_T_45)
node _pstore_drain_opportunistic_T_47 = or(_pstore_drain_opportunistic_T_29, _pstore_drain_opportunistic_T_46)
node _pstore_drain_opportunistic_T_48 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _pstore_drain_opportunistic_T_49 = lt(io.cpu.req.bits.size, UInt<1>(0h0))
node _pstore_drain_opportunistic_T_50 = or(_pstore_drain_opportunistic_T_48, _pstore_drain_opportunistic_T_49)
node _pstore_drain_opportunistic_T_51 = and(_pstore_drain_opportunistic_T_47, _pstore_drain_opportunistic_T_50)
node _pstore_drain_opportunistic_T_52 = or(_pstore_drain_opportunistic_T_24, _pstore_drain_opportunistic_T_51)
node _pstore_drain_opportunistic_T_53 = eq(_pstore_drain_opportunistic_T_52, UInt<1>(0h0))
node _pstore_drain_opportunistic_T_54 = or(_pstore_drain_opportunistic_T_53, pstore_drain_opportunistic_res)
node _pstore_drain_opportunistic_T_55 = asUInt(reset)
node _pstore_drain_opportunistic_T_56 = eq(_pstore_drain_opportunistic_T_55, UInt<1>(0h0))
when _pstore_drain_opportunistic_T_56 :
node _pstore_drain_opportunistic_T_57 = eq(_pstore_drain_opportunistic_T_54, UInt<1>(0h0))
when _pstore_drain_opportunistic_T_57 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:1186 assert(!needsRead(req) || res)\n") : pstore_drain_opportunistic_printf
assert(clock, _pstore_drain_opportunistic_T_54, UInt<1>(0h1), "") : pstore_drain_opportunistic_assert
node _pstore_drain_opportunistic_T_58 = and(io.cpu.req.valid, pstore_drain_opportunistic_res)
node _pstore_drain_opportunistic_T_59 = eq(_pstore_drain_opportunistic_T_58, UInt<1>(0h0))
node _pstore_drain_opportunistic_T_60 = and(s1_valid, s1_waw_hazard)
node _pstore_drain_opportunistic_T_61 = eq(_pstore_drain_opportunistic_T_60, UInt<1>(0h0))
node pstore_drain_opportunistic = and(_pstore_drain_opportunistic_T_59, _pstore_drain_opportunistic_T_61)
reg pstore_drain_on_miss_REG : UInt<1>, clock
connect pstore_drain_on_miss_REG, io.cpu.s2_nack
node pstore_drain_on_miss = or(releaseInFlight, pstore_drain_on_miss_REG)
regreset pstore1_held : UInt<1>, clock, reset, UInt<1>(0h0)
node _pstore1_valid_likely_T = and(s2_valid, s2_write)
node pstore1_valid_likely = or(_pstore1_valid_likely_T, pstore1_held)
node _pstore1_valid_T = and(s2_valid_hit, s2_write)
node _pstore1_valid_T_1 = eq(s2_sc_fail, UInt<1>(0h0))
node _pstore1_valid_T_2 = and(_pstore1_valid_T, _pstore1_valid_T_1)
node _pstore1_valid_T_3 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _pstore1_valid_T_4 = and(_pstore1_valid_T_2, _pstore1_valid_T_3)
node pstore1_valid = or(_pstore1_valid_T_4, pstore1_held)
node _any_pstore_valid_T = or(pstore1_held, pstore2_valid)
connect any_pstore_valid, _any_pstore_valid_T
node _pstore_drain_structural_T = and(pstore1_valid_likely, pstore2_valid)
node _pstore_drain_structural_T_1 = and(s1_valid, s1_write)
node _pstore_drain_structural_T_2 = or(_pstore_drain_structural_T_1, pstore1_rmw)
node pstore_drain_structural = and(_pstore_drain_structural_T, _pstore_drain_structural_T_2)
node _T_49 = and(s2_valid_hit_pre_data_ecc, s2_write)
node _T_50 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
node _T_52 = or(_T_51, pstore1_held)
node _T_53 = eq(_T_52, pstore1_valid)
node _T_54 = or(pstore1_rmw, _T_53)
node _T_55 = asUInt(reset)
node _T_56 = eq(_T_55, UInt<1>(0h0))
when _T_56 :
node _T_57 = eq(_T_54, UInt<1>(0h0))
when _T_57 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:510 assert(pstore1_rmw || pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid)\n") : printf_1
assert(clock, _T_54, UInt<1>(0h1), "") : assert_1
node _T_58 = and(pstore1_valid, pstore_drain_on_miss)
node _T_59 = and(s1_valid_not_nacked, s1_waw_hazard)
node pstore_drain_s2_kill = and(UInt<1>(0h1), io.cpu.s2_kill)
node _pstore_drain_T = eq(pstore1_merge_likely, UInt<1>(0h0))
node _pstore_drain_T_1 = and(UInt<1>(0h0), pstore_drain_structural)
node _pstore_drain_T_2 = and(s2_valid_hit_pre_data_ecc, s2_write)
node _pstore_drain_T_3 = eq(pstore_drain_s2_kill, UInt<1>(0h0))
node _pstore_drain_T_4 = and(_pstore_drain_T_2, _pstore_drain_T_3)
node _pstore_drain_T_5 = or(_pstore_drain_T_4, pstore1_held)
node _pstore_drain_T_6 = eq(pstore1_rmw, UInt<1>(0h0))
node _pstore_drain_T_7 = and(_pstore_drain_T_5, _pstore_drain_T_6)
node _pstore_drain_T_8 = or(_pstore_drain_T_7, pstore2_valid)
node _pstore_drain_T_9 = or(pstore_drain_opportunistic, pstore_drain_on_miss)
node _pstore_drain_T_10 = and(_pstore_drain_T_8, _pstore_drain_T_9)
node _pstore_drain_T_11 = or(_pstore_drain_T_1, _pstore_drain_T_10)
node pstore_drain = and(_pstore_drain_T, _pstore_drain_T_11)
node _pstore1_held_T = and(s2_valid_hit, s2_write)
node _pstore1_held_T_1 = eq(s2_sc_fail, UInt<1>(0h0))
node _pstore1_held_T_2 = and(_pstore1_held_T, _pstore1_held_T_1)
node _pstore1_held_T_3 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _pstore1_held_T_4 = and(_pstore1_held_T_2, _pstore1_held_T_3)
node _pstore1_held_T_5 = eq(s2_store_merge, UInt<1>(0h0))
node _pstore1_held_T_6 = and(_pstore1_held_T_4, _pstore1_held_T_5)
node _pstore1_held_T_7 = or(_pstore1_held_T_6, pstore1_held)
node _pstore1_held_T_8 = and(_pstore1_held_T_7, pstore2_valid)
node _pstore1_held_T_9 = eq(pstore_drain, UInt<1>(0h0))
node _pstore1_held_T_10 = and(_pstore1_held_T_8, _pstore1_held_T_9)
connect pstore1_held, _pstore1_held_T_10
node _advance_pstore1_T = or(pstore1_valid, s2_valid_correct)
node _advance_pstore1_T_1 = eq(pstore2_valid, pstore_drain)
node advance_pstore1 = and(_advance_pstore1_T, _advance_pstore1_T_1)
node _pstore2_valid_T = eq(pstore_drain, UInt<1>(0h0))
node _pstore2_valid_T_1 = and(pstore2_valid, _pstore2_valid_T)
node _pstore2_valid_T_2 = or(_pstore2_valid_T_1, advance_pstore1)
connect pstore2_valid, _pstore2_valid_T_2
node _pstore2_addr_T = mux(s2_correct, s2_vaddr, pstore1_addr)
reg pstore2_addr : UInt<40>, clock
when advance_pstore1 :
connect pstore2_addr, _pstore2_addr_T
node _pstore2_way_T = mux(s2_correct, s2_hit_way, pstore1_way)
reg pstore2_way : UInt<4>, clock
when advance_pstore1 :
connect pstore2_way, _pstore2_way_T
node _pstore2_storegen_data_T = bits(pstore1_storegen_data, 7, 0)
node _pstore2_storegen_data_T_1 = bits(pstore1_mask, 0, 0)
node _pstore2_storegen_data_T_2 = and(pstore1_merge, _pstore2_storegen_data_T_1)
node _pstore2_storegen_data_T_3 = or(advance_pstore1, _pstore2_storegen_data_T_2)
reg pstore2_storegen_data_r : UInt<8>, clock
when _pstore2_storegen_data_T_3 :
connect pstore2_storegen_data_r, _pstore2_storegen_data_T
node _pstore2_storegen_data_T_4 = bits(pstore1_storegen_data, 15, 8)
node _pstore2_storegen_data_T_5 = bits(pstore1_mask, 1, 1)
node _pstore2_storegen_data_T_6 = and(pstore1_merge, _pstore2_storegen_data_T_5)
node _pstore2_storegen_data_T_7 = or(advance_pstore1, _pstore2_storegen_data_T_6)
reg pstore2_storegen_data_r_1 : UInt<8>, clock
when _pstore2_storegen_data_T_7 :
connect pstore2_storegen_data_r_1, _pstore2_storegen_data_T_4
node _pstore2_storegen_data_T_8 = bits(pstore1_storegen_data, 23, 16)
node _pstore2_storegen_data_T_9 = bits(pstore1_mask, 2, 2)
node _pstore2_storegen_data_T_10 = and(pstore1_merge, _pstore2_storegen_data_T_9)
node _pstore2_storegen_data_T_11 = or(advance_pstore1, _pstore2_storegen_data_T_10)
reg pstore2_storegen_data_r_2 : UInt<8>, clock
when _pstore2_storegen_data_T_11 :
connect pstore2_storegen_data_r_2, _pstore2_storegen_data_T_8
node _pstore2_storegen_data_T_12 = bits(pstore1_storegen_data, 31, 24)
node _pstore2_storegen_data_T_13 = bits(pstore1_mask, 3, 3)
node _pstore2_storegen_data_T_14 = and(pstore1_merge, _pstore2_storegen_data_T_13)
node _pstore2_storegen_data_T_15 = or(advance_pstore1, _pstore2_storegen_data_T_14)
reg pstore2_storegen_data_r_3 : UInt<8>, clock
when _pstore2_storegen_data_T_15 :
connect pstore2_storegen_data_r_3, _pstore2_storegen_data_T_12
node _pstore2_storegen_data_T_16 = bits(pstore1_storegen_data, 39, 32)
node _pstore2_storegen_data_T_17 = bits(pstore1_mask, 4, 4)
node _pstore2_storegen_data_T_18 = and(pstore1_merge, _pstore2_storegen_data_T_17)
node _pstore2_storegen_data_T_19 = or(advance_pstore1, _pstore2_storegen_data_T_18)
reg pstore2_storegen_data_r_4 : UInt<8>, clock
when _pstore2_storegen_data_T_19 :
connect pstore2_storegen_data_r_4, _pstore2_storegen_data_T_16
node _pstore2_storegen_data_T_20 = bits(pstore1_storegen_data, 47, 40)
node _pstore2_storegen_data_T_21 = bits(pstore1_mask, 5, 5)
node _pstore2_storegen_data_T_22 = and(pstore1_merge, _pstore2_storegen_data_T_21)
node _pstore2_storegen_data_T_23 = or(advance_pstore1, _pstore2_storegen_data_T_22)
reg pstore2_storegen_data_r_5 : UInt<8>, clock
when _pstore2_storegen_data_T_23 :
connect pstore2_storegen_data_r_5, _pstore2_storegen_data_T_20
node _pstore2_storegen_data_T_24 = bits(pstore1_storegen_data, 55, 48)
node _pstore2_storegen_data_T_25 = bits(pstore1_mask, 6, 6)
node _pstore2_storegen_data_T_26 = and(pstore1_merge, _pstore2_storegen_data_T_25)
node _pstore2_storegen_data_T_27 = or(advance_pstore1, _pstore2_storegen_data_T_26)
reg pstore2_storegen_data_r_6 : UInt<8>, clock
when _pstore2_storegen_data_T_27 :
connect pstore2_storegen_data_r_6, _pstore2_storegen_data_T_24
node _pstore2_storegen_data_T_28 = bits(pstore1_storegen_data, 63, 56)
node _pstore2_storegen_data_T_29 = bits(pstore1_mask, 7, 7)
node _pstore2_storegen_data_T_30 = and(pstore1_merge, _pstore2_storegen_data_T_29)
node _pstore2_storegen_data_T_31 = or(advance_pstore1, _pstore2_storegen_data_T_30)
reg pstore2_storegen_data_r_7 : UInt<8>, clock
when _pstore2_storegen_data_T_31 :
connect pstore2_storegen_data_r_7, _pstore2_storegen_data_T_28
node pstore2_storegen_data_lo_lo = cat(pstore2_storegen_data_r_1, pstore2_storegen_data_r)
node pstore2_storegen_data_lo_hi = cat(pstore2_storegen_data_r_3, pstore2_storegen_data_r_2)
node pstore2_storegen_data_lo = cat(pstore2_storegen_data_lo_hi, pstore2_storegen_data_lo_lo)
node pstore2_storegen_data_hi_lo = cat(pstore2_storegen_data_r_5, pstore2_storegen_data_r_4)
node pstore2_storegen_data_hi_hi = cat(pstore2_storegen_data_r_7, pstore2_storegen_data_r_6)
node pstore2_storegen_data_hi = cat(pstore2_storegen_data_hi_hi, pstore2_storegen_data_hi_lo)
node pstore2_storegen_data = cat(pstore2_storegen_data_hi, pstore2_storegen_data_lo)
reg pstore2_storegen_mask : UInt<8>, clock
node _pstore2_storegen_mask_T = or(advance_pstore1, pstore1_merge)
when _pstore2_storegen_mask_T :
node _pstore2_storegen_mask_mergedMask_T = mux(pstore1_merge, pstore2_storegen_mask, UInt<1>(0h0))
node pstore2_storegen_mask_mergedMask = or(pstore1_mask, _pstore2_storegen_mask_mergedMask_T)
node _pstore2_storegen_mask_mask_T = not(pstore2_storegen_mask_mergedMask)
node _pstore2_storegen_mask_mask_T_1 = mux(s2_correct, UInt<1>(0h0), _pstore2_storegen_mask_mask_T)
node _pstore2_storegen_mask_mask_T_2 = not(_pstore2_storegen_mask_mask_T_1)
connect pstore2_storegen_mask, _pstore2_storegen_mask_mask_T_2
connect s2_store_merge, UInt<1>(0h0)
node dataArb_io_in_0_valid_s2_kill = and(UInt<1>(0h0), io.cpu.s2_kill)
node _dataArb_io_in_0_valid_T = eq(pstore1_merge_likely, UInt<1>(0h0))
node _dataArb_io_in_0_valid_T_1 = and(UInt<1>(0h0), pstore_drain_structural)
node _dataArb_io_in_0_valid_T_2 = and(s2_valid_hit_pre_data_ecc, s2_write)
node _dataArb_io_in_0_valid_T_3 = eq(dataArb_io_in_0_valid_s2_kill, UInt<1>(0h0))
node _dataArb_io_in_0_valid_T_4 = and(_dataArb_io_in_0_valid_T_2, _dataArb_io_in_0_valid_T_3)
node _dataArb_io_in_0_valid_T_5 = or(_dataArb_io_in_0_valid_T_4, pstore1_held)
node _dataArb_io_in_0_valid_T_6 = eq(pstore1_rmw, UInt<1>(0h0))
node _dataArb_io_in_0_valid_T_7 = and(_dataArb_io_in_0_valid_T_5, _dataArb_io_in_0_valid_T_6)
node _dataArb_io_in_0_valid_T_8 = or(_dataArb_io_in_0_valid_T_7, pstore2_valid)
node _dataArb_io_in_0_valid_T_9 = or(pstore_drain_opportunistic, pstore_drain_on_miss)
node _dataArb_io_in_0_valid_T_10 = and(_dataArb_io_in_0_valid_T_8, _dataArb_io_in_0_valid_T_9)
node _dataArb_io_in_0_valid_T_11 = or(_dataArb_io_in_0_valid_T_1, _dataArb_io_in_0_valid_T_10)
node _dataArb_io_in_0_valid_T_12 = and(_dataArb_io_in_0_valid_T, _dataArb_io_in_0_valid_T_11)
connect dataArb.io.in[0].valid, _dataArb_io_in_0_valid_T_12
connect dataArb.io.in[0].bits.write, pstore_drain
node _dataArb_io_in_0_bits_addr_T = mux(pstore2_valid, pstore2_addr, pstore1_addr)
connect dataArb.io.in[0].bits.addr, _dataArb_io_in_0_bits_addr_T
node _dataArb_io_in_0_bits_way_en_T = mux(pstore2_valid, pstore2_way, pstore1_way)
connect dataArb.io.in[0].bits.way_en, _dataArb_io_in_0_bits_way_en_T
node _dataArb_io_in_0_bits_wdata_T = mux(pstore2_valid, pstore2_storegen_data, pstore1_data)
node _dataArb_io_in_0_bits_wdata_T_1 = bits(_dataArb_io_in_0_bits_wdata_T, 7, 0)
node _dataArb_io_in_0_bits_wdata_T_2 = bits(_dataArb_io_in_0_bits_wdata_T, 15, 8)
node _dataArb_io_in_0_bits_wdata_T_3 = bits(_dataArb_io_in_0_bits_wdata_T, 23, 16)
node _dataArb_io_in_0_bits_wdata_T_4 = bits(_dataArb_io_in_0_bits_wdata_T, 31, 24)
node _dataArb_io_in_0_bits_wdata_T_5 = bits(_dataArb_io_in_0_bits_wdata_T, 39, 32)
node _dataArb_io_in_0_bits_wdata_T_6 = bits(_dataArb_io_in_0_bits_wdata_T, 47, 40)
node _dataArb_io_in_0_bits_wdata_T_7 = bits(_dataArb_io_in_0_bits_wdata_T, 55, 48)
node _dataArb_io_in_0_bits_wdata_T_8 = bits(_dataArb_io_in_0_bits_wdata_T, 63, 56)
node dataArb_io_in_0_bits_wdata_lo_lo = cat(_dataArb_io_in_0_bits_wdata_T_2, _dataArb_io_in_0_bits_wdata_T_1)
node dataArb_io_in_0_bits_wdata_lo_hi = cat(_dataArb_io_in_0_bits_wdata_T_4, _dataArb_io_in_0_bits_wdata_T_3)
node dataArb_io_in_0_bits_wdata_lo = cat(dataArb_io_in_0_bits_wdata_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo)
node dataArb_io_in_0_bits_wdata_hi_lo = cat(_dataArb_io_in_0_bits_wdata_T_6, _dataArb_io_in_0_bits_wdata_T_5)
node dataArb_io_in_0_bits_wdata_hi_hi = cat(_dataArb_io_in_0_bits_wdata_T_8, _dataArb_io_in_0_bits_wdata_T_7)
node dataArb_io_in_0_bits_wdata_hi = cat(dataArb_io_in_0_bits_wdata_hi_hi, dataArb_io_in_0_bits_wdata_hi_lo)
node _dataArb_io_in_0_bits_wdata_T_9 = cat(dataArb_io_in_0_bits_wdata_hi, dataArb_io_in_0_bits_wdata_lo)
connect dataArb.io.in[0].bits.wdata, _dataArb_io_in_0_bits_wdata_T_9
node _dataArb_io_in_0_bits_wordMask_eccMask_T = bits(dataArb.io.in[0].bits.eccMask, 0, 0)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_1 = bits(dataArb.io.in[0].bits.eccMask, 1, 1)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_2 = bits(dataArb.io.in[0].bits.eccMask, 2, 2)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_3 = bits(dataArb.io.in[0].bits.eccMask, 3, 3)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_4 = bits(dataArb.io.in[0].bits.eccMask, 4, 4)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_5 = bits(dataArb.io.in[0].bits.eccMask, 5, 5)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_6 = bits(dataArb.io.in[0].bits.eccMask, 6, 6)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_7 = bits(dataArb.io.in[0].bits.eccMask, 7, 7)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_8 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T, _dataArb_io_in_0_bits_wordMask_eccMask_T_1)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_9 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_8, _dataArb_io_in_0_bits_wordMask_eccMask_T_2)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_10 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_9, _dataArb_io_in_0_bits_wordMask_eccMask_T_3)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_11 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_10, _dataArb_io_in_0_bits_wordMask_eccMask_T_4)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_12 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_11, _dataArb_io_in_0_bits_wordMask_eccMask_T_5)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_13 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_12, _dataArb_io_in_0_bits_wordMask_eccMask_T_6)
node dataArb_io_in_0_bits_wordMask_eccMask = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_13, _dataArb_io_in_0_bits_wordMask_eccMask_T_7)
node _dataArb_io_in_0_bits_wordMask_wordMask_T = mux(pstore2_valid, pstore2_addr, pstore1_addr)
node dataArb_io_in_0_bits_wordMask_wordMask = dshl(UInt<1>(0h1), UInt<1>(0h0))
node _dataArb_io_in_0_bits_wordMask_T = bits(dataArb_io_in_0_bits_wordMask_wordMask, 0, 0)
node _dataArb_io_in_0_bits_wordMask_T_1 = bits(dataArb_io_in_0_bits_wordMask_wordMask, 1, 1)
node _dataArb_io_in_0_bits_wordMask_T_2 = cat(_dataArb_io_in_0_bits_wordMask_T_1, _dataArb_io_in_0_bits_wordMask_T)
node _dataArb_io_in_0_bits_wordMask_T_3 = and(_dataArb_io_in_0_bits_wordMask_T_2, dataArb_io_in_0_bits_wordMask_eccMask)
connect dataArb.io.in[0].bits.wordMask, _dataArb_io_in_0_bits_wordMask_T_3
node _dataArb_io_in_0_bits_eccMask_T = mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask)
node _dataArb_io_in_0_bits_eccMask_T_1 = bits(_dataArb_io_in_0_bits_eccMask_T, 0, 0)
node _dataArb_io_in_0_bits_eccMask_T_2 = bits(_dataArb_io_in_0_bits_eccMask_T, 1, 1)
node _dataArb_io_in_0_bits_eccMask_T_3 = bits(_dataArb_io_in_0_bits_eccMask_T, 2, 2)
node _dataArb_io_in_0_bits_eccMask_T_4 = bits(_dataArb_io_in_0_bits_eccMask_T, 3, 3)
node _dataArb_io_in_0_bits_eccMask_T_5 = bits(_dataArb_io_in_0_bits_eccMask_T, 4, 4)
node _dataArb_io_in_0_bits_eccMask_T_6 = bits(_dataArb_io_in_0_bits_eccMask_T, 5, 5)
node _dataArb_io_in_0_bits_eccMask_T_7 = bits(_dataArb_io_in_0_bits_eccMask_T, 6, 6)
node _dataArb_io_in_0_bits_eccMask_T_8 = bits(_dataArb_io_in_0_bits_eccMask_T, 7, 7)
node _dataArb_io_in_0_bits_eccMask_T_9 = orr(_dataArb_io_in_0_bits_eccMask_T_1)
node _dataArb_io_in_0_bits_eccMask_T_10 = orr(_dataArb_io_in_0_bits_eccMask_T_2)
node _dataArb_io_in_0_bits_eccMask_T_11 = orr(_dataArb_io_in_0_bits_eccMask_T_3)
node _dataArb_io_in_0_bits_eccMask_T_12 = orr(_dataArb_io_in_0_bits_eccMask_T_4)
node _dataArb_io_in_0_bits_eccMask_T_13 = orr(_dataArb_io_in_0_bits_eccMask_T_5)
node _dataArb_io_in_0_bits_eccMask_T_14 = orr(_dataArb_io_in_0_bits_eccMask_T_6)
node _dataArb_io_in_0_bits_eccMask_T_15 = orr(_dataArb_io_in_0_bits_eccMask_T_7)
node _dataArb_io_in_0_bits_eccMask_T_16 = orr(_dataArb_io_in_0_bits_eccMask_T_8)
node dataArb_io_in_0_bits_eccMask_lo_lo = cat(_dataArb_io_in_0_bits_eccMask_T_10, _dataArb_io_in_0_bits_eccMask_T_9)
node dataArb_io_in_0_bits_eccMask_lo_hi = cat(_dataArb_io_in_0_bits_eccMask_T_12, _dataArb_io_in_0_bits_eccMask_T_11)
node dataArb_io_in_0_bits_eccMask_lo = cat(dataArb_io_in_0_bits_eccMask_lo_hi, dataArb_io_in_0_bits_eccMask_lo_lo)
node dataArb_io_in_0_bits_eccMask_hi_lo = cat(_dataArb_io_in_0_bits_eccMask_T_14, _dataArb_io_in_0_bits_eccMask_T_13)
node dataArb_io_in_0_bits_eccMask_hi_hi = cat(_dataArb_io_in_0_bits_eccMask_T_16, _dataArb_io_in_0_bits_eccMask_T_15)
node dataArb_io_in_0_bits_eccMask_hi = cat(dataArb_io_in_0_bits_eccMask_hi_hi, dataArb_io_in_0_bits_eccMask_hi_lo)
node _dataArb_io_in_0_bits_eccMask_T_17 = cat(dataArb_io_in_0_bits_eccMask_hi, dataArb_io_in_0_bits_eccMask_lo)
connect dataArb.io.in[0].bits.eccMask, _dataArb_io_in_0_bits_eccMask_T_17
node _s1_hazard_T = bits(pstore1_addr, 7, 3)
node _s1_hazard_T_1 = bits(s1_vaddr, 7, 3)
node _s1_hazard_T_2 = eq(_s1_hazard_T, _s1_hazard_T_1)
node _s1_hazard_T_3 = bits(pstore1_mask, 0, 0)
node _s1_hazard_T_4 = bits(pstore1_mask, 1, 1)
node _s1_hazard_T_5 = bits(pstore1_mask, 2, 2)
node _s1_hazard_T_6 = bits(pstore1_mask, 3, 3)
node _s1_hazard_T_7 = bits(pstore1_mask, 4, 4)
node _s1_hazard_T_8 = bits(pstore1_mask, 5, 5)
node _s1_hazard_T_9 = bits(pstore1_mask, 6, 6)
node _s1_hazard_T_10 = bits(pstore1_mask, 7, 7)
node _s1_hazard_T_11 = orr(_s1_hazard_T_3)
node _s1_hazard_T_12 = orr(_s1_hazard_T_4)
node _s1_hazard_T_13 = orr(_s1_hazard_T_5)
node _s1_hazard_T_14 = orr(_s1_hazard_T_6)
node _s1_hazard_T_15 = orr(_s1_hazard_T_7)
node _s1_hazard_T_16 = orr(_s1_hazard_T_8)
node _s1_hazard_T_17 = orr(_s1_hazard_T_9)
node _s1_hazard_T_18 = orr(_s1_hazard_T_10)
node s1_hazard_lo_lo = cat(_s1_hazard_T_12, _s1_hazard_T_11)
node s1_hazard_lo_hi = cat(_s1_hazard_T_14, _s1_hazard_T_13)
node s1_hazard_lo = cat(s1_hazard_lo_hi, s1_hazard_lo_lo)
node s1_hazard_hi_lo = cat(_s1_hazard_T_16, _s1_hazard_T_15)
node s1_hazard_hi_hi = cat(_s1_hazard_T_18, _s1_hazard_T_17)
node s1_hazard_hi = cat(s1_hazard_hi_hi, s1_hazard_hi_lo)
node _s1_hazard_T_19 = cat(s1_hazard_hi, s1_hazard_lo)
node _s1_hazard_T_20 = bits(_s1_hazard_T_19, 0, 0)
node _s1_hazard_T_21 = bits(_s1_hazard_T_19, 1, 1)
node _s1_hazard_T_22 = bits(_s1_hazard_T_19, 2, 2)
node _s1_hazard_T_23 = bits(_s1_hazard_T_19, 3, 3)
node _s1_hazard_T_24 = bits(_s1_hazard_T_19, 4, 4)
node _s1_hazard_T_25 = bits(_s1_hazard_T_19, 5, 5)
node _s1_hazard_T_26 = bits(_s1_hazard_T_19, 6, 6)
node _s1_hazard_T_27 = bits(_s1_hazard_T_19, 7, 7)
node s1_hazard_lo_lo_1 = cat(_s1_hazard_T_21, _s1_hazard_T_20)
node s1_hazard_lo_hi_1 = cat(_s1_hazard_T_23, _s1_hazard_T_22)
node s1_hazard_lo_1 = cat(s1_hazard_lo_hi_1, s1_hazard_lo_lo_1)
node s1_hazard_hi_lo_1 = cat(_s1_hazard_T_25, _s1_hazard_T_24)
node s1_hazard_hi_hi_1 = cat(_s1_hazard_T_27, _s1_hazard_T_26)
node s1_hazard_hi_1 = cat(s1_hazard_hi_hi_1, s1_hazard_hi_lo_1)
node _s1_hazard_T_28 = cat(s1_hazard_hi_1, s1_hazard_lo_1)
node _s1_hazard_T_29 = bits(s1_mask_xwr, 0, 0)
node _s1_hazard_T_30 = bits(s1_mask_xwr, 1, 1)
node _s1_hazard_T_31 = bits(s1_mask_xwr, 2, 2)
node _s1_hazard_T_32 = bits(s1_mask_xwr, 3, 3)
node _s1_hazard_T_33 = bits(s1_mask_xwr, 4, 4)
node _s1_hazard_T_34 = bits(s1_mask_xwr, 5, 5)
node _s1_hazard_T_35 = bits(s1_mask_xwr, 6, 6)
node _s1_hazard_T_36 = bits(s1_mask_xwr, 7, 7)
node _s1_hazard_T_37 = orr(_s1_hazard_T_29)
node _s1_hazard_T_38 = orr(_s1_hazard_T_30)
node _s1_hazard_T_39 = orr(_s1_hazard_T_31)
node _s1_hazard_T_40 = orr(_s1_hazard_T_32)
node _s1_hazard_T_41 = orr(_s1_hazard_T_33)
node _s1_hazard_T_42 = orr(_s1_hazard_T_34)
node _s1_hazard_T_43 = orr(_s1_hazard_T_35)
node _s1_hazard_T_44 = orr(_s1_hazard_T_36)
node s1_hazard_lo_lo_2 = cat(_s1_hazard_T_38, _s1_hazard_T_37)
node s1_hazard_lo_hi_2 = cat(_s1_hazard_T_40, _s1_hazard_T_39)
node s1_hazard_lo_2 = cat(s1_hazard_lo_hi_2, s1_hazard_lo_lo_2)
node s1_hazard_hi_lo_2 = cat(_s1_hazard_T_42, _s1_hazard_T_41)
node s1_hazard_hi_hi_2 = cat(_s1_hazard_T_44, _s1_hazard_T_43)
node s1_hazard_hi_2 = cat(s1_hazard_hi_hi_2, s1_hazard_hi_lo_2)
node _s1_hazard_T_45 = cat(s1_hazard_hi_2, s1_hazard_lo_2)
node _s1_hazard_T_46 = bits(_s1_hazard_T_45, 0, 0)
node _s1_hazard_T_47 = bits(_s1_hazard_T_45, 1, 1)
node _s1_hazard_T_48 = bits(_s1_hazard_T_45, 2, 2)
node _s1_hazard_T_49 = bits(_s1_hazard_T_45, 3, 3)
node _s1_hazard_T_50 = bits(_s1_hazard_T_45, 4, 4)
node _s1_hazard_T_51 = bits(_s1_hazard_T_45, 5, 5)
node _s1_hazard_T_52 = bits(_s1_hazard_T_45, 6, 6)
node _s1_hazard_T_53 = bits(_s1_hazard_T_45, 7, 7)
node s1_hazard_lo_lo_3 = cat(_s1_hazard_T_47, _s1_hazard_T_46)
node s1_hazard_lo_hi_3 = cat(_s1_hazard_T_49, _s1_hazard_T_48)
node s1_hazard_lo_3 = cat(s1_hazard_lo_hi_3, s1_hazard_lo_lo_3)
node s1_hazard_hi_lo_3 = cat(_s1_hazard_T_51, _s1_hazard_T_50)
node s1_hazard_hi_hi_3 = cat(_s1_hazard_T_53, _s1_hazard_T_52)
node s1_hazard_hi_3 = cat(s1_hazard_hi_hi_3, s1_hazard_hi_lo_3)
node _s1_hazard_T_54 = cat(s1_hazard_hi_3, s1_hazard_lo_3)
node _s1_hazard_T_55 = and(_s1_hazard_T_28, _s1_hazard_T_54)
node _s1_hazard_T_56 = orr(_s1_hazard_T_55)
node _s1_hazard_T_57 = and(pstore1_mask, s1_mask_xwr)
node _s1_hazard_T_58 = orr(_s1_hazard_T_57)
node _s1_hazard_T_59 = mux(s1_write, _s1_hazard_T_56, _s1_hazard_T_58)
node _s1_hazard_T_60 = and(_s1_hazard_T_2, _s1_hazard_T_59)
node _s1_hazard_T_61 = and(pstore1_valid_likely, _s1_hazard_T_60)
node _s1_hazard_T_62 = bits(pstore2_addr, 7, 3)
node _s1_hazard_T_63 = bits(s1_vaddr, 7, 3)
node _s1_hazard_T_64 = eq(_s1_hazard_T_62, _s1_hazard_T_63)
node _s1_hazard_T_65 = bits(pstore2_storegen_mask, 0, 0)
node _s1_hazard_T_66 = bits(pstore2_storegen_mask, 1, 1)
node _s1_hazard_T_67 = bits(pstore2_storegen_mask, 2, 2)
node _s1_hazard_T_68 = bits(pstore2_storegen_mask, 3, 3)
node _s1_hazard_T_69 = bits(pstore2_storegen_mask, 4, 4)
node _s1_hazard_T_70 = bits(pstore2_storegen_mask, 5, 5)
node _s1_hazard_T_71 = bits(pstore2_storegen_mask, 6, 6)
node _s1_hazard_T_72 = bits(pstore2_storegen_mask, 7, 7)
node _s1_hazard_T_73 = orr(_s1_hazard_T_65)
node _s1_hazard_T_74 = orr(_s1_hazard_T_66)
node _s1_hazard_T_75 = orr(_s1_hazard_T_67)
node _s1_hazard_T_76 = orr(_s1_hazard_T_68)
node _s1_hazard_T_77 = orr(_s1_hazard_T_69)
node _s1_hazard_T_78 = orr(_s1_hazard_T_70)
node _s1_hazard_T_79 = orr(_s1_hazard_T_71)
node _s1_hazard_T_80 = orr(_s1_hazard_T_72)
node s1_hazard_lo_lo_4 = cat(_s1_hazard_T_74, _s1_hazard_T_73)
node s1_hazard_lo_hi_4 = cat(_s1_hazard_T_76, _s1_hazard_T_75)
node s1_hazard_lo_4 = cat(s1_hazard_lo_hi_4, s1_hazard_lo_lo_4)
node s1_hazard_hi_lo_4 = cat(_s1_hazard_T_78, _s1_hazard_T_77)
node s1_hazard_hi_hi_4 = cat(_s1_hazard_T_80, _s1_hazard_T_79)
node s1_hazard_hi_4 = cat(s1_hazard_hi_hi_4, s1_hazard_hi_lo_4)
node _s1_hazard_T_81 = cat(s1_hazard_hi_4, s1_hazard_lo_4)
node _s1_hazard_T_82 = bits(_s1_hazard_T_81, 0, 0)
node _s1_hazard_T_83 = bits(_s1_hazard_T_81, 1, 1)
node _s1_hazard_T_84 = bits(_s1_hazard_T_81, 2, 2)
node _s1_hazard_T_85 = bits(_s1_hazard_T_81, 3, 3)
node _s1_hazard_T_86 = bits(_s1_hazard_T_81, 4, 4)
node _s1_hazard_T_87 = bits(_s1_hazard_T_81, 5, 5)
node _s1_hazard_T_88 = bits(_s1_hazard_T_81, 6, 6)
node _s1_hazard_T_89 = bits(_s1_hazard_T_81, 7, 7)
node s1_hazard_lo_lo_5 = cat(_s1_hazard_T_83, _s1_hazard_T_82)
node s1_hazard_lo_hi_5 = cat(_s1_hazard_T_85, _s1_hazard_T_84)
node s1_hazard_lo_5 = cat(s1_hazard_lo_hi_5, s1_hazard_lo_lo_5)
node s1_hazard_hi_lo_5 = cat(_s1_hazard_T_87, _s1_hazard_T_86)
node s1_hazard_hi_hi_5 = cat(_s1_hazard_T_89, _s1_hazard_T_88)
node s1_hazard_hi_5 = cat(s1_hazard_hi_hi_5, s1_hazard_hi_lo_5)
node _s1_hazard_T_90 = cat(s1_hazard_hi_5, s1_hazard_lo_5)
node _s1_hazard_T_91 = bits(s1_mask_xwr, 0, 0)
node _s1_hazard_T_92 = bits(s1_mask_xwr, 1, 1)
node _s1_hazard_T_93 = bits(s1_mask_xwr, 2, 2)
node _s1_hazard_T_94 = bits(s1_mask_xwr, 3, 3)
node _s1_hazard_T_95 = bits(s1_mask_xwr, 4, 4)
node _s1_hazard_T_96 = bits(s1_mask_xwr, 5, 5)
node _s1_hazard_T_97 = bits(s1_mask_xwr, 6, 6)
node _s1_hazard_T_98 = bits(s1_mask_xwr, 7, 7)
node _s1_hazard_T_99 = orr(_s1_hazard_T_91)
node _s1_hazard_T_100 = orr(_s1_hazard_T_92)
node _s1_hazard_T_101 = orr(_s1_hazard_T_93)
node _s1_hazard_T_102 = orr(_s1_hazard_T_94)
node _s1_hazard_T_103 = orr(_s1_hazard_T_95)
node _s1_hazard_T_104 = orr(_s1_hazard_T_96)
node _s1_hazard_T_105 = orr(_s1_hazard_T_97)
node _s1_hazard_T_106 = orr(_s1_hazard_T_98)
node s1_hazard_lo_lo_6 = cat(_s1_hazard_T_100, _s1_hazard_T_99)
node s1_hazard_lo_hi_6 = cat(_s1_hazard_T_102, _s1_hazard_T_101)
node s1_hazard_lo_6 = cat(s1_hazard_lo_hi_6, s1_hazard_lo_lo_6)
node s1_hazard_hi_lo_6 = cat(_s1_hazard_T_104, _s1_hazard_T_103)
node s1_hazard_hi_hi_6 = cat(_s1_hazard_T_106, _s1_hazard_T_105)
node s1_hazard_hi_6 = cat(s1_hazard_hi_hi_6, s1_hazard_hi_lo_6)
node _s1_hazard_T_107 = cat(s1_hazard_hi_6, s1_hazard_lo_6)
node _s1_hazard_T_108 = bits(_s1_hazard_T_107, 0, 0)
node _s1_hazard_T_109 = bits(_s1_hazard_T_107, 1, 1)
node _s1_hazard_T_110 = bits(_s1_hazard_T_107, 2, 2)
node _s1_hazard_T_111 = bits(_s1_hazard_T_107, 3, 3)
node _s1_hazard_T_112 = bits(_s1_hazard_T_107, 4, 4)
node _s1_hazard_T_113 = bits(_s1_hazard_T_107, 5, 5)
node _s1_hazard_T_114 = bits(_s1_hazard_T_107, 6, 6)
node _s1_hazard_T_115 = bits(_s1_hazard_T_107, 7, 7)
node s1_hazard_lo_lo_7 = cat(_s1_hazard_T_109, _s1_hazard_T_108)
node s1_hazard_lo_hi_7 = cat(_s1_hazard_T_111, _s1_hazard_T_110)
node s1_hazard_lo_7 = cat(s1_hazard_lo_hi_7, s1_hazard_lo_lo_7)
node s1_hazard_hi_lo_7 = cat(_s1_hazard_T_113, _s1_hazard_T_112)
node s1_hazard_hi_hi_7 = cat(_s1_hazard_T_115, _s1_hazard_T_114)
node s1_hazard_hi_7 = cat(s1_hazard_hi_hi_7, s1_hazard_hi_lo_7)
node _s1_hazard_T_116 = cat(s1_hazard_hi_7, s1_hazard_lo_7)
node _s1_hazard_T_117 = and(_s1_hazard_T_90, _s1_hazard_T_116)
node _s1_hazard_T_118 = orr(_s1_hazard_T_117)
node _s1_hazard_T_119 = and(pstore2_storegen_mask, s1_mask_xwr)
node _s1_hazard_T_120 = orr(_s1_hazard_T_119)
node _s1_hazard_T_121 = mux(s1_write, _s1_hazard_T_118, _s1_hazard_T_120)
node _s1_hazard_T_122 = and(_s1_hazard_T_64, _s1_hazard_T_121)
node _s1_hazard_T_123 = and(pstore2_valid, _s1_hazard_T_122)
node s1_hazard = or(_s1_hazard_T_61, _s1_hazard_T_123)
node s1_raw_hazard = and(s1_read, s1_hazard)
connect s1_waw_hazard, UInt<1>(0h0)
node _T_60 = and(s1_valid, s1_raw_hazard)
when _T_60 :
connect s1_nack, UInt<1>(0h1)
reg io_cpu_s2_nack_cause_raw_REG : UInt<1>, clock
connect io_cpu_s2_nack_cause_raw_REG, s1_raw_hazard
node _io_cpu_s2_nack_cause_raw_T = eq(s2_waw_hazard, UInt<1>(0h0))
node _io_cpu_s2_nack_cause_raw_T_1 = or(_io_cpu_s2_nack_cause_raw_T, s2_store_merge)
node _io_cpu_s2_nack_cause_raw_T_2 = eq(_io_cpu_s2_nack_cause_raw_T_1, UInt<1>(0h0))
node _io_cpu_s2_nack_cause_raw_T_3 = or(io_cpu_s2_nack_cause_raw_REG, _io_cpu_s2_nack_cause_raw_T_2)
connect io.cpu.s2_nack_cause_raw, _io_cpu_s2_nack_cause_raw_T_3
node _a_source_T = not(uncachedInFlight[0])
node _a_source_T_1 = shl(_a_source_T, 1)
node _a_source_T_2 = bits(_a_source_T_1, 0, 0)
node _a_source_T_3 = bits(_a_source_T_1, 1, 1)
node a_source = mux(_a_source_T_2, UInt<1>(0h0), UInt<1>(0h1))
node _acquire_address_T = shr(s2_req.addr, 6)
node acquire_address = shl(_acquire_address_T, 6)
node _a_mask_T = shl(UInt<1>(0h0), 3)
node a_mask = dshl(pstore1_mask, _a_mask_T)
node _get_legal_T = leq(UInt<1>(0h0), s2_req.size)
node _get_legal_T_1 = leq(s2_req.size, UInt<4>(0hc))
node _get_legal_T_2 = and(_get_legal_T, _get_legal_T_1)
node _get_legal_T_3 = or(UInt<1>(0h0), _get_legal_T_2)
node _get_legal_T_4 = xor(s2_req.addr, UInt<14>(0h3000))
node _get_legal_T_5 = cvt(_get_legal_T_4)
node _get_legal_T_6 = and(_get_legal_T_5, asSInt(UInt<33>(0hffefb000)))
node _get_legal_T_7 = asSInt(_get_legal_T_6)
node _get_legal_T_8 = eq(_get_legal_T_7, asSInt(UInt<1>(0h0)))
node _get_legal_T_9 = and(_get_legal_T_3, _get_legal_T_8)
node _get_legal_T_10 = leq(UInt<1>(0h0), s2_req.size)
node _get_legal_T_11 = leq(s2_req.size, UInt<3>(0h6))
node _get_legal_T_12 = and(_get_legal_T_10, _get_legal_T_11)
node _get_legal_T_13 = or(UInt<1>(0h0), _get_legal_T_12)
node _get_legal_T_14 = xor(s2_req.addr, UInt<1>(0h0))
node _get_legal_T_15 = cvt(_get_legal_T_14)
node _get_legal_T_16 = and(_get_legal_T_15, asSInt(UInt<33>(0hffefa000)))
node _get_legal_T_17 = asSInt(_get_legal_T_16)
node _get_legal_T_18 = eq(_get_legal_T_17, asSInt(UInt<1>(0h0)))
node _get_legal_T_19 = xor(s2_req.addr, UInt<17>(0h10000))
node _get_legal_T_20 = cvt(_get_legal_T_19)
node _get_legal_T_21 = and(_get_legal_T_20, asSInt(UInt<33>(0hfdefb000)))
node _get_legal_T_22 = asSInt(_get_legal_T_21)
node _get_legal_T_23 = eq(_get_legal_T_22, asSInt(UInt<1>(0h0)))
node _get_legal_T_24 = xor(s2_req.addr, UInt<17>(0h10000))
node _get_legal_T_25 = cvt(_get_legal_T_24)
node _get_legal_T_26 = and(_get_legal_T_25, asSInt(UInt<33>(0hffef0000)))
node _get_legal_T_27 = asSInt(_get_legal_T_26)
node _get_legal_T_28 = eq(_get_legal_T_27, asSInt(UInt<1>(0h0)))
node _get_legal_T_29 = xor(s2_req.addr, UInt<26>(0h2000000))
node _get_legal_T_30 = cvt(_get_legal_T_29)
node _get_legal_T_31 = and(_get_legal_T_30, asSInt(UInt<33>(0hffef0000)))
node _get_legal_T_32 = asSInt(_get_legal_T_31)
node _get_legal_T_33 = eq(_get_legal_T_32, asSInt(UInt<1>(0h0)))
node _get_legal_T_34 = xor(s2_req.addr, UInt<28>(0h8000000))
node _get_legal_T_35 = cvt(_get_legal_T_34)
node _get_legal_T_36 = and(_get_legal_T_35, asSInt(UInt<33>(0hffef0000)))
node _get_legal_T_37 = asSInt(_get_legal_T_36)
node _get_legal_T_38 = eq(_get_legal_T_37, asSInt(UInt<1>(0h0)))
node _get_legal_T_39 = xor(s2_req.addr, UInt<28>(0hc000000))
node _get_legal_T_40 = cvt(_get_legal_T_39)
node _get_legal_T_41 = and(_get_legal_T_40, asSInt(UInt<33>(0hfc000000)))
node _get_legal_T_42 = asSInt(_get_legal_T_41)
node _get_legal_T_43 = eq(_get_legal_T_42, asSInt(UInt<1>(0h0)))
node _get_legal_T_44 = xor(s2_req.addr, UInt<29>(0h10020000))
node _get_legal_T_45 = cvt(_get_legal_T_44)
node _get_legal_T_46 = and(_get_legal_T_45, asSInt(UInt<33>(0hffefb000)))
node _get_legal_T_47 = asSInt(_get_legal_T_46)
node _get_legal_T_48 = eq(_get_legal_T_47, asSInt(UInt<1>(0h0)))
node _get_legal_T_49 = xor(s2_req.addr, UInt<32>(0h80000000))
node _get_legal_T_50 = cvt(_get_legal_T_49)
node _get_legal_T_51 = and(_get_legal_T_50, asSInt(UInt<33>(0hf0000000)))
node _get_legal_T_52 = asSInt(_get_legal_T_51)
node _get_legal_T_53 = eq(_get_legal_T_52, asSInt(UInt<1>(0h0)))
node _get_legal_T_54 = or(_get_legal_T_18, _get_legal_T_23)
node _get_legal_T_55 = or(_get_legal_T_54, _get_legal_T_28)
node _get_legal_T_56 = or(_get_legal_T_55, _get_legal_T_33)
node _get_legal_T_57 = or(_get_legal_T_56, _get_legal_T_38)
node _get_legal_T_58 = or(_get_legal_T_57, _get_legal_T_43)
node _get_legal_T_59 = or(_get_legal_T_58, _get_legal_T_48)
node _get_legal_T_60 = or(_get_legal_T_59, _get_legal_T_53)
node _get_legal_T_61 = and(_get_legal_T_13, _get_legal_T_60)
node _get_legal_T_62 = leq(UInt<1>(0h0), s2_req.size)
node _get_legal_T_63 = leq(s2_req.size, UInt<2>(0h3))
node _get_legal_T_64 = and(_get_legal_T_62, _get_legal_T_63)
node _get_legal_T_65 = or(UInt<1>(0h0), _get_legal_T_64)
node _get_legal_T_66 = xor(s2_req.addr, UInt<18>(0h20000))
node _get_legal_T_67 = cvt(_get_legal_T_66)
node _get_legal_T_68 = and(_get_legal_T_67, asSInt(UInt<33>(0hffef8000)))
node _get_legal_T_69 = asSInt(_get_legal_T_68)
node _get_legal_T_70 = eq(_get_legal_T_69, asSInt(UInt<1>(0h0)))
node _get_legal_T_71 = and(_get_legal_T_65, _get_legal_T_70)
node _get_legal_T_72 = or(UInt<1>(0h0), _get_legal_T_9)
node _get_legal_T_73 = or(_get_legal_T_72, _get_legal_T_61)
node get_legal = or(_get_legal_T_73, _get_legal_T_71)
wire get : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect get.opcode, UInt<3>(0h4)
connect get.param, UInt<1>(0h0)
connect get.size, s2_req.size
connect get.source, a_source
connect get.address, s2_req.addr
node _get_a_mask_sizeOH_T = or(s2_req.size, UInt<3>(0h0))
node get_a_mask_sizeOH_shiftAmount = bits(_get_a_mask_sizeOH_T, 1, 0)
node _get_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), get_a_mask_sizeOH_shiftAmount)
node _get_a_mask_sizeOH_T_2 = bits(_get_a_mask_sizeOH_T_1, 2, 0)
node get_a_mask_sizeOH = or(_get_a_mask_sizeOH_T_2, UInt<1>(0h1))
node get_a_mask_sub_sub_sub_0_1 = geq(s2_req.size, UInt<2>(0h3))
node get_a_mask_sub_sub_size = bits(get_a_mask_sizeOH, 2, 2)
node get_a_mask_sub_sub_bit = bits(s2_req.addr, 2, 2)
node get_a_mask_sub_sub_nbit = eq(get_a_mask_sub_sub_bit, UInt<1>(0h0))
node get_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_nbit)
node _get_a_mask_sub_sub_acc_T = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_0_2)
node get_a_mask_sub_sub_0_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T)
node get_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_bit)
node _get_a_mask_sub_sub_acc_T_1 = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_1_2)
node get_a_mask_sub_sub_1_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T_1)
node get_a_mask_sub_size = bits(get_a_mask_sizeOH, 1, 1)
node get_a_mask_sub_bit = bits(s2_req.addr, 1, 1)
node get_a_mask_sub_nbit = eq(get_a_mask_sub_bit, UInt<1>(0h0))
node get_a_mask_sub_0_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_nbit)
node _get_a_mask_sub_acc_T = and(get_a_mask_sub_size, get_a_mask_sub_0_2)
node get_a_mask_sub_0_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T)
node get_a_mask_sub_1_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_bit)
node _get_a_mask_sub_acc_T_1 = and(get_a_mask_sub_size, get_a_mask_sub_1_2)
node get_a_mask_sub_1_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T_1)
node get_a_mask_sub_2_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_nbit)
node _get_a_mask_sub_acc_T_2 = and(get_a_mask_sub_size, get_a_mask_sub_2_2)
node get_a_mask_sub_2_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_2)
node get_a_mask_sub_3_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_bit)
node _get_a_mask_sub_acc_T_3 = and(get_a_mask_sub_size, get_a_mask_sub_3_2)
node get_a_mask_sub_3_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_3)
node get_a_mask_size = bits(get_a_mask_sizeOH, 0, 0)
node get_a_mask_bit = bits(s2_req.addr, 0, 0)
node get_a_mask_nbit = eq(get_a_mask_bit, UInt<1>(0h0))
node get_a_mask_eq = and(get_a_mask_sub_0_2, get_a_mask_nbit)
node _get_a_mask_acc_T = and(get_a_mask_size, get_a_mask_eq)
node get_a_mask_acc = or(get_a_mask_sub_0_1, _get_a_mask_acc_T)
node get_a_mask_eq_1 = and(get_a_mask_sub_0_2, get_a_mask_bit)
node _get_a_mask_acc_T_1 = and(get_a_mask_size, get_a_mask_eq_1)
node get_a_mask_acc_1 = or(get_a_mask_sub_0_1, _get_a_mask_acc_T_1)
node get_a_mask_eq_2 = and(get_a_mask_sub_1_2, get_a_mask_nbit)
node _get_a_mask_acc_T_2 = and(get_a_mask_size, get_a_mask_eq_2)
node get_a_mask_acc_2 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_2)
node get_a_mask_eq_3 = and(get_a_mask_sub_1_2, get_a_mask_bit)
node _get_a_mask_acc_T_3 = and(get_a_mask_size, get_a_mask_eq_3)
node get_a_mask_acc_3 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_3)
node get_a_mask_eq_4 = and(get_a_mask_sub_2_2, get_a_mask_nbit)
node _get_a_mask_acc_T_4 = and(get_a_mask_size, get_a_mask_eq_4)
node get_a_mask_acc_4 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_4)
node get_a_mask_eq_5 = and(get_a_mask_sub_2_2, get_a_mask_bit)
node _get_a_mask_acc_T_5 = and(get_a_mask_size, get_a_mask_eq_5)
node get_a_mask_acc_5 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_5)
node get_a_mask_eq_6 = and(get_a_mask_sub_3_2, get_a_mask_nbit)
node _get_a_mask_acc_T_6 = and(get_a_mask_size, get_a_mask_eq_6)
node get_a_mask_acc_6 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_6)
node get_a_mask_eq_7 = and(get_a_mask_sub_3_2, get_a_mask_bit)
node _get_a_mask_acc_T_7 = and(get_a_mask_size, get_a_mask_eq_7)
node get_a_mask_acc_7 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_7)
node get_a_mask_lo_lo = cat(get_a_mask_acc_1, get_a_mask_acc)
node get_a_mask_lo_hi = cat(get_a_mask_acc_3, get_a_mask_acc_2)
node get_a_mask_lo = cat(get_a_mask_lo_hi, get_a_mask_lo_lo)
node get_a_mask_hi_lo = cat(get_a_mask_acc_5, get_a_mask_acc_4)
node get_a_mask_hi_hi = cat(get_a_mask_acc_7, get_a_mask_acc_6)
node get_a_mask_hi = cat(get_a_mask_hi_hi, get_a_mask_hi_lo)
node _get_a_mask_T = cat(get_a_mask_hi, get_a_mask_lo)
connect get.mask, _get_a_mask_T
invalidate get.data
connect get.corrupt, UInt<1>(0h0)
node _put_legal_T = leq(UInt<1>(0h0), s2_req.size)
node _put_legal_T_1 = leq(s2_req.size, UInt<4>(0hc))
node _put_legal_T_2 = and(_put_legal_T, _put_legal_T_1)
node _put_legal_T_3 = or(UInt<1>(0h0), _put_legal_T_2)
node _put_legal_T_4 = xor(s2_req.addr, UInt<14>(0h3000))
node _put_legal_T_5 = cvt(_put_legal_T_4)
node _put_legal_T_6 = and(_put_legal_T_5, asSInt(UInt<33>(0hffffb000)))
node _put_legal_T_7 = asSInt(_put_legal_T_6)
node _put_legal_T_8 = eq(_put_legal_T_7, asSInt(UInt<1>(0h0)))
node _put_legal_T_9 = and(_put_legal_T_3, _put_legal_T_8)
node _put_legal_T_10 = leq(UInt<1>(0h0), s2_req.size)
node _put_legal_T_11 = leq(s2_req.size, UInt<3>(0h6))
node _put_legal_T_12 = and(_put_legal_T_10, _put_legal_T_11)
node _put_legal_T_13 = or(UInt<1>(0h0), _put_legal_T_12)
node _put_legal_T_14 = xor(s2_req.addr, UInt<1>(0h0))
node _put_legal_T_15 = cvt(_put_legal_T_14)
node _put_legal_T_16 = and(_put_legal_T_15, asSInt(UInt<33>(0hffffa000)))
node _put_legal_T_17 = asSInt(_put_legal_T_16)
node _put_legal_T_18 = eq(_put_legal_T_17, asSInt(UInt<1>(0h0)))
node _put_legal_T_19 = xor(s2_req.addr, UInt<21>(0h100000))
node _put_legal_T_20 = cvt(_put_legal_T_19)
node _put_legal_T_21 = and(_put_legal_T_20, asSInt(UInt<33>(0hfffeb000)))
node _put_legal_T_22 = asSInt(_put_legal_T_21)
node _put_legal_T_23 = eq(_put_legal_T_22, asSInt(UInt<1>(0h0)))
node _put_legal_T_24 = xor(s2_req.addr, UInt<26>(0h2000000))
node _put_legal_T_25 = cvt(_put_legal_T_24)
node _put_legal_T_26 = and(_put_legal_T_25, asSInt(UInt<33>(0hffff0000)))
node _put_legal_T_27 = asSInt(_put_legal_T_26)
node _put_legal_T_28 = eq(_put_legal_T_27, asSInt(UInt<1>(0h0)))
node _put_legal_T_29 = xor(s2_req.addr, UInt<26>(0h2010000))
node _put_legal_T_30 = cvt(_put_legal_T_29)
node _put_legal_T_31 = and(_put_legal_T_30, asSInt(UInt<33>(0hffffb000)))
node _put_legal_T_32 = asSInt(_put_legal_T_31)
node _put_legal_T_33 = eq(_put_legal_T_32, asSInt(UInt<1>(0h0)))
node _put_legal_T_34 = xor(s2_req.addr, UInt<28>(0h8000000))
node _put_legal_T_35 = cvt(_put_legal_T_34)
node _put_legal_T_36 = and(_put_legal_T_35, asSInt(UInt<33>(0hffff0000)))
node _put_legal_T_37 = asSInt(_put_legal_T_36)
node _put_legal_T_38 = eq(_put_legal_T_37, asSInt(UInt<1>(0h0)))
node _put_legal_T_39 = xor(s2_req.addr, UInt<28>(0hc000000))
node _put_legal_T_40 = cvt(_put_legal_T_39)
node _put_legal_T_41 = and(_put_legal_T_40, asSInt(UInt<33>(0hfc000000)))
node _put_legal_T_42 = asSInt(_put_legal_T_41)
node _put_legal_T_43 = eq(_put_legal_T_42, asSInt(UInt<1>(0h0)))
node _put_legal_T_44 = xor(s2_req.addr, UInt<29>(0h10020000))
node _put_legal_T_45 = cvt(_put_legal_T_44)
node _put_legal_T_46 = and(_put_legal_T_45, asSInt(UInt<33>(0hffffb000)))
node _put_legal_T_47 = asSInt(_put_legal_T_46)
node _put_legal_T_48 = eq(_put_legal_T_47, asSInt(UInt<1>(0h0)))
node _put_legal_T_49 = xor(s2_req.addr, UInt<32>(0h80000000))
node _put_legal_T_50 = cvt(_put_legal_T_49)
node _put_legal_T_51 = and(_put_legal_T_50, asSInt(UInt<33>(0hf0000000)))
node _put_legal_T_52 = asSInt(_put_legal_T_51)
node _put_legal_T_53 = eq(_put_legal_T_52, asSInt(UInt<1>(0h0)))
node _put_legal_T_54 = or(_put_legal_T_18, _put_legal_T_23)
node _put_legal_T_55 = or(_put_legal_T_54, _put_legal_T_28)
node _put_legal_T_56 = or(_put_legal_T_55, _put_legal_T_33)
node _put_legal_T_57 = or(_put_legal_T_56, _put_legal_T_38)
node _put_legal_T_58 = or(_put_legal_T_57, _put_legal_T_43)
node _put_legal_T_59 = or(_put_legal_T_58, _put_legal_T_48)
node _put_legal_T_60 = or(_put_legal_T_59, _put_legal_T_53)
node _put_legal_T_61 = and(_put_legal_T_13, _put_legal_T_60)
node _put_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0))
node _put_legal_T_63 = xor(s2_req.addr, UInt<17>(0h10000))
node _put_legal_T_64 = cvt(_put_legal_T_63)
node _put_legal_T_65 = and(_put_legal_T_64, asSInt(UInt<33>(0hffff0000)))
node _put_legal_T_66 = asSInt(_put_legal_T_65)
node _put_legal_T_67 = eq(_put_legal_T_66, asSInt(UInt<1>(0h0)))
node _put_legal_T_68 = and(_put_legal_T_62, _put_legal_T_67)
node _put_legal_T_69 = leq(UInt<1>(0h0), s2_req.size)
node _put_legal_T_70 = leq(s2_req.size, UInt<2>(0h3))
node _put_legal_T_71 = and(_put_legal_T_69, _put_legal_T_70)
node _put_legal_T_72 = or(UInt<1>(0h0), _put_legal_T_71)
node _put_legal_T_73 = xor(s2_req.addr, UInt<18>(0h20000))
node _put_legal_T_74 = cvt(_put_legal_T_73)
node _put_legal_T_75 = and(_put_legal_T_74, asSInt(UInt<33>(0hffff8000)))
node _put_legal_T_76 = asSInt(_put_legal_T_75)
node _put_legal_T_77 = eq(_put_legal_T_76, asSInt(UInt<1>(0h0)))
node _put_legal_T_78 = and(_put_legal_T_72, _put_legal_T_77)
node _put_legal_T_79 = or(UInt<1>(0h0), _put_legal_T_9)
node _put_legal_T_80 = or(_put_legal_T_79, _put_legal_T_61)
node _put_legal_T_81 = or(_put_legal_T_80, _put_legal_T_68)
node put_legal = or(_put_legal_T_81, _put_legal_T_78)
wire put : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect put.opcode, UInt<1>(0h0)
connect put.param, UInt<1>(0h0)
connect put.size, s2_req.size
connect put.source, a_source
connect put.address, s2_req.addr
node _put_a_mask_sizeOH_T = or(s2_req.size, UInt<3>(0h0))
node put_a_mask_sizeOH_shiftAmount = bits(_put_a_mask_sizeOH_T, 1, 0)
node _put_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), put_a_mask_sizeOH_shiftAmount)
node _put_a_mask_sizeOH_T_2 = bits(_put_a_mask_sizeOH_T_1, 2, 0)
node put_a_mask_sizeOH = or(_put_a_mask_sizeOH_T_2, UInt<1>(0h1))
node put_a_mask_sub_sub_sub_0_1 = geq(s2_req.size, UInt<2>(0h3))
node put_a_mask_sub_sub_size = bits(put_a_mask_sizeOH, 2, 2)
node put_a_mask_sub_sub_bit = bits(s2_req.addr, 2, 2)
node put_a_mask_sub_sub_nbit = eq(put_a_mask_sub_sub_bit, UInt<1>(0h0))
node put_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_nbit)
node _put_a_mask_sub_sub_acc_T = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_0_2)
node put_a_mask_sub_sub_0_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T)
node put_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_bit)
node _put_a_mask_sub_sub_acc_T_1 = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_1_2)
node put_a_mask_sub_sub_1_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T_1)
node put_a_mask_sub_size = bits(put_a_mask_sizeOH, 1, 1)
node put_a_mask_sub_bit = bits(s2_req.addr, 1, 1)
node put_a_mask_sub_nbit = eq(put_a_mask_sub_bit, UInt<1>(0h0))
node put_a_mask_sub_0_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_nbit)
node _put_a_mask_sub_acc_T = and(put_a_mask_sub_size, put_a_mask_sub_0_2)
node put_a_mask_sub_0_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T)
node put_a_mask_sub_1_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_bit)
node _put_a_mask_sub_acc_T_1 = and(put_a_mask_sub_size, put_a_mask_sub_1_2)
node put_a_mask_sub_1_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T_1)
node put_a_mask_sub_2_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_nbit)
node _put_a_mask_sub_acc_T_2 = and(put_a_mask_sub_size, put_a_mask_sub_2_2)
node put_a_mask_sub_2_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_2)
node put_a_mask_sub_3_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_bit)
node _put_a_mask_sub_acc_T_3 = and(put_a_mask_sub_size, put_a_mask_sub_3_2)
node put_a_mask_sub_3_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_3)
node put_a_mask_size = bits(put_a_mask_sizeOH, 0, 0)
node put_a_mask_bit = bits(s2_req.addr, 0, 0)
node put_a_mask_nbit = eq(put_a_mask_bit, UInt<1>(0h0))
node put_a_mask_eq = and(put_a_mask_sub_0_2, put_a_mask_nbit)
node _put_a_mask_acc_T = and(put_a_mask_size, put_a_mask_eq)
node put_a_mask_acc = or(put_a_mask_sub_0_1, _put_a_mask_acc_T)
node put_a_mask_eq_1 = and(put_a_mask_sub_0_2, put_a_mask_bit)
node _put_a_mask_acc_T_1 = and(put_a_mask_size, put_a_mask_eq_1)
node put_a_mask_acc_1 = or(put_a_mask_sub_0_1, _put_a_mask_acc_T_1)
node put_a_mask_eq_2 = and(put_a_mask_sub_1_2, put_a_mask_nbit)
node _put_a_mask_acc_T_2 = and(put_a_mask_size, put_a_mask_eq_2)
node put_a_mask_acc_2 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_2)
node put_a_mask_eq_3 = and(put_a_mask_sub_1_2, put_a_mask_bit)
node _put_a_mask_acc_T_3 = and(put_a_mask_size, put_a_mask_eq_3)
node put_a_mask_acc_3 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_3)
node put_a_mask_eq_4 = and(put_a_mask_sub_2_2, put_a_mask_nbit)
node _put_a_mask_acc_T_4 = and(put_a_mask_size, put_a_mask_eq_4)
node put_a_mask_acc_4 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_4)
node put_a_mask_eq_5 = and(put_a_mask_sub_2_2, put_a_mask_bit)
node _put_a_mask_acc_T_5 = and(put_a_mask_size, put_a_mask_eq_5)
node put_a_mask_acc_5 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_5)
node put_a_mask_eq_6 = and(put_a_mask_sub_3_2, put_a_mask_nbit)
node _put_a_mask_acc_T_6 = and(put_a_mask_size, put_a_mask_eq_6)
node put_a_mask_acc_6 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_6)
node put_a_mask_eq_7 = and(put_a_mask_sub_3_2, put_a_mask_bit)
node _put_a_mask_acc_T_7 = and(put_a_mask_size, put_a_mask_eq_7)
node put_a_mask_acc_7 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_7)
node put_a_mask_lo_lo = cat(put_a_mask_acc_1, put_a_mask_acc)
node put_a_mask_lo_hi = cat(put_a_mask_acc_3, put_a_mask_acc_2)
node put_a_mask_lo = cat(put_a_mask_lo_hi, put_a_mask_lo_lo)
node put_a_mask_hi_lo = cat(put_a_mask_acc_5, put_a_mask_acc_4)
node put_a_mask_hi_hi = cat(put_a_mask_acc_7, put_a_mask_acc_6)
node put_a_mask_hi = cat(put_a_mask_hi_hi, put_a_mask_hi_lo)
node _put_a_mask_T = cat(put_a_mask_hi, put_a_mask_lo)
connect put.mask, _put_a_mask_T
connect put.data, pstore1_data
connect put.corrupt, UInt<1>(0h0)
node _putpartial_legal_T = leq(UInt<1>(0h0), s2_req.size)
node _putpartial_legal_T_1 = leq(s2_req.size, UInt<4>(0hc))
node _putpartial_legal_T_2 = and(_putpartial_legal_T, _putpartial_legal_T_1)
node _putpartial_legal_T_3 = or(UInt<1>(0h0), _putpartial_legal_T_2)
node _putpartial_legal_T_4 = xor(s2_req.addr, UInt<14>(0h3000))
node _putpartial_legal_T_5 = cvt(_putpartial_legal_T_4)
node _putpartial_legal_T_6 = and(_putpartial_legal_T_5, asSInt(UInt<33>(0hffffb000)))
node _putpartial_legal_T_7 = asSInt(_putpartial_legal_T_6)
node _putpartial_legal_T_8 = eq(_putpartial_legal_T_7, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_9 = and(_putpartial_legal_T_3, _putpartial_legal_T_8)
node _putpartial_legal_T_10 = leq(UInt<1>(0h0), s2_req.size)
node _putpartial_legal_T_11 = leq(s2_req.size, UInt<3>(0h6))
node _putpartial_legal_T_12 = and(_putpartial_legal_T_10, _putpartial_legal_T_11)
node _putpartial_legal_T_13 = or(UInt<1>(0h0), _putpartial_legal_T_12)
node _putpartial_legal_T_14 = xor(s2_req.addr, UInt<1>(0h0))
node _putpartial_legal_T_15 = cvt(_putpartial_legal_T_14)
node _putpartial_legal_T_16 = and(_putpartial_legal_T_15, asSInt(UInt<33>(0hffffa000)))
node _putpartial_legal_T_17 = asSInt(_putpartial_legal_T_16)
node _putpartial_legal_T_18 = eq(_putpartial_legal_T_17, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_19 = xor(s2_req.addr, UInt<21>(0h100000))
node _putpartial_legal_T_20 = cvt(_putpartial_legal_T_19)
node _putpartial_legal_T_21 = and(_putpartial_legal_T_20, asSInt(UInt<33>(0hfffeb000)))
node _putpartial_legal_T_22 = asSInt(_putpartial_legal_T_21)
node _putpartial_legal_T_23 = eq(_putpartial_legal_T_22, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_24 = xor(s2_req.addr, UInt<26>(0h2000000))
node _putpartial_legal_T_25 = cvt(_putpartial_legal_T_24)
node _putpartial_legal_T_26 = and(_putpartial_legal_T_25, asSInt(UInt<33>(0hffff0000)))
node _putpartial_legal_T_27 = asSInt(_putpartial_legal_T_26)
node _putpartial_legal_T_28 = eq(_putpartial_legal_T_27, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_29 = xor(s2_req.addr, UInt<26>(0h2010000))
node _putpartial_legal_T_30 = cvt(_putpartial_legal_T_29)
node _putpartial_legal_T_31 = and(_putpartial_legal_T_30, asSInt(UInt<33>(0hffffb000)))
node _putpartial_legal_T_32 = asSInt(_putpartial_legal_T_31)
node _putpartial_legal_T_33 = eq(_putpartial_legal_T_32, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_34 = xor(s2_req.addr, UInt<28>(0h8000000))
node _putpartial_legal_T_35 = cvt(_putpartial_legal_T_34)
node _putpartial_legal_T_36 = and(_putpartial_legal_T_35, asSInt(UInt<33>(0hffff0000)))
node _putpartial_legal_T_37 = asSInt(_putpartial_legal_T_36)
node _putpartial_legal_T_38 = eq(_putpartial_legal_T_37, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_39 = xor(s2_req.addr, UInt<28>(0hc000000))
node _putpartial_legal_T_40 = cvt(_putpartial_legal_T_39)
node _putpartial_legal_T_41 = and(_putpartial_legal_T_40, asSInt(UInt<33>(0hfc000000)))
node _putpartial_legal_T_42 = asSInt(_putpartial_legal_T_41)
node _putpartial_legal_T_43 = eq(_putpartial_legal_T_42, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_44 = xor(s2_req.addr, UInt<29>(0h10020000))
node _putpartial_legal_T_45 = cvt(_putpartial_legal_T_44)
node _putpartial_legal_T_46 = and(_putpartial_legal_T_45, asSInt(UInt<33>(0hffffb000)))
node _putpartial_legal_T_47 = asSInt(_putpartial_legal_T_46)
node _putpartial_legal_T_48 = eq(_putpartial_legal_T_47, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_49 = xor(s2_req.addr, UInt<32>(0h80000000))
node _putpartial_legal_T_50 = cvt(_putpartial_legal_T_49)
node _putpartial_legal_T_51 = and(_putpartial_legal_T_50, asSInt(UInt<33>(0hf0000000)))
node _putpartial_legal_T_52 = asSInt(_putpartial_legal_T_51)
node _putpartial_legal_T_53 = eq(_putpartial_legal_T_52, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_54 = or(_putpartial_legal_T_18, _putpartial_legal_T_23)
node _putpartial_legal_T_55 = or(_putpartial_legal_T_54, _putpartial_legal_T_28)
node _putpartial_legal_T_56 = or(_putpartial_legal_T_55, _putpartial_legal_T_33)
node _putpartial_legal_T_57 = or(_putpartial_legal_T_56, _putpartial_legal_T_38)
node _putpartial_legal_T_58 = or(_putpartial_legal_T_57, _putpartial_legal_T_43)
node _putpartial_legal_T_59 = or(_putpartial_legal_T_58, _putpartial_legal_T_48)
node _putpartial_legal_T_60 = or(_putpartial_legal_T_59, _putpartial_legal_T_53)
node _putpartial_legal_T_61 = and(_putpartial_legal_T_13, _putpartial_legal_T_60)
node _putpartial_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0))
node _putpartial_legal_T_63 = xor(s2_req.addr, UInt<17>(0h10000))
node _putpartial_legal_T_64 = cvt(_putpartial_legal_T_63)
node _putpartial_legal_T_65 = and(_putpartial_legal_T_64, asSInt(UInt<33>(0hffff0000)))
node _putpartial_legal_T_66 = asSInt(_putpartial_legal_T_65)
node _putpartial_legal_T_67 = eq(_putpartial_legal_T_66, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_68 = and(_putpartial_legal_T_62, _putpartial_legal_T_67)
node _putpartial_legal_T_69 = leq(UInt<1>(0h0), s2_req.size)
node _putpartial_legal_T_70 = leq(s2_req.size, UInt<2>(0h3))
node _putpartial_legal_T_71 = and(_putpartial_legal_T_69, _putpartial_legal_T_70)
node _putpartial_legal_T_72 = or(UInt<1>(0h0), _putpartial_legal_T_71)
node _putpartial_legal_T_73 = xor(s2_req.addr, UInt<18>(0h20000))
node _putpartial_legal_T_74 = cvt(_putpartial_legal_T_73)
node _putpartial_legal_T_75 = and(_putpartial_legal_T_74, asSInt(UInt<33>(0hffff8000)))
node _putpartial_legal_T_76 = asSInt(_putpartial_legal_T_75)
node _putpartial_legal_T_77 = eq(_putpartial_legal_T_76, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_78 = and(_putpartial_legal_T_72, _putpartial_legal_T_77)
node _putpartial_legal_T_79 = or(UInt<1>(0h0), _putpartial_legal_T_9)
node _putpartial_legal_T_80 = or(_putpartial_legal_T_79, _putpartial_legal_T_61)
node _putpartial_legal_T_81 = or(_putpartial_legal_T_80, _putpartial_legal_T_68)
node putpartial_legal = or(_putpartial_legal_T_81, _putpartial_legal_T_78)
wire putpartial : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect putpartial.opcode, UInt<1>(0h1)
connect putpartial.param, UInt<1>(0h0)
connect putpartial.size, s2_req.size
connect putpartial.source, a_source
connect putpartial.address, s2_req.addr
connect putpartial.mask, a_mask
connect putpartial.data, pstore1_data
connect putpartial.corrupt, UInt<1>(0h0)
wire _atomics_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect _atomics_WIRE.corrupt, UInt<1>(0h0)
connect _atomics_WIRE.data, UInt<64>(0h0)
connect _atomics_WIRE.mask, UInt<8>(0h0)
connect _atomics_WIRE.address, UInt<32>(0h0)
connect _atomics_WIRE.source, UInt<1>(0h0)
connect _atomics_WIRE.size, UInt<4>(0h0)
connect _atomics_WIRE.param, UInt<3>(0h0)
connect _atomics_WIRE.opcode, UInt<3>(0h0)
wire _atomics_WIRE_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect _atomics_WIRE_1, _atomics_WIRE
node _atomics_legal_T = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_1 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_2 = and(_atomics_legal_T, _atomics_legal_T_1)
node _atomics_legal_T_3 = or(UInt<1>(0h0), _atomics_legal_T_2)
node _atomics_legal_T_4 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_5 = cvt(_atomics_legal_T_4)
node _atomics_legal_T_6 = and(_atomics_legal_T_5, asSInt(UInt<33>(0hfffd8000)))
node _atomics_legal_T_7 = asSInt(_atomics_legal_T_6)
node _atomics_legal_T_8 = eq(_atomics_legal_T_7, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_9 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_10 = cvt(_atomics_legal_T_9)
node _atomics_legal_T_11 = and(_atomics_legal_T_10, asSInt(UInt<33>(0hfffe9000)))
node _atomics_legal_T_12 = asSInt(_atomics_legal_T_11)
node _atomics_legal_T_13 = eq(_atomics_legal_T_12, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_14 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_15 = cvt(_atomics_legal_T_14)
node _atomics_legal_T_16 = and(_atomics_legal_T_15, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_17 = asSInt(_atomics_legal_T_16)
node _atomics_legal_T_18 = eq(_atomics_legal_T_17, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_19 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_20 = cvt(_atomics_legal_T_19)
node _atomics_legal_T_21 = and(_atomics_legal_T_20, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_22 = asSInt(_atomics_legal_T_21)
node _atomics_legal_T_23 = eq(_atomics_legal_T_22, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_24 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_25 = cvt(_atomics_legal_T_24)
node _atomics_legal_T_26 = and(_atomics_legal_T_25, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_27 = asSInt(_atomics_legal_T_26)
node _atomics_legal_T_28 = eq(_atomics_legal_T_27, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_29 = xor(s2_req.addr, UInt<28>(0hc000000))
node _atomics_legal_T_30 = cvt(_atomics_legal_T_29)
node _atomics_legal_T_31 = and(_atomics_legal_T_30, asSInt(UInt<33>(0hfc000000)))
node _atomics_legal_T_32 = asSInt(_atomics_legal_T_31)
node _atomics_legal_T_33 = eq(_atomics_legal_T_32, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_34 = xor(s2_req.addr, UInt<29>(0h10020000))
node _atomics_legal_T_35 = cvt(_atomics_legal_T_34)
node _atomics_legal_T_36 = and(_atomics_legal_T_35, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_37 = asSInt(_atomics_legal_T_36)
node _atomics_legal_T_38 = eq(_atomics_legal_T_37, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_39 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_40 = cvt(_atomics_legal_T_39)
node _atomics_legal_T_41 = and(_atomics_legal_T_40, asSInt(UInt<33>(0hf0000000)))
node _atomics_legal_T_42 = asSInt(_atomics_legal_T_41)
node _atomics_legal_T_43 = eq(_atomics_legal_T_42, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_44 = or(_atomics_legal_T_8, _atomics_legal_T_13)
node _atomics_legal_T_45 = or(_atomics_legal_T_44, _atomics_legal_T_18)
node _atomics_legal_T_46 = or(_atomics_legal_T_45, _atomics_legal_T_23)
node _atomics_legal_T_47 = or(_atomics_legal_T_46, _atomics_legal_T_28)
node _atomics_legal_T_48 = or(_atomics_legal_T_47, _atomics_legal_T_33)
node _atomics_legal_T_49 = or(_atomics_legal_T_48, _atomics_legal_T_38)
node _atomics_legal_T_50 = or(_atomics_legal_T_49, _atomics_legal_T_43)
node _atomics_legal_T_51 = and(_atomics_legal_T_3, _atomics_legal_T_50)
node _atomics_legal_T_52 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_53 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_54 = cvt(_atomics_legal_T_53)
node _atomics_legal_T_55 = and(_atomics_legal_T_54, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_56 = asSInt(_atomics_legal_T_55)
node _atomics_legal_T_57 = eq(_atomics_legal_T_56, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_58 = and(_atomics_legal_T_52, _atomics_legal_T_57)
node _atomics_legal_T_59 = or(UInt<1>(0h0), _atomics_legal_T_51)
node atomics_legal = or(_atomics_legal_T_59, _atomics_legal_T_58)
wire atomics_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a.opcode, UInt<2>(0h3)
connect atomics_a.param, UInt<3>(0h3)
connect atomics_a.size, s2_req.size
connect atomics_a.source, a_source
connect atomics_a.address, s2_req.addr
node _atomics_a_mask_sizeOH_T = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount = bits(_atomics_a_mask_sizeOH_T, 1, 0)
node _atomics_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount)
node _atomics_a_mask_sizeOH_T_2 = bits(_atomics_a_mask_sizeOH_T_1, 2, 0)
node atomics_a_mask_sizeOH = or(_atomics_a_mask_sizeOH_T_2, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size = bits(atomics_a_mask_sizeOH, 2, 2)
node atomics_a_mask_sub_sub_bit = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit = eq(atomics_a_mask_sub_sub_bit, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit)
node _atomics_a_mask_sub_sub_acc_T = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_0_2)
node atomics_a_mask_sub_sub_0_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T)
node atomics_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit)
node _atomics_a_mask_sub_sub_acc_T_1 = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_1_2)
node atomics_a_mask_sub_sub_1_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T_1)
node atomics_a_mask_sub_size = bits(atomics_a_mask_sizeOH, 1, 1)
node atomics_a_mask_sub_bit = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit = eq(atomics_a_mask_sub_bit, UInt<1>(0h0))
node atomics_a_mask_sub_0_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_nbit)
node _atomics_a_mask_sub_acc_T = and(atomics_a_mask_sub_size, atomics_a_mask_sub_0_2)
node atomics_a_mask_sub_0_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T)
node atomics_a_mask_sub_1_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_bit)
node _atomics_a_mask_sub_acc_T_1 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_1_2)
node atomics_a_mask_sub_1_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T_1)
node atomics_a_mask_sub_2_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_nbit)
node _atomics_a_mask_sub_acc_T_2 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_2_2)
node atomics_a_mask_sub_2_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_2)
node atomics_a_mask_sub_3_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_bit)
node _atomics_a_mask_sub_acc_T_3 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_3_2)
node atomics_a_mask_sub_3_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_3)
node atomics_a_mask_size = bits(atomics_a_mask_sizeOH, 0, 0)
node atomics_a_mask_bit = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit = eq(atomics_a_mask_bit, UInt<1>(0h0))
node atomics_a_mask_eq = and(atomics_a_mask_sub_0_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T = and(atomics_a_mask_size, atomics_a_mask_eq)
node atomics_a_mask_acc = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T)
node atomics_a_mask_eq_1 = and(atomics_a_mask_sub_0_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_1 = and(atomics_a_mask_size, atomics_a_mask_eq_1)
node atomics_a_mask_acc_1 = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T_1)
node atomics_a_mask_eq_2 = and(atomics_a_mask_sub_1_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T_2 = and(atomics_a_mask_size, atomics_a_mask_eq_2)
node atomics_a_mask_acc_2 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_2)
node atomics_a_mask_eq_3 = and(atomics_a_mask_sub_1_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_3 = and(atomics_a_mask_size, atomics_a_mask_eq_3)
node atomics_a_mask_acc_3 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_3)
node atomics_a_mask_eq_4 = and(atomics_a_mask_sub_2_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T_4 = and(atomics_a_mask_size, atomics_a_mask_eq_4)
node atomics_a_mask_acc_4 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_4)
node atomics_a_mask_eq_5 = and(atomics_a_mask_sub_2_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_5 = and(atomics_a_mask_size, atomics_a_mask_eq_5)
node atomics_a_mask_acc_5 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_5)
node atomics_a_mask_eq_6 = and(atomics_a_mask_sub_3_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T_6 = and(atomics_a_mask_size, atomics_a_mask_eq_6)
node atomics_a_mask_acc_6 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_6)
node atomics_a_mask_eq_7 = and(atomics_a_mask_sub_3_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_7 = and(atomics_a_mask_size, atomics_a_mask_eq_7)
node atomics_a_mask_acc_7 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_7)
node atomics_a_mask_lo_lo = cat(atomics_a_mask_acc_1, atomics_a_mask_acc)
node atomics_a_mask_lo_hi = cat(atomics_a_mask_acc_3, atomics_a_mask_acc_2)
node atomics_a_mask_lo = cat(atomics_a_mask_lo_hi, atomics_a_mask_lo_lo)
node atomics_a_mask_hi_lo = cat(atomics_a_mask_acc_5, atomics_a_mask_acc_4)
node atomics_a_mask_hi_hi = cat(atomics_a_mask_acc_7, atomics_a_mask_acc_6)
node atomics_a_mask_hi = cat(atomics_a_mask_hi_hi, atomics_a_mask_hi_lo)
node _atomics_a_mask_T = cat(atomics_a_mask_hi, atomics_a_mask_lo)
connect atomics_a.mask, _atomics_a_mask_T
connect atomics_a.data, pstore1_data
connect atomics_a.corrupt, UInt<1>(0h0)
node _atomics_legal_T_60 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_61 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_62 = and(_atomics_legal_T_60, _atomics_legal_T_61)
node _atomics_legal_T_63 = or(UInt<1>(0h0), _atomics_legal_T_62)
node _atomics_legal_T_64 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_65 = cvt(_atomics_legal_T_64)
node _atomics_legal_T_66 = and(_atomics_legal_T_65, asSInt(UInt<33>(0hfffd8000)))
node _atomics_legal_T_67 = asSInt(_atomics_legal_T_66)
node _atomics_legal_T_68 = eq(_atomics_legal_T_67, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_69 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_70 = cvt(_atomics_legal_T_69)
node _atomics_legal_T_71 = and(_atomics_legal_T_70, asSInt(UInt<33>(0hfffe9000)))
node _atomics_legal_T_72 = asSInt(_atomics_legal_T_71)
node _atomics_legal_T_73 = eq(_atomics_legal_T_72, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_74 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_75 = cvt(_atomics_legal_T_74)
node _atomics_legal_T_76 = and(_atomics_legal_T_75, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_77 = asSInt(_atomics_legal_T_76)
node _atomics_legal_T_78 = eq(_atomics_legal_T_77, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_79 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_80 = cvt(_atomics_legal_T_79)
node _atomics_legal_T_81 = and(_atomics_legal_T_80, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_82 = asSInt(_atomics_legal_T_81)
node _atomics_legal_T_83 = eq(_atomics_legal_T_82, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_84 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_85 = cvt(_atomics_legal_T_84)
node _atomics_legal_T_86 = and(_atomics_legal_T_85, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_87 = asSInt(_atomics_legal_T_86)
node _atomics_legal_T_88 = eq(_atomics_legal_T_87, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_89 = xor(s2_req.addr, UInt<28>(0hc000000))
node _atomics_legal_T_90 = cvt(_atomics_legal_T_89)
node _atomics_legal_T_91 = and(_atomics_legal_T_90, asSInt(UInt<33>(0hfc000000)))
node _atomics_legal_T_92 = asSInt(_atomics_legal_T_91)
node _atomics_legal_T_93 = eq(_atomics_legal_T_92, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_94 = xor(s2_req.addr, UInt<29>(0h10020000))
node _atomics_legal_T_95 = cvt(_atomics_legal_T_94)
node _atomics_legal_T_96 = and(_atomics_legal_T_95, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_97 = asSInt(_atomics_legal_T_96)
node _atomics_legal_T_98 = eq(_atomics_legal_T_97, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_99 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_100 = cvt(_atomics_legal_T_99)
node _atomics_legal_T_101 = and(_atomics_legal_T_100, asSInt(UInt<33>(0hf0000000)))
node _atomics_legal_T_102 = asSInt(_atomics_legal_T_101)
node _atomics_legal_T_103 = eq(_atomics_legal_T_102, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_104 = or(_atomics_legal_T_68, _atomics_legal_T_73)
node _atomics_legal_T_105 = or(_atomics_legal_T_104, _atomics_legal_T_78)
node _atomics_legal_T_106 = or(_atomics_legal_T_105, _atomics_legal_T_83)
node _atomics_legal_T_107 = or(_atomics_legal_T_106, _atomics_legal_T_88)
node _atomics_legal_T_108 = or(_atomics_legal_T_107, _atomics_legal_T_93)
node _atomics_legal_T_109 = or(_atomics_legal_T_108, _atomics_legal_T_98)
node _atomics_legal_T_110 = or(_atomics_legal_T_109, _atomics_legal_T_103)
node _atomics_legal_T_111 = and(_atomics_legal_T_63, _atomics_legal_T_110)
node _atomics_legal_T_112 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_113 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_114 = cvt(_atomics_legal_T_113)
node _atomics_legal_T_115 = and(_atomics_legal_T_114, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_116 = asSInt(_atomics_legal_T_115)
node _atomics_legal_T_117 = eq(_atomics_legal_T_116, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_118 = and(_atomics_legal_T_112, _atomics_legal_T_117)
node _atomics_legal_T_119 = or(UInt<1>(0h0), _atomics_legal_T_111)
node atomics_legal_1 = or(_atomics_legal_T_119, _atomics_legal_T_118)
wire atomics_a_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_1.opcode, UInt<2>(0h3)
connect atomics_a_1.param, UInt<3>(0h0)
connect atomics_a_1.size, s2_req.size
connect atomics_a_1.source, a_source
connect atomics_a_1.address, s2_req.addr
node _atomics_a_mask_sizeOH_T_3 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_1 = bits(_atomics_a_mask_sizeOH_T_3, 1, 0)
node _atomics_a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_1)
node _atomics_a_mask_sizeOH_T_5 = bits(_atomics_a_mask_sizeOH_T_4, 2, 0)
node atomics_a_mask_sizeOH_1 = or(_atomics_a_mask_sizeOH_T_5, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_1 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 2, 2)
node atomics_a_mask_sub_sub_bit_1 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_1 = eq(atomics_a_mask_sub_sub_bit_1, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_1)
node _atomics_a_mask_sub_sub_acc_T_2 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_0_2_1)
node atomics_a_mask_sub_sub_0_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_2)
node atomics_a_mask_sub_sub_1_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_1)
node _atomics_a_mask_sub_sub_acc_T_3 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_1_2_1)
node atomics_a_mask_sub_sub_1_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_3)
node atomics_a_mask_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 1, 1)
node atomics_a_mask_sub_bit_1 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_1 = eq(atomics_a_mask_sub_bit_1, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_nbit_1)
node _atomics_a_mask_sub_acc_T_4 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_0_2_1)
node atomics_a_mask_sub_0_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_4)
node atomics_a_mask_sub_1_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_bit_1)
node _atomics_a_mask_sub_acc_T_5 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_1_2_1)
node atomics_a_mask_sub_1_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_5)
node atomics_a_mask_sub_2_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_nbit_1)
node _atomics_a_mask_sub_acc_T_6 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_2_2_1)
node atomics_a_mask_sub_2_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_6)
node atomics_a_mask_sub_3_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_bit_1)
node _atomics_a_mask_sub_acc_T_7 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_3_2_1)
node atomics_a_mask_sub_3_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_7)
node atomics_a_mask_size_1 = bits(atomics_a_mask_sizeOH_1, 0, 0)
node atomics_a_mask_bit_1 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_1 = eq(atomics_a_mask_bit_1, UInt<1>(0h0))
node atomics_a_mask_eq_8 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_8 = and(atomics_a_mask_size_1, atomics_a_mask_eq_8)
node atomics_a_mask_acc_8 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_8)
node atomics_a_mask_eq_9 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_9 = and(atomics_a_mask_size_1, atomics_a_mask_eq_9)
node atomics_a_mask_acc_9 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_9)
node atomics_a_mask_eq_10 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_10 = and(atomics_a_mask_size_1, atomics_a_mask_eq_10)
node atomics_a_mask_acc_10 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_10)
node atomics_a_mask_eq_11 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_11 = and(atomics_a_mask_size_1, atomics_a_mask_eq_11)
node atomics_a_mask_acc_11 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_11)
node atomics_a_mask_eq_12 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_12 = and(atomics_a_mask_size_1, atomics_a_mask_eq_12)
node atomics_a_mask_acc_12 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_12)
node atomics_a_mask_eq_13 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_13 = and(atomics_a_mask_size_1, atomics_a_mask_eq_13)
node atomics_a_mask_acc_13 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_13)
node atomics_a_mask_eq_14 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_14 = and(atomics_a_mask_size_1, atomics_a_mask_eq_14)
node atomics_a_mask_acc_14 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_14)
node atomics_a_mask_eq_15 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_15 = and(atomics_a_mask_size_1, atomics_a_mask_eq_15)
node atomics_a_mask_acc_15 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_15)
node atomics_a_mask_lo_lo_1 = cat(atomics_a_mask_acc_9, atomics_a_mask_acc_8)
node atomics_a_mask_lo_hi_1 = cat(atomics_a_mask_acc_11, atomics_a_mask_acc_10)
node atomics_a_mask_lo_1 = cat(atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1)
node atomics_a_mask_hi_lo_1 = cat(atomics_a_mask_acc_13, atomics_a_mask_acc_12)
node atomics_a_mask_hi_hi_1 = cat(atomics_a_mask_acc_15, atomics_a_mask_acc_14)
node atomics_a_mask_hi_1 = cat(atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1)
node _atomics_a_mask_T_1 = cat(atomics_a_mask_hi_1, atomics_a_mask_lo_1)
connect atomics_a_1.mask, _atomics_a_mask_T_1
connect atomics_a_1.data, pstore1_data
connect atomics_a_1.corrupt, UInt<1>(0h0)
node _atomics_legal_T_120 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_121 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_122 = and(_atomics_legal_T_120, _atomics_legal_T_121)
node _atomics_legal_T_123 = or(UInt<1>(0h0), _atomics_legal_T_122)
node _atomics_legal_T_124 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_125 = cvt(_atomics_legal_T_124)
node _atomics_legal_T_126 = and(_atomics_legal_T_125, asSInt(UInt<33>(0hfffd8000)))
node _atomics_legal_T_127 = asSInt(_atomics_legal_T_126)
node _atomics_legal_T_128 = eq(_atomics_legal_T_127, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_129 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_130 = cvt(_atomics_legal_T_129)
node _atomics_legal_T_131 = and(_atomics_legal_T_130, asSInt(UInt<33>(0hfffe9000)))
node _atomics_legal_T_132 = asSInt(_atomics_legal_T_131)
node _atomics_legal_T_133 = eq(_atomics_legal_T_132, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_134 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_135 = cvt(_atomics_legal_T_134)
node _atomics_legal_T_136 = and(_atomics_legal_T_135, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_137 = asSInt(_atomics_legal_T_136)
node _atomics_legal_T_138 = eq(_atomics_legal_T_137, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_139 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_140 = cvt(_atomics_legal_T_139)
node _atomics_legal_T_141 = and(_atomics_legal_T_140, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_142 = asSInt(_atomics_legal_T_141)
node _atomics_legal_T_143 = eq(_atomics_legal_T_142, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_144 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_145 = cvt(_atomics_legal_T_144)
node _atomics_legal_T_146 = and(_atomics_legal_T_145, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_147 = asSInt(_atomics_legal_T_146)
node _atomics_legal_T_148 = eq(_atomics_legal_T_147, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_149 = xor(s2_req.addr, UInt<28>(0hc000000))
node _atomics_legal_T_150 = cvt(_atomics_legal_T_149)
node _atomics_legal_T_151 = and(_atomics_legal_T_150, asSInt(UInt<33>(0hfc000000)))
node _atomics_legal_T_152 = asSInt(_atomics_legal_T_151)
node _atomics_legal_T_153 = eq(_atomics_legal_T_152, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_154 = xor(s2_req.addr, UInt<29>(0h10020000))
node _atomics_legal_T_155 = cvt(_atomics_legal_T_154)
node _atomics_legal_T_156 = and(_atomics_legal_T_155, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_157 = asSInt(_atomics_legal_T_156)
node _atomics_legal_T_158 = eq(_atomics_legal_T_157, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_159 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_160 = cvt(_atomics_legal_T_159)
node _atomics_legal_T_161 = and(_atomics_legal_T_160, asSInt(UInt<33>(0hf0000000)))
node _atomics_legal_T_162 = asSInt(_atomics_legal_T_161)
node _atomics_legal_T_163 = eq(_atomics_legal_T_162, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_164 = or(_atomics_legal_T_128, _atomics_legal_T_133)
node _atomics_legal_T_165 = or(_atomics_legal_T_164, _atomics_legal_T_138)
node _atomics_legal_T_166 = or(_atomics_legal_T_165, _atomics_legal_T_143)
node _atomics_legal_T_167 = or(_atomics_legal_T_166, _atomics_legal_T_148)
node _atomics_legal_T_168 = or(_atomics_legal_T_167, _atomics_legal_T_153)
node _atomics_legal_T_169 = or(_atomics_legal_T_168, _atomics_legal_T_158)
node _atomics_legal_T_170 = or(_atomics_legal_T_169, _atomics_legal_T_163)
node _atomics_legal_T_171 = and(_atomics_legal_T_123, _atomics_legal_T_170)
node _atomics_legal_T_172 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_173 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_174 = cvt(_atomics_legal_T_173)
node _atomics_legal_T_175 = and(_atomics_legal_T_174, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_176 = asSInt(_atomics_legal_T_175)
node _atomics_legal_T_177 = eq(_atomics_legal_T_176, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_178 = and(_atomics_legal_T_172, _atomics_legal_T_177)
node _atomics_legal_T_179 = or(UInt<1>(0h0), _atomics_legal_T_171)
node atomics_legal_2 = or(_atomics_legal_T_179, _atomics_legal_T_178)
wire atomics_a_2 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_2.opcode, UInt<2>(0h3)
connect atomics_a_2.param, UInt<3>(0h1)
connect atomics_a_2.size, s2_req.size
connect atomics_a_2.source, a_source
connect atomics_a_2.address, s2_req.addr
node _atomics_a_mask_sizeOH_T_6 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_2 = bits(_atomics_a_mask_sizeOH_T_6, 1, 0)
node _atomics_a_mask_sizeOH_T_7 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_2)
node _atomics_a_mask_sizeOH_T_8 = bits(_atomics_a_mask_sizeOH_T_7, 2, 0)
node atomics_a_mask_sizeOH_2 = or(_atomics_a_mask_sizeOH_T_8, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_2 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 2, 2)
node atomics_a_mask_sub_sub_bit_2 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_2 = eq(atomics_a_mask_sub_sub_bit_2, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_2)
node _atomics_a_mask_sub_sub_acc_T_4 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_0_2_2)
node atomics_a_mask_sub_sub_0_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_4)
node atomics_a_mask_sub_sub_1_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_2)
node _atomics_a_mask_sub_sub_acc_T_5 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_1_2_2)
node atomics_a_mask_sub_sub_1_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_5)
node atomics_a_mask_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 1, 1)
node atomics_a_mask_sub_bit_2 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_2 = eq(atomics_a_mask_sub_bit_2, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_nbit_2)
node _atomics_a_mask_sub_acc_T_8 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_0_2_2)
node atomics_a_mask_sub_0_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_8)
node atomics_a_mask_sub_1_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_bit_2)
node _atomics_a_mask_sub_acc_T_9 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_1_2_2)
node atomics_a_mask_sub_1_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_9)
node atomics_a_mask_sub_2_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_nbit_2)
node _atomics_a_mask_sub_acc_T_10 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_2_2_2)
node atomics_a_mask_sub_2_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_10)
node atomics_a_mask_sub_3_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_bit_2)
node _atomics_a_mask_sub_acc_T_11 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_3_2_2)
node atomics_a_mask_sub_3_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_11)
node atomics_a_mask_size_2 = bits(atomics_a_mask_sizeOH_2, 0, 0)
node atomics_a_mask_bit_2 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_2 = eq(atomics_a_mask_bit_2, UInt<1>(0h0))
node atomics_a_mask_eq_16 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_16 = and(atomics_a_mask_size_2, atomics_a_mask_eq_16)
node atomics_a_mask_acc_16 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_16)
node atomics_a_mask_eq_17 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_17 = and(atomics_a_mask_size_2, atomics_a_mask_eq_17)
node atomics_a_mask_acc_17 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_17)
node atomics_a_mask_eq_18 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_18 = and(atomics_a_mask_size_2, atomics_a_mask_eq_18)
node atomics_a_mask_acc_18 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_18)
node atomics_a_mask_eq_19 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_19 = and(atomics_a_mask_size_2, atomics_a_mask_eq_19)
node atomics_a_mask_acc_19 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_19)
node atomics_a_mask_eq_20 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_20 = and(atomics_a_mask_size_2, atomics_a_mask_eq_20)
node atomics_a_mask_acc_20 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_20)
node atomics_a_mask_eq_21 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_21 = and(atomics_a_mask_size_2, atomics_a_mask_eq_21)
node atomics_a_mask_acc_21 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_21)
node atomics_a_mask_eq_22 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_22 = and(atomics_a_mask_size_2, atomics_a_mask_eq_22)
node atomics_a_mask_acc_22 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_22)
node atomics_a_mask_eq_23 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_23 = and(atomics_a_mask_size_2, atomics_a_mask_eq_23)
node atomics_a_mask_acc_23 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_23)
node atomics_a_mask_lo_lo_2 = cat(atomics_a_mask_acc_17, atomics_a_mask_acc_16)
node atomics_a_mask_lo_hi_2 = cat(atomics_a_mask_acc_19, atomics_a_mask_acc_18)
node atomics_a_mask_lo_2 = cat(atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2)
node atomics_a_mask_hi_lo_2 = cat(atomics_a_mask_acc_21, atomics_a_mask_acc_20)
node atomics_a_mask_hi_hi_2 = cat(atomics_a_mask_acc_23, atomics_a_mask_acc_22)
node atomics_a_mask_hi_2 = cat(atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2)
node _atomics_a_mask_T_2 = cat(atomics_a_mask_hi_2, atomics_a_mask_lo_2)
connect atomics_a_2.mask, _atomics_a_mask_T_2
connect atomics_a_2.data, pstore1_data
connect atomics_a_2.corrupt, UInt<1>(0h0)
node _atomics_legal_T_180 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_181 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_182 = and(_atomics_legal_T_180, _atomics_legal_T_181)
node _atomics_legal_T_183 = or(UInt<1>(0h0), _atomics_legal_T_182)
node _atomics_legal_T_184 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_185 = cvt(_atomics_legal_T_184)
node _atomics_legal_T_186 = and(_atomics_legal_T_185, asSInt(UInt<33>(0hfffd8000)))
node _atomics_legal_T_187 = asSInt(_atomics_legal_T_186)
node _atomics_legal_T_188 = eq(_atomics_legal_T_187, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_189 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_190 = cvt(_atomics_legal_T_189)
node _atomics_legal_T_191 = and(_atomics_legal_T_190, asSInt(UInt<33>(0hfffe9000)))
node _atomics_legal_T_192 = asSInt(_atomics_legal_T_191)
node _atomics_legal_T_193 = eq(_atomics_legal_T_192, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_194 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_195 = cvt(_atomics_legal_T_194)
node _atomics_legal_T_196 = and(_atomics_legal_T_195, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_197 = asSInt(_atomics_legal_T_196)
node _atomics_legal_T_198 = eq(_atomics_legal_T_197, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_199 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_200 = cvt(_atomics_legal_T_199)
node _atomics_legal_T_201 = and(_atomics_legal_T_200, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_202 = asSInt(_atomics_legal_T_201)
node _atomics_legal_T_203 = eq(_atomics_legal_T_202, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_204 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_205 = cvt(_atomics_legal_T_204)
node _atomics_legal_T_206 = and(_atomics_legal_T_205, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_207 = asSInt(_atomics_legal_T_206)
node _atomics_legal_T_208 = eq(_atomics_legal_T_207, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_209 = xor(s2_req.addr, UInt<28>(0hc000000))
node _atomics_legal_T_210 = cvt(_atomics_legal_T_209)
node _atomics_legal_T_211 = and(_atomics_legal_T_210, asSInt(UInt<33>(0hfc000000)))
node _atomics_legal_T_212 = asSInt(_atomics_legal_T_211)
node _atomics_legal_T_213 = eq(_atomics_legal_T_212, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_214 = xor(s2_req.addr, UInt<29>(0h10020000))
node _atomics_legal_T_215 = cvt(_atomics_legal_T_214)
node _atomics_legal_T_216 = and(_atomics_legal_T_215, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_217 = asSInt(_atomics_legal_T_216)
node _atomics_legal_T_218 = eq(_atomics_legal_T_217, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_219 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_220 = cvt(_atomics_legal_T_219)
node _atomics_legal_T_221 = and(_atomics_legal_T_220, asSInt(UInt<33>(0hf0000000)))
node _atomics_legal_T_222 = asSInt(_atomics_legal_T_221)
node _atomics_legal_T_223 = eq(_atomics_legal_T_222, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_224 = or(_atomics_legal_T_188, _atomics_legal_T_193)
node _atomics_legal_T_225 = or(_atomics_legal_T_224, _atomics_legal_T_198)
node _atomics_legal_T_226 = or(_atomics_legal_T_225, _atomics_legal_T_203)
node _atomics_legal_T_227 = or(_atomics_legal_T_226, _atomics_legal_T_208)
node _atomics_legal_T_228 = or(_atomics_legal_T_227, _atomics_legal_T_213)
node _atomics_legal_T_229 = or(_atomics_legal_T_228, _atomics_legal_T_218)
node _atomics_legal_T_230 = or(_atomics_legal_T_229, _atomics_legal_T_223)
node _atomics_legal_T_231 = and(_atomics_legal_T_183, _atomics_legal_T_230)
node _atomics_legal_T_232 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_233 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_234 = cvt(_atomics_legal_T_233)
node _atomics_legal_T_235 = and(_atomics_legal_T_234, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_236 = asSInt(_atomics_legal_T_235)
node _atomics_legal_T_237 = eq(_atomics_legal_T_236, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_238 = and(_atomics_legal_T_232, _atomics_legal_T_237)
node _atomics_legal_T_239 = or(UInt<1>(0h0), _atomics_legal_T_231)
node atomics_legal_3 = or(_atomics_legal_T_239, _atomics_legal_T_238)
wire atomics_a_3 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_3.opcode, UInt<2>(0h3)
connect atomics_a_3.param, UInt<3>(0h2)
connect atomics_a_3.size, s2_req.size
connect atomics_a_3.source, a_source
connect atomics_a_3.address, s2_req.addr
node _atomics_a_mask_sizeOH_T_9 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_3 = bits(_atomics_a_mask_sizeOH_T_9, 1, 0)
node _atomics_a_mask_sizeOH_T_10 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_3)
node _atomics_a_mask_sizeOH_T_11 = bits(_atomics_a_mask_sizeOH_T_10, 2, 0)
node atomics_a_mask_sizeOH_3 = or(_atomics_a_mask_sizeOH_T_11, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_3 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 2, 2)
node atomics_a_mask_sub_sub_bit_3 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_3 = eq(atomics_a_mask_sub_sub_bit_3, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_3)
node _atomics_a_mask_sub_sub_acc_T_6 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_0_2_3)
node atomics_a_mask_sub_sub_0_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_6)
node atomics_a_mask_sub_sub_1_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_3)
node _atomics_a_mask_sub_sub_acc_T_7 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_1_2_3)
node atomics_a_mask_sub_sub_1_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_7)
node atomics_a_mask_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 1, 1)
node atomics_a_mask_sub_bit_3 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_3 = eq(atomics_a_mask_sub_bit_3, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_nbit_3)
node _atomics_a_mask_sub_acc_T_12 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_0_2_3)
node atomics_a_mask_sub_0_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_12)
node atomics_a_mask_sub_1_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_bit_3)
node _atomics_a_mask_sub_acc_T_13 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_1_2_3)
node atomics_a_mask_sub_1_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_13)
node atomics_a_mask_sub_2_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_nbit_3)
node _atomics_a_mask_sub_acc_T_14 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_2_2_3)
node atomics_a_mask_sub_2_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_14)
node atomics_a_mask_sub_3_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_bit_3)
node _atomics_a_mask_sub_acc_T_15 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_3_2_3)
node atomics_a_mask_sub_3_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_15)
node atomics_a_mask_size_3 = bits(atomics_a_mask_sizeOH_3, 0, 0)
node atomics_a_mask_bit_3 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_3 = eq(atomics_a_mask_bit_3, UInt<1>(0h0))
node atomics_a_mask_eq_24 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_24 = and(atomics_a_mask_size_3, atomics_a_mask_eq_24)
node atomics_a_mask_acc_24 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_24)
node atomics_a_mask_eq_25 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_25 = and(atomics_a_mask_size_3, atomics_a_mask_eq_25)
node atomics_a_mask_acc_25 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_25)
node atomics_a_mask_eq_26 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_26 = and(atomics_a_mask_size_3, atomics_a_mask_eq_26)
node atomics_a_mask_acc_26 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_26)
node atomics_a_mask_eq_27 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_27 = and(atomics_a_mask_size_3, atomics_a_mask_eq_27)
node atomics_a_mask_acc_27 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_27)
node atomics_a_mask_eq_28 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_28 = and(atomics_a_mask_size_3, atomics_a_mask_eq_28)
node atomics_a_mask_acc_28 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_28)
node atomics_a_mask_eq_29 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_29 = and(atomics_a_mask_size_3, atomics_a_mask_eq_29)
node atomics_a_mask_acc_29 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_29)
node atomics_a_mask_eq_30 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_30 = and(atomics_a_mask_size_3, atomics_a_mask_eq_30)
node atomics_a_mask_acc_30 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_30)
node atomics_a_mask_eq_31 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_31 = and(atomics_a_mask_size_3, atomics_a_mask_eq_31)
node atomics_a_mask_acc_31 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_31)
node atomics_a_mask_lo_lo_3 = cat(atomics_a_mask_acc_25, atomics_a_mask_acc_24)
node atomics_a_mask_lo_hi_3 = cat(atomics_a_mask_acc_27, atomics_a_mask_acc_26)
node atomics_a_mask_lo_3 = cat(atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3)
node atomics_a_mask_hi_lo_3 = cat(atomics_a_mask_acc_29, atomics_a_mask_acc_28)
node atomics_a_mask_hi_hi_3 = cat(atomics_a_mask_acc_31, atomics_a_mask_acc_30)
node atomics_a_mask_hi_3 = cat(atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3)
node _atomics_a_mask_T_3 = cat(atomics_a_mask_hi_3, atomics_a_mask_lo_3)
connect atomics_a_3.mask, _atomics_a_mask_T_3
connect atomics_a_3.data, pstore1_data
connect atomics_a_3.corrupt, UInt<1>(0h0)
node _atomics_legal_T_240 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_241 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_242 = and(_atomics_legal_T_240, _atomics_legal_T_241)
node _atomics_legal_T_243 = or(UInt<1>(0h0), _atomics_legal_T_242)
node _atomics_legal_T_244 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_245 = cvt(_atomics_legal_T_244)
node _atomics_legal_T_246 = and(_atomics_legal_T_245, asSInt(UInt<33>(0hfffd8000)))
node _atomics_legal_T_247 = asSInt(_atomics_legal_T_246)
node _atomics_legal_T_248 = eq(_atomics_legal_T_247, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_249 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_250 = cvt(_atomics_legal_T_249)
node _atomics_legal_T_251 = and(_atomics_legal_T_250, asSInt(UInt<33>(0hfffe9000)))
node _atomics_legal_T_252 = asSInt(_atomics_legal_T_251)
node _atomics_legal_T_253 = eq(_atomics_legal_T_252, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_254 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_255 = cvt(_atomics_legal_T_254)
node _atomics_legal_T_256 = and(_atomics_legal_T_255, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_257 = asSInt(_atomics_legal_T_256)
node _atomics_legal_T_258 = eq(_atomics_legal_T_257, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_259 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_260 = cvt(_atomics_legal_T_259)
node _atomics_legal_T_261 = and(_atomics_legal_T_260, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_262 = asSInt(_atomics_legal_T_261)
node _atomics_legal_T_263 = eq(_atomics_legal_T_262, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_264 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_265 = cvt(_atomics_legal_T_264)
node _atomics_legal_T_266 = and(_atomics_legal_T_265, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_267 = asSInt(_atomics_legal_T_266)
node _atomics_legal_T_268 = eq(_atomics_legal_T_267, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_269 = xor(s2_req.addr, UInt<28>(0hc000000))
node _atomics_legal_T_270 = cvt(_atomics_legal_T_269)
node _atomics_legal_T_271 = and(_atomics_legal_T_270, asSInt(UInt<33>(0hfc000000)))
node _atomics_legal_T_272 = asSInt(_atomics_legal_T_271)
node _atomics_legal_T_273 = eq(_atomics_legal_T_272, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_274 = xor(s2_req.addr, UInt<29>(0h10020000))
node _atomics_legal_T_275 = cvt(_atomics_legal_T_274)
node _atomics_legal_T_276 = and(_atomics_legal_T_275, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_277 = asSInt(_atomics_legal_T_276)
node _atomics_legal_T_278 = eq(_atomics_legal_T_277, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_279 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_280 = cvt(_atomics_legal_T_279)
node _atomics_legal_T_281 = and(_atomics_legal_T_280, asSInt(UInt<33>(0hf0000000)))
node _atomics_legal_T_282 = asSInt(_atomics_legal_T_281)
node _atomics_legal_T_283 = eq(_atomics_legal_T_282, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_284 = or(_atomics_legal_T_248, _atomics_legal_T_253)
node _atomics_legal_T_285 = or(_atomics_legal_T_284, _atomics_legal_T_258)
node _atomics_legal_T_286 = or(_atomics_legal_T_285, _atomics_legal_T_263)
node _atomics_legal_T_287 = or(_atomics_legal_T_286, _atomics_legal_T_268)
node _atomics_legal_T_288 = or(_atomics_legal_T_287, _atomics_legal_T_273)
node _atomics_legal_T_289 = or(_atomics_legal_T_288, _atomics_legal_T_278)
node _atomics_legal_T_290 = or(_atomics_legal_T_289, _atomics_legal_T_283)
node _atomics_legal_T_291 = and(_atomics_legal_T_243, _atomics_legal_T_290)
node _atomics_legal_T_292 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_293 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_294 = cvt(_atomics_legal_T_293)
node _atomics_legal_T_295 = and(_atomics_legal_T_294, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_296 = asSInt(_atomics_legal_T_295)
node _atomics_legal_T_297 = eq(_atomics_legal_T_296, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_298 = and(_atomics_legal_T_292, _atomics_legal_T_297)
node _atomics_legal_T_299 = or(UInt<1>(0h0), _atomics_legal_T_291)
node atomics_legal_4 = or(_atomics_legal_T_299, _atomics_legal_T_298)
wire atomics_a_4 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_4.opcode, UInt<2>(0h2)
connect atomics_a_4.param, UInt<3>(0h4)
connect atomics_a_4.size, s2_req.size
connect atomics_a_4.source, a_source
connect atomics_a_4.address, s2_req.addr
node _atomics_a_mask_sizeOH_T_12 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_4 = bits(_atomics_a_mask_sizeOH_T_12, 1, 0)
node _atomics_a_mask_sizeOH_T_13 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_4)
node _atomics_a_mask_sizeOH_T_14 = bits(_atomics_a_mask_sizeOH_T_13, 2, 0)
node atomics_a_mask_sizeOH_4 = or(_atomics_a_mask_sizeOH_T_14, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_4 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 2, 2)
node atomics_a_mask_sub_sub_bit_4 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_4 = eq(atomics_a_mask_sub_sub_bit_4, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_4)
node _atomics_a_mask_sub_sub_acc_T_8 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_0_2_4)
node atomics_a_mask_sub_sub_0_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_8)
node atomics_a_mask_sub_sub_1_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_4)
node _atomics_a_mask_sub_sub_acc_T_9 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_1_2_4)
node atomics_a_mask_sub_sub_1_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_9)
node atomics_a_mask_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 1, 1)
node atomics_a_mask_sub_bit_4 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_4 = eq(atomics_a_mask_sub_bit_4, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_nbit_4)
node _atomics_a_mask_sub_acc_T_16 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_0_2_4)
node atomics_a_mask_sub_0_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_16)
node atomics_a_mask_sub_1_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_bit_4)
node _atomics_a_mask_sub_acc_T_17 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_1_2_4)
node atomics_a_mask_sub_1_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_17)
node atomics_a_mask_sub_2_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_nbit_4)
node _atomics_a_mask_sub_acc_T_18 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_2_2_4)
node atomics_a_mask_sub_2_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_18)
node atomics_a_mask_sub_3_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_bit_4)
node _atomics_a_mask_sub_acc_T_19 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_3_2_4)
node atomics_a_mask_sub_3_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_19)
node atomics_a_mask_size_4 = bits(atomics_a_mask_sizeOH_4, 0, 0)
node atomics_a_mask_bit_4 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_4 = eq(atomics_a_mask_bit_4, UInt<1>(0h0))
node atomics_a_mask_eq_32 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_32 = and(atomics_a_mask_size_4, atomics_a_mask_eq_32)
node atomics_a_mask_acc_32 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_32)
node atomics_a_mask_eq_33 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_33 = and(atomics_a_mask_size_4, atomics_a_mask_eq_33)
node atomics_a_mask_acc_33 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_33)
node atomics_a_mask_eq_34 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_34 = and(atomics_a_mask_size_4, atomics_a_mask_eq_34)
node atomics_a_mask_acc_34 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_34)
node atomics_a_mask_eq_35 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_35 = and(atomics_a_mask_size_4, atomics_a_mask_eq_35)
node atomics_a_mask_acc_35 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_35)
node atomics_a_mask_eq_36 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_36 = and(atomics_a_mask_size_4, atomics_a_mask_eq_36)
node atomics_a_mask_acc_36 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_36)
node atomics_a_mask_eq_37 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_37 = and(atomics_a_mask_size_4, atomics_a_mask_eq_37)
node atomics_a_mask_acc_37 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_37)
node atomics_a_mask_eq_38 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_38 = and(atomics_a_mask_size_4, atomics_a_mask_eq_38)
node atomics_a_mask_acc_38 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_38)
node atomics_a_mask_eq_39 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_39 = and(atomics_a_mask_size_4, atomics_a_mask_eq_39)
node atomics_a_mask_acc_39 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_39)
node atomics_a_mask_lo_lo_4 = cat(atomics_a_mask_acc_33, atomics_a_mask_acc_32)
node atomics_a_mask_lo_hi_4 = cat(atomics_a_mask_acc_35, atomics_a_mask_acc_34)
node atomics_a_mask_lo_4 = cat(atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4)
node atomics_a_mask_hi_lo_4 = cat(atomics_a_mask_acc_37, atomics_a_mask_acc_36)
node atomics_a_mask_hi_hi_4 = cat(atomics_a_mask_acc_39, atomics_a_mask_acc_38)
node atomics_a_mask_hi_4 = cat(atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4)
node _atomics_a_mask_T_4 = cat(atomics_a_mask_hi_4, atomics_a_mask_lo_4)
connect atomics_a_4.mask, _atomics_a_mask_T_4
connect atomics_a_4.data, pstore1_data
connect atomics_a_4.corrupt, UInt<1>(0h0)
node _atomics_legal_T_300 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_301 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_302 = and(_atomics_legal_T_300, _atomics_legal_T_301)
node _atomics_legal_T_303 = or(UInt<1>(0h0), _atomics_legal_T_302)
node _atomics_legal_T_304 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_305 = cvt(_atomics_legal_T_304)
node _atomics_legal_T_306 = and(_atomics_legal_T_305, asSInt(UInt<33>(0hfffd8000)))
node _atomics_legal_T_307 = asSInt(_atomics_legal_T_306)
node _atomics_legal_T_308 = eq(_atomics_legal_T_307, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_309 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_310 = cvt(_atomics_legal_T_309)
node _atomics_legal_T_311 = and(_atomics_legal_T_310, asSInt(UInt<33>(0hfffe9000)))
node _atomics_legal_T_312 = asSInt(_atomics_legal_T_311)
node _atomics_legal_T_313 = eq(_atomics_legal_T_312, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_314 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_315 = cvt(_atomics_legal_T_314)
node _atomics_legal_T_316 = and(_atomics_legal_T_315, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_317 = asSInt(_atomics_legal_T_316)
node _atomics_legal_T_318 = eq(_atomics_legal_T_317, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_319 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_320 = cvt(_atomics_legal_T_319)
node _atomics_legal_T_321 = and(_atomics_legal_T_320, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_322 = asSInt(_atomics_legal_T_321)
node _atomics_legal_T_323 = eq(_atomics_legal_T_322, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_324 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_325 = cvt(_atomics_legal_T_324)
node _atomics_legal_T_326 = and(_atomics_legal_T_325, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_327 = asSInt(_atomics_legal_T_326)
node _atomics_legal_T_328 = eq(_atomics_legal_T_327, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_329 = xor(s2_req.addr, UInt<28>(0hc000000))
node _atomics_legal_T_330 = cvt(_atomics_legal_T_329)
node _atomics_legal_T_331 = and(_atomics_legal_T_330, asSInt(UInt<33>(0hfc000000)))
node _atomics_legal_T_332 = asSInt(_atomics_legal_T_331)
node _atomics_legal_T_333 = eq(_atomics_legal_T_332, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_334 = xor(s2_req.addr, UInt<29>(0h10020000))
node _atomics_legal_T_335 = cvt(_atomics_legal_T_334)
node _atomics_legal_T_336 = and(_atomics_legal_T_335, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_337 = asSInt(_atomics_legal_T_336)
node _atomics_legal_T_338 = eq(_atomics_legal_T_337, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_339 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_340 = cvt(_atomics_legal_T_339)
node _atomics_legal_T_341 = and(_atomics_legal_T_340, asSInt(UInt<33>(0hf0000000)))
node _atomics_legal_T_342 = asSInt(_atomics_legal_T_341)
node _atomics_legal_T_343 = eq(_atomics_legal_T_342, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_344 = or(_atomics_legal_T_308, _atomics_legal_T_313)
node _atomics_legal_T_345 = or(_atomics_legal_T_344, _atomics_legal_T_318)
node _atomics_legal_T_346 = or(_atomics_legal_T_345, _atomics_legal_T_323)
node _atomics_legal_T_347 = or(_atomics_legal_T_346, _atomics_legal_T_328)
node _atomics_legal_T_348 = or(_atomics_legal_T_347, _atomics_legal_T_333)
node _atomics_legal_T_349 = or(_atomics_legal_T_348, _atomics_legal_T_338)
node _atomics_legal_T_350 = or(_atomics_legal_T_349, _atomics_legal_T_343)
node _atomics_legal_T_351 = and(_atomics_legal_T_303, _atomics_legal_T_350)
node _atomics_legal_T_352 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_353 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_354 = cvt(_atomics_legal_T_353)
node _atomics_legal_T_355 = and(_atomics_legal_T_354, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_356 = asSInt(_atomics_legal_T_355)
node _atomics_legal_T_357 = eq(_atomics_legal_T_356, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_358 = and(_atomics_legal_T_352, _atomics_legal_T_357)
node _atomics_legal_T_359 = or(UInt<1>(0h0), _atomics_legal_T_351)
node atomics_legal_5 = or(_atomics_legal_T_359, _atomics_legal_T_358)
wire atomics_a_5 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_5.opcode, UInt<2>(0h2)
connect atomics_a_5.param, UInt<3>(0h0)
connect atomics_a_5.size, s2_req.size
connect atomics_a_5.source, a_source
connect atomics_a_5.address, s2_req.addr
node _atomics_a_mask_sizeOH_T_15 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_5 = bits(_atomics_a_mask_sizeOH_T_15, 1, 0)
node _atomics_a_mask_sizeOH_T_16 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_5)
node _atomics_a_mask_sizeOH_T_17 = bits(_atomics_a_mask_sizeOH_T_16, 2, 0)
node atomics_a_mask_sizeOH_5 = or(_atomics_a_mask_sizeOH_T_17, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_5 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 2, 2)
node atomics_a_mask_sub_sub_bit_5 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_5 = eq(atomics_a_mask_sub_sub_bit_5, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_5)
node _atomics_a_mask_sub_sub_acc_T_10 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_0_2_5)
node atomics_a_mask_sub_sub_0_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_10)
node atomics_a_mask_sub_sub_1_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_5)
node _atomics_a_mask_sub_sub_acc_T_11 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_1_2_5)
node atomics_a_mask_sub_sub_1_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_11)
node atomics_a_mask_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 1, 1)
node atomics_a_mask_sub_bit_5 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_5 = eq(atomics_a_mask_sub_bit_5, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_nbit_5)
node _atomics_a_mask_sub_acc_T_20 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_0_2_5)
node atomics_a_mask_sub_0_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_20)
node atomics_a_mask_sub_1_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_bit_5)
node _atomics_a_mask_sub_acc_T_21 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_1_2_5)
node atomics_a_mask_sub_1_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_21)
node atomics_a_mask_sub_2_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_nbit_5)
node _atomics_a_mask_sub_acc_T_22 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_2_2_5)
node atomics_a_mask_sub_2_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_22)
node atomics_a_mask_sub_3_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_bit_5)
node _atomics_a_mask_sub_acc_T_23 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_3_2_5)
node atomics_a_mask_sub_3_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_23)
node atomics_a_mask_size_5 = bits(atomics_a_mask_sizeOH_5, 0, 0)
node atomics_a_mask_bit_5 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_5 = eq(atomics_a_mask_bit_5, UInt<1>(0h0))
node atomics_a_mask_eq_40 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_40 = and(atomics_a_mask_size_5, atomics_a_mask_eq_40)
node atomics_a_mask_acc_40 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_40)
node atomics_a_mask_eq_41 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_41 = and(atomics_a_mask_size_5, atomics_a_mask_eq_41)
node atomics_a_mask_acc_41 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_41)
node atomics_a_mask_eq_42 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_42 = and(atomics_a_mask_size_5, atomics_a_mask_eq_42)
node atomics_a_mask_acc_42 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_42)
node atomics_a_mask_eq_43 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_43 = and(atomics_a_mask_size_5, atomics_a_mask_eq_43)
node atomics_a_mask_acc_43 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_43)
node atomics_a_mask_eq_44 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_44 = and(atomics_a_mask_size_5, atomics_a_mask_eq_44)
node atomics_a_mask_acc_44 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_44)
node atomics_a_mask_eq_45 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_45 = and(atomics_a_mask_size_5, atomics_a_mask_eq_45)
node atomics_a_mask_acc_45 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_45)
node atomics_a_mask_eq_46 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_46 = and(atomics_a_mask_size_5, atomics_a_mask_eq_46)
node atomics_a_mask_acc_46 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_46)
node atomics_a_mask_eq_47 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_47 = and(atomics_a_mask_size_5, atomics_a_mask_eq_47)
node atomics_a_mask_acc_47 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_47)
node atomics_a_mask_lo_lo_5 = cat(atomics_a_mask_acc_41, atomics_a_mask_acc_40)
node atomics_a_mask_lo_hi_5 = cat(atomics_a_mask_acc_43, atomics_a_mask_acc_42)
node atomics_a_mask_lo_5 = cat(atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5)
node atomics_a_mask_hi_lo_5 = cat(atomics_a_mask_acc_45, atomics_a_mask_acc_44)
node atomics_a_mask_hi_hi_5 = cat(atomics_a_mask_acc_47, atomics_a_mask_acc_46)
node atomics_a_mask_hi_5 = cat(atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5)
node _atomics_a_mask_T_5 = cat(atomics_a_mask_hi_5, atomics_a_mask_lo_5)
connect atomics_a_5.mask, _atomics_a_mask_T_5
connect atomics_a_5.data, pstore1_data
connect atomics_a_5.corrupt, UInt<1>(0h0)
node _atomics_legal_T_360 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_361 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_362 = and(_atomics_legal_T_360, _atomics_legal_T_361)
node _atomics_legal_T_363 = or(UInt<1>(0h0), _atomics_legal_T_362)
node _atomics_legal_T_364 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_365 = cvt(_atomics_legal_T_364)
node _atomics_legal_T_366 = and(_atomics_legal_T_365, asSInt(UInt<33>(0hfffd8000)))
node _atomics_legal_T_367 = asSInt(_atomics_legal_T_366)
node _atomics_legal_T_368 = eq(_atomics_legal_T_367, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_369 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_370 = cvt(_atomics_legal_T_369)
node _atomics_legal_T_371 = and(_atomics_legal_T_370, asSInt(UInt<33>(0hfffe9000)))
node _atomics_legal_T_372 = asSInt(_atomics_legal_T_371)
node _atomics_legal_T_373 = eq(_atomics_legal_T_372, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_374 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_375 = cvt(_atomics_legal_T_374)
node _atomics_legal_T_376 = and(_atomics_legal_T_375, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_377 = asSInt(_atomics_legal_T_376)
node _atomics_legal_T_378 = eq(_atomics_legal_T_377, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_379 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_380 = cvt(_atomics_legal_T_379)
node _atomics_legal_T_381 = and(_atomics_legal_T_380, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_382 = asSInt(_atomics_legal_T_381)
node _atomics_legal_T_383 = eq(_atomics_legal_T_382, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_384 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_385 = cvt(_atomics_legal_T_384)
node _atomics_legal_T_386 = and(_atomics_legal_T_385, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_387 = asSInt(_atomics_legal_T_386)
node _atomics_legal_T_388 = eq(_atomics_legal_T_387, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_389 = xor(s2_req.addr, UInt<28>(0hc000000))
node _atomics_legal_T_390 = cvt(_atomics_legal_T_389)
node _atomics_legal_T_391 = and(_atomics_legal_T_390, asSInt(UInt<33>(0hfc000000)))
node _atomics_legal_T_392 = asSInt(_atomics_legal_T_391)
node _atomics_legal_T_393 = eq(_atomics_legal_T_392, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_394 = xor(s2_req.addr, UInt<29>(0h10020000))
node _atomics_legal_T_395 = cvt(_atomics_legal_T_394)
node _atomics_legal_T_396 = and(_atomics_legal_T_395, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_397 = asSInt(_atomics_legal_T_396)
node _atomics_legal_T_398 = eq(_atomics_legal_T_397, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_399 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_400 = cvt(_atomics_legal_T_399)
node _atomics_legal_T_401 = and(_atomics_legal_T_400, asSInt(UInt<33>(0hf0000000)))
node _atomics_legal_T_402 = asSInt(_atomics_legal_T_401)
node _atomics_legal_T_403 = eq(_atomics_legal_T_402, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_404 = or(_atomics_legal_T_368, _atomics_legal_T_373)
node _atomics_legal_T_405 = or(_atomics_legal_T_404, _atomics_legal_T_378)
node _atomics_legal_T_406 = or(_atomics_legal_T_405, _atomics_legal_T_383)
node _atomics_legal_T_407 = or(_atomics_legal_T_406, _atomics_legal_T_388)
node _atomics_legal_T_408 = or(_atomics_legal_T_407, _atomics_legal_T_393)
node _atomics_legal_T_409 = or(_atomics_legal_T_408, _atomics_legal_T_398)
node _atomics_legal_T_410 = or(_atomics_legal_T_409, _atomics_legal_T_403)
node _atomics_legal_T_411 = and(_atomics_legal_T_363, _atomics_legal_T_410)
node _atomics_legal_T_412 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_413 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_414 = cvt(_atomics_legal_T_413)
node _atomics_legal_T_415 = and(_atomics_legal_T_414, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_416 = asSInt(_atomics_legal_T_415)
node _atomics_legal_T_417 = eq(_atomics_legal_T_416, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_418 = and(_atomics_legal_T_412, _atomics_legal_T_417)
node _atomics_legal_T_419 = or(UInt<1>(0h0), _atomics_legal_T_411)
node atomics_legal_6 = or(_atomics_legal_T_419, _atomics_legal_T_418)
wire atomics_a_6 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_6.opcode, UInt<2>(0h2)
connect atomics_a_6.param, UInt<3>(0h1)
connect atomics_a_6.size, s2_req.size
connect atomics_a_6.source, a_source
connect atomics_a_6.address, s2_req.addr
node _atomics_a_mask_sizeOH_T_18 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_6 = bits(_atomics_a_mask_sizeOH_T_18, 1, 0)
node _atomics_a_mask_sizeOH_T_19 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_6)
node _atomics_a_mask_sizeOH_T_20 = bits(_atomics_a_mask_sizeOH_T_19, 2, 0)
node atomics_a_mask_sizeOH_6 = or(_atomics_a_mask_sizeOH_T_20, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_6 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 2, 2)
node atomics_a_mask_sub_sub_bit_6 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_6 = eq(atomics_a_mask_sub_sub_bit_6, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_6)
node _atomics_a_mask_sub_sub_acc_T_12 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_0_2_6)
node atomics_a_mask_sub_sub_0_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_12)
node atomics_a_mask_sub_sub_1_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_6)
node _atomics_a_mask_sub_sub_acc_T_13 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_1_2_6)
node atomics_a_mask_sub_sub_1_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_13)
node atomics_a_mask_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 1, 1)
node atomics_a_mask_sub_bit_6 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_6 = eq(atomics_a_mask_sub_bit_6, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_nbit_6)
node _atomics_a_mask_sub_acc_T_24 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_0_2_6)
node atomics_a_mask_sub_0_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_24)
node atomics_a_mask_sub_1_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_bit_6)
node _atomics_a_mask_sub_acc_T_25 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_1_2_6)
node atomics_a_mask_sub_1_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_25)
node atomics_a_mask_sub_2_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_nbit_6)
node _atomics_a_mask_sub_acc_T_26 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_2_2_6)
node atomics_a_mask_sub_2_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_26)
node atomics_a_mask_sub_3_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_bit_6)
node _atomics_a_mask_sub_acc_T_27 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_3_2_6)
node atomics_a_mask_sub_3_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_27)
node atomics_a_mask_size_6 = bits(atomics_a_mask_sizeOH_6, 0, 0)
node atomics_a_mask_bit_6 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_6 = eq(atomics_a_mask_bit_6, UInt<1>(0h0))
node atomics_a_mask_eq_48 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_48 = and(atomics_a_mask_size_6, atomics_a_mask_eq_48)
node atomics_a_mask_acc_48 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_48)
node atomics_a_mask_eq_49 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_49 = and(atomics_a_mask_size_6, atomics_a_mask_eq_49)
node atomics_a_mask_acc_49 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_49)
node atomics_a_mask_eq_50 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_50 = and(atomics_a_mask_size_6, atomics_a_mask_eq_50)
node atomics_a_mask_acc_50 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_50)
node atomics_a_mask_eq_51 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_51 = and(atomics_a_mask_size_6, atomics_a_mask_eq_51)
node atomics_a_mask_acc_51 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_51)
node atomics_a_mask_eq_52 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_52 = and(atomics_a_mask_size_6, atomics_a_mask_eq_52)
node atomics_a_mask_acc_52 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_52)
node atomics_a_mask_eq_53 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_53 = and(atomics_a_mask_size_6, atomics_a_mask_eq_53)
node atomics_a_mask_acc_53 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_53)
node atomics_a_mask_eq_54 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_54 = and(atomics_a_mask_size_6, atomics_a_mask_eq_54)
node atomics_a_mask_acc_54 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_54)
node atomics_a_mask_eq_55 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_55 = and(atomics_a_mask_size_6, atomics_a_mask_eq_55)
node atomics_a_mask_acc_55 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_55)
node atomics_a_mask_lo_lo_6 = cat(atomics_a_mask_acc_49, atomics_a_mask_acc_48)
node atomics_a_mask_lo_hi_6 = cat(atomics_a_mask_acc_51, atomics_a_mask_acc_50)
node atomics_a_mask_lo_6 = cat(atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6)
node atomics_a_mask_hi_lo_6 = cat(atomics_a_mask_acc_53, atomics_a_mask_acc_52)
node atomics_a_mask_hi_hi_6 = cat(atomics_a_mask_acc_55, atomics_a_mask_acc_54)
node atomics_a_mask_hi_6 = cat(atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6)
node _atomics_a_mask_T_6 = cat(atomics_a_mask_hi_6, atomics_a_mask_lo_6)
connect atomics_a_6.mask, _atomics_a_mask_T_6
connect atomics_a_6.data, pstore1_data
connect atomics_a_6.corrupt, UInt<1>(0h0)
node _atomics_legal_T_420 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_421 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_422 = and(_atomics_legal_T_420, _atomics_legal_T_421)
node _atomics_legal_T_423 = or(UInt<1>(0h0), _atomics_legal_T_422)
node _atomics_legal_T_424 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_425 = cvt(_atomics_legal_T_424)
node _atomics_legal_T_426 = and(_atomics_legal_T_425, asSInt(UInt<33>(0hfffd8000)))
node _atomics_legal_T_427 = asSInt(_atomics_legal_T_426)
node _atomics_legal_T_428 = eq(_atomics_legal_T_427, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_429 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_430 = cvt(_atomics_legal_T_429)
node _atomics_legal_T_431 = and(_atomics_legal_T_430, asSInt(UInt<33>(0hfffe9000)))
node _atomics_legal_T_432 = asSInt(_atomics_legal_T_431)
node _atomics_legal_T_433 = eq(_atomics_legal_T_432, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_434 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_435 = cvt(_atomics_legal_T_434)
node _atomics_legal_T_436 = and(_atomics_legal_T_435, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_437 = asSInt(_atomics_legal_T_436)
node _atomics_legal_T_438 = eq(_atomics_legal_T_437, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_439 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_440 = cvt(_atomics_legal_T_439)
node _atomics_legal_T_441 = and(_atomics_legal_T_440, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_442 = asSInt(_atomics_legal_T_441)
node _atomics_legal_T_443 = eq(_atomics_legal_T_442, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_444 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_445 = cvt(_atomics_legal_T_444)
node _atomics_legal_T_446 = and(_atomics_legal_T_445, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_447 = asSInt(_atomics_legal_T_446)
node _atomics_legal_T_448 = eq(_atomics_legal_T_447, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_449 = xor(s2_req.addr, UInt<28>(0hc000000))
node _atomics_legal_T_450 = cvt(_atomics_legal_T_449)
node _atomics_legal_T_451 = and(_atomics_legal_T_450, asSInt(UInt<33>(0hfc000000)))
node _atomics_legal_T_452 = asSInt(_atomics_legal_T_451)
node _atomics_legal_T_453 = eq(_atomics_legal_T_452, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_454 = xor(s2_req.addr, UInt<29>(0h10020000))
node _atomics_legal_T_455 = cvt(_atomics_legal_T_454)
node _atomics_legal_T_456 = and(_atomics_legal_T_455, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_457 = asSInt(_atomics_legal_T_456)
node _atomics_legal_T_458 = eq(_atomics_legal_T_457, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_459 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_460 = cvt(_atomics_legal_T_459)
node _atomics_legal_T_461 = and(_atomics_legal_T_460, asSInt(UInt<33>(0hf0000000)))
node _atomics_legal_T_462 = asSInt(_atomics_legal_T_461)
node _atomics_legal_T_463 = eq(_atomics_legal_T_462, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_464 = or(_atomics_legal_T_428, _atomics_legal_T_433)
node _atomics_legal_T_465 = or(_atomics_legal_T_464, _atomics_legal_T_438)
node _atomics_legal_T_466 = or(_atomics_legal_T_465, _atomics_legal_T_443)
node _atomics_legal_T_467 = or(_atomics_legal_T_466, _atomics_legal_T_448)
node _atomics_legal_T_468 = or(_atomics_legal_T_467, _atomics_legal_T_453)
node _atomics_legal_T_469 = or(_atomics_legal_T_468, _atomics_legal_T_458)
node _atomics_legal_T_470 = or(_atomics_legal_T_469, _atomics_legal_T_463)
node _atomics_legal_T_471 = and(_atomics_legal_T_423, _atomics_legal_T_470)
node _atomics_legal_T_472 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_473 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_474 = cvt(_atomics_legal_T_473)
node _atomics_legal_T_475 = and(_atomics_legal_T_474, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_476 = asSInt(_atomics_legal_T_475)
node _atomics_legal_T_477 = eq(_atomics_legal_T_476, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_478 = and(_atomics_legal_T_472, _atomics_legal_T_477)
node _atomics_legal_T_479 = or(UInt<1>(0h0), _atomics_legal_T_471)
node atomics_legal_7 = or(_atomics_legal_T_479, _atomics_legal_T_478)
wire atomics_a_7 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_7.opcode, UInt<2>(0h2)
connect atomics_a_7.param, UInt<3>(0h2)
connect atomics_a_7.size, s2_req.size
connect atomics_a_7.source, a_source
connect atomics_a_7.address, s2_req.addr
node _atomics_a_mask_sizeOH_T_21 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_7 = bits(_atomics_a_mask_sizeOH_T_21, 1, 0)
node _atomics_a_mask_sizeOH_T_22 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_7)
node _atomics_a_mask_sizeOH_T_23 = bits(_atomics_a_mask_sizeOH_T_22, 2, 0)
node atomics_a_mask_sizeOH_7 = or(_atomics_a_mask_sizeOH_T_23, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_7 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 2, 2)
node atomics_a_mask_sub_sub_bit_7 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_7 = eq(atomics_a_mask_sub_sub_bit_7, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_7)
node _atomics_a_mask_sub_sub_acc_T_14 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_0_2_7)
node atomics_a_mask_sub_sub_0_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_14)
node atomics_a_mask_sub_sub_1_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_7)
node _atomics_a_mask_sub_sub_acc_T_15 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_1_2_7)
node atomics_a_mask_sub_sub_1_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_15)
node atomics_a_mask_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 1, 1)
node atomics_a_mask_sub_bit_7 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_7 = eq(atomics_a_mask_sub_bit_7, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_nbit_7)
node _atomics_a_mask_sub_acc_T_28 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_0_2_7)
node atomics_a_mask_sub_0_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_28)
node atomics_a_mask_sub_1_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_bit_7)
node _atomics_a_mask_sub_acc_T_29 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_1_2_7)
node atomics_a_mask_sub_1_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_29)
node atomics_a_mask_sub_2_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_nbit_7)
node _atomics_a_mask_sub_acc_T_30 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_2_2_7)
node atomics_a_mask_sub_2_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_30)
node atomics_a_mask_sub_3_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_bit_7)
node _atomics_a_mask_sub_acc_T_31 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_3_2_7)
node atomics_a_mask_sub_3_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_31)
node atomics_a_mask_size_7 = bits(atomics_a_mask_sizeOH_7, 0, 0)
node atomics_a_mask_bit_7 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_7 = eq(atomics_a_mask_bit_7, UInt<1>(0h0))
node atomics_a_mask_eq_56 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_56 = and(atomics_a_mask_size_7, atomics_a_mask_eq_56)
node atomics_a_mask_acc_56 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_56)
node atomics_a_mask_eq_57 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_57 = and(atomics_a_mask_size_7, atomics_a_mask_eq_57)
node atomics_a_mask_acc_57 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_57)
node atomics_a_mask_eq_58 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_58 = and(atomics_a_mask_size_7, atomics_a_mask_eq_58)
node atomics_a_mask_acc_58 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_58)
node atomics_a_mask_eq_59 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_59 = and(atomics_a_mask_size_7, atomics_a_mask_eq_59)
node atomics_a_mask_acc_59 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_59)
node atomics_a_mask_eq_60 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_60 = and(atomics_a_mask_size_7, atomics_a_mask_eq_60)
node atomics_a_mask_acc_60 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_60)
node atomics_a_mask_eq_61 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_61 = and(atomics_a_mask_size_7, atomics_a_mask_eq_61)
node atomics_a_mask_acc_61 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_61)
node atomics_a_mask_eq_62 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_62 = and(atomics_a_mask_size_7, atomics_a_mask_eq_62)
node atomics_a_mask_acc_62 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_62)
node atomics_a_mask_eq_63 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_63 = and(atomics_a_mask_size_7, atomics_a_mask_eq_63)
node atomics_a_mask_acc_63 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_63)
node atomics_a_mask_lo_lo_7 = cat(atomics_a_mask_acc_57, atomics_a_mask_acc_56)
node atomics_a_mask_lo_hi_7 = cat(atomics_a_mask_acc_59, atomics_a_mask_acc_58)
node atomics_a_mask_lo_7 = cat(atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7)
node atomics_a_mask_hi_lo_7 = cat(atomics_a_mask_acc_61, atomics_a_mask_acc_60)
node atomics_a_mask_hi_hi_7 = cat(atomics_a_mask_acc_63, atomics_a_mask_acc_62)
node atomics_a_mask_hi_7 = cat(atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7)
node _atomics_a_mask_T_7 = cat(atomics_a_mask_hi_7, atomics_a_mask_lo_7)
connect atomics_a_7.mask, _atomics_a_mask_T_7
connect atomics_a_7.data, pstore1_data
connect atomics_a_7.corrupt, UInt<1>(0h0)
node _atomics_legal_T_480 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_481 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_482 = and(_atomics_legal_T_480, _atomics_legal_T_481)
node _atomics_legal_T_483 = or(UInt<1>(0h0), _atomics_legal_T_482)
node _atomics_legal_T_484 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_485 = cvt(_atomics_legal_T_484)
node _atomics_legal_T_486 = and(_atomics_legal_T_485, asSInt(UInt<33>(0hfffd8000)))
node _atomics_legal_T_487 = asSInt(_atomics_legal_T_486)
node _atomics_legal_T_488 = eq(_atomics_legal_T_487, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_489 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_490 = cvt(_atomics_legal_T_489)
node _atomics_legal_T_491 = and(_atomics_legal_T_490, asSInt(UInt<33>(0hfffe9000)))
node _atomics_legal_T_492 = asSInt(_atomics_legal_T_491)
node _atomics_legal_T_493 = eq(_atomics_legal_T_492, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_494 = xor(s2_req.addr, UInt<26>(0h2000000))
node _atomics_legal_T_495 = cvt(_atomics_legal_T_494)
node _atomics_legal_T_496 = and(_atomics_legal_T_495, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_497 = asSInt(_atomics_legal_T_496)
node _atomics_legal_T_498 = eq(_atomics_legal_T_497, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_499 = xor(s2_req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_500 = cvt(_atomics_legal_T_499)
node _atomics_legal_T_501 = and(_atomics_legal_T_500, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_502 = asSInt(_atomics_legal_T_501)
node _atomics_legal_T_503 = eq(_atomics_legal_T_502, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_504 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_505 = cvt(_atomics_legal_T_504)
node _atomics_legal_T_506 = and(_atomics_legal_T_505, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_507 = asSInt(_atomics_legal_T_506)
node _atomics_legal_T_508 = eq(_atomics_legal_T_507, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_509 = xor(s2_req.addr, UInt<28>(0hc000000))
node _atomics_legal_T_510 = cvt(_atomics_legal_T_509)
node _atomics_legal_T_511 = and(_atomics_legal_T_510, asSInt(UInt<33>(0hfc000000)))
node _atomics_legal_T_512 = asSInt(_atomics_legal_T_511)
node _atomics_legal_T_513 = eq(_atomics_legal_T_512, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_514 = xor(s2_req.addr, UInt<29>(0h10020000))
node _atomics_legal_T_515 = cvt(_atomics_legal_T_514)
node _atomics_legal_T_516 = and(_atomics_legal_T_515, asSInt(UInt<33>(0hffff9000)))
node _atomics_legal_T_517 = asSInt(_atomics_legal_T_516)
node _atomics_legal_T_518 = eq(_atomics_legal_T_517, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_519 = xor(s2_req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_520 = cvt(_atomics_legal_T_519)
node _atomics_legal_T_521 = and(_atomics_legal_T_520, asSInt(UInt<33>(0hf0000000)))
node _atomics_legal_T_522 = asSInt(_atomics_legal_T_521)
node _atomics_legal_T_523 = eq(_atomics_legal_T_522, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_524 = or(_atomics_legal_T_488, _atomics_legal_T_493)
node _atomics_legal_T_525 = or(_atomics_legal_T_524, _atomics_legal_T_498)
node _atomics_legal_T_526 = or(_atomics_legal_T_525, _atomics_legal_T_503)
node _atomics_legal_T_527 = or(_atomics_legal_T_526, _atomics_legal_T_508)
node _atomics_legal_T_528 = or(_atomics_legal_T_527, _atomics_legal_T_513)
node _atomics_legal_T_529 = or(_atomics_legal_T_528, _atomics_legal_T_518)
node _atomics_legal_T_530 = or(_atomics_legal_T_529, _atomics_legal_T_523)
node _atomics_legal_T_531 = and(_atomics_legal_T_483, _atomics_legal_T_530)
node _atomics_legal_T_532 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_533 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_534 = cvt(_atomics_legal_T_533)
node _atomics_legal_T_535 = and(_atomics_legal_T_534, asSInt(UInt<33>(0hffff0000)))
node _atomics_legal_T_536 = asSInt(_atomics_legal_T_535)
node _atomics_legal_T_537 = eq(_atomics_legal_T_536, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_538 = and(_atomics_legal_T_532, _atomics_legal_T_537)
node _atomics_legal_T_539 = or(UInt<1>(0h0), _atomics_legal_T_531)
node atomics_legal_8 = or(_atomics_legal_T_539, _atomics_legal_T_538)
wire atomics_a_8 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_8.opcode, UInt<2>(0h2)
connect atomics_a_8.param, UInt<3>(0h3)
connect atomics_a_8.size, s2_req.size
connect atomics_a_8.source, a_source
connect atomics_a_8.address, s2_req.addr
node _atomics_a_mask_sizeOH_T_24 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_8 = bits(_atomics_a_mask_sizeOH_T_24, 1, 0)
node _atomics_a_mask_sizeOH_T_25 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_8)
node _atomics_a_mask_sizeOH_T_26 = bits(_atomics_a_mask_sizeOH_T_25, 2, 0)
node atomics_a_mask_sizeOH_8 = or(_atomics_a_mask_sizeOH_T_26, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_8 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 2, 2)
node atomics_a_mask_sub_sub_bit_8 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_8 = eq(atomics_a_mask_sub_sub_bit_8, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_8)
node _atomics_a_mask_sub_sub_acc_T_16 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_0_2_8)
node atomics_a_mask_sub_sub_0_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_16)
node atomics_a_mask_sub_sub_1_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_8)
node _atomics_a_mask_sub_sub_acc_T_17 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_1_2_8)
node atomics_a_mask_sub_sub_1_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_17)
node atomics_a_mask_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 1, 1)
node atomics_a_mask_sub_bit_8 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_8 = eq(atomics_a_mask_sub_bit_8, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_nbit_8)
node _atomics_a_mask_sub_acc_T_32 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_0_2_8)
node atomics_a_mask_sub_0_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_32)
node atomics_a_mask_sub_1_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_bit_8)
node _atomics_a_mask_sub_acc_T_33 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_1_2_8)
node atomics_a_mask_sub_1_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_33)
node atomics_a_mask_sub_2_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_nbit_8)
node _atomics_a_mask_sub_acc_T_34 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_2_2_8)
node atomics_a_mask_sub_2_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_34)
node atomics_a_mask_sub_3_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_bit_8)
node _atomics_a_mask_sub_acc_T_35 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_3_2_8)
node atomics_a_mask_sub_3_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_35)
node atomics_a_mask_size_8 = bits(atomics_a_mask_sizeOH_8, 0, 0)
node atomics_a_mask_bit_8 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_8 = eq(atomics_a_mask_bit_8, UInt<1>(0h0))
node atomics_a_mask_eq_64 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_64 = and(atomics_a_mask_size_8, atomics_a_mask_eq_64)
node atomics_a_mask_acc_64 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_64)
node atomics_a_mask_eq_65 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_65 = and(atomics_a_mask_size_8, atomics_a_mask_eq_65)
node atomics_a_mask_acc_65 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_65)
node atomics_a_mask_eq_66 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_66 = and(atomics_a_mask_size_8, atomics_a_mask_eq_66)
node atomics_a_mask_acc_66 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_66)
node atomics_a_mask_eq_67 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_67 = and(atomics_a_mask_size_8, atomics_a_mask_eq_67)
node atomics_a_mask_acc_67 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_67)
node atomics_a_mask_eq_68 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_68 = and(atomics_a_mask_size_8, atomics_a_mask_eq_68)
node atomics_a_mask_acc_68 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_68)
node atomics_a_mask_eq_69 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_69 = and(atomics_a_mask_size_8, atomics_a_mask_eq_69)
node atomics_a_mask_acc_69 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_69)
node atomics_a_mask_eq_70 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_70 = and(atomics_a_mask_size_8, atomics_a_mask_eq_70)
node atomics_a_mask_acc_70 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_70)
node atomics_a_mask_eq_71 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_71 = and(atomics_a_mask_size_8, atomics_a_mask_eq_71)
node atomics_a_mask_acc_71 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_71)
node atomics_a_mask_lo_lo_8 = cat(atomics_a_mask_acc_65, atomics_a_mask_acc_64)
node atomics_a_mask_lo_hi_8 = cat(atomics_a_mask_acc_67, atomics_a_mask_acc_66)
node atomics_a_mask_lo_8 = cat(atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8)
node atomics_a_mask_hi_lo_8 = cat(atomics_a_mask_acc_69, atomics_a_mask_acc_68)
node atomics_a_mask_hi_hi_8 = cat(atomics_a_mask_acc_71, atomics_a_mask_acc_70)
node atomics_a_mask_hi_8 = cat(atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8)
node _atomics_a_mask_T_8 = cat(atomics_a_mask_hi_8, atomics_a_mask_lo_8)
connect atomics_a_8.mask, _atomics_a_mask_T_8
connect atomics_a_8.data, pstore1_data
connect atomics_a_8.corrupt, UInt<1>(0h0)
node _atomics_T = eq(UInt<3>(0h4), s2_req.cmd)
node _atomics_T_1 = mux(_atomics_T, atomics_a, _atomics_WIRE_1)
node _atomics_T_2 = eq(UInt<4>(0h9), s2_req.cmd)
node _atomics_T_3 = mux(_atomics_T_2, atomics_a_1, _atomics_T_1)
node _atomics_T_4 = eq(UInt<4>(0ha), s2_req.cmd)
node _atomics_T_5 = mux(_atomics_T_4, atomics_a_2, _atomics_T_3)
node _atomics_T_6 = eq(UInt<4>(0hb), s2_req.cmd)
node _atomics_T_7 = mux(_atomics_T_6, atomics_a_3, _atomics_T_5)
node _atomics_T_8 = eq(UInt<4>(0h8), s2_req.cmd)
node _atomics_T_9 = mux(_atomics_T_8, atomics_a_4, _atomics_T_7)
node _atomics_T_10 = eq(UInt<4>(0hc), s2_req.cmd)
node _atomics_T_11 = mux(_atomics_T_10, atomics_a_5, _atomics_T_9)
node _atomics_T_12 = eq(UInt<4>(0hd), s2_req.cmd)
node _atomics_T_13 = mux(_atomics_T_12, atomics_a_6, _atomics_T_11)
node _atomics_T_14 = eq(UInt<4>(0he), s2_req.cmd)
node _atomics_T_15 = mux(_atomics_T_14, atomics_a_7, _atomics_T_13)
node _atomics_T_16 = eq(UInt<4>(0hf), s2_req.cmd)
node atomics = mux(_atomics_T_16, atomics_a_8, _atomics_T_15)
node _tl_out_a_valid_T = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _tl_out_a_valid_T_1 = xor(s2_req.addr, release_ack_addr)
node _tl_out_a_valid_T_2 = bits(_tl_out_a_valid_T_1, 20, 6)
node _tl_out_a_valid_T_3 = eq(_tl_out_a_valid_T_2, UInt<1>(0h0))
node _tl_out_a_valid_T_4 = and(release_ack_wait, _tl_out_a_valid_T_3)
node _tl_out_a_valid_T_5 = eq(_tl_out_a_valid_T_4, UInt<1>(0h0))
node _tl_out_a_valid_T_6 = and(s2_valid_cached_miss, _tl_out_a_valid_T_5)
node _tl_out_a_valid_T_7 = eq(release_ack_wait, UInt<1>(0h0))
node _tl_out_a_valid_T_8 = and(UInt<1>(0h0), _tl_out_a_valid_T_7)
node _tl_out_a_valid_T_9 = and(_tl_out_a_valid_T_8, UInt<1>(0h1))
node _tl_out_a_valid_T_10 = eq(s2_victim_dirty, UInt<1>(0h0))
node _tl_out_a_valid_T_11 = or(_tl_out_a_valid_T_9, _tl_out_a_valid_T_10)
node _tl_out_a_valid_T_12 = and(_tl_out_a_valid_T_6, _tl_out_a_valid_T_11)
node _tl_out_a_valid_T_13 = or(s2_valid_uncached_pending, _tl_out_a_valid_T_12)
node _tl_out_a_valid_T_14 = and(_tl_out_a_valid_T, _tl_out_a_valid_T_13)
connect tl_out_a.valid, _tl_out_a_valid_T_14
node _tl_out_a_bits_T = eq(s2_uncached, UInt<1>(0h0))
node _tl_out_a_bits_T_1 = shr(s2_req.addr, 6)
node _tl_out_a_bits_T_2 = shl(_tl_out_a_bits_T_1, 6)
node _tl_out_a_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _tl_out_a_bits_legal_T_1 = xor(_tl_out_a_bits_T_2, UInt<1>(0h0))
node _tl_out_a_bits_legal_T_2 = cvt(_tl_out_a_bits_legal_T_1)
node _tl_out_a_bits_legal_T_3 = and(_tl_out_a_bits_legal_T_2, asSInt(UInt<33>(0h8c020000)))
node _tl_out_a_bits_legal_T_4 = asSInt(_tl_out_a_bits_legal_T_3)
node _tl_out_a_bits_legal_T_5 = eq(_tl_out_a_bits_legal_T_4, asSInt(UInt<1>(0h0)))
node _tl_out_a_bits_legal_T_6 = xor(_tl_out_a_bits_T_2, UInt<17>(0h10000))
node _tl_out_a_bits_legal_T_7 = cvt(_tl_out_a_bits_legal_T_6)
node _tl_out_a_bits_legal_T_8 = and(_tl_out_a_bits_legal_T_7, asSInt(UInt<33>(0h8c031000)))
node _tl_out_a_bits_legal_T_9 = asSInt(_tl_out_a_bits_legal_T_8)
node _tl_out_a_bits_legal_T_10 = eq(_tl_out_a_bits_legal_T_9, asSInt(UInt<1>(0h0)))
node _tl_out_a_bits_legal_T_11 = xor(_tl_out_a_bits_T_2, UInt<18>(0h20000))
node _tl_out_a_bits_legal_T_12 = cvt(_tl_out_a_bits_legal_T_11)
node _tl_out_a_bits_legal_T_13 = and(_tl_out_a_bits_legal_T_12, asSInt(UInt<33>(0h8c030000)))
node _tl_out_a_bits_legal_T_14 = asSInt(_tl_out_a_bits_legal_T_13)
node _tl_out_a_bits_legal_T_15 = eq(_tl_out_a_bits_legal_T_14, asSInt(UInt<1>(0h0)))
node _tl_out_a_bits_legal_T_16 = xor(_tl_out_a_bits_T_2, UInt<28>(0hc000000))
node _tl_out_a_bits_legal_T_17 = cvt(_tl_out_a_bits_legal_T_16)
node _tl_out_a_bits_legal_T_18 = and(_tl_out_a_bits_legal_T_17, asSInt(UInt<33>(0h8c000000)))
node _tl_out_a_bits_legal_T_19 = asSInt(_tl_out_a_bits_legal_T_18)
node _tl_out_a_bits_legal_T_20 = eq(_tl_out_a_bits_legal_T_19, asSInt(UInt<1>(0h0)))
node _tl_out_a_bits_legal_T_21 = or(_tl_out_a_bits_legal_T_5, _tl_out_a_bits_legal_T_10)
node _tl_out_a_bits_legal_T_22 = or(_tl_out_a_bits_legal_T_21, _tl_out_a_bits_legal_T_15)
node _tl_out_a_bits_legal_T_23 = or(_tl_out_a_bits_legal_T_22, _tl_out_a_bits_legal_T_20)
node _tl_out_a_bits_legal_T_24 = and(_tl_out_a_bits_legal_T, _tl_out_a_bits_legal_T_23)
node _tl_out_a_bits_legal_T_25 = eq(UInt<3>(0h6), UInt<3>(0h6))
node _tl_out_a_bits_legal_T_26 = or(UInt<1>(0h0), _tl_out_a_bits_legal_T_25)
node _tl_out_a_bits_legal_T_27 = xor(_tl_out_a_bits_T_2, UInt<28>(0h8000000))
node _tl_out_a_bits_legal_T_28 = cvt(_tl_out_a_bits_legal_T_27)
node _tl_out_a_bits_legal_T_29 = and(_tl_out_a_bits_legal_T_28, asSInt(UInt<33>(0h8c030000)))
node _tl_out_a_bits_legal_T_30 = asSInt(_tl_out_a_bits_legal_T_29)
node _tl_out_a_bits_legal_T_31 = eq(_tl_out_a_bits_legal_T_30, asSInt(UInt<1>(0h0)))
node _tl_out_a_bits_legal_T_32 = xor(_tl_out_a_bits_T_2, UInt<32>(0h80000000))
node _tl_out_a_bits_legal_T_33 = cvt(_tl_out_a_bits_legal_T_32)
node _tl_out_a_bits_legal_T_34 = and(_tl_out_a_bits_legal_T_33, asSInt(UInt<33>(0h80000000)))
node _tl_out_a_bits_legal_T_35 = asSInt(_tl_out_a_bits_legal_T_34)
node _tl_out_a_bits_legal_T_36 = eq(_tl_out_a_bits_legal_T_35, asSInt(UInt<1>(0h0)))
node _tl_out_a_bits_legal_T_37 = or(_tl_out_a_bits_legal_T_31, _tl_out_a_bits_legal_T_36)
node _tl_out_a_bits_legal_T_38 = and(_tl_out_a_bits_legal_T_26, _tl_out_a_bits_legal_T_37)
node _tl_out_a_bits_legal_T_39 = or(UInt<1>(0h0), _tl_out_a_bits_legal_T_24)
node tl_out_a_bits_legal = or(_tl_out_a_bits_legal_T_39, _tl_out_a_bits_legal_T_38)
wire tl_out_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect tl_out_a_bits_a.opcode, UInt<3>(0h6)
connect tl_out_a_bits_a.param, s2_grow_param
connect tl_out_a_bits_a.size, UInt<3>(0h6)
connect tl_out_a_bits_a.source, UInt<1>(0h0)
connect tl_out_a_bits_a.address, _tl_out_a_bits_T_2
node _tl_out_a_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0))
node tl_out_a_bits_a_mask_sizeOH_shiftAmount = bits(_tl_out_a_bits_a_mask_sizeOH_T, 1, 0)
node _tl_out_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), tl_out_a_bits_a_mask_sizeOH_shiftAmount)
node _tl_out_a_bits_a_mask_sizeOH_T_2 = bits(_tl_out_a_bits_a_mask_sizeOH_T_1, 2, 0)
node tl_out_a_bits_a_mask_sizeOH = or(_tl_out_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node tl_out_a_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3))
node tl_out_a_bits_a_mask_sub_sub_size = bits(tl_out_a_bits_a_mask_sizeOH, 2, 2)
node tl_out_a_bits_a_mask_sub_sub_bit = bits(_tl_out_a_bits_T_2, 2, 2)
node tl_out_a_bits_a_mask_sub_sub_nbit = eq(tl_out_a_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node tl_out_a_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), tl_out_a_bits_a_mask_sub_sub_nbit)
node _tl_out_a_bits_a_mask_sub_sub_acc_T = and(tl_out_a_bits_a_mask_sub_sub_size, tl_out_a_bits_a_mask_sub_sub_0_2)
node tl_out_a_bits_a_mask_sub_sub_0_1 = or(tl_out_a_bits_a_mask_sub_sub_sub_0_1, _tl_out_a_bits_a_mask_sub_sub_acc_T)
node tl_out_a_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), tl_out_a_bits_a_mask_sub_sub_bit)
node _tl_out_a_bits_a_mask_sub_sub_acc_T_1 = and(tl_out_a_bits_a_mask_sub_sub_size, tl_out_a_bits_a_mask_sub_sub_1_2)
node tl_out_a_bits_a_mask_sub_sub_1_1 = or(tl_out_a_bits_a_mask_sub_sub_sub_0_1, _tl_out_a_bits_a_mask_sub_sub_acc_T_1)
node tl_out_a_bits_a_mask_sub_size = bits(tl_out_a_bits_a_mask_sizeOH, 1, 1)
node tl_out_a_bits_a_mask_sub_bit = bits(_tl_out_a_bits_T_2, 1, 1)
node tl_out_a_bits_a_mask_sub_nbit = eq(tl_out_a_bits_a_mask_sub_bit, UInt<1>(0h0))
node tl_out_a_bits_a_mask_sub_0_2 = and(tl_out_a_bits_a_mask_sub_sub_0_2, tl_out_a_bits_a_mask_sub_nbit)
node _tl_out_a_bits_a_mask_sub_acc_T = and(tl_out_a_bits_a_mask_sub_size, tl_out_a_bits_a_mask_sub_0_2)
node tl_out_a_bits_a_mask_sub_0_1 = or(tl_out_a_bits_a_mask_sub_sub_0_1, _tl_out_a_bits_a_mask_sub_acc_T)
node tl_out_a_bits_a_mask_sub_1_2 = and(tl_out_a_bits_a_mask_sub_sub_0_2, tl_out_a_bits_a_mask_sub_bit)
node _tl_out_a_bits_a_mask_sub_acc_T_1 = and(tl_out_a_bits_a_mask_sub_size, tl_out_a_bits_a_mask_sub_1_2)
node tl_out_a_bits_a_mask_sub_1_1 = or(tl_out_a_bits_a_mask_sub_sub_0_1, _tl_out_a_bits_a_mask_sub_acc_T_1)
node tl_out_a_bits_a_mask_sub_2_2 = and(tl_out_a_bits_a_mask_sub_sub_1_2, tl_out_a_bits_a_mask_sub_nbit)
node _tl_out_a_bits_a_mask_sub_acc_T_2 = and(tl_out_a_bits_a_mask_sub_size, tl_out_a_bits_a_mask_sub_2_2)
node tl_out_a_bits_a_mask_sub_2_1 = or(tl_out_a_bits_a_mask_sub_sub_1_1, _tl_out_a_bits_a_mask_sub_acc_T_2)
node tl_out_a_bits_a_mask_sub_3_2 = and(tl_out_a_bits_a_mask_sub_sub_1_2, tl_out_a_bits_a_mask_sub_bit)
node _tl_out_a_bits_a_mask_sub_acc_T_3 = and(tl_out_a_bits_a_mask_sub_size, tl_out_a_bits_a_mask_sub_3_2)
node tl_out_a_bits_a_mask_sub_3_1 = or(tl_out_a_bits_a_mask_sub_sub_1_1, _tl_out_a_bits_a_mask_sub_acc_T_3)
node tl_out_a_bits_a_mask_size = bits(tl_out_a_bits_a_mask_sizeOH, 0, 0)
node tl_out_a_bits_a_mask_bit = bits(_tl_out_a_bits_T_2, 0, 0)
node tl_out_a_bits_a_mask_nbit = eq(tl_out_a_bits_a_mask_bit, UInt<1>(0h0))
node tl_out_a_bits_a_mask_eq = and(tl_out_a_bits_a_mask_sub_0_2, tl_out_a_bits_a_mask_nbit)
node _tl_out_a_bits_a_mask_acc_T = and(tl_out_a_bits_a_mask_size, tl_out_a_bits_a_mask_eq)
node tl_out_a_bits_a_mask_acc = or(tl_out_a_bits_a_mask_sub_0_1, _tl_out_a_bits_a_mask_acc_T)
node tl_out_a_bits_a_mask_eq_1 = and(tl_out_a_bits_a_mask_sub_0_2, tl_out_a_bits_a_mask_bit)
node _tl_out_a_bits_a_mask_acc_T_1 = and(tl_out_a_bits_a_mask_size, tl_out_a_bits_a_mask_eq_1)
node tl_out_a_bits_a_mask_acc_1 = or(tl_out_a_bits_a_mask_sub_0_1, _tl_out_a_bits_a_mask_acc_T_1)
node tl_out_a_bits_a_mask_eq_2 = and(tl_out_a_bits_a_mask_sub_1_2, tl_out_a_bits_a_mask_nbit)
node _tl_out_a_bits_a_mask_acc_T_2 = and(tl_out_a_bits_a_mask_size, tl_out_a_bits_a_mask_eq_2)
node tl_out_a_bits_a_mask_acc_2 = or(tl_out_a_bits_a_mask_sub_1_1, _tl_out_a_bits_a_mask_acc_T_2)
node tl_out_a_bits_a_mask_eq_3 = and(tl_out_a_bits_a_mask_sub_1_2, tl_out_a_bits_a_mask_bit)
node _tl_out_a_bits_a_mask_acc_T_3 = and(tl_out_a_bits_a_mask_size, tl_out_a_bits_a_mask_eq_3)
node tl_out_a_bits_a_mask_acc_3 = or(tl_out_a_bits_a_mask_sub_1_1, _tl_out_a_bits_a_mask_acc_T_3)
node tl_out_a_bits_a_mask_eq_4 = and(tl_out_a_bits_a_mask_sub_2_2, tl_out_a_bits_a_mask_nbit)
node _tl_out_a_bits_a_mask_acc_T_4 = and(tl_out_a_bits_a_mask_size, tl_out_a_bits_a_mask_eq_4)
node tl_out_a_bits_a_mask_acc_4 = or(tl_out_a_bits_a_mask_sub_2_1, _tl_out_a_bits_a_mask_acc_T_4)
node tl_out_a_bits_a_mask_eq_5 = and(tl_out_a_bits_a_mask_sub_2_2, tl_out_a_bits_a_mask_bit)
node _tl_out_a_bits_a_mask_acc_T_5 = and(tl_out_a_bits_a_mask_size, tl_out_a_bits_a_mask_eq_5)
node tl_out_a_bits_a_mask_acc_5 = or(tl_out_a_bits_a_mask_sub_2_1, _tl_out_a_bits_a_mask_acc_T_5)
node tl_out_a_bits_a_mask_eq_6 = and(tl_out_a_bits_a_mask_sub_3_2, tl_out_a_bits_a_mask_nbit)
node _tl_out_a_bits_a_mask_acc_T_6 = and(tl_out_a_bits_a_mask_size, tl_out_a_bits_a_mask_eq_6)
node tl_out_a_bits_a_mask_acc_6 = or(tl_out_a_bits_a_mask_sub_3_1, _tl_out_a_bits_a_mask_acc_T_6)
node tl_out_a_bits_a_mask_eq_7 = and(tl_out_a_bits_a_mask_sub_3_2, tl_out_a_bits_a_mask_bit)
node _tl_out_a_bits_a_mask_acc_T_7 = and(tl_out_a_bits_a_mask_size, tl_out_a_bits_a_mask_eq_7)
node tl_out_a_bits_a_mask_acc_7 = or(tl_out_a_bits_a_mask_sub_3_1, _tl_out_a_bits_a_mask_acc_T_7)
node tl_out_a_bits_a_mask_lo_lo = cat(tl_out_a_bits_a_mask_acc_1, tl_out_a_bits_a_mask_acc)
node tl_out_a_bits_a_mask_lo_hi = cat(tl_out_a_bits_a_mask_acc_3, tl_out_a_bits_a_mask_acc_2)
node tl_out_a_bits_a_mask_lo = cat(tl_out_a_bits_a_mask_lo_hi, tl_out_a_bits_a_mask_lo_lo)
node tl_out_a_bits_a_mask_hi_lo = cat(tl_out_a_bits_a_mask_acc_5, tl_out_a_bits_a_mask_acc_4)
node tl_out_a_bits_a_mask_hi_hi = cat(tl_out_a_bits_a_mask_acc_7, tl_out_a_bits_a_mask_acc_6)
node tl_out_a_bits_a_mask_hi = cat(tl_out_a_bits_a_mask_hi_hi, tl_out_a_bits_a_mask_hi_lo)
node _tl_out_a_bits_a_mask_T = cat(tl_out_a_bits_a_mask_hi, tl_out_a_bits_a_mask_lo)
connect tl_out_a_bits_a.mask, _tl_out_a_bits_a_mask_T
invalidate tl_out_a_bits_a.data
connect tl_out_a_bits_a.corrupt, UInt<1>(0h0)
node _tl_out_a_bits_T_3 = eq(s2_write, UInt<1>(0h0))
node _tl_out_a_bits_T_4 = eq(s2_req.cmd, UInt<5>(0h11))
node _tl_out_a_bits_T_5 = eq(s2_read, UInt<1>(0h0))
node _tl_out_a_bits_T_6 = mux(_tl_out_a_bits_T_5, put, atomics)
node _tl_out_a_bits_T_7 = mux(_tl_out_a_bits_T_4, putpartial, _tl_out_a_bits_T_6)
node _tl_out_a_bits_T_8 = mux(_tl_out_a_bits_T_3, get, _tl_out_a_bits_T_7)
node _tl_out_a_bits_T_9 = mux(_tl_out_a_bits_T, tl_out_a_bits_a, _tl_out_a_bits_T_8)
connect tl_out_a.bits, _tl_out_a_bits_T_9
node a_sel_shiftAmount = bits(a_source, 0, 0)
node _a_sel_T = dshl(UInt<1>(0h1), a_sel_shiftAmount)
node _a_sel_T_1 = bits(_a_sel_T, 1, 0)
node a_sel = shr(_a_sel_T_1, 1)
node _T_61 = and(tl_out_a.ready, tl_out_a.valid)
when _T_61 :
when s2_uncached :
node _T_62 = bits(a_sel, 0, 0)
when _T_62 :
connect uncachedInFlight[0], UInt<1>(0h1)
connect uncachedReqs[0], s2_req
node _uncachedReqs_0_cmd_T = eq(s2_req.cmd, UInt<5>(0h11))
node _uncachedReqs_0_cmd_T_1 = mux(_uncachedReqs_0_cmd_T, UInt<5>(0h11), UInt<1>(0h1))
node _uncachedReqs_0_cmd_T_2 = mux(s2_write, _uncachedReqs_0_cmd_T_1, UInt<1>(0h0))
connect uncachedReqs[0].cmd, _uncachedReqs_0_cmd_T_2
else :
connect cached_grant_wait, UInt<1>(0h1)
connect refill_way, s2_victim_or_hit_way
node _T_63 = and(nodeOut.d.ready, nodeOut.d.valid)
node _r_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.d.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 3)
node r_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node d_first = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node d_last = or(_r_last_T, _r_last_T_1)
node d_done = and(d_last, _T_63)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T_63 :
node _r_counter_T = mux(d_first, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node d_address_inc = shl(r_4, 3)
node _T_64 = eq(nodeOut.d.bits.opcode, UInt<1>(0h1))
node _T_65 = eq(nodeOut.d.bits.opcode, UInt<1>(0h0))
node _T_66 = eq(nodeOut.d.bits.opcode, UInt<2>(0h2))
node _T_67 = or(_T_64, _T_65)
node grantIsUncached = or(_T_67, _T_66)
node grantIsUncachedData = eq(nodeOut.d.bits.opcode, UInt<1>(0h1))
node _tl_d_data_encoded_T_9 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _tl_d_data_encoded_T_10 = and(nodeOut.d.bits.corrupt, _tl_d_data_encoded_T_9)
node _tl_d_data_encoded_T_11 = eq(grantIsUncached, UInt<1>(0h0))
node _tl_d_data_encoded_T_12 = and(_tl_d_data_encoded_T_10, _tl_d_data_encoded_T_11)
node _tl_d_data_encoded_T_13 = bits(nodeOut.d.bits.data, 7, 0)
node _tl_d_data_encoded_T_14 = bits(nodeOut.d.bits.data, 15, 8)
node _tl_d_data_encoded_T_15 = bits(nodeOut.d.bits.data, 23, 16)
node _tl_d_data_encoded_T_16 = bits(nodeOut.d.bits.data, 31, 24)
node _tl_d_data_encoded_T_17 = bits(nodeOut.d.bits.data, 39, 32)
node _tl_d_data_encoded_T_18 = bits(nodeOut.d.bits.data, 47, 40)
node _tl_d_data_encoded_T_19 = bits(nodeOut.d.bits.data, 55, 48)
node _tl_d_data_encoded_T_20 = bits(nodeOut.d.bits.data, 63, 56)
node tl_d_data_encoded_lo_lo_1 = cat(_tl_d_data_encoded_T_14, _tl_d_data_encoded_T_13)
node tl_d_data_encoded_lo_hi_1 = cat(_tl_d_data_encoded_T_16, _tl_d_data_encoded_T_15)
node tl_d_data_encoded_lo_1 = cat(tl_d_data_encoded_lo_hi_1, tl_d_data_encoded_lo_lo_1)
node tl_d_data_encoded_hi_lo_1 = cat(_tl_d_data_encoded_T_18, _tl_d_data_encoded_T_17)
node tl_d_data_encoded_hi_hi_1 = cat(_tl_d_data_encoded_T_20, _tl_d_data_encoded_T_19)
node tl_d_data_encoded_hi_1 = cat(tl_d_data_encoded_hi_hi_1, tl_d_data_encoded_hi_lo_1)
node _tl_d_data_encoded_T_21 = cat(tl_d_data_encoded_hi_1, tl_d_data_encoded_lo_1)
connect tl_d_data_encoded, _tl_d_data_encoded_T_21
node _grantIsCached_T = eq(nodeOut.d.bits.opcode, UInt<3>(0h4))
node _grantIsCached_T_1 = eq(nodeOut.d.bits.opcode, UInt<3>(0h5))
node grantIsCached = or(_grantIsCached_T, _grantIsCached_T_1)
node grantIsVoluntary = eq(nodeOut.d.bits.opcode, UInt<3>(0h6))
node grantIsRefill = eq(nodeOut.d.bits.opcode, UInt<3>(0h5))
regreset grantInProgress : UInt<1>, clock, reset, UInt<1>(0h0)
regreset blockProbeAfterGrantCount : UInt, clock, reset, UInt<1>(0h0)
node _T_68 = gt(blockProbeAfterGrantCount, UInt<1>(0h0))
when _T_68 :
node _blockProbeAfterGrantCount_T = sub(blockProbeAfterGrantCount, UInt<1>(0h1))
node _blockProbeAfterGrantCount_T_1 = tail(_blockProbeAfterGrantCount_T, 1)
connect blockProbeAfterGrantCount, _blockProbeAfterGrantCount_T_1
node _canAcceptCachedGrant_T = eq(release_state, UInt<4>(0h1))
node _canAcceptCachedGrant_T_1 = eq(release_state, UInt<4>(0h6))
node _canAcceptCachedGrant_T_2 = eq(release_state, UInt<4>(0h9))
node _canAcceptCachedGrant_T_3 = or(_canAcceptCachedGrant_T, _canAcceptCachedGrant_T_1)
node _canAcceptCachedGrant_T_4 = or(_canAcceptCachedGrant_T_3, _canAcceptCachedGrant_T_2)
node canAcceptCachedGrant = eq(_canAcceptCachedGrant_T_4, UInt<1>(0h0))
node _nodeOut_d_ready_T = eq(d_first, UInt<1>(0h0))
node _nodeOut_d_ready_T_1 = or(_nodeOut_d_ready_T, nodeOut.e.ready)
node _nodeOut_d_ready_T_2 = and(_nodeOut_d_ready_T_1, canAcceptCachedGrant)
node _nodeOut_d_ready_T_3 = mux(grantIsCached, _nodeOut_d_ready_T_2, UInt<1>(0h1))
connect nodeOut.d.ready, _nodeOut_d_ready_T_3
node uncachedRespIdxOH_shiftAmount = bits(nodeOut.d.bits.source, 0, 0)
node _uncachedRespIdxOH_T = dshl(UInt<1>(0h1), uncachedRespIdxOH_shiftAmount)
node _uncachedRespIdxOH_T_1 = bits(_uncachedRespIdxOH_T, 1, 0)
node uncachedRespIdxOH = shr(_uncachedRespIdxOH_T_1, 1)
node _uncachedResp_T = bits(uncachedRespIdxOH, 0, 0)
connect uncachedResp, uncachedReqs[0]
node _T_69 = and(nodeOut.d.ready, nodeOut.d.valid)
when _T_69 :
when grantIsCached :
connect grantInProgress, UInt<1>(0h1)
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(cached_grant_wait, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: A GrantData was unexpected by the dcache.\n at DCache.scala:677 assert(cached_grant_wait, \"A GrantData was unexpected by the dcache.\")\n") : printf_2
assert(clock, cached_grant_wait, UInt<1>(0h1), "") : assert_2
when d_last :
connect cached_grant_wait, UInt<1>(0h0)
connect grantInProgress, UInt<1>(0h0)
connect blockProbeAfterGrantCount, UInt<3>(0h7)
connect replace, UInt<1>(0h1)
else :
when grantIsUncached :
node _T_73 = bits(uncachedRespIdxOH, 0, 0)
node _T_74 = and(_T_73, d_last)
when _T_74 :
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(uncachedInFlight[0], UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: An AccessAck was unexpected by the dcache.\n at DCache.scala:687 assert(f, \"An AccessAck was unexpected by the dcache.\") // TODO must handle Ack coming back on same cycle!\n") : printf_3
assert(clock, uncachedInFlight[0], UInt<1>(0h1), "") : assert_3
connect uncachedInFlight[0], UInt<1>(0h0)
when grantIsUncachedData :
node _s1_data_way_T_1 = shl(UInt<1>(0h1), 4)
connect s1_data_way, _s1_data_way_T_1
connect s2_req.cmd, UInt<1>(0h0)
connect s2_req.size, uncachedResp.size
connect s2_req.signed, uncachedResp.signed
connect s2_req.tag, uncachedResp.tag
node _s2_req_addr_dontCareBits_T = shr(s1_paddr, 3)
node s2_req_addr_dontCareBits = shl(_s2_req_addr_dontCareBits_T, 3)
node _s2_req_addr_T = bits(uncachedResp.addr, 2, 0)
node _s2_req_addr_T_1 = or(s2_req_addr_dontCareBits, _s2_req_addr_T)
connect s2_req.addr, _s2_req_addr_T_1
connect s2_uncached_resp_addr, uncachedResp.addr
else :
when grantIsVoluntary :
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(release_ack_wait, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed: A ReleaseAck was unexpected by the dcache.\n at DCache.scala:708 assert(release_ack_wait, \"A ReleaseAck was unexpected by the dcache.\") // TODO should handle Ack coming back on same cycle!\n") : printf_4
assert(clock, release_ack_wait, UInt<1>(0h1), "") : assert_4
connect release_ack_wait, UInt<1>(0h0)
node _nodeOut_e_valid_T = and(nodeOut.d.valid, d_first)
node _nodeOut_e_valid_T_1 = and(_nodeOut_e_valid_T, grantIsCached)
node _nodeOut_e_valid_T_2 = and(_nodeOut_e_valid_T_1, canAcceptCachedGrant)
connect nodeOut.e.valid, _nodeOut_e_valid_T_2
wire nodeOut_e_bits_e : { sink : UInt<3>}
connect nodeOut_e_bits_e.sink, nodeOut.d.bits.sink
connect nodeOut.e.bits, nodeOut_e_bits_e
node _T_81 = and(nodeOut.e.ready, nodeOut.e.valid)
node _T_82 = and(nodeOut.d.ready, nodeOut.d.valid)
node _T_83 = and(_T_82, d_first)
node _T_84 = and(_T_83, grantIsCached)
node _T_85 = eq(_T_81, _T_84)
node _T_86 = asUInt(reset)
node _T_87 = eq(_T_86, UInt<1>(0h0))
when _T_87 :
node _T_88 = eq(_T_85, UInt<1>(0h0))
when _T_88 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:716 assert(tl_out.e.fire === (tl_out.d.fire && d_first && grantIsCached))\n") : printf_5
assert(clock, _T_85, UInt<1>(0h1), "") : assert_5
node _dataArb_io_in_1_valid_T = and(nodeOut.d.valid, grantIsRefill)
node _dataArb_io_in_1_valid_T_1 = and(_dataArb_io_in_1_valid_T, canAcceptCachedGrant)
connect dataArb.io.in[1].valid, _dataArb_io_in_1_valid_T_1
node _T_89 = eq(dataArb.io.in[1].ready, UInt<1>(0h0))
node _T_90 = and(grantIsRefill, _T_89)
when _T_90 :
connect nodeOut.e.valid, UInt<1>(0h0)
connect nodeOut.d.ready, UInt<1>(0h0)
connect dataArb.io.in[1].bits.write, UInt<1>(0h1)
node _dataArb_io_in_1_bits_addr_T = shr(s2_vaddr, 6)
node _dataArb_io_in_1_bits_addr_T_1 = shl(_dataArb_io_in_1_bits_addr_T, 6)
node _dataArb_io_in_1_bits_addr_T_2 = or(_dataArb_io_in_1_bits_addr_T_1, d_address_inc)
connect dataArb.io.in[1].bits.addr, _dataArb_io_in_1_bits_addr_T_2
connect dataArb.io.in[1].bits.way_en, refill_way
connect dataArb.io.in[1].bits.wdata, tl_d_data_encoded
node _dataArb_io_in_1_bits_wordMask_T = not(UInt<1>(0h0))
connect dataArb.io.in[1].bits.wordMask, _dataArb_io_in_1_bits_wordMask_T
node _dataArb_io_in_1_bits_eccMask_T = not(UInt<8>(0h0))
connect dataArb.io.in[1].bits.eccMask, _dataArb_io_in_1_bits_eccMask_T
node _metaArb_io_in_3_valid_T = and(grantIsCached, d_done)
node _metaArb_io_in_3_valid_T_1 = eq(nodeOut.d.bits.denied, UInt<1>(0h0))
node _metaArb_io_in_3_valid_T_2 = and(_metaArb_io_in_3_valid_T, _metaArb_io_in_3_valid_T_1)
connect metaArb.io.in[3].valid, _metaArb_io_in_3_valid_T_2
connect metaArb.io.in[3].bits.write, UInt<1>(0h1)
connect metaArb.io.in[3].bits.way_en, refill_way
node _metaArb_io_in_3_bits_idx_T = bits(s2_vaddr, 7, 6)
connect metaArb.io.in[3].bits.idx, _metaArb_io_in_3_bits_idx_T
node _metaArb_io_in_3_bits_addr_T = shr(io.cpu.req.bits.addr, 8)
node _metaArb_io_in_3_bits_addr_T_1 = bits(s2_vaddr, 7, 0)
node _metaArb_io_in_3_bits_addr_T_2 = cat(_metaArb_io_in_3_bits_addr_T, _metaArb_io_in_3_bits_addr_T_1)
connect metaArb.io.in[3].bits.addr, _metaArb_io_in_3_bits_addr_T_2
node _metaArb_io_in_3_bits_data_T = shr(s2_req.addr, 8)
node _metaArb_io_in_3_bits_data_c_cat_T = eq(s2_req.cmd, UInt<1>(0h1))
node _metaArb_io_in_3_bits_data_c_cat_T_1 = eq(s2_req.cmd, UInt<5>(0h11))
node _metaArb_io_in_3_bits_data_c_cat_T_2 = or(_metaArb_io_in_3_bits_data_c_cat_T, _metaArb_io_in_3_bits_data_c_cat_T_1)
node _metaArb_io_in_3_bits_data_c_cat_T_3 = eq(s2_req.cmd, UInt<3>(0h7))
node _metaArb_io_in_3_bits_data_c_cat_T_4 = or(_metaArb_io_in_3_bits_data_c_cat_T_2, _metaArb_io_in_3_bits_data_c_cat_T_3)
node _metaArb_io_in_3_bits_data_c_cat_T_5 = eq(s2_req.cmd, UInt<3>(0h4))
node _metaArb_io_in_3_bits_data_c_cat_T_6 = eq(s2_req.cmd, UInt<4>(0h9))
node _metaArb_io_in_3_bits_data_c_cat_T_7 = eq(s2_req.cmd, UInt<4>(0ha))
node _metaArb_io_in_3_bits_data_c_cat_T_8 = eq(s2_req.cmd, UInt<4>(0hb))
node _metaArb_io_in_3_bits_data_c_cat_T_9 = or(_metaArb_io_in_3_bits_data_c_cat_T_5, _metaArb_io_in_3_bits_data_c_cat_T_6)
node _metaArb_io_in_3_bits_data_c_cat_T_10 = or(_metaArb_io_in_3_bits_data_c_cat_T_9, _metaArb_io_in_3_bits_data_c_cat_T_7)
node _metaArb_io_in_3_bits_data_c_cat_T_11 = or(_metaArb_io_in_3_bits_data_c_cat_T_10, _metaArb_io_in_3_bits_data_c_cat_T_8)
node _metaArb_io_in_3_bits_data_c_cat_T_12 = eq(s2_req.cmd, UInt<4>(0h8))
node _metaArb_io_in_3_bits_data_c_cat_T_13 = eq(s2_req.cmd, UInt<4>(0hc))
node _metaArb_io_in_3_bits_data_c_cat_T_14 = eq(s2_req.cmd, UInt<4>(0hd))
node _metaArb_io_in_3_bits_data_c_cat_T_15 = eq(s2_req.cmd, UInt<4>(0he))
node _metaArb_io_in_3_bits_data_c_cat_T_16 = eq(s2_req.cmd, UInt<4>(0hf))
node _metaArb_io_in_3_bits_data_c_cat_T_17 = or(_metaArb_io_in_3_bits_data_c_cat_T_12, _metaArb_io_in_3_bits_data_c_cat_T_13)
node _metaArb_io_in_3_bits_data_c_cat_T_18 = or(_metaArb_io_in_3_bits_data_c_cat_T_17, _metaArb_io_in_3_bits_data_c_cat_T_14)
node _metaArb_io_in_3_bits_data_c_cat_T_19 = or(_metaArb_io_in_3_bits_data_c_cat_T_18, _metaArb_io_in_3_bits_data_c_cat_T_15)
node _metaArb_io_in_3_bits_data_c_cat_T_20 = or(_metaArb_io_in_3_bits_data_c_cat_T_19, _metaArb_io_in_3_bits_data_c_cat_T_16)
node _metaArb_io_in_3_bits_data_c_cat_T_21 = or(_metaArb_io_in_3_bits_data_c_cat_T_11, _metaArb_io_in_3_bits_data_c_cat_T_20)
node _metaArb_io_in_3_bits_data_c_cat_T_22 = or(_metaArb_io_in_3_bits_data_c_cat_T_4, _metaArb_io_in_3_bits_data_c_cat_T_21)
node _metaArb_io_in_3_bits_data_c_cat_T_23 = eq(s2_req.cmd, UInt<1>(0h1))
node _metaArb_io_in_3_bits_data_c_cat_T_24 = eq(s2_req.cmd, UInt<5>(0h11))
node _metaArb_io_in_3_bits_data_c_cat_T_25 = or(_metaArb_io_in_3_bits_data_c_cat_T_23, _metaArb_io_in_3_bits_data_c_cat_T_24)
node _metaArb_io_in_3_bits_data_c_cat_T_26 = eq(s2_req.cmd, UInt<3>(0h7))
node _metaArb_io_in_3_bits_data_c_cat_T_27 = or(_metaArb_io_in_3_bits_data_c_cat_T_25, _metaArb_io_in_3_bits_data_c_cat_T_26)
node _metaArb_io_in_3_bits_data_c_cat_T_28 = eq(s2_req.cmd, UInt<3>(0h4))
node _metaArb_io_in_3_bits_data_c_cat_T_29 = eq(s2_req.cmd, UInt<4>(0h9))
node _metaArb_io_in_3_bits_data_c_cat_T_30 = eq(s2_req.cmd, UInt<4>(0ha))
node _metaArb_io_in_3_bits_data_c_cat_T_31 = eq(s2_req.cmd, UInt<4>(0hb))
node _metaArb_io_in_3_bits_data_c_cat_T_32 = or(_metaArb_io_in_3_bits_data_c_cat_T_28, _metaArb_io_in_3_bits_data_c_cat_T_29)
node _metaArb_io_in_3_bits_data_c_cat_T_33 = or(_metaArb_io_in_3_bits_data_c_cat_T_32, _metaArb_io_in_3_bits_data_c_cat_T_30)
node _metaArb_io_in_3_bits_data_c_cat_T_34 = or(_metaArb_io_in_3_bits_data_c_cat_T_33, _metaArb_io_in_3_bits_data_c_cat_T_31)
node _metaArb_io_in_3_bits_data_c_cat_T_35 = eq(s2_req.cmd, UInt<4>(0h8))
node _metaArb_io_in_3_bits_data_c_cat_T_36 = eq(s2_req.cmd, UInt<4>(0hc))
node _metaArb_io_in_3_bits_data_c_cat_T_37 = eq(s2_req.cmd, UInt<4>(0hd))
node _metaArb_io_in_3_bits_data_c_cat_T_38 = eq(s2_req.cmd, UInt<4>(0he))
node _metaArb_io_in_3_bits_data_c_cat_T_39 = eq(s2_req.cmd, UInt<4>(0hf))
node _metaArb_io_in_3_bits_data_c_cat_T_40 = or(_metaArb_io_in_3_bits_data_c_cat_T_35, _metaArb_io_in_3_bits_data_c_cat_T_36)
node _metaArb_io_in_3_bits_data_c_cat_T_41 = or(_metaArb_io_in_3_bits_data_c_cat_T_40, _metaArb_io_in_3_bits_data_c_cat_T_37)
node _metaArb_io_in_3_bits_data_c_cat_T_42 = or(_metaArb_io_in_3_bits_data_c_cat_T_41, _metaArb_io_in_3_bits_data_c_cat_T_38)
node _metaArb_io_in_3_bits_data_c_cat_T_43 = or(_metaArb_io_in_3_bits_data_c_cat_T_42, _metaArb_io_in_3_bits_data_c_cat_T_39)
node _metaArb_io_in_3_bits_data_c_cat_T_44 = or(_metaArb_io_in_3_bits_data_c_cat_T_34, _metaArb_io_in_3_bits_data_c_cat_T_43)
node _metaArb_io_in_3_bits_data_c_cat_T_45 = or(_metaArb_io_in_3_bits_data_c_cat_T_27, _metaArb_io_in_3_bits_data_c_cat_T_44)
node _metaArb_io_in_3_bits_data_c_cat_T_46 = eq(s2_req.cmd, UInt<2>(0h3))
node _metaArb_io_in_3_bits_data_c_cat_T_47 = or(_metaArb_io_in_3_bits_data_c_cat_T_45, _metaArb_io_in_3_bits_data_c_cat_T_46)
node _metaArb_io_in_3_bits_data_c_cat_T_48 = eq(s2_req.cmd, UInt<3>(0h6))
node _metaArb_io_in_3_bits_data_c_cat_T_49 = or(_metaArb_io_in_3_bits_data_c_cat_T_47, _metaArb_io_in_3_bits_data_c_cat_T_48)
node metaArb_io_in_3_bits_data_c = cat(_metaArb_io_in_3_bits_data_c_cat_T_22, _metaArb_io_in_3_bits_data_c_cat_T_49)
node _metaArb_io_in_3_bits_data_T_1 = cat(metaArb_io_in_3_bits_data_c, nodeOut.d.bits.param)
node _metaArb_io_in_3_bits_data_T_2 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _metaArb_io_in_3_bits_data_T_3 = cat(_metaArb_io_in_3_bits_data_T_2, UInt<2>(0h1))
node _metaArb_io_in_3_bits_data_T_4 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _metaArb_io_in_3_bits_data_T_5 = cat(_metaArb_io_in_3_bits_data_T_4, UInt<2>(0h0))
node _metaArb_io_in_3_bits_data_T_6 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _metaArb_io_in_3_bits_data_T_7 = cat(_metaArb_io_in_3_bits_data_T_6, UInt<2>(0h0))
node _metaArb_io_in_3_bits_data_T_8 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _metaArb_io_in_3_bits_data_T_9 = cat(_metaArb_io_in_3_bits_data_T_8, UInt<2>(0h0))
node _metaArb_io_in_3_bits_data_T_10 = eq(_metaArb_io_in_3_bits_data_T_3, _metaArb_io_in_3_bits_data_T_1)
node _metaArb_io_in_3_bits_data_T_11 = mux(_metaArb_io_in_3_bits_data_T_10, UInt<2>(0h1), UInt<2>(0h0))
node _metaArb_io_in_3_bits_data_T_12 = eq(_metaArb_io_in_3_bits_data_T_5, _metaArb_io_in_3_bits_data_T_1)
node _metaArb_io_in_3_bits_data_T_13 = mux(_metaArb_io_in_3_bits_data_T_12, UInt<2>(0h2), _metaArb_io_in_3_bits_data_T_11)
node _metaArb_io_in_3_bits_data_T_14 = eq(_metaArb_io_in_3_bits_data_T_7, _metaArb_io_in_3_bits_data_T_1)
node _metaArb_io_in_3_bits_data_T_15 = mux(_metaArb_io_in_3_bits_data_T_14, UInt<2>(0h2), _metaArb_io_in_3_bits_data_T_13)
node _metaArb_io_in_3_bits_data_T_16 = eq(_metaArb_io_in_3_bits_data_T_9, _metaArb_io_in_3_bits_data_T_1)
node _metaArb_io_in_3_bits_data_T_17 = mux(_metaArb_io_in_3_bits_data_T_16, UInt<2>(0h3), _metaArb_io_in_3_bits_data_T_15)
wire metaArb_io_in_3_bits_data_meta : { state : UInt<2>}
connect metaArb_io_in_3_bits_data_meta.state, _metaArb_io_in_3_bits_data_T_17
wire metaArb_io_in_3_bits_data_meta_1 : { coh : { state : UInt<2>}, tag : UInt<24>}
connect metaArb_io_in_3_bits_data_meta_1.tag, _metaArb_io_in_3_bits_data_T
connect metaArb_io_in_3_bits_data_meta_1.coh, metaArb_io_in_3_bits_data_meta
node _metaArb_io_in_3_bits_data_T_18 = cat(metaArb_io_in_3_bits_data_meta_1.coh.state, metaArb_io_in_3_bits_data_meta_1.tag)
connect metaArb.io.in[3].bits.data, _metaArb_io_in_3_bits_data_T_18
reg blockUncachedGrant : UInt<1>, clock
connect blockUncachedGrant, dataArb.io.out.valid
node _T_91 = or(blockUncachedGrant, s1_valid)
node _T_92 = and(grantIsUncachedData, _T_91)
when _T_92 :
connect nodeOut.d.ready, UInt<1>(0h0)
when nodeOut.d.valid :
connect io.cpu.req.ready, UInt<1>(0h0)
connect dataArb.io.in[1].valid, UInt<1>(0h1)
connect dataArb.io.in[1].bits.write, UInt<1>(0h0)
node _blockUncachedGrant_T = eq(dataArb.io.in[1].ready, UInt<1>(0h0))
connect blockUncachedGrant, _blockUncachedGrant_T
node _T_93 = eq(nodeOut.d.ready, UInt<1>(0h0))
node _T_94 = and(nodeOut.d.valid, _T_93)
node _block_probe_for_core_progress_T = gt(blockProbeAfterGrantCount, UInt<1>(0h0))
node block_probe_for_core_progress = or(_block_probe_for_core_progress_T, lrscValid)
node _block_probe_for_pending_release_ack_T = xor(nodeOut.b.bits.address, release_ack_addr)
node _block_probe_for_pending_release_ack_T_1 = bits(_block_probe_for_pending_release_ack_T, 20, 6)
node _block_probe_for_pending_release_ack_T_2 = eq(_block_probe_for_pending_release_ack_T_1, UInt<1>(0h0))
node block_probe_for_pending_release_ack = and(release_ack_wait, _block_probe_for_pending_release_ack_T_2)
node _block_probe_for_ordering_T = or(releaseInFlight, block_probe_for_pending_release_ack)
node block_probe_for_ordering = or(_block_probe_for_ordering_T, grantInProgress)
node _metaArb_io_in_6_valid_T = eq(block_probe_for_core_progress, UInt<1>(0h0))
node _metaArb_io_in_6_valid_T_1 = or(_metaArb_io_in_6_valid_T, lrscBackingOff)
node _metaArb_io_in_6_valid_T_2 = and(nodeOut.b.valid, _metaArb_io_in_6_valid_T_1)
connect metaArb.io.in[6].valid, _metaArb_io_in_6_valid_T_2
node _nodeOut_b_ready_T = or(block_probe_for_core_progress, block_probe_for_ordering)
node _nodeOut_b_ready_T_1 = or(_nodeOut_b_ready_T, s1_valid)
node _nodeOut_b_ready_T_2 = or(_nodeOut_b_ready_T_1, s2_valid)
node _nodeOut_b_ready_T_3 = eq(_nodeOut_b_ready_T_2, UInt<1>(0h0))
node _nodeOut_b_ready_T_4 = and(metaArb.io.in[6].ready, _nodeOut_b_ready_T_3)
connect nodeOut.b.ready, _nodeOut_b_ready_T_4
connect metaArb.io.in[6].bits.write, UInt<1>(0h0)
node _metaArb_io_in_6_bits_idx_T = bits(nodeOut.b.bits.address, 7, 6)
connect metaArb.io.in[6].bits.idx, _metaArb_io_in_6_bits_idx_T
node _metaArb_io_in_6_bits_addr_T = shr(io.cpu.req.bits.addr, 32)
node _metaArb_io_in_6_bits_addr_T_1 = cat(_metaArb_io_in_6_bits_addr_T, nodeOut.b.bits.address)
connect metaArb.io.in[6].bits.addr, _metaArb_io_in_6_bits_addr_T_1
connect metaArb.io.in[6].bits.way_en, metaArb.io.in[4].bits.way_en
connect metaArb.io.in[6].bits.data, metaArb.io.in[4].bits.data
node _s1_victim_way_T = bits(lfsr, 1, 0)
connect s1_victim_way, _s1_victim_way_T
node _T_95 = and(nodeOut.c.ready, nodeOut.c.valid)
node _r_beats1_decode_T_3 = dshl(UInt<12>(0hfff), nodeOut.c.bits.size)
node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 11, 0)
node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4)
node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 3)
node r_beats1_opdata_1 = bits(nodeOut.c.bits.opcode, 0, 0)
node r_beats1_1 = mux(r_beats1_opdata_1, r_beats1_decode_1, UInt<1>(0h0))
regreset r_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1))
node r_counter1_1 = tail(_r_counter1_T_1, 1)
node c_first = eq(r_counter_1, UInt<1>(0h0))
node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1))
node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0))
node c_last = or(_r_last_T_2, _r_last_T_3)
node releaseDone = and(c_last, _T_95)
node _r_count_T_1 = not(r_counter1_1)
node c_count = and(r_beats1_1, _r_count_T_1)
when _T_95 :
node _r_counter_T_1 = mux(c_first, r_beats1_1, r_counter1_1)
connect r_counter_1, _r_counter_T_1
wire releaseRejected : UInt<1>
node _s1_release_data_valid_T = and(dataArb.io.in[2].ready, dataArb.io.in[2].valid)
reg s1_release_data_valid : UInt<1>, clock
connect s1_release_data_valid, _s1_release_data_valid_T
node _s2_release_data_valid_T = eq(releaseRejected, UInt<1>(0h0))
node _s2_release_data_valid_T_1 = and(s1_release_data_valid, _s2_release_data_valid_T)
reg s2_release_data_valid : UInt<1>, clock
connect s2_release_data_valid, _s2_release_data_valid_T_1
node _releaseRejected_T = and(nodeOut.c.ready, nodeOut.c.valid)
node _releaseRejected_T_1 = eq(_releaseRejected_T, UInt<1>(0h0))
node _releaseRejected_T_2 = and(s2_release_data_valid, _releaseRejected_T_1)
connect releaseRejected, _releaseRejected_T_2
node _releaseDataBeat_T = cat(UInt<1>(0h0), c_count)
node _releaseDataBeat_T_1 = cat(UInt<1>(0h0), s2_release_data_valid)
node _releaseDataBeat_T_2 = add(s1_release_data_valid, _releaseDataBeat_T_1)
node _releaseDataBeat_T_3 = tail(_releaseDataBeat_T_2, 1)
node _releaseDataBeat_T_4 = mux(releaseRejected, UInt<1>(0h0), _releaseDataBeat_T_3)
node _releaseDataBeat_T_5 = add(_releaseDataBeat_T, _releaseDataBeat_T_4)
node releaseDataBeat = tail(_releaseDataBeat_T_5, 1)
wire nackResponseMessage : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect nackResponseMessage.opcode, UInt<3>(0h4)
connect nackResponseMessage.param, UInt<3>(0h5)
connect nackResponseMessage.size, probe_bits.size
connect nackResponseMessage.source, probe_bits.source
connect nackResponseMessage.address, probe_bits.address
invalidate nackResponseMessage.data
connect nackResponseMessage.corrupt, UInt<1>(0h0)
wire cleanReleaseMessage : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect cleanReleaseMessage.opcode, UInt<3>(0h4)
connect cleanReleaseMessage.param, s2_report_param
connect cleanReleaseMessage.size, probe_bits.size
connect cleanReleaseMessage.source, probe_bits.source
connect cleanReleaseMessage.address, probe_bits.address
invalidate cleanReleaseMessage.data
connect cleanReleaseMessage.corrupt, UInt<1>(0h0)
wire dirtyReleaseMessage : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect dirtyReleaseMessage.opcode, UInt<3>(0h5)
connect dirtyReleaseMessage.param, s2_report_param
connect dirtyReleaseMessage.size, probe_bits.size
connect dirtyReleaseMessage.source, probe_bits.source
connect dirtyReleaseMessage.address, probe_bits.address
connect dirtyReleaseMessage.data, UInt<1>(0h0)
connect dirtyReleaseMessage.corrupt, UInt<1>(0h0)
node _nodeOut_c_valid_T = eq(UInt<1>(0h1), UInt<1>(0h0))
node _nodeOut_c_valid_T_1 = eq(release_state, UInt<4>(0h9))
node _nodeOut_c_valid_T_2 = and(_nodeOut_c_valid_T, _nodeOut_c_valid_T_1)
node _nodeOut_c_valid_T_3 = or(s2_release_data_valid, _nodeOut_c_valid_T_2)
node _nodeOut_c_valid_T_4 = and(c_first, release_ack_wait)
node _nodeOut_c_valid_T_5 = eq(_nodeOut_c_valid_T_4, UInt<1>(0h0))
node _nodeOut_c_valid_T_6 = and(_nodeOut_c_valid_T_3, _nodeOut_c_valid_T_5)
connect nodeOut.c.valid, _nodeOut_c_valid_T_6
connect nodeOut.c.bits, nackResponseMessage
wire newCoh : { state : UInt<2>}
connect newCoh, probeNewCoh
connect releaseWay, s2_probe_way
when s2_victimize :
node _T_96 = or(s2_valid_flush_line, s2_flush_valid)
node _T_97 = or(_T_96, io.cpu.s2_nack)
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:817 assert(s2_valid_flush_line || s2_flush_valid || io.cpu.s2_nack)\n") : printf_6
assert(clock, _T_97, UInt<1>(0h1), "") : assert_6
node _discard_line_T = bits(s2_req.size, 1, 1)
node _discard_line_T_1 = and(s2_valid_flush_line, _discard_line_T)
node _discard_line_T_2 = bits(flushing_req.size, 1, 1)
node _discard_line_T_3 = and(s2_flush_valid, _discard_line_T_2)
node discard_line = or(_discard_line_T_1, _discard_line_T_3)
node _release_state_T = eq(discard_line, UInt<1>(0h0))
node _release_state_T_1 = and(s2_victim_dirty, _release_state_T)
node _release_state_T_2 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _release_state_T_3 = eq(release_ack_wait, UInt<1>(0h0))
node _release_state_T_4 = and(_release_state_T_2, _release_state_T_3)
node _release_state_T_5 = and(_release_state_T_4, UInt<1>(0h1))
node _release_state_T_6 = gt(s2_victim_state.state, UInt<2>(0h0))
node _release_state_T_7 = and(_release_state_T_5, _release_state_T_6)
node _release_state_T_8 = or(s2_valid_flush_line, s2_flush_valid)
node _release_state_T_9 = eq(s2_hit_valid, UInt<1>(0h0))
node _release_state_T_10 = and(s2_readwrite, _release_state_T_9)
node _release_state_T_11 = or(_release_state_T_8, _release_state_T_10)
node _release_state_T_12 = and(_release_state_T_7, _release_state_T_11)
node _release_state_T_13 = mux(_release_state_T_12, UInt<4>(0h9), UInt<4>(0h6))
node _release_state_T_14 = mux(_release_state_T_1, UInt<4>(0h1), _release_state_T_13)
connect release_state, _release_state_T_14
node _probe_bits_T_1 = bits(s2_req.addr, 7, 6)
node _probe_bits_T_2 = cat(s2_victim_tag, _probe_bits_T_1)
node _probe_bits_T_3 = shl(_probe_bits_T_2, 6)
wire probe_bits_res : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
invalidate probe_bits_res.corrupt
invalidate probe_bits_res.data
invalidate probe_bits_res.mask
invalidate probe_bits_res.address
invalidate probe_bits_res.source
invalidate probe_bits_res.size
invalidate probe_bits_res.param
invalidate probe_bits_res.opcode
connect probe_bits_res.address, _probe_bits_T_3
connect probe_bits_res.source, UInt<1>(0h0)
connect probe_bits, probe_bits_res
when s2_probe :
wire probeNack : UInt<1>
connect probeNack, UInt<1>(0h1)
when s2_meta_error :
connect release_state, UInt<4>(0h4)
else :
when s2_prb_ack_data :
connect release_state, UInt<4>(0h2)
else :
node _T_101 = gt(s2_probe_state.state, UInt<2>(0h0))
when _T_101 :
connect nodeOut.c.valid, UInt<1>(0h1)
connect nodeOut.c.bits, cleanReleaseMessage
node _release_state_T_15 = mux(releaseDone, UInt<4>(0h7), UInt<4>(0h3))
connect release_state, _release_state_T_15
else :
connect nodeOut.c.valid, UInt<1>(0h1)
node _probeNack_T = eq(releaseDone, UInt<1>(0h0))
connect probeNack, _probeNack_T
node _release_state_T_16 = mux(releaseDone, UInt<4>(0h0), UInt<4>(0h5))
connect release_state, _release_state_T_16
when probeNack :
connect s1_nack, UInt<1>(0h1)
node _T_102 = eq(release_state, UInt<4>(0h4))
when _T_102 :
connect metaArb.io.in[6].valid, UInt<1>(0h1)
node _metaArb_io_in_6_bits_idx_T_1 = bits(probe_bits.address, 7, 6)
connect metaArb.io.in[6].bits.idx, _metaArb_io_in_6_bits_idx_T_1
node _metaArb_io_in_6_bits_addr_T_2 = shr(io.cpu.req.bits.addr, 32)
node _metaArb_io_in_6_bits_addr_T_3 = cat(_metaArb_io_in_6_bits_addr_T_2, probe_bits.address)
connect metaArb.io.in[6].bits.addr, _metaArb_io_in_6_bits_addr_T_3
when metaArb.io.in[6].ready :
connect release_state, UInt<4>(0h0)
connect s1_probe, UInt<1>(0h1)
node _T_103 = eq(release_state, UInt<4>(0h5))
when _T_103 :
connect nodeOut.c.valid, UInt<1>(0h1)
when releaseDone :
connect release_state, UInt<4>(0h0)
node _T_104 = eq(release_state, UInt<4>(0h3))
when _T_104 :
connect nodeOut.c.valid, UInt<1>(0h1)
connect nodeOut.c.bits, cleanReleaseMessage
when releaseDone :
connect release_state, UInt<4>(0h7)
node _T_105 = eq(release_state, UInt<4>(0h2))
when _T_105 :
connect nodeOut.c.bits, dirtyReleaseMessage
when releaseDone :
connect release_state, UInt<4>(0h7)
node _T_106 = eq(release_state, UInt<4>(0h1))
node _T_107 = eq(release_state, UInt<4>(0h6))
node _T_108 = eq(release_state, UInt<4>(0h9))
node _T_109 = or(_T_106, _T_107)
node _T_110 = or(_T_109, _T_108)
when _T_110 :
node _T_111 = eq(release_state, UInt<4>(0h9))
when _T_111 :
node _nodeOut_c_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _nodeOut_c_bits_legal_T_1 = xor(UInt<1>(0h0), UInt<1>(0h0))
node _nodeOut_c_bits_legal_T_2 = cvt(_nodeOut_c_bits_legal_T_1)
node _nodeOut_c_bits_legal_T_3 = and(_nodeOut_c_bits_legal_T_2, asSInt(UInt<33>(0h8c020000)))
node _nodeOut_c_bits_legal_T_4 = asSInt(_nodeOut_c_bits_legal_T_3)
node _nodeOut_c_bits_legal_T_5 = eq(_nodeOut_c_bits_legal_T_4, asSInt(UInt<1>(0h0)))
node _nodeOut_c_bits_legal_T_6 = xor(UInt<1>(0h0), UInt<17>(0h10000))
node _nodeOut_c_bits_legal_T_7 = cvt(_nodeOut_c_bits_legal_T_6)
node _nodeOut_c_bits_legal_T_8 = and(_nodeOut_c_bits_legal_T_7, asSInt(UInt<33>(0h8c031000)))
node _nodeOut_c_bits_legal_T_9 = asSInt(_nodeOut_c_bits_legal_T_8)
node _nodeOut_c_bits_legal_T_10 = eq(_nodeOut_c_bits_legal_T_9, asSInt(UInt<1>(0h0)))
node _nodeOut_c_bits_legal_T_11 = xor(UInt<1>(0h0), UInt<18>(0h20000))
node _nodeOut_c_bits_legal_T_12 = cvt(_nodeOut_c_bits_legal_T_11)
node _nodeOut_c_bits_legal_T_13 = and(_nodeOut_c_bits_legal_T_12, asSInt(UInt<33>(0h8c030000)))
node _nodeOut_c_bits_legal_T_14 = asSInt(_nodeOut_c_bits_legal_T_13)
node _nodeOut_c_bits_legal_T_15 = eq(_nodeOut_c_bits_legal_T_14, asSInt(UInt<1>(0h0)))
node _nodeOut_c_bits_legal_T_16 = xor(UInt<1>(0h0), UInt<28>(0hc000000))
node _nodeOut_c_bits_legal_T_17 = cvt(_nodeOut_c_bits_legal_T_16)
node _nodeOut_c_bits_legal_T_18 = and(_nodeOut_c_bits_legal_T_17, asSInt(UInt<33>(0h8c000000)))
node _nodeOut_c_bits_legal_T_19 = asSInt(_nodeOut_c_bits_legal_T_18)
node _nodeOut_c_bits_legal_T_20 = eq(_nodeOut_c_bits_legal_T_19, asSInt(UInt<1>(0h0)))
node _nodeOut_c_bits_legal_T_21 = or(_nodeOut_c_bits_legal_T_5, _nodeOut_c_bits_legal_T_10)
node _nodeOut_c_bits_legal_T_22 = or(_nodeOut_c_bits_legal_T_21, _nodeOut_c_bits_legal_T_15)
node _nodeOut_c_bits_legal_T_23 = or(_nodeOut_c_bits_legal_T_22, _nodeOut_c_bits_legal_T_20)
node _nodeOut_c_bits_legal_T_24 = and(_nodeOut_c_bits_legal_T, _nodeOut_c_bits_legal_T_23)
node _nodeOut_c_bits_legal_T_25 = eq(UInt<3>(0h6), UInt<3>(0h6))
node _nodeOut_c_bits_legal_T_26 = or(UInt<1>(0h0), _nodeOut_c_bits_legal_T_25)
node _nodeOut_c_bits_legal_T_27 = xor(UInt<1>(0h0), UInt<28>(0h8000000))
node _nodeOut_c_bits_legal_T_28 = cvt(_nodeOut_c_bits_legal_T_27)
node _nodeOut_c_bits_legal_T_29 = and(_nodeOut_c_bits_legal_T_28, asSInt(UInt<33>(0h8c030000)))
node _nodeOut_c_bits_legal_T_30 = asSInt(_nodeOut_c_bits_legal_T_29)
node _nodeOut_c_bits_legal_T_31 = eq(_nodeOut_c_bits_legal_T_30, asSInt(UInt<1>(0h0)))
node _nodeOut_c_bits_legal_T_32 = xor(UInt<1>(0h0), UInt<32>(0h80000000))
node _nodeOut_c_bits_legal_T_33 = cvt(_nodeOut_c_bits_legal_T_32)
node _nodeOut_c_bits_legal_T_34 = and(_nodeOut_c_bits_legal_T_33, asSInt(UInt<33>(0h80000000)))
node _nodeOut_c_bits_legal_T_35 = asSInt(_nodeOut_c_bits_legal_T_34)
node _nodeOut_c_bits_legal_T_36 = eq(_nodeOut_c_bits_legal_T_35, asSInt(UInt<1>(0h0)))
node _nodeOut_c_bits_legal_T_37 = or(_nodeOut_c_bits_legal_T_31, _nodeOut_c_bits_legal_T_36)
node _nodeOut_c_bits_legal_T_38 = and(_nodeOut_c_bits_legal_T_26, _nodeOut_c_bits_legal_T_37)
node _nodeOut_c_bits_legal_T_39 = or(UInt<1>(0h0), _nodeOut_c_bits_legal_T_24)
node nodeOut_c_bits_legal = or(_nodeOut_c_bits_legal_T_39, _nodeOut_c_bits_legal_T_38)
wire nodeOut_c_bits_c : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect nodeOut_c_bits_c.opcode, UInt<3>(0h6)
connect nodeOut_c_bits_c.param, s2_shrink_param
connect nodeOut_c_bits_c.size, UInt<3>(0h6)
connect nodeOut_c_bits_c.source, UInt<1>(0h0)
connect nodeOut_c_bits_c.address, UInt<1>(0h0)
invalidate nodeOut_c_bits_c.data
connect nodeOut_c_bits_c.corrupt, UInt<1>(0h0)
connect nodeOut.c.bits, nodeOut_c_bits_c
else :
node _nodeOut_c_bits_legal_T_40 = or(UInt<1>(0h0), UInt<1>(0h0))
node _nodeOut_c_bits_legal_T_41 = xor(UInt<1>(0h0), UInt<1>(0h0))
node _nodeOut_c_bits_legal_T_42 = cvt(_nodeOut_c_bits_legal_T_41)
node _nodeOut_c_bits_legal_T_43 = and(_nodeOut_c_bits_legal_T_42, asSInt(UInt<33>(0h8c020000)))
node _nodeOut_c_bits_legal_T_44 = asSInt(_nodeOut_c_bits_legal_T_43)
node _nodeOut_c_bits_legal_T_45 = eq(_nodeOut_c_bits_legal_T_44, asSInt(UInt<1>(0h0)))
node _nodeOut_c_bits_legal_T_46 = xor(UInt<1>(0h0), UInt<17>(0h10000))
node _nodeOut_c_bits_legal_T_47 = cvt(_nodeOut_c_bits_legal_T_46)
node _nodeOut_c_bits_legal_T_48 = and(_nodeOut_c_bits_legal_T_47, asSInt(UInt<33>(0h8c031000)))
node _nodeOut_c_bits_legal_T_49 = asSInt(_nodeOut_c_bits_legal_T_48)
node _nodeOut_c_bits_legal_T_50 = eq(_nodeOut_c_bits_legal_T_49, asSInt(UInt<1>(0h0)))
node _nodeOut_c_bits_legal_T_51 = xor(UInt<1>(0h0), UInt<18>(0h20000))
node _nodeOut_c_bits_legal_T_52 = cvt(_nodeOut_c_bits_legal_T_51)
node _nodeOut_c_bits_legal_T_53 = and(_nodeOut_c_bits_legal_T_52, asSInt(UInt<33>(0h8c030000)))
node _nodeOut_c_bits_legal_T_54 = asSInt(_nodeOut_c_bits_legal_T_53)
node _nodeOut_c_bits_legal_T_55 = eq(_nodeOut_c_bits_legal_T_54, asSInt(UInt<1>(0h0)))
node _nodeOut_c_bits_legal_T_56 = xor(UInt<1>(0h0), UInt<28>(0hc000000))
node _nodeOut_c_bits_legal_T_57 = cvt(_nodeOut_c_bits_legal_T_56)
node _nodeOut_c_bits_legal_T_58 = and(_nodeOut_c_bits_legal_T_57, asSInt(UInt<33>(0h8c000000)))
node _nodeOut_c_bits_legal_T_59 = asSInt(_nodeOut_c_bits_legal_T_58)
node _nodeOut_c_bits_legal_T_60 = eq(_nodeOut_c_bits_legal_T_59, asSInt(UInt<1>(0h0)))
node _nodeOut_c_bits_legal_T_61 = or(_nodeOut_c_bits_legal_T_45, _nodeOut_c_bits_legal_T_50)
node _nodeOut_c_bits_legal_T_62 = or(_nodeOut_c_bits_legal_T_61, _nodeOut_c_bits_legal_T_55)
node _nodeOut_c_bits_legal_T_63 = or(_nodeOut_c_bits_legal_T_62, _nodeOut_c_bits_legal_T_60)
node _nodeOut_c_bits_legal_T_64 = and(_nodeOut_c_bits_legal_T_40, _nodeOut_c_bits_legal_T_63)
node _nodeOut_c_bits_legal_T_65 = eq(UInt<3>(0h6), UInt<3>(0h6))
node _nodeOut_c_bits_legal_T_66 = or(UInt<1>(0h0), _nodeOut_c_bits_legal_T_65)
node _nodeOut_c_bits_legal_T_67 = xor(UInt<1>(0h0), UInt<28>(0h8000000))
node _nodeOut_c_bits_legal_T_68 = cvt(_nodeOut_c_bits_legal_T_67)
node _nodeOut_c_bits_legal_T_69 = and(_nodeOut_c_bits_legal_T_68, asSInt(UInt<33>(0h8c030000)))
node _nodeOut_c_bits_legal_T_70 = asSInt(_nodeOut_c_bits_legal_T_69)
node _nodeOut_c_bits_legal_T_71 = eq(_nodeOut_c_bits_legal_T_70, asSInt(UInt<1>(0h0)))
node _nodeOut_c_bits_legal_T_72 = xor(UInt<1>(0h0), UInt<32>(0h80000000))
node _nodeOut_c_bits_legal_T_73 = cvt(_nodeOut_c_bits_legal_T_72)
node _nodeOut_c_bits_legal_T_74 = and(_nodeOut_c_bits_legal_T_73, asSInt(UInt<33>(0h80000000)))
node _nodeOut_c_bits_legal_T_75 = asSInt(_nodeOut_c_bits_legal_T_74)
node _nodeOut_c_bits_legal_T_76 = eq(_nodeOut_c_bits_legal_T_75, asSInt(UInt<1>(0h0)))
node _nodeOut_c_bits_legal_T_77 = or(_nodeOut_c_bits_legal_T_71, _nodeOut_c_bits_legal_T_76)
node _nodeOut_c_bits_legal_T_78 = and(_nodeOut_c_bits_legal_T_66, _nodeOut_c_bits_legal_T_77)
node _nodeOut_c_bits_legal_T_79 = or(UInt<1>(0h0), _nodeOut_c_bits_legal_T_64)
node nodeOut_c_bits_legal_1 = or(_nodeOut_c_bits_legal_T_79, _nodeOut_c_bits_legal_T_78)
wire nodeOut_c_bits_c_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect nodeOut_c_bits_c_1.opcode, UInt<3>(0h7)
connect nodeOut_c_bits_c_1.param, s2_shrink_param
connect nodeOut_c_bits_c_1.size, UInt<3>(0h6)
connect nodeOut_c_bits_c_1.source, UInt<1>(0h0)
connect nodeOut_c_bits_c_1.address, UInt<1>(0h0)
connect nodeOut_c_bits_c_1.data, UInt<1>(0h0)
connect nodeOut_c_bits_c_1.corrupt, UInt<1>(0h0)
connect nodeOut.c.bits, nodeOut_c_bits_c_1
connect newCoh, voluntaryNewCoh
connect releaseWay, s2_victim_or_hit_way
when releaseDone :
connect release_state, UInt<4>(0h6)
node _T_112 = and(nodeOut.c.ready, nodeOut.c.valid)
node _T_113 = and(_T_112, c_first)
when _T_113 :
connect release_ack_wait, UInt<1>(0h1)
connect release_ack_addr, probe_bits.address
connect nodeOut.c.bits.source, probe_bits.source
connect nodeOut.c.bits.address, probe_bits.address
connect nodeOut.c.bits.data, s2_data_corrected
node _nodeOut_c_bits_corrupt_T = and(inWriteback, s2_data_error_uncorrectable)
connect nodeOut.c.bits.corrupt, _nodeOut_c_bits_corrupt_T
node _dataArb_io_in_2_valid_T = lt(releaseDataBeat, UInt<4>(0h8))
node _dataArb_io_in_2_valid_T_1 = and(inWriteback, _dataArb_io_in_2_valid_T)
connect dataArb.io.in[2].valid, _dataArb_io_in_2_valid_T_1
connect dataArb.io.in[2].bits.way_en, dataArb.io.in[1].bits.way_en
connect dataArb.io.in[2].bits.eccMask, dataArb.io.in[1].bits.eccMask
connect dataArb.io.in[2].bits.wordMask, dataArb.io.in[1].bits.wordMask
connect dataArb.io.in[2].bits.wdata, dataArb.io.in[1].bits.wdata
connect dataArb.io.in[2].bits.write, dataArb.io.in[1].bits.write
connect dataArb.io.in[2].bits.addr, dataArb.io.in[1].bits.addr
connect dataArb.io.in[2].bits.write, UInt<1>(0h0)
node _dataArb_io_in_2_bits_addr_T = bits(probe_bits.address, 7, 6)
node _dataArb_io_in_2_bits_addr_T_1 = shl(_dataArb_io_in_2_bits_addr_T, 6)
node _dataArb_io_in_2_bits_addr_T_2 = bits(releaseDataBeat, 2, 0)
node _dataArb_io_in_2_bits_addr_T_3 = shl(_dataArb_io_in_2_bits_addr_T_2, 3)
node _dataArb_io_in_2_bits_addr_T_4 = or(_dataArb_io_in_2_bits_addr_T_1, _dataArb_io_in_2_bits_addr_T_3)
connect dataArb.io.in[2].bits.addr, _dataArb_io_in_2_bits_addr_T_4
node _dataArb_io_in_2_bits_wordMask_T = not(UInt<1>(0h0))
connect dataArb.io.in[2].bits.wordMask, _dataArb_io_in_2_bits_wordMask_T
node _dataArb_io_in_2_bits_eccMask_T = not(UInt<8>(0h0))
connect dataArb.io.in[2].bits.eccMask, _dataArb_io_in_2_bits_eccMask_T
node _dataArb_io_in_2_bits_way_en_T = not(UInt<4>(0h0))
connect dataArb.io.in[2].bits.way_en, _dataArb_io_in_2_bits_way_en_T
node _metaArb_io_in_4_valid_T = eq(release_state, UInt<4>(0h6))
node _metaArb_io_in_4_valid_T_1 = eq(release_state, UInt<4>(0h7))
node _metaArb_io_in_4_valid_T_2 = or(_metaArb_io_in_4_valid_T, _metaArb_io_in_4_valid_T_1)
connect metaArb.io.in[4].valid, _metaArb_io_in_4_valid_T_2
connect metaArb.io.in[4].bits.write, UInt<1>(0h1)
connect metaArb.io.in[4].bits.way_en, releaseWay
node _metaArb_io_in_4_bits_idx_T = bits(probe_bits.address, 7, 6)
connect metaArb.io.in[4].bits.idx, _metaArb_io_in_4_bits_idx_T
node _metaArb_io_in_4_bits_addr_T = shr(io.cpu.req.bits.addr, 8)
node _metaArb_io_in_4_bits_addr_T_1 = bits(probe_bits.address, 7, 0)
node _metaArb_io_in_4_bits_addr_T_2 = cat(_metaArb_io_in_4_bits_addr_T, _metaArb_io_in_4_bits_addr_T_1)
connect metaArb.io.in[4].bits.addr, _metaArb_io_in_4_bits_addr_T_2
node _metaArb_io_in_4_bits_data_T = shr(nodeOut.c.bits.address, 8)
wire metaArb_io_in_4_bits_data_meta : { coh : { state : UInt<2>}, tag : UInt<24>}
connect metaArb_io_in_4_bits_data_meta.tag, _metaArb_io_in_4_bits_data_T
connect metaArb_io_in_4_bits_data_meta.coh, newCoh
node _metaArb_io_in_4_bits_data_T_1 = cat(metaArb_io_in_4_bits_data_meta.coh.state, metaArb_io_in_4_bits_data_meta.tag)
connect metaArb.io.in[4].bits.data, _metaArb_io_in_4_bits_data_T_1
node _T_114 = and(metaArb.io.in[4].ready, metaArb.io.in[4].valid)
when _T_114 :
connect release_state, UInt<4>(0h0)
connect io.cpu.resp.bits.mask, s2_req.mask
connect io.cpu.resp.bits.data, s2_req.data
connect io.cpu.resp.bits.dv, s2_req.dv
connect io.cpu.resp.bits.dprv, s2_req.dprv
connect io.cpu.resp.bits.signed, s2_req.signed
connect io.cpu.resp.bits.size, s2_req.size
connect io.cpu.resp.bits.cmd, s2_req.cmd
connect io.cpu.resp.bits.tag, s2_req.tag
connect io.cpu.resp.bits.addr, s2_req.addr
connect io.cpu.resp.bits.has_data, s2_read
connect io.cpu.resp.bits.replay, UInt<1>(0h0)
node _io_cpu_s2_uncached_T = eq(s2_hit, UInt<1>(0h0))
node _io_cpu_s2_uncached_T_1 = and(s2_uncached, _io_cpu_s2_uncached_T)
connect io.cpu.s2_uncached, _io_cpu_s2_uncached_T_1
connect io.cpu.s2_paddr, s2_req.addr
connect io.cpu.s2_gpa, s2_tlb_xcpt.gpa
connect io.cpu.s2_gpa_is_pte, s2_tlb_xcpt.gpa_is_pte
node _io_cpu_ordered_T = eq(s1_req.no_xcpt, UInt<1>(0h0))
node _io_cpu_ordered_T_1 = and(s1_valid, _io_cpu_ordered_T)
node _io_cpu_ordered_T_2 = eq(s2_req.no_xcpt, UInt<1>(0h0))
node _io_cpu_ordered_T_3 = and(s2_valid, _io_cpu_ordered_T_2)
node _io_cpu_ordered_T_4 = or(_io_cpu_ordered_T_1, _io_cpu_ordered_T_3)
node _io_cpu_ordered_T_5 = or(_io_cpu_ordered_T_4, cached_grant_wait)
node _io_cpu_ordered_T_6 = orr(uncachedInFlight[0])
node _io_cpu_ordered_T_7 = or(_io_cpu_ordered_T_5, _io_cpu_ordered_T_6)
node _io_cpu_ordered_T_8 = eq(_io_cpu_ordered_T_7, UInt<1>(0h0))
connect io.cpu.ordered, _io_cpu_ordered_T_8
node _io_cpu_store_pending_T = eq(s2_req.cmd, UInt<1>(0h1))
node _io_cpu_store_pending_T_1 = eq(s2_req.cmd, UInt<5>(0h11))
node _io_cpu_store_pending_T_2 = or(_io_cpu_store_pending_T, _io_cpu_store_pending_T_1)
node _io_cpu_store_pending_T_3 = eq(s2_req.cmd, UInt<3>(0h7))
node _io_cpu_store_pending_T_4 = or(_io_cpu_store_pending_T_2, _io_cpu_store_pending_T_3)
node _io_cpu_store_pending_T_5 = eq(s2_req.cmd, UInt<3>(0h4))
node _io_cpu_store_pending_T_6 = eq(s2_req.cmd, UInt<4>(0h9))
node _io_cpu_store_pending_T_7 = eq(s2_req.cmd, UInt<4>(0ha))
node _io_cpu_store_pending_T_8 = eq(s2_req.cmd, UInt<4>(0hb))
node _io_cpu_store_pending_T_9 = or(_io_cpu_store_pending_T_5, _io_cpu_store_pending_T_6)
node _io_cpu_store_pending_T_10 = or(_io_cpu_store_pending_T_9, _io_cpu_store_pending_T_7)
node _io_cpu_store_pending_T_11 = or(_io_cpu_store_pending_T_10, _io_cpu_store_pending_T_8)
node _io_cpu_store_pending_T_12 = eq(s2_req.cmd, UInt<4>(0h8))
node _io_cpu_store_pending_T_13 = eq(s2_req.cmd, UInt<4>(0hc))
node _io_cpu_store_pending_T_14 = eq(s2_req.cmd, UInt<4>(0hd))
node _io_cpu_store_pending_T_15 = eq(s2_req.cmd, UInt<4>(0he))
node _io_cpu_store_pending_T_16 = eq(s2_req.cmd, UInt<4>(0hf))
node _io_cpu_store_pending_T_17 = or(_io_cpu_store_pending_T_12, _io_cpu_store_pending_T_13)
node _io_cpu_store_pending_T_18 = or(_io_cpu_store_pending_T_17, _io_cpu_store_pending_T_14)
node _io_cpu_store_pending_T_19 = or(_io_cpu_store_pending_T_18, _io_cpu_store_pending_T_15)
node _io_cpu_store_pending_T_20 = or(_io_cpu_store_pending_T_19, _io_cpu_store_pending_T_16)
node _io_cpu_store_pending_T_21 = or(_io_cpu_store_pending_T_11, _io_cpu_store_pending_T_20)
node _io_cpu_store_pending_T_22 = or(_io_cpu_store_pending_T_4, _io_cpu_store_pending_T_21)
node _io_cpu_store_pending_T_23 = and(cached_grant_wait, _io_cpu_store_pending_T_22)
node _io_cpu_store_pending_T_24 = orr(uncachedInFlight[0])
node _io_cpu_store_pending_T_25 = or(_io_cpu_store_pending_T_23, _io_cpu_store_pending_T_24)
connect io.cpu.store_pending, _io_cpu_store_pending_T_25
node _s1_xcpt_valid_T = eq(s1_req.no_xcpt, UInt<1>(0h0))
node _s1_xcpt_valid_T_1 = and(tlb.io.req.valid, _s1_xcpt_valid_T)
node _s1_xcpt_valid_T_2 = eq(s1_nack, UInt<1>(0h0))
node s1_xcpt_valid = and(_s1_xcpt_valid_T_1, _s1_xcpt_valid_T_2)
reg io_cpu_s2_xcpt_REG : UInt<1>, clock
connect io_cpu_s2_xcpt_REG, s1_xcpt_valid
wire _io_cpu_s2_xcpt_WIRE : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}
connect _io_cpu_s2_xcpt_WIRE.cmd, UInt<5>(0h0)
connect _io_cpu_s2_xcpt_WIRE.size, UInt<2>(0h0)
connect _io_cpu_s2_xcpt_WIRE.prefetchable, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.must_alloc, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.cacheable, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ma.inst, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ma.st, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ma.ld, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ae.inst, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ae.st, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ae.ld, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.gf.inst, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.gf.st, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.gf.ld, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.pf.inst, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.pf.st, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.pf.ld, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.gpa_is_pte, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.gpa, UInt<40>(0h0)
connect _io_cpu_s2_xcpt_WIRE.paddr, UInt<32>(0h0)
connect _io_cpu_s2_xcpt_WIRE.miss, UInt<1>(0h0)
node _io_cpu_s2_xcpt_T = mux(io_cpu_s2_xcpt_REG, s2_tlb_xcpt, _io_cpu_s2_xcpt_WIRE)
connect io.cpu.s2_xcpt.ae.st, _io_cpu_s2_xcpt_T.ae.st
connect io.cpu.s2_xcpt.ae.ld, _io_cpu_s2_xcpt_T.ae.ld
connect io.cpu.s2_xcpt.gf.st, _io_cpu_s2_xcpt_T.gf.st
connect io.cpu.s2_xcpt.gf.ld, _io_cpu_s2_xcpt_T.gf.ld
connect io.cpu.s2_xcpt.pf.st, _io_cpu_s2_xcpt_T.pf.st
connect io.cpu.s2_xcpt.pf.ld, _io_cpu_s2_xcpt_T.pf.ld
connect io.cpu.s2_xcpt.ma.st, _io_cpu_s2_xcpt_T.ma.st
connect io.cpu.s2_xcpt.ma.ld, _io_cpu_s2_xcpt_T.ma.ld
node _T_115 = eq(nodeOut.b.ready, UInt<1>(0h0))
node _T_116 = and(nodeOut.b.valid, _T_115)
node s1_uncached_data_word = bits(nodeOut.d.bits.data, 63, 0)
reg s2_uncached_data_word : UInt<64>, clock
when io.cpu.replay_next :
connect s2_uncached_data_word, s1_uncached_data_word
reg doUncachedResp : UInt<1>, clock
connect doUncachedResp, io.cpu.replay_next
node _io_cpu_resp_valid_T = or(s2_valid_hit_pre_data_ecc, doUncachedResp)
node _io_cpu_resp_valid_T_1 = eq(s2_data_error, UInt<1>(0h0))
node _io_cpu_resp_valid_T_2 = and(_io_cpu_resp_valid_T, _io_cpu_resp_valid_T_1)
connect io.cpu.resp.valid, _io_cpu_resp_valid_T_2
node _io_cpu_replay_next_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _io_cpu_replay_next_T_1 = and(_io_cpu_replay_next_T, grantIsUncachedData)
node _io_cpu_replay_next_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _io_cpu_replay_next_T_3 = and(_io_cpu_replay_next_T_1, _io_cpu_replay_next_T_2)
connect io.cpu.replay_next, _io_cpu_replay_next_T_3
when doUncachedResp :
node _T_117 = eq(s2_valid_hit, UInt<1>(0h0))
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:952 assert(!s2_valid_hit)\n") : printf_7
assert(clock, _T_117, UInt<1>(0h1), "") : assert_7
connect io.cpu.resp.bits.replay, UInt<1>(0h1)
connect io.cpu.resp.bits.addr, s2_uncached_resp_addr
node s2_data_word = bits(s2_data_uncorrected, 63, 0)
node s2_data_word_corrected = bits(s2_data_corrected, 63, 0)
node _s2_data_word_possibly_uncached_T = and(UInt<1>(0h0), doUncachedResp)
node _s2_data_word_possibly_uncached_T_1 = mux(_s2_data_word_possibly_uncached_T, s2_uncached_data_word, UInt<1>(0h0))
node s2_data_word_possibly_uncached = or(_s2_data_word_possibly_uncached_T_1, s2_data_word)
wire size : UInt<2>
connect size, s2_req.size
node _io_cpu_resp_bits_data_shifted_T = bits(s2_req.addr, 2, 2)
node _io_cpu_resp_bits_data_shifted_T_1 = bits(s2_data_word_possibly_uncached, 63, 32)
node _io_cpu_resp_bits_data_shifted_T_2 = bits(s2_data_word_possibly_uncached, 31, 0)
node io_cpu_resp_bits_data_shifted = mux(_io_cpu_resp_bits_data_shifted_T, _io_cpu_resp_bits_data_shifted_T_1, _io_cpu_resp_bits_data_shifted_T_2)
node io_cpu_resp_bits_data_doZero = and(UInt<1>(0h0), s2_sc)
node io_cpu_resp_bits_data_zeroed = mux(io_cpu_resp_bits_data_doZero, UInt<1>(0h0), io_cpu_resp_bits_data_shifted)
node _io_cpu_resp_bits_data_T = eq(size, UInt<2>(0h2))
node _io_cpu_resp_bits_data_T_1 = or(_io_cpu_resp_bits_data_T, io_cpu_resp_bits_data_doZero)
node _io_cpu_resp_bits_data_T_2 = bits(io_cpu_resp_bits_data_zeroed, 31, 31)
node _io_cpu_resp_bits_data_T_3 = and(s2_req.signed, _io_cpu_resp_bits_data_T_2)
node _io_cpu_resp_bits_data_T_4 = mux(_io_cpu_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_cpu_resp_bits_data_T_5 = bits(s2_data_word_possibly_uncached, 63, 32)
node _io_cpu_resp_bits_data_T_6 = mux(_io_cpu_resp_bits_data_T_1, _io_cpu_resp_bits_data_T_4, _io_cpu_resp_bits_data_T_5)
node _io_cpu_resp_bits_data_T_7 = cat(_io_cpu_resp_bits_data_T_6, io_cpu_resp_bits_data_zeroed)
node _io_cpu_resp_bits_data_shifted_T_3 = bits(s2_req.addr, 1, 1)
node _io_cpu_resp_bits_data_shifted_T_4 = bits(_io_cpu_resp_bits_data_T_7, 31, 16)
node _io_cpu_resp_bits_data_shifted_T_5 = bits(_io_cpu_resp_bits_data_T_7, 15, 0)
node io_cpu_resp_bits_data_shifted_1 = mux(_io_cpu_resp_bits_data_shifted_T_3, _io_cpu_resp_bits_data_shifted_T_4, _io_cpu_resp_bits_data_shifted_T_5)
node io_cpu_resp_bits_data_doZero_1 = and(UInt<1>(0h0), s2_sc)
node io_cpu_resp_bits_data_zeroed_1 = mux(io_cpu_resp_bits_data_doZero_1, UInt<1>(0h0), io_cpu_resp_bits_data_shifted_1)
node _io_cpu_resp_bits_data_T_8 = eq(size, UInt<1>(0h1))
node _io_cpu_resp_bits_data_T_9 = or(_io_cpu_resp_bits_data_T_8, io_cpu_resp_bits_data_doZero_1)
node _io_cpu_resp_bits_data_T_10 = bits(io_cpu_resp_bits_data_zeroed_1, 15, 15)
node _io_cpu_resp_bits_data_T_11 = and(s2_req.signed, _io_cpu_resp_bits_data_T_10)
node _io_cpu_resp_bits_data_T_12 = mux(_io_cpu_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _io_cpu_resp_bits_data_T_13 = bits(_io_cpu_resp_bits_data_T_7, 63, 16)
node _io_cpu_resp_bits_data_T_14 = mux(_io_cpu_resp_bits_data_T_9, _io_cpu_resp_bits_data_T_12, _io_cpu_resp_bits_data_T_13)
node _io_cpu_resp_bits_data_T_15 = cat(_io_cpu_resp_bits_data_T_14, io_cpu_resp_bits_data_zeroed_1)
node _io_cpu_resp_bits_data_shifted_T_6 = bits(s2_req.addr, 0, 0)
node _io_cpu_resp_bits_data_shifted_T_7 = bits(_io_cpu_resp_bits_data_T_15, 15, 8)
node _io_cpu_resp_bits_data_shifted_T_8 = bits(_io_cpu_resp_bits_data_T_15, 7, 0)
node io_cpu_resp_bits_data_shifted_2 = mux(_io_cpu_resp_bits_data_shifted_T_6, _io_cpu_resp_bits_data_shifted_T_7, _io_cpu_resp_bits_data_shifted_T_8)
node io_cpu_resp_bits_data_doZero_2 = and(UInt<1>(0h1), s2_sc)
node io_cpu_resp_bits_data_zeroed_2 = mux(io_cpu_resp_bits_data_doZero_2, UInt<1>(0h0), io_cpu_resp_bits_data_shifted_2)
node _io_cpu_resp_bits_data_T_16 = eq(size, UInt<1>(0h0))
node _io_cpu_resp_bits_data_T_17 = or(_io_cpu_resp_bits_data_T_16, io_cpu_resp_bits_data_doZero_2)
node _io_cpu_resp_bits_data_T_18 = bits(io_cpu_resp_bits_data_zeroed_2, 7, 7)
node _io_cpu_resp_bits_data_T_19 = and(s2_req.signed, _io_cpu_resp_bits_data_T_18)
node _io_cpu_resp_bits_data_T_20 = mux(_io_cpu_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _io_cpu_resp_bits_data_T_21 = bits(_io_cpu_resp_bits_data_T_15, 63, 8)
node _io_cpu_resp_bits_data_T_22 = mux(_io_cpu_resp_bits_data_T_17, _io_cpu_resp_bits_data_T_20, _io_cpu_resp_bits_data_T_21)
node _io_cpu_resp_bits_data_T_23 = cat(_io_cpu_resp_bits_data_T_22, io_cpu_resp_bits_data_zeroed_2)
node _io_cpu_resp_bits_data_T_24 = or(_io_cpu_resp_bits_data_T_23, s2_sc_fail)
connect io.cpu.resp.bits.data, _io_cpu_resp_bits_data_T_24
node _io_cpu_resp_bits_data_word_bypass_shifted_T = bits(s2_req.addr, 2, 2)
node _io_cpu_resp_bits_data_word_bypass_shifted_T_1 = bits(s2_data_word_possibly_uncached, 63, 32)
node _io_cpu_resp_bits_data_word_bypass_shifted_T_2 = bits(s2_data_word_possibly_uncached, 31, 0)
node io_cpu_resp_bits_data_word_bypass_shifted = mux(_io_cpu_resp_bits_data_word_bypass_shifted_T, _io_cpu_resp_bits_data_word_bypass_shifted_T_1, _io_cpu_resp_bits_data_word_bypass_shifted_T_2)
node io_cpu_resp_bits_data_word_bypass_doZero = and(UInt<1>(0h0), s2_sc)
node io_cpu_resp_bits_data_word_bypass_zeroed = mux(io_cpu_resp_bits_data_word_bypass_doZero, UInt<1>(0h0), io_cpu_resp_bits_data_word_bypass_shifted)
node _io_cpu_resp_bits_data_word_bypass_T = eq(size, UInt<2>(0h2))
node _io_cpu_resp_bits_data_word_bypass_T_1 = or(_io_cpu_resp_bits_data_word_bypass_T, io_cpu_resp_bits_data_word_bypass_doZero)
node _io_cpu_resp_bits_data_word_bypass_T_2 = bits(io_cpu_resp_bits_data_word_bypass_zeroed, 31, 31)
node _io_cpu_resp_bits_data_word_bypass_T_3 = and(s2_req.signed, _io_cpu_resp_bits_data_word_bypass_T_2)
node _io_cpu_resp_bits_data_word_bypass_T_4 = mux(_io_cpu_resp_bits_data_word_bypass_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_cpu_resp_bits_data_word_bypass_T_5 = bits(s2_data_word_possibly_uncached, 63, 32)
node _io_cpu_resp_bits_data_word_bypass_T_6 = mux(_io_cpu_resp_bits_data_word_bypass_T_1, _io_cpu_resp_bits_data_word_bypass_T_4, _io_cpu_resp_bits_data_word_bypass_T_5)
node _io_cpu_resp_bits_data_word_bypass_T_7 = cat(_io_cpu_resp_bits_data_word_bypass_T_6, io_cpu_resp_bits_data_word_bypass_zeroed)
connect io.cpu.resp.bits.data_word_bypass, _io_cpu_resp_bits_data_word_bypass_T_7
connect io.cpu.resp.bits.data_raw, s2_data_word
connect io.cpu.resp.bits.store_data, pstore1_data
node _T_121 = and(s1_valid_masked, s1_read)
node _T_122 = and(_T_121, s1_write)
node _T_123 = eq(_T_122, UInt<1>(0h0))
node _T_124 = asUInt(reset)
node _T_125 = eq(_T_124, UInt<1>(0h0))
when _T_125 :
node _T_126 = eq(_T_123, UInt<1>(0h0))
when _T_126 :
printf(clock, UInt<1>(0h1), "Assertion failed: unsupported D$ operation\n at DCache.scala:994 assert(!(s1_valid_masked && s1_read && s1_write), \"unsupported D$ operation\")\n") : printf_8
assert(clock, _T_123, UInt<1>(0h1), "") : assert_8
node _T_127 = asUInt(reset)
reg REG : UInt<1>, clock
connect REG, _T_127
when REG :
connect resetting, UInt<1>(0h1)
node flushCounterNext = add(flushCounter, UInt<1>(0h1))
node _flushDone_T = shr(flushCounterNext, 2)
node flushDone = eq(_flushDone_T, UInt<3>(0h4))
node flushCounterWrap = bits(flushCounterNext, 1, 0)
node _T_128 = and(s2_valid_masked, s2_cmd_flush_all)
node _T_129 = and(_T_128, s2_meta_error)
node _T_130 = and(s2_valid_masked, s2_cmd_flush_all)
node _T_131 = and(_T_130, s2_data_error)
node _s1_flush_valid_T = and(metaArb.io.in[5].ready, metaArb.io.in[5].valid)
node _s1_flush_valid_T_1 = eq(s1_flush_valid, UInt<1>(0h0))
node _s1_flush_valid_T_2 = and(_s1_flush_valid_T, _s1_flush_valid_T_1)
node _s1_flush_valid_T_3 = eq(s2_flush_valid_pre_tag_ecc, UInt<1>(0h0))
node _s1_flush_valid_T_4 = and(_s1_flush_valid_T_2, _s1_flush_valid_T_3)
node _s1_flush_valid_T_5 = eq(release_state, UInt<4>(0h0))
node _s1_flush_valid_T_6 = and(_s1_flush_valid_T_4, _s1_flush_valid_T_5)
node _s1_flush_valid_T_7 = eq(release_ack_wait, UInt<1>(0h0))
node _s1_flush_valid_T_8 = and(_s1_flush_valid_T_6, _s1_flush_valid_T_7)
connect s1_flush_valid, _s1_flush_valid_T_8
node _metaArb_io_in_5_valid_T = eq(flushed, UInt<1>(0h0))
node _metaArb_io_in_5_valid_T_1 = and(flushing, _metaArb_io_in_5_valid_T)
connect metaArb.io.in[5].valid, _metaArb_io_in_5_valid_T_1
connect metaArb.io.in[5].bits.write, UInt<1>(0h0)
node _metaArb_io_in_5_bits_idx_T = bits(flushCounter, 1, 0)
connect metaArb.io.in[5].bits.idx, _metaArb_io_in_5_bits_idx_T
node _metaArb_io_in_5_bits_addr_T = shr(io.cpu.req.bits.addr, 8)
node _metaArb_io_in_5_bits_addr_T_1 = shl(metaArb.io.in[5].bits.idx, 6)
node _metaArb_io_in_5_bits_addr_T_2 = cat(_metaArb_io_in_5_bits_addr_T, _metaArb_io_in_5_bits_addr_T_1)
connect metaArb.io.in[5].bits.addr, _metaArb_io_in_5_bits_addr_T_2
connect metaArb.io.in[5].bits.way_en, metaArb.io.in[4].bits.way_en
connect metaArb.io.in[5].bits.data, metaArb.io.in[4].bits.data
connect metaArb.io.in[0].valid, resetting
connect metaArb.io.in[0].bits.data, metaArb.io.in[5].bits.data
connect metaArb.io.in[0].bits.way_en, metaArb.io.in[5].bits.way_en
connect metaArb.io.in[0].bits.idx, metaArb.io.in[5].bits.idx
connect metaArb.io.in[0].bits.addr, metaArb.io.in[5].bits.addr
connect metaArb.io.in[0].bits.write, metaArb.io.in[5].bits.write
connect metaArb.io.in[0].bits.write, UInt<1>(0h1)
node _metaArb_io_in_0_bits_way_en_T = not(UInt<4>(0h0))
connect metaArb.io.in[0].bits.way_en, _metaArb_io_in_0_bits_way_en_T
wire metaArb_io_in_0_bits_data_meta : { state : UInt<2>}
connect metaArb_io_in_0_bits_data_meta.state, UInt<2>(0h0)
wire metaArb_io_in_0_bits_data_meta_1 : { coh : { state : UInt<2>}, tag : UInt<24>}
connect metaArb_io_in_0_bits_data_meta_1.tag, UInt<1>(0h0)
connect metaArb_io_in_0_bits_data_meta_1.coh, metaArb_io_in_0_bits_data_meta
node _metaArb_io_in_0_bits_data_T = cat(metaArb_io_in_0_bits_data_meta_1.coh.state, metaArb_io_in_0_bits_data_meta_1.tag)
connect metaArb.io.in[0].bits.data, _metaArb_io_in_0_bits_data_T
when resetting :
connect flushCounter, flushCounterNext
when flushDone :
connect resetting, UInt<1>(0h0)
node _clock_en_reg_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _clock_en_reg_T_1 = or(_clock_en_reg_T, UInt<1>(0h0))
node _clock_en_reg_T_2 = or(_clock_en_reg_T_1, io.cpu.keep_clock_enabled)
node _clock_en_reg_T_3 = or(_clock_en_reg_T_2, metaArb.io.out.valid)
node _clock_en_reg_T_4 = or(_clock_en_reg_T_3, s1_probe)
node _clock_en_reg_T_5 = or(_clock_en_reg_T_4, s2_probe)
node _clock_en_reg_T_6 = or(_clock_en_reg_T_5, s1_valid)
node _clock_en_reg_T_7 = or(_clock_en_reg_T_6, s2_valid)
node _clock_en_reg_T_8 = or(_clock_en_reg_T_7, io.tlb_port.req.valid)
node _clock_en_reg_T_9 = or(_clock_en_reg_T_8, s1_tlb_req_valid)
node _clock_en_reg_T_10 = or(_clock_en_reg_T_9, s2_tlb_req_valid)
node _clock_en_reg_T_11 = or(_clock_en_reg_T_10, pstore1_held)
node _clock_en_reg_T_12 = or(_clock_en_reg_T_11, pstore2_valid)
node _clock_en_reg_T_13 = neq(release_state, UInt<4>(0h0))
node _clock_en_reg_T_14 = or(_clock_en_reg_T_12, _clock_en_reg_T_13)
node _clock_en_reg_T_15 = or(_clock_en_reg_T_14, release_ack_wait)
node _clock_en_reg_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _clock_en_reg_T_17 = or(_clock_en_reg_T_15, _clock_en_reg_T_16)
node _clock_en_reg_T_18 = eq(tlb.io.req.ready, UInt<1>(0h0))
node _clock_en_reg_T_19 = or(_clock_en_reg_T_17, _clock_en_reg_T_18)
node _clock_en_reg_T_20 = or(_clock_en_reg_T_19, cached_grant_wait)
node _clock_en_reg_T_21 = orr(uncachedInFlight[0])
node _clock_en_reg_T_22 = or(_clock_en_reg_T_20, _clock_en_reg_T_21)
node _clock_en_reg_T_23 = gt(lrscCount, UInt<1>(0h0))
node _clock_en_reg_T_24 = or(_clock_en_reg_T_22, _clock_en_reg_T_23)
node _clock_en_reg_T_25 = gt(blockProbeAfterGrantCount, UInt<1>(0h0))
node _clock_en_reg_T_26 = or(_clock_en_reg_T_24, _clock_en_reg_T_25)
connect clock_en_reg, _clock_en_reg_T_26
node _io_cpu_perf_acquire_T = and(tl_out_a.ready, tl_out_a.valid)
node _io_cpu_perf_acquire_beats1_decode_T = dshl(UInt<12>(0hfff), tl_out_a.bits.size)
node _io_cpu_perf_acquire_beats1_decode_T_1 = bits(_io_cpu_perf_acquire_beats1_decode_T, 11, 0)
node _io_cpu_perf_acquire_beats1_decode_T_2 = not(_io_cpu_perf_acquire_beats1_decode_T_1)
node io_cpu_perf_acquire_beats1_decode = shr(_io_cpu_perf_acquire_beats1_decode_T_2, 3)
node _io_cpu_perf_acquire_beats1_opdata_T = bits(tl_out_a.bits.opcode, 2, 2)
node io_cpu_perf_acquire_beats1_opdata = eq(_io_cpu_perf_acquire_beats1_opdata_T, UInt<1>(0h0))
node io_cpu_perf_acquire_beats1 = mux(io_cpu_perf_acquire_beats1_opdata, io_cpu_perf_acquire_beats1_decode, UInt<1>(0h0))
regreset io_cpu_perf_acquire_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _io_cpu_perf_acquire_counter1_T = sub(io_cpu_perf_acquire_counter, UInt<1>(0h1))
node io_cpu_perf_acquire_counter1 = tail(_io_cpu_perf_acquire_counter1_T, 1)
node io_cpu_perf_acquire_first = eq(io_cpu_perf_acquire_counter, UInt<1>(0h0))
node _io_cpu_perf_acquire_last_T = eq(io_cpu_perf_acquire_counter, UInt<1>(0h1))
node _io_cpu_perf_acquire_last_T_1 = eq(io_cpu_perf_acquire_beats1, UInt<1>(0h0))
node io_cpu_perf_acquire_last = or(_io_cpu_perf_acquire_last_T, _io_cpu_perf_acquire_last_T_1)
node io_cpu_perf_acquire_done = and(io_cpu_perf_acquire_last, _io_cpu_perf_acquire_T)
node _io_cpu_perf_acquire_count_T = not(io_cpu_perf_acquire_counter1)
node io_cpu_perf_acquire_count = and(io_cpu_perf_acquire_beats1, _io_cpu_perf_acquire_count_T)
when _io_cpu_perf_acquire_T :
node _io_cpu_perf_acquire_counter_T = mux(io_cpu_perf_acquire_first, io_cpu_perf_acquire_beats1, io_cpu_perf_acquire_counter1)
connect io_cpu_perf_acquire_counter, _io_cpu_perf_acquire_counter_T
connect io.cpu.perf.acquire, io_cpu_perf_acquire_done
node _io_cpu_perf_release_T = and(nodeOut.c.ready, nodeOut.c.valid)
node _io_cpu_perf_release_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.c.bits.size)
node _io_cpu_perf_release_beats1_decode_T_1 = bits(_io_cpu_perf_release_beats1_decode_T, 11, 0)
node _io_cpu_perf_release_beats1_decode_T_2 = not(_io_cpu_perf_release_beats1_decode_T_1)
node io_cpu_perf_release_beats1_decode = shr(_io_cpu_perf_release_beats1_decode_T_2, 3)
node io_cpu_perf_release_beats1_opdata = bits(nodeOut.c.bits.opcode, 0, 0)
node io_cpu_perf_release_beats1 = mux(io_cpu_perf_release_beats1_opdata, io_cpu_perf_release_beats1_decode, UInt<1>(0h0))
regreset io_cpu_perf_release_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _io_cpu_perf_release_counter1_T = sub(io_cpu_perf_release_counter, UInt<1>(0h1))
node io_cpu_perf_release_counter1 = tail(_io_cpu_perf_release_counter1_T, 1)
node io_cpu_perf_release_first = eq(io_cpu_perf_release_counter, UInt<1>(0h0))
node _io_cpu_perf_release_last_T = eq(io_cpu_perf_release_counter, UInt<1>(0h1))
node _io_cpu_perf_release_last_T_1 = eq(io_cpu_perf_release_beats1, UInt<1>(0h0))
node io_cpu_perf_release_last = or(_io_cpu_perf_release_last_T, _io_cpu_perf_release_last_T_1)
node io_cpu_perf_release_done = and(io_cpu_perf_release_last, _io_cpu_perf_release_T)
node _io_cpu_perf_release_count_T = not(io_cpu_perf_release_counter1)
node io_cpu_perf_release_count = and(io_cpu_perf_release_beats1, _io_cpu_perf_release_count_T)
when _io_cpu_perf_release_T :
node _io_cpu_perf_release_counter_T = mux(io_cpu_perf_release_first, io_cpu_perf_release_beats1, io_cpu_perf_release_counter1)
connect io_cpu_perf_release_counter, _io_cpu_perf_release_counter_T
connect io.cpu.perf.release, io_cpu_perf_release_done
node _io_cpu_perf_grant_T = and(nodeOut.d.valid, d_last)
connect io.cpu.perf.grant, _io_cpu_perf_grant_T
node _io_cpu_perf_tlbMiss_T = and(io.ptw.req.ready, io.ptw.req.valid)
connect io.cpu.perf.tlbMiss, _io_cpu_perf_tlbMiss_T
node _io_cpu_perf_storeBufferEmptyAfterLoad_T = and(s1_valid, s1_write)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_1 = and(s2_valid, s2_write)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_2 = eq(s2_waw_hazard, UInt<1>(0h0))
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_3 = and(_io_cpu_perf_storeBufferEmptyAfterLoad_T_1, _io_cpu_perf_storeBufferEmptyAfterLoad_T_2)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_4 = or(_io_cpu_perf_storeBufferEmptyAfterLoad_T_3, pstore1_held)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_5 = or(_io_cpu_perf_storeBufferEmptyAfterLoad_T, _io_cpu_perf_storeBufferEmptyAfterLoad_T_4)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_6 = or(_io_cpu_perf_storeBufferEmptyAfterLoad_T_5, pstore2_valid)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_7 = eq(_io_cpu_perf_storeBufferEmptyAfterLoad_T_6, UInt<1>(0h0))
connect io.cpu.perf.storeBufferEmptyAfterLoad, _io_cpu_perf_storeBufferEmptyAfterLoad_T_7
node _io_cpu_perf_storeBufferEmptyAfterStore_T = and(s1_valid, s1_write)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_1 = and(s2_valid, s2_write)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_2 = and(_io_cpu_perf_storeBufferEmptyAfterStore_T_1, pstore1_rmw)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_3 = or(_io_cpu_perf_storeBufferEmptyAfterStore_T, _io_cpu_perf_storeBufferEmptyAfterStore_T_2)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_4 = and(s2_valid, s2_write)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_5 = eq(s2_waw_hazard, UInt<1>(0h0))
node _io_cpu_perf_storeBufferEmptyAfterStore_T_6 = and(_io_cpu_perf_storeBufferEmptyAfterStore_T_4, _io_cpu_perf_storeBufferEmptyAfterStore_T_5)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_7 = or(_io_cpu_perf_storeBufferEmptyAfterStore_T_6, pstore1_held)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_8 = and(_io_cpu_perf_storeBufferEmptyAfterStore_T_7, pstore2_valid)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_9 = or(_io_cpu_perf_storeBufferEmptyAfterStore_T_3, _io_cpu_perf_storeBufferEmptyAfterStore_T_8)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_10 = eq(_io_cpu_perf_storeBufferEmptyAfterStore_T_9, UInt<1>(0h0))
connect io.cpu.perf.storeBufferEmptyAfterStore, _io_cpu_perf_storeBufferEmptyAfterStore_T_10
node _io_cpu_perf_canAcceptStoreThenLoad_T = and(s2_valid, s2_write)
node _io_cpu_perf_canAcceptStoreThenLoad_T_1 = and(_io_cpu_perf_canAcceptStoreThenLoad_T, pstore1_rmw)
node _io_cpu_perf_canAcceptStoreThenLoad_T_2 = and(s1_valid, s1_write)
node _io_cpu_perf_canAcceptStoreThenLoad_T_3 = eq(s1_waw_hazard, UInt<1>(0h0))
node _io_cpu_perf_canAcceptStoreThenLoad_T_4 = and(_io_cpu_perf_canAcceptStoreThenLoad_T_2, _io_cpu_perf_canAcceptStoreThenLoad_T_3)
node _io_cpu_perf_canAcceptStoreThenLoad_T_5 = and(_io_cpu_perf_canAcceptStoreThenLoad_T_1, _io_cpu_perf_canAcceptStoreThenLoad_T_4)
node _io_cpu_perf_canAcceptStoreThenLoad_T_6 = and(pstore2_valid, pstore1_valid_likely)
node _io_cpu_perf_canAcceptStoreThenLoad_T_7 = and(s1_valid, s1_write)
node _io_cpu_perf_canAcceptStoreThenLoad_T_8 = and(_io_cpu_perf_canAcceptStoreThenLoad_T_6, _io_cpu_perf_canAcceptStoreThenLoad_T_7)
node _io_cpu_perf_canAcceptStoreThenLoad_T_9 = or(_io_cpu_perf_canAcceptStoreThenLoad_T_5, _io_cpu_perf_canAcceptStoreThenLoad_T_8)
node _io_cpu_perf_canAcceptStoreThenLoad_T_10 = eq(_io_cpu_perf_canAcceptStoreThenLoad_T_9, UInt<1>(0h0))
connect io.cpu.perf.canAcceptStoreThenLoad, _io_cpu_perf_canAcceptStoreThenLoad_T_10
node _io_cpu_perf_canAcceptStoreThenRMW_T = eq(pstore2_valid, UInt<1>(0h0))
node _io_cpu_perf_canAcceptStoreThenRMW_T_1 = and(io.cpu.perf.canAcceptStoreThenLoad, _io_cpu_perf_canAcceptStoreThenRMW_T)
connect io.cpu.perf.canAcceptStoreThenRMW, _io_cpu_perf_canAcceptStoreThenRMW_T_1
node _io_cpu_perf_canAcceptLoadThenLoad_T = and(s1_valid, s1_write)
node _io_cpu_perf_canAcceptLoadThenLoad_T_1 = eq(s1_req.cmd, UInt<1>(0h0))
node _io_cpu_perf_canAcceptLoadThenLoad_T_2 = eq(s1_req.cmd, UInt<5>(0h10))
node _io_cpu_perf_canAcceptLoadThenLoad_T_3 = eq(s1_req.cmd, UInt<3>(0h6))
node _io_cpu_perf_canAcceptLoadThenLoad_T_4 = eq(s1_req.cmd, UInt<3>(0h7))
node _io_cpu_perf_canAcceptLoadThenLoad_T_5 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_1, _io_cpu_perf_canAcceptLoadThenLoad_T_2)
node _io_cpu_perf_canAcceptLoadThenLoad_T_6 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_5, _io_cpu_perf_canAcceptLoadThenLoad_T_3)
node _io_cpu_perf_canAcceptLoadThenLoad_T_7 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_6, _io_cpu_perf_canAcceptLoadThenLoad_T_4)
node _io_cpu_perf_canAcceptLoadThenLoad_T_8 = eq(s1_req.cmd, UInt<3>(0h4))
node _io_cpu_perf_canAcceptLoadThenLoad_T_9 = eq(s1_req.cmd, UInt<4>(0h9))
node _io_cpu_perf_canAcceptLoadThenLoad_T_10 = eq(s1_req.cmd, UInt<4>(0ha))
node _io_cpu_perf_canAcceptLoadThenLoad_T_11 = eq(s1_req.cmd, UInt<4>(0hb))
node _io_cpu_perf_canAcceptLoadThenLoad_T_12 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_8, _io_cpu_perf_canAcceptLoadThenLoad_T_9)
node _io_cpu_perf_canAcceptLoadThenLoad_T_13 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_12, _io_cpu_perf_canAcceptLoadThenLoad_T_10)
node _io_cpu_perf_canAcceptLoadThenLoad_T_14 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_13, _io_cpu_perf_canAcceptLoadThenLoad_T_11)
node _io_cpu_perf_canAcceptLoadThenLoad_T_15 = eq(s1_req.cmd, UInt<4>(0h8))
node _io_cpu_perf_canAcceptLoadThenLoad_T_16 = eq(s1_req.cmd, UInt<4>(0hc))
node _io_cpu_perf_canAcceptLoadThenLoad_T_17 = eq(s1_req.cmd, UInt<4>(0hd))
node _io_cpu_perf_canAcceptLoadThenLoad_T_18 = eq(s1_req.cmd, UInt<4>(0he))
node _io_cpu_perf_canAcceptLoadThenLoad_T_19 = eq(s1_req.cmd, UInt<4>(0hf))
node _io_cpu_perf_canAcceptLoadThenLoad_T_20 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_15, _io_cpu_perf_canAcceptLoadThenLoad_T_16)
node _io_cpu_perf_canAcceptLoadThenLoad_T_21 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_20, _io_cpu_perf_canAcceptLoadThenLoad_T_17)
node _io_cpu_perf_canAcceptLoadThenLoad_T_22 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_21, _io_cpu_perf_canAcceptLoadThenLoad_T_18)
node _io_cpu_perf_canAcceptLoadThenLoad_T_23 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_22, _io_cpu_perf_canAcceptLoadThenLoad_T_19)
node _io_cpu_perf_canAcceptLoadThenLoad_T_24 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_14, _io_cpu_perf_canAcceptLoadThenLoad_T_23)
node _io_cpu_perf_canAcceptLoadThenLoad_T_25 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_7, _io_cpu_perf_canAcceptLoadThenLoad_T_24)
node _io_cpu_perf_canAcceptLoadThenLoad_T_26 = eq(s1_req.cmd, UInt<1>(0h1))
node _io_cpu_perf_canAcceptLoadThenLoad_T_27 = eq(s1_req.cmd, UInt<5>(0h11))
node _io_cpu_perf_canAcceptLoadThenLoad_T_28 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_26, _io_cpu_perf_canAcceptLoadThenLoad_T_27)
node _io_cpu_perf_canAcceptLoadThenLoad_T_29 = eq(s1_req.cmd, UInt<3>(0h7))
node _io_cpu_perf_canAcceptLoadThenLoad_T_30 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_28, _io_cpu_perf_canAcceptLoadThenLoad_T_29)
node _io_cpu_perf_canAcceptLoadThenLoad_T_31 = eq(s1_req.cmd, UInt<3>(0h4))
node _io_cpu_perf_canAcceptLoadThenLoad_T_32 = eq(s1_req.cmd, UInt<4>(0h9))
node _io_cpu_perf_canAcceptLoadThenLoad_T_33 = eq(s1_req.cmd, UInt<4>(0ha))
node _io_cpu_perf_canAcceptLoadThenLoad_T_34 = eq(s1_req.cmd, UInt<4>(0hb))
node _io_cpu_perf_canAcceptLoadThenLoad_T_35 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_31, _io_cpu_perf_canAcceptLoadThenLoad_T_32)
node _io_cpu_perf_canAcceptLoadThenLoad_T_36 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_35, _io_cpu_perf_canAcceptLoadThenLoad_T_33)
node _io_cpu_perf_canAcceptLoadThenLoad_T_37 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_36, _io_cpu_perf_canAcceptLoadThenLoad_T_34)
node _io_cpu_perf_canAcceptLoadThenLoad_T_38 = eq(s1_req.cmd, UInt<4>(0h8))
node _io_cpu_perf_canAcceptLoadThenLoad_T_39 = eq(s1_req.cmd, UInt<4>(0hc))
node _io_cpu_perf_canAcceptLoadThenLoad_T_40 = eq(s1_req.cmd, UInt<4>(0hd))
node _io_cpu_perf_canAcceptLoadThenLoad_T_41 = eq(s1_req.cmd, UInt<4>(0he))
node _io_cpu_perf_canAcceptLoadThenLoad_T_42 = eq(s1_req.cmd, UInt<4>(0hf))
node _io_cpu_perf_canAcceptLoadThenLoad_T_43 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_38, _io_cpu_perf_canAcceptLoadThenLoad_T_39)
node _io_cpu_perf_canAcceptLoadThenLoad_T_44 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_43, _io_cpu_perf_canAcceptLoadThenLoad_T_40)
node _io_cpu_perf_canAcceptLoadThenLoad_T_45 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_44, _io_cpu_perf_canAcceptLoadThenLoad_T_41)
node _io_cpu_perf_canAcceptLoadThenLoad_T_46 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_45, _io_cpu_perf_canAcceptLoadThenLoad_T_42)
node _io_cpu_perf_canAcceptLoadThenLoad_T_47 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_37, _io_cpu_perf_canAcceptLoadThenLoad_T_46)
node _io_cpu_perf_canAcceptLoadThenLoad_T_48 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_30, _io_cpu_perf_canAcceptLoadThenLoad_T_47)
node _io_cpu_perf_canAcceptLoadThenLoad_T_49 = eq(s1_req.cmd, UInt<5>(0h11))
node _io_cpu_perf_canAcceptLoadThenLoad_T_50 = lt(s1_req.size, UInt<1>(0h0))
node _io_cpu_perf_canAcceptLoadThenLoad_T_51 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_49, _io_cpu_perf_canAcceptLoadThenLoad_T_50)
node _io_cpu_perf_canAcceptLoadThenLoad_T_52 = and(_io_cpu_perf_canAcceptLoadThenLoad_T_48, _io_cpu_perf_canAcceptLoadThenLoad_T_51)
node _io_cpu_perf_canAcceptLoadThenLoad_T_53 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_25, _io_cpu_perf_canAcceptLoadThenLoad_T_52)
node _io_cpu_perf_canAcceptLoadThenLoad_T_54 = and(_io_cpu_perf_canAcceptLoadThenLoad_T, _io_cpu_perf_canAcceptLoadThenLoad_T_53)
node _io_cpu_perf_canAcceptLoadThenLoad_T_55 = and(s2_valid, s2_write)
node _io_cpu_perf_canAcceptLoadThenLoad_T_56 = eq(s2_waw_hazard, UInt<1>(0h0))
node _io_cpu_perf_canAcceptLoadThenLoad_T_57 = and(_io_cpu_perf_canAcceptLoadThenLoad_T_55, _io_cpu_perf_canAcceptLoadThenLoad_T_56)
node _io_cpu_perf_canAcceptLoadThenLoad_T_58 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_57, pstore1_held)
node _io_cpu_perf_canAcceptLoadThenLoad_T_59 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_58, pstore2_valid)
node _io_cpu_perf_canAcceptLoadThenLoad_T_60 = and(_io_cpu_perf_canAcceptLoadThenLoad_T_54, _io_cpu_perf_canAcceptLoadThenLoad_T_59)
node _io_cpu_perf_canAcceptLoadThenLoad_T_61 = eq(_io_cpu_perf_canAcceptLoadThenLoad_T_60, UInt<1>(0h0))
connect io.cpu.perf.canAcceptLoadThenLoad, _io_cpu_perf_canAcceptLoadThenLoad_T_61
regreset io_cpu_perf_blocked_near_end_of_refill_refill_count : UInt<3>, clock, reset, UInt<3>(0h0)
node _io_cpu_perf_blocked_near_end_of_refill_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _io_cpu_perf_blocked_near_end_of_refill_T_1 = and(_io_cpu_perf_blocked_near_end_of_refill_T, grantIsRefill)
when _io_cpu_perf_blocked_near_end_of_refill_T_1 :
node _io_cpu_perf_blocked_near_end_of_refill_refill_count_T = add(io_cpu_perf_blocked_near_end_of_refill_refill_count, UInt<1>(0h1))
node _io_cpu_perf_blocked_near_end_of_refill_refill_count_T_1 = tail(_io_cpu_perf_blocked_near_end_of_refill_refill_count_T, 1)
connect io_cpu_perf_blocked_near_end_of_refill_refill_count, _io_cpu_perf_blocked_near_end_of_refill_refill_count_T_1
node io_cpu_perf_blocked_near_end_of_refill = geq(io_cpu_perf_blocked_near_end_of_refill_refill_count, UInt<3>(0h6))
node _io_cpu_perf_blocked_T = eq(io_cpu_perf_blocked_near_end_of_refill, UInt<1>(0h0))
node _io_cpu_perf_blocked_T_1 = and(cached_grant_wait, _io_cpu_perf_blocked_T)
connect io.cpu.perf.blocked, _io_cpu_perf_blocked_T_1
node _T_132 = and(nodeOut.c.ready, nodeOut.c.valid)
node _T_133 = and(_T_132, inWriteback)
node _T_134 = and(_T_133, s2_data_error)
reg data_error : UInt<1>, clock
connect data_error, _T_134
reg data_error_uncorrectable : UInt<1>, clock
connect data_error_uncorrectable, s2_data_error_uncorrectable
node _error_addr_T = bits(metaArb.io.in[1].bits.addr, 7, 6)
node _error_addr_T_1 = cat(s2_first_meta_corrected.tag, _error_addr_T)
node _error_addr_T_2 = shr(probe_bits.address, 6)
node _error_addr_T_3 = mux(metaArb.io.in[1].valid, _error_addr_T_1, _error_addr_T_2)
node error_addr = shl(_error_addr_T_3, 6)
node _io_errors_bus_valid_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _io_errors_bus_valid_T_1 = or(nodeOut.d.bits.denied, nodeOut.d.bits.corrupt)
node _io_errors_bus_valid_T_2 = and(_io_errors_bus_valid_T, _io_errors_bus_valid_T_1)
connect io.errors.bus.valid, _io_errors_bus_valid_T_2
node _io_errors_bus_bits_T = shr(s2_req.addr, 6)
node _io_errors_bus_bits_T_1 = shl(_io_errors_bus_bits_T, 6)
node _io_errors_bus_bits_T_2 = mux(grantIsCached, _io_errors_bus_bits_T_1, UInt<1>(0h0))
connect io.errors.bus.bits, _io_errors_bus_bits_T_2
node _T_135 = and(io.errors.bus.valid, grantIsCached)
node _T_136 = eq(grantIsCached, UInt<1>(0h0))
node _T_137 = and(io.errors.bus.valid, _T_136)
node _T_138 = eq(s2_valid_data_error, UInt<1>(0h0))
node _T_139 = eq(s2_data_error_uncorrectable, UInt<1>(0h0))
node _T_140 = and(s2_valid_data_error, _T_139)
node _T_141 = and(s2_valid_data_error, s2_data_error_uncorrectable)
node _T_142 = eq(s2_victim_dirty, UInt<1>(0h0))
node _T_143 = eq(s2_meta_error, UInt<1>(0h0))
node _T_144 = eq(s2_meta_error_uncorrectable, UInt<1>(0h0))
node _T_145 = and(s2_meta_error, _T_144)
node _T_146 = and(s2_meta_error, s2_meta_error_uncorrectable)
node _T_147 = and(UInt<1>(0h1), _T_143)
node _T_148 = and(UInt<1>(0h1), _T_145)
node _T_149 = and(UInt<1>(0h1), _T_146)
node _T_150 = and(_T_142, _T_147)
node _T_151 = and(_T_142, _T_148)
node _T_152 = and(_T_142, _T_149)
node _T_153 = and(UInt<1>(0h1), _T_143)
node _T_154 = and(UInt<1>(0h1), _T_145)
node _T_155 = and(UInt<1>(0h1), _T_146)
node _T_156 = and(s2_victim_dirty, _T_153)
node _T_157 = and(s2_victim_dirty, _T_154)
node _T_158 = and(s2_victim_dirty, _T_155)
node _T_159 = and(_T_138, _T_150)
node _T_160 = and(_T_138, _T_151)
node _T_161 = and(_T_138, _T_152)
node _T_162 = and(_T_138, _T_156)
node _T_163 = and(_T_138, _T_157)
node _T_164 = and(_T_138, _T_158)
node _T_165 = and(UInt<1>(0h1), _T_143)
node _T_166 = and(UInt<1>(0h1), _T_145)
node _T_167 = and(UInt<1>(0h1), _T_146)
node _T_168 = and(_T_142, _T_165)
node _T_169 = and(_T_142, _T_166)
node _T_170 = and(_T_142, _T_167)
node _T_171 = and(UInt<1>(0h1), _T_143)
node _T_172 = and(UInt<1>(0h1), _T_145)
node _T_173 = and(UInt<1>(0h1), _T_146)
node _T_174 = and(s2_victim_dirty, _T_171)
node _T_175 = and(s2_victim_dirty, _T_172)
node _T_176 = and(s2_victim_dirty, _T_173)
node _T_177 = and(_T_140, _T_168)
node _T_178 = and(_T_140, _T_169)
node _T_179 = and(_T_140, _T_170)
node _T_180 = and(_T_140, _T_174)
node _T_181 = and(_T_140, _T_175)
node _T_182 = and(_T_140, _T_176)
node _T_183 = and(UInt<1>(0h1), _T_143)
node _T_184 = and(UInt<1>(0h1), _T_145)
node _T_185 = and(UInt<1>(0h1), _T_146)
node _T_186 = and(_T_142, _T_183)
node _T_187 = and(_T_142, _T_184)
node _T_188 = and(_T_142, _T_185)
node _T_189 = and(UInt<1>(0h1), _T_143)
node _T_190 = and(UInt<1>(0h1), _T_145)
node _T_191 = and(UInt<1>(0h1), _T_146)
node _T_192 = and(s2_victim_dirty, _T_189)
node _T_193 = and(s2_victim_dirty, _T_190)
node _T_194 = and(s2_victim_dirty, _T_191)
node _T_195 = and(_T_141, _T_186)
node _T_196 = and(_T_141, _T_187)
node _T_197 = and(_T_141, _T_188)
node _T_198 = and(_T_141, _T_192)
node _T_199 = and(_T_141, _T_193)
node _T_200 = and(_T_141, _T_194) | module MiniDCache_4( // @[DCache.scala:101:7]
input clock, // @[DCache.scala:101:7]
input reset, // @[DCache.scala:101:7]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output io_cpu_req_ready, // @[HellaCache.scala:243:14]
input io_cpu_req_valid, // @[HellaCache.scala:243:14]
input [39:0] io_cpu_req_bits_addr, // @[HellaCache.scala:243:14]
input [7:0] io_cpu_req_bits_tag, // @[HellaCache.scala:243:14]
input [1:0] io_cpu_req_bits_size, // @[HellaCache.scala:243:14]
input [1:0] io_cpu_req_bits_dprv, // @[HellaCache.scala:243:14]
input io_cpu_req_bits_dv, // @[HellaCache.scala:243:14]
input io_cpu_req_bits_phys, // @[HellaCache.scala:243:14]
input io_cpu_s1_kill, // @[HellaCache.scala:243:14]
input [63:0] io_cpu_s1_data_data, // @[HellaCache.scala:243:14]
input [7:0] io_cpu_s1_data_mask, // @[HellaCache.scala:243:14]
output io_cpu_s2_nack, // @[HellaCache.scala:243:14]
output io_cpu_s2_nack_cause_raw, // @[HellaCache.scala:243:14]
output io_cpu_s2_uncached, // @[HellaCache.scala:243:14]
output [31:0] io_cpu_s2_paddr, // @[HellaCache.scala:243:14]
output io_cpu_resp_valid, // @[HellaCache.scala:243:14]
output [39:0] io_cpu_resp_bits_addr, // @[HellaCache.scala:243:14]
output [7:0] io_cpu_resp_bits_tag, // @[HellaCache.scala:243:14]
output [4:0] io_cpu_resp_bits_cmd, // @[HellaCache.scala:243:14]
output [1:0] io_cpu_resp_bits_size, // @[HellaCache.scala:243:14]
output io_cpu_resp_bits_signed, // @[HellaCache.scala:243:14]
output [1:0] io_cpu_resp_bits_dprv, // @[HellaCache.scala:243:14]
output io_cpu_resp_bits_dv, // @[HellaCache.scala:243:14]
output [63:0] io_cpu_resp_bits_data, // @[HellaCache.scala:243:14]
output [7:0] io_cpu_resp_bits_mask, // @[HellaCache.scala:243:14]
output io_cpu_resp_bits_replay, // @[HellaCache.scala:243:14]
output io_cpu_resp_bits_has_data, // @[HellaCache.scala:243:14]
output [63:0] io_cpu_resp_bits_data_word_bypass, // @[HellaCache.scala:243:14]
output [63:0] io_cpu_resp_bits_data_raw, // @[HellaCache.scala:243:14]
output [63:0] io_cpu_resp_bits_store_data, // @[HellaCache.scala:243:14]
output io_cpu_replay_next, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_ma_ld, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_ma_st, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_pf_ld, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_pf_st, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_ae_ld, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_ae_st, // @[HellaCache.scala:243:14]
output [39:0] io_cpu_s2_gpa, // @[HellaCache.scala:243:14]
output io_cpu_ordered, // @[HellaCache.scala:243:14]
output io_cpu_store_pending, // @[HellaCache.scala:243:14]
output io_cpu_perf_acquire, // @[HellaCache.scala:243:14]
output io_cpu_perf_release, // @[HellaCache.scala:243:14]
output io_cpu_perf_grant, // @[HellaCache.scala:243:14]
output io_cpu_perf_tlbMiss, // @[HellaCache.scala:243:14]
output io_cpu_perf_blocked, // @[HellaCache.scala:243:14]
output io_cpu_perf_canAcceptStoreThenLoad, // @[HellaCache.scala:243:14]
output io_cpu_perf_canAcceptStoreThenRMW, // @[HellaCache.scala:243:14]
output io_cpu_perf_canAcceptLoadThenLoad, // @[HellaCache.scala:243:14]
output io_cpu_perf_storeBufferEmptyAfterLoad, // @[HellaCache.scala:243:14]
output io_cpu_perf_storeBufferEmptyAfterStore, // @[HellaCache.scala:243:14]
input io_ptw_req_ready, // @[HellaCache.scala:243:14]
output io_ptw_req_valid, // @[HellaCache.scala:243:14]
output [26:0] io_ptw_req_bits_bits_addr, // @[HellaCache.scala:243:14]
output io_ptw_req_bits_bits_need_gpa, // @[HellaCache.scala:243:14]
input io_ptw_resp_valid, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_ae_ptw, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_ae_final, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pf, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_gf, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_hr, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_hw, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_hx, // @[HellaCache.scala:243:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[HellaCache.scala:243:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_d, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_a, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_g, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_u, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_x, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_w, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_r, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_v, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_resp_bits_level, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_homogeneous, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_gpa_valid, // @[HellaCache.scala:243:14]
input [38:0] io_ptw_resp_bits_gpa_bits, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_gpa_is_pte, // @[HellaCache.scala:243:14]
input [3:0] io_ptw_ptbr_mode, // @[HellaCache.scala:243:14]
input [15:0] io_ptw_ptbr_asid, // @[HellaCache.scala:243:14]
input [43:0] io_ptw_ptbr_ppn, // @[HellaCache.scala:243:14]
input io_ptw_status_debug, // @[HellaCache.scala:243:14]
input io_ptw_status_cease, // @[HellaCache.scala:243:14]
input io_ptw_status_wfi, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_status_isa, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_status_dprv, // @[HellaCache.scala:243:14]
input io_ptw_status_dv, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_status_prv, // @[HellaCache.scala:243:14]
input io_ptw_status_v, // @[HellaCache.scala:243:14]
input io_ptw_status_sd, // @[HellaCache.scala:243:14]
input [22:0] io_ptw_status_zero2, // @[HellaCache.scala:243:14]
input io_ptw_status_mpv, // @[HellaCache.scala:243:14]
input io_ptw_status_gva, // @[HellaCache.scala:243:14]
input io_ptw_status_mbe, // @[HellaCache.scala:243:14]
input io_ptw_status_sbe, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_status_sxl, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_status_uxl, // @[HellaCache.scala:243:14]
input io_ptw_status_sd_rv32, // @[HellaCache.scala:243:14]
input [7:0] io_ptw_status_zero1, // @[HellaCache.scala:243:14]
input io_ptw_status_tsr, // @[HellaCache.scala:243:14]
input io_ptw_status_tw, // @[HellaCache.scala:243:14]
input io_ptw_status_tvm, // @[HellaCache.scala:243:14]
input io_ptw_status_mxr, // @[HellaCache.scala:243:14]
input io_ptw_status_sum, // @[HellaCache.scala:243:14]
input io_ptw_status_mprv, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_status_xs, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_status_fs, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_status_mpp, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_status_vs, // @[HellaCache.scala:243:14]
input io_ptw_status_spp, // @[HellaCache.scala:243:14]
input io_ptw_status_mpie, // @[HellaCache.scala:243:14]
input io_ptw_status_ube, // @[HellaCache.scala:243:14]
input io_ptw_status_spie, // @[HellaCache.scala:243:14]
input io_ptw_status_upie, // @[HellaCache.scala:243:14]
input io_ptw_status_mie, // @[HellaCache.scala:243:14]
input io_ptw_status_hie, // @[HellaCache.scala:243:14]
input io_ptw_status_sie, // @[HellaCache.scala:243:14]
input io_ptw_status_uie // @[HellaCache.scala:243:14]
);
wire [23:0] s2_meta_corrected_3_tag; // @[DCache.scala:361:99]
wire [1:0] s2_meta_corrected_3_coh_state; // @[DCache.scala:361:99]
wire [63:0] s1_all_data_ways_3; // @[DCache.scala:325:33]
wire [63:0] s1_all_data_ways_2; // @[DCache.scala:325:33]
wire [63:0] s1_all_data_ways_1; // @[DCache.scala:325:33]
wire [63:0] s1_all_data_ways_0; // @[DCache.scala:325:33]
wire rerocc_tile_dcache_tag_array_MPORT_en; // @[DCache.scala:310:27]
wire s0_req_phys; // @[DCache.scala:192:24]
wire [39:0] s0_req_addr; // @[DCache.scala:192:24]
wire tl_out_a_valid; // @[DCache.scala:159:22]
wire [63:0] tl_out_a_bits_data; // @[DCache.scala:159:22]
wire [7:0] tl_out_a_bits_mask; // @[DCache.scala:159:22]
wire [31:0] tl_out_a_bits_address; // @[DCache.scala:159:22]
wire tl_out_a_bits_source; // @[DCache.scala:159:22]
wire [3:0] tl_out_a_bits_size; // @[DCache.scala:159:22]
wire [2:0] tl_out_a_bits_param; // @[DCache.scala:159:22]
wire [2:0] tl_out_a_bits_opcode; // @[DCache.scala:159:22]
wire [1:0] metaArb_io_out_bits_idx; // @[DCache.scala:135:28]
wire metaArb_io_in_0_valid; // @[DCache.scala:135:28]
wire [4:0] pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_req_bits_size; // @[DCache.scala:120:32]
wire [103:0] _rerocc_tile_dcache_tag_array_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire _lfsr_prng_io_out_0; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_1; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_2; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_3; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_4; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_5; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_6; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_7; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_8; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_9; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_10; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_11; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_12; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_13; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_14; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_15; // @[PRNG.scala:91:22]
wire [19:0] _pma_checker_entries_barrier_12_io_y_ppn; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_hr; // @[package.scala:267:25]
wire [19:0] _pma_checker_entries_barrier_11_io_y_ppn; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_c; // @[package.scala:267:25]
wire [19:0] _pma_checker_entries_barrier_10_io_y_ppn; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_c; // @[package.scala:267:25]
wire [19:0] _pma_checker_entries_barrier_9_io_y_ppn; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_c; // @[package.scala:267:25]
wire [19:0] _pma_checker_entries_barrier_8_io_y_ppn; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_c; // @[package.scala:267:25]
wire _pma_checker_pma_io_resp_r; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_w; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_pp; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_al; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_aa; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_x; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_eff; // @[TLB.scala:422:19]
wire [19:0] _pma_checker_mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25]
wire _tlb_io_req_ready; // @[DCache.scala:119:19]
wire _tlb_io_resp_miss; // @[DCache.scala:119:19]
wire [31:0] _tlb_io_resp_paddr; // @[DCache.scala:119:19]
wire [39:0] _tlb_io_resp_gpa; // @[DCache.scala:119:19]
wire _tlb_io_resp_pf_ld; // @[DCache.scala:119:19]
wire _tlb_io_resp_pf_st; // @[DCache.scala:119:19]
wire _tlb_io_resp_pf_inst; // @[DCache.scala:119:19]
wire _tlb_io_resp_ae_ld; // @[DCache.scala:119:19]
wire _tlb_io_resp_ae_st; // @[DCache.scala:119:19]
wire _tlb_io_resp_ae_inst; // @[DCache.scala:119:19]
wire _tlb_io_resp_ma_ld; // @[DCache.scala:119:19]
wire _tlb_io_resp_ma_st; // @[DCache.scala:119:19]
wire _tlb_io_resp_cacheable; // @[DCache.scala:119:19]
wire _tlb_io_resp_must_alloc; // @[DCache.scala:119:19]
wire _tlb_io_resp_prefetchable; // @[DCache.scala:119:19]
wire [1:0] _tlb_io_resp_size; // @[DCache.scala:119:19]
wire [4:0] _tlb_io_resp_cmd; // @[DCache.scala:119:19]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[DCache.scala:101:7]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[DCache.scala:101:7]
wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[DCache.scala:101:7]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[DCache.scala:101:7]
wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[DCache.scala:101:7]
wire auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[DCache.scala:101:7]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[DCache.scala:101:7]
wire [7:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[DCache.scala:101:7]
wire [63:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[DCache.scala:101:7]
wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[DCache.scala:101:7]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[DCache.scala:101:7]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[DCache.scala:101:7]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[DCache.scala:101:7]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[DCache.scala:101:7]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[DCache.scala:101:7]
wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[DCache.scala:101:7]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[DCache.scala:101:7]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[DCache.scala:101:7]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[DCache.scala:101:7]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[DCache.scala:101:7]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[DCache.scala:101:7]
wire io_cpu_req_valid_0 = io_cpu_req_valid; // @[DCache.scala:101:7]
wire [39:0] io_cpu_req_bits_addr_0 = io_cpu_req_bits_addr; // @[DCache.scala:101:7]
wire [7:0] io_cpu_req_bits_tag_0 = io_cpu_req_bits_tag; // @[DCache.scala:101:7]
wire [1:0] io_cpu_req_bits_size_0 = io_cpu_req_bits_size; // @[DCache.scala:101:7]
wire [1:0] io_cpu_req_bits_dprv_0 = io_cpu_req_bits_dprv; // @[DCache.scala:101:7]
wire io_cpu_req_bits_dv_0 = io_cpu_req_bits_dv; // @[DCache.scala:101:7]
wire io_cpu_req_bits_phys_0 = io_cpu_req_bits_phys; // @[DCache.scala:101:7]
wire io_cpu_s1_kill_0 = io_cpu_s1_kill; // @[DCache.scala:101:7]
wire [63:0] io_cpu_s1_data_data_0 = io_cpu_s1_data_data; // @[DCache.scala:101:7]
wire [7:0] io_cpu_s1_data_mask_0 = io_cpu_s1_data_mask; // @[DCache.scala:101:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[DCache.scala:101:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[DCache.scala:101:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[DCache.scala:101:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[DCache.scala:101:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[DCache.scala:101:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[DCache.scala:101:7]
wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[DCache.scala:101:7]
wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[DCache.scala:101:7]
wire [15:0] io_ptw_ptbr_asid_0 = io_ptw_ptbr_asid; // @[DCache.scala:101:7]
wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[DCache.scala:101:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[DCache.scala:101:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[DCache.scala:101:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[DCache.scala:101:7]
wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[DCache.scala:101:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[DCache.scala:101:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[DCache.scala:101:7]
wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[DCache.scala:101:7]
wire [22:0] io_ptw_status_zero2_0 = io_ptw_status_zero2; // @[DCache.scala:101:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[DCache.scala:101:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[DCache.scala:101:7]
wire io_ptw_status_mbe_0 = io_ptw_status_mbe; // @[DCache.scala:101:7]
wire io_ptw_status_sbe_0 = io_ptw_status_sbe; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_sxl_0 = io_ptw_status_sxl; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_uxl_0 = io_ptw_status_uxl; // @[DCache.scala:101:7]
wire io_ptw_status_sd_rv32_0 = io_ptw_status_sd_rv32; // @[DCache.scala:101:7]
wire [7:0] io_ptw_status_zero1_0 = io_ptw_status_zero1; // @[DCache.scala:101:7]
wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[DCache.scala:101:7]
wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[DCache.scala:101:7]
wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[DCache.scala:101:7]
wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[DCache.scala:101:7]
wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[DCache.scala:101:7]
wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_xs_0 = io_ptw_status_xs; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_vs_0 = io_ptw_status_vs; // @[DCache.scala:101:7]
wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[DCache.scala:101:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[DCache.scala:101:7]
wire io_ptw_status_ube_0 = io_ptw_status_ube; // @[DCache.scala:101:7]
wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[DCache.scala:101:7]
wire io_ptw_status_upie_0 = io_ptw_status_upie; // @[DCache.scala:101:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[DCache.scala:101:7]
wire io_ptw_status_hie_0 = io_ptw_status_hie; // @[DCache.scala:101:7]
wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[DCache.scala:101:7]
wire io_ptw_status_uie_0 = io_ptw_status_uie; // @[DCache.scala:101:7]
wire _dataArb_io_in_3_valid_T_55 = reset; // @[DCache.scala:1186:11]
wire _pstore_drain_opportunistic_T_55 = reset; // @[DCache.scala:1186:11]
wire [4:0] io_cpu_req_bits_cmd = 5'h0; // @[DCache.scala:101:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:101:7]
wire [4:0] io_tlb_port_req_bits_cmd = 5'h0; // @[DCache.scala:101:7]
wire [4:0] pma_checker_io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:120:32]
wire [4:0] s0_req_cmd = 5'h0; // @[DCache.scala:192:24]
wire [4:0] s0_tlb_req_cmd = 5'h0; // @[DCache.scala:199:28]
wire [4:0] _io_cpu_s2_xcpt_WIRE_cmd = 5'h0; // @[DCache.scala:933:74]
wire auto_out_a_bits_corrupt = 1'h0; // @[DCache.scala:101:7]
wire auto_out_c_bits_corrupt = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_req_bits_signed = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_req_bits_no_resp = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_req_bits_no_alloc = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_req_bits_no_xcpt = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_s2_kill = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_gf_ld = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_gf_st = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_s2_gpa_is_pte = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_keep_clock_enabled = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_spvp = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_spv = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_gva = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_debug = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_cease = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_wfi = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_dv = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_v = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_sd = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mpv = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_gva = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mbe = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_sbe = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_tsr = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_tw = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_tvm = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mxr = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_sum = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mprv = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_spp = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mpie = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_ube = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_spie = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_upie = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mie = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_hie = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_sie = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_uie = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_req_valid = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_req_bits_passthrough = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_req_bits_v = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_gpa_is_pte = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_gf_ld = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_gf_st = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_gf_inst = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ma_inst = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s2_kill = 1'h0; // @[DCache.scala:101:7]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire pma_checker_io_req_valid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_miss = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_gpa_is_pte = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_gf_ld = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_gf_st = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_gf_inst = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ma_inst = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_valid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_bits_rs1 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_bits_rs2 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_bits_asid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_bits_hv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_bits_hg = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_ready = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_valid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_bits_bits_need_gpa = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_valid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_ae_ptw = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_ae_final = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pf = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_gf = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_hr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_hw = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_hx = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_d = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_a = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_g = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_u = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_v = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_homogeneous = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_gpa_valid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_gpa_is_pte = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_debug = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_cease = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_wfi = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_dv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_v = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_sd = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mpv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_gva = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mbe = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_sbe = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_tsr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_tw = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_tvm = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mxr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_sum = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mprv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_spp = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mpie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_ube = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_spie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_upie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_hie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_sie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_uie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_spvp = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_spv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_gva = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_debug = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_cease = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_wfi = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_dv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_v = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_sd = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mpv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_gva = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mbe = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_sbe = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_tsr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_tw = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_tvm = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mxr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_sum = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mprv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_spp = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mpie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_ube = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_spie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_upie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_hie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_sie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_uie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_kill = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_priv_v = 1'h0; // @[TLB.scala:369:34]
wire pma_checker__stage1_en_T = 1'h0; // @[TLB.scala:374:41]
wire pma_checker_stage1_en = 1'h0; // @[TLB.scala:374:29]
wire pma_checker__vstage1_en_T = 1'h0; // @[TLB.scala:376:38]
wire pma_checker__vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68]
wire pma_checker_vstage1_en = 1'h0; // @[TLB.scala:376:48]
wire pma_checker__stage2_en_T = 1'h0; // @[TLB.scala:378:38]
wire pma_checker__stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68]
wire pma_checker_stage2_en = 1'h0; // @[TLB.scala:378:48]
wire pma_checker__vm_enabled_T = 1'h0; // @[TLB.scala:399:31]
wire pma_checker__vm_enabled_T_1 = 1'h0; // @[TLB.scala:399:45]
wire pma_checker__vm_enabled_T_2 = 1'h0; // @[TLB.scala:399:64]
wire pma_checker_vm_enabled = 1'h0; // @[TLB.scala:399:61]
wire pma_checker__vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52]
wire pma_checker__vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37]
wire pma_checker__vsatp_mode_mismatch_T_2 = 1'h0; // @[TLB.scala:403:81]
wire pma_checker_vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78]
wire pma_checker_do_refill = 1'h0; // @[TLB.scala:408:29]
wire pma_checker__invalidate_refill_T = 1'h0; // @[package.scala:16:47]
wire pma_checker__invalidate_refill_T_1 = 1'h0; // @[package.scala:16:47]
wire pma_checker__invalidate_refill_T_2 = 1'h0; // @[package.scala:81:59]
wire pma_checker_invalidate_refill = 1'h0; // @[TLB.scala:410:88]
wire pma_checker__mpu_ppn_T = 1'h0; // @[TLB.scala:413:32]
wire pma_checker__sector_hits_T = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_1 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_2 = 1'h0; // @[package.scala:81:59]
wire pma_checker_sector_hits_0 = 1'h0; // @[TLB.scala:172:55]
wire pma_checker__sector_hits_T_8 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_9 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_10 = 1'h0; // @[package.scala:81:59]
wire pma_checker_sector_hits_1 = 1'h0; // @[TLB.scala:172:55]
wire pma_checker__sector_hits_T_16 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_17 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_18 = 1'h0; // @[package.scala:81:59]
wire pma_checker_sector_hits_2 = 1'h0; // @[TLB.scala:172:55]
wire pma_checker__sector_hits_T_24 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_25 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_26 = 1'h0; // @[package.scala:81:59]
wire pma_checker_sector_hits_3 = 1'h0; // @[TLB.scala:172:55]
wire pma_checker__sector_hits_T_32 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_33 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_34 = 1'h0; // @[package.scala:81:59]
wire pma_checker_sector_hits_4 = 1'h0; // @[TLB.scala:172:55]
wire pma_checker__sector_hits_T_40 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_41 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_42 = 1'h0; // @[package.scala:81:59]
wire pma_checker_sector_hits_5 = 1'h0; // @[TLB.scala:172:55]
wire pma_checker__sector_hits_T_48 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_49 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_50 = 1'h0; // @[package.scala:81:59]
wire pma_checker_sector_hits_6 = 1'h0; // @[TLB.scala:172:55]
wire pma_checker__sector_hits_T_56 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_57 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_58 = 1'h0; // @[package.scala:81:59]
wire pma_checker_sector_hits_7 = 1'h0; // @[TLB.scala:172:55]
wire pma_checker_superpage_hits_tagMatch = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__superpage_hits_T_4 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__superpage_hits_T_9 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_superpage_hits_0 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_superpage_hits_tagMatch_1 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__superpage_hits_T_18 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__superpage_hits_T_23 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_superpage_hits_1 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_superpage_hits_tagMatch_2 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__superpage_hits_T_32 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__superpage_hits_T_37 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_superpage_hits_2 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_superpage_hits_tagMatch_3 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__superpage_hits_T_46 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__superpage_hits_T_51 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_superpage_hits_3 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_5 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_0 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_11 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_1 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_17 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_2 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_23 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_3 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_29 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_4 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_35 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_5 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_41 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_6 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_47 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_7 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker_hitsVec_tagMatch = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_52 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_57 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_62 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_hitsVec_8 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker_hitsVec_tagMatch_1 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_67 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_72 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_77 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_hitsVec_9 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker_hitsVec_tagMatch_2 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_82 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_87 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_92 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_hitsVec_10 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker_hitsVec_tagMatch_3 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_97 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_102 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_107 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_hitsVec_11 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker_hitsVec_tagMatch_4 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_112 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_117 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker__hitsVec_T_122 = 1'h0; // @[TLB.scala:183:29]
wire pma_checker_hitsVec_12 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker_refill_v = 1'h0; // @[TLB.scala:448:33]
wire pma_checker_newEntry_u = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_g = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_ae_ptw = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_ae_final = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_pf = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_gf = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_sw = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_sx = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_sr = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_hw = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_hx = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_hr = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24]
wire pma_checker__newEntry_g_T = 1'h0; // @[TLB.scala:453:25]
wire pma_checker__newEntry_ae_stage2_T = 1'h0; // @[TLB.scala:456:53]
wire pma_checker__newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84]
wire pma_checker__newEntry_sr_T_1 = 1'h0; // @[PTW.scala:141:44]
wire pma_checker__newEntry_sr_T_2 = 1'h0; // @[PTW.scala:141:38]
wire pma_checker__newEntry_sr_T_3 = 1'h0; // @[PTW.scala:141:32]
wire pma_checker__newEntry_sr_T_4 = 1'h0; // @[PTW.scala:141:52]
wire pma_checker__newEntry_sr_T_5 = 1'h0; // @[PTW.scala:149:35]
wire pma_checker__newEntry_sw_T_1 = 1'h0; // @[PTW.scala:141:44]
wire pma_checker__newEntry_sw_T_2 = 1'h0; // @[PTW.scala:141:38]
wire pma_checker__newEntry_sw_T_3 = 1'h0; // @[PTW.scala:141:32]
wire pma_checker__newEntry_sw_T_4 = 1'h0; // @[PTW.scala:141:52]
wire pma_checker__newEntry_sw_T_5 = 1'h0; // @[PTW.scala:151:35]
wire pma_checker__newEntry_sw_T_6 = 1'h0; // @[PTW.scala:151:40]
wire pma_checker__newEntry_sx_T_1 = 1'h0; // @[PTW.scala:141:44]
wire pma_checker__newEntry_sx_T_2 = 1'h0; // @[PTW.scala:141:38]
wire pma_checker__newEntry_sx_T_3 = 1'h0; // @[PTW.scala:141:32]
wire pma_checker__newEntry_sx_T_4 = 1'h0; // @[PTW.scala:141:52]
wire pma_checker__newEntry_sx_T_5 = 1'h0; // @[PTW.scala:153:35]
wire pma_checker__waddr_T = 1'h0; // @[TLB.scala:477:45]
wire pma_checker__superpage_entries_0_level_T = 1'h0; // @[package.scala:163:13]
wire pma_checker__superpage_entries_1_level_T = 1'h0; // @[package.scala:163:13]
wire pma_checker__superpage_entries_2_level_T = 1'h0; // @[package.scala:163:13]
wire pma_checker__superpage_entries_3_level_T = 1'h0; // @[package.scala:163:13]
wire pma_checker_sum = 1'h0; // @[TLB.scala:510:16]
wire pma_checker__mxr_T = 1'h0; // @[TLB.scala:518:36]
wire pma_checker_mxr = 1'h0; // @[TLB.scala:518:31]
wire pma_checker__bad_va_T = 1'h0; // @[TLB.scala:568:21]
wire pma_checker_bad_va = 1'h0; // @[TLB.scala:568:34]
wire pma_checker_cmd_lrsc = 1'h0; // @[TLB.scala:570:33]
wire pma_checker_cmd_amo_logical = 1'h0; // @[TLB.scala:571:40]
wire pma_checker_cmd_amo_arithmetic = 1'h0; // @[TLB.scala:572:43]
wire pma_checker_cmd_readx = 1'h0; // @[TLB.scala:575:37]
wire pma_checker__gf_ld_array_T = 1'h0; // @[TLB.scala:600:32]
wire pma_checker__gf_st_array_T = 1'h0; // @[TLB.scala:601:32]
wire pma_checker__gpa_hits_hit_mask_T_1 = 1'h0; // @[TLB.scala:606:60]
wire pma_checker_tlb_hit_if_not_gpa_miss = 1'h0; // @[TLB.scala:610:43]
wire pma_checker_tlb_hit = 1'h0; // @[TLB.scala:611:40]
wire pma_checker__tlb_miss_T_1 = 1'h0; // @[TLB.scala:613:29]
wire pma_checker__tlb_miss_T_3 = 1'h0; // @[TLB.scala:613:53]
wire pma_checker_tlb_miss = 1'h0; // @[TLB.scala:613:64]
wire pma_checker__state_vec_0_set_left_older_T = 1'h0; // @[Replacement.scala:196:43]
wire pma_checker__state_vec_0_set_left_older_T_1 = 1'h0; // @[Replacement.scala:196:43]
wire pma_checker_state_vec_0_left_subtree_state_1 = 1'h0; // @[package.scala:163:13]
wire pma_checker_state_vec_0_right_subtree_state_1 = 1'h0; // @[Replacement.scala:198:38]
wire pma_checker__state_vec_0_T_1 = 1'h0; // @[package.scala:163:13]
wire pma_checker__state_vec_0_T_2 = 1'h0; // @[Replacement.scala:218:17]
wire pma_checker__state_vec_0_T_4 = 1'h0; // @[Replacement.scala:203:16]
wire pma_checker__state_vec_0_T_5 = 1'h0; // @[Replacement.scala:207:62]
wire pma_checker__state_vec_0_T_6 = 1'h0; // @[Replacement.scala:218:17]
wire pma_checker__state_vec_0_set_left_older_T_2 = 1'h0; // @[Replacement.scala:196:43]
wire pma_checker_state_vec_0_left_subtree_state_2 = 1'h0; // @[package.scala:163:13]
wire pma_checker_state_vec_0_right_subtree_state_2 = 1'h0; // @[Replacement.scala:198:38]
wire pma_checker__state_vec_0_T_12 = 1'h0; // @[package.scala:163:13]
wire pma_checker__state_vec_0_T_13 = 1'h0; // @[Replacement.scala:218:17]
wire pma_checker__state_vec_0_T_15 = 1'h0; // @[Replacement.scala:203:16]
wire pma_checker__state_vec_0_T_16 = 1'h0; // @[Replacement.scala:207:62]
wire pma_checker__state_vec_0_T_17 = 1'h0; // @[Replacement.scala:218:17]
wire pma_checker__state_reg_set_left_older_T = 1'h0; // @[Replacement.scala:196:43]
wire pma_checker_state_reg_left_subtree_state = 1'h0; // @[package.scala:163:13]
wire pma_checker_state_reg_right_subtree_state = 1'h0; // @[Replacement.scala:198:38]
wire pma_checker__state_reg_T = 1'h0; // @[package.scala:163:13]
wire pma_checker__state_reg_T_1 = 1'h0; // @[Replacement.scala:218:17]
wire pma_checker__state_reg_T_3 = 1'h0; // @[Replacement.scala:203:16]
wire pma_checker__state_reg_T_4 = 1'h0; // @[Replacement.scala:207:62]
wire pma_checker__state_reg_T_5 = 1'h0; // @[Replacement.scala:218:17]
wire pma_checker__multipleHits_T_2 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_4 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_1 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_5 = 1'h0; // @[Misc.scala:182:39]
wire pma_checker_multipleHits_rightOne = 1'h0; // @[Misc.scala:178:18]
wire pma_checker_multipleHits_rightOne_1 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_7 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_leftOne_2 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_8 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_9 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_leftTwo = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__multipleHits_T_11 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_3 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_13 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_4 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_14 = 1'h0; // @[Misc.scala:182:39]
wire pma_checker_multipleHits_rightOne_2 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker_multipleHits_rightOne_3 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_16 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_1 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_rightOne_4 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_17 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_18 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_2 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_leftOne_5 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_19 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_20 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_leftTwo_1 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__multipleHits_T_23 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_6 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_25 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_7 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_26 = 1'h0; // @[Misc.scala:182:39]
wire pma_checker_multipleHits_rightOne_5 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker_multipleHits_rightOne_6 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_28 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_3 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_leftOne_8 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_29 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_30 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_leftTwo_2 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__multipleHits_T_33 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_9 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_34 = 1'h0; // @[Misc.scala:182:39]
wire pma_checker_multipleHits_rightOne_7 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker_multipleHits_leftOne_10 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_36 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_leftTwo_3 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__multipleHits_T_38 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_11 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_39 = 1'h0; // @[Misc.scala:182:39]
wire pma_checker_multipleHits_rightOne_8 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker_multipleHits_rightOne_9 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_41 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_4 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_rightOne_10 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_42 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_43 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_5 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_rightOne_11 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_44 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_45 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_6 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__multipleHits_T_46 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_47 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_48 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__io_resp_pf_ld_T = 1'h0; // @[TLB.scala:633:28]
wire pma_checker__io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28]
wire pma_checker__io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29]
wire pma_checker__io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66]
wire pma_checker__io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42]
wire pma_checker__io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29]
wire pma_checker__io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73]
wire pma_checker__io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49]
wire pma_checker__io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56]
wire pma_checker__io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30]
wire pma_checker__io_resp_miss_T = 1'h0; // @[TLB.scala:651:29]
wire pma_checker__io_resp_miss_T_1 = 1'h0; // @[TLB.scala:651:52]
wire pma_checker__io_resp_miss_T_2 = 1'h0; // @[TLB.scala:651:64]
wire pma_checker__io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36]
wire pma_checker__io_ptw_req_valid_T = 1'h0; // @[TLB.scala:662:29]
wire pma_checker_r_superpage_repl_addr_left_subtree_older = 1'h0; // @[Replacement.scala:243:38]
wire pma_checker_r_superpage_repl_addr_left_subtree_state = 1'h0; // @[package.scala:163:13]
wire pma_checker_r_superpage_repl_addr_right_subtree_state = 1'h0; // @[Replacement.scala:245:38]
wire pma_checker__r_superpage_repl_addr_T = 1'h0; // @[Replacement.scala:262:12]
wire pma_checker__r_superpage_repl_addr_T_1 = 1'h0; // @[Replacement.scala:262:12]
wire pma_checker__r_superpage_repl_addr_T_2 = 1'h0; // @[Replacement.scala:250:16]
wire pma_checker__r_superpage_repl_addr_T_4 = 1'h0; // @[TLB.scala:757:16]
wire pma_checker_r_sectored_repl_addr_left_subtree_older = 1'h0; // @[Replacement.scala:243:38]
wire pma_checker_r_sectored_repl_addr_left_subtree_older_1 = 1'h0; // @[Replacement.scala:243:38]
wire pma_checker_r_sectored_repl_addr_left_subtree_state_1 = 1'h0; // @[package.scala:163:13]
wire pma_checker_r_sectored_repl_addr_right_subtree_state_1 = 1'h0; // @[Replacement.scala:245:38]
wire pma_checker__r_sectored_repl_addr_T = 1'h0; // @[Replacement.scala:262:12]
wire pma_checker__r_sectored_repl_addr_T_1 = 1'h0; // @[Replacement.scala:262:12]
wire pma_checker__r_sectored_repl_addr_T_2 = 1'h0; // @[Replacement.scala:250:16]
wire pma_checker_r_sectored_repl_addr_left_subtree_older_2 = 1'h0; // @[Replacement.scala:243:38]
wire pma_checker_r_sectored_repl_addr_left_subtree_state_2 = 1'h0; // @[package.scala:163:13]
wire pma_checker_r_sectored_repl_addr_right_subtree_state_2 = 1'h0; // @[Replacement.scala:245:38]
wire pma_checker__r_sectored_repl_addr_T_4 = 1'h0; // @[Replacement.scala:262:12]
wire pma_checker__r_sectored_repl_addr_T_5 = 1'h0; // @[Replacement.scala:262:12]
wire pma_checker__r_sectored_repl_addr_T_6 = 1'h0; // @[Replacement.scala:250:16]
wire pma_checker__r_sectored_repl_addr_valids_T = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_1 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_2 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_3 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_4 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_5 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_6 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_7 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_8 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_9 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_10 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_11 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_12 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_13 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_14 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_15 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_16 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_17 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_18 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_19 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_20 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_21 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_22 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_valids_T_23 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_repl_addr_T_10 = 1'h0; // @[TLB.scala:757:16]
wire pma_checker__r_sectored_hit_valid_T = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_hit_valid_T_1 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_hit_valid_T_2 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_hit_valid_T_3 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_hit_valid_T_4 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_hit_valid_T_5 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_hit_valid_T_6 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_sectored_hit_bits_T_1 = 1'h0; // @[OneHot.scala:32:14]
wire pma_checker__r_sectored_hit_bits_T_3 = 1'h0; // @[OneHot.scala:32:14]
wire pma_checker__r_sectored_hit_bits_T_5 = 1'h0; // @[CircuitMath.scala:28:8]
wire pma_checker__r_superpage_hit_valid_T = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_superpage_hit_valid_T_1 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_superpage_hit_valid_T_2 = 1'h0; // @[package.scala:81:59]
wire pma_checker__r_superpage_hit_bits_T_1 = 1'h0; // @[OneHot.scala:32:14]
wire pma_checker__r_superpage_hit_bits_T_3 = 1'h0; // @[CircuitMath.scala:28:8]
wire pma_checker_hv = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_hv_1 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_1 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_hv_2 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_2 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_hv_3 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_3 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_hv_4 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_4 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_hv_5 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_5 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_hv_6 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_6 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_hv_7 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_7 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_hv_8 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_8 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_tagMatch = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__ignore_T = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_ignore = 1'h0; // @[TLB.scala:182:34]
wire pma_checker_hv_9 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_9 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_tagMatch_1 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker_hv_10 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_10 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_tagMatch_2 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker_hv_11 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_11 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_tagMatch_3 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire pma_checker_hv_12 = 1'h0; // @[TLB.scala:721:36]
wire pma_checker_hg_12 = 1'h0; // @[TLB.scala:722:36]
wire pma_checker_tagMatch_4 = 1'h0; // @[TLB.scala:178:33]
wire pma_checker__ignore_T_12 = 1'h0; // @[TLB.scala:182:28]
wire pma_checker_ignore_12 = 1'h0; // @[TLB.scala:182:34]
wire metaArb_io_in_1_valid = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_5_valid = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_5_bits_write = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_6_bits_write = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_7_bits_write = 1'h0; // @[DCache.scala:135:28]
wire dataArb_io_in_2_bits_write = 1'h0; // @[DCache.scala:152:28]
wire dataArb_io_in_3_bits_write = 1'h0; // @[DCache.scala:152:28]
wire tl_out_a_bits_corrupt = 1'h0; // @[DCache.scala:159:22]
wire nodeOut_a_deq_bits_corrupt = 1'h0; // @[Decoupled.scala:356:21]
wire _s1_tlb_req_valid_T = 1'h0; // @[Decoupled.scala:51:35]
wire s0_req_signed = 1'h0; // @[DCache.scala:192:24]
wire s0_req_no_resp = 1'h0; // @[DCache.scala:192:24]
wire s0_req_no_alloc = 1'h0; // @[DCache.scala:192:24]
wire s0_req_no_xcpt = 1'h0; // @[DCache.scala:192:24]
wire s1_waw_hazard = 1'h0; // @[DCache.scala:216:27]
wire _uncachedInFlight_WIRE_0 = 1'h0; // @[DCache.scala:236:41]
wire _s0_read_T_1 = 1'h0; // @[package.scala:16:47]
wire _s0_read_T_2 = 1'h0; // @[package.scala:16:47]
wire _s0_read_T_3 = 1'h0; // @[package.scala:16:47]
wire _s0_read_T_7 = 1'h0; // @[package.scala:16:47]
wire _s0_read_T_8 = 1'h0; // @[package.scala:16:47]
wire _s0_read_T_9 = 1'h0; // @[package.scala:16:47]
wire _s0_read_T_10 = 1'h0; // @[package.scala:16:47]
wire _s0_read_T_11 = 1'h0; // @[package.scala:81:59]
wire _s0_read_T_12 = 1'h0; // @[package.scala:81:59]
wire _s0_read_T_13 = 1'h0; // @[package.scala:81:59]
wire _s0_read_T_14 = 1'h0; // @[package.scala:16:47]
wire _s0_read_T_15 = 1'h0; // @[package.scala:16:47]
wire _s0_read_T_16 = 1'h0; // @[package.scala:16:47]
wire _s0_read_T_17 = 1'h0; // @[package.scala:16:47]
wire _s0_read_T_18 = 1'h0; // @[package.scala:16:47]
wire _s0_read_T_19 = 1'h0; // @[package.scala:81:59]
wire _s0_read_T_20 = 1'h0; // @[package.scala:81:59]
wire _s0_read_T_21 = 1'h0; // @[package.scala:81:59]
wire _s0_read_T_22 = 1'h0; // @[package.scala:81:59]
wire _s0_read_T_23 = 1'h0; // @[Consts.scala:87:44]
wire _dataArb_io_in_3_valid_res_T = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_res_T_1 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_res_T_2 = 1'h0; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_res_T_4 = 1'h0; // @[DCache.scala:1185:58]
wire _dataArb_io_in_3_valid_T_1 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_2 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_3 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_7 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_8 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_9 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_10 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_11 = 1'h0; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_12 = 1'h0; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_13 = 1'h0; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_14 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_15 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_16 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_17 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_18 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_19 = 1'h0; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_20 = 1'h0; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_21 = 1'h0; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_22 = 1'h0; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_23 = 1'h0; // @[Consts.scala:87:44]
wire _dataArb_io_in_3_valid_T_25 = 1'h0; // @[Consts.scala:90:32]
wire _dataArb_io_in_3_valid_T_26 = 1'h0; // @[Consts.scala:90:49]
wire _dataArb_io_in_3_valid_T_27 = 1'h0; // @[Consts.scala:90:42]
wire _dataArb_io_in_3_valid_T_28 = 1'h0; // @[Consts.scala:90:66]
wire _dataArb_io_in_3_valid_T_29 = 1'h0; // @[Consts.scala:90:59]
wire _dataArb_io_in_3_valid_T_30 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_31 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_32 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_33 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_34 = 1'h0; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_35 = 1'h0; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_36 = 1'h0; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_37 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_38 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_39 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_40 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_41 = 1'h0; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_42 = 1'h0; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_43 = 1'h0; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_44 = 1'h0; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_45 = 1'h0; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_46 = 1'h0; // @[Consts.scala:87:44]
wire _dataArb_io_in_3_valid_T_47 = 1'h0; // @[Consts.scala:90:76]
wire _dataArb_io_in_3_valid_T_48 = 1'h0; // @[DCache.scala:1191:35]
wire _dataArb_io_in_3_valid_T_49 = 1'h0; // @[DCache.scala:1191:57]
wire _dataArb_io_in_3_valid_T_50 = 1'h0; // @[DCache.scala:1191:45]
wire _dataArb_io_in_3_valid_T_51 = 1'h0; // @[DCache.scala:1191:23]
wire _dataArb_io_in_3_valid_T_53 = 1'h0; // @[DCache.scala:1186:12]
wire _dataArb_io_in_3_valid_T_57 = 1'h0; // @[DCache.scala:1186:11]
wire _s1_did_read_T_1 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_2 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_3 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_7 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_8 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_9 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_10 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_11 = 1'h0; // @[package.scala:81:59]
wire _s1_did_read_T_12 = 1'h0; // @[package.scala:81:59]
wire _s1_did_read_T_13 = 1'h0; // @[package.scala:81:59]
wire _s1_did_read_T_14 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_15 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_16 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_17 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_18 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_19 = 1'h0; // @[package.scala:81:59]
wire _s1_did_read_T_20 = 1'h0; // @[package.scala:81:59]
wire _s1_did_read_T_21 = 1'h0; // @[package.scala:81:59]
wire _s1_did_read_T_22 = 1'h0; // @[package.scala:81:59]
wire _s1_did_read_T_23 = 1'h0; // @[Consts.scala:87:44]
wire _s1_did_read_T_25 = 1'h0; // @[Consts.scala:90:32]
wire _s1_did_read_T_26 = 1'h0; // @[Consts.scala:90:49]
wire _s1_did_read_T_27 = 1'h0; // @[Consts.scala:90:42]
wire _s1_did_read_T_28 = 1'h0; // @[Consts.scala:90:66]
wire _s1_did_read_T_29 = 1'h0; // @[Consts.scala:90:59]
wire _s1_did_read_T_30 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_31 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_32 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_33 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_34 = 1'h0; // @[package.scala:81:59]
wire _s1_did_read_T_35 = 1'h0; // @[package.scala:81:59]
wire _s1_did_read_T_36 = 1'h0; // @[package.scala:81:59]
wire _s1_did_read_T_37 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_38 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_39 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_40 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_41 = 1'h0; // @[package.scala:16:47]
wire _s1_did_read_T_42 = 1'h0; // @[package.scala:81:59]
wire _s1_did_read_T_43 = 1'h0; // @[package.scala:81:59]
wire _s1_did_read_T_44 = 1'h0; // @[package.scala:81:59]
wire _s1_did_read_T_45 = 1'h0; // @[package.scala:81:59]
wire _s1_did_read_T_46 = 1'h0; // @[Consts.scala:87:44]
wire _s1_did_read_T_47 = 1'h0; // @[Consts.scala:90:76]
wire _s1_did_read_T_48 = 1'h0; // @[DCache.scala:1191:35]
wire _s1_did_read_T_49 = 1'h0; // @[DCache.scala:1191:57]
wire _s1_did_read_T_50 = 1'h0; // @[DCache.scala:1191:45]
wire _s1_did_read_T_51 = 1'h0; // @[DCache.scala:1191:23]
wire _tlb_io_kill_T = 1'h0; // @[DCache.scala:272:53]
wire _tlb_io_kill_T_1 = 1'h0; // @[DCache.scala:272:33]
wire _s2_pma_T_gpa_is_pte = 1'h0; // @[DCache.scala:349:18]
wire _s2_pma_T_gf_ld = 1'h0; // @[DCache.scala:349:18]
wire _s2_pma_T_gf_st = 1'h0; // @[DCache.scala:349:18]
wire _s2_pma_T_gf_inst = 1'h0; // @[DCache.scala:349:18]
wire _s2_pma_T_ma_inst = 1'h0; // @[DCache.scala:349:18]
wire s2_meta_error_uncorrectable = 1'h0; // @[DCache.scala:360:66]
wire s2_meta_error = 1'h0; // @[DCache.scala:362:83]
wire s2_store_merge = 1'h0; // @[DCache.scala:388:28]
wire _r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _s2_data_error_T = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_1 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_2 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_3 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_4 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_5 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_6 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_7 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_8 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_T_9 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_T_10 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_T_11 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_T_12 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_T_13 = 1'h0; // @[package.scala:81:59]
wire s2_data_error = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T_1 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T_2 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T_3 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T_4 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T_5 = 1'h0; // @[package.scala:81:59]
wire s2_data_error_uncorrectable = 1'h0; // @[package.scala:81:59]
wire s2_valid_data_error = 1'h0; // @[DCache.scala:421:63]
wire s2_cannot_victimize = 1'h0; // @[DCache.scala:428:45]
wire _r_T_73 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_77 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_81 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_119 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_121 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_137 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_141 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_145 = 1'h0; // @[Misc.scala:38:9]
wire _s2_dont_nack_misc_T_2 = 1'h0; // @[DCache.scala:442:23]
wire _s2_dont_nack_misc_T_3 = 1'h0; // @[DCache.scala:442:43]
wire _s2_dont_nack_misc_T_5 = 1'h0; // @[DCache.scala:442:54]
wire _s2_dont_nack_misc_T_6 = 1'h0; // @[DCache.scala:443:23]
wire _s2_dont_nack_misc_T_8 = 1'h0; // @[DCache.scala:443:44]
wire _s2_dont_nack_misc_T_9 = 1'h0; // @[DCache.scala:442:67]
wire _s2_first_meta_corrected_T = 1'h0; // @[Mux.scala:52:83]
wire _s2_first_meta_corrected_T_1 = 1'h0; // @[Mux.scala:52:83]
wire _s2_first_meta_corrected_T_2 = 1'h0; // @[Mux.scala:52:83]
wire _s2_first_meta_corrected_T_3 = 1'h0; // @[Mux.scala:52:83]
wire _metaArb_io_in_1_valid_T_2 = 1'h0; // @[DCache.scala:450:43]
wire _metaArb_io_in_1_bits_way_en_T = 1'h0; // @[OneHot.scala:85:71]
wire _metaArb_io_in_1_bits_way_en_T_1 = 1'h0; // @[OneHot.scala:85:71]
wire _metaArb_io_in_1_bits_way_en_T_2 = 1'h0; // @[OneHot.scala:85:71]
wire _metaArb_io_in_1_bits_way_en_T_3 = 1'h0; // @[OneHot.scala:85:71]
wire s2_lr = 1'h0; // @[DCache.scala:470:56]
wire s2_sc = 1'h0; // @[DCache.scala:471:56]
wire s2_sc_fail = 1'h0; // @[DCache.scala:477:26]
wire _s2_correct_T_1 = 1'h0; // @[DCache.scala:487:34]
wire _s2_correct_T_4 = 1'h0; // @[DCache.scala:487:55]
wire s2_correct = 1'h0; // @[DCache.scala:487:97]
wire _s2_valid_correct_T = 1'h0; // @[DCache.scala:489:60]
wire s2_valid_correct = 1'h0; // @[DCache.scala:489:74]
wire _pstore1_rmw_T_49 = 1'h0; // @[DCache.scala:1191:57]
wire pstore1_rmw = 1'h0; // @[DCache.scala:498:32]
wire pstore1_merge_likely = 1'h0; // @[DCache.scala:499:68]
wire pstore1_merge = 1'h0; // @[DCache.scala:500:38]
wire _pstore_drain_opportunistic_res_T = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_res_T_1 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_res_T_2 = 1'h0; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_res_T_4 = 1'h0; // @[DCache.scala:1185:58]
wire _pstore_drain_opportunistic_T_1 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_2 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_3 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_7 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_8 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_9 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_10 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_11 = 1'h0; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_12 = 1'h0; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_13 = 1'h0; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_14 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_15 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_16 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_17 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_18 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_19 = 1'h0; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_20 = 1'h0; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_21 = 1'h0; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_22 = 1'h0; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_23 = 1'h0; // @[Consts.scala:87:44]
wire _pstore_drain_opportunistic_T_25 = 1'h0; // @[Consts.scala:90:32]
wire _pstore_drain_opportunistic_T_26 = 1'h0; // @[Consts.scala:90:49]
wire _pstore_drain_opportunistic_T_27 = 1'h0; // @[Consts.scala:90:42]
wire _pstore_drain_opportunistic_T_28 = 1'h0; // @[Consts.scala:90:66]
wire _pstore_drain_opportunistic_T_29 = 1'h0; // @[Consts.scala:90:59]
wire _pstore_drain_opportunistic_T_30 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_31 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_32 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_33 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_34 = 1'h0; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_35 = 1'h0; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_36 = 1'h0; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_37 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_38 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_39 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_40 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_41 = 1'h0; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_42 = 1'h0; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_43 = 1'h0; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_44 = 1'h0; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_45 = 1'h0; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_46 = 1'h0; // @[Consts.scala:87:44]
wire _pstore_drain_opportunistic_T_47 = 1'h0; // @[Consts.scala:90:76]
wire _pstore_drain_opportunistic_T_48 = 1'h0; // @[DCache.scala:1191:35]
wire _pstore_drain_opportunistic_T_49 = 1'h0; // @[DCache.scala:1191:57]
wire _pstore_drain_opportunistic_T_50 = 1'h0; // @[DCache.scala:1191:45]
wire _pstore_drain_opportunistic_T_51 = 1'h0; // @[DCache.scala:1191:23]
wire _pstore_drain_opportunistic_T_53 = 1'h0; // @[DCache.scala:1186:12]
wire _pstore_drain_opportunistic_T_57 = 1'h0; // @[DCache.scala:1186:11]
wire _pstore_drain_opportunistic_T_60 = 1'h0; // @[DCache.scala:502:106]
wire pstore_drain_s2_kill = 1'h0; // @[DCache.scala:515:25]
wire _pstore_drain_T_1 = 1'h0; // @[DCache.scala:517:17]
wire _pstore2_storegen_data_T_2 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_6 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_10 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_14 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_18 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_22 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_26 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_30 = 1'h0; // @[DCache.scala:528:95]
wire dataArb_io_in_0_valid_s2_kill = 1'h0; // @[DCache.scala:515:25]
wire _dataArb_io_in_0_valid_T_1 = 1'h0; // @[DCache.scala:517:17]
wire _dataArb_io_in_0_bits_wordMask_T_1 = 1'h0; // @[DCache.scala:555:20]
wire _io_cpu_s2_nack_cause_raw_T_2 = 1'h0; // @[DCache.scala:574:57]
wire get_corrupt = 1'h0; // @[Edges.scala:460:17]
wire _put_legal_T_62 = 1'h0; // @[Parameters.scala:684:29]
wire _put_legal_T_68 = 1'h0; // @[Parameters.scala:684:54]
wire put_corrupt = 1'h0; // @[Edges.scala:480:17]
wire _putpartial_legal_T_62 = 1'h0; // @[Parameters.scala:684:29]
wire _putpartial_legal_T_68 = 1'h0; // @[Parameters.scala:684:54]
wire putpartial_corrupt = 1'h0; // @[Edges.scala:500:17]
wire _atomics_WIRE_source = 1'h0; // @[DCache.scala:587:51]
wire _atomics_WIRE_corrupt = 1'h0; // @[DCache.scala:587:51]
wire _atomics_WIRE_1_source = 1'h0; // @[DCache.scala:587:38]
wire _atomics_WIRE_1_corrupt = 1'h0; // @[DCache.scala:587:38]
wire _atomics_legal_T_52 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_58 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_112 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_118 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_172 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_178 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_232 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_238 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_292 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_298 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_352 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_358 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_412 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_418 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_472 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_478 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_532 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_538 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_T_1_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_3_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_5_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_7_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_9_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_11_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_13_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_15_corrupt = 1'h0; // @[DCache.scala:587:81]
wire atomics_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _tl_out_a_valid_T_8 = 1'h0; // @[DCache.scala:607:44]
wire _tl_out_a_valid_T_9 = 1'h0; // @[DCache.scala:607:65]
wire _tl_out_a_bits_legal_T = 1'h0; // @[Parameters.scala:684:29]
wire _tl_out_a_bits_legal_T_24 = 1'h0; // @[Parameters.scala:684:54]
wire _tl_out_a_bits_legal_T_39 = 1'h0; // @[Parameters.scala:686:26]
wire tl_out_a_bits_a_source = 1'h0; // @[Edges.scala:346:17]
wire tl_out_a_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17]
wire tl_out_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _tl_out_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _tl_out_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _tl_out_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _tl_out_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire _tl_out_a_bits_T_6_corrupt = 1'h0; // @[DCache.scala:611:8]
wire _tl_out_a_bits_T_7_corrupt = 1'h0; // @[DCache.scala:610:8]
wire _tl_out_a_bits_T_8_corrupt = 1'h0; // @[DCache.scala:609:8]
wire _tl_out_a_bits_T_9_corrupt = 1'h0; // @[DCache.scala:608:23]
wire nackResponseMessage_corrupt = 1'h0; // @[Edges.scala:416:17]
wire cleanReleaseMessage_corrupt = 1'h0; // @[Edges.scala:416:17]
wire dirtyReleaseMessage_corrupt = 1'h0; // @[Edges.scala:433:17]
wire _nodeOut_c_valid_T = 1'h0; // @[DCache.scala:810:48]
wire _nodeOut_c_valid_T_2 = 1'h0; // @[DCache.scala:810:74]
wire _discard_line_T_2 = 1'h0; // @[DCache.scala:818:102]
wire _release_state_T_2 = 1'h0; // @[DCache.scala:820:28]
wire _release_state_T_4 = 1'h0; // @[DCache.scala:820:54]
wire _release_state_T_5 = 1'h0; // @[DCache.scala:820:75]
wire _release_state_T_7 = 1'h0; // @[DCache.scala:820:98]
wire _release_state_T_12 = 1'h0; // @[DCache.scala:820:127]
wire probe_bits_res_source = 1'h0; // @[DCache.scala:1202:19]
wire probe_bits_res_corrupt = 1'h0; // @[DCache.scala:1202:19]
wire _nodeOut_c_bits_legal_T = 1'h0; // @[Parameters.scala:684:29]
wire _nodeOut_c_bits_legal_T_1 = 1'h0; // @[Parameters.scala:137:31]
wire _nodeOut_c_bits_legal_T_10 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_c_bits_legal_T_15 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_c_bits_legal_T_20 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_c_bits_legal_T_24 = 1'h0; // @[Parameters.scala:684:54]
wire _nodeOut_c_bits_legal_T_31 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_c_bits_legal_T_36 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_c_bits_legal_T_37 = 1'h0; // @[Parameters.scala:685:42]
wire _nodeOut_c_bits_legal_T_38 = 1'h0; // @[Parameters.scala:684:54]
wire _nodeOut_c_bits_legal_T_39 = 1'h0; // @[Parameters.scala:686:26]
wire nodeOut_c_bits_legal = 1'h0; // @[Parameters.scala:686:26]
wire nodeOut_c_bits_c_source = 1'h0; // @[Edges.scala:380:17]
wire nodeOut_c_bits_c_corrupt = 1'h0; // @[Edges.scala:380:17]
wire _nodeOut_c_bits_legal_T_40 = 1'h0; // @[Parameters.scala:684:29]
wire _nodeOut_c_bits_legal_T_41 = 1'h0; // @[Parameters.scala:137:31]
wire _nodeOut_c_bits_legal_T_50 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_c_bits_legal_T_55 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_c_bits_legal_T_60 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_c_bits_legal_T_64 = 1'h0; // @[Parameters.scala:684:54]
wire _nodeOut_c_bits_legal_T_71 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_c_bits_legal_T_76 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_c_bits_legal_T_77 = 1'h0; // @[Parameters.scala:685:42]
wire _nodeOut_c_bits_legal_T_78 = 1'h0; // @[Parameters.scala:684:54]
wire _nodeOut_c_bits_legal_T_79 = 1'h0; // @[Parameters.scala:686:26]
wire nodeOut_c_bits_legal_1 = 1'h0; // @[Parameters.scala:686:26]
wire nodeOut_c_bits_c_1_source = 1'h0; // @[Edges.scala:396:17]
wire nodeOut_c_bits_c_1_corrupt = 1'h0; // @[Edges.scala:396:17]
wire _nodeOut_c_bits_corrupt_T = 1'h0; // @[DCache.scala:887:42]
wire _io_cpu_s2_xcpt_WIRE_miss = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_gpa_is_pte = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_pf_ld = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_pf_st = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_pf_inst = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_gf_ld = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_gf_st = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_gf_inst = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ae_ld = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ae_st = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ae_inst = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ma_ld = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ma_st = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ma_inst = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_cacheable = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_must_alloc = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_prefetchable = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_T_gpa_is_pte = 1'h0; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_gf_ld = 1'h0; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_gf_st = 1'h0; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_gf_inst = 1'h0; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_ma_inst = 1'h0; // @[DCache.scala:933:24]
wire _s2_data_word_possibly_uncached_T = 1'h0; // @[DCache.scala:972:73]
wire io_cpu_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_cpu_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_cpu_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire io_cpu_resp_bits_data_word_bypass_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire _s1_flush_valid_T = 1'h0; // @[Decoupled.scala:51:35]
wire _s1_flush_valid_T_2 = 1'h0; // @[DCache.scala:1014:43]
wire _s1_flush_valid_T_4 = 1'h0; // @[DCache.scala:1014:62]
wire _s1_flush_valid_T_6 = 1'h0; // @[DCache.scala:1014:93]
wire _s1_flush_valid_T_8 = 1'h0; // @[DCache.scala:1014:122]
wire _metaArb_io_in_5_valid_T = 1'h0; // @[DCache.scala:1015:41]
wire _metaArb_io_in_5_valid_T_1 = 1'h0; // @[DCache.scala:1015:38]
wire _clock_en_reg_T_16 = 1'h0; // @[DCache.scala:1070:25]
wire _io_cpu_perf_storeBufferEmptyAfterStore_T_2 = 1'h0; // @[DCache.scala:1086:27]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_1 = 1'h0; // @[DCache.scala:1089:28]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_5 = 1'h0; // @[DCache.scala:1089:44]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_50 = 1'h0; // @[DCache.scala:1191:57]
wire [63:0] io_cpu_req_bits_data = 64'h0; // @[DCache.scala:101:7]
wire [63:0] s0_req_data = 64'h0; // @[DCache.scala:192:24]
wire [63:0] get_data = 64'h0; // @[Edges.scala:460:17]
wire [63:0] _atomics_WIRE_data = 64'h0; // @[DCache.scala:587:51]
wire [63:0] _atomics_WIRE_1_data = 64'h0; // @[DCache.scala:587:38]
wire [63:0] tl_out_a_bits_a_data = 64'h0; // @[Edges.scala:346:17]
wire [63:0] nackResponseMessage_data = 64'h0; // @[Edges.scala:416:17]
wire [63:0] cleanReleaseMessage_data = 64'h0; // @[Edges.scala:416:17]
wire [63:0] dirtyReleaseMessage_data = 64'h0; // @[Edges.scala:433:17]
wire [63:0] probe_bits_res_data = 64'h0; // @[DCache.scala:1202:19]
wire [63:0] nodeOut_c_bits_c_data = 64'h0; // @[Edges.scala:380:17]
wire [63:0] nodeOut_c_bits_c_1_data = 64'h0; // @[Edges.scala:396:17]
wire [63:0] _s2_data_word_possibly_uncached_T_1 = 64'h0; // @[DCache.scala:972:43]
wire [7:0] io_cpu_req_bits_mask = 8'h0; // @[DCache.scala:101:7]
wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[DCache.scala:101:7]
wire [7:0] pma_checker_io_ptw_status_zero1 = 8'h0; // @[DCache.scala:120:32]
wire [7:0] pma_checker_io_ptw_gstatus_zero1 = 8'h0; // @[DCache.scala:120:32]
wire [7:0] pma_checker_r_sectored_repl_addr_valids = 8'h0; // @[package.scala:45:27]
wire [7:0] pma_checker__r_sectored_hit_bits_T = 8'h0; // @[OneHot.scala:21:45]
wire [7:0] s0_req_mask = 8'h0; // @[DCache.scala:192:24]
wire [7:0] _pstore2_storegen_mask_mergedMask_T = 8'h0; // @[DCache.scala:533:42]
wire [7:0] _atomics_WIRE_mask = 8'h0; // @[DCache.scala:587:51]
wire [7:0] _atomics_WIRE_1_mask = 8'h0; // @[DCache.scala:587:38]
wire [7:0] probe_bits_res_mask = 8'h0; // @[DCache.scala:1202:19]
wire io_cpu_clock_enabled = 1'h1; // @[DCache.scala:101:7]
wire io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:101:7]
wire io_tlb_port_req_ready = 1'h1; // @[DCache.scala:101:7]
wire pma_checker_io_req_ready = 1'h1; // @[DCache.scala:120:32]
wire pma_checker_io_req_bits_passthrough = 1'h1; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:120:32]
wire pma_checker__mpu_ppn_ignore_T = 1'h1; // @[TLB.scala:197:28]
wire pma_checker_mpu_ppn_ignore = 1'h1; // @[TLB.scala:197:34]
wire pma_checker__mpu_ppn_ignore_T_1 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker_mpu_ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34]
wire pma_checker__mpu_priv_T = 1'h1; // @[TLB.scala:415:52]
wire pma_checker__mpu_priv_T_1 = 1'h1; // @[TLB.scala:415:38]
wire pma_checker__homogeneous_T_71 = 1'h1; // @[TLBPermissions.scala:87:22]
wire pma_checker__deny_access_to_debug_T = 1'h1; // @[TLB.scala:428:39]
wire pma_checker__sector_hits_T_6 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_14 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_22 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_30 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_38 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_46 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_54 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_62 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__superpage_hits_tagMatch_T = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__superpage_hits_ignore_T_1 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__superpage_hits_ignore_T_2 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__superpage_hits_tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__superpage_hits_ignore_T_4 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__superpage_hits_ignore_T_5 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__superpage_hits_tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__superpage_hits_ignore_T_7 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__superpage_hits_ignore_T_8 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__superpage_hits_tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__superpage_hits_ignore_T_10 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__superpage_hits_ignore_T_11 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__hitsVec_T_3 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_9 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_15 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_21 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_27 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_33 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_39 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_45 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_tagMatch_T = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__hitsVec_ignore_T_1 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__hitsVec_ignore_T_2 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__hitsVec_tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__hitsVec_ignore_T_4 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__hitsVec_ignore_T_5 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__hitsVec_tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__hitsVec_ignore_T_7 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__hitsVec_ignore_T_8 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__hitsVec_tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__hitsVec_ignore_T_10 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__hitsVec_ignore_T_11 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__hitsVec_tagMatch_T_4 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__hitsVec_ignore_T_13 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_13 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_116 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__hitsVec_ignore_T_14 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_hitsVec_ignore_14 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__hitsVec_T_121 = 1'h1; // @[TLB.scala:183:40]
wire pma_checker__hits_T = 1'h1; // @[TLB.scala:442:18]
wire pma_checker__newEntry_sr_T = 1'h1; // @[PTW.scala:141:47]
wire pma_checker__newEntry_sw_T = 1'h1; // @[PTW.scala:141:47]
wire pma_checker__newEntry_sx_T = 1'h1; // @[PTW.scala:141:47]
wire pma_checker__ppn_T = 1'h1; // @[TLB.scala:502:30]
wire pma_checker__ppn_ignore_T = 1'h1; // @[TLB.scala:197:28]
wire pma_checker__ppn_ignore_T_1 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker_ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34]
wire pma_checker__ppn_ignore_T_2 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker__ppn_ignore_T_3 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker_ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34]
wire pma_checker__ppn_ignore_T_4 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker__ppn_ignore_T_5 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker_ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34]
wire pma_checker__ppn_ignore_T_6 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker__ppn_ignore_T_7 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker_ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34]
wire pma_checker__ppn_ignore_T_8 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker_ppn_ignore_8 = 1'h1; // @[TLB.scala:197:34]
wire pma_checker__ppn_ignore_T_9 = 1'h1; // @[TLB.scala:197:28]
wire pma_checker_ppn_ignore_9 = 1'h1; // @[TLB.scala:197:34]
wire pma_checker__stage1_bypass_T_1 = 1'h1; // @[TLB.scala:517:83]
wire pma_checker__stage2_bypass_T = 1'h1; // @[TLB.scala:523:42]
wire pma_checker__bad_va_T_1 = 1'h1; // @[TLB.scala:560:26]
wire pma_checker__gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107]
wire pma_checker__tlb_miss_T = 1'h1; // @[TLB.scala:613:32]
wire pma_checker__tlb_miss_T_2 = 1'h1; // @[TLB.scala:613:56]
wire pma_checker__tlb_miss_T_4 = 1'h1; // @[TLB.scala:613:67]
wire pma_checker_state_vec_0_set_left_older = 1'h1; // @[Replacement.scala:196:33]
wire pma_checker_state_vec_0_set_left_older_1 = 1'h1; // @[Replacement.scala:196:33]
wire pma_checker__state_vec_0_T_3 = 1'h1; // @[Replacement.scala:218:7]
wire pma_checker__state_vec_0_T_7 = 1'h1; // @[Replacement.scala:218:7]
wire pma_checker__state_vec_0_T_8 = 1'h1; // @[Replacement.scala:206:16]
wire pma_checker_state_vec_0_set_left_older_2 = 1'h1; // @[Replacement.scala:196:33]
wire pma_checker__state_vec_0_T_14 = 1'h1; // @[Replacement.scala:218:7]
wire pma_checker__state_vec_0_T_18 = 1'h1; // @[Replacement.scala:218:7]
wire pma_checker__state_vec_0_T_19 = 1'h1; // @[Replacement.scala:206:16]
wire pma_checker_state_reg_set_left_older = 1'h1; // @[Replacement.scala:196:33]
wire pma_checker__state_reg_T_2 = 1'h1; // @[Replacement.scala:218:7]
wire pma_checker__state_reg_T_6 = 1'h1; // @[Replacement.scala:218:7]
wire pma_checker__state_reg_T_7 = 1'h1; // @[Replacement.scala:206:16]
wire pma_checker__io_req_ready_T = 1'h1; // @[TLB.scala:631:25]
wire pma_checker__io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20]
wire pma_checker__io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28]
wire pma_checker__r_superpage_repl_addr_T_6 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_superpage_repl_addr_T_7 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_superpage_repl_addr_T_8 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_superpage_repl_addr_T_9 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_sectored_repl_addr_T_12 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_sectored_repl_addr_T_13 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_sectored_repl_addr_T_14 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_sectored_repl_addr_T_15 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_sectored_repl_addr_T_16 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_sectored_repl_addr_T_17 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_sectored_repl_addr_T_18 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__r_sectored_repl_addr_T_19 = 1'h1; // @[OneHot.scala:48:45]
wire pma_checker__tagMatch_T = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__ignore_T_1 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__ignore_T_2 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__ignore_T_4 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__ignore_T_5 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__ignore_T_7 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__ignore_T_8 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__ignore_T_10 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker__ignore_T_11 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__tagMatch_T_4 = 1'h1; // @[TLB.scala:178:43]
wire pma_checker__ignore_T_13 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_ignore_13 = 1'h1; // @[TLB.scala:182:34]
wire pma_checker__ignore_T_14 = 1'h1; // @[TLB.scala:182:28]
wire pma_checker_ignore_14 = 1'h1; // @[TLB.scala:182:34]
wire metaArb_io_in_0_ready = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_0_bits_write = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_1_bits_write = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_2_bits_write = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_3_bits_write = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_4_bits_write = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_out_ready = 1'h1; // @[DCache.scala:135:28]
wire metaArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19]
wire dataArb_io_in_0_ready = 1'h1; // @[DCache.scala:152:28]
wire dataArb_io_in_1_bits_wordMask = 1'h1; // @[DCache.scala:152:28]
wire dataArb_io_in_2_bits_wordMask = 1'h1; // @[DCache.scala:152:28]
wire dataArb_io_in_3_bits_wordMask = 1'h1; // @[DCache.scala:152:28]
wire dataArb_io_out_ready = 1'h1; // @[DCache.scala:152:28]
wire dataArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19]
wire _s0_read_T = 1'h1; // @[package.scala:16:47]
wire _s0_read_T_4 = 1'h1; // @[package.scala:81:59]
wire _s0_read_T_5 = 1'h1; // @[package.scala:81:59]
wire _s0_read_T_6 = 1'h1; // @[package.scala:81:59]
wire s0_read = 1'h1; // @[Consts.scala:89:68]
wire _dataArb_io_in_3_valid_res_T_3 = 1'h1; // @[DCache.scala:1185:15]
wire dataArb_io_in_3_valid_res = 1'h1; // @[DCache.scala:1185:46]
wire _dataArb_io_in_3_valid_T = 1'h1; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_4 = 1'h1; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_5 = 1'h1; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_6 = 1'h1; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_24 = 1'h1; // @[Consts.scala:89:68]
wire _dataArb_io_in_3_valid_T_52 = 1'h1; // @[DCache.scala:1190:21]
wire _dataArb_io_in_3_valid_T_54 = 1'h1; // @[DCache.scala:1186:28]
wire _s1_did_read_T = 1'h1; // @[package.scala:16:47]
wire _s1_did_read_T_4 = 1'h1; // @[package.scala:81:59]
wire _s1_did_read_T_5 = 1'h1; // @[package.scala:81:59]
wire _s1_did_read_T_6 = 1'h1; // @[package.scala:81:59]
wire _s1_did_read_T_24 = 1'h1; // @[Consts.scala:89:68]
wire _s1_did_read_T_52 = 1'h1; // @[DCache.scala:1190:21]
wire _s2_valid_not_killed_T = 1'h1; // @[DCache.scala:338:48]
wire _s2_flush_valid_T = 1'h1; // @[DCache.scala:363:54]
wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T = 1'h1; // @[DCache.scala:397:74]
wire _s2_valid_hit_pre_data_ecc_and_waw_T_1 = 1'h1; // @[DCache.scala:418:108]
wire _s2_valid_hit_pre_data_ecc_T = 1'h1; // @[DCache.scala:420:73]
wire _s2_valid_hit_pre_data_ecc_T_1 = 1'h1; // @[DCache.scala:420:88]
wire _s2_valid_hit_T = 1'h1; // @[DCache.scala:422:51]
wire _s2_valid_miss_T_1 = 1'h1; // @[DCache.scala:423:58]
wire _s2_victimize_T = 1'h1; // @[DCache.scala:429:43]
wire _r_T_117 = 1'h1; // @[Metadata.scala:140:24]
wire _s2_dont_nack_misc_T = 1'h1; // @[DCache.scala:441:46]
wire _s2_dont_nack_misc_T_4 = 1'h1; // @[DCache.scala:442:57]
wire _metaArb_io_in_2_bits_write_T = 1'h1; // @[DCache.scala:463:34]
wire _s2_valid_correct_T_1 = 1'h1; // @[DCache.scala:489:77]
wire _pstore1_merge_T_1 = 1'h1; // @[DCache.scala:490:61]
wire _pstore1_merge_T_3 = 1'h1; // @[DCache.scala:491:51]
wire _pstore_drain_opportunistic_res_T_3 = 1'h1; // @[DCache.scala:1185:15]
wire pstore_drain_opportunistic_res = 1'h1; // @[DCache.scala:1185:46]
wire _pstore_drain_opportunistic_T = 1'h1; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_4 = 1'h1; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_5 = 1'h1; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_6 = 1'h1; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_24 = 1'h1; // @[Consts.scala:89:68]
wire _pstore_drain_opportunistic_T_52 = 1'h1; // @[DCache.scala:1190:21]
wire _pstore_drain_opportunistic_T_54 = 1'h1; // @[DCache.scala:1186:28]
wire _pstore_drain_opportunistic_T_61 = 1'h1; // @[DCache.scala:502:95]
wire _pstore1_valid_T_1 = 1'h1; // @[DCache.scala:490:61]
wire _pstore1_valid_T_3 = 1'h1; // @[DCache.scala:491:51]
wire _pstore_drain_T = 1'h1; // @[DCache.scala:516:5]
wire _pstore_drain_T_3 = 1'h1; // @[DCache.scala:506:87]
wire _pstore_drain_T_6 = 1'h1; // @[DCache.scala:518:44]
wire _pstore1_held_T_1 = 1'h1; // @[DCache.scala:490:61]
wire _pstore1_held_T_3 = 1'h1; // @[DCache.scala:491:51]
wire _pstore1_held_T_5 = 1'h1; // @[DCache.scala:521:38]
wire _dataArb_io_in_0_valid_T = 1'h1; // @[DCache.scala:516:5]
wire _dataArb_io_in_0_valid_T_3 = 1'h1; // @[DCache.scala:506:87]
wire _dataArb_io_in_0_valid_T_6 = 1'h1; // @[DCache.scala:518:44]
wire _dataArb_io_in_0_bits_wordMask_T = 1'h1; // @[DCache.scala:555:20]
wire _io_cpu_s2_nack_cause_raw_T = 1'h1; // @[DCache.scala:574:59]
wire _io_cpu_s2_nack_cause_raw_T_1 = 1'h1; // @[DCache.scala:574:74]
wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _get_legal_T_62 = 1'h1; // @[Parameters.scala:92:28]
wire _get_legal_T_63 = 1'h1; // @[Parameters.scala:92:38]
wire _get_legal_T_64 = 1'h1; // @[Parameters.scala:92:33]
wire _get_legal_T_65 = 1'h1; // @[Parameters.scala:684:29]
wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _put_legal_T_69 = 1'h1; // @[Parameters.scala:92:28]
wire _put_legal_T_70 = 1'h1; // @[Parameters.scala:92:38]
wire _put_legal_T_71 = 1'h1; // @[Parameters.scala:92:33]
wire _put_legal_T_72 = 1'h1; // @[Parameters.scala:684:29]
wire _putpartial_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _putpartial_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _putpartial_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _putpartial_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _putpartial_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _putpartial_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _putpartial_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _putpartial_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _putpartial_legal_T_69 = 1'h1; // @[Parameters.scala:92:28]
wire _putpartial_legal_T_70 = 1'h1; // @[Parameters.scala:92:38]
wire _putpartial_legal_T_71 = 1'h1; // @[Parameters.scala:92:33]
wire _putpartial_legal_T_72 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_60 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_61 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_62 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_63 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_120 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_121 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_122 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_123 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_180 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_181 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_182 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_183 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_240 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_241 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_242 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_243 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_300 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_301 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_302 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_303 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_360 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_361 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_362 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_363 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_420 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_421 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_422 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_423 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_480 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_481 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_482 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_483 = 1'h1; // @[Parameters.scala:684:29]
wire _tl_out_a_valid_T = 1'h1; // @[DCache.scala:603:21]
wire _tl_out_a_bits_legal_T_25 = 1'h1; // @[Parameters.scala:91:44]
wire _tl_out_a_bits_legal_T_26 = 1'h1; // @[Parameters.scala:684:29]
wire tl_out_a_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire tl_out_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire tl_out_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire tl_out_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire tl_out_a_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire _tl_d_data_encoded_T_9 = 1'h1; // @[DCache.scala:663:80]
wire _dataArb_io_in_1_bits_wordMask_T = 1'h1; // @[DCache.scala:731:39]
wire _nodeOut_c_bits_legal_T_5 = 1'h1; // @[Parameters.scala:137:59]
wire _nodeOut_c_bits_legal_T_21 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_c_bits_legal_T_22 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_c_bits_legal_T_23 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_c_bits_legal_T_25 = 1'h1; // @[Parameters.scala:91:44]
wire _nodeOut_c_bits_legal_T_26 = 1'h1; // @[Parameters.scala:684:29]
wire _nodeOut_c_bits_legal_T_45 = 1'h1; // @[Parameters.scala:137:59]
wire _nodeOut_c_bits_legal_T_61 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_c_bits_legal_T_62 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_c_bits_legal_T_63 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_c_bits_legal_T_65 = 1'h1; // @[Parameters.scala:91:44]
wire _nodeOut_c_bits_legal_T_66 = 1'h1; // @[Parameters.scala:684:29]
wire _dataArb_io_in_2_bits_wordMask_T = 1'h1; // @[DCache.scala:904:37]
wire _io_cpu_resp_valid_T_1 = 1'h1; // @[DCache.scala:949:73]
wire _io_cpu_replay_next_T_2 = 1'h1; // @[DCache.scala:950:65]
wire _clock_en_reg_T = 1'h1; // @[DCache.scala:1060:19]
wire _clock_en_reg_T_1 = 1'h1; // @[DCache.scala:1060:44]
wire _clock_en_reg_T_2 = 1'h1; // @[DCache.scala:1061:46]
wire _clock_en_reg_T_3 = 1'h1; // @[DCache.scala:1062:31]
wire _clock_en_reg_T_4 = 1'h1; // @[DCache.scala:1063:26]
wire _clock_en_reg_T_5 = 1'h1; // @[DCache.scala:1064:14]
wire _clock_en_reg_T_6 = 1'h1; // @[DCache.scala:1064:26]
wire _clock_en_reg_T_7 = 1'h1; // @[DCache.scala:1065:14]
wire _clock_en_reg_T_8 = 1'h1; // @[DCache.scala:1065:26]
wire _clock_en_reg_T_9 = 1'h1; // @[DCache.scala:1066:27]
wire _clock_en_reg_T_10 = 1'h1; // @[DCache.scala:1067:22]
wire _clock_en_reg_T_11 = 1'h1; // @[DCache.scala:1067:42]
wire _clock_en_reg_T_12 = 1'h1; // @[DCache.scala:1068:18]
wire _clock_en_reg_T_14 = 1'h1; // @[DCache.scala:1068:35]
wire _clock_en_reg_T_15 = 1'h1; // @[DCache.scala:1069:31]
wire _clock_en_reg_T_17 = 1'h1; // @[DCache.scala:1070:22]
wire _clock_en_reg_T_19 = 1'h1; // @[DCache.scala:1070:46]
wire _clock_en_reg_T_20 = 1'h1; // @[DCache.scala:1071:23]
wire _clock_en_reg_T_22 = 1'h1; // @[DCache.scala:1072:23]
wire _clock_en_reg_T_24 = 1'h1; // @[DCache.scala:1072:54]
wire _clock_en_reg_T_26 = 1'h1; // @[DCache.scala:1073:21]
wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_2 = 1'h1; // @[DCache.scala:1082:31]
wire _io_cpu_perf_storeBufferEmptyAfterStore_T_5 = 1'h1; // @[DCache.scala:1087:31]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_3 = 1'h1; // @[DCache.scala:1089:72]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_56 = 1'h1; // @[DCache.scala:1092:115]
wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_tlb_port_req_bits_size = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_tlb_port_req_bits_prv = 2'h0; // @[DCache.scala:101:7]
wire [1:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_software = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_resp_bits_level = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_dprv = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_prv = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_sxl = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_uxl = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_xs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_fs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_mpp = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_vs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_hstatus_vsxl = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_dprv = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_prv = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_sxl = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_uxl = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_fs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_mpp = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_vs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_real_hits_lo_lo_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_real_hits_lo_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_real_hits_hi_lo_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_real_hits_hi_hi_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_real_hits_hi_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker__special_entry_level_T = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_special_entry_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_special_entry_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_special_entry_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_special_entry_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_waddr = 2'h0; // @[TLB.scala:477:22]
wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_1 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_2 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_3 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_4 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_5 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_6 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_7 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_lo_lo = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_lo_hi = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_hi_lo = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_hi_hi = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_hi_2 = 2'h0; // @[OneHot.scala:30:18]
wire [1:0] pma_checker_lo_2 = 2'h0; // @[OneHot.scala:31:18]
wire [1:0] pma_checker__state_vec_0_T = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker__state_vec_0_T_11 = 2'h0; // @[Replacement.scala:207:62]
wire [1:0] pma_checker_lo_3 = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_hi_3 = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_hi_4 = 2'h0; // @[OneHot.scala:30:18]
wire [1:0] pma_checker_lo_4 = 2'h0; // @[OneHot.scala:31:18]
wire [1:0] pma_checker_state_reg_touch_way_sized = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker__multipleHits_T_3 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] pma_checker__multipleHits_T_12 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] pma_checker__multipleHits_T_24 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] pma_checker__multipleHits_T_32 = 2'h0; // @[Misc.scala:181:37]
wire [1:0] pma_checker__multipleHits_T_37 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] pma_checker__r_superpage_repl_addr_T_3 = 2'h0; // @[Replacement.scala:249:12]
wire [1:0] pma_checker_r_superpage_repl_addr_valids_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_r_superpage_repl_addr_valids_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker__r_superpage_repl_addr_T_12 = 2'h0; // @[Mux.scala:50:70]
wire [1:0] pma_checker__r_superpage_repl_addr_T_13 = 2'h0; // @[TLB.scala:757:8]
wire [1:0] pma_checker__r_sectored_repl_addr_T_3 = 2'h0; // @[Replacement.scala:249:12]
wire [1:0] pma_checker__r_sectored_repl_addr_T_7 = 2'h0; // @[Replacement.scala:249:12]
wire [1:0] pma_checker__r_sectored_repl_addr_T_8 = 2'h0; // @[Replacement.scala:250:16]
wire [1:0] pma_checker_r_sectored_repl_addr_valids_lo_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_r_sectored_repl_addr_valids_lo_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_r_sectored_repl_addr_valids_hi_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_r_sectored_repl_addr_valids_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_r_sectored_hit_bits_lo_lo = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_r_sectored_hit_bits_lo_hi = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_r_sectored_hit_bits_hi_lo = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_r_sectored_hit_bits_hi_hi = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_r_sectored_hit_bits_hi_2 = 2'h0; // @[OneHot.scala:30:18]
wire [1:0] pma_checker_r_sectored_hit_bits_lo_2 = 2'h0; // @[OneHot.scala:31:18]
wire [1:0] pma_checker__r_sectored_hit_bits_T_4 = 2'h0; // @[OneHot.scala:32:28]
wire [1:0] pma_checker__r_sectored_hit_bits_T_6 = 2'h0; // @[OneHot.scala:32:10]
wire [1:0] pma_checker_r_superpage_hit_bits_lo = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_r_superpage_hit_bits_hi = 2'h0; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_r_superpage_hit_bits_hi_1 = 2'h0; // @[OneHot.scala:30:18]
wire [1:0] pma_checker_r_superpage_hit_bits_lo_1 = 2'h0; // @[OneHot.scala:31:18]
wire [1:0] pma_checker__r_superpage_hit_bits_T_2 = 2'h0; // @[OneHot.scala:32:28]
wire [1:0] pma_checker__r_superpage_hit_bits_T_4 = 2'h0; // @[OneHot.scala:32:10]
wire [1:0] s1_meta_hit_state_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _s2_valid_no_xcpt_T_1 = 2'h0; // @[DCache.scala:332:54]
wire [1:0] s2_meta_correctable_errors_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] s2_meta_correctable_errors_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] s2_meta_uncorrectable_errors_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] s2_meta_uncorrectable_errors_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] _r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_75 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_79 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_83 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_87 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_91 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_139 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_143 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_147 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_151 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_155 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _metaArb_io_in_3_bits_data_T_2 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _metaArb_io_in_3_bits_data_T_4 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] probe_bits_res_param = 2'h0; // @[DCache.scala:1202:19]
wire [1:0] _nodeOut_c_bits_legal_T_2 = 2'h0; // @[Parameters.scala:137:41]
wire [1:0] _nodeOut_c_bits_legal_T_42 = 2'h0; // @[Parameters.scala:137:41]
wire [1:0] _io_cpu_s2_xcpt_WIRE_size = 2'h0; // @[DCache.scala:933:74]
wire [1:0] metaArb_io_in_0_bits_data_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] metaArb_io_in_0_bits_data_meta_1_coh_state = 2'h0; // @[HellaCache.scala:305:20]
wire [3:0] pma_checker__r_superpage_repl_addr_T_5 = 4'hF; // @[TLB.scala:757:43]
wire [3:0] metaArb_io_in_0_bits_way_en = 4'hF; // @[DCache.scala:135:28]
wire [3:0] dataArb_io_in_2_bits_way_en = 4'hF; // @[DCache.scala:152:28]
wire [3:0] dataArb_io_in_3_bits_way_en = 4'hF; // @[DCache.scala:152:28]
wire [3:0] _dataArb_io_in_3_bits_way_en_T = 4'hF; // @[DCache.scala:257:35]
wire [3:0] _r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] tl_out_a_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] tl_out_a_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10]
wire [3:0] _dataArb_io_in_2_bits_way_en_T = 4'hF; // @[DCache.scala:906:35]
wire [3:0] _metaArb_io_in_0_bits_way_en_T = 4'hF; // @[DCache.scala:1049:35]
wire [7:0] pma_checker__r_sectored_repl_addr_T_11 = 8'hFF; // @[TLB.scala:757:43]
wire [7:0] dataArb_io_in_1_bits_eccMask = 8'hFF; // @[DCache.scala:152:28]
wire [7:0] dataArb_io_in_2_bits_eccMask = 8'hFF; // @[DCache.scala:152:28]
wire [7:0] dataArb_io_in_3_bits_eccMask = 8'hFF; // @[DCache.scala:152:28]
wire [7:0] _dataArb_io_in_3_bits_wordMask_T = 8'hFF; // @[DCache.scala:254:9]
wire [7:0] _dataArb_io_in_3_bits_eccMask_T = 8'hFF; // @[DCache.scala:256:36]
wire [7:0] tl_out_a_bits_a_mask = 8'hFF; // @[Edges.scala:346:17]
wire [7:0] _tl_out_a_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10]
wire [7:0] _dataArb_io_in_1_bits_eccMask_T = 8'hFF; // @[DCache.scala:732:38]
wire [7:0] _dataArb_io_in_2_bits_eccMask_T = 8'hFF; // @[DCache.scala:905:36]
wire [2:0] pma_checker__r_sectored_repl_addr_T_20 = 3'h6; // @[Mux.scala:50:70]
wire [2:0] tl_out_a_bits_a_opcode = 3'h6; // @[Edges.scala:346:17]
wire [2:0] _tl_out_a_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34]
wire [2:0] nodeOut_c_bits_c_opcode = 3'h6; // @[Edges.scala:380:17]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:101:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:101:7]
wire [3:0] pma_checker_io_ptw_ptbr_mode = 4'h0; // @[DCache.scala:120:32]
wire [3:0] pma_checker_io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:120:32]
wire [3:0] pma_checker_io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:120:32]
wire [3:0] pma_checker_satp_mode = 4'h0; // @[TLB.scala:373:17]
wire [3:0] pma_checker_real_hits_hi_hi = 4'h0; // @[package.scala:45:27]
wire [3:0] pma_checker_lo = 4'h0; // @[OneHot.scala:21:45]
wire [3:0] pma_checker_hi = 4'h0; // @[OneHot.scala:21:45]
wire [3:0] pma_checker_hi_1 = 4'h0; // @[OneHot.scala:30:18]
wire [3:0] pma_checker_lo_1 = 4'h0; // @[OneHot.scala:31:18]
wire [3:0] pma_checker__multipleHits_T_31 = 4'h0; // @[Misc.scala:182:39]
wire [3:0] pma_checker_r_superpage_repl_addr_valids = 4'h0; // @[package.scala:45:27]
wire [3:0] pma_checker_r_sectored_repl_addr_valids_lo = 4'h0; // @[package.scala:45:27]
wire [3:0] pma_checker_r_sectored_repl_addr_valids_hi = 4'h0; // @[package.scala:45:27]
wire [3:0] pma_checker_r_sectored_hit_bits_lo = 4'h0; // @[OneHot.scala:21:45]
wire [3:0] pma_checker_r_sectored_hit_bits_hi = 4'h0; // @[OneHot.scala:21:45]
wire [3:0] pma_checker_r_sectored_hit_bits_hi_1 = 4'h0; // @[OneHot.scala:30:18]
wire [3:0] pma_checker_r_sectored_hit_bits_lo_1 = 4'h0; // @[OneHot.scala:31:18]
wire [3:0] pma_checker__r_sectored_hit_bits_T_2 = 4'h0; // @[OneHot.scala:32:28]
wire [3:0] pma_checker__r_superpage_hit_bits_T = 4'h0; // @[OneHot.scala:21:45]
wire [3:0] metaArb_io_in_1_bits_way_en = 4'h0; // @[DCache.scala:135:28]
wire [3:0] s2_meta_correctable_errors = 4'h0; // @[package.scala:45:27]
wire [3:0] s2_meta_uncorrectable_errors = 4'h0; // @[package.scala:45:27]
wire [3:0] _s2_meta_error_T = 4'h0; // @[DCache.scala:362:53]
wire [3:0] _r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r_T_63 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _r_T_127 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _metaArb_io_in_1_bits_way_en_T_4 = 4'h0; // @[Mux.scala:50:70]
wire [3:0] _metaArb_io_in_1_bits_way_en_T_5 = 4'h0; // @[Mux.scala:50:70]
wire [3:0] _metaArb_io_in_1_bits_way_en_T_6 = 4'h0; // @[Mux.scala:50:70]
wire [3:0] _metaArb_io_in_1_bits_way_en_T_7 = 4'h0; // @[Mux.scala:50:70]
wire [3:0] _metaArb_io_in_1_bits_way_en_T_8 = 4'h0; // @[DCache.scala:452:69]
wire [3:0] _metaArb_io_in_1_bits_way_en_T_9 = 4'h0; // @[DCache.scala:452:64]
wire [3:0] _a_mask_T = 4'h0; // @[DCache.scala:582:90]
wire [3:0] _atomics_WIRE_size = 4'h0; // @[DCache.scala:587:51]
wire [3:0] _atomics_WIRE_1_size = 4'h0; // @[DCache.scala:587:38]
wire [3:0] _metaArb_io_in_3_bits_data_T_5 = 4'h0; // @[Metadata.scala:87:10]
wire [3:0] probe_bits_res_size = 4'h0; // @[DCache.scala:1202:19]
wire [2:0] pma_checker_real_hits_lo_lo = 3'h0; // @[package.scala:45:27]
wire [2:0] pma_checker_real_hits_lo_hi = 3'h0; // @[package.scala:45:27]
wire [2:0] pma_checker_real_hits_hi_lo = 3'h0; // @[package.scala:45:27]
wire [2:0] pma_checker_special_entry_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_special_entry_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_special_entry_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_waddr_1 = 3'h0; // @[TLB.scala:485:22]
wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_state_vec_0_touch_way_sized = 3'h0; // @[package.scala:163:13]
wire [2:0] pma_checker_state_vec_0_left_subtree_state = 3'h0; // @[package.scala:163:13]
wire [2:0] pma_checker_state_vec_0_right_subtree_state = 3'h0; // @[Replacement.scala:198:38]
wire [2:0] pma_checker__state_vec_0_T_10 = 3'h0; // @[Replacement.scala:203:16]
wire [2:0] pma_checker__multipleHits_T_1 = 3'h0; // @[Misc.scala:181:37]
wire [2:0] pma_checker__multipleHits_T_10 = 3'h0; // @[Misc.scala:182:39]
wire [2:0] pma_checker__multipleHits_T_22 = 3'h0; // @[Misc.scala:181:37]
wire [2:0] pma_checker_r_sectored_repl_addr_left_subtree_state = 3'h0; // @[package.scala:163:13]
wire [2:0] pma_checker_r_sectored_repl_addr_right_subtree_state = 3'h0; // @[Replacement.scala:245:38]
wire [2:0] pma_checker__r_sectored_repl_addr_T_9 = 3'h0; // @[Replacement.scala:249:12]
wire [2:0] pma_checker__r_sectored_repl_addr_T_26 = 3'h0; // @[Mux.scala:50:70]
wire [2:0] pma_checker__r_sectored_repl_addr_T_27 = 3'h0; // @[TLB.scala:757:8]
wire [2:0] pma_checker__r_sectored_hit_bits_T_7 = 3'h0; // @[OneHot.scala:32:10]
wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17]
wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] putpartial_param = 3'h0; // @[Edges.scala:500:17]
wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[DCache.scala:587:51]
wire [2:0] _atomics_WIRE_param = 3'h0; // @[DCache.scala:587:51]
wire [2:0] _atomics_WIRE_1_opcode = 3'h0; // @[DCache.scala:587:38]
wire [2:0] _atomics_WIRE_1_param = 3'h0; // @[DCache.scala:587:38]
wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17]
wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17]
wire [2:0] probe_bits_res_opcode = 3'h0; // @[DCache.scala:1202:19]
wire [2:0] pma_checker__state_vec_0_T_9 = 3'h5; // @[Replacement.scala:202:12]
wire [2:0] pma_checker__state_vec_0_T_20 = 3'h5; // @[Replacement.scala:202:12]
wire [2:0] pma_checker__state_vec_0_T_21 = 3'h5; // @[Replacement.scala:206:16]
wire [2:0] pma_checker__state_reg_T_8 = 3'h5; // @[Replacement.scala:202:12]
wire [2:0] pma_checker__r_sectored_repl_addr_T_21 = 3'h5; // @[Mux.scala:50:70]
wire [2:0] tl_out_a_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81]
wire [2:0] nackResponseMessage_param = 3'h5; // @[Edges.scala:416:17]
wire [2:0] dirtyReleaseMessage_opcode = 3'h5; // @[Edges.scala:433:17]
wire [2:0] pma_checker__r_sectored_repl_addr_T_22 = 3'h4; // @[Mux.scala:50:70]
wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17]
wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17]
wire [2:0] _tl_out_a_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27]
wire [2:0] nackResponseMessage_opcode = 3'h4; // @[Edges.scala:416:17]
wire [2:0] cleanReleaseMessage_opcode = 3'h4; // @[Edges.scala:416:17]
wire [1:0] pma_checker__r_superpage_repl_addr_T_11 = 2'h1; // @[Mux.scala:50:70]
wire [1:0] _r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] dataArb_io_in_0_bits_wordMask_wordMask = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _dataArb_io_in_0_bits_wordMask_T_2 = 2'h1; // @[DCache.scala:555:20]
wire [1:0] _metaArb_io_in_3_bits_data_T_6 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] pma_checker_state_vec_0_hi = 2'h2; // @[Replacement.scala:202:12]
wire [1:0] pma_checker_state_vec_0_hi_1 = 2'h2; // @[Replacement.scala:202:12]
wire [1:0] pma_checker_state_reg_hi = 2'h2; // @[Replacement.scala:202:12]
wire [1:0] pma_checker__r_superpage_repl_addr_T_10 = 2'h2; // @[Mux.scala:50:70]
wire [1:0] pma_checker__state_T = 2'h2; // @[TLB.scala:704:45]
wire [1:0] _r_T_118 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_120 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_122 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] tl_out_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [2:0] pma_checker__r_sectored_repl_addr_T_23 = 3'h3; // @[Mux.scala:50:70]
wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17]
wire [2:0] pma_checker__r_sectored_repl_addr_T_24 = 3'h2; // @[Mux.scala:50:70]
wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17]
wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] pma_checker_mpu_priv = 3'h1; // @[TLB.scala:415:27]
wire [2:0] pma_checker__r_sectored_repl_addr_T_25 = 3'h1; // @[Mux.scala:50:70]
wire [2:0] putpartial_opcode = 3'h1; // @[Edges.scala:500:17]
wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17]
wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17]
wire [3:0] pma_checker_state_vec_0_hi_2 = 4'h8; // @[Replacement.scala:202:12]
wire [3:0] _r_T_71 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _r_T_135 = 4'h8; // @[Metadata.scala:133:10]
wire [11:0] pma_checker__gpa_hits_hit_mask_T_2 = 12'h0; // @[TLB.scala:606:24]
wire [11:0] pma_checker__io_resp_gpa_offset_T = 12'h0; // @[TLB.scala:658:47]
wire [26:0] pma_checker_io_ptw_req_bits_bits_addr = 27'h0; // @[DCache.scala:120:32]
wire [26:0] pma_checker__io_resp_gpa_page_T_2 = 27'h0; // @[TLB.scala:657:58]
wire [6:0] pma_checker__state_vec_0_T_22 = 7'h45; // @[Replacement.scala:202:12]
wire [38:0] pma_checker_io_sfence_bits_addr = 39'h0; // @[DCache.scala:120:32]
wire [38:0] pma_checker_io_ptw_resp_bits_gpa_bits = 39'h0; // @[DCache.scala:120:32]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:101:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:101:7]
wire [15:0] pma_checker_io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:120:32]
wire [15:0] pma_checker_io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:120:32]
wire [15:0] pma_checker_io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:120:32]
wire [15:0] pma_checker_satp_asid = 16'h0; // @[TLB.scala:373:17]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:101:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:101:7]
wire [43:0] pma_checker_io_ptw_resp_bits_pte_ppn = 44'h0; // @[DCache.scala:120:32]
wire [43:0] pma_checker_io_ptw_ptbr_ppn = 44'h0; // @[DCache.scala:120:32]
wire [43:0] pma_checker_io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:120:32]
wire [43:0] pma_checker_io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:120:32]
wire [43:0] pma_checker_satp_ppn = 44'h0; // @[TLB.scala:373:17]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:101:7]
wire [29:0] pma_checker_io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:120:32]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:101:7]
wire [8:0] pma_checker_io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:120:32]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:101:7]
wire [5:0] pma_checker_io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:120:32]
wire [5:0] pma_checker_real_hits_lo = 6'h0; // @[package.scala:45:27]
wire [5:0] pma_checker_special_entry_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_superpage_entries_0_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_superpage_entries_1_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_superpage_entries_2_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_superpage_entries_3_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_0_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_1_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_2_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_3_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_4_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_5_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_6_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_7_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker__multipleHits_T = 6'h0; // @[Misc.scala:181:37]
wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[DCache.scala:101:7]
wire [31:0] pma_checker_io_ptw_status_isa = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_gstatus_isa = 32'h0; // @[DCache.scala:120:32]
wire [31:0] _atomics_WIRE_address = 32'h0; // @[DCache.scala:587:51]
wire [31:0] _atomics_WIRE_1_address = 32'h0; // @[DCache.scala:587:38]
wire [31:0] nodeOut_c_bits_c_address = 32'h0; // @[Edges.scala:380:17]
wire [31:0] nodeOut_c_bits_c_1_address = 32'h0; // @[Edges.scala:396:17]
wire [31:0] _io_cpu_s2_xcpt_WIRE_paddr = 32'h0; // @[DCache.scala:933:74]
wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[DCache.scala:101:7]
wire [22:0] pma_checker_io_ptw_status_zero2 = 23'h0; // @[DCache.scala:120:32]
wire [22:0] pma_checker_io_ptw_gstatus_zero2 = 23'h0; // @[DCache.scala:120:32]
wire [39:0] io_tlb_port_req_bits_vaddr = 40'h0; // @[DCache.scala:101:7]
wire [39:0] _io_cpu_s2_xcpt_WIRE_gpa = 40'h0; // @[DCache.scala:933:74]
wire [25:0] metaArb_io_in_0_bits_data = 26'h0; // @[DCache.scala:135:28]
wire [25:0] _metaArb_io_in_0_bits_data_T = 26'h0; // @[DCache.scala:1050:85]
wire [23:0] metaArb_io_in_0_bits_data_meta_1_tag = 24'h0; // @[HellaCache.scala:305:20]
wire [3:0] _r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r_T_65 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _r_T_129 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] tl_out_a_bits_a_size = 4'h6; // @[Edges.scala:346:17]
wire [3:0] _release_state_T_13 = 4'h6; // @[DCache.scala:820:27]
wire [3:0] nodeOut_c_bits_c_size = 4'h6; // @[Edges.scala:380:17]
wire [3:0] nodeOut_c_bits_c_1_size = 4'h6; // @[Edges.scala:396:17]
wire [2:0] nodeOut_c_bits_c_1_opcode = 3'h7; // @[Edges.scala:396:17]
wire [32:0] _nodeOut_c_bits_legal_T_33 = 33'h80000000; // @[Parameters.scala:137:41]
wire [32:0] _nodeOut_c_bits_legal_T_34 = 33'h80000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_35 = 33'h80000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_73 = 33'h80000000; // @[Parameters.scala:137:41]
wire [32:0] _nodeOut_c_bits_legal_T_74 = 33'h80000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_75 = 33'h80000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_29 = 33'h8000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_30 = 33'h8000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_69 = 33'h8000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_70 = 33'h8000000; // @[Parameters.scala:137:46]
wire [28:0] _nodeOut_c_bits_legal_T_28 = 29'h8000000; // @[Parameters.scala:137:41]
wire [28:0] _nodeOut_c_bits_legal_T_68 = 29'h8000000; // @[Parameters.scala:137:41]
wire [32:0] _nodeOut_c_bits_legal_T_18 = 33'hC000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_19 = 33'hC000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_58 = 33'hC000000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_59 = 33'hC000000; // @[Parameters.scala:137:46]
wire [28:0] _nodeOut_c_bits_legal_T_17 = 29'hC000000; // @[Parameters.scala:137:41]
wire [28:0] _nodeOut_c_bits_legal_T_57 = 29'hC000000; // @[Parameters.scala:137:41]
wire [32:0] _nodeOut_c_bits_legal_T_13 = 33'h20000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_14 = 33'h20000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_53 = 33'h20000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_54 = 33'h20000; // @[Parameters.scala:137:46]
wire [18:0] _nodeOut_c_bits_legal_T_12 = 19'h20000; // @[Parameters.scala:137:41]
wire [18:0] _nodeOut_c_bits_legal_T_52 = 19'h20000; // @[Parameters.scala:137:41]
wire [32:0] _nodeOut_c_bits_legal_T_8 = 33'h10000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_9 = 33'h10000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_48 = 33'h10000; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_49 = 33'h10000; // @[Parameters.scala:137:46]
wire [17:0] _nodeOut_c_bits_legal_T_7 = 18'h10000; // @[Parameters.scala:137:41]
wire [17:0] _nodeOut_c_bits_legal_T_47 = 18'h10000; // @[Parameters.scala:137:41]
wire [32:0] _nodeOut_c_bits_legal_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_4 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_43 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _nodeOut_c_bits_legal_T_44 = 33'h0; // @[Parameters.scala:137:46]
wire [3:0] _r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _metaArb_io_in_3_bits_data_T_9 = 4'hC; // @[Metadata.scala:89:10]
wire [1:0] _r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] tl_out_a_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] tl_out_a_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] tl_out_a_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] tl_out_a_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _metaArb_io_in_3_bits_data_T_8 = 2'h3; // @[Metadata.scala:24:15]
wire [3:0] _r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_67 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _r_T_131 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _tl_out_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _metaArb_io_in_3_bits_data_T_7 = 4'h4; // @[Metadata.scala:88:10]
wire [3:0] _r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_62 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _r_T_126 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _metaArb_io_in_3_bits_data_T_3 = 4'h1; // @[Metadata.scala:86:10]
wire [4:0] _s1_data_way_T_1 = 5'h10; // @[DCache.scala:694:32]
wire [3:0] _r_T_70 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_134 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_69 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_133 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_68 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _r_T_132 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r_T_66 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_130 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_64 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_128 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_61 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_125 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_60 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_124 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [13:0] pma_checker__ae_array_T_2 = 14'h0; // @[TLB.scala:583:8]
wire [13:0] pma_checker__ae_st_array_T_7 = 14'h0; // @[TLB.scala:590:8]
wire [13:0] pma_checker__ae_st_array_T_10 = 14'h0; // @[TLB.scala:591:8]
wire [13:0] pma_checker__must_alloc_array_T_3 = 14'h0; // @[TLB.scala:594:8]
wire [13:0] pma_checker__must_alloc_array_T_6 = 14'h0; // @[TLB.scala:595:8]
wire [13:0] pma_checker__must_alloc_array_T_9 = 14'h0; // @[TLB.scala:596:8]
wire [13:0] pma_checker__gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46]
wire [13:0] pma_checker_gf_ld_array = 14'h0; // @[TLB.scala:600:24]
wire [13:0] pma_checker__gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53]
wire [13:0] pma_checker_gf_st_array = 14'h0; // @[TLB.scala:601:24]
wire [13:0] pma_checker__gf_inst_array_T = 14'h0; // @[TLB.scala:602:36]
wire [13:0] pma_checker_gf_inst_array = 14'h0; // @[TLB.scala:602:26]
wire [13:0] pma_checker_gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73]
wire [13:0] pma_checker__io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58]
wire [13:0] pma_checker__io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65]
wire [13:0] pma_checker__io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48]
wire [6:0] pma_checker_real_hits_hi = 7'h0; // @[package.scala:45:27]
wire [6:0] pma_checker__state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25]
wire [6:0] pma_checker__multipleHits_T_21 = 7'h0; // @[Misc.scala:182:39]
wire [12:0] pma_checker_real_hits = 13'h0; // @[package.scala:45:27]
wire [12:0] pma_checker__stage1_bypass_T = 13'h0; // @[TLB.scala:517:27]
wire [12:0] pma_checker_stage1_bypass = 13'h0; // @[TLB.scala:517:61]
wire [12:0] pma_checker__r_array_T_2 = 13'h0; // @[TLB.scala:520:74]
wire [12:0] pma_checker__hr_array_T_2 = 13'h0; // @[TLB.scala:524:60]
wire [12:0] pma_checker__gpa_hits_T = 13'h0; // @[TLB.scala:607:30]
wire [12:0] pma_checker__tlb_hit_T = 13'h0; // @[TLB.scala:611:28]
wire [12:0] pma_checker__stage1_bypass_T_2 = 13'h1FFF; // @[TLB.scala:517:68]
wire [12:0] pma_checker__stage1_bypass_T_4 = 13'h1FFF; // @[TLB.scala:517:95]
wire [12:0] pma_checker_stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27]
wire [12:0] pma_checker__hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111]
wire [12:0] pma_checker__hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55]
wire [12:0] pma_checker__hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55]
wire [12:0] pma_checker__gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88]
wire [12:0] pma_checker_gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82]
wire [12:0] pma_checker__gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16]
wire [12:0] pma_checker_gpa_hits = 13'h1FFF; // @[TLB.scala:607:14]
wire [13:0] pma_checker_hr_array = 14'h3FFF; // @[TLB.scala:524:21]
wire [13:0] pma_checker_hw_array = 14'h3FFF; // @[TLB.scala:525:21]
wire [13:0] pma_checker_hx_array = 14'h3FFF; // @[TLB.scala:526:21]
wire [13:0] pma_checker__must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19]
wire [13:0] pma_checker__gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50]
wire [19:0] pma_checker_refill_ppn = 20'h0; // @[TLB.scala:406:44]
wire [19:0] pma_checker_newEntry_ppn = 20'h0; // @[TLB.scala:449:24]
wire [19:0] pma_checker__ppn_T_42 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_43 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_44 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_45 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_46 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_47 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_48 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_49 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_50 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_51 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_52 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_53 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_54 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_56 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_57 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_58 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_59 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_60 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_61 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_62 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_63 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_64 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_65 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_66 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_67 = 20'h0; // @[Mux.scala:30:73]
wire [30:0] pma_checker_special_entry_data_0_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_superpage_entries_0_data_0_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_superpage_entries_1_data_0_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_superpage_entries_2_data_0_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_superpage_entries_3_data_0_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_0_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_1_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_2_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_3_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_4_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_5_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_6_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_7_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_special_entry_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_superpage_entries_0_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_superpage_entries_1_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_superpage_entries_2_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_superpage_entries_3_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_0_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_1_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_2_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_3_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_4_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_5_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_6_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_7_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_special_entry_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_special_entry_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [13:0] pma_checker_hits = 14'h2000; // @[TLB.scala:442:17]
wire [9:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_future = 10'h0; // @[DCache.scala:120:32]
wire [31:0] _nodeOut_c_bits_legal_T_32 = 32'h80000000; // @[Parameters.scala:137:31]
wire [31:0] _nodeOut_c_bits_legal_T_72 = 32'h80000000; // @[Parameters.scala:137:31]
wire [27:0] _nodeOut_c_bits_legal_T_16 = 28'hC000000; // @[Parameters.scala:137:31]
wire [27:0] _nodeOut_c_bits_legal_T_56 = 28'hC000000; // @[Parameters.scala:137:31]
wire [27:0] _nodeOut_c_bits_legal_T_27 = 28'h8000000; // @[Parameters.scala:137:31]
wire [27:0] _nodeOut_c_bits_legal_T_67 = 28'h8000000; // @[Parameters.scala:137:31]
wire [17:0] _nodeOut_c_bits_legal_T_11 = 18'h20000; // @[Parameters.scala:137:31]
wire [17:0] _nodeOut_c_bits_legal_T_51 = 18'h20000; // @[Parameters.scala:137:31]
wire [16:0] _nodeOut_c_bits_legal_T_6 = 17'h10000; // @[Parameters.scala:137:31]
wire [16:0] _nodeOut_c_bits_legal_T_46 = 17'h10000; // @[Parameters.scala:137:31]
wire [41:0] pma_checker__mpu_ppn_WIRE_1 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_1 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_3 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_5 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_7 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_9 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_11 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_13 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_15 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_17 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_19 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_21 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_23 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_25 = 42'h0; // @[TLB.scala:170:77]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[DCache.scala:101:7]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[DCache.scala:101:7]
wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[DCache.scala:101:7]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[DCache.scala:101:7]
wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[DCache.scala:101:7]
wire nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[DCache.scala:101:7]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[DCache.scala:101:7]
wire [7:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[DCache.scala:101:7]
wire [63:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[DCache.scala:101:7]
wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[DCache.scala:101:7]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[DCache.scala:101:7]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[DCache.scala:101:7]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[DCache.scala:101:7]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[DCache.scala:101:7]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[DCache.scala:101:7]
wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[DCache.scala:101:7]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[DCache.scala:101:7]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[DCache.scala:101:7]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[DCache.scala:101:7]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[DCache.scala:101:7]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[DCache.scala:101:7]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire metaArb_io_in_7_valid = io_cpu_req_valid_0; // @[DCache.scala:101:7, :135:28]
wire _dataArb_io_in_3_valid_T_58 = io_cpu_req_valid_0; // @[DCache.scala:101:7, :242:46]
wire _s1_did_read_T_53 = io_cpu_req_valid_0; // @[DCache.scala:101:7, :259:75]
wire _pstore_drain_opportunistic_T_58 = io_cpu_req_valid_0; // @[DCache.scala:101:7, :502:55]
wire [39:0] metaArb_io_in_7_bits_addr = io_cpu_req_bits_addr_0; // @[DCache.scala:101:7, :135:28]
wire [7:0] s0_req_tag = io_cpu_req_bits_tag_0; // @[DCache.scala:101:7, :192:24]
wire [1:0] s0_req_size = io_cpu_req_bits_size_0; // @[DCache.scala:101:7, :192:24]
wire [1:0] s0_req_dprv = io_cpu_req_bits_dprv_0; // @[DCache.scala:101:7, :192:24]
wire s0_req_dv = io_cpu_req_bits_dv_0; // @[DCache.scala:101:7, :192:24]
wire _io_cpu_s2_nack_T_5; // @[DCache.scala:445:86]
wire _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:574:54]
wire _io_cpu_s2_uncached_T_1; // @[DCache.scala:920:37]
wire _io_cpu_resp_valid_T_2; // @[DCache.scala:949:70]
wire [63:0] _io_cpu_resp_bits_data_T_24; // @[DCache.scala:974:41]
wire s2_read; // @[Consts.scala:89:68]
wire [63:0] _io_cpu_resp_bits_data_word_bypass_T_7; // @[AMOALU.scala:45:16]
wire [63:0] s2_data_word; // @[DCache.scala:970:80]
wire _io_cpu_replay_next_T_3; // @[DCache.scala:950:62]
wire _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:933:24]
wire _io_cpu_ordered_T_8; // @[DCache.scala:929:21]
wire _io_cpu_store_pending_T_25; // @[DCache.scala:930:70]
wire io_cpu_perf_acquire_done; // @[Edges.scala:233:22]
wire io_cpu_perf_release_done; // @[Edges.scala:233:22]
wire _io_cpu_perf_grant_T; // @[DCache.scala:1078:39]
wire _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35]
wire _io_cpu_perf_blocked_T_1; // @[DCache.scala:1106:23]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_10; // @[DCache.scala:1088:41]
wire _io_cpu_perf_canAcceptStoreThenRMW_T_1; // @[DCache.scala:1091:75]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_61; // @[DCache.scala:1092:40]
wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_7; // @[DCache.scala:1080:44]
wire _io_cpu_perf_storeBufferEmptyAfterStore_T_10; // @[DCache.scala:1084:45]
wire _io_errors_bus_valid_T_2; // @[DCache.scala:1129:42]
wire [2:0] auto_out_a_bits_opcode_0; // @[DCache.scala:101:7]
wire [2:0] auto_out_a_bits_param_0; // @[DCache.scala:101:7]
wire [3:0] auto_out_a_bits_size_0; // @[DCache.scala:101:7]
wire auto_out_a_bits_source_0; // @[DCache.scala:101:7]
wire [31:0] auto_out_a_bits_address_0; // @[DCache.scala:101:7]
wire [7:0] auto_out_a_bits_mask_0; // @[DCache.scala:101:7]
wire [63:0] auto_out_a_bits_data_0; // @[DCache.scala:101:7]
wire auto_out_a_valid_0; // @[DCache.scala:101:7]
wire auto_out_b_ready_0; // @[DCache.scala:101:7]
wire [2:0] auto_out_c_bits_opcode_0; // @[DCache.scala:101:7]
wire [2:0] auto_out_c_bits_param_0; // @[DCache.scala:101:7]
wire [3:0] auto_out_c_bits_size_0; // @[DCache.scala:101:7]
wire auto_out_c_bits_source_0; // @[DCache.scala:101:7]
wire [31:0] auto_out_c_bits_address_0; // @[DCache.scala:101:7]
wire [63:0] auto_out_c_bits_data_0; // @[DCache.scala:101:7]
wire auto_out_c_valid_0; // @[DCache.scala:101:7]
wire auto_out_d_ready_0; // @[DCache.scala:101:7]
wire [2:0] auto_out_e_bits_sink_0; // @[DCache.scala:101:7]
wire auto_out_e_valid_0; // @[DCache.scala:101:7]
wire io_cpu_req_ready_0; // @[DCache.scala:101:7]
wire [39:0] io_cpu_resp_bits_addr_0; // @[DCache.scala:101:7]
wire [7:0] io_cpu_resp_bits_tag_0; // @[DCache.scala:101:7]
wire [4:0] io_cpu_resp_bits_cmd_0; // @[DCache.scala:101:7]
wire [1:0] io_cpu_resp_bits_size_0; // @[DCache.scala:101:7]
wire io_cpu_resp_bits_signed_0; // @[DCache.scala:101:7]
wire [1:0] io_cpu_resp_bits_dprv_0; // @[DCache.scala:101:7]
wire io_cpu_resp_bits_dv_0; // @[DCache.scala:101:7]
wire [63:0] io_cpu_resp_bits_data_0; // @[DCache.scala:101:7]
wire [7:0] io_cpu_resp_bits_mask_0; // @[DCache.scala:101:7]
wire io_cpu_resp_bits_replay_0; // @[DCache.scala:101:7]
wire io_cpu_resp_bits_has_data_0; // @[DCache.scala:101:7]
wire [63:0] io_cpu_resp_bits_data_word_bypass_0; // @[DCache.scala:101:7]
wire [63:0] io_cpu_resp_bits_data_raw_0; // @[DCache.scala:101:7]
wire [63:0] io_cpu_resp_bits_store_data_0; // @[DCache.scala:101:7]
wire io_cpu_resp_valid_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_ma_ld_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_ma_st_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_pf_ld_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_pf_st_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_ae_ld_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_ae_st_0; // @[DCache.scala:101:7]
wire io_cpu_perf_acquire_0; // @[DCache.scala:101:7]
wire io_cpu_perf_release_0; // @[DCache.scala:101:7]
wire io_cpu_perf_grant_0; // @[DCache.scala:101:7]
wire io_cpu_perf_tlbMiss_0; // @[DCache.scala:101:7]
wire io_cpu_perf_blocked_0; // @[DCache.scala:101:7]
wire io_cpu_perf_canAcceptStoreThenLoad_0; // @[DCache.scala:101:7]
wire io_cpu_perf_canAcceptStoreThenRMW_0; // @[DCache.scala:101:7]
wire io_cpu_perf_canAcceptLoadThenLoad_0; // @[DCache.scala:101:7]
wire io_cpu_perf_storeBufferEmptyAfterLoad_0; // @[DCache.scala:101:7]
wire io_cpu_perf_storeBufferEmptyAfterStore_0; // @[DCache.scala:101:7]
wire io_cpu_s2_nack_0; // @[DCache.scala:101:7]
wire io_cpu_s2_nack_cause_raw_0; // @[DCache.scala:101:7]
wire io_cpu_s2_uncached_0; // @[DCache.scala:101:7]
wire [31:0] io_cpu_s2_paddr_0; // @[DCache.scala:101:7]
wire io_cpu_replay_next_0; // @[DCache.scala:101:7]
wire [39:0] io_cpu_s2_gpa_0; // @[DCache.scala:101:7]
wire io_cpu_ordered_0; // @[DCache.scala:101:7]
wire io_cpu_store_pending_0; // @[DCache.scala:101:7]
wire [26:0] io_ptw_req_bits_bits_addr_0; // @[DCache.scala:101:7]
wire io_ptw_req_bits_bits_need_gpa_0; // @[DCache.scala:101:7]
wire io_ptw_req_valid_0; // @[DCache.scala:101:7]
wire io_errors_bus_valid; // @[DCache.scala:101:7]
wire [31:0] io_errors_bus_bits; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_pf_ld; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_pf_st; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_pf_inst; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ae_ld; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ae_st; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ae_inst; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ma_ld; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ma_st; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_miss; // @[DCache.scala:101:7]
wire [31:0] io_tlb_port_s1_resp_paddr; // @[DCache.scala:101:7]
wire [39:0] io_tlb_port_s1_resp_gpa; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_cacheable; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_must_alloc; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_prefetchable; // @[DCache.scala:101:7]
wire [1:0] io_tlb_port_s1_resp_size; // @[DCache.scala:101:7]
wire [4:0] io_tlb_port_s1_resp_cmd; // @[DCache.scala:101:7]
wire nodeOut_a_deq_ready = nodeOut_a_ready; // @[Decoupled.scala:356:21]
wire nodeOut_a_deq_valid; // @[Decoupled.scala:356:21]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[DCache.scala:101:7]
wire [2:0] nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[DCache.scala:101:7]
wire [2:0] nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[DCache.scala:101:7]
wire [3:0] nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[DCache.scala:101:7]
wire nodeOut_a_deq_bits_source; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[DCache.scala:101:7]
wire [31:0] nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[DCache.scala:101:7]
wire [7:0] nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[DCache.scala:101:7]
wire [63:0] nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[DCache.scala:101:7]
wire _nodeOut_b_ready_T_4; // @[DCache.scala:770:44]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[DCache.scala:101:7]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[DCache.scala:101:7]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[DCache.scala:101:7]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[DCache.scala:101:7]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[DCache.scala:101:7]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[DCache.scala:101:7]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[DCache.scala:101:7]
wire [63:0] s2_data_corrected; // @[package.scala:45:27]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[DCache.scala:101:7]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[DCache.scala:101:7]
wire uncachedRespIdxOH_shiftAmount = nodeOut_d_bits_source; // @[OneHot.scala:64:49]
wire [2:0] nodeOut_e_bits_e_sink = nodeOut_d_bits_sink; // @[Edges.scala:451:17]
wire [63:0] s1_uncached_data_word = nodeOut_d_bits_data; // @[package.scala:211:50]
wire _tl_d_data_encoded_T_10 = nodeOut_d_bits_corrupt; // @[DCache.scala:663:77]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[DCache.scala:101:7]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[DCache.scala:101:7]
wire [1:0] pma_checker_io_resp_size = pma_checker_io_req_bits_size; // @[DCache.scala:120:32]
wire [4:0] pma_checker_io_resp_cmd = pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32]
wire [31:0] pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23]
wire [39:0] pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8]
wire pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41]
wire pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48]
wire pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29]
wire pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41]
wire pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41]
wire pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41]
wire pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31]
wire pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31]
wire pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41]
wire pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51]
wire pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59]
wire [39:0] pma_checker_io_req_bits_vaddr; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_req_bits_prv; // @[DCache.scala:120:32]
wire pma_checker_io_req_bits_v; // @[DCache.scala:120:32]
wire pma_checker_io_resp_pf_ld; // @[DCache.scala:120:32]
wire pma_checker_io_resp_pf_st; // @[DCache.scala:120:32]
wire pma_checker_io_resp_pf_inst; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ae_ld; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ae_st; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ae_inst; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ma_ld; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ma_st; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_resp_paddr; // @[DCache.scala:120:32]
wire [39:0] pma_checker_io_resp_gpa; // @[DCache.scala:120:32]
wire pma_checker_io_resp_cacheable; // @[DCache.scala:120:32]
wire pma_checker_io_resp_must_alloc; // @[DCache.scala:120:32]
wire pma_checker_io_resp_prefetchable; // @[DCache.scala:120:32]
wire [26:0] pma_checker_vpn = pma_checker_io_req_bits_vaddr[38:12]; // @[TLB.scala:335:30]
wire [26:0] pma_checker__mpu_ppn_T_24 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] pma_checker__mpu_ppn_T_28 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] pma_checker__sector_hits_T_3 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__sector_hits_T_11 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__sector_hits_T_19 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__sector_hits_T_27 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__sector_hits_T_35 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__sector_hits_T_43 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__sector_hits_T_51 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__sector_hits_T_59 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__superpage_hits_T = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_5 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_10 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_14 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_19 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_24 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_28 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_33 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_38 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_42 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_47 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__superpage_hits_T_52 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__hitsVec_T_6 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__hitsVec_T_12 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__hitsVec_T_18 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__hitsVec_T_24 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__hitsVec_T_30 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__hitsVec_T_36 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__hitsVec_T_42 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [26:0] pma_checker__hitsVec_T_48 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_53 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_58 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_63 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_68 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_73 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_78 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_83 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_88 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_93 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_98 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_103 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_108 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_113 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__hitsVec_T_118 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30]
wire [26:0] pma_checker__ppn_T_5 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] pma_checker__ppn_T_13 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] pma_checker__ppn_T_21 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] pma_checker__ppn_T_29 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] pma_checker__ppn_T_33 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] pma_checker__ppn_T_37 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30]
wire pma_checker_priv_s = pma_checker_io_req_bits_prv[0]; // @[TLB.scala:370:20]
wire pma_checker_priv_uses_vm = ~(pma_checker_io_req_bits_prv[1]); // @[TLB.scala:372:27]
wire [19:0] pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_1 = pma_checker__mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_fragmented_superpage = pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_2 = pma_checker__mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_c = pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_3 = pma_checker__mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_eff = pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_4 = pma_checker__mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_paa = pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_5 = pma_checker__mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_pal = pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_6 = pma_checker__mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_ppp = pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_7 = pma_checker__mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_pr = pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_8 = pma_checker__mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_px = pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_9 = pma_checker__mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_pw = pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_10 = pma_checker__mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_hr = pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_11 = pma_checker__mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_hx = pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_12 = pma_checker__mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_hw = pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_13 = pma_checker__mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_sr = pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_14 = pma_checker__mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_sx = pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_15 = pma_checker__mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_sw = pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_16 = pma_checker__mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_gf = pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_17 = pma_checker__mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_pf = pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_18 = pma_checker__mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_ae_stage2 = pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_19 = pma_checker__mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_ae_final = pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_20 = pma_checker__mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_ae_ptw = pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_21 = pma_checker__mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_g = pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_22 = pma_checker__mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_u = pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_23 = pma_checker__mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__mpu_ppn_WIRE_ppn = pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77]
wire [1:0] pma_checker_mpu_ppn_res = _pma_checker_mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25]
wire [26:0] pma_checker__mpu_ppn_T_25 = {pma_checker__mpu_ppn_T_24[26:20], pma_checker__mpu_ppn_T_24[19:0] | _pma_checker_mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__mpu_ppn_T_26 = pma_checker__mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] pma_checker__mpu_ppn_T_27 = {pma_checker_mpu_ppn_res, pma_checker__mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}]
wire [26:0] pma_checker__mpu_ppn_T_29 = {pma_checker__mpu_ppn_T_28[26:20], pma_checker__mpu_ppn_T_28[19:0] | _pma_checker_mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__mpu_ppn_T_30 = pma_checker__mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] pma_checker__mpu_ppn_T_31 = {pma_checker__mpu_ppn_T_27, pma_checker__mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}]
wire [27:0] pma_checker__mpu_ppn_T_32 = pma_checker_io_req_bits_vaddr[39:12]; // @[TLB.scala:413:146]
wire [27:0] pma_checker__mpu_ppn_T_33 = pma_checker__mpu_ppn_T_32; // @[TLB.scala:413:{20,146}]
wire [27:0] pma_checker_mpu_ppn = pma_checker__mpu_ppn_T_33; // @[TLB.scala:412:20, :413:20]
wire [11:0] pma_checker__mpu_physaddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52]
wire [11:0] pma_checker__io_resp_paddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :652:46]
wire [11:0] pma_checker__io_resp_gpa_offset_T_1 = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :658:82]
wire [39:0] pma_checker_mpu_physaddr = {pma_checker_mpu_ppn, pma_checker__mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}]
wire [39:0] pma_checker__homogeneous_T = pma_checker_mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] pma_checker__homogeneous_T_79 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] pma_checker__deny_access_to_debug_T_1 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25]
wire [2:0] pma_checker__mpu_priv_T_2 = {1'h0, pma_checker_io_req_bits_prv}; // @[TLB.scala:415:103]
wire pma_checker_cacheable; // @[TLB.scala:425:41]
wire pma_checker_newEntry_c = pma_checker_cacheable; // @[TLB.scala:425:41, :449:24]
wire [40:0] pma_checker__homogeneous_T_1 = {1'h0, pma_checker__homogeneous_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_2 = pma_checker__homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_3 = pma_checker__homogeneous_T_2; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_4 = pma_checker__homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_60 = pma_checker__homogeneous_T_4; // @[TLBPermissions.scala:101:65]
wire [39:0] _GEN = {pma_checker_mpu_physaddr[39:14], pma_checker_mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25]
wire [39:0] pma_checker__homogeneous_T_5; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_5 = _GEN; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_84; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_84 = _GEN; // @[Parameters.scala:137:31]
wire [40:0] pma_checker__homogeneous_T_6 = {1'h0, pma_checker__homogeneous_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_7 = pma_checker__homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_8 = pma_checker__homogeneous_T_7; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_9 = pma_checker__homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_0 = {pma_checker_mpu_physaddr[39:17], pma_checker_mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25]
wire [39:0] pma_checker__homogeneous_T_10; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_10 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_72; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_89; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_89 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_121; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_121 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_128; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_128 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] pma_checker__homogeneous_T_11 = {1'h0, pma_checker__homogeneous_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_12 = pma_checker__homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_13 = pma_checker__homogeneous_T_12; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_14 = pma_checker__homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] pma_checker__homogeneous_T_15 = {pma_checker_mpu_physaddr[39:18], pma_checker_mpu_physaddr[17:0] ^ 18'h20000}; // @[TLB.scala:414:25]
wire [40:0] pma_checker__homogeneous_T_16 = {1'h0, pma_checker__homogeneous_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_17 = pma_checker__homogeneous_T_16 & 41'h1FFFFFFC000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_18 = pma_checker__homogeneous_T_17; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_19 = pma_checker__homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] pma_checker__homogeneous_T_20 = {pma_checker_mpu_physaddr[39:18], pma_checker_mpu_physaddr[17:0] ^ 18'h24000}; // @[TLB.scala:414:25]
wire [40:0] pma_checker__homogeneous_T_21 = {1'h0, pma_checker__homogeneous_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_22 = pma_checker__homogeneous_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_23 = pma_checker__homogeneous_T_22; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_24 = pma_checker__homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] pma_checker__homogeneous_T_25 = {pma_checker_mpu_physaddr[39:21], pma_checker_mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25]
wire [40:0] pma_checker__homogeneous_T_26 = {1'h0, pma_checker__homogeneous_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_27 = pma_checker__homogeneous_T_26 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_28 = pma_checker__homogeneous_T_27; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_29 = pma_checker__homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] pma_checker__homogeneous_T_30 = {pma_checker_mpu_physaddr[39:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25]
wire [40:0] pma_checker__homogeneous_T_31 = {1'h0, pma_checker__homogeneous_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_32 = pma_checker__homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_33 = pma_checker__homogeneous_T_32; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_34 = pma_checker__homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] pma_checker__homogeneous_T_35 = {pma_checker_mpu_physaddr[39:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25]
wire [40:0] pma_checker__homogeneous_T_36 = {1'h0, pma_checker__homogeneous_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_37 = pma_checker__homogeneous_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_38 = pma_checker__homogeneous_T_37; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_39 = pma_checker__homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_1 = {pma_checker_mpu_physaddr[39:28], pma_checker_mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25]
wire [39:0] pma_checker__homogeneous_T_40; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_40 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_94; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_94 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_109; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] pma_checker__homogeneous_T_41 = {1'h0, pma_checker__homogeneous_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_42 = pma_checker__homogeneous_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_43 = pma_checker__homogeneous_T_42; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_44 = pma_checker__homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] pma_checker__homogeneous_T_45 = {pma_checker_mpu_physaddr[39:28], pma_checker_mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25]
wire [40:0] pma_checker__homogeneous_T_46 = {1'h0, pma_checker__homogeneous_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_47 = pma_checker__homogeneous_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_48 = pma_checker__homogeneous_T_47; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_49 = pma_checker__homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] pma_checker__homogeneous_T_50 = {pma_checker_mpu_physaddr[39:29], pma_checker_mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25]
wire [40:0] pma_checker__homogeneous_T_51 = {1'h0, pma_checker__homogeneous_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_52 = pma_checker__homogeneous_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_53 = pma_checker__homogeneous_T_52; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_54 = pma_checker__homogeneous_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_2 = {pma_checker_mpu_physaddr[39:32], pma_checker_mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15]
wire [39:0] pma_checker__homogeneous_T_55; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_55 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_99; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_99 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] pma_checker__homogeneous_T_114; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_114 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] pma_checker__homogeneous_T_56 = {1'h0, pma_checker__homogeneous_T_55}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_57 = pma_checker__homogeneous_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_58 = pma_checker__homogeneous_T_57; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_59 = pma_checker__homogeneous_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_61 = pma_checker__homogeneous_T_60 | pma_checker__homogeneous_T_9; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_62 = pma_checker__homogeneous_T_61 | pma_checker__homogeneous_T_14; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_63 = pma_checker__homogeneous_T_62 | pma_checker__homogeneous_T_19; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_64 = pma_checker__homogeneous_T_63 | pma_checker__homogeneous_T_24; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_65 = pma_checker__homogeneous_T_64 | pma_checker__homogeneous_T_29; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_66 = pma_checker__homogeneous_T_65 | pma_checker__homogeneous_T_34; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_67 = pma_checker__homogeneous_T_66 | pma_checker__homogeneous_T_39; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_68 = pma_checker__homogeneous_T_67 | pma_checker__homogeneous_T_44; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_69 = pma_checker__homogeneous_T_68 | pma_checker__homogeneous_T_49; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_70 = pma_checker__homogeneous_T_69 | pma_checker__homogeneous_T_54; // @[TLBPermissions.scala:101:65]
wire pma_checker_homogeneous = pma_checker__homogeneous_T_70 | pma_checker__homogeneous_T_59; // @[TLBPermissions.scala:101:65]
wire [40:0] pma_checker__homogeneous_T_73 = {1'h0, pma_checker__homogeneous_T_72}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_74 = pma_checker__homogeneous_T_73 & 41'h8A130000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_75 = pma_checker__homogeneous_T_74; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_76 = pma_checker__homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_77 = pma_checker__homogeneous_T_76; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_78 = ~pma_checker__homogeneous_T_77; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] pma_checker__homogeneous_T_80 = {1'h0, pma_checker__homogeneous_T_79}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_81 = pma_checker__homogeneous_T_80 & 41'hFFFF3000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_82 = pma_checker__homogeneous_T_81; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_83 = pma_checker__homogeneous_T_82 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_104 = pma_checker__homogeneous_T_83; // @[TLBPermissions.scala:85:66]
wire [40:0] pma_checker__homogeneous_T_85 = {1'h0, pma_checker__homogeneous_T_84}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_86 = pma_checker__homogeneous_T_85 & 41'hFFFF3000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_87 = pma_checker__homogeneous_T_86; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_88 = pma_checker__homogeneous_T_87 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] pma_checker__homogeneous_T_90 = {1'h0, pma_checker__homogeneous_T_89}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_91 = pma_checker__homogeneous_T_90 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_92 = pma_checker__homogeneous_T_91; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_93 = pma_checker__homogeneous_T_92 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] pma_checker__homogeneous_T_95 = {1'h0, pma_checker__homogeneous_T_94}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_96 = pma_checker__homogeneous_T_95 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_97 = pma_checker__homogeneous_T_96; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_98 = pma_checker__homogeneous_T_97 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] pma_checker__homogeneous_T_100 = {1'h0, pma_checker__homogeneous_T_99}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_101 = pma_checker__homogeneous_T_100 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_102 = pma_checker__homogeneous_T_101; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_103 = pma_checker__homogeneous_T_102 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_105 = pma_checker__homogeneous_T_104 | pma_checker__homogeneous_T_88; // @[TLBPermissions.scala:85:66]
wire pma_checker__homogeneous_T_106 = pma_checker__homogeneous_T_105 | pma_checker__homogeneous_T_93; // @[TLBPermissions.scala:85:66]
wire pma_checker__homogeneous_T_107 = pma_checker__homogeneous_T_106 | pma_checker__homogeneous_T_98; // @[TLBPermissions.scala:85:66]
wire pma_checker__homogeneous_T_108 = pma_checker__homogeneous_T_107 | pma_checker__homogeneous_T_103; // @[TLBPermissions.scala:85:66]
wire [40:0] pma_checker__homogeneous_T_110 = {1'h0, pma_checker__homogeneous_T_109}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_111 = pma_checker__homogeneous_T_110 & 41'h8E020000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_112 = pma_checker__homogeneous_T_111; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_113 = pma_checker__homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_119 = pma_checker__homogeneous_T_113; // @[TLBPermissions.scala:85:66]
wire [40:0] pma_checker__homogeneous_T_115 = {1'h0, pma_checker__homogeneous_T_114}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_116 = pma_checker__homogeneous_T_115 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_117 = pma_checker__homogeneous_T_116; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_118 = pma_checker__homogeneous_T_117 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_120 = pma_checker__homogeneous_T_119 | pma_checker__homogeneous_T_118; // @[TLBPermissions.scala:85:66]
wire [40:0] pma_checker__homogeneous_T_122 = {1'h0, pma_checker__homogeneous_T_121}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_123 = pma_checker__homogeneous_T_122 & 41'h8A130000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_124 = pma_checker__homogeneous_T_123; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_125 = pma_checker__homogeneous_T_124 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_126 = pma_checker__homogeneous_T_125; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_127 = ~pma_checker__homogeneous_T_126; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] pma_checker__homogeneous_T_129 = {1'h0, pma_checker__homogeneous_T_128}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__homogeneous_T_130 = pma_checker__homogeneous_T_129 & 41'h8A130000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__homogeneous_T_131 = pma_checker__homogeneous_T_130; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_132 = pma_checker__homogeneous_T_131 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_133 = pma_checker__homogeneous_T_132; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_134 = ~pma_checker__homogeneous_T_133; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] pma_checker__deny_access_to_debug_T_2 = {1'h0, pma_checker__deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}]
wire [40:0] pma_checker__deny_access_to_debug_T_3 = pma_checker__deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] pma_checker__deny_access_to_debug_T_4 = pma_checker__deny_access_to_debug_T_3; // @[Parameters.scala:137:46]
wire pma_checker__deny_access_to_debug_T_5 = pma_checker__deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker_deny_access_to_debug = pma_checker__deny_access_to_debug_T_5; // @[TLB.scala:428:50]
wire pma_checker__prot_r_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33]
wire pma_checker__prot_r_T_1 = _pma_checker_pma_io_resp_r & pma_checker__prot_r_T; // @[TLB.scala:422:19, :429:{30,33}]
wire pma_checker_prot_r = pma_checker__prot_r_T_1; // @[TLB.scala:429:{30,55}]
wire pma_checker_newEntry_pr = pma_checker_prot_r; // @[TLB.scala:429:55, :449:24]
wire pma_checker__prot_w_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33]
wire pma_checker__prot_w_T_1 = _pma_checker_pma_io_resp_w & pma_checker__prot_w_T; // @[TLB.scala:422:19, :430:{30,33}]
wire pma_checker_prot_w = pma_checker__prot_w_T_1; // @[TLB.scala:430:{30,55}]
wire pma_checker_newEntry_pw = pma_checker_prot_w; // @[TLB.scala:430:55, :449:24]
wire pma_checker__prot_x_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33]
wire pma_checker__prot_x_T_1 = _pma_checker_pma_io_resp_x & pma_checker__prot_x_T; // @[TLB.scala:422:19, :434:{30,33}]
wire pma_checker_prot_x = pma_checker__prot_x_T_1; // @[TLB.scala:434:{30,55}]
wire pma_checker_newEntry_px = pma_checker_prot_x; // @[TLB.scala:434:55, :449:24]
wire [24:0] pma_checker__sector_hits_T_4 = pma_checker__sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_5 = pma_checker__sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_7 = pma_checker__sector_hits_T_5 & pma_checker__sector_hits_T_6; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__sector_hits_T_12 = pma_checker__sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_13 = pma_checker__sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_15 = pma_checker__sector_hits_T_13 & pma_checker__sector_hits_T_14; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__sector_hits_T_20 = pma_checker__sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_21 = pma_checker__sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_23 = pma_checker__sector_hits_T_21 & pma_checker__sector_hits_T_22; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__sector_hits_T_28 = pma_checker__sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_29 = pma_checker__sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_31 = pma_checker__sector_hits_T_29 & pma_checker__sector_hits_T_30; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__sector_hits_T_36 = pma_checker__sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_37 = pma_checker__sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_39 = pma_checker__sector_hits_T_37 & pma_checker__sector_hits_T_38; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__sector_hits_T_44 = pma_checker__sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_45 = pma_checker__sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_47 = pma_checker__sector_hits_T_45 & pma_checker__sector_hits_T_46; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__sector_hits_T_52 = pma_checker__sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_53 = pma_checker__sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_55 = pma_checker__sector_hits_T_53 & pma_checker__sector_hits_T_54; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__sector_hits_T_60 = pma_checker__sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_61 = pma_checker__sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_63 = pma_checker__sector_hits_T_61 & pma_checker__sector_hits_T_62; // @[TLB.scala:174:{86,95,105}]
wire [8:0] pma_checker__superpage_hits_T_1 = pma_checker__superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_2 = pma_checker__superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__superpage_hits_T_3 = pma_checker__superpage_hits_T_2; // @[TLB.scala:183:{40,79}]
wire pma_checker_superpage_hits_ignore_1 = pma_checker__superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] pma_checker__superpage_hits_T_6 = pma_checker__superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_7 = pma_checker__superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__superpage_hits_T_8 = pma_checker_superpage_hits_ignore_1 | pma_checker__superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}]
wire [8:0] pma_checker__superpage_hits_T_11 = pma_checker__superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_12 = pma_checker__superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [8:0] pma_checker__superpage_hits_T_15 = pma_checker__superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_16 = pma_checker__superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__superpage_hits_T_17 = pma_checker__superpage_hits_T_16; // @[TLB.scala:183:{40,79}]
wire pma_checker_superpage_hits_ignore_4 = pma_checker__superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] pma_checker__superpage_hits_T_20 = pma_checker__superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_21 = pma_checker__superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__superpage_hits_T_22 = pma_checker_superpage_hits_ignore_4 | pma_checker__superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}]
wire [8:0] pma_checker__superpage_hits_T_25 = pma_checker__superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_26 = pma_checker__superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [8:0] pma_checker__superpage_hits_T_29 = pma_checker__superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_30 = pma_checker__superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__superpage_hits_T_31 = pma_checker__superpage_hits_T_30; // @[TLB.scala:183:{40,79}]
wire pma_checker_superpage_hits_ignore_7 = pma_checker__superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}]
wire [8:0] pma_checker__superpage_hits_T_34 = pma_checker__superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_35 = pma_checker__superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__superpage_hits_T_36 = pma_checker_superpage_hits_ignore_7 | pma_checker__superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}]
wire [8:0] pma_checker__superpage_hits_T_39 = pma_checker__superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_40 = pma_checker__superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [8:0] pma_checker__superpage_hits_T_43 = pma_checker__superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_44 = pma_checker__superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__superpage_hits_T_45 = pma_checker__superpage_hits_T_44; // @[TLB.scala:183:{40,79}]
wire pma_checker_superpage_hits_ignore_10 = pma_checker__superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}]
wire [8:0] pma_checker__superpage_hits_T_48 = pma_checker__superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_49 = pma_checker__superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__superpage_hits_T_50 = pma_checker_superpage_hits_ignore_10 | pma_checker__superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}]
wire [8:0] pma_checker__superpage_hits_T_53 = pma_checker__superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__superpage_hits_T_54 = pma_checker__superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [1:0] pma_checker_hitsVec_idx = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_1 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_2 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_3 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_4 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_5 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_6 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_7 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_24 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_48 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_72 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_96 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_120 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_144 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_168 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [24:0] pma_checker__hitsVec_T_1 = pma_checker__hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_2 = pma_checker__hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_4 = pma_checker__hitsVec_T_2 & pma_checker__hitsVec_T_3; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__hitsVec_T_7 = pma_checker__hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_8 = pma_checker__hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_10 = pma_checker__hitsVec_T_8 & pma_checker__hitsVec_T_9; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__hitsVec_T_13 = pma_checker__hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_14 = pma_checker__hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_16 = pma_checker__hitsVec_T_14 & pma_checker__hitsVec_T_15; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__hitsVec_T_19 = pma_checker__hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_20 = pma_checker__hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_22 = pma_checker__hitsVec_T_20 & pma_checker__hitsVec_T_21; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__hitsVec_T_25 = pma_checker__hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_26 = pma_checker__hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_28 = pma_checker__hitsVec_T_26 & pma_checker__hitsVec_T_27; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__hitsVec_T_31 = pma_checker__hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_32 = pma_checker__hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_34 = pma_checker__hitsVec_T_32 & pma_checker__hitsVec_T_33; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__hitsVec_T_37 = pma_checker__hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_38 = pma_checker__hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_40 = pma_checker__hitsVec_T_38 & pma_checker__hitsVec_T_39; // @[TLB.scala:174:{86,95,105}]
wire [24:0] pma_checker__hitsVec_T_43 = pma_checker__hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_44 = pma_checker__hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_46 = pma_checker__hitsVec_T_44 & pma_checker__hitsVec_T_45; // @[TLB.scala:174:{86,95,105}]
wire [8:0] pma_checker__hitsVec_T_49 = pma_checker__hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_50 = pma_checker__hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_51 = pma_checker__hitsVec_T_50; // @[TLB.scala:183:{40,79}]
wire pma_checker_hitsVec_ignore_1 = pma_checker__hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] pma_checker__hitsVec_T_54 = pma_checker__hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_55 = pma_checker__hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_56 = pma_checker_hitsVec_ignore_1 | pma_checker__hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}]
wire [8:0] pma_checker__hitsVec_T_59 = pma_checker__hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_60 = pma_checker__hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [8:0] pma_checker__hitsVec_T_64 = pma_checker__hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_65 = pma_checker__hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_66 = pma_checker__hitsVec_T_65; // @[TLB.scala:183:{40,79}]
wire pma_checker_hitsVec_ignore_4 = pma_checker__hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] pma_checker__hitsVec_T_69 = pma_checker__hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_70 = pma_checker__hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_71 = pma_checker_hitsVec_ignore_4 | pma_checker__hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}]
wire [8:0] pma_checker__hitsVec_T_74 = pma_checker__hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_75 = pma_checker__hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [8:0] pma_checker__hitsVec_T_79 = pma_checker__hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_80 = pma_checker__hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_81 = pma_checker__hitsVec_T_80; // @[TLB.scala:183:{40,79}]
wire pma_checker_hitsVec_ignore_7 = pma_checker__hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}]
wire [8:0] pma_checker__hitsVec_T_84 = pma_checker__hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_85 = pma_checker__hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_86 = pma_checker_hitsVec_ignore_7 | pma_checker__hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}]
wire [8:0] pma_checker__hitsVec_T_89 = pma_checker__hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_90 = pma_checker__hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [8:0] pma_checker__hitsVec_T_94 = pma_checker__hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_95 = pma_checker__hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_96 = pma_checker__hitsVec_T_95; // @[TLB.scala:183:{40,79}]
wire pma_checker_hitsVec_ignore_10 = pma_checker__hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}]
wire [8:0] pma_checker__hitsVec_T_99 = pma_checker__hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_100 = pma_checker__hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_101 = pma_checker_hitsVec_ignore_10 | pma_checker__hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}]
wire [8:0] pma_checker__hitsVec_T_104 = pma_checker__hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_105 = pma_checker__hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [8:0] pma_checker__hitsVec_T_109 = pma_checker__hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_110 = pma_checker__hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker__hitsVec_T_111 = pma_checker__hitsVec_T_110; // @[TLB.scala:183:{40,79}]
wire [8:0] pma_checker__hitsVec_T_114 = pma_checker__hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_115 = pma_checker__hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [8:0] pma_checker__hitsVec_T_119 = pma_checker__hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}]
wire pma_checker__hitsVec_T_120 = pma_checker__hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}]
wire pma_checker_newEntry_ppp; // @[TLB.scala:449:24]
wire pma_checker_newEntry_pal; // @[TLB.scala:449:24]
wire pma_checker_newEntry_paa; // @[TLB.scala:449:24]
wire pma_checker_newEntry_eff; // @[TLB.scala:449:24]
wire [1:0] _GEN_3 = {pma_checker_newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24]
wire [1:0] pma_checker_special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign pma_checker_special_entry_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_0_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_1_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_2_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_3_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_0_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_1_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_2_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_3_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_4_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_5_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_6_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_7_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] _GEN_4 = {pma_checker_newEntry_pal, pma_checker_newEntry_paa}; // @[TLB.scala:217:24, :449:24]
wire [1:0] pma_checker_special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_special_entry_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24]
wire [2:0] pma_checker_special_entry_data_0_lo_lo_hi = {pma_checker_special_entry_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_special_entry_data_0_lo_lo = {pma_checker_special_entry_data_0_lo_lo_hi, pma_checker_special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_5 = {pma_checker_newEntry_px, pma_checker_newEntry_pr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] pma_checker_special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_special_entry_data_0_lo_hi_lo_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_5; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_5; // @[TLB.scala:217:24]
wire [2:0] pma_checker_special_entry_data_0_lo_hi_lo = {pma_checker_special_entry_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] _GEN_6 = {2'h0, pma_checker_newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] pma_checker_special_entry_data_0_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_special_entry_data_0_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_0_data_0_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_1_data_0_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_2_data_0_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_3_data_0_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_0_data_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_1_data_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_2_data_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_3_data_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_4_data_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_5_data_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_6_data_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_7_data_lo_hi_hi = _GEN_6; // @[TLB.scala:217:24]
wire [5:0] pma_checker_special_entry_data_0_lo_hi = {pma_checker_special_entry_data_0_lo_hi_hi, pma_checker_special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_special_entry_data_0_lo = {pma_checker_special_entry_data_0_lo_hi, pma_checker_special_entry_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__special_entry_data_0_T = {31'h0, pma_checker_special_entry_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi = {pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_superpage_entries_0_data_0_lo_lo = {pma_checker_superpage_entries_0_data_0_lo_lo_hi, pma_checker_superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo = {pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_superpage_entries_0_data_0_lo_hi = {pma_checker_superpage_entries_0_data_0_lo_hi_hi, pma_checker_superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_superpage_entries_0_data_0_lo = {pma_checker_superpage_entries_0_data_0_lo_hi, pma_checker_superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__superpage_entries_0_data_0_T = {31'h0, pma_checker_superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi = {pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_superpage_entries_1_data_0_lo_lo = {pma_checker_superpage_entries_1_data_0_lo_lo_hi, pma_checker_superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo = {pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_superpage_entries_1_data_0_lo_hi = {pma_checker_superpage_entries_1_data_0_lo_hi_hi, pma_checker_superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_superpage_entries_1_data_0_lo = {pma_checker_superpage_entries_1_data_0_lo_hi, pma_checker_superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__superpage_entries_1_data_0_T = {31'h0, pma_checker_superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi = {pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_superpage_entries_2_data_0_lo_lo = {pma_checker_superpage_entries_2_data_0_lo_lo_hi, pma_checker_superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo = {pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_superpage_entries_2_data_0_lo_hi = {pma_checker_superpage_entries_2_data_0_lo_hi_hi, pma_checker_superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_superpage_entries_2_data_0_lo = {pma_checker_superpage_entries_2_data_0_lo_hi, pma_checker_superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__superpage_entries_2_data_0_T = {31'h0, pma_checker_superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi = {pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_superpage_entries_3_data_0_lo_lo = {pma_checker_superpage_entries_3_data_0_lo_lo_hi, pma_checker_superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo = {pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_superpage_entries_3_data_0_lo_hi = {pma_checker_superpage_entries_3_data_0_lo_hi_hi, pma_checker_superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_superpage_entries_3_data_0_lo = {pma_checker_superpage_entries_3_data_0_lo_hi, pma_checker_superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__superpage_entries_3_data_0_T = {31'h0, pma_checker_superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi = {pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_0_data_lo_lo = {pma_checker_sectored_entries_0_0_data_lo_lo_hi, pma_checker_sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo = {pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_sectored_entries_0_0_data_lo_hi = {pma_checker_sectored_entries_0_0_data_lo_hi_hi, pma_checker_sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_0_data_lo = {pma_checker_sectored_entries_0_0_data_lo_hi, pma_checker_sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_0_data_T = {31'h0, pma_checker_sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi = {pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_1_data_lo_lo = {pma_checker_sectored_entries_0_1_data_lo_lo_hi, pma_checker_sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo = {pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_sectored_entries_0_1_data_lo_hi = {pma_checker_sectored_entries_0_1_data_lo_hi_hi, pma_checker_sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_1_data_lo = {pma_checker_sectored_entries_0_1_data_lo_hi, pma_checker_sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_1_data_T = {31'h0, pma_checker_sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi = {pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_2_data_lo_lo = {pma_checker_sectored_entries_0_2_data_lo_lo_hi, pma_checker_sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo = {pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_sectored_entries_0_2_data_lo_hi = {pma_checker_sectored_entries_0_2_data_lo_hi_hi, pma_checker_sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_2_data_lo = {pma_checker_sectored_entries_0_2_data_lo_hi, pma_checker_sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_2_data_T = {31'h0, pma_checker_sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi = {pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_3_data_lo_lo = {pma_checker_sectored_entries_0_3_data_lo_lo_hi, pma_checker_sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo = {pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_sectored_entries_0_3_data_lo_hi = {pma_checker_sectored_entries_0_3_data_lo_hi_hi, pma_checker_sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_3_data_lo = {pma_checker_sectored_entries_0_3_data_lo_hi, pma_checker_sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_3_data_T = {31'h0, pma_checker_sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi = {pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_4_data_lo_lo = {pma_checker_sectored_entries_0_4_data_lo_lo_hi, pma_checker_sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo = {pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_sectored_entries_0_4_data_lo_hi = {pma_checker_sectored_entries_0_4_data_lo_hi_hi, pma_checker_sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_4_data_lo = {pma_checker_sectored_entries_0_4_data_lo_hi, pma_checker_sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_4_data_T = {31'h0, pma_checker_sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi = {pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_5_data_lo_lo = {pma_checker_sectored_entries_0_5_data_lo_lo_hi, pma_checker_sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo = {pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_sectored_entries_0_5_data_lo_hi = {pma_checker_sectored_entries_0_5_data_lo_hi_hi, pma_checker_sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_5_data_lo = {pma_checker_sectored_entries_0_5_data_lo_hi, pma_checker_sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_5_data_T = {31'h0, pma_checker_sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi = {pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_6_data_lo_lo = {pma_checker_sectored_entries_0_6_data_lo_lo_hi, pma_checker_sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo = {pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_sectored_entries_0_6_data_lo_hi = {pma_checker_sectored_entries_0_6_data_lo_hi_hi, pma_checker_sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_6_data_lo = {pma_checker_sectored_entries_0_6_data_lo_hi, pma_checker_sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_6_data_T = {31'h0, pma_checker_sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi = {pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_7_data_lo_lo = {pma_checker_sectored_entries_0_7_data_lo_lo_hi, pma_checker_sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo = {pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_sectored_entries_0_7_data_lo_hi = {pma_checker_sectored_entries_0_7_data_lo_hi_hi, pma_checker_sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_7_data_lo = {pma_checker_sectored_entries_0_7_data_lo_hi, pma_checker_sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_7_data_T = {31'h0, pma_checker_sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24]
wire [19:0] pma_checker__entries_T_23; // @[TLB.scala:170:77]
wire pma_checker__entries_T_22; // @[TLB.scala:170:77]
wire pma_checker__entries_T_21; // @[TLB.scala:170:77]
wire pma_checker__entries_T_20; // @[TLB.scala:170:77]
wire pma_checker__entries_T_19; // @[TLB.scala:170:77]
wire pma_checker__entries_T_18; // @[TLB.scala:170:77]
wire pma_checker__entries_T_17; // @[TLB.scala:170:77]
wire pma_checker__entries_T_16; // @[TLB.scala:170:77]
wire pma_checker__entries_T_15; // @[TLB.scala:170:77]
wire pma_checker__entries_T_14; // @[TLB.scala:170:77]
wire pma_checker__entries_T_13; // @[TLB.scala:170:77]
wire pma_checker__entries_T_12; // @[TLB.scala:170:77]
wire pma_checker__entries_T_11; // @[TLB.scala:170:77]
wire pma_checker__entries_T_10; // @[TLB.scala:170:77]
wire pma_checker__entries_T_9; // @[TLB.scala:170:77]
wire pma_checker__entries_T_8; // @[TLB.scala:170:77]
wire pma_checker__entries_T_7; // @[TLB.scala:170:77]
wire pma_checker__entries_T_6; // @[TLB.scala:170:77]
wire pma_checker__entries_T_5; // @[TLB.scala:170:77]
wire pma_checker__entries_T_4; // @[TLB.scala:170:77]
wire pma_checker__entries_T_3; // @[TLB.scala:170:77]
wire pma_checker__entries_T_2; // @[TLB.scala:170:77]
wire pma_checker__entries_T_1; // @[TLB.scala:170:77]
assign pma_checker__entries_T_1 = pma_checker__entries_WIRE_1[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_fragmented_superpage = pma_checker__entries_T_1; // @[TLB.scala:170:77]
assign pma_checker__entries_T_2 = pma_checker__entries_WIRE_1[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_c = pma_checker__entries_T_2; // @[TLB.scala:170:77]
assign pma_checker__entries_T_3 = pma_checker__entries_WIRE_1[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_eff = pma_checker__entries_T_3; // @[TLB.scala:170:77]
assign pma_checker__entries_T_4 = pma_checker__entries_WIRE_1[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_paa = pma_checker__entries_T_4; // @[TLB.scala:170:77]
assign pma_checker__entries_T_5 = pma_checker__entries_WIRE_1[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_pal = pma_checker__entries_T_5; // @[TLB.scala:170:77]
assign pma_checker__entries_T_6 = pma_checker__entries_WIRE_1[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_ppp = pma_checker__entries_T_6; // @[TLB.scala:170:77]
assign pma_checker__entries_T_7 = pma_checker__entries_WIRE_1[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_pr = pma_checker__entries_T_7; // @[TLB.scala:170:77]
assign pma_checker__entries_T_8 = pma_checker__entries_WIRE_1[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_px = pma_checker__entries_T_8; // @[TLB.scala:170:77]
assign pma_checker__entries_T_9 = pma_checker__entries_WIRE_1[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_pw = pma_checker__entries_T_9; // @[TLB.scala:170:77]
assign pma_checker__entries_T_10 = pma_checker__entries_WIRE_1[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_hr = pma_checker__entries_T_10; // @[TLB.scala:170:77]
assign pma_checker__entries_T_11 = pma_checker__entries_WIRE_1[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_hx = pma_checker__entries_T_11; // @[TLB.scala:170:77]
assign pma_checker__entries_T_12 = pma_checker__entries_WIRE_1[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_hw = pma_checker__entries_T_12; // @[TLB.scala:170:77]
assign pma_checker__entries_T_13 = pma_checker__entries_WIRE_1[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_sr = pma_checker__entries_T_13; // @[TLB.scala:170:77]
assign pma_checker__entries_T_14 = pma_checker__entries_WIRE_1[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_sx = pma_checker__entries_T_14; // @[TLB.scala:170:77]
assign pma_checker__entries_T_15 = pma_checker__entries_WIRE_1[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_sw = pma_checker__entries_T_15; // @[TLB.scala:170:77]
assign pma_checker__entries_T_16 = pma_checker__entries_WIRE_1[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_gf = pma_checker__entries_T_16; // @[TLB.scala:170:77]
assign pma_checker__entries_T_17 = pma_checker__entries_WIRE_1[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_pf = pma_checker__entries_T_17; // @[TLB.scala:170:77]
assign pma_checker__entries_T_18 = pma_checker__entries_WIRE_1[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_ae_stage2 = pma_checker__entries_T_18; // @[TLB.scala:170:77]
assign pma_checker__entries_T_19 = pma_checker__entries_WIRE_1[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_ae_final = pma_checker__entries_T_19; // @[TLB.scala:170:77]
assign pma_checker__entries_T_20 = pma_checker__entries_WIRE_1[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_ae_ptw = pma_checker__entries_T_20; // @[TLB.scala:170:77]
assign pma_checker__entries_T_21 = pma_checker__entries_WIRE_1[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_g = pma_checker__entries_T_21; // @[TLB.scala:170:77]
assign pma_checker__entries_T_22 = pma_checker__entries_WIRE_1[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_u = pma_checker__entries_T_22; // @[TLB.scala:170:77]
assign pma_checker__entries_T_23 = pma_checker__entries_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_ppn = pma_checker__entries_T_23; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_47; // @[TLB.scala:170:77]
wire pma_checker__entries_T_46; // @[TLB.scala:170:77]
wire pma_checker__entries_T_45; // @[TLB.scala:170:77]
wire pma_checker__entries_T_44; // @[TLB.scala:170:77]
wire pma_checker__entries_T_43; // @[TLB.scala:170:77]
wire pma_checker__entries_T_42; // @[TLB.scala:170:77]
wire pma_checker__entries_T_41; // @[TLB.scala:170:77]
wire pma_checker__entries_T_40; // @[TLB.scala:170:77]
wire pma_checker__entries_T_39; // @[TLB.scala:170:77]
wire pma_checker__entries_T_38; // @[TLB.scala:170:77]
wire pma_checker__entries_T_37; // @[TLB.scala:170:77]
wire pma_checker__entries_T_36; // @[TLB.scala:170:77]
wire pma_checker__entries_T_35; // @[TLB.scala:170:77]
wire pma_checker__entries_T_34; // @[TLB.scala:170:77]
wire pma_checker__entries_T_33; // @[TLB.scala:170:77]
wire pma_checker__entries_T_32; // @[TLB.scala:170:77]
wire pma_checker__entries_T_31; // @[TLB.scala:170:77]
wire pma_checker__entries_T_30; // @[TLB.scala:170:77]
wire pma_checker__entries_T_29; // @[TLB.scala:170:77]
wire pma_checker__entries_T_28; // @[TLB.scala:170:77]
wire pma_checker__entries_T_27; // @[TLB.scala:170:77]
wire pma_checker__entries_T_26; // @[TLB.scala:170:77]
wire pma_checker__entries_T_25; // @[TLB.scala:170:77]
assign pma_checker__entries_T_25 = pma_checker__entries_WIRE_3[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_fragmented_superpage = pma_checker__entries_T_25; // @[TLB.scala:170:77]
assign pma_checker__entries_T_26 = pma_checker__entries_WIRE_3[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_c = pma_checker__entries_T_26; // @[TLB.scala:170:77]
assign pma_checker__entries_T_27 = pma_checker__entries_WIRE_3[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_eff = pma_checker__entries_T_27; // @[TLB.scala:170:77]
assign pma_checker__entries_T_28 = pma_checker__entries_WIRE_3[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_paa = pma_checker__entries_T_28; // @[TLB.scala:170:77]
assign pma_checker__entries_T_29 = pma_checker__entries_WIRE_3[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_pal = pma_checker__entries_T_29; // @[TLB.scala:170:77]
assign pma_checker__entries_T_30 = pma_checker__entries_WIRE_3[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_ppp = pma_checker__entries_T_30; // @[TLB.scala:170:77]
assign pma_checker__entries_T_31 = pma_checker__entries_WIRE_3[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_pr = pma_checker__entries_T_31; // @[TLB.scala:170:77]
assign pma_checker__entries_T_32 = pma_checker__entries_WIRE_3[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_px = pma_checker__entries_T_32; // @[TLB.scala:170:77]
assign pma_checker__entries_T_33 = pma_checker__entries_WIRE_3[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_pw = pma_checker__entries_T_33; // @[TLB.scala:170:77]
assign pma_checker__entries_T_34 = pma_checker__entries_WIRE_3[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_hr = pma_checker__entries_T_34; // @[TLB.scala:170:77]
assign pma_checker__entries_T_35 = pma_checker__entries_WIRE_3[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_hx = pma_checker__entries_T_35; // @[TLB.scala:170:77]
assign pma_checker__entries_T_36 = pma_checker__entries_WIRE_3[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_hw = pma_checker__entries_T_36; // @[TLB.scala:170:77]
assign pma_checker__entries_T_37 = pma_checker__entries_WIRE_3[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_sr = pma_checker__entries_T_37; // @[TLB.scala:170:77]
assign pma_checker__entries_T_38 = pma_checker__entries_WIRE_3[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_sx = pma_checker__entries_T_38; // @[TLB.scala:170:77]
assign pma_checker__entries_T_39 = pma_checker__entries_WIRE_3[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_sw = pma_checker__entries_T_39; // @[TLB.scala:170:77]
assign pma_checker__entries_T_40 = pma_checker__entries_WIRE_3[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_gf = pma_checker__entries_T_40; // @[TLB.scala:170:77]
assign pma_checker__entries_T_41 = pma_checker__entries_WIRE_3[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_pf = pma_checker__entries_T_41; // @[TLB.scala:170:77]
assign pma_checker__entries_T_42 = pma_checker__entries_WIRE_3[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_ae_stage2 = pma_checker__entries_T_42; // @[TLB.scala:170:77]
assign pma_checker__entries_T_43 = pma_checker__entries_WIRE_3[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_ae_final = pma_checker__entries_T_43; // @[TLB.scala:170:77]
assign pma_checker__entries_T_44 = pma_checker__entries_WIRE_3[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_ae_ptw = pma_checker__entries_T_44; // @[TLB.scala:170:77]
assign pma_checker__entries_T_45 = pma_checker__entries_WIRE_3[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_g = pma_checker__entries_T_45; // @[TLB.scala:170:77]
assign pma_checker__entries_T_46 = pma_checker__entries_WIRE_3[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_u = pma_checker__entries_T_46; // @[TLB.scala:170:77]
assign pma_checker__entries_T_47 = pma_checker__entries_WIRE_3[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_2_ppn = pma_checker__entries_T_47; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_71; // @[TLB.scala:170:77]
wire pma_checker__entries_T_70; // @[TLB.scala:170:77]
wire pma_checker__entries_T_69; // @[TLB.scala:170:77]
wire pma_checker__entries_T_68; // @[TLB.scala:170:77]
wire pma_checker__entries_T_67; // @[TLB.scala:170:77]
wire pma_checker__entries_T_66; // @[TLB.scala:170:77]
wire pma_checker__entries_T_65; // @[TLB.scala:170:77]
wire pma_checker__entries_T_64; // @[TLB.scala:170:77]
wire pma_checker__entries_T_63; // @[TLB.scala:170:77]
wire pma_checker__entries_T_62; // @[TLB.scala:170:77]
wire pma_checker__entries_T_61; // @[TLB.scala:170:77]
wire pma_checker__entries_T_60; // @[TLB.scala:170:77]
wire pma_checker__entries_T_59; // @[TLB.scala:170:77]
wire pma_checker__entries_T_58; // @[TLB.scala:170:77]
wire pma_checker__entries_T_57; // @[TLB.scala:170:77]
wire pma_checker__entries_T_56; // @[TLB.scala:170:77]
wire pma_checker__entries_T_55; // @[TLB.scala:170:77]
wire pma_checker__entries_T_54; // @[TLB.scala:170:77]
wire pma_checker__entries_T_53; // @[TLB.scala:170:77]
wire pma_checker__entries_T_52; // @[TLB.scala:170:77]
wire pma_checker__entries_T_51; // @[TLB.scala:170:77]
wire pma_checker__entries_T_50; // @[TLB.scala:170:77]
wire pma_checker__entries_T_49; // @[TLB.scala:170:77]
assign pma_checker__entries_T_49 = pma_checker__entries_WIRE_5[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_fragmented_superpage = pma_checker__entries_T_49; // @[TLB.scala:170:77]
assign pma_checker__entries_T_50 = pma_checker__entries_WIRE_5[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_c = pma_checker__entries_T_50; // @[TLB.scala:170:77]
assign pma_checker__entries_T_51 = pma_checker__entries_WIRE_5[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_eff = pma_checker__entries_T_51; // @[TLB.scala:170:77]
assign pma_checker__entries_T_52 = pma_checker__entries_WIRE_5[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_paa = pma_checker__entries_T_52; // @[TLB.scala:170:77]
assign pma_checker__entries_T_53 = pma_checker__entries_WIRE_5[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_pal = pma_checker__entries_T_53; // @[TLB.scala:170:77]
assign pma_checker__entries_T_54 = pma_checker__entries_WIRE_5[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_ppp = pma_checker__entries_T_54; // @[TLB.scala:170:77]
assign pma_checker__entries_T_55 = pma_checker__entries_WIRE_5[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_pr = pma_checker__entries_T_55; // @[TLB.scala:170:77]
assign pma_checker__entries_T_56 = pma_checker__entries_WIRE_5[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_px = pma_checker__entries_T_56; // @[TLB.scala:170:77]
assign pma_checker__entries_T_57 = pma_checker__entries_WIRE_5[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_pw = pma_checker__entries_T_57; // @[TLB.scala:170:77]
assign pma_checker__entries_T_58 = pma_checker__entries_WIRE_5[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_hr = pma_checker__entries_T_58; // @[TLB.scala:170:77]
assign pma_checker__entries_T_59 = pma_checker__entries_WIRE_5[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_hx = pma_checker__entries_T_59; // @[TLB.scala:170:77]
assign pma_checker__entries_T_60 = pma_checker__entries_WIRE_5[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_hw = pma_checker__entries_T_60; // @[TLB.scala:170:77]
assign pma_checker__entries_T_61 = pma_checker__entries_WIRE_5[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_sr = pma_checker__entries_T_61; // @[TLB.scala:170:77]
assign pma_checker__entries_T_62 = pma_checker__entries_WIRE_5[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_sx = pma_checker__entries_T_62; // @[TLB.scala:170:77]
assign pma_checker__entries_T_63 = pma_checker__entries_WIRE_5[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_sw = pma_checker__entries_T_63; // @[TLB.scala:170:77]
assign pma_checker__entries_T_64 = pma_checker__entries_WIRE_5[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_gf = pma_checker__entries_T_64; // @[TLB.scala:170:77]
assign pma_checker__entries_T_65 = pma_checker__entries_WIRE_5[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_pf = pma_checker__entries_T_65; // @[TLB.scala:170:77]
assign pma_checker__entries_T_66 = pma_checker__entries_WIRE_5[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_ae_stage2 = pma_checker__entries_T_66; // @[TLB.scala:170:77]
assign pma_checker__entries_T_67 = pma_checker__entries_WIRE_5[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_ae_final = pma_checker__entries_T_67; // @[TLB.scala:170:77]
assign pma_checker__entries_T_68 = pma_checker__entries_WIRE_5[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_ae_ptw = pma_checker__entries_T_68; // @[TLB.scala:170:77]
assign pma_checker__entries_T_69 = pma_checker__entries_WIRE_5[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_g = pma_checker__entries_T_69; // @[TLB.scala:170:77]
assign pma_checker__entries_T_70 = pma_checker__entries_WIRE_5[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_u = pma_checker__entries_T_70; // @[TLB.scala:170:77]
assign pma_checker__entries_T_71 = pma_checker__entries_WIRE_5[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_4_ppn = pma_checker__entries_T_71; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_95; // @[TLB.scala:170:77]
wire pma_checker__entries_T_94; // @[TLB.scala:170:77]
wire pma_checker__entries_T_93; // @[TLB.scala:170:77]
wire pma_checker__entries_T_92; // @[TLB.scala:170:77]
wire pma_checker__entries_T_91; // @[TLB.scala:170:77]
wire pma_checker__entries_T_90; // @[TLB.scala:170:77]
wire pma_checker__entries_T_89; // @[TLB.scala:170:77]
wire pma_checker__entries_T_88; // @[TLB.scala:170:77]
wire pma_checker__entries_T_87; // @[TLB.scala:170:77]
wire pma_checker__entries_T_86; // @[TLB.scala:170:77]
wire pma_checker__entries_T_85; // @[TLB.scala:170:77]
wire pma_checker__entries_T_84; // @[TLB.scala:170:77]
wire pma_checker__entries_T_83; // @[TLB.scala:170:77]
wire pma_checker__entries_T_82; // @[TLB.scala:170:77]
wire pma_checker__entries_T_81; // @[TLB.scala:170:77]
wire pma_checker__entries_T_80; // @[TLB.scala:170:77]
wire pma_checker__entries_T_79; // @[TLB.scala:170:77]
wire pma_checker__entries_T_78; // @[TLB.scala:170:77]
wire pma_checker__entries_T_77; // @[TLB.scala:170:77]
wire pma_checker__entries_T_76; // @[TLB.scala:170:77]
wire pma_checker__entries_T_75; // @[TLB.scala:170:77]
wire pma_checker__entries_T_74; // @[TLB.scala:170:77]
wire pma_checker__entries_T_73; // @[TLB.scala:170:77]
assign pma_checker__entries_T_73 = pma_checker__entries_WIRE_7[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_fragmented_superpage = pma_checker__entries_T_73; // @[TLB.scala:170:77]
assign pma_checker__entries_T_74 = pma_checker__entries_WIRE_7[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_c = pma_checker__entries_T_74; // @[TLB.scala:170:77]
assign pma_checker__entries_T_75 = pma_checker__entries_WIRE_7[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_eff = pma_checker__entries_T_75; // @[TLB.scala:170:77]
assign pma_checker__entries_T_76 = pma_checker__entries_WIRE_7[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_paa = pma_checker__entries_T_76; // @[TLB.scala:170:77]
assign pma_checker__entries_T_77 = pma_checker__entries_WIRE_7[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_pal = pma_checker__entries_T_77; // @[TLB.scala:170:77]
assign pma_checker__entries_T_78 = pma_checker__entries_WIRE_7[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_ppp = pma_checker__entries_T_78; // @[TLB.scala:170:77]
assign pma_checker__entries_T_79 = pma_checker__entries_WIRE_7[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_pr = pma_checker__entries_T_79; // @[TLB.scala:170:77]
assign pma_checker__entries_T_80 = pma_checker__entries_WIRE_7[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_px = pma_checker__entries_T_80; // @[TLB.scala:170:77]
assign pma_checker__entries_T_81 = pma_checker__entries_WIRE_7[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_pw = pma_checker__entries_T_81; // @[TLB.scala:170:77]
assign pma_checker__entries_T_82 = pma_checker__entries_WIRE_7[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_hr = pma_checker__entries_T_82; // @[TLB.scala:170:77]
assign pma_checker__entries_T_83 = pma_checker__entries_WIRE_7[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_hx = pma_checker__entries_T_83; // @[TLB.scala:170:77]
assign pma_checker__entries_T_84 = pma_checker__entries_WIRE_7[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_hw = pma_checker__entries_T_84; // @[TLB.scala:170:77]
assign pma_checker__entries_T_85 = pma_checker__entries_WIRE_7[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_sr = pma_checker__entries_T_85; // @[TLB.scala:170:77]
assign pma_checker__entries_T_86 = pma_checker__entries_WIRE_7[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_sx = pma_checker__entries_T_86; // @[TLB.scala:170:77]
assign pma_checker__entries_T_87 = pma_checker__entries_WIRE_7[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_sw = pma_checker__entries_T_87; // @[TLB.scala:170:77]
assign pma_checker__entries_T_88 = pma_checker__entries_WIRE_7[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_gf = pma_checker__entries_T_88; // @[TLB.scala:170:77]
assign pma_checker__entries_T_89 = pma_checker__entries_WIRE_7[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_pf = pma_checker__entries_T_89; // @[TLB.scala:170:77]
assign pma_checker__entries_T_90 = pma_checker__entries_WIRE_7[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_ae_stage2 = pma_checker__entries_T_90; // @[TLB.scala:170:77]
assign pma_checker__entries_T_91 = pma_checker__entries_WIRE_7[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_ae_final = pma_checker__entries_T_91; // @[TLB.scala:170:77]
assign pma_checker__entries_T_92 = pma_checker__entries_WIRE_7[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_ae_ptw = pma_checker__entries_T_92; // @[TLB.scala:170:77]
assign pma_checker__entries_T_93 = pma_checker__entries_WIRE_7[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_g = pma_checker__entries_T_93; // @[TLB.scala:170:77]
assign pma_checker__entries_T_94 = pma_checker__entries_WIRE_7[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_u = pma_checker__entries_T_94; // @[TLB.scala:170:77]
assign pma_checker__entries_T_95 = pma_checker__entries_WIRE_7[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_6_ppn = pma_checker__entries_T_95; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_119; // @[TLB.scala:170:77]
wire pma_checker__entries_T_118; // @[TLB.scala:170:77]
wire pma_checker__entries_T_117; // @[TLB.scala:170:77]
wire pma_checker__entries_T_116; // @[TLB.scala:170:77]
wire pma_checker__entries_T_115; // @[TLB.scala:170:77]
wire pma_checker__entries_T_114; // @[TLB.scala:170:77]
wire pma_checker__entries_T_113; // @[TLB.scala:170:77]
wire pma_checker__entries_T_112; // @[TLB.scala:170:77]
wire pma_checker__entries_T_111; // @[TLB.scala:170:77]
wire pma_checker__entries_T_110; // @[TLB.scala:170:77]
wire pma_checker__entries_T_109; // @[TLB.scala:170:77]
wire pma_checker__entries_T_108; // @[TLB.scala:170:77]
wire pma_checker__entries_T_107; // @[TLB.scala:170:77]
wire pma_checker__entries_T_106; // @[TLB.scala:170:77]
wire pma_checker__entries_T_105; // @[TLB.scala:170:77]
wire pma_checker__entries_T_104; // @[TLB.scala:170:77]
wire pma_checker__entries_T_103; // @[TLB.scala:170:77]
wire pma_checker__entries_T_102; // @[TLB.scala:170:77]
wire pma_checker__entries_T_101; // @[TLB.scala:170:77]
wire pma_checker__entries_T_100; // @[TLB.scala:170:77]
wire pma_checker__entries_T_99; // @[TLB.scala:170:77]
wire pma_checker__entries_T_98; // @[TLB.scala:170:77]
wire pma_checker__entries_T_97; // @[TLB.scala:170:77]
assign pma_checker__entries_T_97 = pma_checker__entries_WIRE_9[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_fragmented_superpage = pma_checker__entries_T_97; // @[TLB.scala:170:77]
assign pma_checker__entries_T_98 = pma_checker__entries_WIRE_9[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_c = pma_checker__entries_T_98; // @[TLB.scala:170:77]
assign pma_checker__entries_T_99 = pma_checker__entries_WIRE_9[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_eff = pma_checker__entries_T_99; // @[TLB.scala:170:77]
assign pma_checker__entries_T_100 = pma_checker__entries_WIRE_9[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_paa = pma_checker__entries_T_100; // @[TLB.scala:170:77]
assign pma_checker__entries_T_101 = pma_checker__entries_WIRE_9[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_pal = pma_checker__entries_T_101; // @[TLB.scala:170:77]
assign pma_checker__entries_T_102 = pma_checker__entries_WIRE_9[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_ppp = pma_checker__entries_T_102; // @[TLB.scala:170:77]
assign pma_checker__entries_T_103 = pma_checker__entries_WIRE_9[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_pr = pma_checker__entries_T_103; // @[TLB.scala:170:77]
assign pma_checker__entries_T_104 = pma_checker__entries_WIRE_9[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_px = pma_checker__entries_T_104; // @[TLB.scala:170:77]
assign pma_checker__entries_T_105 = pma_checker__entries_WIRE_9[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_pw = pma_checker__entries_T_105; // @[TLB.scala:170:77]
assign pma_checker__entries_T_106 = pma_checker__entries_WIRE_9[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_hr = pma_checker__entries_T_106; // @[TLB.scala:170:77]
assign pma_checker__entries_T_107 = pma_checker__entries_WIRE_9[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_hx = pma_checker__entries_T_107; // @[TLB.scala:170:77]
assign pma_checker__entries_T_108 = pma_checker__entries_WIRE_9[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_hw = pma_checker__entries_T_108; // @[TLB.scala:170:77]
assign pma_checker__entries_T_109 = pma_checker__entries_WIRE_9[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_sr = pma_checker__entries_T_109; // @[TLB.scala:170:77]
assign pma_checker__entries_T_110 = pma_checker__entries_WIRE_9[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_sx = pma_checker__entries_T_110; // @[TLB.scala:170:77]
assign pma_checker__entries_T_111 = pma_checker__entries_WIRE_9[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_sw = pma_checker__entries_T_111; // @[TLB.scala:170:77]
assign pma_checker__entries_T_112 = pma_checker__entries_WIRE_9[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_gf = pma_checker__entries_T_112; // @[TLB.scala:170:77]
assign pma_checker__entries_T_113 = pma_checker__entries_WIRE_9[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_pf = pma_checker__entries_T_113; // @[TLB.scala:170:77]
assign pma_checker__entries_T_114 = pma_checker__entries_WIRE_9[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_ae_stage2 = pma_checker__entries_T_114; // @[TLB.scala:170:77]
assign pma_checker__entries_T_115 = pma_checker__entries_WIRE_9[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_ae_final = pma_checker__entries_T_115; // @[TLB.scala:170:77]
assign pma_checker__entries_T_116 = pma_checker__entries_WIRE_9[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_ae_ptw = pma_checker__entries_T_116; // @[TLB.scala:170:77]
assign pma_checker__entries_T_117 = pma_checker__entries_WIRE_9[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_g = pma_checker__entries_T_117; // @[TLB.scala:170:77]
assign pma_checker__entries_T_118 = pma_checker__entries_WIRE_9[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_u = pma_checker__entries_T_118; // @[TLB.scala:170:77]
assign pma_checker__entries_T_119 = pma_checker__entries_WIRE_9[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_8_ppn = pma_checker__entries_T_119; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_143; // @[TLB.scala:170:77]
wire pma_checker__entries_T_142; // @[TLB.scala:170:77]
wire pma_checker__entries_T_141; // @[TLB.scala:170:77]
wire pma_checker__entries_T_140; // @[TLB.scala:170:77]
wire pma_checker__entries_T_139; // @[TLB.scala:170:77]
wire pma_checker__entries_T_138; // @[TLB.scala:170:77]
wire pma_checker__entries_T_137; // @[TLB.scala:170:77]
wire pma_checker__entries_T_136; // @[TLB.scala:170:77]
wire pma_checker__entries_T_135; // @[TLB.scala:170:77]
wire pma_checker__entries_T_134; // @[TLB.scala:170:77]
wire pma_checker__entries_T_133; // @[TLB.scala:170:77]
wire pma_checker__entries_T_132; // @[TLB.scala:170:77]
wire pma_checker__entries_T_131; // @[TLB.scala:170:77]
wire pma_checker__entries_T_130; // @[TLB.scala:170:77]
wire pma_checker__entries_T_129; // @[TLB.scala:170:77]
wire pma_checker__entries_T_128; // @[TLB.scala:170:77]
wire pma_checker__entries_T_127; // @[TLB.scala:170:77]
wire pma_checker__entries_T_126; // @[TLB.scala:170:77]
wire pma_checker__entries_T_125; // @[TLB.scala:170:77]
wire pma_checker__entries_T_124; // @[TLB.scala:170:77]
wire pma_checker__entries_T_123; // @[TLB.scala:170:77]
wire pma_checker__entries_T_122; // @[TLB.scala:170:77]
wire pma_checker__entries_T_121; // @[TLB.scala:170:77]
assign pma_checker__entries_T_121 = pma_checker__entries_WIRE_11[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_fragmented_superpage = pma_checker__entries_T_121; // @[TLB.scala:170:77]
assign pma_checker__entries_T_122 = pma_checker__entries_WIRE_11[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_c = pma_checker__entries_T_122; // @[TLB.scala:170:77]
assign pma_checker__entries_T_123 = pma_checker__entries_WIRE_11[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_eff = pma_checker__entries_T_123; // @[TLB.scala:170:77]
assign pma_checker__entries_T_124 = pma_checker__entries_WIRE_11[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_paa = pma_checker__entries_T_124; // @[TLB.scala:170:77]
assign pma_checker__entries_T_125 = pma_checker__entries_WIRE_11[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_pal = pma_checker__entries_T_125; // @[TLB.scala:170:77]
assign pma_checker__entries_T_126 = pma_checker__entries_WIRE_11[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_ppp = pma_checker__entries_T_126; // @[TLB.scala:170:77]
assign pma_checker__entries_T_127 = pma_checker__entries_WIRE_11[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_pr = pma_checker__entries_T_127; // @[TLB.scala:170:77]
assign pma_checker__entries_T_128 = pma_checker__entries_WIRE_11[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_px = pma_checker__entries_T_128; // @[TLB.scala:170:77]
assign pma_checker__entries_T_129 = pma_checker__entries_WIRE_11[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_pw = pma_checker__entries_T_129; // @[TLB.scala:170:77]
assign pma_checker__entries_T_130 = pma_checker__entries_WIRE_11[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_hr = pma_checker__entries_T_130; // @[TLB.scala:170:77]
assign pma_checker__entries_T_131 = pma_checker__entries_WIRE_11[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_hx = pma_checker__entries_T_131; // @[TLB.scala:170:77]
assign pma_checker__entries_T_132 = pma_checker__entries_WIRE_11[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_hw = pma_checker__entries_T_132; // @[TLB.scala:170:77]
assign pma_checker__entries_T_133 = pma_checker__entries_WIRE_11[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_sr = pma_checker__entries_T_133; // @[TLB.scala:170:77]
assign pma_checker__entries_T_134 = pma_checker__entries_WIRE_11[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_sx = pma_checker__entries_T_134; // @[TLB.scala:170:77]
assign pma_checker__entries_T_135 = pma_checker__entries_WIRE_11[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_sw = pma_checker__entries_T_135; // @[TLB.scala:170:77]
assign pma_checker__entries_T_136 = pma_checker__entries_WIRE_11[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_gf = pma_checker__entries_T_136; // @[TLB.scala:170:77]
assign pma_checker__entries_T_137 = pma_checker__entries_WIRE_11[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_pf = pma_checker__entries_T_137; // @[TLB.scala:170:77]
assign pma_checker__entries_T_138 = pma_checker__entries_WIRE_11[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_ae_stage2 = pma_checker__entries_T_138; // @[TLB.scala:170:77]
assign pma_checker__entries_T_139 = pma_checker__entries_WIRE_11[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_ae_final = pma_checker__entries_T_139; // @[TLB.scala:170:77]
assign pma_checker__entries_T_140 = pma_checker__entries_WIRE_11[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_ae_ptw = pma_checker__entries_T_140; // @[TLB.scala:170:77]
assign pma_checker__entries_T_141 = pma_checker__entries_WIRE_11[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_g = pma_checker__entries_T_141; // @[TLB.scala:170:77]
assign pma_checker__entries_T_142 = pma_checker__entries_WIRE_11[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_u = pma_checker__entries_T_142; // @[TLB.scala:170:77]
assign pma_checker__entries_T_143 = pma_checker__entries_WIRE_11[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_10_ppn = pma_checker__entries_T_143; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_167; // @[TLB.scala:170:77]
wire pma_checker__entries_T_166; // @[TLB.scala:170:77]
wire pma_checker__entries_T_165; // @[TLB.scala:170:77]
wire pma_checker__entries_T_164; // @[TLB.scala:170:77]
wire pma_checker__entries_T_163; // @[TLB.scala:170:77]
wire pma_checker__entries_T_162; // @[TLB.scala:170:77]
wire pma_checker__entries_T_161; // @[TLB.scala:170:77]
wire pma_checker__entries_T_160; // @[TLB.scala:170:77]
wire pma_checker__entries_T_159; // @[TLB.scala:170:77]
wire pma_checker__entries_T_158; // @[TLB.scala:170:77]
wire pma_checker__entries_T_157; // @[TLB.scala:170:77]
wire pma_checker__entries_T_156; // @[TLB.scala:170:77]
wire pma_checker__entries_T_155; // @[TLB.scala:170:77]
wire pma_checker__entries_T_154; // @[TLB.scala:170:77]
wire pma_checker__entries_T_153; // @[TLB.scala:170:77]
wire pma_checker__entries_T_152; // @[TLB.scala:170:77]
wire pma_checker__entries_T_151; // @[TLB.scala:170:77]
wire pma_checker__entries_T_150; // @[TLB.scala:170:77]
wire pma_checker__entries_T_149; // @[TLB.scala:170:77]
wire pma_checker__entries_T_148; // @[TLB.scala:170:77]
wire pma_checker__entries_T_147; // @[TLB.scala:170:77]
wire pma_checker__entries_T_146; // @[TLB.scala:170:77]
wire pma_checker__entries_T_145; // @[TLB.scala:170:77]
assign pma_checker__entries_T_145 = pma_checker__entries_WIRE_13[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_fragmented_superpage = pma_checker__entries_T_145; // @[TLB.scala:170:77]
assign pma_checker__entries_T_146 = pma_checker__entries_WIRE_13[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_c = pma_checker__entries_T_146; // @[TLB.scala:170:77]
assign pma_checker__entries_T_147 = pma_checker__entries_WIRE_13[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_eff = pma_checker__entries_T_147; // @[TLB.scala:170:77]
assign pma_checker__entries_T_148 = pma_checker__entries_WIRE_13[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_paa = pma_checker__entries_T_148; // @[TLB.scala:170:77]
assign pma_checker__entries_T_149 = pma_checker__entries_WIRE_13[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_pal = pma_checker__entries_T_149; // @[TLB.scala:170:77]
assign pma_checker__entries_T_150 = pma_checker__entries_WIRE_13[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_ppp = pma_checker__entries_T_150; // @[TLB.scala:170:77]
assign pma_checker__entries_T_151 = pma_checker__entries_WIRE_13[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_pr = pma_checker__entries_T_151; // @[TLB.scala:170:77]
assign pma_checker__entries_T_152 = pma_checker__entries_WIRE_13[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_px = pma_checker__entries_T_152; // @[TLB.scala:170:77]
assign pma_checker__entries_T_153 = pma_checker__entries_WIRE_13[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_pw = pma_checker__entries_T_153; // @[TLB.scala:170:77]
assign pma_checker__entries_T_154 = pma_checker__entries_WIRE_13[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_hr = pma_checker__entries_T_154; // @[TLB.scala:170:77]
assign pma_checker__entries_T_155 = pma_checker__entries_WIRE_13[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_hx = pma_checker__entries_T_155; // @[TLB.scala:170:77]
assign pma_checker__entries_T_156 = pma_checker__entries_WIRE_13[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_hw = pma_checker__entries_T_156; // @[TLB.scala:170:77]
assign pma_checker__entries_T_157 = pma_checker__entries_WIRE_13[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_sr = pma_checker__entries_T_157; // @[TLB.scala:170:77]
assign pma_checker__entries_T_158 = pma_checker__entries_WIRE_13[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_sx = pma_checker__entries_T_158; // @[TLB.scala:170:77]
assign pma_checker__entries_T_159 = pma_checker__entries_WIRE_13[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_sw = pma_checker__entries_T_159; // @[TLB.scala:170:77]
assign pma_checker__entries_T_160 = pma_checker__entries_WIRE_13[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_gf = pma_checker__entries_T_160; // @[TLB.scala:170:77]
assign pma_checker__entries_T_161 = pma_checker__entries_WIRE_13[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_pf = pma_checker__entries_T_161; // @[TLB.scala:170:77]
assign pma_checker__entries_T_162 = pma_checker__entries_WIRE_13[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_ae_stage2 = pma_checker__entries_T_162; // @[TLB.scala:170:77]
assign pma_checker__entries_T_163 = pma_checker__entries_WIRE_13[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_ae_final = pma_checker__entries_T_163; // @[TLB.scala:170:77]
assign pma_checker__entries_T_164 = pma_checker__entries_WIRE_13[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_ae_ptw = pma_checker__entries_T_164; // @[TLB.scala:170:77]
assign pma_checker__entries_T_165 = pma_checker__entries_WIRE_13[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_g = pma_checker__entries_T_165; // @[TLB.scala:170:77]
assign pma_checker__entries_T_166 = pma_checker__entries_WIRE_13[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_u = pma_checker__entries_T_166; // @[TLB.scala:170:77]
assign pma_checker__entries_T_167 = pma_checker__entries_WIRE_13[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_12_ppn = pma_checker__entries_T_167; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_191; // @[TLB.scala:170:77]
wire pma_checker__entries_T_190; // @[TLB.scala:170:77]
wire pma_checker__entries_T_189; // @[TLB.scala:170:77]
wire pma_checker__entries_T_188; // @[TLB.scala:170:77]
wire pma_checker__entries_T_187; // @[TLB.scala:170:77]
wire pma_checker__entries_T_186; // @[TLB.scala:170:77]
wire pma_checker__entries_T_185; // @[TLB.scala:170:77]
wire pma_checker__entries_T_184; // @[TLB.scala:170:77]
wire pma_checker__entries_T_183; // @[TLB.scala:170:77]
wire pma_checker__entries_T_182; // @[TLB.scala:170:77]
wire pma_checker__entries_T_181; // @[TLB.scala:170:77]
wire pma_checker__entries_T_180; // @[TLB.scala:170:77]
wire pma_checker__entries_T_179; // @[TLB.scala:170:77]
wire pma_checker__entries_T_178; // @[TLB.scala:170:77]
wire pma_checker__entries_T_177; // @[TLB.scala:170:77]
wire pma_checker__entries_T_176; // @[TLB.scala:170:77]
wire pma_checker__entries_T_175; // @[TLB.scala:170:77]
wire pma_checker__entries_T_174; // @[TLB.scala:170:77]
wire pma_checker__entries_T_173; // @[TLB.scala:170:77]
wire pma_checker__entries_T_172; // @[TLB.scala:170:77]
wire pma_checker__entries_T_171; // @[TLB.scala:170:77]
wire pma_checker__entries_T_170; // @[TLB.scala:170:77]
wire pma_checker__entries_T_169; // @[TLB.scala:170:77]
assign pma_checker__entries_T_169 = pma_checker__entries_WIRE_15[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_fragmented_superpage = pma_checker__entries_T_169; // @[TLB.scala:170:77]
assign pma_checker__entries_T_170 = pma_checker__entries_WIRE_15[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_c = pma_checker__entries_T_170; // @[TLB.scala:170:77]
assign pma_checker__entries_T_171 = pma_checker__entries_WIRE_15[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_eff = pma_checker__entries_T_171; // @[TLB.scala:170:77]
assign pma_checker__entries_T_172 = pma_checker__entries_WIRE_15[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_paa = pma_checker__entries_T_172; // @[TLB.scala:170:77]
assign pma_checker__entries_T_173 = pma_checker__entries_WIRE_15[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_pal = pma_checker__entries_T_173; // @[TLB.scala:170:77]
assign pma_checker__entries_T_174 = pma_checker__entries_WIRE_15[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_ppp = pma_checker__entries_T_174; // @[TLB.scala:170:77]
assign pma_checker__entries_T_175 = pma_checker__entries_WIRE_15[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_pr = pma_checker__entries_T_175; // @[TLB.scala:170:77]
assign pma_checker__entries_T_176 = pma_checker__entries_WIRE_15[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_px = pma_checker__entries_T_176; // @[TLB.scala:170:77]
assign pma_checker__entries_T_177 = pma_checker__entries_WIRE_15[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_pw = pma_checker__entries_T_177; // @[TLB.scala:170:77]
assign pma_checker__entries_T_178 = pma_checker__entries_WIRE_15[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_hr = pma_checker__entries_T_178; // @[TLB.scala:170:77]
assign pma_checker__entries_T_179 = pma_checker__entries_WIRE_15[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_hx = pma_checker__entries_T_179; // @[TLB.scala:170:77]
assign pma_checker__entries_T_180 = pma_checker__entries_WIRE_15[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_hw = pma_checker__entries_T_180; // @[TLB.scala:170:77]
assign pma_checker__entries_T_181 = pma_checker__entries_WIRE_15[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_sr = pma_checker__entries_T_181; // @[TLB.scala:170:77]
assign pma_checker__entries_T_182 = pma_checker__entries_WIRE_15[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_sx = pma_checker__entries_T_182; // @[TLB.scala:170:77]
assign pma_checker__entries_T_183 = pma_checker__entries_WIRE_15[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_sw = pma_checker__entries_T_183; // @[TLB.scala:170:77]
assign pma_checker__entries_T_184 = pma_checker__entries_WIRE_15[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_gf = pma_checker__entries_T_184; // @[TLB.scala:170:77]
assign pma_checker__entries_T_185 = pma_checker__entries_WIRE_15[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_pf = pma_checker__entries_T_185; // @[TLB.scala:170:77]
assign pma_checker__entries_T_186 = pma_checker__entries_WIRE_15[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_ae_stage2 = pma_checker__entries_T_186; // @[TLB.scala:170:77]
assign pma_checker__entries_T_187 = pma_checker__entries_WIRE_15[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_ae_final = pma_checker__entries_T_187; // @[TLB.scala:170:77]
assign pma_checker__entries_T_188 = pma_checker__entries_WIRE_15[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_ae_ptw = pma_checker__entries_T_188; // @[TLB.scala:170:77]
assign pma_checker__entries_T_189 = pma_checker__entries_WIRE_15[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_g = pma_checker__entries_T_189; // @[TLB.scala:170:77]
assign pma_checker__entries_T_190 = pma_checker__entries_WIRE_15[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_u = pma_checker__entries_T_190; // @[TLB.scala:170:77]
assign pma_checker__entries_T_191 = pma_checker__entries_WIRE_15[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_14_ppn = pma_checker__entries_T_191; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_214; // @[TLB.scala:170:77]
wire pma_checker__entries_T_213; // @[TLB.scala:170:77]
wire pma_checker__entries_T_212; // @[TLB.scala:170:77]
wire pma_checker__entries_T_211; // @[TLB.scala:170:77]
wire pma_checker__entries_T_210; // @[TLB.scala:170:77]
wire pma_checker__entries_T_209; // @[TLB.scala:170:77]
wire pma_checker__entries_T_208; // @[TLB.scala:170:77]
wire pma_checker__entries_T_207; // @[TLB.scala:170:77]
wire pma_checker__entries_T_206; // @[TLB.scala:170:77]
wire pma_checker__entries_T_205; // @[TLB.scala:170:77]
wire pma_checker__entries_T_204; // @[TLB.scala:170:77]
wire pma_checker__entries_T_203; // @[TLB.scala:170:77]
wire pma_checker__entries_T_202; // @[TLB.scala:170:77]
wire pma_checker__entries_T_201; // @[TLB.scala:170:77]
wire pma_checker__entries_T_200; // @[TLB.scala:170:77]
wire pma_checker__entries_T_199; // @[TLB.scala:170:77]
wire pma_checker__entries_T_198; // @[TLB.scala:170:77]
wire pma_checker__entries_T_197; // @[TLB.scala:170:77]
wire pma_checker__entries_T_196; // @[TLB.scala:170:77]
wire pma_checker__entries_T_195; // @[TLB.scala:170:77]
wire pma_checker__entries_T_194; // @[TLB.scala:170:77]
wire pma_checker__entries_T_193; // @[TLB.scala:170:77]
wire pma_checker__entries_T_192; // @[TLB.scala:170:77]
assign pma_checker__entries_T_192 = pma_checker__entries_WIRE_17[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_fragmented_superpage = pma_checker__entries_T_192; // @[TLB.scala:170:77]
assign pma_checker__entries_T_193 = pma_checker__entries_WIRE_17[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_c = pma_checker__entries_T_193; // @[TLB.scala:170:77]
assign pma_checker__entries_T_194 = pma_checker__entries_WIRE_17[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_eff = pma_checker__entries_T_194; // @[TLB.scala:170:77]
assign pma_checker__entries_T_195 = pma_checker__entries_WIRE_17[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_paa = pma_checker__entries_T_195; // @[TLB.scala:170:77]
assign pma_checker__entries_T_196 = pma_checker__entries_WIRE_17[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_pal = pma_checker__entries_T_196; // @[TLB.scala:170:77]
assign pma_checker__entries_T_197 = pma_checker__entries_WIRE_17[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_ppp = pma_checker__entries_T_197; // @[TLB.scala:170:77]
assign pma_checker__entries_T_198 = pma_checker__entries_WIRE_17[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_pr = pma_checker__entries_T_198; // @[TLB.scala:170:77]
assign pma_checker__entries_T_199 = pma_checker__entries_WIRE_17[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_px = pma_checker__entries_T_199; // @[TLB.scala:170:77]
assign pma_checker__entries_T_200 = pma_checker__entries_WIRE_17[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_pw = pma_checker__entries_T_200; // @[TLB.scala:170:77]
assign pma_checker__entries_T_201 = pma_checker__entries_WIRE_17[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_hr = pma_checker__entries_T_201; // @[TLB.scala:170:77]
assign pma_checker__entries_T_202 = pma_checker__entries_WIRE_17[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_hx = pma_checker__entries_T_202; // @[TLB.scala:170:77]
assign pma_checker__entries_T_203 = pma_checker__entries_WIRE_17[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_hw = pma_checker__entries_T_203; // @[TLB.scala:170:77]
assign pma_checker__entries_T_204 = pma_checker__entries_WIRE_17[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_sr = pma_checker__entries_T_204; // @[TLB.scala:170:77]
assign pma_checker__entries_T_205 = pma_checker__entries_WIRE_17[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_sx = pma_checker__entries_T_205; // @[TLB.scala:170:77]
assign pma_checker__entries_T_206 = pma_checker__entries_WIRE_17[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_sw = pma_checker__entries_T_206; // @[TLB.scala:170:77]
assign pma_checker__entries_T_207 = pma_checker__entries_WIRE_17[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_gf = pma_checker__entries_T_207; // @[TLB.scala:170:77]
assign pma_checker__entries_T_208 = pma_checker__entries_WIRE_17[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_pf = pma_checker__entries_T_208; // @[TLB.scala:170:77]
assign pma_checker__entries_T_209 = pma_checker__entries_WIRE_17[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_ae_stage2 = pma_checker__entries_T_209; // @[TLB.scala:170:77]
assign pma_checker__entries_T_210 = pma_checker__entries_WIRE_17[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_ae_final = pma_checker__entries_T_210; // @[TLB.scala:170:77]
assign pma_checker__entries_T_211 = pma_checker__entries_WIRE_17[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_ae_ptw = pma_checker__entries_T_211; // @[TLB.scala:170:77]
assign pma_checker__entries_T_212 = pma_checker__entries_WIRE_17[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_g = pma_checker__entries_T_212; // @[TLB.scala:170:77]
assign pma_checker__entries_T_213 = pma_checker__entries_WIRE_17[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_u = pma_checker__entries_T_213; // @[TLB.scala:170:77]
assign pma_checker__entries_T_214 = pma_checker__entries_WIRE_17[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_16_ppn = pma_checker__entries_T_214; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_237; // @[TLB.scala:170:77]
wire pma_checker__entries_T_236; // @[TLB.scala:170:77]
wire pma_checker__entries_T_235; // @[TLB.scala:170:77]
wire pma_checker__entries_T_234; // @[TLB.scala:170:77]
wire pma_checker__entries_T_233; // @[TLB.scala:170:77]
wire pma_checker__entries_T_232; // @[TLB.scala:170:77]
wire pma_checker__entries_T_231; // @[TLB.scala:170:77]
wire pma_checker__entries_T_230; // @[TLB.scala:170:77]
wire pma_checker__entries_T_229; // @[TLB.scala:170:77]
wire pma_checker__entries_T_228; // @[TLB.scala:170:77]
wire pma_checker__entries_T_227; // @[TLB.scala:170:77]
wire pma_checker__entries_T_226; // @[TLB.scala:170:77]
wire pma_checker__entries_T_225; // @[TLB.scala:170:77]
wire pma_checker__entries_T_224; // @[TLB.scala:170:77]
wire pma_checker__entries_T_223; // @[TLB.scala:170:77]
wire pma_checker__entries_T_222; // @[TLB.scala:170:77]
wire pma_checker__entries_T_221; // @[TLB.scala:170:77]
wire pma_checker__entries_T_220; // @[TLB.scala:170:77]
wire pma_checker__entries_T_219; // @[TLB.scala:170:77]
wire pma_checker__entries_T_218; // @[TLB.scala:170:77]
wire pma_checker__entries_T_217; // @[TLB.scala:170:77]
wire pma_checker__entries_T_216; // @[TLB.scala:170:77]
wire pma_checker__entries_T_215; // @[TLB.scala:170:77]
assign pma_checker__entries_T_215 = pma_checker__entries_WIRE_19[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_fragmented_superpage = pma_checker__entries_T_215; // @[TLB.scala:170:77]
assign pma_checker__entries_T_216 = pma_checker__entries_WIRE_19[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_c = pma_checker__entries_T_216; // @[TLB.scala:170:77]
assign pma_checker__entries_T_217 = pma_checker__entries_WIRE_19[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_eff = pma_checker__entries_T_217; // @[TLB.scala:170:77]
assign pma_checker__entries_T_218 = pma_checker__entries_WIRE_19[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_paa = pma_checker__entries_T_218; // @[TLB.scala:170:77]
assign pma_checker__entries_T_219 = pma_checker__entries_WIRE_19[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_pal = pma_checker__entries_T_219; // @[TLB.scala:170:77]
assign pma_checker__entries_T_220 = pma_checker__entries_WIRE_19[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_ppp = pma_checker__entries_T_220; // @[TLB.scala:170:77]
assign pma_checker__entries_T_221 = pma_checker__entries_WIRE_19[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_pr = pma_checker__entries_T_221; // @[TLB.scala:170:77]
assign pma_checker__entries_T_222 = pma_checker__entries_WIRE_19[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_px = pma_checker__entries_T_222; // @[TLB.scala:170:77]
assign pma_checker__entries_T_223 = pma_checker__entries_WIRE_19[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_pw = pma_checker__entries_T_223; // @[TLB.scala:170:77]
assign pma_checker__entries_T_224 = pma_checker__entries_WIRE_19[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_hr = pma_checker__entries_T_224; // @[TLB.scala:170:77]
assign pma_checker__entries_T_225 = pma_checker__entries_WIRE_19[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_hx = pma_checker__entries_T_225; // @[TLB.scala:170:77]
assign pma_checker__entries_T_226 = pma_checker__entries_WIRE_19[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_hw = pma_checker__entries_T_226; // @[TLB.scala:170:77]
assign pma_checker__entries_T_227 = pma_checker__entries_WIRE_19[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_sr = pma_checker__entries_T_227; // @[TLB.scala:170:77]
assign pma_checker__entries_T_228 = pma_checker__entries_WIRE_19[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_sx = pma_checker__entries_T_228; // @[TLB.scala:170:77]
assign pma_checker__entries_T_229 = pma_checker__entries_WIRE_19[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_sw = pma_checker__entries_T_229; // @[TLB.scala:170:77]
assign pma_checker__entries_T_230 = pma_checker__entries_WIRE_19[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_gf = pma_checker__entries_T_230; // @[TLB.scala:170:77]
assign pma_checker__entries_T_231 = pma_checker__entries_WIRE_19[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_pf = pma_checker__entries_T_231; // @[TLB.scala:170:77]
assign pma_checker__entries_T_232 = pma_checker__entries_WIRE_19[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_ae_stage2 = pma_checker__entries_T_232; // @[TLB.scala:170:77]
assign pma_checker__entries_T_233 = pma_checker__entries_WIRE_19[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_ae_final = pma_checker__entries_T_233; // @[TLB.scala:170:77]
assign pma_checker__entries_T_234 = pma_checker__entries_WIRE_19[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_ae_ptw = pma_checker__entries_T_234; // @[TLB.scala:170:77]
assign pma_checker__entries_T_235 = pma_checker__entries_WIRE_19[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_g = pma_checker__entries_T_235; // @[TLB.scala:170:77]
assign pma_checker__entries_T_236 = pma_checker__entries_WIRE_19[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_u = pma_checker__entries_T_236; // @[TLB.scala:170:77]
assign pma_checker__entries_T_237 = pma_checker__entries_WIRE_19[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_18_ppn = pma_checker__entries_T_237; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_260; // @[TLB.scala:170:77]
wire pma_checker__entries_T_259; // @[TLB.scala:170:77]
wire pma_checker__entries_T_258; // @[TLB.scala:170:77]
wire pma_checker__entries_T_257; // @[TLB.scala:170:77]
wire pma_checker__entries_T_256; // @[TLB.scala:170:77]
wire pma_checker__entries_T_255; // @[TLB.scala:170:77]
wire pma_checker__entries_T_254; // @[TLB.scala:170:77]
wire pma_checker__entries_T_253; // @[TLB.scala:170:77]
wire pma_checker__entries_T_252; // @[TLB.scala:170:77]
wire pma_checker__entries_T_251; // @[TLB.scala:170:77]
wire pma_checker__entries_T_250; // @[TLB.scala:170:77]
wire pma_checker__entries_T_249; // @[TLB.scala:170:77]
wire pma_checker__entries_T_248; // @[TLB.scala:170:77]
wire pma_checker__entries_T_247; // @[TLB.scala:170:77]
wire pma_checker__entries_T_246; // @[TLB.scala:170:77]
wire pma_checker__entries_T_245; // @[TLB.scala:170:77]
wire pma_checker__entries_T_244; // @[TLB.scala:170:77]
wire pma_checker__entries_T_243; // @[TLB.scala:170:77]
wire pma_checker__entries_T_242; // @[TLB.scala:170:77]
wire pma_checker__entries_T_241; // @[TLB.scala:170:77]
wire pma_checker__entries_T_240; // @[TLB.scala:170:77]
wire pma_checker__entries_T_239; // @[TLB.scala:170:77]
wire pma_checker__entries_T_238; // @[TLB.scala:170:77]
assign pma_checker__entries_T_238 = pma_checker__entries_WIRE_21[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_fragmented_superpage = pma_checker__entries_T_238; // @[TLB.scala:170:77]
assign pma_checker__entries_T_239 = pma_checker__entries_WIRE_21[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_c = pma_checker__entries_T_239; // @[TLB.scala:170:77]
assign pma_checker__entries_T_240 = pma_checker__entries_WIRE_21[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_eff = pma_checker__entries_T_240; // @[TLB.scala:170:77]
assign pma_checker__entries_T_241 = pma_checker__entries_WIRE_21[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_paa = pma_checker__entries_T_241; // @[TLB.scala:170:77]
assign pma_checker__entries_T_242 = pma_checker__entries_WIRE_21[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_pal = pma_checker__entries_T_242; // @[TLB.scala:170:77]
assign pma_checker__entries_T_243 = pma_checker__entries_WIRE_21[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_ppp = pma_checker__entries_T_243; // @[TLB.scala:170:77]
assign pma_checker__entries_T_244 = pma_checker__entries_WIRE_21[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_pr = pma_checker__entries_T_244; // @[TLB.scala:170:77]
assign pma_checker__entries_T_245 = pma_checker__entries_WIRE_21[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_px = pma_checker__entries_T_245; // @[TLB.scala:170:77]
assign pma_checker__entries_T_246 = pma_checker__entries_WIRE_21[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_pw = pma_checker__entries_T_246; // @[TLB.scala:170:77]
assign pma_checker__entries_T_247 = pma_checker__entries_WIRE_21[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_hr = pma_checker__entries_T_247; // @[TLB.scala:170:77]
assign pma_checker__entries_T_248 = pma_checker__entries_WIRE_21[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_hx = pma_checker__entries_T_248; // @[TLB.scala:170:77]
assign pma_checker__entries_T_249 = pma_checker__entries_WIRE_21[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_hw = pma_checker__entries_T_249; // @[TLB.scala:170:77]
assign pma_checker__entries_T_250 = pma_checker__entries_WIRE_21[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_sr = pma_checker__entries_T_250; // @[TLB.scala:170:77]
assign pma_checker__entries_T_251 = pma_checker__entries_WIRE_21[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_sx = pma_checker__entries_T_251; // @[TLB.scala:170:77]
assign pma_checker__entries_T_252 = pma_checker__entries_WIRE_21[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_sw = pma_checker__entries_T_252; // @[TLB.scala:170:77]
assign pma_checker__entries_T_253 = pma_checker__entries_WIRE_21[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_gf = pma_checker__entries_T_253; // @[TLB.scala:170:77]
assign pma_checker__entries_T_254 = pma_checker__entries_WIRE_21[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_pf = pma_checker__entries_T_254; // @[TLB.scala:170:77]
assign pma_checker__entries_T_255 = pma_checker__entries_WIRE_21[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_ae_stage2 = pma_checker__entries_T_255; // @[TLB.scala:170:77]
assign pma_checker__entries_T_256 = pma_checker__entries_WIRE_21[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_ae_final = pma_checker__entries_T_256; // @[TLB.scala:170:77]
assign pma_checker__entries_T_257 = pma_checker__entries_WIRE_21[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_ae_ptw = pma_checker__entries_T_257; // @[TLB.scala:170:77]
assign pma_checker__entries_T_258 = pma_checker__entries_WIRE_21[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_g = pma_checker__entries_T_258; // @[TLB.scala:170:77]
assign pma_checker__entries_T_259 = pma_checker__entries_WIRE_21[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_u = pma_checker__entries_T_259; // @[TLB.scala:170:77]
assign pma_checker__entries_T_260 = pma_checker__entries_WIRE_21[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_20_ppn = pma_checker__entries_T_260; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_283; // @[TLB.scala:170:77]
wire pma_checker__entries_T_282; // @[TLB.scala:170:77]
wire pma_checker__entries_T_281; // @[TLB.scala:170:77]
wire pma_checker__entries_T_280; // @[TLB.scala:170:77]
wire pma_checker__entries_T_279; // @[TLB.scala:170:77]
wire pma_checker__entries_T_278; // @[TLB.scala:170:77]
wire pma_checker__entries_T_277; // @[TLB.scala:170:77]
wire pma_checker__entries_T_276; // @[TLB.scala:170:77]
wire pma_checker__entries_T_275; // @[TLB.scala:170:77]
wire pma_checker__entries_T_274; // @[TLB.scala:170:77]
wire pma_checker__entries_T_273; // @[TLB.scala:170:77]
wire pma_checker__entries_T_272; // @[TLB.scala:170:77]
wire pma_checker__entries_T_271; // @[TLB.scala:170:77]
wire pma_checker__entries_T_270; // @[TLB.scala:170:77]
wire pma_checker__entries_T_269; // @[TLB.scala:170:77]
wire pma_checker__entries_T_268; // @[TLB.scala:170:77]
wire pma_checker__entries_T_267; // @[TLB.scala:170:77]
wire pma_checker__entries_T_266; // @[TLB.scala:170:77]
wire pma_checker__entries_T_265; // @[TLB.scala:170:77]
wire pma_checker__entries_T_264; // @[TLB.scala:170:77]
wire pma_checker__entries_T_263; // @[TLB.scala:170:77]
wire pma_checker__entries_T_262; // @[TLB.scala:170:77]
wire pma_checker__entries_T_261; // @[TLB.scala:170:77]
assign pma_checker__entries_T_261 = pma_checker__entries_WIRE_23[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_fragmented_superpage = pma_checker__entries_T_261; // @[TLB.scala:170:77]
assign pma_checker__entries_T_262 = pma_checker__entries_WIRE_23[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_c = pma_checker__entries_T_262; // @[TLB.scala:170:77]
assign pma_checker__entries_T_263 = pma_checker__entries_WIRE_23[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_eff = pma_checker__entries_T_263; // @[TLB.scala:170:77]
assign pma_checker__entries_T_264 = pma_checker__entries_WIRE_23[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_paa = pma_checker__entries_T_264; // @[TLB.scala:170:77]
assign pma_checker__entries_T_265 = pma_checker__entries_WIRE_23[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_pal = pma_checker__entries_T_265; // @[TLB.scala:170:77]
assign pma_checker__entries_T_266 = pma_checker__entries_WIRE_23[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_ppp = pma_checker__entries_T_266; // @[TLB.scala:170:77]
assign pma_checker__entries_T_267 = pma_checker__entries_WIRE_23[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_pr = pma_checker__entries_T_267; // @[TLB.scala:170:77]
assign pma_checker__entries_T_268 = pma_checker__entries_WIRE_23[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_px = pma_checker__entries_T_268; // @[TLB.scala:170:77]
assign pma_checker__entries_T_269 = pma_checker__entries_WIRE_23[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_pw = pma_checker__entries_T_269; // @[TLB.scala:170:77]
assign pma_checker__entries_T_270 = pma_checker__entries_WIRE_23[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_hr = pma_checker__entries_T_270; // @[TLB.scala:170:77]
assign pma_checker__entries_T_271 = pma_checker__entries_WIRE_23[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_hx = pma_checker__entries_T_271; // @[TLB.scala:170:77]
assign pma_checker__entries_T_272 = pma_checker__entries_WIRE_23[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_hw = pma_checker__entries_T_272; // @[TLB.scala:170:77]
assign pma_checker__entries_T_273 = pma_checker__entries_WIRE_23[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_sr = pma_checker__entries_T_273; // @[TLB.scala:170:77]
assign pma_checker__entries_T_274 = pma_checker__entries_WIRE_23[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_sx = pma_checker__entries_T_274; // @[TLB.scala:170:77]
assign pma_checker__entries_T_275 = pma_checker__entries_WIRE_23[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_sw = pma_checker__entries_T_275; // @[TLB.scala:170:77]
assign pma_checker__entries_T_276 = pma_checker__entries_WIRE_23[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_gf = pma_checker__entries_T_276; // @[TLB.scala:170:77]
assign pma_checker__entries_T_277 = pma_checker__entries_WIRE_23[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_pf = pma_checker__entries_T_277; // @[TLB.scala:170:77]
assign pma_checker__entries_T_278 = pma_checker__entries_WIRE_23[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_ae_stage2 = pma_checker__entries_T_278; // @[TLB.scala:170:77]
assign pma_checker__entries_T_279 = pma_checker__entries_WIRE_23[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_ae_final = pma_checker__entries_T_279; // @[TLB.scala:170:77]
assign pma_checker__entries_T_280 = pma_checker__entries_WIRE_23[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_ae_ptw = pma_checker__entries_T_280; // @[TLB.scala:170:77]
assign pma_checker__entries_T_281 = pma_checker__entries_WIRE_23[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_g = pma_checker__entries_T_281; // @[TLB.scala:170:77]
assign pma_checker__entries_T_282 = pma_checker__entries_WIRE_23[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_u = pma_checker__entries_T_282; // @[TLB.scala:170:77]
assign pma_checker__entries_T_283 = pma_checker__entries_WIRE_23[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_22_ppn = pma_checker__entries_T_283; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_306; // @[TLB.scala:170:77]
wire pma_checker__entries_T_305; // @[TLB.scala:170:77]
wire pma_checker__entries_T_304; // @[TLB.scala:170:77]
wire pma_checker__entries_T_303; // @[TLB.scala:170:77]
wire pma_checker__entries_T_302; // @[TLB.scala:170:77]
wire pma_checker__entries_T_301; // @[TLB.scala:170:77]
wire pma_checker__entries_T_300; // @[TLB.scala:170:77]
wire pma_checker__entries_T_299; // @[TLB.scala:170:77]
wire pma_checker__entries_T_298; // @[TLB.scala:170:77]
wire pma_checker__entries_T_297; // @[TLB.scala:170:77]
wire pma_checker__entries_T_296; // @[TLB.scala:170:77]
wire pma_checker__entries_T_295; // @[TLB.scala:170:77]
wire pma_checker__entries_T_294; // @[TLB.scala:170:77]
wire pma_checker__entries_T_293; // @[TLB.scala:170:77]
wire pma_checker__entries_T_292; // @[TLB.scala:170:77]
wire pma_checker__entries_T_291; // @[TLB.scala:170:77]
wire pma_checker__entries_T_290; // @[TLB.scala:170:77]
wire pma_checker__entries_T_289; // @[TLB.scala:170:77]
wire pma_checker__entries_T_288; // @[TLB.scala:170:77]
wire pma_checker__entries_T_287; // @[TLB.scala:170:77]
wire pma_checker__entries_T_286; // @[TLB.scala:170:77]
wire pma_checker__entries_T_285; // @[TLB.scala:170:77]
wire pma_checker__entries_T_284; // @[TLB.scala:170:77]
assign pma_checker__entries_T_284 = pma_checker__entries_WIRE_25[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_fragmented_superpage = pma_checker__entries_T_284; // @[TLB.scala:170:77]
assign pma_checker__entries_T_285 = pma_checker__entries_WIRE_25[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_c = pma_checker__entries_T_285; // @[TLB.scala:170:77]
assign pma_checker__entries_T_286 = pma_checker__entries_WIRE_25[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_eff = pma_checker__entries_T_286; // @[TLB.scala:170:77]
assign pma_checker__entries_T_287 = pma_checker__entries_WIRE_25[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_paa = pma_checker__entries_T_287; // @[TLB.scala:170:77]
assign pma_checker__entries_T_288 = pma_checker__entries_WIRE_25[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_pal = pma_checker__entries_T_288; // @[TLB.scala:170:77]
assign pma_checker__entries_T_289 = pma_checker__entries_WIRE_25[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_ppp = pma_checker__entries_T_289; // @[TLB.scala:170:77]
assign pma_checker__entries_T_290 = pma_checker__entries_WIRE_25[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_pr = pma_checker__entries_T_290; // @[TLB.scala:170:77]
assign pma_checker__entries_T_291 = pma_checker__entries_WIRE_25[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_px = pma_checker__entries_T_291; // @[TLB.scala:170:77]
assign pma_checker__entries_T_292 = pma_checker__entries_WIRE_25[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_pw = pma_checker__entries_T_292; // @[TLB.scala:170:77]
assign pma_checker__entries_T_293 = pma_checker__entries_WIRE_25[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_hr = pma_checker__entries_T_293; // @[TLB.scala:170:77]
assign pma_checker__entries_T_294 = pma_checker__entries_WIRE_25[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_hx = pma_checker__entries_T_294; // @[TLB.scala:170:77]
assign pma_checker__entries_T_295 = pma_checker__entries_WIRE_25[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_hw = pma_checker__entries_T_295; // @[TLB.scala:170:77]
assign pma_checker__entries_T_296 = pma_checker__entries_WIRE_25[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_sr = pma_checker__entries_T_296; // @[TLB.scala:170:77]
assign pma_checker__entries_T_297 = pma_checker__entries_WIRE_25[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_sx = pma_checker__entries_T_297; // @[TLB.scala:170:77]
assign pma_checker__entries_T_298 = pma_checker__entries_WIRE_25[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_sw = pma_checker__entries_T_298; // @[TLB.scala:170:77]
assign pma_checker__entries_T_299 = pma_checker__entries_WIRE_25[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_gf = pma_checker__entries_T_299; // @[TLB.scala:170:77]
assign pma_checker__entries_T_300 = pma_checker__entries_WIRE_25[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_pf = pma_checker__entries_T_300; // @[TLB.scala:170:77]
assign pma_checker__entries_T_301 = pma_checker__entries_WIRE_25[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_ae_stage2 = pma_checker__entries_T_301; // @[TLB.scala:170:77]
assign pma_checker__entries_T_302 = pma_checker__entries_WIRE_25[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_ae_final = pma_checker__entries_T_302; // @[TLB.scala:170:77]
assign pma_checker__entries_T_303 = pma_checker__entries_WIRE_25[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_ae_ptw = pma_checker__entries_T_303; // @[TLB.scala:170:77]
assign pma_checker__entries_T_304 = pma_checker__entries_WIRE_25[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_g = pma_checker__entries_T_304; // @[TLB.scala:170:77]
assign pma_checker__entries_T_305 = pma_checker__entries_WIRE_25[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_u = pma_checker__entries_T_305; // @[TLB.scala:170:77]
assign pma_checker__entries_T_306 = pma_checker__entries_WIRE_25[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_24_ppn = pma_checker__entries_T_306; // @[TLB.scala:170:77]
wire [1:0] pma_checker_ppn_res = _pma_checker_entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25]
wire pma_checker_ppn_ignore = pma_checker__ppn_ignore_T; // @[TLB.scala:197:{28,34}]
wire [26:0] pma_checker__ppn_T_1 = pma_checker_ppn_ignore ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] pma_checker__ppn_T_2 = {pma_checker__ppn_T_1[26:20], pma_checker__ppn_T_1[19:0] | _pma_checker_entries_barrier_8_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_3 = pma_checker__ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] pma_checker__ppn_T_4 = {pma_checker_ppn_res, pma_checker__ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}]
wire [26:0] pma_checker__ppn_T_6 = {pma_checker__ppn_T_5[26:20], pma_checker__ppn_T_5[19:0] | _pma_checker_entries_barrier_8_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_7 = pma_checker__ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] pma_checker__ppn_T_8 = {pma_checker__ppn_T_4, pma_checker__ppn_T_7}; // @[TLB.scala:198:{18,58}]
wire [1:0] pma_checker_ppn_res_1 = _pma_checker_entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25]
wire pma_checker_ppn_ignore_2 = pma_checker__ppn_ignore_T_2; // @[TLB.scala:197:{28,34}]
wire [26:0] pma_checker__ppn_T_9 = pma_checker_ppn_ignore_2 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] pma_checker__ppn_T_10 = {pma_checker__ppn_T_9[26:20], pma_checker__ppn_T_9[19:0] | _pma_checker_entries_barrier_9_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_11 = pma_checker__ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] pma_checker__ppn_T_12 = {pma_checker_ppn_res_1, pma_checker__ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}]
wire [26:0] pma_checker__ppn_T_14 = {pma_checker__ppn_T_13[26:20], pma_checker__ppn_T_13[19:0] | _pma_checker_entries_barrier_9_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_15 = pma_checker__ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] pma_checker__ppn_T_16 = {pma_checker__ppn_T_12, pma_checker__ppn_T_15}; // @[TLB.scala:198:{18,58}]
wire [1:0] pma_checker_ppn_res_2 = _pma_checker_entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25]
wire pma_checker_ppn_ignore_4 = pma_checker__ppn_ignore_T_4; // @[TLB.scala:197:{28,34}]
wire [26:0] pma_checker__ppn_T_17 = pma_checker_ppn_ignore_4 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] pma_checker__ppn_T_18 = {pma_checker__ppn_T_17[26:20], pma_checker__ppn_T_17[19:0] | _pma_checker_entries_barrier_10_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_19 = pma_checker__ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] pma_checker__ppn_T_20 = {pma_checker_ppn_res_2, pma_checker__ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}]
wire [26:0] pma_checker__ppn_T_22 = {pma_checker__ppn_T_21[26:20], pma_checker__ppn_T_21[19:0] | _pma_checker_entries_barrier_10_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_23 = pma_checker__ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] pma_checker__ppn_T_24 = {pma_checker__ppn_T_20, pma_checker__ppn_T_23}; // @[TLB.scala:198:{18,58}]
wire [1:0] pma_checker_ppn_res_3 = _pma_checker_entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25]
wire pma_checker_ppn_ignore_6 = pma_checker__ppn_ignore_T_6; // @[TLB.scala:197:{28,34}]
wire [26:0] pma_checker__ppn_T_25 = pma_checker_ppn_ignore_6 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] pma_checker__ppn_T_26 = {pma_checker__ppn_T_25[26:20], pma_checker__ppn_T_25[19:0] | _pma_checker_entries_barrier_11_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_27 = pma_checker__ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] pma_checker__ppn_T_28 = {pma_checker_ppn_res_3, pma_checker__ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}]
wire [26:0] pma_checker__ppn_T_30 = {pma_checker__ppn_T_29[26:20], pma_checker__ppn_T_29[19:0] | _pma_checker_entries_barrier_11_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_31 = pma_checker__ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] pma_checker__ppn_T_32 = {pma_checker__ppn_T_28, pma_checker__ppn_T_31}; // @[TLB.scala:198:{18,58}]
wire [1:0] pma_checker_ppn_res_4 = _pma_checker_entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25]
wire [26:0] pma_checker__ppn_T_34 = {pma_checker__ppn_T_33[26:20], pma_checker__ppn_T_33[19:0] | _pma_checker_entries_barrier_12_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_35 = pma_checker__ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] pma_checker__ppn_T_36 = {pma_checker_ppn_res_4, pma_checker__ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}]
wire [26:0] pma_checker__ppn_T_38 = {pma_checker__ppn_T_37[26:20], pma_checker__ppn_T_37[19:0] | _pma_checker_entries_barrier_12_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] pma_checker__ppn_T_39 = pma_checker__ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] pma_checker__ppn_T_40 = {pma_checker__ppn_T_36, pma_checker__ppn_T_39}; // @[TLB.scala:198:{18,58}]
wire [19:0] pma_checker__ppn_T_41 = pma_checker_vpn[19:0]; // @[TLB.scala:335:30, :502:125]
wire [19:0] pma_checker__ppn_T_55 = pma_checker__ppn_T_41; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_68 = pma_checker__ppn_T_55; // @[Mux.scala:30:73]
wire [19:0] pma_checker_ppn = pma_checker__ppn_T_68; // @[Mux.scala:30:73]
wire [1:0] pma_checker_ptw_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_ptw, _pma_checker_entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_ae_array_lo_lo = {pma_checker_ptw_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_ptw, _pma_checker_entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_ae_array_lo_hi = {pma_checker_ptw_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_ptw_ae_array_lo = {pma_checker_ptw_ae_array_lo_hi, pma_checker_ptw_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_ptw_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_ptw, _pma_checker_entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_ae_array_hi_lo = {pma_checker_ptw_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_ptw, _pma_checker_entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_ptw, _pma_checker_entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_ptw_ae_array_hi_hi = {pma_checker_ptw_ae_array_hi_hi_hi, pma_checker_ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_ptw_ae_array_hi = {pma_checker_ptw_ae_array_hi_hi, pma_checker_ptw_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__ptw_ae_array_T = {pma_checker_ptw_ae_array_hi, pma_checker_ptw_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_ptw_ae_array = {1'h0, pma_checker__ptw_ae_array_T}; // @[package.scala:45:27]
wire [1:0] pma_checker_final_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_final, _pma_checker_entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_final_ae_array_lo_lo = {pma_checker_final_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_final_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_final, _pma_checker_entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_final_ae_array_lo_hi = {pma_checker_final_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_final_ae_array_lo = {pma_checker_final_ae_array_lo_hi, pma_checker_final_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_final_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_final, _pma_checker_entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_final_ae_array_hi_lo = {pma_checker_final_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_final_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_final, _pma_checker_entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_final_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_final, _pma_checker_entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_final_ae_array_hi_hi = {pma_checker_final_ae_array_hi_hi_hi, pma_checker_final_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_final_ae_array_hi = {pma_checker_final_ae_array_hi_hi, pma_checker_final_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__final_ae_array_T = {pma_checker_final_ae_array_hi, pma_checker_final_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_final_ae_array = {1'h0, pma_checker__final_ae_array_T}; // @[package.scala:45:27]
wire [1:0] pma_checker_ptw_pf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pf, _pma_checker_entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_pf_array_lo_lo = {pma_checker_ptw_pf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_pf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pf, _pma_checker_entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_pf_array_lo_hi = {pma_checker_ptw_pf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_ptw_pf_array_lo = {pma_checker_ptw_pf_array_lo_hi, pma_checker_ptw_pf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_ptw_pf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pf, _pma_checker_entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_pf_array_hi_lo = {pma_checker_ptw_pf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_pf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_pf, _pma_checker_entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_pf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_pf, _pma_checker_entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_ptw_pf_array_hi_hi = {pma_checker_ptw_pf_array_hi_hi_hi, pma_checker_ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_ptw_pf_array_hi = {pma_checker_ptw_pf_array_hi_hi, pma_checker_ptw_pf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__ptw_pf_array_T = {pma_checker_ptw_pf_array_hi, pma_checker_ptw_pf_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_ptw_pf_array = {1'h0, pma_checker__ptw_pf_array_T}; // @[package.scala:45:27]
wire [1:0] pma_checker_ptw_gf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_gf, _pma_checker_entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_gf_array_lo_lo = {pma_checker_ptw_gf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_gf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_gf, _pma_checker_entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_gf_array_lo_hi = {pma_checker_ptw_gf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_ptw_gf_array_lo = {pma_checker_ptw_gf_array_lo_hi, pma_checker_ptw_gf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_ptw_gf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_gf, _pma_checker_entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_gf_array_hi_lo = {pma_checker_ptw_gf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_gf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_gf, _pma_checker_entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_gf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_gf, _pma_checker_entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_ptw_gf_array_hi_hi = {pma_checker_ptw_gf_array_hi_hi_hi, pma_checker_ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_ptw_gf_array_hi = {pma_checker_ptw_gf_array_hi_hi, pma_checker_ptw_gf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__ptw_gf_array_T = {pma_checker_ptw_gf_array_hi, pma_checker_ptw_gf_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_ptw_gf_array = {1'h0, pma_checker__ptw_gf_array_T}; // @[package.scala:45:27]
wire [13:0] pma_checker__gf_ld_array_T_3 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :600:82]
wire [13:0] pma_checker__gf_st_array_T_2 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :601:63]
wire [13:0] pma_checker__gf_inst_array_T_1 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :602:46]
wire pma_checker__priv_rw_ok_T = ~pma_checker_priv_s; // @[TLB.scala:370:20, :513:24]
wire pma_checker__priv_rw_ok_T_1 = pma_checker__priv_rw_ok_T; // @[TLB.scala:513:{24,32}]
wire [1:0] _GEN_7 = {_pma_checker_entries_barrier_2_io_y_u, _pma_checker_entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_lo_lo_hi = _GEN_7; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_lo_lo_hi_1 = _GEN_7; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_lo_lo_hi = _GEN_7; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_lo_lo_hi_1 = _GEN_7; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_rw_ok_lo_lo = {pma_checker_priv_rw_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_8 = {_pma_checker_entries_barrier_5_io_y_u, _pma_checker_entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_lo_hi_hi = _GEN_8; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_lo_hi_hi_1 = _GEN_8; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_lo_hi_hi = _GEN_8; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_lo_hi_hi_1 = _GEN_8; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_rw_ok_lo_hi = {pma_checker_priv_rw_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_priv_rw_ok_lo = {pma_checker_priv_rw_ok_lo_hi, pma_checker_priv_rw_ok_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_9 = {_pma_checker_entries_barrier_8_io_y_u, _pma_checker_entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_lo_hi = _GEN_9; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_lo_hi_1 = _GEN_9; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_lo_hi = _GEN_9; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_lo_hi_1 = _GEN_9; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_rw_ok_hi_lo = {pma_checker_priv_rw_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_10 = {_pma_checker_entries_barrier_10_io_y_u, _pma_checker_entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_hi_lo = _GEN_10; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_hi_lo_1 = _GEN_10; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_hi_lo; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_hi_lo = _GEN_10; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_hi_lo_1 = _GEN_10; // @[package.scala:45:27]
wire [1:0] _GEN_11 = {_pma_checker_entries_barrier_12_io_y_u, _pma_checker_entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_hi_hi = _GEN_11; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_hi_hi_1 = _GEN_11; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_hi_hi = _GEN_11; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_hi_hi_1 = _GEN_11; // @[package.scala:45:27]
wire [3:0] pma_checker_priv_rw_ok_hi_hi = {pma_checker_priv_rw_ok_hi_hi_hi, pma_checker_priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_priv_rw_ok_hi = {pma_checker_priv_rw_ok_hi_hi, pma_checker_priv_rw_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_rw_ok_T_2 = {pma_checker_priv_rw_ok_hi, pma_checker_priv_rw_ok_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_rw_ok_T_3 = pma_checker__priv_rw_ok_T_1 ? pma_checker__priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_rw_ok_lo_lo_1 = {pma_checker_priv_rw_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_priv_rw_ok_lo_hi_1 = {pma_checker_priv_rw_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_priv_rw_ok_lo_1 = {pma_checker_priv_rw_ok_lo_hi_1, pma_checker_priv_rw_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_rw_ok_hi_lo_1 = {pma_checker_priv_rw_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_priv_rw_ok_hi_hi_1 = {pma_checker_priv_rw_ok_hi_hi_hi_1, pma_checker_priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] pma_checker_priv_rw_ok_hi_1 = {pma_checker_priv_rw_ok_hi_hi_1, pma_checker_priv_rw_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_rw_ok_T_4 = {pma_checker_priv_rw_ok_hi_1, pma_checker_priv_rw_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_rw_ok_T_5 = ~pma_checker__priv_rw_ok_T_4; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_rw_ok_T_6 = pma_checker_priv_s ? pma_checker__priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}]
wire [12:0] pma_checker_priv_rw_ok = pma_checker__priv_rw_ok_T_3 | pma_checker__priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}]
wire [2:0] pma_checker_priv_x_ok_lo_lo = {pma_checker_priv_x_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_priv_x_ok_lo_hi = {pma_checker_priv_x_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_priv_x_ok_lo = {pma_checker_priv_x_ok_lo_hi, pma_checker_priv_x_ok_lo_lo}; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_x_ok_hi_lo = {pma_checker_priv_x_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_priv_x_ok_hi_hi = {pma_checker_priv_x_ok_hi_hi_hi, pma_checker_priv_x_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_priv_x_ok_hi = {pma_checker_priv_x_ok_hi_hi, pma_checker_priv_x_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_x_ok_T = {pma_checker_priv_x_ok_hi, pma_checker_priv_x_ok_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_x_ok_T_1 = ~pma_checker__priv_x_ok_T; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_x_ok_lo_lo_1 = {pma_checker_priv_x_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_priv_x_ok_lo_hi_1 = {pma_checker_priv_x_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_priv_x_ok_lo_1 = {pma_checker_priv_x_ok_lo_hi_1, pma_checker_priv_x_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_x_ok_hi_lo_1 = {pma_checker_priv_x_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_priv_x_ok_hi_hi_1 = {pma_checker_priv_x_ok_hi_hi_hi_1, pma_checker_priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] pma_checker_priv_x_ok_hi_1 = {pma_checker_priv_x_ok_hi_hi_1, pma_checker_priv_x_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_x_ok_T_2 = {pma_checker_priv_x_ok_hi_1, pma_checker_priv_x_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker_priv_x_ok = pma_checker_priv_s ? pma_checker__priv_x_ok_T_1 : pma_checker__priv_x_ok_T_2; // @[package.scala:45:27]
wire [1:0] pma_checker_stage1_bypass_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_stage2, _pma_checker_entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_stage1_bypass_lo_lo = {pma_checker_stage1_bypass_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_stage1_bypass_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_stage2, _pma_checker_entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_stage1_bypass_lo_hi = {pma_checker_stage1_bypass_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_stage1_bypass_lo = {pma_checker_stage1_bypass_lo_hi, pma_checker_stage1_bypass_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_stage1_bypass_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_stage2, _pma_checker_entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_stage1_bypass_hi_lo = {pma_checker_stage1_bypass_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_stage1_bypass_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_stage2, _pma_checker_entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_stage1_bypass_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_stage2, _pma_checker_entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_stage1_bypass_hi_hi = {pma_checker_stage1_bypass_hi_hi_hi, pma_checker_stage1_bypass_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_stage1_bypass_hi = {pma_checker_stage1_bypass_hi_hi, pma_checker_stage1_bypass_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__stage1_bypass_T_3 = {pma_checker_stage1_bypass_hi, pma_checker_stage1_bypass_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_r_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sr, _pma_checker_entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_r_array_lo_lo = {pma_checker_r_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sr, _pma_checker_entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_r_array_lo_hi = {pma_checker_r_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_r_array_lo = {pma_checker_r_array_lo_hi, pma_checker_r_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_r_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sr, _pma_checker_entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_r_array_hi_lo = {pma_checker_r_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sr, _pma_checker_entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sr, _pma_checker_entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_r_array_hi_hi = {pma_checker_r_array_hi_hi_hi, pma_checker_r_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_r_array_hi = {pma_checker_r_array_hi_hi, pma_checker_r_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__r_array_T = {pma_checker_r_array_hi, pma_checker_r_array_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__r_array_T_3 = pma_checker__r_array_T; // @[package.scala:45:27]
wire [1:0] _GEN_12 = {_pma_checker_entries_barrier_2_io_y_sx, _pma_checker_entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_lo_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_r_array_lo_lo_hi_1 = _GEN_12; // @[package.scala:45:27]
wire [1:0] pma_checker_x_array_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_x_array_lo_lo_hi = _GEN_12; // @[package.scala:45:27]
wire [2:0] pma_checker_r_array_lo_lo_1 = {pma_checker_r_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_13 = {_pma_checker_entries_barrier_5_io_y_sx, _pma_checker_entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_lo_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_r_array_lo_hi_hi_1 = _GEN_13; // @[package.scala:45:27]
wire [1:0] pma_checker_x_array_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_x_array_lo_hi_hi = _GEN_13; // @[package.scala:45:27]
wire [2:0] pma_checker_r_array_lo_hi_1 = {pma_checker_r_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_r_array_lo_1 = {pma_checker_r_array_lo_hi_1, pma_checker_r_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_14 = {_pma_checker_entries_barrier_8_io_y_sx, _pma_checker_entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_hi_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_r_array_hi_lo_hi_1 = _GEN_14; // @[package.scala:45:27]
wire [1:0] pma_checker_x_array_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_x_array_hi_lo_hi = _GEN_14; // @[package.scala:45:27]
wire [2:0] pma_checker_r_array_hi_lo_1 = {pma_checker_r_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_15 = {_pma_checker_entries_barrier_10_io_y_sx, _pma_checker_entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_hi_hi_lo_1; // @[package.scala:45:27]
assign pma_checker_r_array_hi_hi_lo_1 = _GEN_15; // @[package.scala:45:27]
wire [1:0] pma_checker_x_array_hi_hi_lo; // @[package.scala:45:27]
assign pma_checker_x_array_hi_hi_lo = _GEN_15; // @[package.scala:45:27]
wire [1:0] _GEN_16 = {_pma_checker_entries_barrier_12_io_y_sx, _pma_checker_entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_hi_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_r_array_hi_hi_hi_1 = _GEN_16; // @[package.scala:45:27]
wire [1:0] pma_checker_x_array_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_x_array_hi_hi_hi = _GEN_16; // @[package.scala:45:27]
wire [3:0] pma_checker_r_array_hi_hi_1 = {pma_checker_r_array_hi_hi_hi_1, pma_checker_r_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] pma_checker_r_array_hi_1 = {pma_checker_r_array_hi_hi_1, pma_checker_r_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__r_array_T_1 = {pma_checker_r_array_hi_1, pma_checker_r_array_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__r_array_T_4 = pma_checker_priv_rw_ok & pma_checker__r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}]
wire [12:0] pma_checker__r_array_T_5 = pma_checker__r_array_T_4; // @[TLB.scala:520:{41,113}]
wire [13:0] pma_checker_r_array = {1'h1, pma_checker__r_array_T_5}; // @[TLB.scala:520:{20,113}]
wire [13:0] pma_checker__pf_ld_array_T = pma_checker_r_array; // @[TLB.scala:520:20, :597:41]
wire [1:0] pma_checker_w_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sw, _pma_checker_entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_w_array_lo_lo = {pma_checker_w_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_w_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sw, _pma_checker_entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_w_array_lo_hi = {pma_checker_w_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_w_array_lo = {pma_checker_w_array_lo_hi, pma_checker_w_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_w_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sw, _pma_checker_entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_w_array_hi_lo = {pma_checker_w_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_w_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sw, _pma_checker_entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_w_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sw, _pma_checker_entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_w_array_hi_hi = {pma_checker_w_array_hi_hi_hi, pma_checker_w_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_w_array_hi = {pma_checker_w_array_hi_hi, pma_checker_w_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__w_array_T = {pma_checker_w_array_hi, pma_checker_w_array_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__w_array_T_1 = pma_checker_priv_rw_ok & pma_checker__w_array_T; // @[package.scala:45:27]
wire [12:0] pma_checker__w_array_T_2 = pma_checker__w_array_T_1; // @[TLB.scala:521:{41,69}]
wire [13:0] pma_checker_w_array = {1'h1, pma_checker__w_array_T_2}; // @[TLB.scala:521:{20,69}]
wire [2:0] pma_checker_x_array_lo_lo = {pma_checker_x_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_x_array_lo_hi = {pma_checker_x_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_x_array_lo = {pma_checker_x_array_lo_hi, pma_checker_x_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] pma_checker_x_array_hi_lo = {pma_checker_x_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_x_array_hi_hi = {pma_checker_x_array_hi_hi_hi, pma_checker_x_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_x_array_hi = {pma_checker_x_array_hi_hi, pma_checker_x_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__x_array_T = {pma_checker_x_array_hi, pma_checker_x_array_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__x_array_T_1 = pma_checker_priv_x_ok & pma_checker__x_array_T; // @[package.scala:45:27]
wire [12:0] pma_checker__x_array_T_2 = pma_checker__x_array_T_1; // @[TLB.scala:522:{40,68}]
wire [13:0] pma_checker_x_array = {1'h1, pma_checker__x_array_T_2}; // @[TLB.scala:522:{20,68}]
wire [1:0] pma_checker_hr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hr, _pma_checker_entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hr_array_lo_lo = {pma_checker_hr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hr, _pma_checker_entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hr_array_lo_hi = {pma_checker_hr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_hr_array_lo = {pma_checker_hr_array_lo_hi, pma_checker_hr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_hr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hr, _pma_checker_entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hr_array_hi_lo = {pma_checker_hr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hr, _pma_checker_entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hr, _pma_checker_entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_hr_array_hi_hi = {pma_checker_hr_array_hi_hi_hi, pma_checker_hr_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_hr_array_hi = {pma_checker_hr_array_hi_hi, pma_checker_hr_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__hr_array_T = {pma_checker_hr_array_hi, pma_checker_hr_array_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__hr_array_T_3 = pma_checker__hr_array_T; // @[package.scala:45:27]
wire [1:0] _GEN_17 = {_pma_checker_entries_barrier_2_io_y_hx, _pma_checker_entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_lo_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_hr_array_lo_lo_hi_1 = _GEN_17; // @[package.scala:45:27]
wire [1:0] pma_checker_hx_array_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_hx_array_lo_lo_hi = _GEN_17; // @[package.scala:45:27]
wire [2:0] pma_checker_hr_array_lo_lo_1 = {pma_checker_hr_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_18 = {_pma_checker_entries_barrier_5_io_y_hx, _pma_checker_entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_lo_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_hr_array_lo_hi_hi_1 = _GEN_18; // @[package.scala:45:27]
wire [1:0] pma_checker_hx_array_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_hx_array_lo_hi_hi = _GEN_18; // @[package.scala:45:27]
wire [2:0] pma_checker_hr_array_lo_hi_1 = {pma_checker_hr_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_hr_array_lo_1 = {pma_checker_hr_array_lo_hi_1, pma_checker_hr_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_19 = {_pma_checker_entries_barrier_8_io_y_hx, _pma_checker_entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_hi_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_hr_array_hi_lo_hi_1 = _GEN_19; // @[package.scala:45:27]
wire [1:0] pma_checker_hx_array_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_hx_array_hi_lo_hi = _GEN_19; // @[package.scala:45:27]
wire [2:0] pma_checker_hr_array_hi_lo_1 = {pma_checker_hr_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_20 = {_pma_checker_entries_barrier_10_io_y_hx, _pma_checker_entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_hi_hi_lo_1; // @[package.scala:45:27]
assign pma_checker_hr_array_hi_hi_lo_1 = _GEN_20; // @[package.scala:45:27]
wire [1:0] pma_checker_hx_array_hi_hi_lo; // @[package.scala:45:27]
assign pma_checker_hx_array_hi_hi_lo = _GEN_20; // @[package.scala:45:27]
wire [1:0] _GEN_21 = {_pma_checker_entries_barrier_12_io_y_hx, _pma_checker_entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_hi_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_hr_array_hi_hi_hi_1 = _GEN_21; // @[package.scala:45:27]
wire [1:0] pma_checker_hx_array_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_hx_array_hi_hi_hi = _GEN_21; // @[package.scala:45:27]
wire [3:0] pma_checker_hr_array_hi_hi_1 = {pma_checker_hr_array_hi_hi_hi_1, pma_checker_hr_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] pma_checker_hr_array_hi_1 = {pma_checker_hr_array_hi_hi_1, pma_checker_hr_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__hr_array_T_1 = {pma_checker_hr_array_hi_1, pma_checker_hr_array_lo_1}; // @[package.scala:45:27]
wire [1:0] pma_checker_hw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hw, _pma_checker_entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hw_array_lo_lo = {pma_checker_hw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hw, _pma_checker_entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hw_array_lo_hi = {pma_checker_hw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_hw_array_lo = {pma_checker_hw_array_lo_hi, pma_checker_hw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_hw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hw, _pma_checker_entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hw_array_hi_lo = {pma_checker_hw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hw_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hw, _pma_checker_entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hw_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hw, _pma_checker_entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_hw_array_hi_hi = {pma_checker_hw_array_hi_hi_hi, pma_checker_hw_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_hw_array_hi = {pma_checker_hw_array_hi_hi, pma_checker_hw_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__hw_array_T = {pma_checker_hw_array_hi, pma_checker_hw_array_lo}; // @[package.scala:45:27]
wire [2:0] pma_checker_hx_array_lo_lo = {pma_checker_hx_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hx_array_lo_hi = {pma_checker_hx_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_hx_array_lo = {pma_checker_hx_array_lo_hi, pma_checker_hx_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] pma_checker_hx_array_hi_lo = {pma_checker_hx_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_hx_array_hi_hi = {pma_checker_hx_array_hi_hi_hi, pma_checker_hx_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_hx_array_hi = {pma_checker_hx_array_hi_hi, pma_checker_hx_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__hx_array_T = {pma_checker_hx_array_hi, pma_checker_hx_array_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker__pr_array_T = {2{pma_checker_prot_r}}; // @[TLB.scala:429:55, :529:26]
wire [1:0] pma_checker_pr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pr, _pma_checker_entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pr_array_lo_lo = {pma_checker_pr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pr, _pma_checker_entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pr_array_lo_hi = {pma_checker_pr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pr_array_lo = {pma_checker_pr_array_lo_hi, pma_checker_pr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_pr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pr, _pma_checker_entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pr_array_hi_lo = {pma_checker_pr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pr_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pr, _pma_checker_entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pr_array_hi_hi = {pma_checker_pr_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pr_array_hi = {pma_checker_pr_array_hi_hi, pma_checker_pr_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__pr_array_T_1 = {pma_checker_pr_array_hi, pma_checker_pr_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker__pr_array_T_2 = {pma_checker__pr_array_T, pma_checker__pr_array_T_1}; // @[package.scala:45:27]
wire [13:0] _GEN_22 = pma_checker_ptw_ae_array | pma_checker_final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104]
wire [13:0] pma_checker__pr_array_T_3; // @[TLB.scala:529:104]
assign pma_checker__pr_array_T_3 = _GEN_22; // @[TLB.scala:529:104]
wire [13:0] pma_checker__pw_array_T_3; // @[TLB.scala:531:104]
assign pma_checker__pw_array_T_3 = _GEN_22; // @[TLB.scala:529:104, :531:104]
wire [13:0] pma_checker__px_array_T_3; // @[TLB.scala:533:104]
assign pma_checker__px_array_T_3 = _GEN_22; // @[TLB.scala:529:104, :533:104]
wire [13:0] pma_checker__pr_array_T_4 = ~pma_checker__pr_array_T_3; // @[TLB.scala:529:{89,104}]
wire [13:0] pma_checker_pr_array = pma_checker__pr_array_T_2 & pma_checker__pr_array_T_4; // @[TLB.scala:529:{21,87,89}]
wire [1:0] pma_checker__pw_array_T = {2{pma_checker_prot_w}}; // @[TLB.scala:430:55, :531:26]
wire [1:0] pma_checker_pw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pw, _pma_checker_entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pw_array_lo_lo = {pma_checker_pw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pw, _pma_checker_entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pw_array_lo_hi = {pma_checker_pw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pw_array_lo = {pma_checker_pw_array_lo_hi, pma_checker_pw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_pw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pw, _pma_checker_entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pw_array_hi_lo = {pma_checker_pw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pw_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pw, _pma_checker_entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pw_array_hi_hi = {pma_checker_pw_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pw_array_hi = {pma_checker_pw_array_hi_hi, pma_checker_pw_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__pw_array_T_1 = {pma_checker_pw_array_hi, pma_checker_pw_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker__pw_array_T_2 = {pma_checker__pw_array_T, pma_checker__pw_array_T_1}; // @[package.scala:45:27]
wire [13:0] pma_checker__pw_array_T_4 = ~pma_checker__pw_array_T_3; // @[TLB.scala:531:{89,104}]
wire [13:0] pma_checker_pw_array = pma_checker__pw_array_T_2 & pma_checker__pw_array_T_4; // @[TLB.scala:531:{21,87,89}]
wire [1:0] pma_checker__px_array_T = {2{pma_checker_prot_x}}; // @[TLB.scala:434:55, :533:26]
wire [1:0] pma_checker_px_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_px, _pma_checker_entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_px_array_lo_lo = {pma_checker_px_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_px_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_px, _pma_checker_entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_px_array_lo_hi = {pma_checker_px_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_px_array_lo = {pma_checker_px_array_lo_hi, pma_checker_px_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_px_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_px, _pma_checker_entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_px_array_hi_lo = {pma_checker_px_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_px_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_px, _pma_checker_entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_px_array_hi_hi = {pma_checker_px_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_px_array_hi = {pma_checker_px_array_hi_hi, pma_checker_px_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__px_array_T_1 = {pma_checker_px_array_hi, pma_checker_px_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker__px_array_T_2 = {pma_checker__px_array_T, pma_checker__px_array_T_1}; // @[package.scala:45:27]
wire [13:0] pma_checker__px_array_T_4 = ~pma_checker__px_array_T_3; // @[TLB.scala:533:{89,104}]
wire [13:0] pma_checker_px_array = pma_checker__px_array_T_2 & pma_checker__px_array_T_4; // @[TLB.scala:533:{21,87,89}]
wire [1:0] pma_checker__eff_array_T = {2{_pma_checker_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27]
wire [1:0] pma_checker_eff_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_eff, _pma_checker_entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_eff_array_lo_lo = {pma_checker_eff_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_eff_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_eff, _pma_checker_entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_eff_array_lo_hi = {pma_checker_eff_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_eff_array_lo = {pma_checker_eff_array_lo_hi, pma_checker_eff_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_eff_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_eff, _pma_checker_entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_eff_array_hi_lo = {pma_checker_eff_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_eff_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_eff, _pma_checker_entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_eff_array_hi_hi = {pma_checker_eff_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_eff_array_hi = {pma_checker_eff_array_hi_hi, pma_checker_eff_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__eff_array_T_1 = {pma_checker_eff_array_hi, pma_checker_eff_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_eff_array = {pma_checker__eff_array_T, pma_checker__eff_array_T_1}; // @[package.scala:45:27]
wire [1:0] pma_checker__c_array_T = {2{pma_checker_cacheable}}; // @[TLB.scala:425:41, :537:25]
wire [1:0] _GEN_23 = {_pma_checker_entries_barrier_2_io_y_c, _pma_checker_entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_c_array_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_c_array_lo_lo_hi = _GEN_23; // @[package.scala:45:27]
wire [1:0] pma_checker_prefetchable_array_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_prefetchable_array_lo_lo_hi = _GEN_23; // @[package.scala:45:27]
wire [2:0] pma_checker_c_array_lo_lo = {pma_checker_c_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_24 = {_pma_checker_entries_barrier_5_io_y_c, _pma_checker_entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_c_array_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_c_array_lo_hi_hi = _GEN_24; // @[package.scala:45:27]
wire [1:0] pma_checker_prefetchable_array_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_prefetchable_array_lo_hi_hi = _GEN_24; // @[package.scala:45:27]
wire [2:0] pma_checker_c_array_lo_hi = {pma_checker_c_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_c_array_lo = {pma_checker_c_array_lo_hi, pma_checker_c_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_25 = {_pma_checker_entries_barrier_8_io_y_c, _pma_checker_entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_c_array_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_c_array_hi_lo_hi = _GEN_25; // @[package.scala:45:27]
wire [1:0] pma_checker_prefetchable_array_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_prefetchable_array_hi_lo_hi = _GEN_25; // @[package.scala:45:27]
wire [2:0] pma_checker_c_array_hi_lo = {pma_checker_c_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_26 = {_pma_checker_entries_barrier_11_io_y_c, _pma_checker_entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_c_array_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_c_array_hi_hi_hi = _GEN_26; // @[package.scala:45:27]
wire [1:0] pma_checker_prefetchable_array_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_prefetchable_array_hi_hi_hi = _GEN_26; // @[package.scala:45:27]
wire [2:0] pma_checker_c_array_hi_hi = {pma_checker_c_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_c_array_hi = {pma_checker_c_array_hi_hi, pma_checker_c_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__c_array_T_1 = {pma_checker_c_array_hi, pma_checker_c_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_c_array = {pma_checker__c_array_T, pma_checker__c_array_T_1}; // @[package.scala:45:27]
wire [13:0] pma_checker_lrscAllowed = pma_checker_c_array; // @[TLB.scala:537:20, :580:24]
wire [1:0] pma_checker__ppp_array_T = {2{_pma_checker_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27]
wire [1:0] pma_checker_ppp_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ppp, _pma_checker_entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ppp_array_lo_lo = {pma_checker_ppp_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ppp_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ppp, _pma_checker_entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ppp_array_lo_hi = {pma_checker_ppp_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_ppp_array_lo = {pma_checker_ppp_array_lo_hi, pma_checker_ppp_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_ppp_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ppp, _pma_checker_entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ppp_array_hi_lo = {pma_checker_ppp_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ppp_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_ppp, _pma_checker_entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ppp_array_hi_hi = {pma_checker_ppp_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_ppp_array_hi = {pma_checker_ppp_array_hi_hi, pma_checker_ppp_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__ppp_array_T_1 = {pma_checker_ppp_array_hi, pma_checker_ppp_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_ppp_array = {pma_checker__ppp_array_T, pma_checker__ppp_array_T_1}; // @[package.scala:45:27]
wire [1:0] pma_checker__paa_array_T = {2{_pma_checker_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27]
wire [1:0] pma_checker_paa_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_paa, _pma_checker_entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_paa_array_lo_lo = {pma_checker_paa_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_paa_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_paa, _pma_checker_entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_paa_array_lo_hi = {pma_checker_paa_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_paa_array_lo = {pma_checker_paa_array_lo_hi, pma_checker_paa_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_paa_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_paa, _pma_checker_entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_paa_array_hi_lo = {pma_checker_paa_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_paa_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_paa, _pma_checker_entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_paa_array_hi_hi = {pma_checker_paa_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_paa_array_hi = {pma_checker_paa_array_hi_hi, pma_checker_paa_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__paa_array_T_1 = {pma_checker_paa_array_hi, pma_checker_paa_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_paa_array = {pma_checker__paa_array_T, pma_checker__paa_array_T_1}; // @[package.scala:45:27]
wire [13:0] pma_checker_paa_array_if_cached = pma_checker_paa_array; // @[TLB.scala:541:22, :545:39]
wire [1:0] pma_checker__pal_array_T = {2{_pma_checker_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27]
wire [1:0] pma_checker_pal_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pal, _pma_checker_entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pal_array_lo_lo = {pma_checker_pal_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pal_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pal, _pma_checker_entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pal_array_lo_hi = {pma_checker_pal_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pal_array_lo = {pma_checker_pal_array_lo_hi, pma_checker_pal_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_pal_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pal, _pma_checker_entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pal_array_hi_lo = {pma_checker_pal_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pal_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pal, _pma_checker_entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pal_array_hi_hi = {pma_checker_pal_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pal_array_hi = {pma_checker_pal_array_hi_hi, pma_checker_pal_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__pal_array_T_1 = {pma_checker_pal_array_hi, pma_checker_pal_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_pal_array = {pma_checker__pal_array_T, pma_checker__pal_array_T_1}; // @[package.scala:45:27]
wire [13:0] pma_checker_pal_array_if_cached = pma_checker_pal_array; // @[TLB.scala:543:22, :546:39]
wire [13:0] pma_checker_ppp_array_if_cached = pma_checker_ppp_array | pma_checker_c_array; // @[TLB.scala:537:20, :539:22, :544:39]
wire pma_checker__prefetchable_array_T = pma_checker_cacheable & pma_checker_homogeneous; // @[TLBPermissions.scala:101:65]
wire [1:0] pma_checker__prefetchable_array_T_1 = {pma_checker__prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}]
wire [2:0] pma_checker_prefetchable_array_lo_lo = {pma_checker_prefetchable_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_prefetchable_array_lo_hi = {pma_checker_prefetchable_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_prefetchable_array_lo = {pma_checker_prefetchable_array_lo_hi, pma_checker_prefetchable_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] pma_checker_prefetchable_array_hi_lo = {pma_checker_prefetchable_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_prefetchable_array_hi_hi = {pma_checker_prefetchable_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_prefetchable_array_hi = {pma_checker_prefetchable_array_hi_hi, pma_checker_prefetchable_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__prefetchable_array_T_2 = {pma_checker_prefetchable_array_hi, pma_checker_prefetchable_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_prefetchable_array = {pma_checker__prefetchable_array_T_1, pma_checker__prefetchable_array_T_2}; // @[package.scala:45:27]
wire [3:0] pma_checker__misaligned_T = 4'h1 << pma_checker_io_req_bits_size; // @[OneHot.scala:58:35]
wire [4:0] pma_checker__misaligned_T_1 = {1'h0, pma_checker__misaligned_T} - 5'h1; // @[OneHot.scala:58:35]
wire [3:0] pma_checker__misaligned_T_2 = pma_checker__misaligned_T_1[3:0]; // @[TLB.scala:550:69]
wire [39:0] pma_checker__misaligned_T_3 = {36'h0, pma_checker_io_req_bits_vaddr[3:0] & pma_checker__misaligned_T_2}; // @[TLB.scala:550:{39,69}]
wire pma_checker_misaligned = |pma_checker__misaligned_T_3; // @[TLB.scala:550:{39,77}]
wire [39:0] pma_checker_bad_va_maskedVAddr = pma_checker_io_req_bits_vaddr & 40'hC000000000; // @[TLB.scala:559:43]
wire pma_checker__bad_va_T_2 = pma_checker_bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51]
wire pma_checker__bad_va_T_3 = pma_checker_bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86]
wire pma_checker__bad_va_T_4 = pma_checker__bad_va_T_3; // @[TLB.scala:560:{71,86}]
wire pma_checker__bad_va_T_5 = pma_checker__bad_va_T_2 | pma_checker__bad_va_T_4; // @[TLB.scala:560:{51,59,71}]
wire pma_checker__bad_va_T_6 = ~pma_checker__bad_va_T_5; // @[TLB.scala:560:{37,59}]
wire pma_checker__bad_va_T_7 = pma_checker__bad_va_T_6; // @[TLB.scala:560:{34,37}]
wire _GEN_27 = pma_checker_io_req_bits_cmd == 5'h6; // @[package.scala:16:47]
wire pma_checker__cmd_lrsc_T; // @[package.scala:16:47]
assign pma_checker__cmd_lrsc_T = _GEN_27; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_2; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_2 = _GEN_27; // @[package.scala:16:47]
wire _GEN_28 = pma_checker_io_req_bits_cmd == 5'h7; // @[package.scala:16:47]
wire pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47]
assign pma_checker__cmd_lrsc_T_1 = _GEN_28; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_3; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_3 = _GEN_28; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_3; // @[Consts.scala:90:66]
assign pma_checker__cmd_write_T_3 = _GEN_28; // @[package.scala:16:47]
wire pma_checker__cmd_lrsc_T_2 = pma_checker__cmd_lrsc_T | pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47, :81:59]
wire _GEN_29 = pma_checker_io_req_bits_cmd == 5'h4; // @[package.scala:16:47]
wire pma_checker__cmd_amo_logical_T; // @[package.scala:16:47]
assign pma_checker__cmd_amo_logical_T = _GEN_29; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_7; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_7 = _GEN_29; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_5; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_5 = _GEN_29; // @[package.scala:16:47]
wire _GEN_30 = pma_checker_io_req_bits_cmd == 5'h9; // @[package.scala:16:47]
wire pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47]
assign pma_checker__cmd_amo_logical_T_1 = _GEN_30; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_8; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_8 = _GEN_30; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_6; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_6 = _GEN_30; // @[package.scala:16:47]
wire _GEN_31 = pma_checker_io_req_bits_cmd == 5'hA; // @[package.scala:16:47]
wire pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47]
assign pma_checker__cmd_amo_logical_T_2 = _GEN_31; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_9; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_9 = _GEN_31; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_7; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_7 = _GEN_31; // @[package.scala:16:47]
wire _GEN_32 = pma_checker_io_req_bits_cmd == 5'hB; // @[package.scala:16:47]
wire pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47]
assign pma_checker__cmd_amo_logical_T_3 = _GEN_32; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_10; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_10 = _GEN_32; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_8; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_8 = _GEN_32; // @[package.scala:16:47]
wire pma_checker__cmd_amo_logical_T_4 = pma_checker__cmd_amo_logical_T | pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_amo_logical_T_5 = pma_checker__cmd_amo_logical_T_4 | pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_amo_logical_T_6 = pma_checker__cmd_amo_logical_T_5 | pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_33 = pma_checker_io_req_bits_cmd == 5'h8; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T; // @[package.scala:16:47]
assign pma_checker__cmd_amo_arithmetic_T = _GEN_33; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_14; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_14 = _GEN_33; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_12; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_12 = _GEN_33; // @[package.scala:16:47]
wire _GEN_34 = pma_checker_io_req_bits_cmd == 5'hC; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47]
assign pma_checker__cmd_amo_arithmetic_T_1 = _GEN_34; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_15; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_15 = _GEN_34; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_13; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_13 = _GEN_34; // @[package.scala:16:47]
wire _GEN_35 = pma_checker_io_req_bits_cmd == 5'hD; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47]
assign pma_checker__cmd_amo_arithmetic_T_2 = _GEN_35; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_16; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_16 = _GEN_35; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_14; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_14 = _GEN_35; // @[package.scala:16:47]
wire _GEN_36 = pma_checker_io_req_bits_cmd == 5'hE; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47]
assign pma_checker__cmd_amo_arithmetic_T_3 = _GEN_36; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_17; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_17 = _GEN_36; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_15; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_15 = _GEN_36; // @[package.scala:16:47]
wire _GEN_37 = pma_checker_io_req_bits_cmd == 5'hF; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47]
assign pma_checker__cmd_amo_arithmetic_T_4 = _GEN_37; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_18; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_18 = _GEN_37; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_16; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_16 = _GEN_37; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T_5 = pma_checker__cmd_amo_arithmetic_T | pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_amo_arithmetic_T_6 = pma_checker__cmd_amo_arithmetic_T_5 | pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_amo_arithmetic_T_7 = pma_checker__cmd_amo_arithmetic_T_6 | pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_amo_arithmetic_T_8 = pma_checker__cmd_amo_arithmetic_T_7 | pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59]
wire _GEN_38 = pma_checker_io_req_bits_cmd == 5'h11; // @[TLB.scala:573:41]
wire pma_checker_cmd_put_partial; // @[TLB.scala:573:41]
assign pma_checker_cmd_put_partial = _GEN_38; // @[TLB.scala:573:41]
wire pma_checker__cmd_write_T_1; // @[Consts.scala:90:49]
assign pma_checker__cmd_write_T_1 = _GEN_38; // @[TLB.scala:573:41]
wire pma_checker__cmd_read_T = pma_checker_io_req_bits_cmd == 5'h0; // @[package.scala:16:47]
wire _GEN_39 = pma_checker_io_req_bits_cmd == 5'h10; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_1; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_1 = _GEN_39; // @[package.scala:16:47]
wire pma_checker__cmd_readx_T; // @[TLB.scala:575:56]
assign pma_checker__cmd_readx_T = _GEN_39; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_4 = pma_checker__cmd_read_T | pma_checker__cmd_read_T_1; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_5 = pma_checker__cmd_read_T_4 | pma_checker__cmd_read_T_2; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_6 = pma_checker__cmd_read_T_5 | pma_checker__cmd_read_T_3; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_11 = pma_checker__cmd_read_T_7 | pma_checker__cmd_read_T_8; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_12 = pma_checker__cmd_read_T_11 | pma_checker__cmd_read_T_9; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_13 = pma_checker__cmd_read_T_12 | pma_checker__cmd_read_T_10; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_19 = pma_checker__cmd_read_T_14 | pma_checker__cmd_read_T_15; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_20 = pma_checker__cmd_read_T_19 | pma_checker__cmd_read_T_16; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_21 = pma_checker__cmd_read_T_20 | pma_checker__cmd_read_T_17; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_22 = pma_checker__cmd_read_T_21 | pma_checker__cmd_read_T_18; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_23 = pma_checker__cmd_read_T_13 | pma_checker__cmd_read_T_22; // @[package.scala:81:59]
wire pma_checker_cmd_read = pma_checker__cmd_read_T_6 | pma_checker__cmd_read_T_23; // @[package.scala:81:59]
wire pma_checker__cmd_write_T = pma_checker_io_req_bits_cmd == 5'h1; // @[DCache.scala:120:32]
wire pma_checker__cmd_write_T_2 = pma_checker__cmd_write_T | pma_checker__cmd_write_T_1; // @[Consts.scala:90:{32,42,49}]
wire pma_checker__cmd_write_T_4 = pma_checker__cmd_write_T_2 | pma_checker__cmd_write_T_3; // @[Consts.scala:90:{42,59,66}]
wire pma_checker__cmd_write_T_9 = pma_checker__cmd_write_T_5 | pma_checker__cmd_write_T_6; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_10 = pma_checker__cmd_write_T_9 | pma_checker__cmd_write_T_7; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_11 = pma_checker__cmd_write_T_10 | pma_checker__cmd_write_T_8; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_17 = pma_checker__cmd_write_T_12 | pma_checker__cmd_write_T_13; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_18 = pma_checker__cmd_write_T_17 | pma_checker__cmd_write_T_14; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_19 = pma_checker__cmd_write_T_18 | pma_checker__cmd_write_T_15; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_20 = pma_checker__cmd_write_T_19 | pma_checker__cmd_write_T_16; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_21 = pma_checker__cmd_write_T_11 | pma_checker__cmd_write_T_20; // @[package.scala:81:59]
wire pma_checker_cmd_write = pma_checker__cmd_write_T_4 | pma_checker__cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire pma_checker__cmd_write_perms_T = pma_checker_io_req_bits_cmd == 5'h5; // @[package.scala:16:47]
wire pma_checker__cmd_write_perms_T_1 = pma_checker_io_req_bits_cmd == 5'h17; // @[package.scala:16:47]
wire pma_checker__cmd_write_perms_T_2 = pma_checker__cmd_write_perms_T | pma_checker__cmd_write_perms_T_1; // @[package.scala:16:47, :81:59]
wire pma_checker_cmd_write_perms = pma_checker_cmd_write | pma_checker__cmd_write_perms_T_2; // @[package.scala:81:59]
wire [13:0] pma_checker__ae_array_T = pma_checker_misaligned ? pma_checker_eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8]
wire [13:0] pma_checker_ae_array = pma_checker__ae_array_T; // @[TLB.scala:582:{8,37}]
wire [13:0] pma_checker__ae_array_T_1 = ~pma_checker_lrscAllowed; // @[TLB.scala:580:24, :583:19]
wire [13:0] pma_checker__ae_ld_array_T = ~pma_checker_pr_array; // @[TLB.scala:529:87, :586:46]
wire [13:0] pma_checker__ae_ld_array_T_1 = pma_checker_ae_array | pma_checker__ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}]
wire [13:0] pma_checker_ae_ld_array = pma_checker_cmd_read ? pma_checker__ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}]
wire [13:0] pma_checker__ae_st_array_T = ~pma_checker_pw_array; // @[TLB.scala:531:87, :588:37]
wire [13:0] pma_checker__ae_st_array_T_1 = pma_checker_ae_array | pma_checker__ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}]
wire [13:0] pma_checker__ae_st_array_T_2 = pma_checker_cmd_write_perms ? pma_checker__ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}]
wire [13:0] pma_checker__ae_st_array_T_3 = ~pma_checker_ppp_array_if_cached; // @[TLB.scala:544:39, :589:26]
wire [13:0] pma_checker__ae_st_array_T_4 = pma_checker_cmd_put_partial ? pma_checker__ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}]
wire [13:0] pma_checker__ae_st_array_T_5 = pma_checker__ae_st_array_T_2 | pma_checker__ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8]
wire [13:0] pma_checker__ae_st_array_T_8 = pma_checker__ae_st_array_T_5; // @[TLB.scala:588:53, :589:53]
wire [13:0] pma_checker__ae_st_array_T_6 = ~pma_checker_pal_array_if_cached; // @[TLB.scala:546:39, :590:26]
wire [13:0] pma_checker_ae_st_array = pma_checker__ae_st_array_T_8; // @[TLB.scala:589:53, :590:53]
wire [13:0] pma_checker__ae_st_array_T_9 = ~pma_checker_paa_array_if_cached; // @[TLB.scala:545:39, :591:29]
wire [13:0] pma_checker__must_alloc_array_T = ~pma_checker_ppp_array; // @[TLB.scala:539:22, :593:26]
wire [13:0] pma_checker__must_alloc_array_T_1 = pma_checker_cmd_put_partial ? pma_checker__must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}]
wire [13:0] pma_checker__must_alloc_array_T_4 = pma_checker__must_alloc_array_T_1; // @[TLB.scala:593:{8,43}]
wire [13:0] pma_checker__must_alloc_array_T_2 = ~pma_checker_pal_array; // @[TLB.scala:543:22, :594:26]
wire [13:0] pma_checker__must_alloc_array_T_7 = pma_checker__must_alloc_array_T_4; // @[TLB.scala:593:43, :594:43]
wire [13:0] pma_checker__must_alloc_array_T_5 = ~pma_checker_paa_array; // @[TLB.scala:541:22, :595:29]
wire [13:0] pma_checker_must_alloc_array = pma_checker__must_alloc_array_T_7; // @[TLB.scala:594:43, :595:46]
wire [13:0] pma_checker__pf_ld_array_T_1 = ~pma_checker__pf_ld_array_T; // @[TLB.scala:597:{37,41}]
wire [13:0] pma_checker__pf_ld_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73]
wire [13:0] pma_checker__pf_ld_array_T_3 = pma_checker__pf_ld_array_T_1 & pma_checker__pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}]
wire [13:0] pma_checker__pf_ld_array_T_4 = pma_checker__pf_ld_array_T_3 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}]
wire [13:0] pma_checker__pf_ld_array_T_5 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106]
wire [13:0] pma_checker__pf_ld_array_T_6 = pma_checker__pf_ld_array_T_4 & pma_checker__pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}]
wire [13:0] pma_checker_pf_ld_array = pma_checker_cmd_read ? pma_checker__pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}]
wire [13:0] pma_checker__pf_st_array_T = ~pma_checker_w_array; // @[TLB.scala:521:20, :598:44]
wire [13:0] pma_checker__pf_st_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55]
wire [13:0] pma_checker__pf_st_array_T_2 = pma_checker__pf_st_array_T & pma_checker__pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}]
wire [13:0] pma_checker__pf_st_array_T_3 = pma_checker__pf_st_array_T_2 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}]
wire [13:0] pma_checker__pf_st_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88]
wire [13:0] pma_checker__pf_st_array_T_5 = pma_checker__pf_st_array_T_3 & pma_checker__pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}]
wire [13:0] pma_checker_pf_st_array = pma_checker_cmd_write_perms ? pma_checker__pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}]
wire [13:0] pma_checker__pf_inst_array_T = ~pma_checker_x_array; // @[TLB.scala:522:20, :599:25]
wire [13:0] pma_checker__pf_inst_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36]
wire [13:0] pma_checker__pf_inst_array_T_2 = pma_checker__pf_inst_array_T & pma_checker__pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}]
wire [13:0] pma_checker__pf_inst_array_T_3 = pma_checker__pf_inst_array_T_2 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}]
wire [13:0] pma_checker__pf_inst_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69]
wire [13:0] pma_checker_pf_inst_array = pma_checker__pf_inst_array_T_3 & pma_checker__pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}]
wire [13:0] pma_checker__gf_ld_array_T_4 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100]
wire [13:0] pma_checker__gf_ld_array_T_5 = pma_checker__gf_ld_array_T_3 & pma_checker__gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}]
wire [13:0] pma_checker__gf_st_array_T_3 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81]
wire [13:0] pma_checker__gf_st_array_T_4 = pma_checker__gf_st_array_T_2 & pma_checker__gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}]
wire [13:0] pma_checker__gf_inst_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64]
wire [13:0] pma_checker__gf_inst_array_T_3 = pma_checker__gf_inst_array_T_1 & pma_checker__gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}]
wire pma_checker__gpa_hits_hit_mask_T = pma_checker_vpn == 27'h0; // @[TLB.scala:335:30, :606:73]
wire [13:0] pma_checker__io_resp_pf_ld_T_1 = pma_checker_pf_ld_array & 14'h2000; // @[TLB.scala:597:24, :633:57]
wire pma_checker__io_resp_pf_ld_T_2 = |pma_checker__io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}]
assign pma_checker__io_resp_pf_ld_T_3 = pma_checker__io_resp_pf_ld_T_2; // @[TLB.scala:633:{41,65}]
assign pma_checker_io_resp_pf_ld = pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41]
wire [13:0] pma_checker__io_resp_pf_st_T_1 = pma_checker_pf_st_array & 14'h2000; // @[TLB.scala:598:24, :634:64]
wire pma_checker__io_resp_pf_st_T_2 = |pma_checker__io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}]
assign pma_checker__io_resp_pf_st_T_3 = pma_checker__io_resp_pf_st_T_2; // @[TLB.scala:634:{48,72}]
assign pma_checker_io_resp_pf_st = pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48]
wire [13:0] pma_checker__io_resp_pf_inst_T = pma_checker_pf_inst_array & 14'h2000; // @[TLB.scala:599:67, :635:47]
wire pma_checker__io_resp_pf_inst_T_1 = |pma_checker__io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}]
assign pma_checker__io_resp_pf_inst_T_2 = pma_checker__io_resp_pf_inst_T_1; // @[TLB.scala:635:{29,55}]
assign pma_checker_io_resp_pf_inst = pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29]
wire [13:0] pma_checker__io_resp_ae_ld_T = pma_checker_ae_ld_array & 14'h2000; // @[TLB.scala:586:24, :641:33]
assign pma_checker__io_resp_ae_ld_T_1 = |pma_checker__io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}]
assign pma_checker_io_resp_ae_ld = pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41]
wire [13:0] pma_checker__io_resp_ae_st_T = pma_checker_ae_st_array & 14'h2000; // @[TLB.scala:590:53, :642:33]
assign pma_checker__io_resp_ae_st_T_1 = |pma_checker__io_resp_ae_st_T; // @[TLB.scala:642:{33,41}]
assign pma_checker_io_resp_ae_st = pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41]
wire [13:0] pma_checker__io_resp_ae_inst_T = ~pma_checker_px_array; // @[TLB.scala:533:87, :643:23]
wire [13:0] pma_checker__io_resp_ae_inst_T_1 = pma_checker__io_resp_ae_inst_T & 14'h2000; // @[TLB.scala:643:{23,33}]
assign pma_checker__io_resp_ae_inst_T_2 = |pma_checker__io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}]
assign pma_checker_io_resp_ae_inst = pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41]
assign pma_checker__io_resp_ma_ld_T = pma_checker_misaligned & pma_checker_cmd_read; // @[TLB.scala:550:77, :645:31]
assign pma_checker_io_resp_ma_ld = pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31]
assign pma_checker__io_resp_ma_st_T = pma_checker_misaligned & pma_checker_cmd_write; // @[TLB.scala:550:77, :646:31]
assign pma_checker_io_resp_ma_st = pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31]
wire [13:0] pma_checker__io_resp_cacheable_T = pma_checker_c_array & 14'h2000; // @[TLB.scala:537:20, :648:33]
assign pma_checker__io_resp_cacheable_T_1 = |pma_checker__io_resp_cacheable_T; // @[TLB.scala:648:{33,41}]
assign pma_checker_io_resp_cacheable = pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41]
wire [13:0] pma_checker__io_resp_must_alloc_T = pma_checker_must_alloc_array & 14'h2000; // @[TLB.scala:595:46, :649:43]
assign pma_checker__io_resp_must_alloc_T_1 = |pma_checker__io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}]
assign pma_checker_io_resp_must_alloc = pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51]
wire [13:0] pma_checker__io_resp_prefetchable_T = pma_checker_prefetchable_array & 14'h2000; // @[TLB.scala:547:31, :650:47]
wire pma_checker__io_resp_prefetchable_T_1 = |pma_checker__io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}]
assign pma_checker__io_resp_prefetchable_T_2 = pma_checker__io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}]
assign pma_checker_io_resp_prefetchable = pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59]
assign pma_checker__io_resp_paddr_T_1 = {pma_checker_ppn, pma_checker__io_resp_paddr_T}; // @[Mux.scala:30:73]
assign pma_checker_io_resp_paddr = pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23]
wire [27:0] pma_checker__io_resp_gpa_page_T_1 = {1'h0, pma_checker_vpn}; // @[TLB.scala:335:30, :657:36]
wire [27:0] pma_checker_io_resp_gpa_page = pma_checker__io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}]
wire [11:0] pma_checker_io_resp_gpa_offset = pma_checker__io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}]
assign pma_checker__io_resp_gpa_T = {pma_checker_io_resp_gpa_page, pma_checker_io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8]
assign pma_checker_io_resp_gpa = pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8]
wire pma_checker_ignore_1 = pma_checker__ignore_T_1; // @[TLB.scala:182:{28,34}]
wire pma_checker_ignore_4 = pma_checker__ignore_T_4; // @[TLB.scala:182:{28,34}]
wire pma_checker_ignore_7 = pma_checker__ignore_T_7; // @[TLB.scala:182:{28,34}]
wire pma_checker_ignore_10 = pma_checker__ignore_T_10; // @[TLB.scala:182:{28,34}]
wire replace; // @[Replacement.scala:37:29]
wire [1:0] lfsr_lo_lo_lo = {_lfsr_prng_io_out_1, _lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_lo_lo_hi = {_lfsr_prng_io_out_3, _lfsr_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_lo_lo = {lfsr_lo_lo_hi, lfsr_lo_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_lo_hi_lo = {_lfsr_prng_io_out_5, _lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_lo_hi_hi = {_lfsr_prng_io_out_7, _lfsr_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_lo_hi = {lfsr_lo_hi_hi, lfsr_lo_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] lfsr_lo = {lfsr_lo_hi, lfsr_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_hi_lo_lo = {_lfsr_prng_io_out_9, _lfsr_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_hi_lo_hi = {_lfsr_prng_io_out_11, _lfsr_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_hi_lo = {lfsr_hi_lo_hi, lfsr_hi_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_hi_hi_lo = {_lfsr_prng_io_out_13, _lfsr_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_hi_hi_hi = {_lfsr_prng_io_out_15, _lfsr_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_hi_hi = {lfsr_hi_hi_hi, lfsr_hi_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] lfsr_hi = {lfsr_hi_hi, lfsr_hi_lo}; // @[PRNG.scala:95:17]
wire [15:0] lfsr = {lfsr_hi, lfsr_lo}; // @[PRNG.scala:95:17]
wire metaArb__grant_T = metaArb_io_in_0_valid; // @[Arbiter.scala:45:68]
wire [39:0] _metaArb_io_in_5_bits_addr_T_2; // @[DCache.scala:1018:36]
wire [1:0] _metaArb_io_in_5_bits_idx_T; // @[DCache.scala:1017:44]
wire metaArb__io_in_1_ready_T; // @[Arbiter.scala:153:19]
wire [39:0] _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:454:36]
wire [1:0] _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:453:35]
wire [25:0] _metaArb_io_in_1_bits_data_T; // @[DCache.scala:458:14]
wire metaArb__io_in_2_ready_T; // @[Arbiter.scala:153:19]
wire _metaArb_io_in_2_valid_T; // @[DCache.scala:462:63]
wire [39:0] _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:466:36]
wire [1:0] _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:465:40]
wire [3:0] s2_victim_or_hit_way; // @[DCache.scala:432:33]
wire [25:0] _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:467:97]
wire metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19]
wire _metaArb_io_in_3_valid_T_2; // @[DCache.scala:741:53]
wire [39:0] _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:745:36]
wire [1:0] _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:744:40]
wire [25:0] _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:746:134]
wire metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19]
wire _metaArb_io_in_4_valid_T_2; // @[package.scala:81:59]
wire [39:0] _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:912:36]
wire [1:0] _metaArb_io_in_4_bits_idx_T; // @[DCache.scala:1200:47]
wire [3:0] releaseWay; // @[DCache.scala:232:24]
wire [25:0] _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:913:97]
wire metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19]
wire metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19]
wire metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19]
wire [1:0] _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:263:58]
wire metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31]
wire [1:0] _s1_meta_WIRE = metaArb_io_out_bits_idx; // @[DCache.scala:135:28, :314:35]
wire [39:0] metaArb_io_in_0_bits_addr; // @[DCache.scala:135:28]
wire [1:0] metaArb_io_in_0_bits_idx; // @[DCache.scala:135:28]
wire [39:0] metaArb_io_in_1_bits_addr; // @[DCache.scala:135:28]
wire [1:0] metaArb_io_in_1_bits_idx; // @[DCache.scala:135:28]
wire [25:0] metaArb_io_in_1_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_1_ready; // @[DCache.scala:135:28]
wire [39:0] metaArb_io_in_2_bits_addr; // @[DCache.scala:135:28]
wire [1:0] metaArb_io_in_2_bits_idx; // @[DCache.scala:135:28]
wire [3:0] metaArb_io_in_2_bits_way_en; // @[DCache.scala:135:28]
wire [25:0] metaArb_io_in_2_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_2_ready; // @[DCache.scala:135:28]
wire metaArb_io_in_2_valid; // @[DCache.scala:135:28]
wire [39:0] metaArb_io_in_3_bits_addr; // @[DCache.scala:135:28]
wire [1:0] metaArb_io_in_3_bits_idx; // @[DCache.scala:135:28]
wire [3:0] metaArb_io_in_3_bits_way_en; // @[DCache.scala:135:28]
wire [25:0] metaArb_io_in_3_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_3_ready; // @[DCache.scala:135:28]
wire metaArb_io_in_3_valid; // @[DCache.scala:135:28]
wire [39:0] metaArb_io_in_4_bits_addr; // @[DCache.scala:135:28]
wire [1:0] metaArb_io_in_4_bits_idx; // @[DCache.scala:135:28]
wire [3:0] metaArb_io_in_4_bits_way_en; // @[DCache.scala:135:28]
wire [25:0] metaArb_io_in_4_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_4_ready; // @[DCache.scala:135:28]
wire metaArb_io_in_4_valid; // @[DCache.scala:135:28]
wire [39:0] metaArb_io_in_5_bits_addr; // @[DCache.scala:135:28]
wire [1:0] metaArb_io_in_5_bits_idx; // @[DCache.scala:135:28]
wire [3:0] metaArb_io_in_5_bits_way_en; // @[DCache.scala:135:28]
wire [25:0] metaArb_io_in_5_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_5_ready; // @[DCache.scala:135:28]
wire [39:0] metaArb_io_in_6_bits_addr; // @[DCache.scala:135:28]
wire [1:0] metaArb_io_in_6_bits_idx; // @[DCache.scala:135:28]
wire [3:0] metaArb_io_in_6_bits_way_en; // @[DCache.scala:135:28]
wire [25:0] metaArb_io_in_6_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_6_ready; // @[DCache.scala:135:28]
wire metaArb_io_in_6_valid; // @[DCache.scala:135:28]
wire [1:0] metaArb_io_in_7_bits_idx; // @[DCache.scala:135:28]
wire [3:0] metaArb_io_in_7_bits_way_en; // @[DCache.scala:135:28]
wire [25:0] metaArb_io_in_7_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_7_ready; // @[DCache.scala:135:28]
wire metaArb_io_out_bits_write; // @[DCache.scala:135:28]
wire [39:0] metaArb_io_out_bits_addr; // @[DCache.scala:135:28]
wire [3:0] metaArb_io_out_bits_way_en; // @[DCache.scala:135:28]
wire [25:0] metaArb_io_out_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_out_valid; // @[DCache.scala:135:28]
wire [2:0] metaArb_io_chosen; // @[DCache.scala:135:28]
assign metaArb_io_chosen = metaArb_io_in_0_valid ? 3'h0 : metaArb_io_in_2_valid ? 3'h2 : metaArb_io_in_3_valid ? 3'h3 : metaArb_io_in_4_valid ? 3'h4 : {2'h3, ~metaArb_io_in_6_valid}; // @[Arbiter.scala:142:13, :145:26, :146:17]
assign metaArb_io_out_bits_write = metaArb_io_in_0_valid | metaArb_io_in_2_valid | metaArb_io_in_3_valid | metaArb_io_in_4_valid; // @[Arbiter.scala:145:26, :147:19]
assign metaArb_io_out_bits_addr = metaArb_io_in_0_valid ? metaArb_io_in_0_bits_addr : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_addr : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_addr : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_addr : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_addr : metaArb_io_in_7_bits_addr; // @[Arbiter.scala:143:15, :145:26, :147:19]
assign metaArb_io_out_bits_idx = metaArb_io_in_0_valid ? metaArb_io_in_0_bits_idx : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_idx : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_idx : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_idx : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_idx : metaArb_io_in_7_bits_idx; // @[Arbiter.scala:143:15, :145:26, :147:19]
assign metaArb_io_out_bits_way_en = metaArb_io_in_0_valid ? 4'hF : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_way_en : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_way_en : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_way_en : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_way_en : metaArb_io_in_7_bits_way_en; // @[Arbiter.scala:143:15, :145:26, :147:19]
assign metaArb_io_out_bits_data = metaArb_io_in_0_valid ? 26'h0 : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_data : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_data : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_data : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_data : metaArb_io_in_7_bits_data; // @[Arbiter.scala:143:15, :145:26, :147:19]
wire metaArb__grant_T_1 = metaArb__grant_T | metaArb_io_in_2_valid; // @[Arbiter.scala:45:68]
wire metaArb__grant_T_2 = metaArb__grant_T_1 | metaArb_io_in_3_valid; // @[Arbiter.scala:45:68]
wire metaArb__grant_T_3 = metaArb__grant_T_2 | metaArb_io_in_4_valid; // @[Arbiter.scala:45:68]
wire metaArb__grant_T_4 = metaArb__grant_T_3; // @[Arbiter.scala:45:68]
wire metaArb__grant_T_5 = metaArb__grant_T_4 | metaArb_io_in_6_valid; // @[Arbiter.scala:45:68]
wire metaArb_grant_1 = ~metaArb_io_in_0_valid; // @[Arbiter.scala:45:78]
assign metaArb__io_in_1_ready_T = metaArb_grant_1; // @[Arbiter.scala:45:78, :153:19]
wire metaArb_grant_2 = ~metaArb__grant_T; // @[Arbiter.scala:45:{68,78}]
assign metaArb__io_in_2_ready_T = metaArb_grant_2; // @[Arbiter.scala:45:78, :153:19]
wire metaArb_grant_3 = ~metaArb__grant_T_1; // @[Arbiter.scala:45:{68,78}]
assign metaArb__io_in_3_ready_T = metaArb_grant_3; // @[Arbiter.scala:45:78, :153:19]
wire metaArb_grant_4 = ~metaArb__grant_T_2; // @[Arbiter.scala:45:{68,78}]
assign metaArb__io_in_4_ready_T = metaArb_grant_4; // @[Arbiter.scala:45:78, :153:19]
wire metaArb_grant_5 = ~metaArb__grant_T_3; // @[Arbiter.scala:45:{68,78}]
assign metaArb__io_in_5_ready_T = metaArb_grant_5; // @[Arbiter.scala:45:78, :153:19]
wire metaArb_grant_6 = ~metaArb__grant_T_4; // @[Arbiter.scala:45:{68,78}]
assign metaArb__io_in_6_ready_T = metaArb_grant_6; // @[Arbiter.scala:45:78, :153:19]
wire metaArb_grant_7 = ~metaArb__grant_T_5; // @[Arbiter.scala:45:{68,78}]
assign metaArb__io_in_7_ready_T = metaArb_grant_7; // @[Arbiter.scala:45:78, :153:19]
assign metaArb_io_in_1_ready = metaArb__io_in_1_ready_T; // @[Arbiter.scala:153:19]
assign metaArb_io_in_2_ready = metaArb__io_in_2_ready_T; // @[Arbiter.scala:153:19]
assign metaArb_io_in_3_ready = metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19]
assign metaArb_io_in_4_ready = metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19]
assign metaArb_io_in_5_ready = metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19]
assign metaArb_io_in_6_ready = metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19]
assign metaArb_io_in_7_ready = metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19]
wire metaArb__io_out_valid_T = ~metaArb_grant_7; // @[Arbiter.scala:45:78, :154:19]
assign metaArb__io_out_valid_T_1 = metaArb__io_out_valid_T | metaArb_io_in_7_valid; // @[Arbiter.scala:154:{19,31}]
assign metaArb_io_out_valid = metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31]
wire _s1_meta_T_1; // @[DCache.scala:314:59]
wire wmask_0; // @[DCache.scala:311:74]
wire wmask_1; // @[DCache.scala:311:74]
wire wmask_2; // @[DCache.scala:311:74]
wire wmask_3; // @[DCache.scala:311:74]
wire [25:0] _s1_meta_uncorrected_WIRE = _rerocc_tile_dcache_tag_array_RW0_rdata[25:0]; // @[DescribedSRAM.scala:17:26]
wire [25:0] _s1_meta_uncorrected_WIRE_1 = _rerocc_tile_dcache_tag_array_RW0_rdata[51:26]; // @[DescribedSRAM.scala:17:26]
wire [25:0] _s1_meta_uncorrected_WIRE_2 = _rerocc_tile_dcache_tag_array_RW0_rdata[77:52]; // @[DescribedSRAM.scala:17:26]
wire [25:0] _s1_meta_uncorrected_WIRE_3 = _rerocc_tile_dcache_tag_array_RW0_rdata[103:78]; // @[DescribedSRAM.scala:17:26]
wire _dataArb_io_in_0_valid_T_12; // @[DCache.scala:516:27]
wire pstore_drain; // @[DCache.scala:516:27]
wire [63:0] _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27]
wire [7:0] _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27]
wire [3:0] _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:550:38]
wire dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19]
wire [63:0] tl_d_data_encoded; // @[DCache.scala:324:31]
wire dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19]
wire _dataArb_io_in_2_valid_T_1; // @[DCache.scala:900:41]
wire [7:0] _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:903:72]
wire dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19]
wire dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31]
wire [7:0] dataArb_io_in_0_bits_addr; // @[DCache.scala:152:28]
wire dataArb_io_in_0_bits_write; // @[DCache.scala:152:28]
wire [63:0] dataArb_io_in_0_bits_wdata; // @[DCache.scala:152:28]
wire dataArb_io_in_0_bits_wordMask; // @[DCache.scala:152:28]
wire [7:0] dataArb_io_in_0_bits_eccMask; // @[DCache.scala:152:28]
wire [3:0] dataArb_io_in_0_bits_way_en; // @[DCache.scala:152:28]
wire dataArb_io_in_0_valid; // @[DCache.scala:152:28]
wire [7:0] dataArb_io_in_1_bits_addr; // @[DCache.scala:152:28]
wire dataArb_io_in_1_bits_write; // @[DCache.scala:152:28]
wire [63:0] dataArb_io_in_1_bits_wdata; // @[DCache.scala:152:28]
wire [3:0] dataArb_io_in_1_bits_way_en; // @[DCache.scala:152:28]
wire dataArb_io_in_1_ready; // @[DCache.scala:152:28]
wire dataArb_io_in_1_valid; // @[DCache.scala:152:28]
wire [7:0] dataArb_io_in_2_bits_addr; // @[DCache.scala:152:28]
wire [63:0] dataArb_io_in_2_bits_wdata; // @[DCache.scala:152:28]
wire dataArb_io_in_2_ready; // @[DCache.scala:152:28]
wire dataArb_io_in_2_valid; // @[DCache.scala:152:28]
wire [7:0] dataArb_io_in_3_bits_addr; // @[DCache.scala:152:28]
wire [63:0] dataArb_io_in_3_bits_wdata; // @[DCache.scala:152:28]
wire dataArb_io_in_3_ready; // @[DCache.scala:152:28]
wire dataArb_io_in_3_valid; // @[DCache.scala:152:28]
wire [7:0] dataArb_io_out_bits_addr; // @[DCache.scala:152:28]
wire dataArb_io_out_bits_write; // @[DCache.scala:152:28]
wire [63:0] dataArb_io_out_bits_wdata; // @[DCache.scala:152:28]
wire dataArb_io_out_bits_wordMask; // @[DCache.scala:152:28]
wire [7:0] dataArb_io_out_bits_eccMask; // @[DCache.scala:152:28]
wire [3:0] dataArb_io_out_bits_way_en; // @[DCache.scala:152:28]
wire dataArb_io_out_valid; // @[DCache.scala:152:28]
wire [1:0] dataArb_io_chosen; // @[DCache.scala:152:28]
assign dataArb_io_chosen = dataArb_io_in_0_valid ? 2'h0 : dataArb_io_in_1_valid ? 2'h1 : {1'h1, ~dataArb_io_in_2_valid}; // @[Arbiter.scala:142:13, :145:26, :146:17]
assign dataArb_io_out_bits_addr = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_addr : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_addr : dataArb_io_in_2_valid ? dataArb_io_in_2_bits_addr : dataArb_io_in_3_bits_addr; // @[Arbiter.scala:143:15, :145:26, :147:19]
assign dataArb_io_out_bits_write = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_write : dataArb_io_in_1_valid & dataArb_io_in_1_bits_write; // @[Arbiter.scala:145:26, :147:19]
assign dataArb_io_out_bits_wdata = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wdata : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_wdata : dataArb_io_in_2_valid ? dataArb_io_in_2_bits_wdata : dataArb_io_in_3_bits_wdata; // @[Arbiter.scala:143:15, :145:26, :147:19]
assign dataArb_io_out_bits_wordMask = ~dataArb_io_in_0_valid | dataArb_io_in_0_bits_wordMask; // @[Arbiter.scala:145:26, :147:19]
assign dataArb_io_out_bits_eccMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_eccMask : 8'hFF; // @[Arbiter.scala:145:26, :147:19]
assign dataArb_io_out_bits_way_en = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_way_en : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_way_en : 4'hF; // @[Arbiter.scala:145:26, :147:19]
wire dataArb__grant_T = dataArb_io_in_0_valid | dataArb_io_in_1_valid; // @[Arbiter.scala:45:68]
wire dataArb__grant_T_1 = dataArb__grant_T | dataArb_io_in_2_valid; // @[Arbiter.scala:45:68]
wire dataArb_grant_1 = ~dataArb_io_in_0_valid; // @[Arbiter.scala:45:78]
assign dataArb__io_in_1_ready_T = dataArb_grant_1; // @[Arbiter.scala:45:78, :153:19]
wire dataArb_grant_2 = ~dataArb__grant_T; // @[Arbiter.scala:45:{68,78}]
assign dataArb__io_in_2_ready_T = dataArb_grant_2; // @[Arbiter.scala:45:78, :153:19]
wire dataArb_grant_3 = ~dataArb__grant_T_1; // @[Arbiter.scala:45:{68,78}]
assign dataArb__io_in_3_ready_T = dataArb_grant_3; // @[Arbiter.scala:45:78, :153:19]
assign dataArb_io_in_1_ready = dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19]
assign dataArb_io_in_2_ready = dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19]
assign dataArb_io_in_3_ready = dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19]
wire dataArb__io_out_valid_T = ~dataArb_grant_3; // @[Arbiter.scala:45:78, :154:19]
assign dataArb__io_out_valid_T_1 = dataArb__io_out_valid_T | dataArb_io_in_3_valid; // @[Arbiter.scala:154:{19,31}]
assign dataArb_io_out_valid = dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31]
wire _tl_out_a_valid_T_14; // @[DCache.scala:603:37]
assign nodeOut_a_deq_valid = tl_out_a_valid; // @[Decoupled.scala:356:21]
wire [2:0] _tl_out_a_bits_T_9_opcode; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_opcode = tl_out_a_bits_opcode; // @[Decoupled.scala:356:21]
wire [2:0] _tl_out_a_bits_T_9_param; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_param = tl_out_a_bits_param; // @[Decoupled.scala:356:21]
wire [3:0] _tl_out_a_bits_T_9_size; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_size = tl_out_a_bits_size; // @[Decoupled.scala:356:21]
wire _tl_out_a_bits_T_9_source; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_source = tl_out_a_bits_source; // @[Decoupled.scala:356:21]
wire [31:0] _tl_out_a_bits_T_9_address; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_address = tl_out_a_bits_address; // @[Decoupled.scala:356:21]
wire [7:0] _tl_out_a_bits_T_9_mask; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_mask = tl_out_a_bits_mask; // @[Decoupled.scala:356:21]
wire [63:0] _tl_out_a_bits_T_9_data; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_data = tl_out_a_bits_data; // @[Decoupled.scala:356:21]
wire tl_out_a_ready; // @[DCache.scala:159:22]
assign tl_out_a_ready = nodeOut_a_deq_ready; // @[Decoupled.scala:356:21]
assign nodeOut_a_valid = nodeOut_a_deq_valid; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_opcode = nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_param = nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_size = nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_source = nodeOut_a_deq_bits_source; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_address = nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_mask = nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_data = nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21]
wire _s1_valid_T = io_cpu_req_ready_0 & io_cpu_req_valid_0; // @[Decoupled.scala:51:35]
reg s1_valid; // @[DCache.scala:182:25]
wire _GEN_40 = nodeOut_b_ready & nodeOut_b_valid; // @[Decoupled.scala:51:35]
wire _s1_probe_T; // @[Decoupled.scala:51:35]
assign _s1_probe_T = _GEN_40; // @[Decoupled.scala:51:35]
wire _probe_bits_T; // @[Decoupled.scala:51:35]
assign _probe_bits_T = _GEN_40; // @[Decoupled.scala:51:35]
reg s1_probe; // @[DCache.scala:183:25]
reg [2:0] probe_bits_opcode; // @[DCache.scala:184:29]
reg [1:0] probe_bits_param; // @[DCache.scala:184:29]
reg [3:0] probe_bits_size; // @[DCache.scala:184:29]
wire [3:0] nackResponseMessage_size = probe_bits_size; // @[Edges.scala:416:17]
wire [3:0] cleanReleaseMessage_size = probe_bits_size; // @[Edges.scala:416:17]
wire [3:0] dirtyReleaseMessage_size = probe_bits_size; // @[Edges.scala:433:17]
reg probe_bits_source; // @[DCache.scala:184:29]
assign nodeOut_c_bits_source = probe_bits_source; // @[DCache.scala:184:29]
wire nackResponseMessage_source = probe_bits_source; // @[Edges.scala:416:17]
wire cleanReleaseMessage_source = probe_bits_source; // @[Edges.scala:416:17]
wire dirtyReleaseMessage_source = probe_bits_source; // @[Edges.scala:433:17]
reg [31:0] probe_bits_address; // @[DCache.scala:184:29]
assign nodeOut_c_bits_address = probe_bits_address; // @[DCache.scala:184:29]
wire [31:0] nackResponseMessage_address = probe_bits_address; // @[Edges.scala:416:17]
wire [31:0] cleanReleaseMessage_address = probe_bits_address; // @[Edges.scala:416:17]
wire [31:0] dirtyReleaseMessage_address = probe_bits_address; // @[Edges.scala:433:17]
reg [7:0] probe_bits_mask; // @[DCache.scala:184:29]
reg [63:0] probe_bits_data; // @[DCache.scala:184:29]
reg probe_bits_corrupt; // @[DCache.scala:184:29]
wire s1_nack; // @[DCache.scala:185:28]
wire _s1_valid_masked_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37]
wire s1_valid_masked = s1_valid & _s1_valid_masked_T; // @[DCache.scala:182:25, :186:{34,37}]
wire _s1_valid_not_nacked_T = ~s1_nack; // @[DCache.scala:185:28, :187:41]
wire s1_valid_not_nacked = s1_valid & _s1_valid_not_nacked_T; // @[DCache.scala:182:25, :187:{38,41}]
wire _s0_clk_en_T = ~metaArb_io_out_bits_write; // @[DCache.scala:135:28, :190:43]
wire s0_clk_en = metaArb_io_out_valid & _s0_clk_en_T; // @[DCache.scala:135:28, :190:{40,43}]
wire _s1_tlb_req_T = s0_clk_en; // @[DCache.scala:190:40, :208:52]
wire [39:0] _s0_req_addr_T_2; // @[DCache.scala:193:21]
wire [39:0] s0_tlb_req_vaddr = s0_req_addr; // @[DCache.scala:192:24, :199:28]
wire [1:0] s0_tlb_req_size = s0_req_size; // @[DCache.scala:192:24, :199:28]
wire [1:0] s0_tlb_req_prv = s0_req_dprv; // @[DCache.scala:192:24, :199:28]
wire s0_tlb_req_v = s0_req_dv; // @[DCache.scala:192:24, :199:28]
wire s0_tlb_req_passthrough = s0_req_phys; // @[DCache.scala:192:24, :199:28]
wire [33:0] _s0_req_addr_T = metaArb_io_out_bits_addr[39:6]; // @[DCache.scala:135:28, :193:47]
wire [5:0] _s0_req_addr_T_1 = io_cpu_req_bits_addr_0[5:0]; // @[DCache.scala:101:7, :193:84]
assign _s0_req_addr_T_2 = {_s0_req_addr_T, _s0_req_addr_T_1}; // @[DCache.scala:193:{21,47,84}]
assign s0_req_addr = _s0_req_addr_T_2; // @[DCache.scala:192:24, :193:21]
assign s0_req_phys = ~metaArb_io_in_7_ready | io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :135:28, :192:24, :195:{9,34,48}]
reg [39:0] s1_req_addr; // @[DCache.scala:196:25]
assign pma_checker_io_req_bits_vaddr = s1_req_addr; // @[DCache.scala:120:32, :196:25]
reg [7:0] s1_req_tag; // @[DCache.scala:196:25]
reg [4:0] s1_req_cmd; // @[DCache.scala:196:25]
assign pma_checker_io_req_bits_cmd = s1_req_cmd; // @[DCache.scala:120:32, :196:25]
reg [1:0] s1_req_size; // @[DCache.scala:196:25]
assign pma_checker_io_req_bits_size = s1_req_size; // @[DCache.scala:120:32, :196:25]
wire [1:0] s1_mask_xwr_size = s1_req_size; // @[DCache.scala:196:25]
reg s1_req_signed; // @[DCache.scala:196:25]
reg [1:0] s1_req_dprv; // @[DCache.scala:196:25]
assign pma_checker_io_req_bits_prv = s1_req_dprv; // @[DCache.scala:120:32, :196:25]
reg s1_req_dv; // @[DCache.scala:196:25]
assign pma_checker_io_req_bits_v = s1_req_dv; // @[DCache.scala:120:32, :196:25]
reg s1_req_phys; // @[DCache.scala:196:25]
reg s1_req_no_resp; // @[DCache.scala:196:25]
reg s1_req_no_alloc; // @[DCache.scala:196:25]
reg s1_req_no_xcpt; // @[DCache.scala:196:25]
reg [63:0] s1_req_data; // @[DCache.scala:196:25]
reg [7:0] s1_req_mask; // @[DCache.scala:196:25]
wire [31:0] _s1_vaddr_T = s1_req_addr[39:8]; // @[DCache.scala:196:25, :197:56]
wire [7:0] _s1_vaddr_T_1 = s1_req_addr[7:0]; // @[DCache.scala:196:25, :197:78]
wire [39:0] s1_vaddr = {_s1_vaddr_T, _s1_vaddr_T_1}; // @[DCache.scala:197:{21,56,78}]
reg [39:0] s1_tlb_req_vaddr; // @[DCache.scala:208:29]
reg s1_tlb_req_passthrough; // @[DCache.scala:208:29]
reg [1:0] s1_tlb_req_size; // @[DCache.scala:208:29]
reg [4:0] s1_tlb_req_cmd; // @[DCache.scala:208:29]
reg [1:0] s1_tlb_req_prv; // @[DCache.scala:208:29]
reg s1_tlb_req_v; // @[DCache.scala:208:29]
wire _GEN_41 = s1_req_cmd == 5'h0; // @[package.scala:16:47]
wire _s1_read_T; // @[package.scala:16:47]
assign _s1_read_T = _GEN_41; // @[package.scala:16:47]
wire _pstore1_rmw_T; // @[package.scala:16:47]
assign _pstore1_rmw_T = _GEN_41; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_1; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_1 = _GEN_41; // @[package.scala:16:47]
wire _GEN_42 = s1_req_cmd == 5'h10; // @[package.scala:16:47]
wire _s1_read_T_1; // @[package.scala:16:47]
assign _s1_read_T_1 = _GEN_42; // @[package.scala:16:47]
wire _pstore1_rmw_T_1; // @[package.scala:16:47]
assign _pstore1_rmw_T_1 = _GEN_42; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_2; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_2 = _GEN_42; // @[package.scala:16:47]
wire _GEN_43 = s1_req_cmd == 5'h6; // @[package.scala:16:47]
wire _s1_read_T_2; // @[package.scala:16:47]
assign _s1_read_T_2 = _GEN_43; // @[package.scala:16:47]
wire _pstore1_rmw_T_2; // @[package.scala:16:47]
assign _pstore1_rmw_T_2 = _GEN_43; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_3; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_3 = _GEN_43; // @[package.scala:16:47]
wire _GEN_44 = s1_req_cmd == 5'h7; // @[package.scala:16:47]
wire _s1_read_T_3; // @[package.scala:16:47]
assign _s1_read_T_3 = _GEN_44; // @[package.scala:16:47]
wire _s1_write_T_3; // @[Consts.scala:90:66]
assign _s1_write_T_3 = _GEN_44; // @[package.scala:16:47]
wire _pstore1_rmw_T_3; // @[package.scala:16:47]
assign _pstore1_rmw_T_3 = _GEN_44; // @[package.scala:16:47]
wire _pstore1_rmw_T_28; // @[Consts.scala:90:66]
assign _pstore1_rmw_T_28 = _GEN_44; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_4; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_4 = _GEN_44; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_29; // @[Consts.scala:90:66]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_29 = _GEN_44; // @[package.scala:16:47]
wire _s1_read_T_4 = _s1_read_T | _s1_read_T_1; // @[package.scala:16:47, :81:59]
wire _s1_read_T_5 = _s1_read_T_4 | _s1_read_T_2; // @[package.scala:16:47, :81:59]
wire _s1_read_T_6 = _s1_read_T_5 | _s1_read_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_45 = s1_req_cmd == 5'h4; // @[package.scala:16:47]
wire _s1_read_T_7; // @[package.scala:16:47]
assign _s1_read_T_7 = _GEN_45; // @[package.scala:16:47]
wire _s1_write_T_5; // @[package.scala:16:47]
assign _s1_write_T_5 = _GEN_45; // @[package.scala:16:47]
wire _pstore1_rmw_T_7; // @[package.scala:16:47]
assign _pstore1_rmw_T_7 = _GEN_45; // @[package.scala:16:47]
wire _pstore1_rmw_T_30; // @[package.scala:16:47]
assign _pstore1_rmw_T_30 = _GEN_45; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_8; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_8 = _GEN_45; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_31; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_31 = _GEN_45; // @[package.scala:16:47]
wire _GEN_46 = s1_req_cmd == 5'h9; // @[package.scala:16:47]
wire _s1_read_T_8; // @[package.scala:16:47]
assign _s1_read_T_8 = _GEN_46; // @[package.scala:16:47]
wire _s1_write_T_6; // @[package.scala:16:47]
assign _s1_write_T_6 = _GEN_46; // @[package.scala:16:47]
wire _pstore1_rmw_T_8; // @[package.scala:16:47]
assign _pstore1_rmw_T_8 = _GEN_46; // @[package.scala:16:47]
wire _pstore1_rmw_T_31; // @[package.scala:16:47]
assign _pstore1_rmw_T_31 = _GEN_46; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_9; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_9 = _GEN_46; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_32; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_32 = _GEN_46; // @[package.scala:16:47]
wire _GEN_47 = s1_req_cmd == 5'hA; // @[package.scala:16:47]
wire _s1_read_T_9; // @[package.scala:16:47]
assign _s1_read_T_9 = _GEN_47; // @[package.scala:16:47]
wire _s1_write_T_7; // @[package.scala:16:47]
assign _s1_write_T_7 = _GEN_47; // @[package.scala:16:47]
wire _pstore1_rmw_T_9; // @[package.scala:16:47]
assign _pstore1_rmw_T_9 = _GEN_47; // @[package.scala:16:47]
wire _pstore1_rmw_T_32; // @[package.scala:16:47]
assign _pstore1_rmw_T_32 = _GEN_47; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_10; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_10 = _GEN_47; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_33; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_33 = _GEN_47; // @[package.scala:16:47]
wire _GEN_48 = s1_req_cmd == 5'hB; // @[package.scala:16:47]
wire _s1_read_T_10; // @[package.scala:16:47]
assign _s1_read_T_10 = _GEN_48; // @[package.scala:16:47]
wire _s1_write_T_8; // @[package.scala:16:47]
assign _s1_write_T_8 = _GEN_48; // @[package.scala:16:47]
wire _pstore1_rmw_T_10; // @[package.scala:16:47]
assign _pstore1_rmw_T_10 = _GEN_48; // @[package.scala:16:47]
wire _pstore1_rmw_T_33; // @[package.scala:16:47]
assign _pstore1_rmw_T_33 = _GEN_48; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_11; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_11 = _GEN_48; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_34; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_34 = _GEN_48; // @[package.scala:16:47]
wire _s1_read_T_11 = _s1_read_T_7 | _s1_read_T_8; // @[package.scala:16:47, :81:59]
wire _s1_read_T_12 = _s1_read_T_11 | _s1_read_T_9; // @[package.scala:16:47, :81:59]
wire _s1_read_T_13 = _s1_read_T_12 | _s1_read_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_49 = s1_req_cmd == 5'h8; // @[package.scala:16:47]
wire _s1_read_T_14; // @[package.scala:16:47]
assign _s1_read_T_14 = _GEN_49; // @[package.scala:16:47]
wire _s1_write_T_12; // @[package.scala:16:47]
assign _s1_write_T_12 = _GEN_49; // @[package.scala:16:47]
wire _pstore1_rmw_T_14; // @[package.scala:16:47]
assign _pstore1_rmw_T_14 = _GEN_49; // @[package.scala:16:47]
wire _pstore1_rmw_T_37; // @[package.scala:16:47]
assign _pstore1_rmw_T_37 = _GEN_49; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_15; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_15 = _GEN_49; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_38; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_38 = _GEN_49; // @[package.scala:16:47]
wire _GEN_50 = s1_req_cmd == 5'hC; // @[package.scala:16:47]
wire _s1_read_T_15; // @[package.scala:16:47]
assign _s1_read_T_15 = _GEN_50; // @[package.scala:16:47]
wire _s1_write_T_13; // @[package.scala:16:47]
assign _s1_write_T_13 = _GEN_50; // @[package.scala:16:47]
wire _pstore1_rmw_T_15; // @[package.scala:16:47]
assign _pstore1_rmw_T_15 = _GEN_50; // @[package.scala:16:47]
wire _pstore1_rmw_T_38; // @[package.scala:16:47]
assign _pstore1_rmw_T_38 = _GEN_50; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_16; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_16 = _GEN_50; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_39; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_39 = _GEN_50; // @[package.scala:16:47]
wire _GEN_51 = s1_req_cmd == 5'hD; // @[package.scala:16:47]
wire _s1_read_T_16; // @[package.scala:16:47]
assign _s1_read_T_16 = _GEN_51; // @[package.scala:16:47]
wire _s1_write_T_14; // @[package.scala:16:47]
assign _s1_write_T_14 = _GEN_51; // @[package.scala:16:47]
wire _pstore1_rmw_T_16; // @[package.scala:16:47]
assign _pstore1_rmw_T_16 = _GEN_51; // @[package.scala:16:47]
wire _pstore1_rmw_T_39; // @[package.scala:16:47]
assign _pstore1_rmw_T_39 = _GEN_51; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_17; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_17 = _GEN_51; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_40; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_40 = _GEN_51; // @[package.scala:16:47]
wire _GEN_52 = s1_req_cmd == 5'hE; // @[package.scala:16:47]
wire _s1_read_T_17; // @[package.scala:16:47]
assign _s1_read_T_17 = _GEN_52; // @[package.scala:16:47]
wire _s1_write_T_15; // @[package.scala:16:47]
assign _s1_write_T_15 = _GEN_52; // @[package.scala:16:47]
wire _pstore1_rmw_T_17; // @[package.scala:16:47]
assign _pstore1_rmw_T_17 = _GEN_52; // @[package.scala:16:47]
wire _pstore1_rmw_T_40; // @[package.scala:16:47]
assign _pstore1_rmw_T_40 = _GEN_52; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_18; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_18 = _GEN_52; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_41; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_41 = _GEN_52; // @[package.scala:16:47]
wire _GEN_53 = s1_req_cmd == 5'hF; // @[package.scala:16:47]
wire _s1_read_T_18; // @[package.scala:16:47]
assign _s1_read_T_18 = _GEN_53; // @[package.scala:16:47]
wire _s1_write_T_16; // @[package.scala:16:47]
assign _s1_write_T_16 = _GEN_53; // @[package.scala:16:47]
wire _pstore1_rmw_T_18; // @[package.scala:16:47]
assign _pstore1_rmw_T_18 = _GEN_53; // @[package.scala:16:47]
wire _pstore1_rmw_T_41; // @[package.scala:16:47]
assign _pstore1_rmw_T_41 = _GEN_53; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_19; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_19 = _GEN_53; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_42; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_42 = _GEN_53; // @[package.scala:16:47]
wire _s1_read_T_19 = _s1_read_T_14 | _s1_read_T_15; // @[package.scala:16:47, :81:59]
wire _s1_read_T_20 = _s1_read_T_19 | _s1_read_T_16; // @[package.scala:16:47, :81:59]
wire _s1_read_T_21 = _s1_read_T_20 | _s1_read_T_17; // @[package.scala:16:47, :81:59]
wire _s1_read_T_22 = _s1_read_T_21 | _s1_read_T_18; // @[package.scala:16:47, :81:59]
wire _s1_read_T_23 = _s1_read_T_13 | _s1_read_T_22; // @[package.scala:81:59]
wire s1_read = _s1_read_T_6 | _s1_read_T_23; // @[package.scala:81:59]
wire _GEN_54 = s1_req_cmd == 5'h1; // @[DCache.scala:196:25]
wire _s1_write_T; // @[Consts.scala:90:32]
assign _s1_write_T = _GEN_54; // @[Consts.scala:90:32]
wire _pstore1_rmw_T_25; // @[Consts.scala:90:32]
assign _pstore1_rmw_T_25 = _GEN_54; // @[Consts.scala:90:32]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_26; // @[Consts.scala:90:32]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_26 = _GEN_54; // @[Consts.scala:90:32]
wire _T_20 = s1_req_cmd == 5'h11; // @[DCache.scala:196:25]
wire _s1_write_T_1; // @[Consts.scala:90:49]
assign _s1_write_T_1 = _T_20; // @[Consts.scala:90:49]
wire _s1_mask_T; // @[DCache.scala:327:32]
assign _s1_mask_T = _T_20; // @[DCache.scala:327:32]
wire _pstore1_rmw_T_26; // @[Consts.scala:90:49]
assign _pstore1_rmw_T_26 = _T_20; // @[Consts.scala:90:49]
wire _pstore1_rmw_T_48; // @[DCache.scala:1191:35]
assign _pstore1_rmw_T_48 = _T_20; // @[DCache.scala:1191:35]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_27; // @[Consts.scala:90:49]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_27 = _T_20; // @[Consts.scala:90:49]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_49; // @[DCache.scala:1191:35]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_49 = _T_20; // @[DCache.scala:1191:35]
wire _s1_write_T_2 = _s1_write_T | _s1_write_T_1; // @[Consts.scala:90:{32,42,49}]
wire _s1_write_T_4 = _s1_write_T_2 | _s1_write_T_3; // @[Consts.scala:90:{42,59,66}]
wire _s1_write_T_9 = _s1_write_T_5 | _s1_write_T_6; // @[package.scala:16:47, :81:59]
wire _s1_write_T_10 = _s1_write_T_9 | _s1_write_T_7; // @[package.scala:16:47, :81:59]
wire _s1_write_T_11 = _s1_write_T_10 | _s1_write_T_8; // @[package.scala:16:47, :81:59]
wire _s1_write_T_17 = _s1_write_T_12 | _s1_write_T_13; // @[package.scala:16:47, :81:59]
wire _s1_write_T_18 = _s1_write_T_17 | _s1_write_T_14; // @[package.scala:16:47, :81:59]
wire _s1_write_T_19 = _s1_write_T_18 | _s1_write_T_15; // @[package.scala:16:47, :81:59]
wire _s1_write_T_20 = _s1_write_T_19 | _s1_write_T_16; // @[package.scala:16:47, :81:59]
wire _s1_write_T_21 = _s1_write_T_11 | _s1_write_T_20; // @[package.scala:81:59]
wire s1_write = _s1_write_T_4 | _s1_write_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire s1_readwrite = s1_read | s1_write; // @[DCache.scala:212:30]
wire _s1_sfence_T = s1_req_cmd == 5'h14; // @[DCache.scala:196:25, :213:30]
wire _GEN_55 = s1_req_cmd == 5'h15; // @[DCache.scala:196:25, :213:57]
wire _s1_sfence_T_1; // @[DCache.scala:213:57]
assign _s1_sfence_T_1 = _GEN_55; // @[DCache.scala:213:57]
wire _tlb_io_sfence_bits_hv_T; // @[DCache.scala:283:39]
assign _tlb_io_sfence_bits_hv_T = _GEN_55; // @[DCache.scala:213:57, :283:39]
wire _s1_sfence_T_2 = _s1_sfence_T | _s1_sfence_T_1; // @[DCache.scala:213:{30,43,57}]
wire _GEN_56 = s1_req_cmd == 5'h16; // @[DCache.scala:196:25, :213:85]
wire _s1_sfence_T_3; // @[DCache.scala:213:85]
assign _s1_sfence_T_3 = _GEN_56; // @[DCache.scala:213:85]
wire _tlb_io_sfence_bits_hg_T; // @[DCache.scala:284:39]
assign _tlb_io_sfence_bits_hg_T = _GEN_56; // @[DCache.scala:213:85, :284:39]
wire s1_sfence = _s1_sfence_T_2 | _s1_sfence_T_3; // @[DCache.scala:213:{43,71,85}]
wire _s1_flush_line_T = s1_req_cmd == 5'h5; // @[DCache.scala:196:25, :214:34]
wire _s1_flush_line_T_1 = s1_req_size[0]; // @[DCache.scala:196:25, :214:64]
wire _tlb_io_sfence_bits_rs1_T = s1_req_size[0]; // @[DCache.scala:196:25, :214:64, :279:40]
wire s1_flush_line = _s1_flush_line_T & _s1_flush_line_T_1; // @[DCache.scala:214:{34,50,64}]
reg s1_flush_valid; // @[DCache.scala:215:27]
reg cached_grant_wait; // @[DCache.scala:223:34]
reg resetting; // @[DCache.scala:224:26]
assign metaArb_io_in_0_valid = resetting; // @[DCache.scala:135:28, :224:26]
reg [3:0] flushCounter; // @[DCache.scala:225:29]
reg release_ack_wait; // @[DCache.scala:226:33]
reg [31:0] release_ack_addr; // @[DCache.scala:227:29]
reg [3:0] release_state; // @[DCache.scala:228:30]
reg [3:0] refill_way; // @[DCache.scala:229:23]
assign metaArb_io_in_3_bits_way_en = refill_way; // @[DCache.scala:135:28, :229:23]
assign dataArb_io_in_1_bits_way_en = refill_way; // @[DCache.scala:152:28, :229:23]
wire _any_pstore_valid_T; // @[DCache.scala:508:36]
wire any_pstore_valid; // @[DCache.scala:230:30]
wire _T_106 = release_state == 4'h1; // @[package.scala:16:47]
wire _inWriteback_T; // @[package.scala:16:47]
assign _inWriteback_T = _T_106; // @[package.scala:16:47]
wire _canAcceptCachedGrant_T; // @[package.scala:16:47]
assign _canAcceptCachedGrant_T = _T_106; // @[package.scala:16:47]
wire _inWriteback_T_1 = release_state == 4'h2; // @[package.scala:16:47]
wire inWriteback = _inWriteback_T | _inWriteback_T_1; // @[package.scala:16:47, :81:59]
assign metaArb_io_in_4_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24]
assign metaArb_io_in_5_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24]
assign metaArb_io_in_6_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24]
assign metaArb_io_in_7_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24]
wire _io_cpu_req_ready_T = ~(|release_state); // @[DCache.scala:228:30, :233:38]
wire _io_cpu_req_ready_T_1 = ~cached_grant_wait; // @[DCache.scala:223:34, :233:54]
wire _io_cpu_req_ready_T_2 = _io_cpu_req_ready_T & _io_cpu_req_ready_T_1; // @[DCache.scala:233:{38,51,54}]
wire _io_cpu_req_ready_T_3 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :233:76]
wire _io_cpu_req_ready_T_4 = _io_cpu_req_ready_T_2 & _io_cpu_req_ready_T_3; // @[DCache.scala:233:{51,73,76}]
reg uncachedInFlight_0; // @[DCache.scala:236:33]
wire _s2_valid_cached_miss_T_2 = uncachedInFlight_0; // @[DCache.scala:236:33, :425:88]
wire _s2_valid_uncached_pending_T_1 = uncachedInFlight_0; // @[DCache.scala:236:33, :430:92]
wire _io_cpu_ordered_T_6 = uncachedInFlight_0; // @[DCache.scala:236:33, :929:142]
wire _io_cpu_store_pending_T_24 = uncachedInFlight_0; // @[DCache.scala:236:33, :930:97]
wire _clock_en_reg_T_21 = uncachedInFlight_0; // @[DCache.scala:236:33, :1072:50]
reg [39:0] uncachedReqs_0_addr; // @[DCache.scala:237:25]
wire [39:0] uncachedResp_addr = uncachedReqs_0_addr; // @[DCache.scala:237:25, :238:30]
reg [7:0] uncachedReqs_0_tag; // @[DCache.scala:237:25]
wire [7:0] uncachedResp_tag = uncachedReqs_0_tag; // @[DCache.scala:237:25, :238:30]
reg [4:0] uncachedReqs_0_cmd; // @[DCache.scala:237:25]
wire [4:0] uncachedResp_cmd = uncachedReqs_0_cmd; // @[DCache.scala:237:25, :238:30]
reg [1:0] uncachedReqs_0_size; // @[DCache.scala:237:25]
wire [1:0] uncachedResp_size = uncachedReqs_0_size; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_signed; // @[DCache.scala:237:25]
wire uncachedResp_signed = uncachedReqs_0_signed; // @[DCache.scala:237:25, :238:30]
reg [1:0] uncachedReqs_0_dprv; // @[DCache.scala:237:25]
wire [1:0] uncachedResp_dprv = uncachedReqs_0_dprv; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_dv; // @[DCache.scala:237:25]
wire uncachedResp_dv = uncachedReqs_0_dv; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_phys; // @[DCache.scala:237:25]
wire uncachedResp_phys = uncachedReqs_0_phys; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_no_resp; // @[DCache.scala:237:25]
wire uncachedResp_no_resp = uncachedReqs_0_no_resp; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_no_alloc; // @[DCache.scala:237:25]
wire uncachedResp_no_alloc = uncachedReqs_0_no_alloc; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25]
wire uncachedResp_no_xcpt = uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25, :238:30]
reg [63:0] uncachedReqs_0_data; // @[DCache.scala:237:25]
wire [63:0] uncachedResp_data = uncachedReqs_0_data; // @[DCache.scala:237:25, :238:30]
reg [7:0] uncachedReqs_0_mask; // @[DCache.scala:237:25]
wire [7:0] uncachedResp_mask = uncachedReqs_0_mask; // @[DCache.scala:237:25, :238:30]
wire _dataArb_io_in_3_valid_T_56 = ~_dataArb_io_in_3_valid_T_55; // @[DCache.scala:1186:11]
assign dataArb_io_in_3_valid = _dataArb_io_in_3_valid_T_58; // @[DCache.scala:152:28, :242:46]
wire [31:0] _dataArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[39:8]; // @[DCache.scala:101:7, :245:89]
wire [31:0] _metaArb_io_in_1_bits_addr_T = io_cpu_req_bits_addr_0[39:8]; // @[DCache.scala:101:7, :245:89, :454:58]
wire [31:0] _metaArb_io_in_2_bits_addr_T = io_cpu_req_bits_addr_0[39:8]; // @[DCache.scala:101:7, :245:89, :466:58]
wire [31:0] _metaArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[39:8]; // @[DCache.scala:101:7, :245:89, :745:58]
wire [31:0] _metaArb_io_in_4_bits_addr_T = io_cpu_req_bits_addr_0[39:8]; // @[DCache.scala:101:7, :245:89, :912:58]
wire [31:0] _metaArb_io_in_5_bits_addr_T = io_cpu_req_bits_addr_0[39:8]; // @[DCache.scala:101:7, :245:89, :1018:58]
wire [7:0] _dataArb_io_in_3_bits_addr_T_1 = io_cpu_req_bits_addr_0[7:0]; // @[DCache.scala:101:7, :245:120]
wire [39:0] _dataArb_io_in_3_bits_addr_T_2 = {_dataArb_io_in_3_bits_addr_T, _dataArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:245:{36,89,120}]
assign dataArb_io_in_3_bits_addr = _dataArb_io_in_3_bits_addr_T_2[7:0]; // @[DCache.scala:152:28, :245:{30,36}]
wire _s1_did_read_T_54 = dataArb_io_in_3_ready & _s1_did_read_T_53; // @[DCache.scala:152:28, :259:{54,75}]
reg s1_did_read; // @[DCache.scala:259:30]
wire _s2_data_word_en_T = s1_did_read; // @[DCache.scala:259:30, :367:63]
assign _metaArb_io_in_7_bits_idx_T = _dataArb_io_in_3_bits_addr_T_2[7:6]; // @[DCache.scala:245:36, :263:58]
assign metaArb_io_in_7_bits_idx = _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:135:28, :263:58]
wire _s1_cmd_uses_tlb_T = s1_readwrite | s1_flush_line; // @[DCache.scala:212:30, :214:50, :270:38]
wire _s1_cmd_uses_tlb_T_1 = s1_req_cmd == 5'h17; // @[DCache.scala:196:25, :270:69]
wire s1_cmd_uses_tlb = _s1_cmd_uses_tlb_T | _s1_cmd_uses_tlb_T_1; // @[DCache.scala:270:{38,55,69}]
wire _tlb_io_req_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :273:55]
wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[DCache.scala:182:25, :273:{52,55}]
wire _tlb_io_req_valid_T_2 = _tlb_io_req_valid_T_1 & s1_cmd_uses_tlb; // @[DCache.scala:270:55, :273:{52,71}]
wire _tlb_io_req_valid_T_3 = _tlb_io_req_valid_T_2; // @[DCache.scala:273:{40,71}]
wire _T_10 = ~_tlb_io_req_ready & ~io_ptw_resp_valid_0 & ~io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :119:19, :275:{9,27,30,53,56}]
wire _T_14 = s1_valid & s1_cmd_uses_tlb & _tlb_io_resp_miss; // @[DCache.scala:119:19, :182:25, :270:55, :276:{39,58}]
wire _tlb_io_sfence_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :278:38]
wire _tlb_io_sfence_valid_T_1 = s1_valid & _tlb_io_sfence_valid_T; // @[DCache.scala:182:25, :278:{35,38}]
wire _tlb_io_sfence_valid_T_2 = _tlb_io_sfence_valid_T_1 & s1_sfence; // @[DCache.scala:213:71, :278:{35,54}]
wire _tlb_io_sfence_bits_rs2_T = s1_req_size[1]; // @[DCache.scala:196:25, :280:40]
wire [19:0] _s1_paddr_T = s1_req_addr[31:12]; // @[DCache.scala:196:25, :298:55]
wire [19:0] _s1_paddr_T_1 = _tlb_io_resp_paddr[31:12]; // @[DCache.scala:119:19, :298:99]
wire [19:0] _s1_paddr_T_2 = _s1_paddr_T_1; // @[DCache.scala:298:{25,99}]
wire [11:0] _s1_paddr_T_3 = s1_req_addr[11:0]; // @[DCache.scala:196:25, :298:125]
wire [31:0] s1_paddr = {_s1_paddr_T_2, _s1_paddr_T_3}; // @[DCache.scala:298:{21,25,125}]
wire [1:0] _s1_victim_way_T; // @[package.scala:163:13]
wire [1:0] s1_victim_way; // @[DCache.scala:299:27]
assign rerocc_tile_dcache_tag_array_MPORT_en = metaArb_io_out_valid & metaArb_io_out_bits_write; // @[DCache.scala:135:28, :310:27]
assign wmask_0 = metaArb_io_out_bits_way_en[0]; // @[DCache.scala:135:28, :311:74]
assign wmask_1 = metaArb_io_out_bits_way_en[1]; // @[DCache.scala:135:28, :311:74]
assign wmask_2 = metaArb_io_out_bits_way_en[2]; // @[DCache.scala:135:28, :311:74]
assign wmask_3 = metaArb_io_out_bits_way_en[3]; // @[DCache.scala:135:28, :311:74]
wire _s1_meta_T = ~metaArb_io_out_bits_write; // @[DCache.scala:135:28, :190:43, :314:62]
assign _s1_meta_T_1 = metaArb_io_out_valid & _s1_meta_T; // @[DCache.scala:135:28, :314:{59,62}]
wire [1:0] _s1_meta_uncorrected_T_1; // @[DCache.scala:315:80]
wire [23:0] _s1_meta_uncorrected_T; // @[DCache.scala:315:80]
wire [1:0] s1_meta_uncorrected_0_coh_state; // @[DCache.scala:315:80]
wire [23:0] s1_meta_uncorrected_0_tag; // @[DCache.scala:315:80]
assign _s1_meta_uncorrected_T = _s1_meta_uncorrected_WIRE[23:0]; // @[DCache.scala:315:80]
assign s1_meta_uncorrected_0_tag = _s1_meta_uncorrected_T; // @[DCache.scala:315:80]
assign _s1_meta_uncorrected_T_1 = _s1_meta_uncorrected_WIRE[25:24]; // @[DCache.scala:315:80]
assign s1_meta_uncorrected_0_coh_state = _s1_meta_uncorrected_T_1; // @[DCache.scala:315:80]
wire [1:0] _s1_meta_uncorrected_T_3; // @[DCache.scala:315:80]
wire [23:0] _s1_meta_uncorrected_T_2; // @[DCache.scala:315:80]
wire [1:0] s1_meta_uncorrected_1_coh_state; // @[DCache.scala:315:80]
wire [23:0] s1_meta_uncorrected_1_tag; // @[DCache.scala:315:80]
assign _s1_meta_uncorrected_T_2 = _s1_meta_uncorrected_WIRE_1[23:0]; // @[DCache.scala:315:80]
assign s1_meta_uncorrected_1_tag = _s1_meta_uncorrected_T_2; // @[DCache.scala:315:80]
assign _s1_meta_uncorrected_T_3 = _s1_meta_uncorrected_WIRE_1[25:24]; // @[DCache.scala:315:80]
assign s1_meta_uncorrected_1_coh_state = _s1_meta_uncorrected_T_3; // @[DCache.scala:315:80]
wire [1:0] _s1_meta_uncorrected_T_5; // @[DCache.scala:315:80]
wire [23:0] _s1_meta_uncorrected_T_4; // @[DCache.scala:315:80]
wire [1:0] s1_meta_uncorrected_2_coh_state; // @[DCache.scala:315:80]
wire [23:0] s1_meta_uncorrected_2_tag; // @[DCache.scala:315:80]
assign _s1_meta_uncorrected_T_4 = _s1_meta_uncorrected_WIRE_2[23:0]; // @[DCache.scala:315:80]
assign s1_meta_uncorrected_2_tag = _s1_meta_uncorrected_T_4; // @[DCache.scala:315:80]
assign _s1_meta_uncorrected_T_5 = _s1_meta_uncorrected_WIRE_2[25:24]; // @[DCache.scala:315:80]
assign s1_meta_uncorrected_2_coh_state = _s1_meta_uncorrected_T_5; // @[DCache.scala:315:80]
wire [1:0] _s1_meta_uncorrected_T_7; // @[DCache.scala:315:80]
wire [23:0] _s1_meta_uncorrected_T_6; // @[DCache.scala:315:80]
wire [1:0] s1_meta_uncorrected_3_coh_state; // @[DCache.scala:315:80]
wire [23:0] s1_meta_uncorrected_3_tag; // @[DCache.scala:315:80]
assign _s1_meta_uncorrected_T_6 = _s1_meta_uncorrected_WIRE_3[23:0]; // @[DCache.scala:315:80]
assign s1_meta_uncorrected_3_tag = _s1_meta_uncorrected_T_6; // @[DCache.scala:315:80]
assign _s1_meta_uncorrected_T_7 = _s1_meta_uncorrected_WIRE_3[25:24]; // @[DCache.scala:315:80]
assign s1_meta_uncorrected_3_coh_state = _s1_meta_uncorrected_T_7; // @[DCache.scala:315:80]
wire [23:0] s1_tag = s1_paddr[31:8]; // @[DCache.scala:298:21, :316:29]
wire _s1_meta_hit_way_T = |s1_meta_uncorrected_0_coh_state; // @[Metadata.scala:50:45]
wire _GEN_57 = s1_meta_uncorrected_0_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83]
wire _s1_meta_hit_way_T_1; // @[DCache.scala:317:83]
assign _s1_meta_hit_way_T_1 = _GEN_57; // @[DCache.scala:317:83]
wire _s1_meta_hit_state_T; // @[DCache.scala:319:48]
assign _s1_meta_hit_state_T = _GEN_57; // @[DCache.scala:317:83, :319:48]
wire _s1_meta_hit_way_T_2 = _s1_meta_hit_way_T & _s1_meta_hit_way_T_1; // @[Metadata.scala:50:45]
wire _s1_meta_hit_way_T_3 = |s1_meta_uncorrected_1_coh_state; // @[Metadata.scala:50:45]
wire _GEN_58 = s1_meta_uncorrected_1_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83]
wire _s1_meta_hit_way_T_4; // @[DCache.scala:317:83]
assign _s1_meta_hit_way_T_4 = _GEN_58; // @[DCache.scala:317:83]
wire _s1_meta_hit_state_T_4; // @[DCache.scala:319:48]
assign _s1_meta_hit_state_T_4 = _GEN_58; // @[DCache.scala:317:83, :319:48]
wire _s1_meta_hit_way_T_5 = _s1_meta_hit_way_T_3 & _s1_meta_hit_way_T_4; // @[Metadata.scala:50:45]
wire _s1_meta_hit_way_T_6 = |s1_meta_uncorrected_2_coh_state; // @[Metadata.scala:50:45]
wire _GEN_59 = s1_meta_uncorrected_2_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83]
wire _s1_meta_hit_way_T_7; // @[DCache.scala:317:83]
assign _s1_meta_hit_way_T_7 = _GEN_59; // @[DCache.scala:317:83]
wire _s1_meta_hit_state_T_8; // @[DCache.scala:319:48]
assign _s1_meta_hit_state_T_8 = _GEN_59; // @[DCache.scala:317:83, :319:48]
wire _s1_meta_hit_way_T_8 = _s1_meta_hit_way_T_6 & _s1_meta_hit_way_T_7; // @[Metadata.scala:50:45]
wire _s1_meta_hit_way_T_9 = |s1_meta_uncorrected_3_coh_state; // @[Metadata.scala:50:45]
wire _GEN_60 = s1_meta_uncorrected_3_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83]
wire _s1_meta_hit_way_T_10; // @[DCache.scala:317:83]
assign _s1_meta_hit_way_T_10 = _GEN_60; // @[DCache.scala:317:83]
wire _s1_meta_hit_state_T_12; // @[DCache.scala:319:48]
assign _s1_meta_hit_state_T_12 = _GEN_60; // @[DCache.scala:317:83, :319:48]
wire _s1_meta_hit_way_T_11 = _s1_meta_hit_way_T_9 & _s1_meta_hit_way_T_10; // @[Metadata.scala:50:45]
wire [1:0] s1_meta_hit_way_lo = {_s1_meta_hit_way_T_5, _s1_meta_hit_way_T_2}; // @[package.scala:45:27]
wire [1:0] s1_meta_hit_way_hi = {_s1_meta_hit_way_T_11, _s1_meta_hit_way_T_8}; // @[package.scala:45:27]
wire [3:0] s1_hit_way = {s1_meta_hit_way_hi, s1_meta_hit_way_lo}; // @[package.scala:45:27]
wire _s1_meta_hit_state_T_1 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62]
wire _s1_meta_hit_state_T_2 = _s1_meta_hit_state_T & _s1_meta_hit_state_T_1; // @[DCache.scala:319:{48,59,62}]
wire [1:0] _s1_meta_hit_state_T_3 = _s1_meta_hit_state_T_2 ? s1_meta_uncorrected_0_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}]
wire _s1_meta_hit_state_T_5 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62]
wire _s1_meta_hit_state_T_6 = _s1_meta_hit_state_T_4 & _s1_meta_hit_state_T_5; // @[DCache.scala:319:{48,59,62}]
wire [1:0] _s1_meta_hit_state_T_7 = _s1_meta_hit_state_T_6 ? s1_meta_uncorrected_1_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}]
wire _s1_meta_hit_state_T_9 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62]
wire _s1_meta_hit_state_T_10 = _s1_meta_hit_state_T_8 & _s1_meta_hit_state_T_9; // @[DCache.scala:319:{48,59,62}]
wire [1:0] _s1_meta_hit_state_T_11 = _s1_meta_hit_state_T_10 ? s1_meta_uncorrected_2_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}]
wire _s1_meta_hit_state_T_13 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62]
wire _s1_meta_hit_state_T_14 = _s1_meta_hit_state_T_12 & _s1_meta_hit_state_T_13; // @[DCache.scala:319:{48,59,62}]
wire [1:0] _s1_meta_hit_state_T_15 = _s1_meta_hit_state_T_14 ? s1_meta_uncorrected_3_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}]
wire [1:0] _s1_meta_hit_state_T_16 = _s1_meta_hit_state_T_3 | _s1_meta_hit_state_T_7; // @[DCache.scala:319:41, :320:19]
wire [1:0] _s1_meta_hit_state_T_17 = _s1_meta_hit_state_T_16 | _s1_meta_hit_state_T_11; // @[DCache.scala:319:41, :320:19]
wire [1:0] _s1_meta_hit_state_T_18 = _s1_meta_hit_state_T_17 | _s1_meta_hit_state_T_15; // @[DCache.scala:319:41, :320:19]
wire [1:0] _s1_meta_hit_state_WIRE = _s1_meta_hit_state_T_18; // @[DCache.scala:320:{19,32}]
wire [1:0] _s1_meta_hit_state_T_19; // @[DCache.scala:320:32]
wire [1:0] s1_hit_state_state; // @[DCache.scala:320:32]
assign _s1_meta_hit_state_T_19 = _s1_meta_hit_state_WIRE; // @[DCache.scala:320:32]
assign s1_hit_state_state = _s1_meta_hit_state_T_19; // @[DCache.scala:320:32]
wire [3:0] _s1_data_way_T = inWriteback ? releaseWay : s1_hit_way; // @[package.scala:45:27, :81:59]
wire [4:0] s1_data_way; // @[DCache.scala:323:32]
wire [7:0] _tl_d_data_encoded_T = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_13 = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_1 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_14 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_2 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_15 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_3 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_16 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_4 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_17 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_5 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_18 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_6 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_19 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_7 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_20 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50]
wire [15:0] tl_d_data_encoded_lo_lo = {_tl_d_data_encoded_T_1, _tl_d_data_encoded_T}; // @[package.scala:45:27, :211:50]
wire [15:0] tl_d_data_encoded_lo_hi = {_tl_d_data_encoded_T_3, _tl_d_data_encoded_T_2}; // @[package.scala:45:27, :211:50]
wire [31:0] tl_d_data_encoded_lo = {tl_d_data_encoded_lo_hi, tl_d_data_encoded_lo_lo}; // @[package.scala:45:27]
wire [15:0] tl_d_data_encoded_hi_lo = {_tl_d_data_encoded_T_5, _tl_d_data_encoded_T_4}; // @[package.scala:45:27, :211:50]
wire [15:0] tl_d_data_encoded_hi_hi = {_tl_d_data_encoded_T_7, _tl_d_data_encoded_T_6}; // @[package.scala:45:27, :211:50]
wire [31:0] tl_d_data_encoded_hi = {tl_d_data_encoded_hi_hi, tl_d_data_encoded_hi_lo}; // @[package.scala:45:27]
wire [63:0] _tl_d_data_encoded_T_8 = {tl_d_data_encoded_hi, tl_d_data_encoded_lo}; // @[package.scala:45:27]
wire [63:0] _tl_d_data_encoded_T_21; // @[package.scala:45:27]
assign dataArb_io_in_1_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31]
assign dataArb_io_in_2_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31]
assign dataArb_io_in_3_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31]
wire [63:0] s1_all_data_ways_4 = tl_d_data_encoded; // @[DCache.scala:324:31, :325:33]
wire [63:0] s2_data_s1_way_words_0_0 = s1_all_data_ways_0; // @[package.scala:211:50]
wire [63:0] s2_data_s1_way_words_1_0 = s1_all_data_ways_1; // @[package.scala:211:50]
wire [63:0] s2_data_s1_way_words_2_0 = s1_all_data_ways_2; // @[package.scala:211:50]
wire [63:0] s2_data_s1_way_words_3_0 = s1_all_data_ways_3; // @[package.scala:211:50]
wire [63:0] s2_data_s1_way_words_4_0 = s1_all_data_ways_4; // @[package.scala:211:50]
wire _s1_mask_xwr_upper_T = s1_req_addr[0]; // @[DCache.scala:196:25]
wire _s1_mask_xwr_lower_T = s1_req_addr[0]; // @[DCache.scala:196:25]
wire _s1_mask_xwr_upper_T_1 = _s1_mask_xwr_upper_T; // @[AMOALU.scala:20:{22,27}]
wire _s1_mask_xwr_upper_T_2 = |s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53]
wire _s1_mask_xwr_upper_T_3 = _s1_mask_xwr_upper_T_2; // @[AMOALU.scala:20:{47,53}]
wire s1_mask_xwr_upper = _s1_mask_xwr_upper_T_1 | _s1_mask_xwr_upper_T_3; // @[AMOALU.scala:20:{22,42,47}]
wire s1_mask_xwr_lower = ~_s1_mask_xwr_lower_T; // @[AMOALU.scala:21:{22,27}]
wire [1:0] _s1_mask_xwr_T = {s1_mask_xwr_upper, s1_mask_xwr_lower}; // @[AMOALU.scala:20:42, :21:22, :22:16]
wire _s1_mask_xwr_upper_T_4 = s1_req_addr[1]; // @[DCache.scala:196:25]
wire _s1_mask_xwr_lower_T_1 = s1_req_addr[1]; // @[DCache.scala:196:25]
wire [1:0] _s1_mask_xwr_upper_T_5 = _s1_mask_xwr_upper_T_4 ? _s1_mask_xwr_T : 2'h0; // @[AMOALU.scala:20:{22,27}, :22:16]
wire _s1_mask_xwr_upper_T_6 = s1_mask_xwr_size[1]; // @[AMOALU.scala:11:18, :20:53]
wire [1:0] _s1_mask_xwr_upper_T_7 = {2{_s1_mask_xwr_upper_T_6}}; // @[AMOALU.scala:20:{47,53}]
wire [1:0] s1_mask_xwr_upper_1 = _s1_mask_xwr_upper_T_5 | _s1_mask_xwr_upper_T_7; // @[AMOALU.scala:20:{22,42,47}]
wire [1:0] s1_mask_xwr_lower_1 = _s1_mask_xwr_lower_T_1 ? 2'h0 : _s1_mask_xwr_T; // @[AMOALU.scala:21:{22,27}, :22:16]
wire [3:0] _s1_mask_xwr_T_1 = {s1_mask_xwr_upper_1, s1_mask_xwr_lower_1}; // @[AMOALU.scala:20:42, :21:22, :22:16]
wire _s1_mask_xwr_upper_T_8 = s1_req_addr[2]; // @[DCache.scala:196:25]
wire _s1_mask_xwr_lower_T_2 = s1_req_addr[2]; // @[DCache.scala:196:25]
wire [3:0] _s1_mask_xwr_upper_T_9 = _s1_mask_xwr_upper_T_8 ? _s1_mask_xwr_T_1 : 4'h0; // @[AMOALU.scala:20:{22,27}, :22:16]
wire _s1_mask_xwr_upper_T_10 = &s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53]
wire [3:0] _s1_mask_xwr_upper_T_11 = {4{_s1_mask_xwr_upper_T_10}}; // @[AMOALU.scala:20:{47,53}]
wire [3:0] s1_mask_xwr_upper_2 = _s1_mask_xwr_upper_T_9 | _s1_mask_xwr_upper_T_11; // @[AMOALU.scala:20:{22,42,47}]
wire [3:0] s1_mask_xwr_lower_2 = _s1_mask_xwr_lower_T_2 ? 4'h0 : _s1_mask_xwr_T_1; // @[AMOALU.scala:21:{22,27}, :22:16]
wire [7:0] s1_mask_xwr = {s1_mask_xwr_upper_2, s1_mask_xwr_lower_2}; // @[AMOALU.scala:20:42, :21:22, :22:16]
wire [7:0] s1_mask = _s1_mask_T ? io_cpu_s1_data_mask_0 : s1_mask_xwr; // @[DCache.scala:101:7, :327:{20,32}]
wire _s2_valid_T = ~s1_sfence; // @[DCache.scala:213:71, :331:45]
wire _s2_valid_T_1 = s1_valid_masked & _s2_valid_T; // @[DCache.scala:186:34, :331:{42,45}]
reg s2_valid; // @[DCache.scala:331:25]
wire [1:0] _s2_valid_no_xcpt_T = {io_cpu_s2_xcpt_ae_ld_0, io_cpu_s2_xcpt_ae_st_0}; // @[DCache.scala:101:7, :332:54]
wire [1:0] _s2_valid_no_xcpt_T_2 = {io_cpu_s2_xcpt_pf_ld_0, io_cpu_s2_xcpt_pf_st_0}; // @[DCache.scala:101:7, :332:54]
wire [1:0] _s2_valid_no_xcpt_T_3 = {io_cpu_s2_xcpt_ma_ld_0, io_cpu_s2_xcpt_ma_st_0}; // @[DCache.scala:101:7, :332:54]
wire [3:0] s2_valid_no_xcpt_lo = {2'h0, _s2_valid_no_xcpt_T}; // @[DCache.scala:332:54]
wire [3:0] s2_valid_no_xcpt_hi = {_s2_valid_no_xcpt_T_3, _s2_valid_no_xcpt_T_2}; // @[DCache.scala:332:54]
wire [7:0] _s2_valid_no_xcpt_T_4 = {s2_valid_no_xcpt_hi, s2_valid_no_xcpt_lo}; // @[DCache.scala:332:54]
wire _s2_valid_no_xcpt_T_5 = |_s2_valid_no_xcpt_T_4; // @[DCache.scala:332:{54,61}]
wire _s2_valid_no_xcpt_T_6 = ~_s2_valid_no_xcpt_T_5; // @[DCache.scala:332:{38,61}]
wire s2_valid_no_xcpt = s2_valid & _s2_valid_no_xcpt_T_6; // @[DCache.scala:331:25, :332:{35,38}]
reg s2_probe; // @[DCache.scala:333:25]
wire _releaseInFlight_T = s1_probe | s2_probe; // @[DCache.scala:183:25, :333:25, :334:34]
wire _releaseInFlight_T_1 = |release_state; // @[DCache.scala:228:30, :233:38, :334:63]
wire releaseInFlight = _releaseInFlight_T | _releaseInFlight_T_1; // @[DCache.scala:334:{34,46,63}]
wire _s2_not_nacked_in_s1_T = ~s1_nack; // @[DCache.scala:185:28, :187:41, :335:37]
reg s2_not_nacked_in_s1; // @[DCache.scala:335:36]
wire s2_valid_not_nacked_in_s1 = s2_valid & s2_not_nacked_in_s1; // @[DCache.scala:331:25, :335:36, :336:44]
wire s2_valid_masked = s2_valid_no_xcpt & s2_not_nacked_in_s1; // @[DCache.scala:332:35, :335:36, :337:42]
wire s2_valid_not_killed = s2_valid_masked; // @[DCache.scala:337:42, :338:45]
wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :397:71]
wire _s2_dont_nack_misc_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :441:43]
reg [39:0] s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _put_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _putpartial_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_4 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_64 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_124 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_184 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_244 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_304 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_364 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_424 = s2_req_addr; // @[DCache.scala:339:19]
wire [39:0] _atomics_legal_T_484 = s2_req_addr; // @[DCache.scala:339:19]
reg [7:0] s2_req_tag; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_tag_0 = s2_req_tag; // @[DCache.scala:101:7, :339:19]
reg [4:0] s2_req_cmd; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_cmd_0 = s2_req_cmd; // @[DCache.scala:101:7, :339:19]
reg [1:0] s2_req_size; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_size_0 = s2_req_size; // @[DCache.scala:101:7, :339:19]
wire [1:0] size = s2_req_size; // @[DCache.scala:339:19]
reg s2_req_signed; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_signed_0 = s2_req_signed; // @[DCache.scala:101:7, :339:19]
reg [1:0] s2_req_dprv; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_dprv_0 = s2_req_dprv; // @[DCache.scala:101:7, :339:19]
reg s2_req_dv; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_dv_0 = s2_req_dv; // @[DCache.scala:101:7, :339:19]
reg s2_req_phys; // @[DCache.scala:339:19]
reg s2_req_no_resp; // @[DCache.scala:339:19]
reg s2_req_no_alloc; // @[DCache.scala:339:19]
reg s2_req_no_xcpt; // @[DCache.scala:339:19]
reg [63:0] s2_req_data; // @[DCache.scala:339:19]
reg [7:0] s2_req_mask; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_mask_0 = s2_req_mask; // @[DCache.scala:101:7, :339:19]
wire _GEN_61 = s2_req_cmd == 5'h5; // @[DCache.scala:339:19, :340:37]
wire _s2_cmd_flush_all_T; // @[DCache.scala:340:37]
assign _s2_cmd_flush_all_T = _GEN_61; // @[DCache.scala:340:37]
wire _s2_cmd_flush_line_T; // @[DCache.scala:341:38]
assign _s2_cmd_flush_line_T = _GEN_61; // @[DCache.scala:340:37, :341:38]
wire _s2_cmd_flush_all_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68]
wire _s2_cmd_flush_line_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68, :341:68]
wire _s2_cmd_flush_all_T_2 = ~_s2_cmd_flush_all_T_1; // @[DCache.scala:340:{56,68}]
wire s2_cmd_flush_all = _s2_cmd_flush_all_T & _s2_cmd_flush_all_T_2; // @[DCache.scala:340:{37,53,56}]
wire s2_cmd_flush_line = _s2_cmd_flush_line_T & _s2_cmd_flush_line_T_1; // @[DCache.scala:341:{38,54,68}]
reg s2_tlb_xcpt_miss; // @[DCache.scala:342:24]
reg [31:0] s2_tlb_xcpt_paddr; // @[DCache.scala:342:24]
reg [39:0] s2_tlb_xcpt_gpa; // @[DCache.scala:342:24]
assign io_cpu_s2_gpa_0 = s2_tlb_xcpt_gpa; // @[DCache.scala:101:7, :342:24]
reg s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24]
reg [1:0] s2_tlb_xcpt_size; // @[DCache.scala:342:24]
reg [4:0] s2_tlb_xcpt_cmd; // @[DCache.scala:342:24]
reg s2_pma_miss; // @[DCache.scala:343:19]
reg [31:0] s2_pma_paddr; // @[DCache.scala:343:19]
reg [39:0] s2_pma_gpa; // @[DCache.scala:343:19]
reg s2_pma_pf_ld; // @[DCache.scala:343:19]
reg s2_pma_pf_st; // @[DCache.scala:343:19]
reg s2_pma_pf_inst; // @[DCache.scala:343:19]
reg s2_pma_ae_ld; // @[DCache.scala:343:19]
reg s2_pma_ae_st; // @[DCache.scala:343:19]
reg s2_pma_ae_inst; // @[DCache.scala:343:19]
reg s2_pma_ma_ld; // @[DCache.scala:343:19]
reg s2_pma_ma_st; // @[DCache.scala:343:19]
reg s2_pma_cacheable; // @[DCache.scala:343:19]
reg s2_pma_must_alloc; // @[DCache.scala:343:19]
reg s2_pma_prefetchable; // @[DCache.scala:343:19]
reg [1:0] s2_pma_size; // @[DCache.scala:343:19]
reg [4:0] s2_pma_cmd; // @[DCache.scala:343:19]
reg [39:0] s2_uncached_resp_addr; // @[DCache.scala:344:34]
wire _T_30 = s1_valid_not_nacked | s1_flush_valid; // @[DCache.scala:187:38, :215:27, :345:29]
wire _s2_vaddr_T; // @[DCache.scala:351:62]
assign _s2_vaddr_T = _T_30; // @[DCache.scala:345:29, :351:62]
wire _s1_meta_clk_en_T; // @[DCache.scala:357:44]
assign _s1_meta_clk_en_T = _T_30; // @[DCache.scala:345:29, :357:44]
wire _s2_hit_state_T; // @[DCache.scala:386:66]
assign _s2_hit_state_T = _T_30; // @[DCache.scala:345:29, :386:66]
wire _s2_victim_way_T; // @[DCache.scala:431:77]
assign _s2_victim_way_T = _T_30; // @[DCache.scala:345:29, :431:77]
reg [39:0] s2_vaddr_r; // @[DCache.scala:351:31]
wire [31:0] _s2_vaddr_T_1 = s2_vaddr_r[39:8]; // @[DCache.scala:351:{31,81}]
wire [7:0] _s2_vaddr_T_2 = s2_req_addr[7:0]; // @[DCache.scala:339:19, :351:103]
wire [39:0] s2_vaddr = {_s2_vaddr_T_1, _s2_vaddr_T_2}; // @[DCache.scala:351:{21,81,103}]
wire _s2_read_T = s2_req_cmd == 5'h0; // @[package.scala:16:47]
wire _s2_read_T_1 = s2_req_cmd == 5'h10; // @[package.scala:16:47]
wire _GEN_62 = s2_req_cmd == 5'h6; // @[package.scala:16:47]
wire _s2_read_T_2; // @[package.scala:16:47]
assign _s2_read_T_2 = _GEN_62; // @[package.scala:16:47]
wire _r_c_cat_T_48; // @[Consts.scala:91:71]
assign _r_c_cat_T_48 = _GEN_62; // @[package.scala:16:47]
wire _s2_lr_T; // @[DCache.scala:470:70]
assign _s2_lr_T = _GEN_62; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:71]
assign _metaArb_io_in_3_bits_data_c_cat_T_48 = _GEN_62; // @[package.scala:16:47]
wire _GEN_63 = s2_req_cmd == 5'h7; // @[package.scala:16:47]
wire _s2_read_T_3; // @[package.scala:16:47]
assign _s2_read_T_3 = _GEN_63; // @[package.scala:16:47]
wire _s2_write_T_3; // @[Consts.scala:90:66]
assign _s2_write_T_3 = _GEN_63; // @[package.scala:16:47]
wire _r_c_cat_T_3; // @[Consts.scala:90:66]
assign _r_c_cat_T_3 = _GEN_63; // @[package.scala:16:47]
wire _r_c_cat_T_26; // @[Consts.scala:90:66]
assign _r_c_cat_T_26 = _GEN_63; // @[package.scala:16:47]
wire _s2_sc_T; // @[DCache.scala:471:70]
assign _s2_sc_T = _GEN_63; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:66]
assign _metaArb_io_in_3_bits_data_c_cat_T_3 = _GEN_63; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:66]
assign _metaArb_io_in_3_bits_data_c_cat_T_26 = _GEN_63; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_3; // @[Consts.scala:90:66]
assign _io_cpu_store_pending_T_3 = _GEN_63; // @[package.scala:16:47]
wire _s2_read_T_4 = _s2_read_T | _s2_read_T_1; // @[package.scala:16:47, :81:59]
wire _s2_read_T_5 = _s2_read_T_4 | _s2_read_T_2; // @[package.scala:16:47, :81:59]
wire _s2_read_T_6 = _s2_read_T_5 | _s2_read_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_64 = s2_req_cmd == 5'h4; // @[package.scala:16:47]
wire _s2_read_T_7; // @[package.scala:16:47]
assign _s2_read_T_7 = _GEN_64; // @[package.scala:16:47]
wire _s2_write_T_5; // @[package.scala:16:47]
assign _s2_write_T_5 = _GEN_64; // @[package.scala:16:47]
wire _r_c_cat_T_5; // @[package.scala:16:47]
assign _r_c_cat_T_5 = _GEN_64; // @[package.scala:16:47]
wire _r_c_cat_T_28; // @[package.scala:16:47]
assign _r_c_cat_T_28 = _GEN_64; // @[package.scala:16:47]
wire _atomics_T; // @[DCache.scala:587:81]
assign _atomics_T = _GEN_64; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_5; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_5 = _GEN_64; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_28; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_28 = _GEN_64; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_5; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_5 = _GEN_64; // @[package.scala:16:47]
wire _GEN_65 = s2_req_cmd == 5'h9; // @[package.scala:16:47]
wire _s2_read_T_8; // @[package.scala:16:47]
assign _s2_read_T_8 = _GEN_65; // @[package.scala:16:47]
wire _s2_write_T_6; // @[package.scala:16:47]
assign _s2_write_T_6 = _GEN_65; // @[package.scala:16:47]
wire _r_c_cat_T_6; // @[package.scala:16:47]
assign _r_c_cat_T_6 = _GEN_65; // @[package.scala:16:47]
wire _r_c_cat_T_29; // @[package.scala:16:47]
assign _r_c_cat_T_29 = _GEN_65; // @[package.scala:16:47]
wire _atomics_T_2; // @[DCache.scala:587:81]
assign _atomics_T_2 = _GEN_65; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_6 = _GEN_65; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_29 = _GEN_65; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_6; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_6 = _GEN_65; // @[package.scala:16:47]
wire _GEN_66 = s2_req_cmd == 5'hA; // @[package.scala:16:47]
wire _s2_read_T_9; // @[package.scala:16:47]
assign _s2_read_T_9 = _GEN_66; // @[package.scala:16:47]
wire _s2_write_T_7; // @[package.scala:16:47]
assign _s2_write_T_7 = _GEN_66; // @[package.scala:16:47]
wire _r_c_cat_T_7; // @[package.scala:16:47]
assign _r_c_cat_T_7 = _GEN_66; // @[package.scala:16:47]
wire _r_c_cat_T_30; // @[package.scala:16:47]
assign _r_c_cat_T_30 = _GEN_66; // @[package.scala:16:47]
wire _atomics_T_4; // @[DCache.scala:587:81]
assign _atomics_T_4 = _GEN_66; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_7 = _GEN_66; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_30 = _GEN_66; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_7; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_7 = _GEN_66; // @[package.scala:16:47]
wire _GEN_67 = s2_req_cmd == 5'hB; // @[package.scala:16:47]
wire _s2_read_T_10; // @[package.scala:16:47]
assign _s2_read_T_10 = _GEN_67; // @[package.scala:16:47]
wire _s2_write_T_8; // @[package.scala:16:47]
assign _s2_write_T_8 = _GEN_67; // @[package.scala:16:47]
wire _r_c_cat_T_8; // @[package.scala:16:47]
assign _r_c_cat_T_8 = _GEN_67; // @[package.scala:16:47]
wire _r_c_cat_T_31; // @[package.scala:16:47]
assign _r_c_cat_T_31 = _GEN_67; // @[package.scala:16:47]
wire _atomics_T_6; // @[DCache.scala:587:81]
assign _atomics_T_6 = _GEN_67; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_8 = _GEN_67; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_31 = _GEN_67; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_8; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_8 = _GEN_67; // @[package.scala:16:47]
wire _s2_read_T_11 = _s2_read_T_7 | _s2_read_T_8; // @[package.scala:16:47, :81:59]
wire _s2_read_T_12 = _s2_read_T_11 | _s2_read_T_9; // @[package.scala:16:47, :81:59]
wire _s2_read_T_13 = _s2_read_T_12 | _s2_read_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_68 = s2_req_cmd == 5'h8; // @[package.scala:16:47]
wire _s2_read_T_14; // @[package.scala:16:47]
assign _s2_read_T_14 = _GEN_68; // @[package.scala:16:47]
wire _s2_write_T_12; // @[package.scala:16:47]
assign _s2_write_T_12 = _GEN_68; // @[package.scala:16:47]
wire _r_c_cat_T_12; // @[package.scala:16:47]
assign _r_c_cat_T_12 = _GEN_68; // @[package.scala:16:47]
wire _r_c_cat_T_35; // @[package.scala:16:47]
assign _r_c_cat_T_35 = _GEN_68; // @[package.scala:16:47]
wire _atomics_T_8; // @[DCache.scala:587:81]
assign _atomics_T_8 = _GEN_68; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_12; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_12 = _GEN_68; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_35; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_35 = _GEN_68; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_12; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_12 = _GEN_68; // @[package.scala:16:47]
wire _GEN_69 = s2_req_cmd == 5'hC; // @[package.scala:16:47]
wire _s2_read_T_15; // @[package.scala:16:47]
assign _s2_read_T_15 = _GEN_69; // @[package.scala:16:47]
wire _s2_write_T_13; // @[package.scala:16:47]
assign _s2_write_T_13 = _GEN_69; // @[package.scala:16:47]
wire _r_c_cat_T_13; // @[package.scala:16:47]
assign _r_c_cat_T_13 = _GEN_69; // @[package.scala:16:47]
wire _r_c_cat_T_36; // @[package.scala:16:47]
assign _r_c_cat_T_36 = _GEN_69; // @[package.scala:16:47]
wire _atomics_T_10; // @[DCache.scala:587:81]
assign _atomics_T_10 = _GEN_69; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_13 = _GEN_69; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_36 = _GEN_69; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_13; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_13 = _GEN_69; // @[package.scala:16:47]
wire _GEN_70 = s2_req_cmd == 5'hD; // @[package.scala:16:47]
wire _s2_read_T_16; // @[package.scala:16:47]
assign _s2_read_T_16 = _GEN_70; // @[package.scala:16:47]
wire _s2_write_T_14; // @[package.scala:16:47]
assign _s2_write_T_14 = _GEN_70; // @[package.scala:16:47]
wire _r_c_cat_T_14; // @[package.scala:16:47]
assign _r_c_cat_T_14 = _GEN_70; // @[package.scala:16:47]
wire _r_c_cat_T_37; // @[package.scala:16:47]
assign _r_c_cat_T_37 = _GEN_70; // @[package.scala:16:47]
wire _atomics_T_12; // @[DCache.scala:587:81]
assign _atomics_T_12 = _GEN_70; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_14 = _GEN_70; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_37 = _GEN_70; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_14; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_14 = _GEN_70; // @[package.scala:16:47]
wire _GEN_71 = s2_req_cmd == 5'hE; // @[package.scala:16:47]
wire _s2_read_T_17; // @[package.scala:16:47]
assign _s2_read_T_17 = _GEN_71; // @[package.scala:16:47]
wire _s2_write_T_15; // @[package.scala:16:47]
assign _s2_write_T_15 = _GEN_71; // @[package.scala:16:47]
wire _r_c_cat_T_15; // @[package.scala:16:47]
assign _r_c_cat_T_15 = _GEN_71; // @[package.scala:16:47]
wire _r_c_cat_T_38; // @[package.scala:16:47]
assign _r_c_cat_T_38 = _GEN_71; // @[package.scala:16:47]
wire _atomics_T_14; // @[DCache.scala:587:81]
assign _atomics_T_14 = _GEN_71; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_15 = _GEN_71; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_38 = _GEN_71; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_15; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_15 = _GEN_71; // @[package.scala:16:47]
wire _GEN_72 = s2_req_cmd == 5'hF; // @[package.scala:16:47]
wire _s2_read_T_18; // @[package.scala:16:47]
assign _s2_read_T_18 = _GEN_72; // @[package.scala:16:47]
wire _s2_write_T_16; // @[package.scala:16:47]
assign _s2_write_T_16 = _GEN_72; // @[package.scala:16:47]
wire _r_c_cat_T_16; // @[package.scala:16:47]
assign _r_c_cat_T_16 = _GEN_72; // @[package.scala:16:47]
wire _r_c_cat_T_39; // @[package.scala:16:47]
assign _r_c_cat_T_39 = _GEN_72; // @[package.scala:16:47]
wire _atomics_T_16; // @[DCache.scala:587:81]
assign _atomics_T_16 = _GEN_72; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_16 = _GEN_72; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_39 = _GEN_72; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_16; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_16 = _GEN_72; // @[package.scala:16:47]
wire _s2_read_T_19 = _s2_read_T_14 | _s2_read_T_15; // @[package.scala:16:47, :81:59]
wire _s2_read_T_20 = _s2_read_T_19 | _s2_read_T_16; // @[package.scala:16:47, :81:59]
wire _s2_read_T_21 = _s2_read_T_20 | _s2_read_T_17; // @[package.scala:16:47, :81:59]
wire _s2_read_T_22 = _s2_read_T_21 | _s2_read_T_18; // @[package.scala:16:47, :81:59]
wire _s2_read_T_23 = _s2_read_T_13 | _s2_read_T_22; // @[package.scala:81:59]
assign s2_read = _s2_read_T_6 | _s2_read_T_23; // @[package.scala:81:59]
assign io_cpu_resp_bits_has_data_0 = s2_read; // @[DCache.scala:101:7]
wire _GEN_73 = s2_req_cmd == 5'h1; // @[DCache.scala:339:19]
wire _s2_write_T; // @[Consts.scala:90:32]
assign _s2_write_T = _GEN_73; // @[Consts.scala:90:32]
wire _r_c_cat_T; // @[Consts.scala:90:32]
assign _r_c_cat_T = _GEN_73; // @[Consts.scala:90:32]
wire _r_c_cat_T_23; // @[Consts.scala:90:32]
assign _r_c_cat_T_23 = _GEN_73; // @[Consts.scala:90:32]
wire _metaArb_io_in_3_bits_data_c_cat_T; // @[Consts.scala:90:32]
assign _metaArb_io_in_3_bits_data_c_cat_T = _GEN_73; // @[Consts.scala:90:32]
wire _metaArb_io_in_3_bits_data_c_cat_T_23; // @[Consts.scala:90:32]
assign _metaArb_io_in_3_bits_data_c_cat_T_23 = _GEN_73; // @[Consts.scala:90:32]
wire _io_cpu_store_pending_T; // @[Consts.scala:90:32]
assign _io_cpu_store_pending_T = _GEN_73; // @[Consts.scala:90:32]
wire _GEN_74 = s2_req_cmd == 5'h11; // @[DCache.scala:339:19]
wire _s2_write_T_1; // @[Consts.scala:90:49]
assign _s2_write_T_1 = _GEN_74; // @[Consts.scala:90:49]
wire _r_c_cat_T_1; // @[Consts.scala:90:49]
assign _r_c_cat_T_1 = _GEN_74; // @[Consts.scala:90:49]
wire _r_c_cat_T_24; // @[Consts.scala:90:49]
assign _r_c_cat_T_24 = _GEN_74; // @[Consts.scala:90:49]
wire _tl_out_a_bits_T_4; // @[DCache.scala:610:20]
assign _tl_out_a_bits_T_4 = _GEN_74; // @[DCache.scala:610:20]
wire _uncachedReqs_0_cmd_T; // @[DCache.scala:637:49]
assign _uncachedReqs_0_cmd_T = _GEN_74; // @[DCache.scala:637:49]
wire _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:49]
assign _metaArb_io_in_3_bits_data_c_cat_T_1 = _GEN_74; // @[Consts.scala:90:49]
wire _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:49]
assign _metaArb_io_in_3_bits_data_c_cat_T_24 = _GEN_74; // @[Consts.scala:90:49]
wire _io_cpu_store_pending_T_1; // @[Consts.scala:90:49]
assign _io_cpu_store_pending_T_1 = _GEN_74; // @[Consts.scala:90:49]
wire _s2_write_T_2 = _s2_write_T | _s2_write_T_1; // @[Consts.scala:90:{32,42,49}]
wire _s2_write_T_4 = _s2_write_T_2 | _s2_write_T_3; // @[Consts.scala:90:{42,59,66}]
wire _s2_write_T_9 = _s2_write_T_5 | _s2_write_T_6; // @[package.scala:16:47, :81:59]
wire _s2_write_T_10 = _s2_write_T_9 | _s2_write_T_7; // @[package.scala:16:47, :81:59]
wire _s2_write_T_11 = _s2_write_T_10 | _s2_write_T_8; // @[package.scala:16:47, :81:59]
wire _s2_write_T_17 = _s2_write_T_12 | _s2_write_T_13; // @[package.scala:16:47, :81:59]
wire _s2_write_T_18 = _s2_write_T_17 | _s2_write_T_14; // @[package.scala:16:47, :81:59]
wire _s2_write_T_19 = _s2_write_T_18 | _s2_write_T_15; // @[package.scala:16:47, :81:59]
wire _s2_write_T_20 = _s2_write_T_19 | _s2_write_T_16; // @[package.scala:16:47, :81:59]
wire _s2_write_T_21 = _s2_write_T_11 | _s2_write_T_20; // @[package.scala:81:59]
wire s2_write = _s2_write_T_4 | _s2_write_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire s2_readwrite = s2_read | s2_write; // @[DCache.scala:354:30]
reg s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43]
wire s2_flush_valid = s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43, :363:51]
wire s1_meta_clk_en = _s1_meta_clk_en_T | s1_probe; // @[DCache.scala:183:25, :357:{44,62}]
reg [25:0] s2_meta_corrected_r; // @[DCache.scala:361:61]
wire [25:0] _s2_meta_corrected_WIRE = s2_meta_corrected_r; // @[DCache.scala:361:{61,99}]
wire [1:0] _s2_meta_corrected_T_1; // @[DCache.scala:361:99]
wire [23:0] _s2_meta_corrected_T; // @[DCache.scala:361:99]
wire [1:0] s2_meta_corrected_0_coh_state; // @[DCache.scala:361:99]
wire [23:0] s2_meta_corrected_0_tag; // @[DCache.scala:361:99]
assign _s2_meta_corrected_T = _s2_meta_corrected_WIRE[23:0]; // @[DCache.scala:361:99]
assign s2_meta_corrected_0_tag = _s2_meta_corrected_T; // @[DCache.scala:361:99]
assign _s2_meta_corrected_T_1 = _s2_meta_corrected_WIRE[25:24]; // @[DCache.scala:361:99]
assign s2_meta_corrected_0_coh_state = _s2_meta_corrected_T_1; // @[DCache.scala:361:99]
reg [25:0] s2_meta_corrected_r_1; // @[DCache.scala:361:61]
wire [25:0] _s2_meta_corrected_WIRE_1 = s2_meta_corrected_r_1; // @[DCache.scala:361:{61,99}]
wire [1:0] _s2_meta_corrected_T_3; // @[DCache.scala:361:99]
wire [23:0] _s2_meta_corrected_T_2; // @[DCache.scala:361:99]
wire [1:0] s2_meta_corrected_1_coh_state; // @[DCache.scala:361:99]
wire [23:0] s2_meta_corrected_1_tag; // @[DCache.scala:361:99]
assign _s2_meta_corrected_T_2 = _s2_meta_corrected_WIRE_1[23:0]; // @[DCache.scala:361:99]
assign s2_meta_corrected_1_tag = _s2_meta_corrected_T_2; // @[DCache.scala:361:99]
assign _s2_meta_corrected_T_3 = _s2_meta_corrected_WIRE_1[25:24]; // @[DCache.scala:361:99]
assign s2_meta_corrected_1_coh_state = _s2_meta_corrected_T_3; // @[DCache.scala:361:99]
reg [25:0] s2_meta_corrected_r_2; // @[DCache.scala:361:61]
wire [25:0] _s2_meta_corrected_WIRE_2 = s2_meta_corrected_r_2; // @[DCache.scala:361:{61,99}]
wire [1:0] _s2_meta_corrected_T_5; // @[DCache.scala:361:99]
wire [23:0] _s2_meta_corrected_T_4; // @[DCache.scala:361:99]
wire [1:0] s2_meta_corrected_2_coh_state; // @[DCache.scala:361:99]
wire [23:0] s2_meta_corrected_2_tag; // @[DCache.scala:361:99]
assign _s2_meta_corrected_T_4 = _s2_meta_corrected_WIRE_2[23:0]; // @[DCache.scala:361:99]
assign s2_meta_corrected_2_tag = _s2_meta_corrected_T_4; // @[DCache.scala:361:99]
assign _s2_meta_corrected_T_5 = _s2_meta_corrected_WIRE_2[25:24]; // @[DCache.scala:361:99]
assign s2_meta_corrected_2_coh_state = _s2_meta_corrected_T_5; // @[DCache.scala:361:99]
reg [25:0] s2_meta_corrected_r_3; // @[DCache.scala:361:61]
wire [25:0] _s2_meta_corrected_WIRE_3 = s2_meta_corrected_r_3; // @[DCache.scala:361:{61,99}]
wire [1:0] _s2_meta_corrected_T_7; // @[DCache.scala:361:99]
wire [23:0] _s2_meta_corrected_T_6; // @[DCache.scala:361:99]
wire [1:0] _s2_first_meta_corrected_T_4_coh_state = s2_meta_corrected_3_coh_state; // @[Mux.scala:50:70]
wire [23:0] _s2_first_meta_corrected_T_4_tag = s2_meta_corrected_3_tag; // @[Mux.scala:50:70]
assign _s2_meta_corrected_T_6 = _s2_meta_corrected_WIRE_3[23:0]; // @[DCache.scala:361:99]
assign s2_meta_corrected_3_tag = _s2_meta_corrected_T_6; // @[DCache.scala:361:99]
assign _s2_meta_corrected_T_7 = _s2_meta_corrected_WIRE_3[25:24]; // @[DCache.scala:361:99]
assign s2_meta_corrected_3_coh_state = _s2_meta_corrected_T_7; // @[DCache.scala:361:99]
wire _s2_data_en_T = s1_valid | inWriteback; // @[package.scala:81:59]
wire s2_data_en = _s2_data_en_T | io_cpu_replay_next_0; // @[DCache.scala:101:7, :366:{23,38}]
wire s2_data_word_en = inWriteback | _s2_data_word_en_T; // @[package.scala:81:59]
wire _s2_data_s1_word_en_T = ~io_cpu_replay_next_0; // @[DCache.scala:101:7, :377:28]
wire s2_data_s1_word_en = ~_s2_data_s1_word_en_T | s2_data_word_en; // @[DCache.scala:367:22, :377:{27,28}]
wire _s2_data_T = s2_data_s1_word_en; // @[DCache.scala:377:27, :379:39]
wire [4:0] _s2_data_T_1 = _s2_data_T ? s1_data_way : 5'h0; // @[DCache.scala:323:32, :379:{28,39}]
wire _s2_data_T_2 = _s2_data_T_1[0]; // @[Mux.scala:32:36]
wire _s2_data_T_3 = _s2_data_T_1[1]; // @[Mux.scala:32:36]
wire _s2_data_T_4 = _s2_data_T_1[2]; // @[Mux.scala:32:36]
wire _s2_data_T_5 = _s2_data_T_1[3]; // @[Mux.scala:32:36]
wire _s2_data_T_6 = _s2_data_T_1[4]; // @[Mux.scala:32:36]
wire [63:0] _s2_data_T_7 = _s2_data_T_2 ? s2_data_s1_way_words_0_0 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_T_8 = _s2_data_T_3 ? s2_data_s1_way_words_1_0 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_T_9 = _s2_data_T_4 ? s2_data_s1_way_words_2_0 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_T_10 = _s2_data_T_5 ? s2_data_s1_way_words_3_0 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_T_11 = _s2_data_T_6 ? s2_data_s1_way_words_4_0 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_T_12 = _s2_data_T_7 | _s2_data_T_8; // @[Mux.scala:30:73]
wire [63:0] _s2_data_T_13 = _s2_data_T_12 | _s2_data_T_9; // @[Mux.scala:30:73]
wire [63:0] _s2_data_T_14 = _s2_data_T_13 | _s2_data_T_10; // @[Mux.scala:30:73]
wire [63:0] _s2_data_T_15 = _s2_data_T_14 | _s2_data_T_11; // @[Mux.scala:30:73]
wire [63:0] _s2_data_WIRE = _s2_data_T_15; // @[Mux.scala:30:73]
reg [63:0] s2_data; // @[DCache.scala:379:18]
reg [3:0] s2_probe_way; // @[DCache.scala:383:31]
reg [1:0] s2_probe_state_state; // @[DCache.scala:384:33]
reg [3:0] s2_hit_way; // @[DCache.scala:385:29]
reg [1:0] s2_hit_state_state; // @[DCache.scala:386:31]
wire s2_hit_valid = |s2_hit_state_state; // @[Metadata.scala:50:45]
wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59]
wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59]
wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_75 = s2_req_cmd == 5'h3; // @[DCache.scala:339:19]
wire _r_c_cat_T_46; // @[Consts.scala:91:54]
assign _r_c_cat_T_46 = _GEN_75; // @[Consts.scala:91:54]
wire _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:91:54]
assign _metaArb_io_in_3_bits_data_c_cat_T_46 = _GEN_75; // @[Consts.scala:91:54]
wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r_T = {r_c, s2_hit_state_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_25 = _r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_27 = {1'h0, _r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r_T_28 = _r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_30 = _r_T_28 ? 2'h2 : _r_T_27; // @[Misc.scala:35:36, :49:20]
wire _r_T_31 = _r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_33 = _r_T_31 ? 2'h1 : _r_T_30; // @[Misc.scala:35:36, :49:20]
wire _r_T_34 = _r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_36 = _r_T_34 ? 2'h2 : _r_T_33; // @[Misc.scala:35:36, :49:20]
wire _r_T_37 = _r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_39 = _r_T_37 ? 2'h0 : _r_T_36; // @[Misc.scala:35:36, :49:20]
wire _r_T_40 = _r_T == 4'hE; // @[Misc.scala:49:20]
wire _r_T_41 = _r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_42 = _r_T_40 ? 2'h3 : _r_T_39; // @[Misc.scala:35:36, :49:20]
wire _r_T_43 = &_r_T; // @[Misc.scala:49:20]
wire _r_T_44 = _r_T_43 | _r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_45 = _r_T_43 ? 2'h3 : _r_T_42; // @[Misc.scala:35:36, :49:20]
wire _r_T_46 = _r_T == 4'h6; // @[Misc.scala:49:20]
wire _r_T_47 = _r_T_46 | _r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_48 = _r_T_46 ? 2'h2 : _r_T_45; // @[Misc.scala:35:36, :49:20]
wire _r_T_49 = _r_T == 4'h7; // @[Misc.scala:49:20]
wire _r_T_50 = _r_T_49 | _r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_51 = _r_T_49 ? 2'h3 : _r_T_48; // @[Misc.scala:35:36, :49:20]
wire _r_T_52 = _r_T == 4'h1; // @[Misc.scala:49:20]
wire _r_T_53 = _r_T_52 | _r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_54 = _r_T_52 ? 2'h1 : _r_T_51; // @[Misc.scala:35:36, :49:20]
wire _r_T_55 = _r_T == 4'h2; // @[Misc.scala:49:20]
wire _r_T_56 = _r_T_55 | _r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_57 = _r_T_55 ? 2'h2 : _r_T_54; // @[Misc.scala:35:36, :49:20]
wire _r_T_58 = _r_T == 4'h3; // @[Misc.scala:49:20]
wire s2_hit = _r_T_58 | _r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] s2_grow_param = _r_T_58 ? 2'h3 : _r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] s2_new_hit_state_state = s2_grow_param; // @[Misc.scala:35:36]
wire [1:0] metaArb_io_in_2_bits_data_meta_coh_state = s2_new_hit_state_state; // @[Metadata.scala:160:20]
wire [15:0] s2_data_corrected_lo_lo = s2_data[15:0]; // @[package.scala:45:27]
wire [15:0] s2_data_uncorrected_lo_lo = s2_data[15:0]; // @[package.scala:45:27]
wire [15:0] s2_data_corrected_lo_hi = s2_data[31:16]; // @[package.scala:45:27]
wire [15:0] s2_data_uncorrected_lo_hi = s2_data[31:16]; // @[package.scala:45:27]
wire [31:0] s2_data_corrected_lo = {s2_data_corrected_lo_hi, s2_data_corrected_lo_lo}; // @[package.scala:45:27]
wire [15:0] s2_data_corrected_hi_lo = s2_data[47:32]; // @[package.scala:45:27]
wire [15:0] s2_data_uncorrected_hi_lo = s2_data[47:32]; // @[package.scala:45:27]
wire [15:0] s2_data_corrected_hi_hi = s2_data[63:48]; // @[package.scala:45:27]
wire [15:0] s2_data_uncorrected_hi_hi = s2_data[63:48]; // @[package.scala:45:27]
wire [31:0] s2_data_corrected_hi = {s2_data_corrected_hi_hi, s2_data_corrected_hi_lo}; // @[package.scala:45:27]
assign s2_data_corrected = {s2_data_corrected_hi, s2_data_corrected_lo}; // @[package.scala:45:27]
assign nodeOut_c_bits_data = s2_data_corrected; // @[package.scala:45:27]
wire [63:0] s2_data_word_corrected = s2_data_corrected; // @[package.scala:45:27]
wire [31:0] s2_data_uncorrected_lo = {s2_data_uncorrected_lo_hi, s2_data_uncorrected_lo_lo}; // @[package.scala:45:27]
wire [31:0] s2_data_uncorrected_hi = {s2_data_uncorrected_hi_hi, s2_data_uncorrected_hi_lo}; // @[package.scala:45:27]
wire [63:0] s2_data_uncorrected = {s2_data_uncorrected_hi, s2_data_uncorrected_lo}; // @[package.scala:45:27]
assign s2_data_word = s2_data_uncorrected; // @[package.scala:45:27]
wire s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 & s2_hit; // @[Misc.scala:35:9]
wire _s2_valid_hit_pre_data_ecc_and_waw_T = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_readwrite; // @[DCache.scala:354:30, :397:89, :418:89]
wire s2_valid_hit_pre_data_ecc_and_waw = _s2_valid_hit_pre_data_ecc_and_waw_T; // @[DCache.scala:418:{89,105}]
wire s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw; // @[DCache.scala:418:105, :420:69]
wire s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_cmd_flush_line; // @[DCache.scala:341:54, :397:89, :419:75]
wire _s2_victim_tag_T = s2_valid_flush_line; // @[DCache.scala:419:75, :433:47]
wire s2_valid_hit = s2_valid_hit_pre_data_ecc; // @[DCache.scala:420:69, :422:48]
wire _s2_valid_miss_T = s2_valid_masked & s2_readwrite; // @[DCache.scala:337:42, :354:30, :423:39]
wire _s2_valid_miss_T_2 = _s2_valid_miss_T; // @[DCache.scala:423:{39,55}]
wire _s2_valid_miss_T_3 = ~s2_hit; // @[Misc.scala:35:9]
wire s2_valid_miss = _s2_valid_miss_T_2 & _s2_valid_miss_T_3; // @[DCache.scala:423:{55,73,76}]
wire _s2_uncached_T = ~s2_pma_cacheable; // @[DCache.scala:343:19, :424:21]
wire _s2_uncached_T_1 = ~s2_pma_must_alloc; // @[DCache.scala:343:19, :424:61]
wire _s2_uncached_T_2 = s2_req_no_alloc & _s2_uncached_T_1; // @[DCache.scala:339:19, :424:{58,61}]
wire _s2_uncached_T_3 = ~s2_hit_valid; // @[Metadata.scala:50:45]
wire _s2_uncached_T_4 = _s2_uncached_T_2 & _s2_uncached_T_3; // @[DCache.scala:424:{58,80,83}]
wire s2_uncached = _s2_uncached_T | _s2_uncached_T_4; // @[DCache.scala:424:{21,39,80}]
wire _s2_valid_cached_miss_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47]
wire _s2_valid_cached_miss_T_1 = s2_valid_miss & _s2_valid_cached_miss_T; // @[DCache.scala:423:73, :425:{44,47}]
wire _s2_valid_cached_miss_T_3 = ~_s2_valid_cached_miss_T_2; // @[DCache.scala:425:{63,88}]
wire s2_valid_cached_miss = _s2_valid_cached_miss_T_1 & _s2_valid_cached_miss_T_3; // @[DCache.scala:425:{44,60,63}]
wire _s2_want_victimize_T = s2_valid_cached_miss | s2_valid_flush_line; // @[DCache.scala:419:75, :425:60, :427:77]
wire _s2_want_victimize_T_1 = _s2_want_victimize_T; // @[DCache.scala:427:{77,100}]
wire _s2_want_victimize_T_2 = _s2_want_victimize_T_1 | s2_flush_valid; // @[DCache.scala:363:51, :427:{100,123}]
wire s2_want_victimize = _s2_want_victimize_T_2; // @[DCache.scala:427:{52,123}]
wire s2_victimize = s2_want_victimize; // @[DCache.scala:427:52, :429:40]
wire _s2_cannot_victimize_T = ~s2_flush_valid; // @[DCache.scala:363:51, :428:29]
wire _s2_valid_uncached_pending_T = s2_valid_miss & s2_uncached; // @[DCache.scala:423:73, :424:39, :430:49]
wire _s2_valid_uncached_pending_T_2 = ~_s2_valid_uncached_pending_T_1; // @[DCache.scala:430:{67,92}]
wire s2_valid_uncached_pending = _s2_valid_uncached_pending_T & _s2_valid_uncached_pending_T_2; // @[DCache.scala:430:{49,64,67}]
reg [1:0] s2_victim_way_r; // @[DCache.scala:431:41]
wire [3:0] s2_victim_way = 4'h1 << s2_victim_way_r; // @[OneHot.scala:58:35]
assign s2_victim_or_hit_way = s2_hit_valid ? s2_hit_way : s2_victim_way; // @[OneHot.scala:58:35]
assign metaArb_io_in_2_bits_way_en = s2_victim_or_hit_way; // @[DCache.scala:135:28, :432:33]
wire [23:0] _s2_victim_tag_T_1 = s2_req_addr[31:8]; // @[DCache.scala:339:19, :433:82]
wire _s2_victim_tag_T_2 = s2_victim_way[0]; // @[OneHot.scala:58:35]
wire _s2_victim_state_T = s2_victim_way[0]; // @[OneHot.scala:58:35]
wire _s2_victim_tag_T_3 = s2_victim_way[1]; // @[OneHot.scala:58:35]
wire _s2_victim_state_T_1 = s2_victim_way[1]; // @[OneHot.scala:58:35]
wire _s2_victim_tag_T_4 = s2_victim_way[2]; // @[OneHot.scala:58:35]
wire _s2_victim_state_T_2 = s2_victim_way[2]; // @[OneHot.scala:58:35]
wire _s2_victim_tag_T_5 = s2_victim_way[3]; // @[OneHot.scala:58:35]
wire _s2_victim_state_T_3 = s2_victim_way[3]; // @[OneHot.scala:58:35]
wire [1:0] _s2_victim_tag_WIRE_2_state; // @[Mux.scala:30:73]
wire [23:0] _s2_victim_tag_WIRE_1; // @[Mux.scala:30:73]
wire [23:0] _s2_victim_tag_T_6 = _s2_victim_tag_T_2 ? s2_meta_corrected_0_tag : 24'h0; // @[Mux.scala:30:73, :32:36]
wire [23:0] _s2_victim_tag_T_7 = _s2_victim_tag_T_3 ? s2_meta_corrected_1_tag : 24'h0; // @[Mux.scala:30:73, :32:36]
wire [23:0] _s2_victim_tag_T_8 = _s2_victim_tag_T_4 ? s2_meta_corrected_2_tag : 24'h0; // @[Mux.scala:30:73, :32:36]
wire [23:0] _s2_victim_tag_T_9 = _s2_victim_tag_T_5 ? s2_meta_corrected_3_tag : 24'h0; // @[Mux.scala:30:73, :32:36]
wire [23:0] _s2_victim_tag_T_10 = _s2_victim_tag_T_6 | _s2_victim_tag_T_7; // @[Mux.scala:30:73]
wire [23:0] _s2_victim_tag_T_11 = _s2_victim_tag_T_10 | _s2_victim_tag_T_8; // @[Mux.scala:30:73]
wire [23:0] _s2_victim_tag_T_12 = _s2_victim_tag_T_11 | _s2_victim_tag_T_9; // @[Mux.scala:30:73]
assign _s2_victim_tag_WIRE_1 = _s2_victim_tag_T_12; // @[Mux.scala:30:73]
wire [23:0] _s2_victim_tag_WIRE_tag = _s2_victim_tag_WIRE_1; // @[Mux.scala:30:73]
wire [1:0] _s2_victim_tag_WIRE_3; // @[Mux.scala:30:73]
wire [1:0] _s2_victim_tag_WIRE_coh_state = _s2_victim_tag_WIRE_2_state; // @[Mux.scala:30:73]
wire [1:0] _s2_victim_tag_T_13 = _s2_victim_tag_T_2 ? s2_meta_corrected_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_victim_tag_T_14 = _s2_victim_tag_T_3 ? s2_meta_corrected_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_victim_tag_T_15 = _s2_victim_tag_T_4 ? s2_meta_corrected_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_victim_tag_T_16 = _s2_victim_tag_T_5 ? s2_meta_corrected_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_victim_tag_T_17 = _s2_victim_tag_T_13 | _s2_victim_tag_T_14; // @[Mux.scala:30:73]
wire [1:0] _s2_victim_tag_T_18 = _s2_victim_tag_T_17 | _s2_victim_tag_T_15; // @[Mux.scala:30:73]
wire [1:0] _s2_victim_tag_T_19 = _s2_victim_tag_T_18 | _s2_victim_tag_T_16; // @[Mux.scala:30:73]
assign _s2_victim_tag_WIRE_3 = _s2_victim_tag_T_19; // @[Mux.scala:30:73]
assign _s2_victim_tag_WIRE_2_state = _s2_victim_tag_WIRE_3; // @[Mux.scala:30:73]
wire [23:0] s2_victim_tag = _s2_victim_tag_T ? _s2_victim_tag_T_1 : _s2_victim_tag_WIRE_tag; // @[Mux.scala:30:73]
wire [1:0] _s2_victim_state_WIRE_2_state; // @[Mux.scala:30:73]
wire [23:0] _s2_victim_state_WIRE_1; // @[Mux.scala:30:73]
wire [23:0] _s2_victim_state_T_4 = _s2_victim_state_T ? s2_meta_corrected_0_tag : 24'h0; // @[Mux.scala:30:73, :32:36]
wire [23:0] _s2_victim_state_T_5 = _s2_victim_state_T_1 ? s2_meta_corrected_1_tag : 24'h0; // @[Mux.scala:30:73, :32:36]
wire [23:0] _s2_victim_state_T_6 = _s2_victim_state_T_2 ? s2_meta_corrected_2_tag : 24'h0; // @[Mux.scala:30:73, :32:36]
wire [23:0] _s2_victim_state_T_7 = _s2_victim_state_T_3 ? s2_meta_corrected_3_tag : 24'h0; // @[Mux.scala:30:73, :32:36]
wire [23:0] _s2_victim_state_T_8 = _s2_victim_state_T_4 | _s2_victim_state_T_5; // @[Mux.scala:30:73]
wire [23:0] _s2_victim_state_T_9 = _s2_victim_state_T_8 | _s2_victim_state_T_6; // @[Mux.scala:30:73]
wire [23:0] _s2_victim_state_T_10 = _s2_victim_state_T_9 | _s2_victim_state_T_7; // @[Mux.scala:30:73]
assign _s2_victim_state_WIRE_1 = _s2_victim_state_T_10; // @[Mux.scala:30:73]
wire [23:0] _s2_victim_state_WIRE_tag = _s2_victim_state_WIRE_1; // @[Mux.scala:30:73]
wire [1:0] _s2_victim_state_WIRE_3; // @[Mux.scala:30:73]
wire [1:0] _s2_victim_state_WIRE_coh_state = _s2_victim_state_WIRE_2_state; // @[Mux.scala:30:73]
wire [1:0] _s2_victim_state_T_11 = _s2_victim_state_T ? s2_meta_corrected_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_victim_state_T_12 = _s2_victim_state_T_1 ? s2_meta_corrected_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_victim_state_T_13 = _s2_victim_state_T_2 ? s2_meta_corrected_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_victim_state_T_14 = _s2_victim_state_T_3 ? s2_meta_corrected_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _s2_victim_state_T_15 = _s2_victim_state_T_11 | _s2_victim_state_T_12; // @[Mux.scala:30:73]
wire [1:0] _s2_victim_state_T_16 = _s2_victim_state_T_15 | _s2_victim_state_T_13; // @[Mux.scala:30:73]
wire [1:0] _s2_victim_state_T_17 = _s2_victim_state_T_16 | _s2_victim_state_T_14; // @[Mux.scala:30:73]
assign _s2_victim_state_WIRE_3 = _s2_victim_state_T_17; // @[Mux.scala:30:73]
assign _s2_victim_state_WIRE_2_state = _s2_victim_state_WIRE_3; // @[Mux.scala:30:73]
wire [1:0] s2_victim_state_state = s2_hit_valid ? s2_hit_state_state : _s2_victim_state_WIRE_coh_state; // @[Mux.scala:30:73]
wire [3:0] _r_T_59 = {probe_bits_param, s2_probe_state_state}; // @[Metadata.scala:120:19]
wire _r_T_72 = _r_T_59 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_74 = _r_T_72 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_76 = _r_T_59 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_78 = _r_T_76 ? 3'h2 : _r_T_74; // @[Misc.scala:38:36, :56:20]
wire _r_T_80 = _r_T_59 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_82 = _r_T_80 ? 3'h1 : _r_T_78; // @[Misc.scala:38:36, :56:20]
wire _r_T_84 = _r_T_59 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_85 = _r_T_84; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_86 = _r_T_84 ? 3'h1 : _r_T_82; // @[Misc.scala:38:36, :56:20]
wire _r_T_88 = _r_T_59 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_89 = ~_r_T_88 & _r_T_85; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_90 = _r_T_88 ? 3'h5 : _r_T_86; // @[Misc.scala:38:36, :56:20]
wire _r_T_92 = _r_T_59 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_93 = ~_r_T_92 & _r_T_89; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_94 = _r_T_92 ? 3'h4 : _r_T_90; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_95 = {1'h0, _r_T_92}; // @[Misc.scala:38:63, :56:20]
wire _r_T_96 = _r_T_59 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_97 = ~_r_T_96 & _r_T_93; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_98 = _r_T_96 ? 3'h0 : _r_T_94; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_99 = _r_T_96 ? 2'h1 : _r_T_95; // @[Misc.scala:38:63, :56:20]
wire _r_T_100 = _r_T_59 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_101 = _r_T_100 | _r_T_97; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_102 = _r_T_100 ? 3'h0 : _r_T_98; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_103 = _r_T_100 ? 2'h1 : _r_T_99; // @[Misc.scala:38:63, :56:20]
wire _r_T_104 = _r_T_59 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_105 = ~_r_T_104 & _r_T_101; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_106 = _r_T_104 ? 3'h5 : _r_T_102; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_107 = _r_T_104 ? 2'h0 : _r_T_103; // @[Misc.scala:38:63, :56:20]
wire _r_T_108 = _r_T_59 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_109 = ~_r_T_108 & _r_T_105; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_110 = _r_T_108 ? 3'h4 : _r_T_106; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_111 = _r_T_108 ? 2'h1 : _r_T_107; // @[Misc.scala:38:63, :56:20]
wire _r_T_112 = _r_T_59 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_113 = ~_r_T_112 & _r_T_109; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_114 = _r_T_112 ? 3'h3 : _r_T_110; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_115 = _r_T_112 ? 2'h2 : _r_T_111; // @[Misc.scala:38:63, :56:20]
wire _r_T_116 = _r_T_59 == 4'h3; // @[Misc.scala:56:20]
wire s2_prb_ack_data = _r_T_116 | _r_T_113; // @[Misc.scala:38:9, :56:20]
wire [2:0] s2_report_param = _r_T_116 ? 3'h3 : _r_T_114; // @[Misc.scala:38:36, :56:20]
wire [2:0] cleanReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36]
wire [2:0] dirtyReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36]
wire [1:0] r_3 = _r_T_116 ? 2'h2 : _r_T_115; // @[Misc.scala:38:63, :56:20]
wire [1:0] probeNewCoh_state = r_3; // @[Misc.scala:38:63]
wire [3:0] _r_T_123 = {2'h2, s2_victim_state_state}; // @[Metadata.scala:120:19]
wire _r_T_136 = _r_T_123 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_138 = _r_T_136 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_140 = _r_T_123 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_142 = _r_T_140 ? 3'h2 : _r_T_138; // @[Misc.scala:38:36, :56:20]
wire _r_T_144 = _r_T_123 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_146 = _r_T_144 ? 3'h1 : _r_T_142; // @[Misc.scala:38:36, :56:20]
wire _r_T_148 = _r_T_123 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_149 = _r_T_148; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_150 = _r_T_148 ? 3'h1 : _r_T_146; // @[Misc.scala:38:36, :56:20]
wire _r_T_152 = _r_T_123 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_153 = ~_r_T_152 & _r_T_149; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_154 = _r_T_152 ? 3'h5 : _r_T_150; // @[Misc.scala:38:36, :56:20]
wire _r_T_156 = _r_T_123 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_157 = ~_r_T_156 & _r_T_153; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_158 = _r_T_156 ? 3'h4 : _r_T_154; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_159 = {1'h0, _r_T_156}; // @[Misc.scala:38:63, :56:20]
wire _r_T_160 = _r_T_123 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_161 = ~_r_T_160 & _r_T_157; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_162 = _r_T_160 ? 3'h0 : _r_T_158; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_163 = _r_T_160 ? 2'h1 : _r_T_159; // @[Misc.scala:38:63, :56:20]
wire _r_T_164 = _r_T_123 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_165 = _r_T_164 | _r_T_161; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_166 = _r_T_164 ? 3'h0 : _r_T_162; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_167 = _r_T_164 ? 2'h1 : _r_T_163; // @[Misc.scala:38:63, :56:20]
wire _r_T_168 = _r_T_123 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_169 = ~_r_T_168 & _r_T_165; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_170 = _r_T_168 ? 3'h5 : _r_T_166; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_171 = _r_T_168 ? 2'h0 : _r_T_167; // @[Misc.scala:38:63, :56:20]
wire _r_T_172 = _r_T_123 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_173 = ~_r_T_172 & _r_T_169; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_174 = _r_T_172 ? 3'h4 : _r_T_170; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_175 = _r_T_172 ? 2'h1 : _r_T_171; // @[Misc.scala:38:63, :56:20]
wire _r_T_176 = _r_T_123 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_177 = ~_r_T_176 & _r_T_173; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_178 = _r_T_176 ? 3'h3 : _r_T_174; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_179 = _r_T_176 ? 2'h2 : _r_T_175; // @[Misc.scala:38:63, :56:20]
wire _r_T_180 = _r_T_123 == 4'h3; // @[Misc.scala:56:20]
wire s2_victim_dirty = _r_T_180 | _r_T_177; // @[Misc.scala:38:9, :56:20]
wire [2:0] s2_shrink_param = _r_T_180 ? 3'h3 : _r_T_178; // @[Misc.scala:38:36, :56:20]
wire [2:0] nodeOut_c_bits_c_param = s2_shrink_param; // @[Misc.scala:38:36]
wire [2:0] nodeOut_c_bits_c_1_param = s2_shrink_param; // @[Misc.scala:38:36]
wire [1:0] r_3_1 = _r_T_180 ? 2'h2 : _r_T_179; // @[Misc.scala:38:63, :56:20]
wire [1:0] voluntaryNewCoh_state = r_3_1; // @[Misc.scala:38:63]
wire _s2_update_meta_T = s2_hit_state_state == s2_new_hit_state_state; // @[Metadata.scala:46:46, :160:20]
wire s2_update_meta = ~_s2_update_meta_T; // @[Metadata.scala:46:46, :47:40]
wire s2_dont_nack_uncached = s2_valid_uncached_pending & tl_out_a_ready; // @[DCache.scala:159:22, :430:64, :440:57]
wire _s2_dont_nack_misc_T_7 = ~s2_hit; // @[Misc.scala:35:9]
wire _s2_dont_nack_misc_T_10 = s2_req_cmd == 5'h17; // @[DCache.scala:339:19, :444:17]
wire _s2_dont_nack_misc_T_11 = _s2_dont_nack_misc_T_10; // @[DCache.scala:443:55, :444:17]
wire s2_dont_nack_misc = _s2_dont_nack_misc_T_1 & _s2_dont_nack_misc_T_11; // @[DCache.scala:441:{43,61}, :443:55]
wire _io_cpu_s2_nack_T = ~s2_dont_nack_uncached; // @[DCache.scala:440:57, :445:41]
wire _io_cpu_s2_nack_T_1 = s2_valid_no_xcpt & _io_cpu_s2_nack_T; // @[DCache.scala:332:35, :445:{38,41}]
wire _io_cpu_s2_nack_T_2 = ~s2_dont_nack_misc; // @[DCache.scala:441:61, :445:67]
wire _io_cpu_s2_nack_T_3 = _io_cpu_s2_nack_T_1 & _io_cpu_s2_nack_T_2; // @[DCache.scala:445:{38,64,67}]
wire _io_cpu_s2_nack_T_4 = ~s2_valid_hit; // @[DCache.scala:422:48, :445:89]
assign _io_cpu_s2_nack_T_5 = _io_cpu_s2_nack_T_3 & _io_cpu_s2_nack_T_4; // @[DCache.scala:445:{64,86,89}]
assign io_cpu_s2_nack_0 = _io_cpu_s2_nack_T_5; // @[DCache.scala:101:7, :445:86]
assign _metaArb_io_in_2_valid_T = s2_valid_hit_pre_data_ecc_and_waw & s2_update_meta; // @[Metadata.scala:47:40]
wire _T_40 = io_cpu_s2_nack_0 | _metaArb_io_in_2_valid_T; // @[DCache.scala:101:7, :446:24, :462:63]
wire [1:0] _s2_first_meta_corrected_T_5_coh_state = _s2_first_meta_corrected_T_4_coh_state; // @[Mux.scala:50:70]
wire [23:0] _s2_first_meta_corrected_T_5_tag = _s2_first_meta_corrected_T_4_tag; // @[Mux.scala:50:70]
wire [1:0] s2_first_meta_corrected_coh_state = _s2_first_meta_corrected_T_5_coh_state; // @[Mux.scala:50:70]
wire [23:0] s2_first_meta_corrected_tag = _s2_first_meta_corrected_T_5_tag; // @[Mux.scala:50:70]
wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_state = s2_first_meta_corrected_coh_state; // @[Mux.scala:50:70]
wire [23:0] metaArb_io_in_1_bits_data_new_meta_tag = s2_first_meta_corrected_tag; // @[Mux.scala:50:70]
wire _metaArb_io_in_1_valid_T = s2_valid_masked | s2_flush_valid_pre_tag_ecc; // @[DCache.scala:337:42, :355:43, :450:63]
wire _metaArb_io_in_1_valid_T_1 = _metaArb_io_in_1_valid_T | s2_probe; // @[DCache.scala:333:25, :450:{63,93}]
wire [1:0] _metaArb_io_in_1_bits_idx_T = probe_bits_address[7:6]; // @[DCache.scala:184:29, :1200:47]
wire [1:0] _metaArb_io_in_6_bits_idx_T_1 = probe_bits_address[7:6]; // @[DCache.scala:184:29, :1200:47]
wire [1:0] _dataArb_io_in_2_bits_addr_T = probe_bits_address[7:6]; // @[DCache.scala:184:29, :1200:47]
assign _metaArb_io_in_4_bits_idx_T = probe_bits_address[7:6]; // @[DCache.scala:184:29, :1200:47]
wire [1:0] _metaArb_io_in_1_bits_idx_T_1 = s2_vaddr[7:6]; // @[DCache.scala:351:21, :453:76]
assign _metaArb_io_in_2_bits_idx_T = s2_vaddr[7:6]; // @[DCache.scala:351:21, :453:76, :465:40]
assign _metaArb_io_in_3_bits_idx_T = s2_vaddr[7:6]; // @[DCache.scala:351:21, :453:76, :744:40]
assign _metaArb_io_in_1_bits_idx_T_2 = s2_probe ? _metaArb_io_in_1_bits_idx_T : _metaArb_io_in_1_bits_idx_T_1; // @[DCache.scala:333:25, :453:{35,76}, :1200:47]
assign metaArb_io_in_1_bits_idx = _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:135:28, :453:35]
wire [7:0] _metaArb_io_in_1_bits_addr_T_1 = {_metaArb_io_in_1_bits_idx_T_2, 6'h0}; // @[DCache.scala:453:35, :454:98]
assign _metaArb_io_in_1_bits_addr_T_2 = {_metaArb_io_in_1_bits_addr_T, _metaArb_io_in_1_bits_addr_T_1}; // @[DCache.scala:454:{36,58,98}]
assign metaArb_io_in_1_bits_addr = _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:135:28, :454:36]
assign _metaArb_io_in_1_bits_data_T = {metaArb_io_in_1_bits_data_new_meta_coh_state, metaArb_io_in_1_bits_data_new_meta_tag}; // @[DCache.scala:456:31, :458:14]
assign metaArb_io_in_1_bits_data = _metaArb_io_in_1_bits_data_T; // @[DCache.scala:135:28, :458:14]
assign metaArb_io_in_2_valid = _metaArb_io_in_2_valid_T; // @[DCache.scala:135:28, :462:63]
assign metaArb_io_in_2_bits_idx = _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:135:28, :465:40]
wire [7:0] _metaArb_io_in_2_bits_addr_T_1 = s2_vaddr[7:0]; // @[DCache.scala:351:21, :466:80]
wire [7:0] _metaArb_io_in_3_bits_addr_T_1 = s2_vaddr[7:0]; // @[DCache.scala:351:21, :466:80, :745:80]
assign _metaArb_io_in_2_bits_addr_T_2 = {_metaArb_io_in_2_bits_addr_T, _metaArb_io_in_2_bits_addr_T_1}; // @[DCache.scala:466:{36,58,80}]
assign metaArb_io_in_2_bits_addr = _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:135:28, :466:36]
wire [31:0] _metaArb_io_in_2_bits_data_T = s2_req_addr[39:8]; // @[DCache.scala:339:19, :467:68]
wire [31:0] _metaArb_io_in_3_bits_data_T = s2_req_addr[39:8]; // @[DCache.scala:339:19, :467:68, :746:68]
wire [23:0] metaArb_io_in_2_bits_data_meta_tag; // @[HellaCache.scala:305:20]
assign metaArb_io_in_2_bits_data_meta_tag = _metaArb_io_in_2_bits_data_T[23:0]; // @[HellaCache.scala:305:20, :306:14]
assign _metaArb_io_in_2_bits_data_T_1 = {metaArb_io_in_2_bits_data_meta_coh_state, metaArb_io_in_2_bits_data_meta_tag}; // @[HellaCache.scala:305:20]
assign metaArb_io_in_2_bits_data = _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:135:28, :467:97]
reg [4:0] lrscCount; // @[DCache.scala:472:26]
wire lrscValid = |(lrscCount[4:2]); // @[DCache.scala:472:26, :473:29]
wire _lrscBackingOff_T = |lrscCount; // @[DCache.scala:472:26, :474:34]
wire _lrscBackingOff_T_1 = ~lrscValid; // @[DCache.scala:473:29, :474:43]
wire lrscBackingOff = _lrscBackingOff_T & _lrscBackingOff_T_1; // @[DCache.scala:474:{34,40,43}]
reg [33:0] lrscAddr; // @[DCache.scala:475:21]
wire [33:0] _lrscAddrMatch_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49]
wire [33:0] _lrscAddr_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :480:29]
wire [33:0] _acquire_address_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :578:38]
wire [33:0] _tl_out_a_bits_T_1 = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :1210:39]
wire [33:0] _io_errors_bus_bits_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :1130:58]
wire lrscAddrMatch = lrscAddr == _lrscAddrMatch_T; // @[DCache.scala:475:21, :476:{32,49}]
wire _s2_sc_fail_T = lrscValid & lrscAddrMatch; // @[DCache.scala:473:29, :476:32, :477:41]
wire _s2_sc_fail_T_1 = ~_s2_sc_fail_T; // @[DCache.scala:477:{29,41}]
wire [4:0] _lrscCount_T = s2_hit ? 5'h13 : 5'h0; // @[Misc.scala:35:9]
wire [5:0] _lrscCount_T_1 = {1'h0, lrscCount} - 6'h1; // @[DCache.scala:472:26, :482:51]
wire [4:0] _lrscCount_T_2 = _lrscCount_T_1[4:0]; // @[DCache.scala:482:51]
wire _s2_correct_T = ~any_pstore_valid; // @[DCache.scala:230:30, :487:37]
wire _s2_correct_T_2 = any_pstore_valid | s2_valid; // @[DCache.scala:230:30, :331:25, :487:84]
reg s2_correct_REG; // @[DCache.scala:487:66]
wire _s2_correct_T_3 = ~s2_correct_REG; // @[DCache.scala:487:{58,66}]
wire _GEN_76 = s1_valid_not_nacked & s1_write; // @[DCache.scala:187:38, :492:63]
wire _pstore1_cmd_T; // @[DCache.scala:492:63]
assign _pstore1_cmd_T = _GEN_76; // @[DCache.scala:492:63]
wire _pstore1_addr_T; // @[DCache.scala:493:62]
assign _pstore1_addr_T = _GEN_76; // @[DCache.scala:492:63, :493:62]
wire _pstore1_data_T; // @[DCache.scala:494:73]
assign _pstore1_data_T = _GEN_76; // @[DCache.scala:492:63, :494:73]
wire _pstore1_way_T; // @[DCache.scala:495:63]
assign _pstore1_way_T = _GEN_76; // @[DCache.scala:492:63, :495:63]
wire _pstore1_mask_T; // @[DCache.scala:496:61]
assign _pstore1_mask_T = _GEN_76; // @[DCache.scala:492:63, :496:61]
wire _pstore1_rmw_T_53; // @[DCache.scala:498:84]
assign _pstore1_rmw_T_53 = _GEN_76; // @[DCache.scala:492:63, :498:84]
reg [4:0] pstore1_cmd; // @[DCache.scala:492:30]
reg [39:0] pstore1_addr; // @[DCache.scala:493:31]
wire [39:0] _pstore2_addr_T = pstore1_addr; // @[DCache.scala:493:31, :524:35]
reg [63:0] pstore1_data; // @[DCache.scala:494:31]
assign io_cpu_resp_bits_store_data_0 = pstore1_data; // @[DCache.scala:101:7, :494:31]
wire [63:0] pstore1_storegen_data = pstore1_data; // @[DCache.scala:494:31, :497:42]
wire [63:0] put_data = pstore1_data; // @[Edges.scala:480:17]
wire [63:0] putpartial_data = pstore1_data; // @[Edges.scala:500:17]
wire [63:0] atomics_a_data = pstore1_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_1_data = pstore1_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_2_data = pstore1_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_3_data = pstore1_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_4_data = pstore1_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_5_data = pstore1_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_6_data = pstore1_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_7_data = pstore1_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_8_data = pstore1_data; // @[Edges.scala:517:17]
reg [3:0] pstore1_way; // @[DCache.scala:495:30]
wire [3:0] _pstore2_way_T = pstore1_way; // @[DCache.scala:495:30, :525:34]
reg [7:0] pstore1_mask; // @[DCache.scala:496:31]
wire [7:0] pstore2_storegen_mask_mergedMask = pstore1_mask; // @[DCache.scala:496:31, :533:37]
wire _pstore1_rmw_T_4 = _pstore1_rmw_T | _pstore1_rmw_T_1; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_5 = _pstore1_rmw_T_4 | _pstore1_rmw_T_2; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_6 = _pstore1_rmw_T_5 | _pstore1_rmw_T_3; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_11 = _pstore1_rmw_T_7 | _pstore1_rmw_T_8; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_12 = _pstore1_rmw_T_11 | _pstore1_rmw_T_9; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_13 = _pstore1_rmw_T_12 | _pstore1_rmw_T_10; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_19 = _pstore1_rmw_T_14 | _pstore1_rmw_T_15; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_20 = _pstore1_rmw_T_19 | _pstore1_rmw_T_16; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_21 = _pstore1_rmw_T_20 | _pstore1_rmw_T_17; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_22 = _pstore1_rmw_T_21 | _pstore1_rmw_T_18; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_23 = _pstore1_rmw_T_13 | _pstore1_rmw_T_22; // @[package.scala:81:59]
wire _pstore1_rmw_T_24 = _pstore1_rmw_T_6 | _pstore1_rmw_T_23; // @[package.scala:81:59]
wire _pstore1_rmw_T_27 = _pstore1_rmw_T_25 | _pstore1_rmw_T_26; // @[Consts.scala:90:{32,42,49}]
wire _pstore1_rmw_T_29 = _pstore1_rmw_T_27 | _pstore1_rmw_T_28; // @[Consts.scala:90:{42,59,66}]
wire _pstore1_rmw_T_34 = _pstore1_rmw_T_30 | _pstore1_rmw_T_31; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_35 = _pstore1_rmw_T_34 | _pstore1_rmw_T_32; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_36 = _pstore1_rmw_T_35 | _pstore1_rmw_T_33; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_42 = _pstore1_rmw_T_37 | _pstore1_rmw_T_38; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_43 = _pstore1_rmw_T_42 | _pstore1_rmw_T_39; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_44 = _pstore1_rmw_T_43 | _pstore1_rmw_T_40; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_45 = _pstore1_rmw_T_44 | _pstore1_rmw_T_41; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_46 = _pstore1_rmw_T_36 | _pstore1_rmw_T_45; // @[package.scala:81:59]
wire _pstore1_rmw_T_47 = _pstore1_rmw_T_29 | _pstore1_rmw_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _pstore1_rmw_T_50 = _pstore1_rmw_T_48; // @[DCache.scala:1191:{35,45}]
wire _pstore1_rmw_T_51 = _pstore1_rmw_T_47 & _pstore1_rmw_T_50; // @[DCache.scala:1191:{23,45}]
wire _pstore1_rmw_T_52 = _pstore1_rmw_T_24 | _pstore1_rmw_T_51; // @[DCache.scala:1190:21, :1191:23]
reg pstore1_rmw_r; // @[DCache.scala:498:44]
wire _pstore1_merge_likely_T = s2_valid_not_nacked_in_s1 & s2_write; // @[DCache.scala:336:44, :499:56]
wire _GEN_77 = s2_valid_hit & s2_write; // @[DCache.scala:422:48, :490:46]
wire _pstore1_merge_T; // @[DCache.scala:490:46]
assign _pstore1_merge_T = _GEN_77; // @[DCache.scala:490:46]
wire _pstore1_valid_T; // @[DCache.scala:490:46]
assign _pstore1_valid_T = _GEN_77; // @[DCache.scala:490:46]
wire _pstore1_held_T; // @[DCache.scala:490:46]
assign _pstore1_held_T = _GEN_77; // @[DCache.scala:490:46]
wire _pstore1_merge_T_2 = _pstore1_merge_T; // @[DCache.scala:490:{46,58}]
wire _pstore1_merge_T_4 = _pstore1_merge_T_2; // @[DCache.scala:490:58, :491:48]
reg pstore2_valid; // @[DCache.scala:501:30]
wire _pstore_drain_opportunistic_T_56 = ~_pstore_drain_opportunistic_T_55; // @[DCache.scala:1186:11]
wire _pstore_drain_opportunistic_T_59 = ~_pstore_drain_opportunistic_T_58; // @[DCache.scala:502:{36,55}]
wire pstore_drain_opportunistic = _pstore_drain_opportunistic_T_59; // @[DCache.scala:502:{36,92}]
reg pstore_drain_on_miss_REG; // @[DCache.scala:503:56]
wire pstore_drain_on_miss = releaseInFlight | pstore_drain_on_miss_REG; // @[DCache.scala:334:46, :503:{46,56}]
reg pstore1_held; // @[DCache.scala:504:29]
wire _GEN_78 = s2_valid & s2_write; // @[DCache.scala:331:25, :505:39]
wire _pstore1_valid_likely_T; // @[DCache.scala:505:39]
assign _pstore1_valid_likely_T = _GEN_78; // @[DCache.scala:505:39]
wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_1; // @[DCache.scala:1082:16]
assign _io_cpu_perf_storeBufferEmptyAfterLoad_T_1 = _GEN_78; // @[DCache.scala:505:39, :1082:16]
wire _io_cpu_perf_storeBufferEmptyAfterStore_T_1; // @[DCache.scala:1086:15]
assign _io_cpu_perf_storeBufferEmptyAfterStore_T_1 = _GEN_78; // @[DCache.scala:505:39, :1086:15]
wire _io_cpu_perf_storeBufferEmptyAfterStore_T_4; // @[DCache.scala:1087:16]
assign _io_cpu_perf_storeBufferEmptyAfterStore_T_4 = _GEN_78; // @[DCache.scala:505:39, :1087:16]
wire _io_cpu_perf_canAcceptStoreThenLoad_T; // @[DCache.scala:1089:16]
assign _io_cpu_perf_canAcceptStoreThenLoad_T = _GEN_78; // @[DCache.scala:505:39, :1089:16]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_55; // @[DCache.scala:1092:100]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_55 = _GEN_78; // @[DCache.scala:505:39, :1092:100]
wire pstore1_valid_likely = _pstore1_valid_likely_T | pstore1_held; // @[DCache.scala:504:29, :505:{39,51}]
wire _pstore1_valid_T_2 = _pstore1_valid_T; // @[DCache.scala:490:{46,58}]
wire _pstore1_valid_T_4 = _pstore1_valid_T_2; // @[DCache.scala:490:58, :491:48]
wire pstore1_valid = _pstore1_valid_T_4 | pstore1_held; // @[DCache.scala:491:48, :504:29, :507:38]
wire _advance_pstore1_T = pstore1_valid; // @[DCache.scala:507:38, :522:40]
assign _any_pstore_valid_T = pstore1_held | pstore2_valid; // @[DCache.scala:501:30, :504:29, :508:36]
assign any_pstore_valid = _any_pstore_valid_T; // @[DCache.scala:230:30, :508:36]
wire _GEN_79 = pstore1_valid_likely & pstore2_valid; // @[DCache.scala:501:30, :505:51, :509:54]
wire _pstore_drain_structural_T; // @[DCache.scala:509:54]
assign _pstore_drain_structural_T = _GEN_79; // @[DCache.scala:509:54]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_6; // @[DCache.scala:1090:20]
assign _io_cpu_perf_canAcceptStoreThenLoad_T_6 = _GEN_79; // @[DCache.scala:509:54, :1090:20]
wire _GEN_80 = s1_valid & s1_write; // @[DCache.scala:182:25, :509:85]
wire _pstore_drain_structural_T_1; // @[DCache.scala:509:85]
assign _pstore_drain_structural_T_1 = _GEN_80; // @[DCache.scala:509:85]
wire _io_cpu_perf_storeBufferEmptyAfterLoad_T; // @[DCache.scala:1081:15]
assign _io_cpu_perf_storeBufferEmptyAfterLoad_T = _GEN_80; // @[DCache.scala:509:85, :1081:15]
wire _io_cpu_perf_storeBufferEmptyAfterStore_T; // @[DCache.scala:1085:15]
assign _io_cpu_perf_storeBufferEmptyAfterStore_T = _GEN_80; // @[DCache.scala:509:85, :1085:15]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_2; // @[DCache.scala:1089:57]
assign _io_cpu_perf_canAcceptStoreThenLoad_T_2 = _GEN_80; // @[DCache.scala:509:85, :1089:57]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_7; // @[DCache.scala:1090:57]
assign _io_cpu_perf_canAcceptStoreThenLoad_T_7 = _GEN_80; // @[DCache.scala:509:85, :1090:57]
wire _io_cpu_perf_canAcceptLoadThenLoad_T; // @[DCache.scala:1092:52]
assign _io_cpu_perf_canAcceptLoadThenLoad_T = _GEN_80; // @[DCache.scala:509:85, :1092:52]
wire _pstore_drain_structural_T_2 = _pstore_drain_structural_T_1; // @[DCache.scala:509:{85,98}]
wire pstore_drain_structural = _pstore_drain_structural_T & _pstore_drain_structural_T_2; // @[DCache.scala:509:{54,71,98}]
wire _T_49 = s2_valid_hit_pre_data_ecc & s2_write; // @[DCache.scala:420:69, :506:72]
wire _pstore_drain_T_2; // @[DCache.scala:506:72]
assign _pstore_drain_T_2 = _T_49; // @[DCache.scala:506:72]
wire _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:72]
assign _dataArb_io_in_0_valid_T_2 = _T_49; // @[DCache.scala:506:72]
wire _pstore_drain_T_4 = _pstore_drain_T_2; // @[DCache.scala:506:{72,84}]
wire _pstore_drain_T_5 = _pstore_drain_T_4 | pstore1_held; // @[DCache.scala:504:29, :506:{84,96}]
wire _pstore_drain_T_7 = _pstore_drain_T_5; // @[DCache.scala:506:96, :518:41]
wire _pstore_drain_T_8 = _pstore_drain_T_7 | pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}]
wire _GEN_81 = pstore_drain_opportunistic | pstore_drain_on_miss; // @[DCache.scala:502:92, :503:46, :518:107]
wire _pstore_drain_T_9; // @[DCache.scala:518:107]
assign _pstore_drain_T_9 = _GEN_81; // @[DCache.scala:518:107]
wire _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:107]
assign _dataArb_io_in_0_valid_T_9 = _GEN_81; // @[DCache.scala:518:107]
wire _pstore_drain_T_10 = _pstore_drain_T_8 & _pstore_drain_T_9; // @[DCache.scala:518:{58,76,107}]
wire _pstore_drain_T_11 = _pstore_drain_T_10; // @[DCache.scala:517:44, :518:76]
assign pstore_drain = _pstore_drain_T_11; // @[DCache.scala:516:27, :517:44]
assign dataArb_io_in_0_bits_write = pstore_drain; // @[DCache.scala:152:28, :516:27]
wire _pstore1_held_T_2 = _pstore1_held_T; // @[DCache.scala:490:{46,58}]
wire _pstore1_held_T_4 = _pstore1_held_T_2; // @[DCache.scala:490:58, :491:48]
wire _pstore1_held_T_6 = _pstore1_held_T_4; // @[DCache.scala:491:48, :521:35]
wire _pstore1_held_T_7 = _pstore1_held_T_6 | pstore1_held; // @[DCache.scala:504:29, :521:{35,54}]
wire _pstore1_held_T_8 = _pstore1_held_T_7 & pstore2_valid; // @[DCache.scala:501:30, :521:{54,71}]
wire _pstore1_held_T_9 = ~pstore_drain; // @[DCache.scala:516:27, :521:91]
wire _pstore1_held_T_10 = _pstore1_held_T_8 & _pstore1_held_T_9; // @[DCache.scala:521:{71,88,91}]
wire _advance_pstore1_T_1 = pstore2_valid == pstore_drain; // @[DCache.scala:501:30, :516:27, :522:79]
wire advance_pstore1 = _advance_pstore1_T & _advance_pstore1_T_1; // @[DCache.scala:522:{40,61,79}]
wire _pstore2_storegen_data_T_3 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_7 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_11 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_15 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_19 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_23 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_27 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_31 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_mask_T = advance_pstore1; // @[DCache.scala:522:61, :532:27]
wire _pstore2_valid_T = ~pstore_drain; // @[DCache.scala:516:27, :521:91, :523:37]
wire _pstore2_valid_T_1 = pstore2_valid & _pstore2_valid_T; // @[DCache.scala:501:30, :523:{34,37}]
wire _pstore2_valid_T_2 = _pstore2_valid_T_1 | advance_pstore1; // @[DCache.scala:522:61, :523:{34,51}]
reg [39:0] pstore2_addr; // @[DCache.scala:524:31]
reg [3:0] pstore2_way; // @[DCache.scala:525:30]
wire [7:0] _pstore2_storegen_data_T = pstore1_storegen_data[7:0]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_1 = pstore1_mask[0]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_3 = pstore1_mask[0]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_4 = pstore1_storegen_data[15:8]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_5 = pstore1_mask[1]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_4 = pstore1_mask[1]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_1; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_8 = pstore1_storegen_data[23:16]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_9 = pstore1_mask[2]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_5 = pstore1_mask[2]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_2; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_12 = pstore1_storegen_data[31:24]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_13 = pstore1_mask[3]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_6 = pstore1_mask[3]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_3; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_16 = pstore1_storegen_data[39:32]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_17 = pstore1_mask[4]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_7 = pstore1_mask[4]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_4; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_20 = pstore1_storegen_data[47:40]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_21 = pstore1_mask[5]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_8 = pstore1_mask[5]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_5; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_24 = pstore1_storegen_data[55:48]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_25 = pstore1_mask[6]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_9 = pstore1_mask[6]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_6; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_28 = pstore1_storegen_data[63:56]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_29 = pstore1_mask[7]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_10 = pstore1_mask[7]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_7; // @[DCache.scala:528:22]
wire [15:0] pstore2_storegen_data_lo_lo = {pstore2_storegen_data_r_1, pstore2_storegen_data_r}; // @[package.scala:45:27]
wire [15:0] pstore2_storegen_data_lo_hi = {pstore2_storegen_data_r_3, pstore2_storegen_data_r_2}; // @[package.scala:45:27]
wire [31:0] pstore2_storegen_data_lo = {pstore2_storegen_data_lo_hi, pstore2_storegen_data_lo_lo}; // @[package.scala:45:27]
wire [15:0] pstore2_storegen_data_hi_lo = {pstore2_storegen_data_r_5, pstore2_storegen_data_r_4}; // @[package.scala:45:27]
wire [15:0] pstore2_storegen_data_hi_hi = {pstore2_storegen_data_r_7, pstore2_storegen_data_r_6}; // @[package.scala:45:27]
wire [31:0] pstore2_storegen_data_hi = {pstore2_storegen_data_hi_hi, pstore2_storegen_data_hi_lo}; // @[package.scala:45:27]
wire [63:0] pstore2_storegen_data = {pstore2_storegen_data_hi, pstore2_storegen_data_lo}; // @[package.scala:45:27]
reg [7:0] pstore2_storegen_mask; // @[DCache.scala:531:19]
wire [7:0] _pstore2_storegen_mask_mask_T = ~pstore2_storegen_mask_mergedMask; // @[DCache.scala:533:37, :534:37]
wire [7:0] _pstore2_storegen_mask_mask_T_1 = _pstore2_storegen_mask_mask_T; // @[DCache.scala:534:{19,37}]
wire [7:0] _pstore2_storegen_mask_mask_T_2 = ~_pstore2_storegen_mask_mask_T_1; // @[DCache.scala:534:{15,19}]
wire _dataArb_io_in_0_valid_T_4 = _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:{72,84}]
wire _dataArb_io_in_0_valid_T_5 = _dataArb_io_in_0_valid_T_4 | pstore1_held; // @[DCache.scala:504:29, :506:{84,96}]
wire _dataArb_io_in_0_valid_T_7 = _dataArb_io_in_0_valid_T_5; // @[DCache.scala:506:96, :518:41]
wire _dataArb_io_in_0_valid_T_8 = _dataArb_io_in_0_valid_T_7 | pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}]
wire _dataArb_io_in_0_valid_T_10 = _dataArb_io_in_0_valid_T_8 & _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:{58,76,107}]
wire _dataArb_io_in_0_valid_T_11 = _dataArb_io_in_0_valid_T_10; // @[DCache.scala:517:44, :518:76]
assign _dataArb_io_in_0_valid_T_12 = _dataArb_io_in_0_valid_T_11; // @[DCache.scala:516:27, :517:44]
assign dataArb_io_in_0_valid = _dataArb_io_in_0_valid_T_12; // @[DCache.scala:152:28, :516:27]
wire [39:0] _GEN_82 = pstore2_valid ? pstore2_addr : pstore1_addr; // @[DCache.scala:493:31, :501:30, :524:31, :549:36]
wire [39:0] _dataArb_io_in_0_bits_addr_T; // @[DCache.scala:549:36]
assign _dataArb_io_in_0_bits_addr_T = _GEN_82; // @[DCache.scala:549:36]
wire [39:0] _dataArb_io_in_0_bits_wordMask_wordMask_T; // @[DCache.scala:554:32]
assign _dataArb_io_in_0_bits_wordMask_wordMask_T = _GEN_82; // @[DCache.scala:549:36, :554:32]
assign dataArb_io_in_0_bits_addr = _dataArb_io_in_0_bits_addr_T[7:0]; // @[DCache.scala:152:28, :549:{30,36}]
assign _dataArb_io_in_0_bits_way_en_T = pstore2_valid ? pstore2_way : pstore1_way; // @[DCache.scala:495:30, :501:30, :525:30, :550:38]
assign dataArb_io_in_0_bits_way_en = _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:152:28, :550:38]
wire [63:0] _dataArb_io_in_0_bits_wdata_T = pstore2_valid ? pstore2_storegen_data : pstore1_data; // @[package.scala:45:27]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_1 = _dataArb_io_in_0_bits_wdata_T[7:0]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_2 = _dataArb_io_in_0_bits_wdata_T[15:8]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_3 = _dataArb_io_in_0_bits_wdata_T[23:16]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_4 = _dataArb_io_in_0_bits_wdata_T[31:24]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_5 = _dataArb_io_in_0_bits_wdata_T[39:32]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_6 = _dataArb_io_in_0_bits_wdata_T[47:40]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_7 = _dataArb_io_in_0_bits_wdata_T[55:48]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_8 = _dataArb_io_in_0_bits_wdata_T[63:56]; // @[package.scala:211:50]
wire [15:0] dataArb_io_in_0_bits_wdata_lo_lo = {_dataArb_io_in_0_bits_wdata_T_2, _dataArb_io_in_0_bits_wdata_T_1}; // @[package.scala:45:27, :211:50]
wire [15:0] dataArb_io_in_0_bits_wdata_lo_hi = {_dataArb_io_in_0_bits_wdata_T_4, _dataArb_io_in_0_bits_wdata_T_3}; // @[package.scala:45:27, :211:50]
wire [31:0] dataArb_io_in_0_bits_wdata_lo = {dataArb_io_in_0_bits_wdata_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo}; // @[package.scala:45:27]
wire [15:0] dataArb_io_in_0_bits_wdata_hi_lo = {_dataArb_io_in_0_bits_wdata_T_6, _dataArb_io_in_0_bits_wdata_T_5}; // @[package.scala:45:27, :211:50]
wire [15:0] dataArb_io_in_0_bits_wdata_hi_hi = {_dataArb_io_in_0_bits_wdata_T_8, _dataArb_io_in_0_bits_wdata_T_7}; // @[package.scala:45:27, :211:50]
wire [31:0] dataArb_io_in_0_bits_wdata_hi = {dataArb_io_in_0_bits_wdata_hi_hi, dataArb_io_in_0_bits_wdata_hi_lo}; // @[package.scala:45:27]
assign _dataArb_io_in_0_bits_wdata_T_9 = {dataArb_io_in_0_bits_wdata_hi, dataArb_io_in_0_bits_wdata_lo}; // @[package.scala:45:27]
assign dataArb_io_in_0_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T = _dataArb_io_in_0_bits_eccMask_T_17[0]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T_17[1]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T_17[2]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T_17[3]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T_17[4]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T_17[5]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T_17[6]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T_17[7]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_8 = _dataArb_io_in_0_bits_wordMask_eccMask_T | _dataArb_io_in_0_bits_wordMask_eccMask_T_1; // @[package.scala:81:59]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_9 = _dataArb_io_in_0_bits_wordMask_eccMask_T_8 | _dataArb_io_in_0_bits_wordMask_eccMask_T_2; // @[package.scala:81:59]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_10 = _dataArb_io_in_0_bits_wordMask_eccMask_T_9 | _dataArb_io_in_0_bits_wordMask_eccMask_T_3; // @[package.scala:81:59]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_11 = _dataArb_io_in_0_bits_wordMask_eccMask_T_10 | _dataArb_io_in_0_bits_wordMask_eccMask_T_4; // @[package.scala:81:59]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_12 = _dataArb_io_in_0_bits_wordMask_eccMask_T_11 | _dataArb_io_in_0_bits_wordMask_eccMask_T_5; // @[package.scala:81:59]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_13 = _dataArb_io_in_0_bits_wordMask_eccMask_T_12 | _dataArb_io_in_0_bits_wordMask_eccMask_T_6; // @[package.scala:81:59]
wire dataArb_io_in_0_bits_wordMask_eccMask = _dataArb_io_in_0_bits_wordMask_eccMask_T_13 | _dataArb_io_in_0_bits_wordMask_eccMask_T_7; // @[package.scala:81:59]
wire [1:0] _dataArb_io_in_0_bits_wordMask_T_3 = {1'h0, dataArb_io_in_0_bits_wordMask_eccMask}; // @[package.scala:81:59]
assign dataArb_io_in_0_bits_wordMask = _dataArb_io_in_0_bits_wordMask_T_3[0]; // @[DCache.scala:152:28, :552:34, :555:55]
wire [7:0] _dataArb_io_in_0_bits_eccMask_T = pstore2_valid ? pstore2_storegen_mask : pstore1_mask; // @[DCache.scala:496:31, :501:30, :531:19, :557:47]
wire _dataArb_io_in_0_bits_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T[0]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_9 = _dataArb_io_in_0_bits_eccMask_T_1; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T[1]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_10 = _dataArb_io_in_0_bits_eccMask_T_2; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T[2]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_11 = _dataArb_io_in_0_bits_eccMask_T_3; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T[3]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_12 = _dataArb_io_in_0_bits_eccMask_T_4; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T[4]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_13 = _dataArb_io_in_0_bits_eccMask_T_5; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T[5]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_14 = _dataArb_io_in_0_bits_eccMask_T_6; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T[6]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_15 = _dataArb_io_in_0_bits_eccMask_T_7; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_8 = _dataArb_io_in_0_bits_eccMask_T[7]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_16 = _dataArb_io_in_0_bits_eccMask_T_8; // @[package.scala:211:50]
wire [1:0] dataArb_io_in_0_bits_eccMask_lo_lo = {_dataArb_io_in_0_bits_eccMask_T_10, _dataArb_io_in_0_bits_eccMask_T_9}; // @[package.scala:45:27]
wire [1:0] dataArb_io_in_0_bits_eccMask_lo_hi = {_dataArb_io_in_0_bits_eccMask_T_12, _dataArb_io_in_0_bits_eccMask_T_11}; // @[package.scala:45:27]
wire [3:0] dataArb_io_in_0_bits_eccMask_lo = {dataArb_io_in_0_bits_eccMask_lo_hi, dataArb_io_in_0_bits_eccMask_lo_lo}; // @[package.scala:45:27]
wire [1:0] dataArb_io_in_0_bits_eccMask_hi_lo = {_dataArb_io_in_0_bits_eccMask_T_14, _dataArb_io_in_0_bits_eccMask_T_13}; // @[package.scala:45:27]
wire [1:0] dataArb_io_in_0_bits_eccMask_hi_hi = {_dataArb_io_in_0_bits_eccMask_T_16, _dataArb_io_in_0_bits_eccMask_T_15}; // @[package.scala:45:27]
wire [3:0] dataArb_io_in_0_bits_eccMask_hi = {dataArb_io_in_0_bits_eccMask_hi_hi, dataArb_io_in_0_bits_eccMask_hi_lo}; // @[package.scala:45:27]
assign _dataArb_io_in_0_bits_eccMask_T_17 = {dataArb_io_in_0_bits_eccMask_hi, dataArb_io_in_0_bits_eccMask_lo}; // @[package.scala:45:27]
assign dataArb_io_in_0_bits_eccMask = _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27]
wire [4:0] _s1_hazard_T = pstore1_addr[7:3]; // @[DCache.scala:493:31, :561:9]
wire [4:0] _s1_hazard_T_1 = s1_vaddr[7:3]; // @[DCache.scala:197:21, :561:43]
wire [4:0] _s1_hazard_T_63 = s1_vaddr[7:3]; // @[DCache.scala:197:21, :561:43]
wire _s1_hazard_T_2 = _s1_hazard_T == _s1_hazard_T_1; // @[DCache.scala:561:{9,31,43}]
wire _s1_hazard_T_11 = _s1_hazard_T_3; // @[package.scala:211:50]
wire _s1_hazard_T_12 = _s1_hazard_T_4; // @[package.scala:211:50]
wire _s1_hazard_T_13 = _s1_hazard_T_5; // @[package.scala:211:50]
wire _s1_hazard_T_14 = _s1_hazard_T_6; // @[package.scala:211:50]
wire _s1_hazard_T_15 = _s1_hazard_T_7; // @[package.scala:211:50]
wire _s1_hazard_T_16 = _s1_hazard_T_8; // @[package.scala:211:50]
wire _s1_hazard_T_17 = _s1_hazard_T_9; // @[package.scala:211:50]
wire _s1_hazard_T_18 = _s1_hazard_T_10; // @[package.scala:211:50]
wire [1:0] s1_hazard_lo_lo = {_s1_hazard_T_12, _s1_hazard_T_11}; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_hi = {_s1_hazard_T_14, _s1_hazard_T_13}; // @[package.scala:45:27]
wire [3:0] s1_hazard_lo = {s1_hazard_lo_hi, s1_hazard_lo_lo}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_lo = {_s1_hazard_T_16, _s1_hazard_T_15}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_hi = {_s1_hazard_T_18, _s1_hazard_T_17}; // @[package.scala:45:27]
wire [3:0] s1_hazard_hi = {s1_hazard_hi_hi, s1_hazard_hi_lo}; // @[package.scala:45:27]
wire [7:0] _s1_hazard_T_19 = {s1_hazard_hi, s1_hazard_lo}; // @[package.scala:45:27]
wire _s1_hazard_T_20 = _s1_hazard_T_19[0]; // @[package.scala:45:27]
wire _s1_hazard_T_21 = _s1_hazard_T_19[1]; // @[package.scala:45:27]
wire _s1_hazard_T_22 = _s1_hazard_T_19[2]; // @[package.scala:45:27]
wire _s1_hazard_T_23 = _s1_hazard_T_19[3]; // @[package.scala:45:27]
wire _s1_hazard_T_24 = _s1_hazard_T_19[4]; // @[package.scala:45:27]
wire _s1_hazard_T_25 = _s1_hazard_T_19[5]; // @[package.scala:45:27]
wire _s1_hazard_T_26 = _s1_hazard_T_19[6]; // @[package.scala:45:27]
wire _s1_hazard_T_27 = _s1_hazard_T_19[7]; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_lo_1 = {_s1_hazard_T_21, _s1_hazard_T_20}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_lo_hi_1 = {_s1_hazard_T_23, _s1_hazard_T_22}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_lo_1 = {s1_hazard_lo_hi_1, s1_hazard_lo_lo_1}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_lo_1 = {_s1_hazard_T_25, _s1_hazard_T_24}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_hi_1 = {_s1_hazard_T_27, _s1_hazard_T_26}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_hi_1 = {s1_hazard_hi_hi_1, s1_hazard_hi_lo_1}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_28 = {s1_hazard_hi_1, s1_hazard_lo_1}; // @[DCache.scala:1182:52]
wire _s1_hazard_T_29 = s1_mask_xwr[0]; // @[package.scala:211:50]
wire _s1_hazard_T_91 = s1_mask_xwr[0]; // @[package.scala:211:50]
wire _s1_hazard_T_37 = _s1_hazard_T_29; // @[package.scala:211:50]
wire _s1_hazard_T_30 = s1_mask_xwr[1]; // @[package.scala:211:50]
wire _s1_hazard_T_92 = s1_mask_xwr[1]; // @[package.scala:211:50]
wire _s1_hazard_T_38 = _s1_hazard_T_30; // @[package.scala:211:50]
wire _s1_hazard_T_31 = s1_mask_xwr[2]; // @[package.scala:211:50]
wire _s1_hazard_T_93 = s1_mask_xwr[2]; // @[package.scala:211:50]
wire _s1_hazard_T_39 = _s1_hazard_T_31; // @[package.scala:211:50]
wire _s1_hazard_T_32 = s1_mask_xwr[3]; // @[package.scala:211:50]
wire _s1_hazard_T_94 = s1_mask_xwr[3]; // @[package.scala:211:50]
wire _s1_hazard_T_40 = _s1_hazard_T_32; // @[package.scala:211:50]
wire _s1_hazard_T_33 = s1_mask_xwr[4]; // @[package.scala:211:50]
wire _s1_hazard_T_95 = s1_mask_xwr[4]; // @[package.scala:211:50]
wire _s1_hazard_T_41 = _s1_hazard_T_33; // @[package.scala:211:50]
wire _s1_hazard_T_34 = s1_mask_xwr[5]; // @[package.scala:211:50]
wire _s1_hazard_T_96 = s1_mask_xwr[5]; // @[package.scala:211:50]
wire _s1_hazard_T_42 = _s1_hazard_T_34; // @[package.scala:211:50]
wire _s1_hazard_T_35 = s1_mask_xwr[6]; // @[package.scala:211:50]
wire _s1_hazard_T_97 = s1_mask_xwr[6]; // @[package.scala:211:50]
wire _s1_hazard_T_43 = _s1_hazard_T_35; // @[package.scala:211:50]
wire _s1_hazard_T_36 = s1_mask_xwr[7]; // @[package.scala:211:50]
wire _s1_hazard_T_98 = s1_mask_xwr[7]; // @[package.scala:211:50]
wire _s1_hazard_T_44 = _s1_hazard_T_36; // @[package.scala:211:50]
wire [1:0] s1_hazard_lo_lo_2 = {_s1_hazard_T_38, _s1_hazard_T_37}; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_hi_2 = {_s1_hazard_T_40, _s1_hazard_T_39}; // @[package.scala:45:27]
wire [3:0] s1_hazard_lo_2 = {s1_hazard_lo_hi_2, s1_hazard_lo_lo_2}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_lo_2 = {_s1_hazard_T_42, _s1_hazard_T_41}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_hi_2 = {_s1_hazard_T_44, _s1_hazard_T_43}; // @[package.scala:45:27]
wire [3:0] s1_hazard_hi_2 = {s1_hazard_hi_hi_2, s1_hazard_hi_lo_2}; // @[package.scala:45:27]
wire [7:0] _s1_hazard_T_45 = {s1_hazard_hi_2, s1_hazard_lo_2}; // @[package.scala:45:27]
wire _s1_hazard_T_46 = _s1_hazard_T_45[0]; // @[package.scala:45:27]
wire _s1_hazard_T_47 = _s1_hazard_T_45[1]; // @[package.scala:45:27]
wire _s1_hazard_T_48 = _s1_hazard_T_45[2]; // @[package.scala:45:27]
wire _s1_hazard_T_49 = _s1_hazard_T_45[3]; // @[package.scala:45:27]
wire _s1_hazard_T_50 = _s1_hazard_T_45[4]; // @[package.scala:45:27]
wire _s1_hazard_T_51 = _s1_hazard_T_45[5]; // @[package.scala:45:27]
wire _s1_hazard_T_52 = _s1_hazard_T_45[6]; // @[package.scala:45:27]
wire _s1_hazard_T_53 = _s1_hazard_T_45[7]; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_lo_3 = {_s1_hazard_T_47, _s1_hazard_T_46}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_lo_hi_3 = {_s1_hazard_T_49, _s1_hazard_T_48}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_lo_3 = {s1_hazard_lo_hi_3, s1_hazard_lo_lo_3}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_lo_3 = {_s1_hazard_T_51, _s1_hazard_T_50}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_hi_3 = {_s1_hazard_T_53, _s1_hazard_T_52}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_hi_3 = {s1_hazard_hi_hi_3, s1_hazard_hi_lo_3}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_54 = {s1_hazard_hi_3, s1_hazard_lo_3}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_55 = _s1_hazard_T_28 & _s1_hazard_T_54; // @[DCache.scala:562:38, :1182:52]
wire _s1_hazard_T_56 = |_s1_hazard_T_55; // @[DCache.scala:562:{38,66}]
wire [7:0] _s1_hazard_T_57 = pstore1_mask & s1_mask_xwr; // @[DCache.scala:496:31, :562:77]
wire _s1_hazard_T_58 = |_s1_hazard_T_57; // @[DCache.scala:562:{77,92}]
wire _s1_hazard_T_59 = s1_write ? _s1_hazard_T_56 : _s1_hazard_T_58; // @[DCache.scala:562:{8,66,92}]
wire _s1_hazard_T_60 = _s1_hazard_T_2 & _s1_hazard_T_59; // @[DCache.scala:561:{31,65}, :562:8]
wire _s1_hazard_T_61 = pstore1_valid_likely & _s1_hazard_T_60; // @[DCache.scala:505:51, :561:65, :564:27]
wire [4:0] _s1_hazard_T_62 = pstore2_addr[7:3]; // @[DCache.scala:524:31, :561:9]
wire _s1_hazard_T_64 = _s1_hazard_T_62 == _s1_hazard_T_63; // @[DCache.scala:561:{9,31,43}]
wire _s1_hazard_T_65 = pstore2_storegen_mask[0]; // @[package.scala:211:50]
wire _s1_hazard_T_73 = _s1_hazard_T_65; // @[package.scala:211:50]
wire _s1_hazard_T_66 = pstore2_storegen_mask[1]; // @[package.scala:211:50]
wire _s1_hazard_T_74 = _s1_hazard_T_66; // @[package.scala:211:50]
wire _s1_hazard_T_67 = pstore2_storegen_mask[2]; // @[package.scala:211:50]
wire _s1_hazard_T_75 = _s1_hazard_T_67; // @[package.scala:211:50]
wire _s1_hazard_T_68 = pstore2_storegen_mask[3]; // @[package.scala:211:50]
wire _s1_hazard_T_76 = _s1_hazard_T_68; // @[package.scala:211:50]
wire _s1_hazard_T_69 = pstore2_storegen_mask[4]; // @[package.scala:211:50]
wire _s1_hazard_T_77 = _s1_hazard_T_69; // @[package.scala:211:50]
wire _s1_hazard_T_70 = pstore2_storegen_mask[5]; // @[package.scala:211:50]
wire _s1_hazard_T_78 = _s1_hazard_T_70; // @[package.scala:211:50]
wire _s1_hazard_T_71 = pstore2_storegen_mask[6]; // @[package.scala:211:50]
wire _s1_hazard_T_79 = _s1_hazard_T_71; // @[package.scala:211:50]
wire _s1_hazard_T_72 = pstore2_storegen_mask[7]; // @[package.scala:211:50]
wire _s1_hazard_T_80 = _s1_hazard_T_72; // @[package.scala:211:50]
wire [1:0] s1_hazard_lo_lo_4 = {_s1_hazard_T_74, _s1_hazard_T_73}; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_hi_4 = {_s1_hazard_T_76, _s1_hazard_T_75}; // @[package.scala:45:27]
wire [3:0] s1_hazard_lo_4 = {s1_hazard_lo_hi_4, s1_hazard_lo_lo_4}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_lo_4 = {_s1_hazard_T_78, _s1_hazard_T_77}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_hi_4 = {_s1_hazard_T_80, _s1_hazard_T_79}; // @[package.scala:45:27]
wire [3:0] s1_hazard_hi_4 = {s1_hazard_hi_hi_4, s1_hazard_hi_lo_4}; // @[package.scala:45:27]
wire [7:0] _s1_hazard_T_81 = {s1_hazard_hi_4, s1_hazard_lo_4}; // @[package.scala:45:27]
wire _s1_hazard_T_82 = _s1_hazard_T_81[0]; // @[package.scala:45:27]
wire _s1_hazard_T_83 = _s1_hazard_T_81[1]; // @[package.scala:45:27]
wire _s1_hazard_T_84 = _s1_hazard_T_81[2]; // @[package.scala:45:27]
wire _s1_hazard_T_85 = _s1_hazard_T_81[3]; // @[package.scala:45:27]
wire _s1_hazard_T_86 = _s1_hazard_T_81[4]; // @[package.scala:45:27]
wire _s1_hazard_T_87 = _s1_hazard_T_81[5]; // @[package.scala:45:27]
wire _s1_hazard_T_88 = _s1_hazard_T_81[6]; // @[package.scala:45:27]
wire _s1_hazard_T_89 = _s1_hazard_T_81[7]; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_lo_5 = {_s1_hazard_T_83, _s1_hazard_T_82}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_lo_hi_5 = {_s1_hazard_T_85, _s1_hazard_T_84}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_lo_5 = {s1_hazard_lo_hi_5, s1_hazard_lo_lo_5}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_lo_5 = {_s1_hazard_T_87, _s1_hazard_T_86}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_hi_5 = {_s1_hazard_T_89, _s1_hazard_T_88}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_hi_5 = {s1_hazard_hi_hi_5, s1_hazard_hi_lo_5}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_90 = {s1_hazard_hi_5, s1_hazard_lo_5}; // @[DCache.scala:1182:52]
wire _s1_hazard_T_99 = _s1_hazard_T_91; // @[package.scala:211:50]
wire _s1_hazard_T_100 = _s1_hazard_T_92; // @[package.scala:211:50]
wire _s1_hazard_T_101 = _s1_hazard_T_93; // @[package.scala:211:50]
wire _s1_hazard_T_102 = _s1_hazard_T_94; // @[package.scala:211:50]
wire _s1_hazard_T_103 = _s1_hazard_T_95; // @[package.scala:211:50]
wire _s1_hazard_T_104 = _s1_hazard_T_96; // @[package.scala:211:50]
wire _s1_hazard_T_105 = _s1_hazard_T_97; // @[package.scala:211:50]
wire _s1_hazard_T_106 = _s1_hazard_T_98; // @[package.scala:211:50]
wire [1:0] s1_hazard_lo_lo_6 = {_s1_hazard_T_100, _s1_hazard_T_99}; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_hi_6 = {_s1_hazard_T_102, _s1_hazard_T_101}; // @[package.scala:45:27]
wire [3:0] s1_hazard_lo_6 = {s1_hazard_lo_hi_6, s1_hazard_lo_lo_6}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_lo_6 = {_s1_hazard_T_104, _s1_hazard_T_103}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_hi_6 = {_s1_hazard_T_106, _s1_hazard_T_105}; // @[package.scala:45:27]
wire [3:0] s1_hazard_hi_6 = {s1_hazard_hi_hi_6, s1_hazard_hi_lo_6}; // @[package.scala:45:27]
wire [7:0] _s1_hazard_T_107 = {s1_hazard_hi_6, s1_hazard_lo_6}; // @[package.scala:45:27]
wire _s1_hazard_T_108 = _s1_hazard_T_107[0]; // @[package.scala:45:27]
wire _s1_hazard_T_109 = _s1_hazard_T_107[1]; // @[package.scala:45:27]
wire _s1_hazard_T_110 = _s1_hazard_T_107[2]; // @[package.scala:45:27]
wire _s1_hazard_T_111 = _s1_hazard_T_107[3]; // @[package.scala:45:27]
wire _s1_hazard_T_112 = _s1_hazard_T_107[4]; // @[package.scala:45:27]
wire _s1_hazard_T_113 = _s1_hazard_T_107[5]; // @[package.scala:45:27]
wire _s1_hazard_T_114 = _s1_hazard_T_107[6]; // @[package.scala:45:27]
wire _s1_hazard_T_115 = _s1_hazard_T_107[7]; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_lo_7 = {_s1_hazard_T_109, _s1_hazard_T_108}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_lo_hi_7 = {_s1_hazard_T_111, _s1_hazard_T_110}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_lo_7 = {s1_hazard_lo_hi_7, s1_hazard_lo_lo_7}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_lo_7 = {_s1_hazard_T_113, _s1_hazard_T_112}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_hi_7 = {_s1_hazard_T_115, _s1_hazard_T_114}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_hi_7 = {s1_hazard_hi_hi_7, s1_hazard_hi_lo_7}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_116 = {s1_hazard_hi_7, s1_hazard_lo_7}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_117 = _s1_hazard_T_90 & _s1_hazard_T_116; // @[DCache.scala:562:38, :1182:52]
wire _s1_hazard_T_118 = |_s1_hazard_T_117; // @[DCache.scala:562:{38,66}]
wire [7:0] _s1_hazard_T_119 = pstore2_storegen_mask & s1_mask_xwr; // @[DCache.scala:531:19, :562:77]
wire _s1_hazard_T_120 = |_s1_hazard_T_119; // @[DCache.scala:562:{77,92}]
wire _s1_hazard_T_121 = s1_write ? _s1_hazard_T_118 : _s1_hazard_T_120; // @[DCache.scala:562:{8,66,92}]
wire _s1_hazard_T_122 = _s1_hazard_T_64 & _s1_hazard_T_121; // @[DCache.scala:561:{31,65}, :562:8]
wire _s1_hazard_T_123 = pstore2_valid & _s1_hazard_T_122; // @[DCache.scala:501:30, :561:65, :565:21]
wire s1_hazard = _s1_hazard_T_61 | _s1_hazard_T_123; // @[DCache.scala:564:{27,69}, :565:21]
wire s1_raw_hazard = s1_read & s1_hazard; // @[DCache.scala:564:69, :566:31]
wire _T_60 = s1_valid & s1_raw_hazard; // @[DCache.scala:182:25, :566:31, :571:18]
reg io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:38]
assign _io_cpu_s2_nack_cause_raw_T_3 = io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:{38,54}]
assign io_cpu_s2_nack_cause_raw_0 = _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:101:7, :574:54]
wire _a_source_T = ~uncachedInFlight_0; // @[DCache.scala:236:33, :577:34]
wire [1:0] _a_source_T_1 = {_a_source_T, 1'h0}; // @[DCache.scala:577:{34,59}]
wire _a_source_T_2 = _a_source_T_1[0]; // @[OneHot.scala:48:45]
wire _a_source_T_3 = _a_source_T_1[1]; // @[OneHot.scala:48:45]
wire a_source = ~_a_source_T_2; // @[OneHot.scala:48:45]
wire get_source = a_source; // @[Mux.scala:50:70]
wire put_source = a_source; // @[Mux.scala:50:70]
wire putpartial_source = a_source; // @[Mux.scala:50:70]
wire atomics_a_source = a_source; // @[Mux.scala:50:70]
wire atomics_a_1_source = a_source; // @[Mux.scala:50:70]
wire atomics_a_2_source = a_source; // @[Mux.scala:50:70]
wire atomics_a_3_source = a_source; // @[Mux.scala:50:70]
wire atomics_a_4_source = a_source; // @[Mux.scala:50:70]
wire atomics_a_5_source = a_source; // @[Mux.scala:50:70]
wire atomics_a_6_source = a_source; // @[Mux.scala:50:70]
wire atomics_a_7_source = a_source; // @[Mux.scala:50:70]
wire atomics_a_8_source = a_source; // @[Mux.scala:50:70]
wire a_sel_shiftAmount = a_source; // @[OneHot.scala:64:49]
wire [39:0] acquire_address = {_acquire_address_T, 6'h0}; // @[DCache.scala:578:{38,49}]
wire [22:0] a_mask = {15'h0, pstore1_mask}; // @[DCache.scala:496:31, :582:29]
wire [39:0] _GEN_83 = {s2_req_addr[39:14], s2_req_addr[13:0] ^ 14'h3000}; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_4; // @[Parameters.scala:137:31]
assign _get_legal_T_4 = _GEN_83; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_4; // @[Parameters.scala:137:31]
assign _put_legal_T_4 = _GEN_83; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_4; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_4 = _GEN_83; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_6 = _get_legal_T_5 & 41'hFFEFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46]
wire _get_legal_T_8 = _get_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54]
wire _get_legal_T_72 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_16 = _get_legal_T_15 & 41'hFFEFA000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46]
wire _get_legal_T_18 = _get_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_84 = {s2_req_addr[39:17], s2_req_addr[16:0] ^ 17'h10000}; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_19; // @[Parameters.scala:137:31]
assign _get_legal_T_19 = _GEN_84; // @[Parameters.scala:137:31]
wire [39:0] _get_legal_T_24; // @[Parameters.scala:137:31]
assign _get_legal_T_24 = _GEN_84; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_63; // @[Parameters.scala:137:31]
assign _put_legal_T_63 = _GEN_84; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_63; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_63 = _GEN_84; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_53; // @[Parameters.scala:137:31]
assign _atomics_legal_T_53 = _GEN_84; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_113; // @[Parameters.scala:137:31]
assign _atomics_legal_T_113 = _GEN_84; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_173; // @[Parameters.scala:137:31]
assign _atomics_legal_T_173 = _GEN_84; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_233; // @[Parameters.scala:137:31]
assign _atomics_legal_T_233 = _GEN_84; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_293; // @[Parameters.scala:137:31]
assign _atomics_legal_T_293 = _GEN_84; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_353; // @[Parameters.scala:137:31]
assign _atomics_legal_T_353 = _GEN_84; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_413; // @[Parameters.scala:137:31]
assign _atomics_legal_T_413 = _GEN_84; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_473; // @[Parameters.scala:137:31]
assign _atomics_legal_T_473 = _GEN_84; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_533; // @[Parameters.scala:137:31]
assign _atomics_legal_T_533 = _GEN_84; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_21 = _get_legal_T_20 & 41'hFDEFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46]
wire _get_legal_T_23 = _get_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_26 = _get_legal_T_25 & 41'hFFEF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46]
wire _get_legal_T_28 = _get_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_85 = {s2_req_addr[39:26], s2_req_addr[25:0] ^ 26'h2000000}; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_29; // @[Parameters.scala:137:31]
assign _get_legal_T_29 = _GEN_85; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_24; // @[Parameters.scala:137:31]
assign _put_legal_T_24 = _GEN_85; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_24; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_24 = _GEN_85; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_14; // @[Parameters.scala:137:31]
assign _atomics_legal_T_14 = _GEN_85; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_74; // @[Parameters.scala:137:31]
assign _atomics_legal_T_74 = _GEN_85; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_134; // @[Parameters.scala:137:31]
assign _atomics_legal_T_134 = _GEN_85; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_194; // @[Parameters.scala:137:31]
assign _atomics_legal_T_194 = _GEN_85; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_254; // @[Parameters.scala:137:31]
assign _atomics_legal_T_254 = _GEN_85; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_314; // @[Parameters.scala:137:31]
assign _atomics_legal_T_314 = _GEN_85; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_374; // @[Parameters.scala:137:31]
assign _atomics_legal_T_374 = _GEN_85; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_434; // @[Parameters.scala:137:31]
assign _atomics_legal_T_434 = _GEN_85; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_494; // @[Parameters.scala:137:31]
assign _atomics_legal_T_494 = _GEN_85; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_31 = _get_legal_T_30 & 41'hFFEF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46]
wire _get_legal_T_33 = _get_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_86 = {s2_req_addr[39:28], s2_req_addr[27:0] ^ 28'h8000000}; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_34; // @[Parameters.scala:137:31]
assign _get_legal_T_34 = _GEN_86; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_34; // @[Parameters.scala:137:31]
assign _put_legal_T_34 = _GEN_86; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_34; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_34 = _GEN_86; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_24; // @[Parameters.scala:137:31]
assign _atomics_legal_T_24 = _GEN_86; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_84; // @[Parameters.scala:137:31]
assign _atomics_legal_T_84 = _GEN_86; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_144; // @[Parameters.scala:137:31]
assign _atomics_legal_T_144 = _GEN_86; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_204; // @[Parameters.scala:137:31]
assign _atomics_legal_T_204 = _GEN_86; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_264; // @[Parameters.scala:137:31]
assign _atomics_legal_T_264 = _GEN_86; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_324; // @[Parameters.scala:137:31]
assign _atomics_legal_T_324 = _GEN_86; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_384; // @[Parameters.scala:137:31]
assign _atomics_legal_T_384 = _GEN_86; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_444; // @[Parameters.scala:137:31]
assign _atomics_legal_T_444 = _GEN_86; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_504; // @[Parameters.scala:137:31]
assign _atomics_legal_T_504 = _GEN_86; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_36 = _get_legal_T_35 & 41'hFFEF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46]
wire _get_legal_T_38 = _get_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_87 = {s2_req_addr[39:28], s2_req_addr[27:0] ^ 28'hC000000}; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_39; // @[Parameters.scala:137:31]
assign _get_legal_T_39 = _GEN_87; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_39; // @[Parameters.scala:137:31]
assign _put_legal_T_39 = _GEN_87; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_39; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_39 = _GEN_87; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_29; // @[Parameters.scala:137:31]
assign _atomics_legal_T_29 = _GEN_87; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_89; // @[Parameters.scala:137:31]
assign _atomics_legal_T_89 = _GEN_87; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_149; // @[Parameters.scala:137:31]
assign _atomics_legal_T_149 = _GEN_87; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_209; // @[Parameters.scala:137:31]
assign _atomics_legal_T_209 = _GEN_87; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_269; // @[Parameters.scala:137:31]
assign _atomics_legal_T_269 = _GEN_87; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_329; // @[Parameters.scala:137:31]
assign _atomics_legal_T_329 = _GEN_87; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_389; // @[Parameters.scala:137:31]
assign _atomics_legal_T_389 = _GEN_87; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_449; // @[Parameters.scala:137:31]
assign _atomics_legal_T_449 = _GEN_87; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_509; // @[Parameters.scala:137:31]
assign _atomics_legal_T_509 = _GEN_87; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_41 = _get_legal_T_40 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46]
wire _get_legal_T_43 = _get_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_88 = {s2_req_addr[39:29], s2_req_addr[28:0] ^ 29'h10020000}; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_44; // @[Parameters.scala:137:31]
assign _get_legal_T_44 = _GEN_88; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_44; // @[Parameters.scala:137:31]
assign _put_legal_T_44 = _GEN_88; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_44; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_44 = _GEN_88; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_34; // @[Parameters.scala:137:31]
assign _atomics_legal_T_34 = _GEN_88; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_94; // @[Parameters.scala:137:31]
assign _atomics_legal_T_94 = _GEN_88; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_154; // @[Parameters.scala:137:31]
assign _atomics_legal_T_154 = _GEN_88; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_214; // @[Parameters.scala:137:31]
assign _atomics_legal_T_214 = _GEN_88; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_274; // @[Parameters.scala:137:31]
assign _atomics_legal_T_274 = _GEN_88; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_334; // @[Parameters.scala:137:31]
assign _atomics_legal_T_334 = _GEN_88; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_394; // @[Parameters.scala:137:31]
assign _atomics_legal_T_394 = _GEN_88; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_454; // @[Parameters.scala:137:31]
assign _atomics_legal_T_454 = _GEN_88; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_514; // @[Parameters.scala:137:31]
assign _atomics_legal_T_514 = _GEN_88; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_46 = _get_legal_T_45 & 41'hFFEFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46]
wire _get_legal_T_48 = _get_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
assign io_cpu_s2_paddr_0 = s2_req_addr[31:0]; // @[DCache.scala:101:7, :339:19]
wire [31:0] get_address = s2_req_addr[31:0]; // @[Edges.scala:460:17]
wire [31:0] put_address = s2_req_addr[31:0]; // @[Edges.scala:480:17]
wire [31:0] putpartial_address = s2_req_addr[31:0]; // @[Edges.scala:500:17]
wire [31:0] atomics_a_address = s2_req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_1_address = s2_req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_2_address = s2_req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_3_address = s2_req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_4_address = s2_req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_5_address = s2_req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_6_address = s2_req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_7_address = s2_req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_8_address = s2_req_addr[31:0]; // @[Edges.scala:517:17]
wire [39:0] _GEN_89 = {s2_req_addr[39:32], s2_req_addr[31:0] ^ 32'h80000000}; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_49; // @[Parameters.scala:137:31]
assign _get_legal_T_49 = _GEN_89; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_49; // @[Parameters.scala:137:31]
assign _put_legal_T_49 = _GEN_89; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_49; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_49 = _GEN_89; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_39; // @[Parameters.scala:137:31]
assign _atomics_legal_T_39 = _GEN_89; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_99; // @[Parameters.scala:137:31]
assign _atomics_legal_T_99 = _GEN_89; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_159; // @[Parameters.scala:137:31]
assign _atomics_legal_T_159 = _GEN_89; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_219; // @[Parameters.scala:137:31]
assign _atomics_legal_T_219 = _GEN_89; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_279; // @[Parameters.scala:137:31]
assign _atomics_legal_T_279 = _GEN_89; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_339; // @[Parameters.scala:137:31]
assign _atomics_legal_T_339 = _GEN_89; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_399; // @[Parameters.scala:137:31]
assign _atomics_legal_T_399 = _GEN_89; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_459; // @[Parameters.scala:137:31]
assign _atomics_legal_T_459 = _GEN_89; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_519; // @[Parameters.scala:137:31]
assign _atomics_legal_T_519 = _GEN_89; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_50 = {1'h0, _get_legal_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_51 = _get_legal_T_50 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_52 = _get_legal_T_51; // @[Parameters.scala:137:46]
wire _get_legal_T_53 = _get_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _get_legal_T_54 = _get_legal_T_18 | _get_legal_T_23; // @[Parameters.scala:685:42]
wire _get_legal_T_55 = _get_legal_T_54 | _get_legal_T_28; // @[Parameters.scala:685:42]
wire _get_legal_T_56 = _get_legal_T_55 | _get_legal_T_33; // @[Parameters.scala:685:42]
wire _get_legal_T_57 = _get_legal_T_56 | _get_legal_T_38; // @[Parameters.scala:685:42]
wire _get_legal_T_58 = _get_legal_T_57 | _get_legal_T_43; // @[Parameters.scala:685:42]
wire _get_legal_T_59 = _get_legal_T_58 | _get_legal_T_48; // @[Parameters.scala:685:42]
wire _get_legal_T_60 = _get_legal_T_59 | _get_legal_T_53; // @[Parameters.scala:685:42]
wire _get_legal_T_61 = _get_legal_T_60; // @[Parameters.scala:684:54, :685:42]
wire [39:0] _GEN_90 = {s2_req_addr[39:18], s2_req_addr[17:0] ^ 18'h20000}; // @[DCache.scala:339:19]
wire [39:0] _get_legal_T_66; // @[Parameters.scala:137:31]
assign _get_legal_T_66 = _GEN_90; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_73; // @[Parameters.scala:137:31]
assign _put_legal_T_73 = _GEN_90; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_73; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_73 = _GEN_90; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_67 = {1'h0, _get_legal_T_66}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_68 = _get_legal_T_67 & 41'hFFEF8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_69 = _get_legal_T_68; // @[Parameters.scala:137:46]
wire _get_legal_T_70 = _get_legal_T_69 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _get_legal_T_71 = _get_legal_T_70; // @[Parameters.scala:684:54]
wire _get_legal_T_73 = _get_legal_T_72 | _get_legal_T_61; // @[Parameters.scala:684:54, :686:26]
wire get_legal = _get_legal_T_73 | _get_legal_T_71; // @[Parameters.scala:684:54, :686:26]
wire [7:0] _get_a_mask_T; // @[Misc.scala:222:10]
wire [3:0] get_size; // @[Edges.scala:460:17]
wire [7:0] get_mask; // @[Edges.scala:460:17]
wire [3:0] _GEN_91 = {2'h0, s2_req_size}; // @[Edges.scala:463:15]
assign get_size = _GEN_91; // @[Edges.scala:460:17, :463:15]
wire [3:0] put_size; // @[Edges.scala:480:17]
assign put_size = _GEN_91; // @[Edges.scala:463:15, :480:17]
wire [3:0] putpartial_size; // @[Edges.scala:500:17]
assign putpartial_size = _GEN_91; // @[Edges.scala:463:15, :500:17]
wire [3:0] atomics_a_size; // @[Edges.scala:534:17]
assign atomics_a_size = _GEN_91; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17]
assign atomics_a_1_size = _GEN_91; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17]
assign atomics_a_2_size = _GEN_91; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17]
assign atomics_a_3_size = _GEN_91; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17]
assign atomics_a_4_size = _GEN_91; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17]
assign atomics_a_5_size = _GEN_91; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17]
assign atomics_a_6_size = _GEN_91; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17]
assign atomics_a_7_size = _GEN_91; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17]
assign atomics_a_8_size = _GEN_91; // @[Edges.scala:463:15, :517:17]
wire [2:0] _GEN_92 = {1'h0, s2_req_size}; // @[Misc.scala:202:34]
wire [2:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _get_a_mask_sizeOH_T = _GEN_92; // @[Misc.scala:202:34]
wire [2:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _put_a_mask_sizeOH_T = _GEN_92; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T = _GEN_92; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_3 = _GEN_92; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_6 = _GEN_92; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_9 = _GEN_92; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_12 = _GEN_92; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_15 = _GEN_92; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_18 = _GEN_92; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_21 = _GEN_92; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_24 = _GEN_92; // @[Misc.scala:202:34]
wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire get_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21]
wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26]
wire put_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_1 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_2 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_3 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_4 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_5 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_6 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_7 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_8 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire _io_cpu_resp_bits_data_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26]
wire _io_cpu_resp_bits_data_word_bypass_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26]
wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26]
wire put_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_1 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_2 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_3 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_4 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_5 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_6 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_7 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_8 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire _io_cpu_resp_bits_data_shifted_T_3 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26]
wire put_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_1 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_2 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_3 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_4 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_5 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_6 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_7 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_8 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire _io_cpu_resp_bits_data_shifted_T_6 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc = get_a_mask_sub_0_1 | _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_1 = get_a_mask_sub_0_1 | _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_2 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_3 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_4 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_5 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_6 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_7 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] get_a_mask_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] get_a_mask_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] get_a_mask_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] get_a_mask_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10]
assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10]
wire [40:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_6 = _put_legal_T_5 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46]
wire _put_legal_T_8 = _put_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54]
wire _put_legal_T_79 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_16 = _put_legal_T_15 & 41'hFFFFA000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46]
wire _put_legal_T_18 = _put_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_93 = {s2_req_addr[39:21], s2_req_addr[20:0] ^ 21'h100000}; // @[DCache.scala:339:19]
wire [39:0] _put_legal_T_19; // @[Parameters.scala:137:31]
assign _put_legal_T_19 = _GEN_93; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_19; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_19 = _GEN_93; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_9; // @[Parameters.scala:137:31]
assign _atomics_legal_T_9 = _GEN_93; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_69; // @[Parameters.scala:137:31]
assign _atomics_legal_T_69 = _GEN_93; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_129; // @[Parameters.scala:137:31]
assign _atomics_legal_T_129 = _GEN_93; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_189; // @[Parameters.scala:137:31]
assign _atomics_legal_T_189 = _GEN_93; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_249; // @[Parameters.scala:137:31]
assign _atomics_legal_T_249 = _GEN_93; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_309; // @[Parameters.scala:137:31]
assign _atomics_legal_T_309 = _GEN_93; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_369; // @[Parameters.scala:137:31]
assign _atomics_legal_T_369 = _GEN_93; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_429; // @[Parameters.scala:137:31]
assign _atomics_legal_T_429 = _GEN_93; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_489; // @[Parameters.scala:137:31]
assign _atomics_legal_T_489 = _GEN_93; // @[Parameters.scala:137:31]
wire [40:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_21 = _put_legal_T_20 & 41'hFFFEB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46]
wire _put_legal_T_23 = _put_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_26 = _put_legal_T_25 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46]
wire _put_legal_T_28 = _put_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_94 = {s2_req_addr[39:26], s2_req_addr[25:0] ^ 26'h2010000}; // @[DCache.scala:339:19]
wire [39:0] _put_legal_T_29; // @[Parameters.scala:137:31]
assign _put_legal_T_29 = _GEN_94; // @[Parameters.scala:137:31]
wire [39:0] _putpartial_legal_T_29; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_29 = _GEN_94; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_19; // @[Parameters.scala:137:31]
assign _atomics_legal_T_19 = _GEN_94; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_79; // @[Parameters.scala:137:31]
assign _atomics_legal_T_79 = _GEN_94; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_139; // @[Parameters.scala:137:31]
assign _atomics_legal_T_139 = _GEN_94; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_199; // @[Parameters.scala:137:31]
assign _atomics_legal_T_199 = _GEN_94; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_259; // @[Parameters.scala:137:31]
assign _atomics_legal_T_259 = _GEN_94; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_319; // @[Parameters.scala:137:31]
assign _atomics_legal_T_319 = _GEN_94; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_379; // @[Parameters.scala:137:31]
assign _atomics_legal_T_379 = _GEN_94; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_439; // @[Parameters.scala:137:31]
assign _atomics_legal_T_439 = _GEN_94; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_499; // @[Parameters.scala:137:31]
assign _atomics_legal_T_499 = _GEN_94; // @[Parameters.scala:137:31]
wire [40:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_31 = _put_legal_T_30 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46]
wire _put_legal_T_33 = _put_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_36 = _put_legal_T_35 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46]
wire _put_legal_T_38 = _put_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_40 = {1'h0, _put_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_41 = _put_legal_T_40 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_42 = _put_legal_T_41; // @[Parameters.scala:137:46]
wire _put_legal_T_43 = _put_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_45 = {1'h0, _put_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_46 = _put_legal_T_45 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_47 = _put_legal_T_46; // @[Parameters.scala:137:46]
wire _put_legal_T_48 = _put_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_50 = {1'h0, _put_legal_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_51 = _put_legal_T_50 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_52 = _put_legal_T_51; // @[Parameters.scala:137:46]
wire _put_legal_T_53 = _put_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_54 = _put_legal_T_18 | _put_legal_T_23; // @[Parameters.scala:685:42]
wire _put_legal_T_55 = _put_legal_T_54 | _put_legal_T_28; // @[Parameters.scala:685:42]
wire _put_legal_T_56 = _put_legal_T_55 | _put_legal_T_33; // @[Parameters.scala:685:42]
wire _put_legal_T_57 = _put_legal_T_56 | _put_legal_T_38; // @[Parameters.scala:685:42]
wire _put_legal_T_58 = _put_legal_T_57 | _put_legal_T_43; // @[Parameters.scala:685:42]
wire _put_legal_T_59 = _put_legal_T_58 | _put_legal_T_48; // @[Parameters.scala:685:42]
wire _put_legal_T_60 = _put_legal_T_59 | _put_legal_T_53; // @[Parameters.scala:685:42]
wire _put_legal_T_61 = _put_legal_T_60; // @[Parameters.scala:684:54, :685:42]
wire [40:0] _put_legal_T_64 = {1'h0, _put_legal_T_63}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_65 = _put_legal_T_64 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_66 = _put_legal_T_65; // @[Parameters.scala:137:46]
wire _put_legal_T_67 = _put_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_74 = {1'h0, _put_legal_T_73}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_75 = _put_legal_T_74 & 41'hFFFF8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_76 = _put_legal_T_75; // @[Parameters.scala:137:46]
wire _put_legal_T_77 = _put_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_78 = _put_legal_T_77; // @[Parameters.scala:684:54]
wire _put_legal_T_80 = _put_legal_T_79 | _put_legal_T_61; // @[Parameters.scala:684:54, :686:26]
wire _put_legal_T_81 = _put_legal_T_80; // @[Parameters.scala:686:26]
wire put_legal = _put_legal_T_81 | _put_legal_T_78; // @[Parameters.scala:684:54, :686:26]
wire [7:0] _put_a_mask_T; // @[Misc.scala:222:10]
wire [7:0] put_mask; // @[Edges.scala:480:17]
wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire put_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21]
wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc = put_a_mask_sub_0_1 | _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_1 = put_a_mask_sub_0_1 | _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_2 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_3 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_4 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_5 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_6 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_7 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] put_a_mask_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] put_a_mask_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] put_a_mask_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] put_a_mask_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10]
assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10]
wire [40:0] _putpartial_legal_T_5 = {1'h0, _putpartial_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_6 = _putpartial_legal_T_5 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_7 = _putpartial_legal_T_6; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_8 = _putpartial_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _putpartial_legal_T_9 = _putpartial_legal_T_8; // @[Parameters.scala:684:54]
wire _putpartial_legal_T_79 = _putpartial_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _putpartial_legal_T_15 = {1'h0, _putpartial_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_16 = _putpartial_legal_T_15 & 41'hFFFFA000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_17 = _putpartial_legal_T_16; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_18 = _putpartial_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_20 = {1'h0, _putpartial_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_21 = _putpartial_legal_T_20 & 41'hFFFEB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_22 = _putpartial_legal_T_21; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_23 = _putpartial_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_25 = {1'h0, _putpartial_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_26 = _putpartial_legal_T_25 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_27 = _putpartial_legal_T_26; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_28 = _putpartial_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_30 = {1'h0, _putpartial_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_31 = _putpartial_legal_T_30 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_32 = _putpartial_legal_T_31; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_33 = _putpartial_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_35 = {1'h0, _putpartial_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_36 = _putpartial_legal_T_35 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_37 = _putpartial_legal_T_36; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_38 = _putpartial_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_40 = {1'h0, _putpartial_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_41 = _putpartial_legal_T_40 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_42 = _putpartial_legal_T_41; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_43 = _putpartial_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_45 = {1'h0, _putpartial_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_46 = _putpartial_legal_T_45 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_47 = _putpartial_legal_T_46; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_48 = _putpartial_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_50 = {1'h0, _putpartial_legal_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_51 = _putpartial_legal_T_50 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_52 = _putpartial_legal_T_51; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_53 = _putpartial_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _putpartial_legal_T_54 = _putpartial_legal_T_18 | _putpartial_legal_T_23; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_55 = _putpartial_legal_T_54 | _putpartial_legal_T_28; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_56 = _putpartial_legal_T_55 | _putpartial_legal_T_33; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_57 = _putpartial_legal_T_56 | _putpartial_legal_T_38; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_58 = _putpartial_legal_T_57 | _putpartial_legal_T_43; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_59 = _putpartial_legal_T_58 | _putpartial_legal_T_48; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_60 = _putpartial_legal_T_59 | _putpartial_legal_T_53; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_61 = _putpartial_legal_T_60; // @[Parameters.scala:684:54, :685:42]
wire [40:0] _putpartial_legal_T_64 = {1'h0, _putpartial_legal_T_63}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_65 = _putpartial_legal_T_64 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_66 = _putpartial_legal_T_65; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_67 = _putpartial_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _putpartial_legal_T_74 = {1'h0, _putpartial_legal_T_73}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _putpartial_legal_T_75 = _putpartial_legal_T_74 & 41'hFFFF8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _putpartial_legal_T_76 = _putpartial_legal_T_75; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_77 = _putpartial_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _putpartial_legal_T_78 = _putpartial_legal_T_77; // @[Parameters.scala:684:54]
wire _putpartial_legal_T_80 = _putpartial_legal_T_79 | _putpartial_legal_T_61; // @[Parameters.scala:684:54, :686:26]
wire _putpartial_legal_T_81 = _putpartial_legal_T_80; // @[Parameters.scala:686:26]
wire putpartial_legal = _putpartial_legal_T_81 | _putpartial_legal_T_78; // @[Parameters.scala:684:54, :686:26]
wire [7:0] putpartial_mask; // @[Edges.scala:500:17]
assign putpartial_mask = a_mask[7:0]; // @[Edges.scala:500:17, :508:15]
wire [40:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46]
wire _atomics_legal_T_8 = _atomics_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46]
wire _atomics_legal_T_13 = _atomics_legal_T_12 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46]
wire _atomics_legal_T_18 = _atomics_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_20 = {1'h0, _atomics_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_21 = _atomics_legal_T_20 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_22 = _atomics_legal_T_21; // @[Parameters.scala:137:46]
wire _atomics_legal_T_23 = _atomics_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_26 = _atomics_legal_T_25 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_27 = _atomics_legal_T_26; // @[Parameters.scala:137:46]
wire _atomics_legal_T_28 = _atomics_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_30 = {1'h0, _atomics_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_31 = _atomics_legal_T_30 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_32 = _atomics_legal_T_31; // @[Parameters.scala:137:46]
wire _atomics_legal_T_33 = _atomics_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_35 = {1'h0, _atomics_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_36 = _atomics_legal_T_35 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_37 = _atomics_legal_T_36; // @[Parameters.scala:137:46]
wire _atomics_legal_T_38 = _atomics_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_40 = {1'h0, _atomics_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_41 = _atomics_legal_T_40 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_42 = _atomics_legal_T_41; // @[Parameters.scala:137:46]
wire _atomics_legal_T_43 = _atomics_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_44 = _atomics_legal_T_8 | _atomics_legal_T_13; // @[Parameters.scala:685:42]
wire _atomics_legal_T_45 = _atomics_legal_T_44 | _atomics_legal_T_18; // @[Parameters.scala:685:42]
wire _atomics_legal_T_46 = _atomics_legal_T_45 | _atomics_legal_T_23; // @[Parameters.scala:685:42]
wire _atomics_legal_T_47 = _atomics_legal_T_46 | _atomics_legal_T_28; // @[Parameters.scala:685:42]
wire _atomics_legal_T_48 = _atomics_legal_T_47 | _atomics_legal_T_33; // @[Parameters.scala:685:42]
wire _atomics_legal_T_49 = _atomics_legal_T_48 | _atomics_legal_T_38; // @[Parameters.scala:685:42]
wire _atomics_legal_T_50 = _atomics_legal_T_49 | _atomics_legal_T_43; // @[Parameters.scala:685:42]
wire _atomics_legal_T_51 = _atomics_legal_T_50; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_59 = _atomics_legal_T_51; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_54 = {1'h0, _atomics_legal_T_53}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_55 = _atomics_legal_T_54 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_56 = _atomics_legal_T_55; // @[Parameters.scala:137:46]
wire _atomics_legal_T_57 = _atomics_legal_T_56 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal = _atomics_legal_T_59; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T; // @[Misc.scala:222:10]
wire [7:0] atomics_a_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10]
assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_65 = {1'h0, _atomics_legal_T_64}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_66 = _atomics_legal_T_65 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_67 = _atomics_legal_T_66; // @[Parameters.scala:137:46]
wire _atomics_legal_T_68 = _atomics_legal_T_67 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_70 = {1'h0, _atomics_legal_T_69}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_71 = _atomics_legal_T_70 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_72 = _atomics_legal_T_71; // @[Parameters.scala:137:46]
wire _atomics_legal_T_73 = _atomics_legal_T_72 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_75 = {1'h0, _atomics_legal_T_74}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_76 = _atomics_legal_T_75 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_77 = _atomics_legal_T_76; // @[Parameters.scala:137:46]
wire _atomics_legal_T_78 = _atomics_legal_T_77 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_80 = {1'h0, _atomics_legal_T_79}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_81 = _atomics_legal_T_80 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_82 = _atomics_legal_T_81; // @[Parameters.scala:137:46]
wire _atomics_legal_T_83 = _atomics_legal_T_82 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_85 = {1'h0, _atomics_legal_T_84}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_86 = _atomics_legal_T_85 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_87 = _atomics_legal_T_86; // @[Parameters.scala:137:46]
wire _atomics_legal_T_88 = _atomics_legal_T_87 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_90 = {1'h0, _atomics_legal_T_89}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_91 = _atomics_legal_T_90 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_92 = _atomics_legal_T_91; // @[Parameters.scala:137:46]
wire _atomics_legal_T_93 = _atomics_legal_T_92 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_95 = {1'h0, _atomics_legal_T_94}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_96 = _atomics_legal_T_95 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_97 = _atomics_legal_T_96; // @[Parameters.scala:137:46]
wire _atomics_legal_T_98 = _atomics_legal_T_97 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_100 = {1'h0, _atomics_legal_T_99}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_101 = _atomics_legal_T_100 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_102 = _atomics_legal_T_101; // @[Parameters.scala:137:46]
wire _atomics_legal_T_103 = _atomics_legal_T_102 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_104 = _atomics_legal_T_68 | _atomics_legal_T_73; // @[Parameters.scala:685:42]
wire _atomics_legal_T_105 = _atomics_legal_T_104 | _atomics_legal_T_78; // @[Parameters.scala:685:42]
wire _atomics_legal_T_106 = _atomics_legal_T_105 | _atomics_legal_T_83; // @[Parameters.scala:685:42]
wire _atomics_legal_T_107 = _atomics_legal_T_106 | _atomics_legal_T_88; // @[Parameters.scala:685:42]
wire _atomics_legal_T_108 = _atomics_legal_T_107 | _atomics_legal_T_93; // @[Parameters.scala:685:42]
wire _atomics_legal_T_109 = _atomics_legal_T_108 | _atomics_legal_T_98; // @[Parameters.scala:685:42]
wire _atomics_legal_T_110 = _atomics_legal_T_109 | _atomics_legal_T_103; // @[Parameters.scala:685:42]
wire _atomics_legal_T_111 = _atomics_legal_T_110; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_119 = _atomics_legal_T_111; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_114 = {1'h0, _atomics_legal_T_113}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_115 = _atomics_legal_T_114 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_116 = _atomics_legal_T_115; // @[Parameters.scala:137:46]
wire _atomics_legal_T_117 = _atomics_legal_T_116 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_1 = _atomics_legal_T_119; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10]
wire [7:0] atomics_a_1_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_1 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_8 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size_1 & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_8 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_9 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size_1 & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_9 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_10 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size_1 & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_10 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_11 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size_1 & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_11 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_12 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size_1 & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_12 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_13 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size_1 & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_13 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_14 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size_1 & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_14 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_15 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size_1 & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_15 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10]
assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_125 = {1'h0, _atomics_legal_T_124}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_126 = _atomics_legal_T_125 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_127 = _atomics_legal_T_126; // @[Parameters.scala:137:46]
wire _atomics_legal_T_128 = _atomics_legal_T_127 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_130 = {1'h0, _atomics_legal_T_129}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_131 = _atomics_legal_T_130 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_132 = _atomics_legal_T_131; // @[Parameters.scala:137:46]
wire _atomics_legal_T_133 = _atomics_legal_T_132 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_135 = {1'h0, _atomics_legal_T_134}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_136 = _atomics_legal_T_135 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_137 = _atomics_legal_T_136; // @[Parameters.scala:137:46]
wire _atomics_legal_T_138 = _atomics_legal_T_137 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_140 = {1'h0, _atomics_legal_T_139}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_141 = _atomics_legal_T_140 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_142 = _atomics_legal_T_141; // @[Parameters.scala:137:46]
wire _atomics_legal_T_143 = _atomics_legal_T_142 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_145 = {1'h0, _atomics_legal_T_144}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_146 = _atomics_legal_T_145 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_147 = _atomics_legal_T_146; // @[Parameters.scala:137:46]
wire _atomics_legal_T_148 = _atomics_legal_T_147 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_150 = {1'h0, _atomics_legal_T_149}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_151 = _atomics_legal_T_150 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_152 = _atomics_legal_T_151; // @[Parameters.scala:137:46]
wire _atomics_legal_T_153 = _atomics_legal_T_152 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_155 = {1'h0, _atomics_legal_T_154}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_156 = _atomics_legal_T_155 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_157 = _atomics_legal_T_156; // @[Parameters.scala:137:46]
wire _atomics_legal_T_158 = _atomics_legal_T_157 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_160 = {1'h0, _atomics_legal_T_159}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_161 = _atomics_legal_T_160 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_162 = _atomics_legal_T_161; // @[Parameters.scala:137:46]
wire _atomics_legal_T_163 = _atomics_legal_T_162 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_164 = _atomics_legal_T_128 | _atomics_legal_T_133; // @[Parameters.scala:685:42]
wire _atomics_legal_T_165 = _atomics_legal_T_164 | _atomics_legal_T_138; // @[Parameters.scala:685:42]
wire _atomics_legal_T_166 = _atomics_legal_T_165 | _atomics_legal_T_143; // @[Parameters.scala:685:42]
wire _atomics_legal_T_167 = _atomics_legal_T_166 | _atomics_legal_T_148; // @[Parameters.scala:685:42]
wire _atomics_legal_T_168 = _atomics_legal_T_167 | _atomics_legal_T_153; // @[Parameters.scala:685:42]
wire _atomics_legal_T_169 = _atomics_legal_T_168 | _atomics_legal_T_158; // @[Parameters.scala:685:42]
wire _atomics_legal_T_170 = _atomics_legal_T_169 | _atomics_legal_T_163; // @[Parameters.scala:685:42]
wire _atomics_legal_T_171 = _atomics_legal_T_170; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_179 = _atomics_legal_T_171; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_174 = {1'h0, _atomics_legal_T_173}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_175 = _atomics_legal_T_174 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_176 = _atomics_legal_T_175; // @[Parameters.scala:137:46]
wire _atomics_legal_T_177 = _atomics_legal_T_176 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_2 = _atomics_legal_T_179; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10]
wire [7:0] atomics_a_2_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_2 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_2 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_2 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_2 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_2 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_2 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_2 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_2 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_2 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10]
assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_185 = {1'h0, _atomics_legal_T_184}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_186 = _atomics_legal_T_185 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_187 = _atomics_legal_T_186; // @[Parameters.scala:137:46]
wire _atomics_legal_T_188 = _atomics_legal_T_187 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_190 = {1'h0, _atomics_legal_T_189}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_191 = _atomics_legal_T_190 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_192 = _atomics_legal_T_191; // @[Parameters.scala:137:46]
wire _atomics_legal_T_193 = _atomics_legal_T_192 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_195 = {1'h0, _atomics_legal_T_194}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_196 = _atomics_legal_T_195 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_197 = _atomics_legal_T_196; // @[Parameters.scala:137:46]
wire _atomics_legal_T_198 = _atomics_legal_T_197 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_200 = {1'h0, _atomics_legal_T_199}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_201 = _atomics_legal_T_200 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_202 = _atomics_legal_T_201; // @[Parameters.scala:137:46]
wire _atomics_legal_T_203 = _atomics_legal_T_202 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_205 = {1'h0, _atomics_legal_T_204}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_206 = _atomics_legal_T_205 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_207 = _atomics_legal_T_206; // @[Parameters.scala:137:46]
wire _atomics_legal_T_208 = _atomics_legal_T_207 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_210 = {1'h0, _atomics_legal_T_209}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_211 = _atomics_legal_T_210 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_212 = _atomics_legal_T_211; // @[Parameters.scala:137:46]
wire _atomics_legal_T_213 = _atomics_legal_T_212 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_215 = {1'h0, _atomics_legal_T_214}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_216 = _atomics_legal_T_215 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_217 = _atomics_legal_T_216; // @[Parameters.scala:137:46]
wire _atomics_legal_T_218 = _atomics_legal_T_217 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_220 = {1'h0, _atomics_legal_T_219}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_221 = _atomics_legal_T_220 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_222 = _atomics_legal_T_221; // @[Parameters.scala:137:46]
wire _atomics_legal_T_223 = _atomics_legal_T_222 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_224 = _atomics_legal_T_188 | _atomics_legal_T_193; // @[Parameters.scala:685:42]
wire _atomics_legal_T_225 = _atomics_legal_T_224 | _atomics_legal_T_198; // @[Parameters.scala:685:42]
wire _atomics_legal_T_226 = _atomics_legal_T_225 | _atomics_legal_T_203; // @[Parameters.scala:685:42]
wire _atomics_legal_T_227 = _atomics_legal_T_226 | _atomics_legal_T_208; // @[Parameters.scala:685:42]
wire _atomics_legal_T_228 = _atomics_legal_T_227 | _atomics_legal_T_213; // @[Parameters.scala:685:42]
wire _atomics_legal_T_229 = _atomics_legal_T_228 | _atomics_legal_T_218; // @[Parameters.scala:685:42]
wire _atomics_legal_T_230 = _atomics_legal_T_229 | _atomics_legal_T_223; // @[Parameters.scala:685:42]
wire _atomics_legal_T_231 = _atomics_legal_T_230; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_239 = _atomics_legal_T_231; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_234 = {1'h0, _atomics_legal_T_233}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_235 = _atomics_legal_T_234 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_236 = _atomics_legal_T_235; // @[Parameters.scala:137:46]
wire _atomics_legal_T_237 = _atomics_legal_T_236 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_3 = _atomics_legal_T_239; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10]
wire [7:0] atomics_a_3_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_3 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_24 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_3 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_24 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_25 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_3 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_25 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_26 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_3 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_26 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_27 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_3 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_27 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_28 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_3 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_28 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_29 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_3 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_29 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_30 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_3 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_30 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_31 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_3 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_31 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10]
assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_245 = {1'h0, _atomics_legal_T_244}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_246 = _atomics_legal_T_245 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_247 = _atomics_legal_T_246; // @[Parameters.scala:137:46]
wire _atomics_legal_T_248 = _atomics_legal_T_247 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_250 = {1'h0, _atomics_legal_T_249}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_251 = _atomics_legal_T_250 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_252 = _atomics_legal_T_251; // @[Parameters.scala:137:46]
wire _atomics_legal_T_253 = _atomics_legal_T_252 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_255 = {1'h0, _atomics_legal_T_254}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_256 = _atomics_legal_T_255 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_257 = _atomics_legal_T_256; // @[Parameters.scala:137:46]
wire _atomics_legal_T_258 = _atomics_legal_T_257 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_260 = {1'h0, _atomics_legal_T_259}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_261 = _atomics_legal_T_260 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_262 = _atomics_legal_T_261; // @[Parameters.scala:137:46]
wire _atomics_legal_T_263 = _atomics_legal_T_262 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_265 = {1'h0, _atomics_legal_T_264}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_266 = _atomics_legal_T_265 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_267 = _atomics_legal_T_266; // @[Parameters.scala:137:46]
wire _atomics_legal_T_268 = _atomics_legal_T_267 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_270 = {1'h0, _atomics_legal_T_269}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_271 = _atomics_legal_T_270 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_272 = _atomics_legal_T_271; // @[Parameters.scala:137:46]
wire _atomics_legal_T_273 = _atomics_legal_T_272 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_275 = {1'h0, _atomics_legal_T_274}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_276 = _atomics_legal_T_275 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_277 = _atomics_legal_T_276; // @[Parameters.scala:137:46]
wire _atomics_legal_T_278 = _atomics_legal_T_277 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_280 = {1'h0, _atomics_legal_T_279}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_281 = _atomics_legal_T_280 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_282 = _atomics_legal_T_281; // @[Parameters.scala:137:46]
wire _atomics_legal_T_283 = _atomics_legal_T_282 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_284 = _atomics_legal_T_248 | _atomics_legal_T_253; // @[Parameters.scala:685:42]
wire _atomics_legal_T_285 = _atomics_legal_T_284 | _atomics_legal_T_258; // @[Parameters.scala:685:42]
wire _atomics_legal_T_286 = _atomics_legal_T_285 | _atomics_legal_T_263; // @[Parameters.scala:685:42]
wire _atomics_legal_T_287 = _atomics_legal_T_286 | _atomics_legal_T_268; // @[Parameters.scala:685:42]
wire _atomics_legal_T_288 = _atomics_legal_T_287 | _atomics_legal_T_273; // @[Parameters.scala:685:42]
wire _atomics_legal_T_289 = _atomics_legal_T_288 | _atomics_legal_T_278; // @[Parameters.scala:685:42]
wire _atomics_legal_T_290 = _atomics_legal_T_289 | _atomics_legal_T_283; // @[Parameters.scala:685:42]
wire _atomics_legal_T_291 = _atomics_legal_T_290; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_299 = _atomics_legal_T_291; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_294 = {1'h0, _atomics_legal_T_293}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_295 = _atomics_legal_T_294 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_296 = _atomics_legal_T_295; // @[Parameters.scala:137:46]
wire _atomics_legal_T_297 = _atomics_legal_T_296 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_4 = _atomics_legal_T_299; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10]
wire [7:0] atomics_a_4_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_4 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_4 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_4 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_4 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_4 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_4 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_4 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_4 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_4 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10]
assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_305 = {1'h0, _atomics_legal_T_304}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_306 = _atomics_legal_T_305 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_307 = _atomics_legal_T_306; // @[Parameters.scala:137:46]
wire _atomics_legal_T_308 = _atomics_legal_T_307 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_310 = {1'h0, _atomics_legal_T_309}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_311 = _atomics_legal_T_310 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_312 = _atomics_legal_T_311; // @[Parameters.scala:137:46]
wire _atomics_legal_T_313 = _atomics_legal_T_312 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_315 = {1'h0, _atomics_legal_T_314}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_316 = _atomics_legal_T_315 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_317 = _atomics_legal_T_316; // @[Parameters.scala:137:46]
wire _atomics_legal_T_318 = _atomics_legal_T_317 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_320 = {1'h0, _atomics_legal_T_319}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_321 = _atomics_legal_T_320 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_322 = _atomics_legal_T_321; // @[Parameters.scala:137:46]
wire _atomics_legal_T_323 = _atomics_legal_T_322 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_325 = {1'h0, _atomics_legal_T_324}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_326 = _atomics_legal_T_325 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_327 = _atomics_legal_T_326; // @[Parameters.scala:137:46]
wire _atomics_legal_T_328 = _atomics_legal_T_327 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_330 = {1'h0, _atomics_legal_T_329}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_331 = _atomics_legal_T_330 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_332 = _atomics_legal_T_331; // @[Parameters.scala:137:46]
wire _atomics_legal_T_333 = _atomics_legal_T_332 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_335 = {1'h0, _atomics_legal_T_334}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_336 = _atomics_legal_T_335 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_337 = _atomics_legal_T_336; // @[Parameters.scala:137:46]
wire _atomics_legal_T_338 = _atomics_legal_T_337 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_340 = {1'h0, _atomics_legal_T_339}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_341 = _atomics_legal_T_340 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_342 = _atomics_legal_T_341; // @[Parameters.scala:137:46]
wire _atomics_legal_T_343 = _atomics_legal_T_342 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_344 = _atomics_legal_T_308 | _atomics_legal_T_313; // @[Parameters.scala:685:42]
wire _atomics_legal_T_345 = _atomics_legal_T_344 | _atomics_legal_T_318; // @[Parameters.scala:685:42]
wire _atomics_legal_T_346 = _atomics_legal_T_345 | _atomics_legal_T_323; // @[Parameters.scala:685:42]
wire _atomics_legal_T_347 = _atomics_legal_T_346 | _atomics_legal_T_328; // @[Parameters.scala:685:42]
wire _atomics_legal_T_348 = _atomics_legal_T_347 | _atomics_legal_T_333; // @[Parameters.scala:685:42]
wire _atomics_legal_T_349 = _atomics_legal_T_348 | _atomics_legal_T_338; // @[Parameters.scala:685:42]
wire _atomics_legal_T_350 = _atomics_legal_T_349 | _atomics_legal_T_343; // @[Parameters.scala:685:42]
wire _atomics_legal_T_351 = _atomics_legal_T_350; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_359 = _atomics_legal_T_351; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_354 = {1'h0, _atomics_legal_T_353}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_355 = _atomics_legal_T_354 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_356 = _atomics_legal_T_355; // @[Parameters.scala:137:46]
wire _atomics_legal_T_357 = _atomics_legal_T_356 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_5 = _atomics_legal_T_359; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10]
wire [7:0] atomics_a_5_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_5 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_40 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_5 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_40 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_41 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_5 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_41 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_42 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_5 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_42 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_43 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_5 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_43 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_44 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_5 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_44 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_45 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_5 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_45 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_46 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_5 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_46 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_47 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_5 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_47 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10]
assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_365 = {1'h0, _atomics_legal_T_364}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_366 = _atomics_legal_T_365 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_367 = _atomics_legal_T_366; // @[Parameters.scala:137:46]
wire _atomics_legal_T_368 = _atomics_legal_T_367 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_370 = {1'h0, _atomics_legal_T_369}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_371 = _atomics_legal_T_370 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_372 = _atomics_legal_T_371; // @[Parameters.scala:137:46]
wire _atomics_legal_T_373 = _atomics_legal_T_372 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_375 = {1'h0, _atomics_legal_T_374}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_376 = _atomics_legal_T_375 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_377 = _atomics_legal_T_376; // @[Parameters.scala:137:46]
wire _atomics_legal_T_378 = _atomics_legal_T_377 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_380 = {1'h0, _atomics_legal_T_379}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_381 = _atomics_legal_T_380 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_382 = _atomics_legal_T_381; // @[Parameters.scala:137:46]
wire _atomics_legal_T_383 = _atomics_legal_T_382 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_385 = {1'h0, _atomics_legal_T_384}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_386 = _atomics_legal_T_385 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_387 = _atomics_legal_T_386; // @[Parameters.scala:137:46]
wire _atomics_legal_T_388 = _atomics_legal_T_387 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_390 = {1'h0, _atomics_legal_T_389}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_391 = _atomics_legal_T_390 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_392 = _atomics_legal_T_391; // @[Parameters.scala:137:46]
wire _atomics_legal_T_393 = _atomics_legal_T_392 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_395 = {1'h0, _atomics_legal_T_394}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_396 = _atomics_legal_T_395 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_397 = _atomics_legal_T_396; // @[Parameters.scala:137:46]
wire _atomics_legal_T_398 = _atomics_legal_T_397 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_400 = {1'h0, _atomics_legal_T_399}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_401 = _atomics_legal_T_400 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_402 = _atomics_legal_T_401; // @[Parameters.scala:137:46]
wire _atomics_legal_T_403 = _atomics_legal_T_402 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_404 = _atomics_legal_T_368 | _atomics_legal_T_373; // @[Parameters.scala:685:42]
wire _atomics_legal_T_405 = _atomics_legal_T_404 | _atomics_legal_T_378; // @[Parameters.scala:685:42]
wire _atomics_legal_T_406 = _atomics_legal_T_405 | _atomics_legal_T_383; // @[Parameters.scala:685:42]
wire _atomics_legal_T_407 = _atomics_legal_T_406 | _atomics_legal_T_388; // @[Parameters.scala:685:42]
wire _atomics_legal_T_408 = _atomics_legal_T_407 | _atomics_legal_T_393; // @[Parameters.scala:685:42]
wire _atomics_legal_T_409 = _atomics_legal_T_408 | _atomics_legal_T_398; // @[Parameters.scala:685:42]
wire _atomics_legal_T_410 = _atomics_legal_T_409 | _atomics_legal_T_403; // @[Parameters.scala:685:42]
wire _atomics_legal_T_411 = _atomics_legal_T_410; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_419 = _atomics_legal_T_411; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_414 = {1'h0, _atomics_legal_T_413}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_415 = _atomics_legal_T_414 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_416 = _atomics_legal_T_415; // @[Parameters.scala:137:46]
wire _atomics_legal_T_417 = _atomics_legal_T_416 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_6 = _atomics_legal_T_419; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10]
wire [7:0] atomics_a_6_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_6 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_6 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_6 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_6 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_6 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_6 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_6 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_6 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_6 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10]
assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_425 = {1'h0, _atomics_legal_T_424}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_426 = _atomics_legal_T_425 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_427 = _atomics_legal_T_426; // @[Parameters.scala:137:46]
wire _atomics_legal_T_428 = _atomics_legal_T_427 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_430 = {1'h0, _atomics_legal_T_429}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_431 = _atomics_legal_T_430 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_432 = _atomics_legal_T_431; // @[Parameters.scala:137:46]
wire _atomics_legal_T_433 = _atomics_legal_T_432 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_435 = {1'h0, _atomics_legal_T_434}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_436 = _atomics_legal_T_435 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_437 = _atomics_legal_T_436; // @[Parameters.scala:137:46]
wire _atomics_legal_T_438 = _atomics_legal_T_437 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_440 = {1'h0, _atomics_legal_T_439}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_441 = _atomics_legal_T_440 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_442 = _atomics_legal_T_441; // @[Parameters.scala:137:46]
wire _atomics_legal_T_443 = _atomics_legal_T_442 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_445 = {1'h0, _atomics_legal_T_444}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_446 = _atomics_legal_T_445 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_447 = _atomics_legal_T_446; // @[Parameters.scala:137:46]
wire _atomics_legal_T_448 = _atomics_legal_T_447 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_450 = {1'h0, _atomics_legal_T_449}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_451 = _atomics_legal_T_450 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_452 = _atomics_legal_T_451; // @[Parameters.scala:137:46]
wire _atomics_legal_T_453 = _atomics_legal_T_452 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_455 = {1'h0, _atomics_legal_T_454}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_456 = _atomics_legal_T_455 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_457 = _atomics_legal_T_456; // @[Parameters.scala:137:46]
wire _atomics_legal_T_458 = _atomics_legal_T_457 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_460 = {1'h0, _atomics_legal_T_459}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_461 = _atomics_legal_T_460 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_462 = _atomics_legal_T_461; // @[Parameters.scala:137:46]
wire _atomics_legal_T_463 = _atomics_legal_T_462 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_464 = _atomics_legal_T_428 | _atomics_legal_T_433; // @[Parameters.scala:685:42]
wire _atomics_legal_T_465 = _atomics_legal_T_464 | _atomics_legal_T_438; // @[Parameters.scala:685:42]
wire _atomics_legal_T_466 = _atomics_legal_T_465 | _atomics_legal_T_443; // @[Parameters.scala:685:42]
wire _atomics_legal_T_467 = _atomics_legal_T_466 | _atomics_legal_T_448; // @[Parameters.scala:685:42]
wire _atomics_legal_T_468 = _atomics_legal_T_467 | _atomics_legal_T_453; // @[Parameters.scala:685:42]
wire _atomics_legal_T_469 = _atomics_legal_T_468 | _atomics_legal_T_458; // @[Parameters.scala:685:42]
wire _atomics_legal_T_470 = _atomics_legal_T_469 | _atomics_legal_T_463; // @[Parameters.scala:685:42]
wire _atomics_legal_T_471 = _atomics_legal_T_470; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_479 = _atomics_legal_T_471; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_474 = {1'h0, _atomics_legal_T_473}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_475 = _atomics_legal_T_474 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_476 = _atomics_legal_T_475; // @[Parameters.scala:137:46]
wire _atomics_legal_T_477 = _atomics_legal_T_476 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_7 = _atomics_legal_T_479; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10]
wire [7:0] atomics_a_7_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_7 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_56 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_7 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_56 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_57 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_7 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_57 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_58 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_7 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_58 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_59 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_7 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_59 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_60 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_7 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_60 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_61 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_7 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_61 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_62 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_7 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_62 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_63 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_7 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_63 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10]
assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_485 = {1'h0, _atomics_legal_T_484}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_486 = _atomics_legal_T_485 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_487 = _atomics_legal_T_486; // @[Parameters.scala:137:46]
wire _atomics_legal_T_488 = _atomics_legal_T_487 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_490 = {1'h0, _atomics_legal_T_489}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_491 = _atomics_legal_T_490 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_492 = _atomics_legal_T_491; // @[Parameters.scala:137:46]
wire _atomics_legal_T_493 = _atomics_legal_T_492 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_495 = {1'h0, _atomics_legal_T_494}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_496 = _atomics_legal_T_495 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_497 = _atomics_legal_T_496; // @[Parameters.scala:137:46]
wire _atomics_legal_T_498 = _atomics_legal_T_497 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_500 = {1'h0, _atomics_legal_T_499}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_501 = _atomics_legal_T_500 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_502 = _atomics_legal_T_501; // @[Parameters.scala:137:46]
wire _atomics_legal_T_503 = _atomics_legal_T_502 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_505 = {1'h0, _atomics_legal_T_504}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_506 = _atomics_legal_T_505 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_507 = _atomics_legal_T_506; // @[Parameters.scala:137:46]
wire _atomics_legal_T_508 = _atomics_legal_T_507 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_510 = {1'h0, _atomics_legal_T_509}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_511 = _atomics_legal_T_510 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_512 = _atomics_legal_T_511; // @[Parameters.scala:137:46]
wire _atomics_legal_T_513 = _atomics_legal_T_512 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_515 = {1'h0, _atomics_legal_T_514}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_516 = _atomics_legal_T_515 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_517 = _atomics_legal_T_516; // @[Parameters.scala:137:46]
wire _atomics_legal_T_518 = _atomics_legal_T_517 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_520 = {1'h0, _atomics_legal_T_519}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_521 = _atomics_legal_T_520 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_522 = _atomics_legal_T_521; // @[Parameters.scala:137:46]
wire _atomics_legal_T_523 = _atomics_legal_T_522 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_524 = _atomics_legal_T_488 | _atomics_legal_T_493; // @[Parameters.scala:685:42]
wire _atomics_legal_T_525 = _atomics_legal_T_524 | _atomics_legal_T_498; // @[Parameters.scala:685:42]
wire _atomics_legal_T_526 = _atomics_legal_T_525 | _atomics_legal_T_503; // @[Parameters.scala:685:42]
wire _atomics_legal_T_527 = _atomics_legal_T_526 | _atomics_legal_T_508; // @[Parameters.scala:685:42]
wire _atomics_legal_T_528 = _atomics_legal_T_527 | _atomics_legal_T_513; // @[Parameters.scala:685:42]
wire _atomics_legal_T_529 = _atomics_legal_T_528 | _atomics_legal_T_518; // @[Parameters.scala:685:42]
wire _atomics_legal_T_530 = _atomics_legal_T_529 | _atomics_legal_T_523; // @[Parameters.scala:685:42]
wire _atomics_legal_T_531 = _atomics_legal_T_530; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_539 = _atomics_legal_T_531; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_534 = {1'h0, _atomics_legal_T_533}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_535 = _atomics_legal_T_534 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_536 = _atomics_legal_T_535; // @[Parameters.scala:137:46]
wire _atomics_legal_T_537 = _atomics_legal_T_536 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_8 = _atomics_legal_T_539; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10]
wire [7:0] atomics_a_8_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_8 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_8 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_8 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_8 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_8 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_8 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_8 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_8 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_8 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10]
assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10]
wire [2:0] _GEN_95 = _atomics_T ? 3'h3 : 3'h0; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_1_opcode; // @[DCache.scala:587:81]
assign _atomics_T_1_opcode = _GEN_95; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_1_param; // @[DCache.scala:587:81]
assign _atomics_T_1_param = _GEN_95; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17]
wire _atomics_T_1_source = _atomics_T & atomics_a_source; // @[Edges.scala:534:17]
wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 8'h0; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 64'h0; // @[Edges.scala:534:17]
wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17]
wire _atomics_T_3_source = _atomics_T_2 ? atomics_a_1_source : _atomics_T_1_source; // @[Edges.scala:534:17]
wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17]
wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17]
wire _atomics_T_5_source = _atomics_T_4 ? atomics_a_2_source : _atomics_T_3_source; // @[Edges.scala:534:17]
wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17]
wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17]
wire _atomics_T_7_source = _atomics_T_6 ? atomics_a_3_source : _atomics_T_5_source; // @[Edges.scala:534:17]
wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17]
wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17]
wire _atomics_T_9_source = _atomics_T_8 ? atomics_a_4_source : _atomics_T_7_source; // @[Edges.scala:517:17]
wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17]
wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17]
wire _atomics_T_11_source = _atomics_T_10 ? atomics_a_5_source : _atomics_T_9_source; // @[Edges.scala:517:17]
wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17]
wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17]
wire _atomics_T_13_source = _atomics_T_12 ? atomics_a_6_source : _atomics_T_11_source; // @[Edges.scala:517:17]
wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17]
wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17]
wire _atomics_T_15_source = _atomics_T_14 ? atomics_a_7_source : _atomics_T_13_source; // @[Edges.scala:517:17]
wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17]
wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[DCache.scala:587:81]
wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[DCache.scala:587:81]
wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17]
wire atomics_source = _atomics_T_16 ? atomics_a_8_source : _atomics_T_15_source; // @[Edges.scala:517:17]
wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17]
wire [7:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17]
wire [63:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17]
wire [39:0] _tl_out_a_valid_T_1 = {s2_req_addr[39:32], s2_req_addr[31:0] ^ release_ack_addr}; // @[DCache.scala:227:29, :339:19, :606:43]
wire [14:0] _tl_out_a_valid_T_2 = _tl_out_a_valid_T_1[20:6]; // @[DCache.scala:606:{43,62}]
wire _tl_out_a_valid_T_3 = _tl_out_a_valid_T_2 == 15'h0; // @[DCache.scala:582:29, :606:{62,118}]
wire _tl_out_a_valid_T_4 = release_ack_wait & _tl_out_a_valid_T_3; // @[DCache.scala:226:33, :606:{27,118}]
wire _tl_out_a_valid_T_5 = ~_tl_out_a_valid_T_4; // @[DCache.scala:606:{8,27}]
wire _tl_out_a_valid_T_6 = s2_valid_cached_miss & _tl_out_a_valid_T_5; // @[DCache.scala:425:60, :605:29, :606:8]
wire _tl_out_a_valid_T_7 = ~release_ack_wait; // @[DCache.scala:226:33, :607:47]
wire _tl_out_a_valid_T_10 = ~s2_victim_dirty; // @[Misc.scala:38:9]
wire _tl_out_a_valid_T_11 = _tl_out_a_valid_T_10; // @[DCache.scala:607:{88,91}]
wire _tl_out_a_valid_T_12 = _tl_out_a_valid_T_6 & _tl_out_a_valid_T_11; // @[DCache.scala:605:29, :606:127, :607:88]
wire _tl_out_a_valid_T_13 = s2_valid_uncached_pending | _tl_out_a_valid_T_12; // @[DCache.scala:430:64, :604:32, :606:127]
assign _tl_out_a_valid_T_14 = _tl_out_a_valid_T_13; // @[DCache.scala:603:37, :604:32]
assign tl_out_a_valid = _tl_out_a_valid_T_14; // @[DCache.scala:159:22, :603:37]
wire _tl_out_a_bits_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47, :608:24]
wire [39:0] _tl_out_a_bits_T_2 = {_tl_out_a_bits_T_1, 6'h0}; // @[DCache.scala:1210:{39,60}]
wire [39:0] _tl_out_a_bits_legal_T_1 = _tl_out_a_bits_T_2; // @[DCache.scala:1210:60]
wire [40:0] _tl_out_a_bits_legal_T_2 = {1'h0, _tl_out_a_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _tl_out_a_bits_legal_T_3 = _tl_out_a_bits_legal_T_2 & 41'h8C020000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _tl_out_a_bits_legal_T_4 = _tl_out_a_bits_legal_T_3; // @[Parameters.scala:137:46]
wire _tl_out_a_bits_legal_T_5 = _tl_out_a_bits_legal_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _tl_out_a_bits_legal_T_6 = {_tl_out_a_bits_T_2[39:17], _tl_out_a_bits_T_2[16:0] ^ 17'h10000}; // @[DCache.scala:1210:60]
wire [40:0] _tl_out_a_bits_legal_T_7 = {1'h0, _tl_out_a_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _tl_out_a_bits_legal_T_8 = _tl_out_a_bits_legal_T_7 & 41'h8C031000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _tl_out_a_bits_legal_T_9 = _tl_out_a_bits_legal_T_8; // @[Parameters.scala:137:46]
wire _tl_out_a_bits_legal_T_10 = _tl_out_a_bits_legal_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _tl_out_a_bits_legal_T_11 = {_tl_out_a_bits_T_2[39:18], _tl_out_a_bits_T_2[17:0] ^ 18'h20000}; // @[DCache.scala:1210:60]
wire [40:0] _tl_out_a_bits_legal_T_12 = {1'h0, _tl_out_a_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _tl_out_a_bits_legal_T_13 = _tl_out_a_bits_legal_T_12 & 41'h8C030000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _tl_out_a_bits_legal_T_14 = _tl_out_a_bits_legal_T_13; // @[Parameters.scala:137:46]
wire _tl_out_a_bits_legal_T_15 = _tl_out_a_bits_legal_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _tl_out_a_bits_legal_T_16 = {_tl_out_a_bits_T_2[39:28], _tl_out_a_bits_T_2[27:0] ^ 28'hC000000}; // @[DCache.scala:1210:60]
wire [40:0] _tl_out_a_bits_legal_T_17 = {1'h0, _tl_out_a_bits_legal_T_16}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _tl_out_a_bits_legal_T_18 = _tl_out_a_bits_legal_T_17 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _tl_out_a_bits_legal_T_19 = _tl_out_a_bits_legal_T_18; // @[Parameters.scala:137:46]
wire _tl_out_a_bits_legal_T_20 = _tl_out_a_bits_legal_T_19 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _tl_out_a_bits_legal_T_21 = _tl_out_a_bits_legal_T_5 | _tl_out_a_bits_legal_T_10; // @[Parameters.scala:685:42]
wire _tl_out_a_bits_legal_T_22 = _tl_out_a_bits_legal_T_21 | _tl_out_a_bits_legal_T_15; // @[Parameters.scala:685:42]
wire _tl_out_a_bits_legal_T_23 = _tl_out_a_bits_legal_T_22 | _tl_out_a_bits_legal_T_20; // @[Parameters.scala:685:42]
wire [39:0] _tl_out_a_bits_legal_T_27 = {_tl_out_a_bits_T_2[39:28], _tl_out_a_bits_T_2[27:0] ^ 28'h8000000}; // @[DCache.scala:1210:60]
wire [40:0] _tl_out_a_bits_legal_T_28 = {1'h0, _tl_out_a_bits_legal_T_27}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _tl_out_a_bits_legal_T_29 = _tl_out_a_bits_legal_T_28 & 41'h8C030000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _tl_out_a_bits_legal_T_30 = _tl_out_a_bits_legal_T_29; // @[Parameters.scala:137:46]
wire _tl_out_a_bits_legal_T_31 = _tl_out_a_bits_legal_T_30 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] tl_out_a_bits_a_address = _tl_out_a_bits_T_2[31:0]; // @[Edges.scala:346:17]
wire [39:0] _tl_out_a_bits_legal_T_32 = {_tl_out_a_bits_T_2[39:32], tl_out_a_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17]
wire [40:0] _tl_out_a_bits_legal_T_33 = {1'h0, _tl_out_a_bits_legal_T_32}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _tl_out_a_bits_legal_T_34 = _tl_out_a_bits_legal_T_33 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _tl_out_a_bits_legal_T_35 = _tl_out_a_bits_legal_T_34; // @[Parameters.scala:137:46]
wire _tl_out_a_bits_legal_T_36 = _tl_out_a_bits_legal_T_35 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _tl_out_a_bits_legal_T_37 = _tl_out_a_bits_legal_T_31 | _tl_out_a_bits_legal_T_36; // @[Parameters.scala:685:42]
wire _tl_out_a_bits_legal_T_38 = _tl_out_a_bits_legal_T_37; // @[Parameters.scala:684:54, :685:42]
wire tl_out_a_bits_legal = _tl_out_a_bits_legal_T_38; // @[Parameters.scala:684:54, :686:26]
wire [2:0] tl_out_a_bits_a_param; // @[Edges.scala:346:17]
assign tl_out_a_bits_a_param = {1'h0, s2_grow_param}; // @[Misc.scala:35:36]
wire tl_out_a_bits_a_mask_sub_sub_bit = _tl_out_a_bits_T_2[2]; // @[Misc.scala:210:26]
wire tl_out_a_bits_a_mask_sub_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire tl_out_a_bits_a_mask_sub_sub_nbit = ~tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire tl_out_a_bits_a_mask_sub_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _tl_out_a_bits_a_mask_sub_sub_acc_T = tl_out_a_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire _tl_out_a_bits_a_mask_sub_sub_acc_T_1 = tl_out_a_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire tl_out_a_bits_a_mask_sub_bit = _tl_out_a_bits_T_2[1]; // @[Misc.scala:210:26]
wire tl_out_a_bits_a_mask_sub_nbit = ~tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire tl_out_a_bits_a_mask_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire tl_out_a_bits_a_mask_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire tl_out_a_bits_a_mask_sub_2_2 = tl_out_a_bits_a_mask_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire tl_out_a_bits_a_mask_sub_3_2 = tl_out_a_bits_a_mask_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire tl_out_a_bits_a_mask_bit = _tl_out_a_bits_T_2[0]; // @[Misc.scala:210:26]
wire tl_out_a_bits_a_mask_nbit = ~tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire tl_out_a_bits_a_mask_eq = tl_out_a_bits_a_mask_sub_0_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _tl_out_a_bits_a_mask_acc_T = tl_out_a_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38]
wire tl_out_a_bits_a_mask_eq_1 = tl_out_a_bits_a_mask_sub_0_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _tl_out_a_bits_a_mask_acc_T_1 = tl_out_a_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire tl_out_a_bits_a_mask_eq_2 = tl_out_a_bits_a_mask_sub_1_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _tl_out_a_bits_a_mask_acc_T_2 = tl_out_a_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire tl_out_a_bits_a_mask_eq_3 = tl_out_a_bits_a_mask_sub_1_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _tl_out_a_bits_a_mask_acc_T_3 = tl_out_a_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire tl_out_a_bits_a_mask_eq_4 = tl_out_a_bits_a_mask_sub_2_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _tl_out_a_bits_a_mask_acc_T_4 = tl_out_a_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire tl_out_a_bits_a_mask_eq_5 = tl_out_a_bits_a_mask_sub_2_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _tl_out_a_bits_a_mask_acc_T_5 = tl_out_a_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire tl_out_a_bits_a_mask_eq_6 = tl_out_a_bits_a_mask_sub_3_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _tl_out_a_bits_a_mask_acc_T_6 = tl_out_a_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire tl_out_a_bits_a_mask_eq_7 = tl_out_a_bits_a_mask_sub_3_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _tl_out_a_bits_a_mask_acc_T_7 = tl_out_a_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38]
wire _tl_out_a_bits_T_3 = ~s2_write; // @[DCache.scala:609:9]
wire _tl_out_a_bits_T_5 = ~s2_read; // @[DCache.scala:611:9]
wire [2:0] _tl_out_a_bits_T_6_opcode = _tl_out_a_bits_T_5 ? 3'h0 : atomics_opcode; // @[DCache.scala:587:81, :611:{8,9}]
wire [2:0] _tl_out_a_bits_T_6_param = _tl_out_a_bits_T_5 ? 3'h0 : atomics_param; // @[DCache.scala:587:81, :611:{8,9}]
wire [3:0] _tl_out_a_bits_T_6_size = _tl_out_a_bits_T_5 ? put_size : atomics_size; // @[Edges.scala:480:17]
wire _tl_out_a_bits_T_6_source = _tl_out_a_bits_T_5 ? put_source : atomics_source; // @[Edges.scala:480:17]
wire [31:0] _tl_out_a_bits_T_6_address = _tl_out_a_bits_T_5 ? put_address : atomics_address; // @[Edges.scala:480:17]
wire [7:0] _tl_out_a_bits_T_6_mask = _tl_out_a_bits_T_5 ? put_mask : atomics_mask; // @[Edges.scala:480:17]
wire [63:0] _tl_out_a_bits_T_6_data = _tl_out_a_bits_T_5 ? put_data : atomics_data; // @[Edges.scala:480:17]
wire [2:0] _tl_out_a_bits_T_7_opcode = _tl_out_a_bits_T_4 ? 3'h1 : _tl_out_a_bits_T_6_opcode; // @[DCache.scala:610:{8,20}, :611:8]
wire [2:0] _tl_out_a_bits_T_7_param = _tl_out_a_bits_T_4 ? 3'h0 : _tl_out_a_bits_T_6_param; // @[DCache.scala:610:{8,20}, :611:8]
wire [3:0] _tl_out_a_bits_T_7_size = _tl_out_a_bits_T_4 ? putpartial_size : _tl_out_a_bits_T_6_size; // @[Edges.scala:500:17]
wire _tl_out_a_bits_T_7_source = _tl_out_a_bits_T_4 ? putpartial_source : _tl_out_a_bits_T_6_source; // @[Edges.scala:500:17]
wire [31:0] _tl_out_a_bits_T_7_address = _tl_out_a_bits_T_4 ? putpartial_address : _tl_out_a_bits_T_6_address; // @[Edges.scala:500:17]
wire [7:0] _tl_out_a_bits_T_7_mask = _tl_out_a_bits_T_4 ? putpartial_mask : _tl_out_a_bits_T_6_mask; // @[Edges.scala:500:17]
wire [63:0] _tl_out_a_bits_T_7_data = _tl_out_a_bits_T_4 ? putpartial_data : _tl_out_a_bits_T_6_data; // @[Edges.scala:500:17]
wire [2:0] _tl_out_a_bits_T_8_opcode = _tl_out_a_bits_T_3 ? 3'h4 : _tl_out_a_bits_T_7_opcode; // @[DCache.scala:609:{8,9}, :610:8]
wire [2:0] _tl_out_a_bits_T_8_param = _tl_out_a_bits_T_3 ? 3'h0 : _tl_out_a_bits_T_7_param; // @[DCache.scala:609:{8,9}, :610:8]
wire [3:0] _tl_out_a_bits_T_8_size = _tl_out_a_bits_T_3 ? get_size : _tl_out_a_bits_T_7_size; // @[Edges.scala:460:17]
wire _tl_out_a_bits_T_8_source = _tl_out_a_bits_T_3 ? get_source : _tl_out_a_bits_T_7_source; // @[Edges.scala:460:17]
wire [31:0] _tl_out_a_bits_T_8_address = _tl_out_a_bits_T_3 ? get_address : _tl_out_a_bits_T_7_address; // @[Edges.scala:460:17]
wire [7:0] _tl_out_a_bits_T_8_mask = _tl_out_a_bits_T_3 ? get_mask : _tl_out_a_bits_T_7_mask; // @[Edges.scala:460:17]
wire [63:0] _tl_out_a_bits_T_8_data = _tl_out_a_bits_T_3 ? 64'h0 : _tl_out_a_bits_T_7_data; // @[DCache.scala:609:{8,9}, :610:8]
assign _tl_out_a_bits_T_9_opcode = _tl_out_a_bits_T ? 3'h6 : _tl_out_a_bits_T_8_opcode; // @[DCache.scala:608:{23,24}, :609:8]
assign _tl_out_a_bits_T_9_param = _tl_out_a_bits_T ? tl_out_a_bits_a_param : _tl_out_a_bits_T_8_param; // @[Edges.scala:346:17]
assign _tl_out_a_bits_T_9_size = _tl_out_a_bits_T ? 4'h6 : _tl_out_a_bits_T_8_size; // @[DCache.scala:608:{23,24}, :609:8]
assign _tl_out_a_bits_T_9_source = ~_tl_out_a_bits_T & _tl_out_a_bits_T_8_source; // @[DCache.scala:608:{23,24}, :609:8]
assign _tl_out_a_bits_T_9_address = _tl_out_a_bits_T ? tl_out_a_bits_a_address : _tl_out_a_bits_T_8_address; // @[Edges.scala:346:17]
assign _tl_out_a_bits_T_9_mask = _tl_out_a_bits_T ? 8'hFF : _tl_out_a_bits_T_8_mask; // @[DCache.scala:608:{23,24}, :609:8]
assign _tl_out_a_bits_T_9_data = _tl_out_a_bits_T ? 64'h0 : _tl_out_a_bits_T_8_data; // @[DCache.scala:608:{23,24}, :609:8]
assign tl_out_a_bits_opcode = _tl_out_a_bits_T_9_opcode; // @[DCache.scala:159:22, :608:23]
assign tl_out_a_bits_param = _tl_out_a_bits_T_9_param; // @[DCache.scala:159:22, :608:23]
assign tl_out_a_bits_size = _tl_out_a_bits_T_9_size; // @[DCache.scala:159:22, :608:23]
assign tl_out_a_bits_source = _tl_out_a_bits_T_9_source; // @[DCache.scala:159:22, :608:23]
assign tl_out_a_bits_address = _tl_out_a_bits_T_9_address; // @[DCache.scala:159:22, :608:23]
assign tl_out_a_bits_mask = _tl_out_a_bits_T_9_mask; // @[DCache.scala:159:22, :608:23]
assign tl_out_a_bits_data = _tl_out_a_bits_T_9_data; // @[DCache.scala:159:22, :608:23]
wire [1:0] _a_sel_T = 2'h1 << a_sel_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [1:0] _a_sel_T_1 = _a_sel_T; // @[OneHot.scala:65:{12,27}]
wire a_sel = _a_sel_T_1[1]; // @[OneHot.scala:65:27]
wire _io_cpu_perf_acquire_T = tl_out_a_ready & tl_out_a_valid; // @[Decoupled.scala:51:35]
wire [4:0] _uncachedReqs_0_cmd_T_1 = {_uncachedReqs_0_cmd_T, 4'h1}; // @[DCache.scala:637:{37,49}]
wire [4:0] _uncachedReqs_0_cmd_T_2 = s2_write ? _uncachedReqs_0_cmd_T_1 : 5'h0; // @[DCache.scala:637:{23,37}]
wire _T_82 = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35]
wire _io_cpu_replay_next_T; // @[Decoupled.scala:51:35]
assign _io_cpu_replay_next_T = _T_82; // @[Decoupled.scala:51:35]
wire _io_cpu_perf_blocked_near_end_of_refill_T; // @[Decoupled.scala:51:35]
assign _io_cpu_perf_blocked_near_end_of_refill_T = _T_82; // @[Decoupled.scala:51:35]
wire _io_errors_bus_valid_T; // @[Decoupled.scala:51:35]
assign _io_errors_bus_valid_T = _T_82; // @[Decoupled.scala:51:35]
wire [26:0] _r_beats1_decode_T = 27'hFFF << nodeOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire r_beats1_opdata = nodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] r_counter; // @[Edges.scala:229:27]
wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_done = d_last & _T_82; // @[Decoupled.scala:51:35]
wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _r_counter_T = d_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] d_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29]
wire grantIsUncachedData = nodeOut_d_bits_opcode == 3'h1; // @[package.scala:16:47]
wire grantIsUncached = grantIsUncachedData | nodeOut_d_bits_opcode == 3'h0 | nodeOut_d_bits_opcode == 3'h2; // @[package.scala:16:47, :81:59]
wire _tl_d_data_encoded_T_11 = ~grantIsUncached; // @[package.scala:81:59]
wire _tl_d_data_encoded_T_12 = _tl_d_data_encoded_T_10 & _tl_d_data_encoded_T_11; // @[DCache.scala:663:{77,126,129}]
wire [15:0] tl_d_data_encoded_lo_lo_1 = {_tl_d_data_encoded_T_14, _tl_d_data_encoded_T_13}; // @[package.scala:45:27, :211:50]
wire [15:0] tl_d_data_encoded_lo_hi_1 = {_tl_d_data_encoded_T_16, _tl_d_data_encoded_T_15}; // @[package.scala:45:27, :211:50]
wire [31:0] tl_d_data_encoded_lo_1 = {tl_d_data_encoded_lo_hi_1, tl_d_data_encoded_lo_lo_1}; // @[package.scala:45:27]
wire [15:0] tl_d_data_encoded_hi_lo_1 = {_tl_d_data_encoded_T_18, _tl_d_data_encoded_T_17}; // @[package.scala:45:27, :211:50]
wire [15:0] tl_d_data_encoded_hi_hi_1 = {_tl_d_data_encoded_T_20, _tl_d_data_encoded_T_19}; // @[package.scala:45:27, :211:50]
wire [31:0] tl_d_data_encoded_hi_1 = {tl_d_data_encoded_hi_hi_1, tl_d_data_encoded_hi_lo_1}; // @[package.scala:45:27]
assign _tl_d_data_encoded_T_21 = {tl_d_data_encoded_hi_1, tl_d_data_encoded_lo_1}; // @[package.scala:45:27]
assign tl_d_data_encoded = _tl_d_data_encoded_T_21; // @[package.scala:45:27]
wire _grantIsCached_T = nodeOut_d_bits_opcode == 3'h4; // @[package.scala:16:47]
wire _GEN_96 = nodeOut_d_bits_opcode == 3'h5; // @[package.scala:16:47]
wire _grantIsCached_T_1; // @[package.scala:16:47]
assign _grantIsCached_T_1 = _GEN_96; // @[package.scala:16:47]
wire grantIsRefill; // @[DCache.scala:666:29]
assign grantIsRefill = _GEN_96; // @[package.scala:16:47]
wire grantIsCached = _grantIsCached_T | _grantIsCached_T_1; // @[package.scala:16:47, :81:59]
wire grantIsVoluntary = nodeOut_d_bits_opcode == 3'h6; // @[DCache.scala:665:32]
reg grantInProgress; // @[DCache.scala:667:32]
reg [2:0] blockProbeAfterGrantCount; // @[DCache.scala:668:42]
wire [3:0] _blockProbeAfterGrantCount_T = {1'h0, blockProbeAfterGrantCount} - 4'h1; // @[DCache.scala:668:42, :669:99]
wire [2:0] _blockProbeAfterGrantCount_T_1 = _blockProbeAfterGrantCount_T[2:0]; // @[DCache.scala:669:99]
wire _T_107 = release_state == 4'h6; // @[package.scala:16:47]
wire _canAcceptCachedGrant_T_1; // @[package.scala:16:47]
assign _canAcceptCachedGrant_T_1 = _T_107; // @[package.scala:16:47]
wire _metaArb_io_in_4_valid_T; // @[package.scala:16:47]
assign _metaArb_io_in_4_valid_T = _T_107; // @[package.scala:16:47]
wire _T_111 = release_state == 4'h9; // @[package.scala:16:47]
wire _canAcceptCachedGrant_T_2; // @[package.scala:16:47]
assign _canAcceptCachedGrant_T_2 = _T_111; // @[package.scala:16:47]
wire _nodeOut_c_valid_T_1; // @[DCache.scala:810:91]
assign _nodeOut_c_valid_T_1 = _T_111; // @[package.scala:16:47]
wire _canAcceptCachedGrant_T_3 = _canAcceptCachedGrant_T | _canAcceptCachedGrant_T_1; // @[package.scala:16:47, :81:59]
wire _canAcceptCachedGrant_T_4 = _canAcceptCachedGrant_T_3 | _canAcceptCachedGrant_T_2; // @[package.scala:16:47, :81:59]
wire canAcceptCachedGrant = ~_canAcceptCachedGrant_T_4; // @[package.scala:81:59]
wire _nodeOut_d_ready_T = ~d_first; // @[Edges.scala:231:25]
wire _nodeOut_d_ready_T_1 = _nodeOut_d_ready_T | nodeOut_e_ready; // @[DCache.scala:671:{41,50}]
wire _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T_1 & canAcceptCachedGrant; // @[DCache.scala:670:30, :671:{50,69}]
wire _nodeOut_d_ready_T_3 = ~grantIsCached | _nodeOut_d_ready_T_2; // @[package.scala:81:59]
wire [1:0] _uncachedRespIdxOH_T = 2'h1 << uncachedRespIdxOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [1:0] _uncachedRespIdxOH_T_1 = _uncachedRespIdxOH_T; // @[OneHot.scala:65:{12,27}]
wire uncachedRespIdxOH = _uncachedRespIdxOH_T_1[1]; // @[OneHot.scala:65:27]
wire _uncachedResp_T = uncachedRespIdxOH; // @[Mux.scala:32:36]
wire _GEN_97 = _T_82 & grantIsCached; // @[Decoupled.scala:51:35]
assign replace = _GEN_97 & d_last; // @[Replacement.scala:37:29, :38:11]
wire _T_74 = uncachedRespIdxOH & d_last; // @[Edges.scala:232:33]
assign s1_data_way = ~_T_82 | grantIsCached | ~(grantIsUncached & grantIsUncachedData) ? {1'h0, _s1_data_way_T} : 5'h10; // @[Decoupled.scala:51:35]
wire [28:0] _s2_req_addr_dontCareBits_T = s1_paddr[31:3]; // @[DCache.scala:298:21, :701:41]
wire [31:0] s2_req_addr_dontCareBits = {_s2_req_addr_dontCareBits_T, 3'h0}; // @[DCache.scala:701:{41,55}]
wire [2:0] _s2_req_addr_T = uncachedResp_addr[2:0]; // @[DCache.scala:238:30, :702:45]
wire [31:0] _s2_req_addr_T_1 = {s2_req_addr_dontCareBits[31:3], s2_req_addr_dontCareBits[2:0] | _s2_req_addr_T}; // @[DCache.scala:701:55, :702:{26,45}]
wire _nodeOut_e_valid_T = nodeOut_d_valid & d_first; // @[Edges.scala:231:25]
wire _nodeOut_e_valid_T_1 = _nodeOut_e_valid_T & grantIsCached; // @[package.scala:81:59]
wire _nodeOut_e_valid_T_2 = _nodeOut_e_valid_T_1 & canAcceptCachedGrant; // @[DCache.scala:670:30, :714:{47,64}]
assign nodeOut_e_bits_sink = nodeOut_e_bits_e_sink; // @[Edges.scala:451:17]
wire _dataArb_io_in_1_valid_T = nodeOut_d_valid & grantIsRefill; // @[DCache.scala:666:29, :721:44]
wire _dataArb_io_in_1_valid_T_1 = _dataArb_io_in_1_valid_T & canAcceptCachedGrant; // @[DCache.scala:670:30, :721:{44,61}]
wire _T_90 = grantIsRefill & ~dataArb_io_in_1_ready; // @[DCache.scala:152:28, :666:29, :722:{23,26}]
assign nodeOut_e_valid = ~_T_90 & _nodeOut_e_valid_T_2; // @[DCache.scala:714:{18,64}, :722:{23,51}, :723:20]
wire [33:0] _dataArb_io_in_1_bits_addr_T = s2_vaddr[39:6]; // @[DCache.scala:351:21, :728:46]
wire [39:0] _dataArb_io_in_1_bits_addr_T_1 = {_dataArb_io_in_1_bits_addr_T, 6'h0}; // @[DCache.scala:728:{46,57}]
wire [39:0] _dataArb_io_in_1_bits_addr_T_2 = {_dataArb_io_in_1_bits_addr_T_1[39:12], _dataArb_io_in_1_bits_addr_T_1[11:0] | d_address_inc}; // @[Edges.scala:269:29]
assign dataArb_io_in_1_bits_addr = _dataArb_io_in_1_bits_addr_T_2[7:0]; // @[DCache.scala:152:28, :728:{32,67}]
wire _metaArb_io_in_3_valid_T = grantIsCached & d_done; // @[package.scala:81:59]
wire _metaArb_io_in_3_valid_T_1 = ~nodeOut_d_bits_denied; // @[DCache.scala:741:56]
assign _metaArb_io_in_3_valid_T_2 = _metaArb_io_in_3_valid_T & _metaArb_io_in_3_valid_T_1; // @[DCache.scala:741:{43,53,56}]
assign metaArb_io_in_3_valid = _metaArb_io_in_3_valid_T_2; // @[DCache.scala:135:28, :741:53]
assign metaArb_io_in_3_bits_idx = _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:135:28, :744:40]
assign _metaArb_io_in_3_bits_addr_T_2 = {_metaArb_io_in_3_bits_addr_T, _metaArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:745:{36,58,80}]
assign metaArb_io_in_3_bits_addr = _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:135:28, :745:36]
wire _metaArb_io_in_3_bits_data_c_cat_T_2 = _metaArb_io_in_3_bits_data_c_cat_T | _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _metaArb_io_in_3_bits_data_c_cat_T_4 = _metaArb_io_in_3_bits_data_c_cat_T_2 | _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _metaArb_io_in_3_bits_data_c_cat_T_9 = _metaArb_io_in_3_bits_data_c_cat_T_5 | _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_10 = _metaArb_io_in_3_bits_data_c_cat_T_9 | _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_11 = _metaArb_io_in_3_bits_data_c_cat_T_10 | _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_17 = _metaArb_io_in_3_bits_data_c_cat_T_12 | _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_18 = _metaArb_io_in_3_bits_data_c_cat_T_17 | _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_19 = _metaArb_io_in_3_bits_data_c_cat_T_18 | _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_20 = _metaArb_io_in_3_bits_data_c_cat_T_19 | _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_21 = _metaArb_io_in_3_bits_data_c_cat_T_11 | _metaArb_io_in_3_bits_data_c_cat_T_20; // @[package.scala:81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_22 = _metaArb_io_in_3_bits_data_c_cat_T_4 | _metaArb_io_in_3_bits_data_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _metaArb_io_in_3_bits_data_c_cat_T_25 = _metaArb_io_in_3_bits_data_c_cat_T_23 | _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _metaArb_io_in_3_bits_data_c_cat_T_27 = _metaArb_io_in_3_bits_data_c_cat_T_25 | _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _metaArb_io_in_3_bits_data_c_cat_T_32 = _metaArb_io_in_3_bits_data_c_cat_T_28 | _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_33 = _metaArb_io_in_3_bits_data_c_cat_T_32 | _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_34 = _metaArb_io_in_3_bits_data_c_cat_T_33 | _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_40 = _metaArb_io_in_3_bits_data_c_cat_T_35 | _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_41 = _metaArb_io_in_3_bits_data_c_cat_T_40 | _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_42 = _metaArb_io_in_3_bits_data_c_cat_T_41 | _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_43 = _metaArb_io_in_3_bits_data_c_cat_T_42 | _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_44 = _metaArb_io_in_3_bits_data_c_cat_T_34 | _metaArb_io_in_3_bits_data_c_cat_T_43; // @[package.scala:81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_45 = _metaArb_io_in_3_bits_data_c_cat_T_27 | _metaArb_io_in_3_bits_data_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _metaArb_io_in_3_bits_data_c_cat_T_47 = _metaArb_io_in_3_bits_data_c_cat_T_45 | _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _metaArb_io_in_3_bits_data_c_cat_T_49 = _metaArb_io_in_3_bits_data_c_cat_T_47 | _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] metaArb_io_in_3_bits_data_c = {_metaArb_io_in_3_bits_data_c_cat_T_22, _metaArb_io_in_3_bits_data_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _metaArb_io_in_3_bits_data_T_1 = {metaArb_io_in_3_bits_data_c, nodeOut_d_bits_param}; // @[Metadata.scala:29:18, :84:18]
wire _metaArb_io_in_3_bits_data_T_10 = _metaArb_io_in_3_bits_data_T_1 == 4'h1; // @[Metadata.scala:84:{18,38}]
wire [1:0] _metaArb_io_in_3_bits_data_T_11 = {1'h0, _metaArb_io_in_3_bits_data_T_10}; // @[Metadata.scala:84:38]
wire _metaArb_io_in_3_bits_data_T_12 = _metaArb_io_in_3_bits_data_T_1 == 4'h0; // @[Metadata.scala:84:{18,38}]
wire [1:0] _metaArb_io_in_3_bits_data_T_13 = _metaArb_io_in_3_bits_data_T_12 ? 2'h2 : _metaArb_io_in_3_bits_data_T_11; // @[Metadata.scala:84:38]
wire _metaArb_io_in_3_bits_data_T_14 = _metaArb_io_in_3_bits_data_T_1 == 4'h4; // @[Metadata.scala:84:{18,38}]
wire [1:0] _metaArb_io_in_3_bits_data_T_15 = _metaArb_io_in_3_bits_data_T_14 ? 2'h2 : _metaArb_io_in_3_bits_data_T_13; // @[Metadata.scala:84:38]
wire _metaArb_io_in_3_bits_data_T_16 = _metaArb_io_in_3_bits_data_T_1 == 4'hC; // @[Metadata.scala:84:{18,38}]
wire [1:0] _metaArb_io_in_3_bits_data_T_17 = _metaArb_io_in_3_bits_data_T_16 ? 2'h3 : _metaArb_io_in_3_bits_data_T_15; // @[Metadata.scala:84:38]
wire [1:0] metaArb_io_in_3_bits_data_meta_state = _metaArb_io_in_3_bits_data_T_17; // @[Metadata.scala:84:38, :160:20]
wire [1:0] metaArb_io_in_3_bits_data_meta_1_coh_state = metaArb_io_in_3_bits_data_meta_state; // @[Metadata.scala:160:20]
wire [23:0] metaArb_io_in_3_bits_data_meta_1_tag; // @[HellaCache.scala:305:20]
assign metaArb_io_in_3_bits_data_meta_1_tag = _metaArb_io_in_3_bits_data_T[23:0]; // @[HellaCache.scala:305:20, :306:14]
assign _metaArb_io_in_3_bits_data_T_18 = {metaArb_io_in_3_bits_data_meta_1_coh_state, metaArb_io_in_3_bits_data_meta_1_tag}; // @[HellaCache.scala:305:20]
assign metaArb_io_in_3_bits_data = _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:135:28, :746:134]
reg blockUncachedGrant; // @[DCache.scala:750:33]
wire _T_92 = grantIsUncachedData & (blockUncachedGrant | s1_valid); // @[package.scala:16:47]
assign nodeOut_d_ready = ~(_T_92 | _T_90) & _nodeOut_d_ready_T_3; // @[DCache.scala:671:{18,24}, :722:{23,51}, :724:20, :752:{31,68}, :753:22]
assign io_cpu_req_ready_0 = _T_92 ? ~(nodeOut_d_valid | _T_10 | ~metaArb_io_in_7_ready | ~dataArb_io_in_3_ready) & _io_cpu_req_ready_T_4 : ~(_T_10 | ~metaArb_io_in_7_ready | ~dataArb_io_in_3_ready) & _io_cpu_req_ready_T_4; // @[DCache.scala:101:7, :135:28, :152:28, :195:9, :233:{20,73}, :258:{9,45,64}, :267:{34,53}, :275:{27,53,79,98}, :752:{31,68}, :755:29, :756:26]
wire _GEN_98 = _T_92 & nodeOut_d_valid; // @[DCache.scala:721:26, :752:{31,68}, :755:29, :757:32]
assign dataArb_io_in_1_valid = _GEN_98 | _dataArb_io_in_1_valid_T_1; // @[DCache.scala:152:28, :721:{26,61}, :752:68, :755:29, :757:32]
assign dataArb_io_in_1_bits_write = ~_T_92 | ~nodeOut_d_valid; // @[DCache.scala:152:28, :727:33, :752:{31,68}, :755:29, :758:37]
wire _blockUncachedGrant_T = ~dataArb_io_in_1_ready; // @[DCache.scala:152:28, :722:26, :759:31]
wire _block_probe_for_core_progress_T = |blockProbeAfterGrantCount; // @[DCache.scala:668:42, :669:35, :766:65]
wire block_probe_for_core_progress = _block_probe_for_core_progress_T | lrscValid; // @[DCache.scala:473:29, :766:{65,71}]
wire [31:0] _block_probe_for_pending_release_ack_T = nodeOut_b_bits_address ^ release_ack_addr; // @[DCache.scala:227:29, :767:88]
wire [14:0] _block_probe_for_pending_release_ack_T_1 = _block_probe_for_pending_release_ack_T[20:6]; // @[DCache.scala:767:{88,107}]
wire _block_probe_for_pending_release_ack_T_2 = _block_probe_for_pending_release_ack_T_1 == 15'h0; // @[DCache.scala:582:29, :767:{107,163}]
wire block_probe_for_pending_release_ack = release_ack_wait & _block_probe_for_pending_release_ack_T_2; // @[DCache.scala:226:33, :767:{62,163}]
wire _block_probe_for_ordering_T = releaseInFlight | block_probe_for_pending_release_ack; // @[DCache.scala:334:46, :767:62, :768:50]
wire block_probe_for_ordering = _block_probe_for_ordering_T | grantInProgress; // @[DCache.scala:667:32, :768:{50,89}]
wire _metaArb_io_in_6_valid_T = ~block_probe_for_core_progress; // @[DCache.scala:766:71, :769:48]
wire _metaArb_io_in_6_valid_T_1 = _metaArb_io_in_6_valid_T | lrscBackingOff; // @[DCache.scala:474:40, :769:{48,79}]
wire _metaArb_io_in_6_valid_T_2 = nodeOut_b_valid & _metaArb_io_in_6_valid_T_1; // @[DCache.scala:769:{44,79}]
wire _nodeOut_b_ready_T = block_probe_for_core_progress | block_probe_for_ordering; // @[DCache.scala:766:71, :768:89, :770:79]
wire _nodeOut_b_ready_T_1 = _nodeOut_b_ready_T | s1_valid; // @[DCache.scala:182:25, :770:{79,107}]
wire _nodeOut_b_ready_T_2 = _nodeOut_b_ready_T_1 | s2_valid; // @[DCache.scala:331:25, :770:{107,119}]
wire _nodeOut_b_ready_T_3 = ~_nodeOut_b_ready_T_2; // @[DCache.scala:770:{47,119}]
assign _nodeOut_b_ready_T_4 = metaArb_io_in_6_ready & _nodeOut_b_ready_T_3; // @[DCache.scala:135:28, :770:{44,47}]
assign nodeOut_b_ready = _nodeOut_b_ready_T_4; // @[DCache.scala:770:44]
wire [1:0] _metaArb_io_in_6_bits_idx_T = nodeOut_b_bits_address[7:6]; // @[DCache.scala:1200:47]
wire [7:0] _metaArb_io_in_6_bits_addr_T = io_cpu_req_bits_addr_0[39:32]; // @[DCache.scala:101:7, :773:58]
wire [7:0] _metaArb_io_in_6_bits_addr_T_2 = io_cpu_req_bits_addr_0[39:32]; // @[DCache.scala:101:7, :773:58, :844:62]
wire [39:0] _metaArb_io_in_6_bits_addr_T_1 = {_metaArb_io_in_6_bits_addr_T, nodeOut_b_bits_address}; // @[DCache.scala:773:{36,58}]
assign _s1_victim_way_T = lfsr[1:0]; // @[PRNG.scala:95:17]
assign s1_victim_way = _s1_victim_way_T; // @[package.scala:163:13]
wire _T_132 = nodeOut_c_ready & nodeOut_c_valid; // @[Decoupled.scala:51:35]
wire _releaseRejected_T; // @[Decoupled.scala:51:35]
assign _releaseRejected_T = _T_132; // @[Decoupled.scala:51:35]
wire _io_cpu_perf_release_T; // @[Decoupled.scala:51:35]
assign _io_cpu_perf_release_T = _T_132; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_99 = 27'hFFF << nodeOut_c_bits_size; // @[package.scala:243:71]
wire [26:0] _r_beats1_decode_T_3; // @[package.scala:243:71]
assign _r_beats1_decode_T_3 = _GEN_99; // @[package.scala:243:71]
wire [26:0] _io_cpu_perf_release_beats1_decode_T; // @[package.scala:243:71]
assign _io_cpu_perf_release_beats1_decode_T = _GEN_99; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_4 = _r_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_5 = ~_r_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] r_beats1_decode_1 = _r_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire r_beats1_opdata_1 = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36]
wire io_cpu_perf_release_beats1_opdata = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36]
wire [8:0] r_beats1_1 = r_beats1_opdata_1 ? r_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
reg [8:0] r_counter_1; // @[Edges.scala:229:27]
wire [9:0] _r_counter1_T_1 = {1'h0, r_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] r_counter1_1 = _r_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire c_first = r_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T_2 = r_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_3 = r_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire c_last = _r_last_T_2 | _r_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire releaseDone = c_last & _T_132; // @[Decoupled.scala:51:35]
wire [8:0] _r_count_T_1 = ~r_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] c_count = r_beats1_1 & _r_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _r_counter_T_1 = c_first ? r_beats1_1 : r_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _releaseRejected_T_2; // @[DCache.scala:803:44]
wire releaseRejected; // @[DCache.scala:800:29]
wire _s1_release_data_valid_T = dataArb_io_in_2_ready & _dataArb_io_in_2_valid_T_1; // @[Decoupled.scala:51:35]
reg s1_release_data_valid; // @[DCache.scala:801:38]
wire _s2_release_data_valid_T = ~releaseRejected; // @[DCache.scala:800:29, :802:64]
wire _s2_release_data_valid_T_1 = s1_release_data_valid & _s2_release_data_valid_T; // @[DCache.scala:801:38, :802:{61,64}]
reg s2_release_data_valid; // @[DCache.scala:802:38]
wire _nodeOut_c_valid_T_3 = s2_release_data_valid; // @[DCache.scala:802:38, :810:44]
wire _releaseRejected_T_1 = ~_releaseRejected_T; // @[Decoupled.scala:51:35]
assign _releaseRejected_T_2 = s2_release_data_valid & _releaseRejected_T_1; // @[DCache.scala:802:38, :803:{44,47}]
assign releaseRejected = _releaseRejected_T_2; // @[DCache.scala:800:29, :803:44]
wire [9:0] _releaseDataBeat_T = {1'h0, c_count}; // @[Edges.scala:234:25]
wire [1:0] _releaseDataBeat_T_1 = {1'h0, s2_release_data_valid}; // @[DCache.scala:802:38, :804:98]
wire [2:0] _releaseDataBeat_T_2 = {2'h0, s1_release_data_valid} + {1'h0, _releaseDataBeat_T_1}; // @[DCache.scala:801:38, :804:{93,98}]
wire [1:0] _releaseDataBeat_T_3 = _releaseDataBeat_T_2[1:0]; // @[DCache.scala:804:93]
wire [1:0] _releaseDataBeat_T_4 = releaseRejected ? 2'h0 : _releaseDataBeat_T_3; // @[DCache.scala:800:29, :804:{48,93}]
wire [10:0] _releaseDataBeat_T_5 = {1'h0, _releaseDataBeat_T} + {9'h0, _releaseDataBeat_T_4}; // @[DCache.scala:804:{28,43,48}]
wire [9:0] releaseDataBeat = _releaseDataBeat_T_5[9:0]; // @[DCache.scala:804:43]
wire _nodeOut_c_valid_T_4 = c_first & release_ack_wait; // @[Edges.scala:231:25]
wire _nodeOut_c_valid_T_5 = ~_nodeOut_c_valid_T_4; // @[DCache.scala:810:{120,130}]
wire _nodeOut_c_valid_T_6 = _nodeOut_c_valid_T_3 & _nodeOut_c_valid_T_5; // @[DCache.scala:810:{44,117,120}]
wire [1:0] newCoh_state; // @[DCache.scala:812:27]
wire [1:0] metaArb_io_in_4_bits_data_meta_coh_state = newCoh_state; // @[HellaCache.scala:305:20]
wire _release_state_T_8 = s2_valid_flush_line | s2_flush_valid; // @[DCache.scala:363:51, :419:75, :817:34, :820:151]
wire _discard_line_T = s2_req_size[1]; // @[DCache.scala:339:19, :818:60]
wire _discard_line_T_1 = s2_valid_flush_line & _discard_line_T; // @[DCache.scala:419:75, :818:{46,60}]
wire _discard_line_T_3 = s2_flush_valid & _discard_line_T_2; // @[DCache.scala:363:51, :818:{82,102}]
wire discard_line = _discard_line_T_1 | _discard_line_T_3; // @[DCache.scala:818:{46,64,82}]
wire _release_state_T = ~discard_line; // @[DCache.scala:818:64, :819:47]
wire _release_state_T_1 = s2_victim_dirty & _release_state_T; // @[Misc.scala:38:9]
wire _release_state_T_3 = ~release_ack_wait; // @[DCache.scala:226:33, :607:47, :820:57]
wire _release_state_T_6 = |s2_victim_state_state; // @[Metadata.scala:50:45]
wire _release_state_T_9 = ~s2_hit_valid; // @[Metadata.scala:50:45]
wire _release_state_T_10 = s2_readwrite & _release_state_T_9; // @[DCache.scala:354:30, :820:{185,188}]
wire _release_state_T_11 = _release_state_T_8 | _release_state_T_10; // @[DCache.scala:820:{151,169,185}]
wire [3:0] _release_state_T_14 = _release_state_T_1 ? 4'h1 : 4'h6; // @[DCache.scala:819:{27,44}]
wire [1:0] _probe_bits_T_1 = s2_req_addr[7:6]; // @[DCache.scala:339:19, :822:76]
wire [25:0] _probe_bits_T_2 = {s2_victim_tag, _probe_bits_T_1}; // @[DCache.scala:433:26, :822:{49,76}]
wire [31:0] _probe_bits_T_3 = {_probe_bits_T_2, 6'h0}; // @[DCache.scala:822:{49,96}]
wire [31:0] probe_bits_res_address = _probe_bits_T_3; // @[DCache.scala:822:96, :1202:19]
wire probeNack; // @[DCache.scala:825:34]
wire [3:0] _release_state_T_15 = {1'h0, releaseDone, 2'h3}; // @[Edges.scala:233:22]
wire _probeNack_T = ~releaseDone; // @[Edges.scala:233:22]
assign probeNack = s2_prb_ack_data | (|s2_probe_state_state) | _probeNack_T; // @[Misc.scala:38:9]
wire [3:0] _release_state_T_16 = releaseDone ? 4'h0 : 4'h5; // @[Edges.scala:233:22]
assign s1_nack = s2_probe ? probeNack | _T_60 | _T_40 | _T_14 : _T_60 | _T_40 | _T_14; // @[DCache.scala:185:28, :276:{39,58,79}, :288:{75,85}, :333:25, :446:{24,82,92}, :571:{18,36,46}, :824:21, :825:34, :839:{24,34}]
wire _T_102 = release_state == 4'h4; // @[DCache.scala:228:30, :841:25]
assign metaArb_io_in_6_valid = _T_102 | _metaArb_io_in_6_valid_T_2; // @[DCache.scala:135:28, :769:{26,44}, :841:{25,44}, :842:30]
assign metaArb_io_in_6_bits_idx = _T_102 ? _metaArb_io_in_6_bits_idx_T_1 : _metaArb_io_in_6_bits_idx_T; // @[DCache.scala:135:28, :772:29, :841:{25,44}, :843:33, :1200:47]
wire [39:0] _metaArb_io_in_6_bits_addr_T_3 = {_metaArb_io_in_6_bits_addr_T_2, probe_bits_address}; // @[DCache.scala:184:29, :844:{40,62}]
assign metaArb_io_in_6_bits_addr = _T_102 ? _metaArb_io_in_6_bits_addr_T_3 : _metaArb_io_in_6_bits_addr_T_1; // @[DCache.scala:135:28, :773:{30,36}, :841:{25,44}, :844:{34,40}]
wire _T_103 = release_state == 4'h5; // @[DCache.scala:228:30, :850:25]
wire _T_104 = release_state == 4'h3; // @[DCache.scala:228:30, :854:25]
assign nodeOut_c_valid = _T_104 | _T_103 | s2_probe & ~s2_prb_ack_data | _nodeOut_c_valid_T_6; // @[Misc.scala:38:9]
wire _GEN_100 = _T_104 | ~(~s2_probe | s2_prb_ack_data | ~(|s2_probe_state_state)); // @[Misc.scala:38:9]
wire _T_110 = _T_106 | _T_107 | _T_111; // @[package.scala:16:47, :81:59]
assign nodeOut_c_bits_opcode = _T_110 ? {2'h3, ~_T_111} : {2'h2, _inWriteback_T_1}; // @[package.scala:16:47, :81:59]
assign nodeOut_c_bits_param = _T_110 ? (_T_111 ? nodeOut_c_bits_c_param : nodeOut_c_bits_c_1_param) : _inWriteback_T_1 ? dirtyReleaseMessage_param : _GEN_100 ? cleanReleaseMessage_param : 3'h5; // @[package.scala:16:47, :81:59]
assign nodeOut_c_bits_size = _T_110 ? 4'h6 : _inWriteback_T_1 ? dirtyReleaseMessage_size : _GEN_100 ? cleanReleaseMessage_size : nackResponseMessage_size; // @[package.scala:16:47, :81:59]
assign newCoh_state = _T_110 ? voluntaryNewCoh_state : probeNewCoh_state; // @[package.scala:81:59]
assign releaseWay = _T_110 ? s2_victim_or_hit_way : s2_probe_way; // @[package.scala:81:59]
wire _dataArb_io_in_2_valid_T = releaseDataBeat < 10'h8; // @[DCache.scala:804:43, :900:60]
assign _dataArb_io_in_2_valid_T_1 = inWriteback & _dataArb_io_in_2_valid_T; // @[package.scala:81:59]
assign dataArb_io_in_2_valid = _dataArb_io_in_2_valid_T_1; // @[DCache.scala:152:28, :900:41]
wire [7:0] _dataArb_io_in_2_bits_addr_T_1 = {_dataArb_io_in_2_bits_addr_T, 6'h0}; // @[DCache.scala:903:55, :1200:47]
wire [2:0] _dataArb_io_in_2_bits_addr_T_2 = releaseDataBeat[2:0]; // @[DCache.scala:804:43, :903:90]
wire [5:0] _dataArb_io_in_2_bits_addr_T_3 = {_dataArb_io_in_2_bits_addr_T_2, 3'h0}; // @[DCache.scala:903:{90,117}]
assign _dataArb_io_in_2_bits_addr_T_4 = {_dataArb_io_in_2_bits_addr_T_1[7:6], _dataArb_io_in_2_bits_addr_T_1[5:0] | _dataArb_io_in_2_bits_addr_T_3}; // @[DCache.scala:903:{55,72,117}]
assign dataArb_io_in_2_bits_addr = _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:152:28, :903:72]
wire _metaArb_io_in_4_valid_T_1 = release_state == 4'h7; // @[package.scala:16:47]
assign _metaArb_io_in_4_valid_T_2 = _metaArb_io_in_4_valid_T | _metaArb_io_in_4_valid_T_1; // @[package.scala:16:47, :81:59]
assign metaArb_io_in_4_valid = _metaArb_io_in_4_valid_T_2; // @[package.scala:81:59]
assign metaArb_io_in_4_bits_idx = _metaArb_io_in_4_bits_idx_T; // @[DCache.scala:135:28, :1200:47]
wire [7:0] _metaArb_io_in_4_bits_addr_T_1 = probe_bits_address[7:0]; // @[DCache.scala:184:29, :912:90]
assign _metaArb_io_in_4_bits_addr_T_2 = {_metaArb_io_in_4_bits_addr_T, _metaArb_io_in_4_bits_addr_T_1}; // @[DCache.scala:912:{36,58,90}]
assign metaArb_io_in_4_bits_addr = _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:135:28, :912:36]
wire [23:0] _metaArb_io_in_4_bits_data_T = nodeOut_c_bits_address[31:8]; // @[DCache.scala:913:78]
wire [23:0] metaArb_io_in_4_bits_data_meta_tag = _metaArb_io_in_4_bits_data_T; // @[HellaCache.scala:305:20]
assign _metaArb_io_in_4_bits_data_T_1 = {metaArb_io_in_4_bits_data_meta_coh_state, metaArb_io_in_4_bits_data_meta_tag}; // @[HellaCache.scala:305:20]
assign metaArb_io_in_4_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97]
assign metaArb_io_in_5_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97]
assign metaArb_io_in_6_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97]
assign metaArb_io_in_7_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97]
wire _io_cpu_s2_uncached_T = ~s2_hit; // @[Misc.scala:35:9]
assign _io_cpu_s2_uncached_T_1 = s2_uncached & _io_cpu_s2_uncached_T; // @[DCache.scala:424:39, :920:{37,40}]
assign io_cpu_s2_uncached_0 = _io_cpu_s2_uncached_T_1; // @[DCache.scala:101:7, :920:37]
wire _io_cpu_ordered_T = ~s1_req_no_xcpt; // @[DCache.scala:196:25, :929:35]
wire _io_cpu_ordered_T_1 = s1_valid & _io_cpu_ordered_T; // @[DCache.scala:182:25, :929:{32,35}]
wire _io_cpu_ordered_T_2 = ~s2_req_no_xcpt; // @[DCache.scala:339:19, :929:72]
wire _io_cpu_ordered_T_3 = s2_valid & _io_cpu_ordered_T_2; // @[DCache.scala:331:25, :929:{69,72}]
wire _io_cpu_ordered_T_4 = _io_cpu_ordered_T_1 | _io_cpu_ordered_T_3; // @[DCache.scala:929:{32,57,69}]
wire _io_cpu_ordered_T_5 = _io_cpu_ordered_T_4 | cached_grant_wait; // @[DCache.scala:223:34, :929:{57,94}]
wire _io_cpu_ordered_T_7 = _io_cpu_ordered_T_5 | _io_cpu_ordered_T_6; // @[DCache.scala:929:{94,115,142}]
assign _io_cpu_ordered_T_8 = ~_io_cpu_ordered_T_7; // @[DCache.scala:929:{21,115}]
assign io_cpu_ordered_0 = _io_cpu_ordered_T_8; // @[DCache.scala:101:7, :929:21]
wire _io_cpu_store_pending_T_2 = _io_cpu_store_pending_T | _io_cpu_store_pending_T_1; // @[Consts.scala:90:{32,42,49}]
wire _io_cpu_store_pending_T_4 = _io_cpu_store_pending_T_2 | _io_cpu_store_pending_T_3; // @[Consts.scala:90:{42,59,66}]
wire _io_cpu_store_pending_T_9 = _io_cpu_store_pending_T_5 | _io_cpu_store_pending_T_6; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_10 = _io_cpu_store_pending_T_9 | _io_cpu_store_pending_T_7; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_11 = _io_cpu_store_pending_T_10 | _io_cpu_store_pending_T_8; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_17 = _io_cpu_store_pending_T_12 | _io_cpu_store_pending_T_13; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_18 = _io_cpu_store_pending_T_17 | _io_cpu_store_pending_T_14; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_19 = _io_cpu_store_pending_T_18 | _io_cpu_store_pending_T_15; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_20 = _io_cpu_store_pending_T_19 | _io_cpu_store_pending_T_16; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_21 = _io_cpu_store_pending_T_11 | _io_cpu_store_pending_T_20; // @[package.scala:81:59]
wire _io_cpu_store_pending_T_22 = _io_cpu_store_pending_T_4 | _io_cpu_store_pending_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _io_cpu_store_pending_T_23 = cached_grant_wait & _io_cpu_store_pending_T_22; // @[DCache.scala:223:34, :930:46]
assign _io_cpu_store_pending_T_25 = _io_cpu_store_pending_T_23 | _io_cpu_store_pending_T_24; // @[DCache.scala:930:{46,70,97}]
assign io_cpu_store_pending_0 = _io_cpu_store_pending_T_25; // @[DCache.scala:101:7, :930:70]
wire _s1_xcpt_valid_T = ~s1_req_no_xcpt; // @[DCache.scala:196:25, :929:35, :932:43]
wire _s1_xcpt_valid_T_1 = _tlb_io_req_valid_T_3 & _s1_xcpt_valid_T; // @[DCache.scala:273:40, :932:{40,43}]
wire _s1_xcpt_valid_T_2 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :932:68]
wire s1_xcpt_valid = _s1_xcpt_valid_T_1 & _s1_xcpt_valid_T_2; // @[DCache.scala:932:{40,65,68}]
reg io_cpu_s2_xcpt_REG; // @[DCache.scala:933:32]
wire _io_cpu_s2_xcpt_T_miss = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_miss; // @[DCache.scala:342:24, :933:{24,32}]
wire [31:0] _io_cpu_s2_xcpt_T_paddr = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_paddr : 32'h0; // @[DCache.scala:342:24, :933:{24,32}]
wire [39:0] _io_cpu_s2_xcpt_T_gpa = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_gpa : 40'h0; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_pf_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_pf_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24, :933:{24,32}]
wire _io_cpu_s2_xcpt_T_pf_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_ae_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_ae_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24, :933:{24,32}]
wire _io_cpu_s2_xcpt_T_ae_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_ma_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_ma_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24, :933:{24,32}]
wire _io_cpu_s2_xcpt_T_cacheable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24, :933:{24,32}]
wire _io_cpu_s2_xcpt_T_must_alloc = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24, :933:{24,32}]
wire _io_cpu_s2_xcpt_T_prefetchable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24, :933:{24,32}]
wire [1:0] _io_cpu_s2_xcpt_T_size = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_size : 2'h0; // @[DCache.scala:342:24, :933:{24,32}]
wire [4:0] _io_cpu_s2_xcpt_T_cmd = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_cmd : 5'h0; // @[DCache.scala:342:24, :933:{24,32}]
assign io_cpu_s2_xcpt_pf_ld_0 = _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:101:7, :933:24]
assign io_cpu_s2_xcpt_pf_st_0 = _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:101:7, :933:24]
assign io_cpu_s2_xcpt_ae_ld_0 = _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:101:7, :933:24]
assign io_cpu_s2_xcpt_ae_st_0 = _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:101:7, :933:24]
assign io_cpu_s2_xcpt_ma_ld_0 = _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:101:7, :933:24]
assign io_cpu_s2_xcpt_ma_st_0 = _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:101:7, :933:24]
reg [63:0] s2_uncached_data_word; // @[DCache.scala:947:40]
reg doUncachedResp; // @[DCache.scala:948:31]
assign io_cpu_resp_bits_replay_0 = doUncachedResp; // @[DCache.scala:101:7, :948:31]
wire _io_cpu_resp_valid_T = s2_valid_hit_pre_data_ecc | doUncachedResp; // @[DCache.scala:420:69, :948:31, :949:51]
assign _io_cpu_resp_valid_T_2 = _io_cpu_resp_valid_T; // @[DCache.scala:949:{51,70}]
assign io_cpu_resp_valid_0 = _io_cpu_resp_valid_T_2; // @[DCache.scala:101:7, :949:70]
wire _io_cpu_replay_next_T_1 = _io_cpu_replay_next_T & grantIsUncachedData; // @[Decoupled.scala:51:35]
assign _io_cpu_replay_next_T_3 = _io_cpu_replay_next_T_1; // @[DCache.scala:950:{39,62}]
assign io_cpu_replay_next_0 = _io_cpu_replay_next_T_3; // @[DCache.scala:101:7, :950:62]
assign io_cpu_resp_bits_addr_0 = doUncachedResp ? s2_uncached_resp_addr : s2_req_addr; // @[DCache.scala:101:7, :339:19, :344:34, :917:37, :948:31, :951:25, :954:27]
assign io_cpu_resp_bits_data_raw_0 = s2_data_word; // @[DCache.scala:101:7, :970:80]
wire [63:0] s2_data_word_possibly_uncached = s2_data_word; // @[DCache.scala:970:80, :972:120]
wire [31:0] _io_cpu_resp_bits_data_shifted_T_1 = s2_data_word_possibly_uncached[63:32]; // @[DCache.scala:972:120]
wire [31:0] _io_cpu_resp_bits_data_T_5 = s2_data_word_possibly_uncached[63:32]; // @[DCache.scala:972:120]
wire [31:0] _io_cpu_resp_bits_data_word_bypass_shifted_T_1 = s2_data_word_possibly_uncached[63:32]; // @[DCache.scala:972:120]
wire [31:0] _io_cpu_resp_bits_data_word_bypass_T_5 = s2_data_word_possibly_uncached[63:32]; // @[DCache.scala:972:120]
wire [31:0] _io_cpu_resp_bits_data_shifted_T_2 = s2_data_word_possibly_uncached[31:0]; // @[DCache.scala:972:120]
wire [31:0] _io_cpu_resp_bits_data_word_bypass_shifted_T_2 = s2_data_word_possibly_uncached[31:0]; // @[DCache.scala:972:120]
wire [31:0] io_cpu_resp_bits_data_shifted = _io_cpu_resp_bits_data_shifted_T ? _io_cpu_resp_bits_data_shifted_T_1 : _io_cpu_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] io_cpu_resp_bits_data_zeroed = io_cpu_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _GEN_101 = size == 2'h2; // @[AMOALU.scala:11:18, :45:26]
wire _io_cpu_resp_bits_data_T; // @[AMOALU.scala:45:26]
assign _io_cpu_resp_bits_data_T = _GEN_101; // @[AMOALU.scala:45:26]
wire _io_cpu_resp_bits_data_word_bypass_T; // @[AMOALU.scala:45:26]
assign _io_cpu_resp_bits_data_word_bypass_T = _GEN_101; // @[AMOALU.scala:45:26]
wire _io_cpu_resp_bits_data_T_1 = _io_cpu_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _io_cpu_resp_bits_data_T_2 = io_cpu_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _io_cpu_resp_bits_data_T_3 = s2_req_signed & _io_cpu_resp_bits_data_T_2; // @[DCache.scala:339:19]
wire [31:0] _io_cpu_resp_bits_data_T_4 = {32{_io_cpu_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _io_cpu_resp_bits_data_T_6 = _io_cpu_resp_bits_data_T_1 ? _io_cpu_resp_bits_data_T_4 : _io_cpu_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_cpu_resp_bits_data_T_7 = {_io_cpu_resp_bits_data_T_6, io_cpu_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire [15:0] _io_cpu_resp_bits_data_shifted_T_4 = _io_cpu_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _io_cpu_resp_bits_data_shifted_T_5 = _io_cpu_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] io_cpu_resp_bits_data_shifted_1 = _io_cpu_resp_bits_data_shifted_T_3 ? _io_cpu_resp_bits_data_shifted_T_4 : _io_cpu_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] io_cpu_resp_bits_data_zeroed_1 = io_cpu_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _io_cpu_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26]
wire _io_cpu_resp_bits_data_T_9 = _io_cpu_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _io_cpu_resp_bits_data_T_10 = io_cpu_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _io_cpu_resp_bits_data_T_11 = s2_req_signed & _io_cpu_resp_bits_data_T_10; // @[DCache.scala:339:19]
wire [47:0] _io_cpu_resp_bits_data_T_12 = {48{_io_cpu_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _io_cpu_resp_bits_data_T_13 = _io_cpu_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _io_cpu_resp_bits_data_T_14 = _io_cpu_resp_bits_data_T_9 ? _io_cpu_resp_bits_data_T_12 : _io_cpu_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_cpu_resp_bits_data_T_15 = {_io_cpu_resp_bits_data_T_14, io_cpu_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire [7:0] _io_cpu_resp_bits_data_shifted_T_7 = _io_cpu_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _io_cpu_resp_bits_data_shifted_T_8 = _io_cpu_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] io_cpu_resp_bits_data_shifted_2 = _io_cpu_resp_bits_data_shifted_T_6 ? _io_cpu_resp_bits_data_shifted_T_7 : _io_cpu_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] io_cpu_resp_bits_data_zeroed_2 = io_cpu_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23]
wire _io_cpu_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26]
wire _io_cpu_resp_bits_data_T_17 = _io_cpu_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}]
wire _io_cpu_resp_bits_data_T_18 = io_cpu_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _io_cpu_resp_bits_data_T_19 = s2_req_signed & _io_cpu_resp_bits_data_T_18; // @[DCache.scala:339:19]
wire [55:0] _io_cpu_resp_bits_data_T_20 = {56{_io_cpu_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _io_cpu_resp_bits_data_T_21 = _io_cpu_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _io_cpu_resp_bits_data_T_22 = _io_cpu_resp_bits_data_T_17 ? _io_cpu_resp_bits_data_T_20 : _io_cpu_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_cpu_resp_bits_data_T_23 = {_io_cpu_resp_bits_data_T_22, io_cpu_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign _io_cpu_resp_bits_data_T_24 = _io_cpu_resp_bits_data_T_23; // @[DCache.scala:974:41]
assign io_cpu_resp_bits_data_0 = _io_cpu_resp_bits_data_T_24; // @[DCache.scala:101:7, :974:41]
wire [31:0] io_cpu_resp_bits_data_word_bypass_shifted = _io_cpu_resp_bits_data_word_bypass_shifted_T ? _io_cpu_resp_bits_data_word_bypass_shifted_T_1 : _io_cpu_resp_bits_data_word_bypass_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] io_cpu_resp_bits_data_word_bypass_zeroed = io_cpu_resp_bits_data_word_bypass_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _io_cpu_resp_bits_data_word_bypass_T_1 = _io_cpu_resp_bits_data_word_bypass_T; // @[AMOALU.scala:45:{26,34}]
wire _io_cpu_resp_bits_data_word_bypass_T_2 = io_cpu_resp_bits_data_word_bypass_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _io_cpu_resp_bits_data_word_bypass_T_3 = s2_req_signed & _io_cpu_resp_bits_data_word_bypass_T_2; // @[DCache.scala:339:19]
wire [31:0] _io_cpu_resp_bits_data_word_bypass_T_4 = {32{_io_cpu_resp_bits_data_word_bypass_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _io_cpu_resp_bits_data_word_bypass_T_6 = _io_cpu_resp_bits_data_word_bypass_T_1 ? _io_cpu_resp_bits_data_word_bypass_T_4 : _io_cpu_resp_bits_data_word_bypass_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
assign _io_cpu_resp_bits_data_word_bypass_T_7 = {_io_cpu_resp_bits_data_word_bypass_T_6, io_cpu_resp_bits_data_word_bypass_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign io_cpu_resp_bits_data_word_bypass_0 = _io_cpu_resp_bits_data_word_bypass_T_7; // @[DCache.scala:101:7] |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncAsyncCrossingSink_n1x1_4 :
input clock : Clock
input reset : Reset
output auto : { flip in : { sync : UInt<1>[1]}, out : UInt<1>[1]}
wire nodeIn : { sync : UInt<1>[1]}
invalidate nodeIn.sync[0]
wire nodeOut : UInt<1>[1]
invalidate nodeOut[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
inst chain of SynchronizerShiftReg_w1_d3_4
connect chain.clock, clock
connect chain.reset, reset
connect chain.io.d, nodeIn.sync[0]
wire _WIRE : UInt<1>[1]
wire _WIRE_1 : UInt<1>
connect _WIRE_1, chain.io.q
node _T = bits(_WIRE_1, 0, 0)
connect _WIRE[0], _T
connect nodeOut, _WIRE | module IntSyncAsyncCrossingSink_n1x1_4( // @[Crossing.scala:74:9]
input clock, // @[Crossing.scala:74:9]
input reset, // @[Crossing.scala:74:9]
input auto_in_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_out_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:74:9]
wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:74:9]
wire nodeOut_0; // @[MixedNode.scala:542:17]
wire auto_out_0_0; // @[Crossing.scala:74:9]
assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:74:9]
SynchronizerShiftReg_w1_d3_4 chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (nodeIn_sync_0), // @[MixedNode.scala:551:17]
.io_q (nodeOut_0)
); // @[ShiftReg.scala:45:23]
assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:74:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_64 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}}
inst input_buffer of InputBuffer_64
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
connect input_buffer.io.deq[4].ready, UInt<1>(0h0)
connect input_buffer.io.deq[5].ready, UInt<1>(0h0)
connect input_buffer.io.deq[6].ready, UInt<1>(0h0)
connect input_buffer.io.deq[7].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter8_RouteComputerReq_64
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h1d))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
connect route_arbiter.io.in[0].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[0].bits.flow.egress_node_id
invalidate route_arbiter.io.in[0].bits.flow.egress_node
invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[0].bits.flow.ingress_node
invalidate route_arbiter.io.in[0].bits.flow.vnet_id
invalidate route_arbiter.io.in[0].bits.src_virt_id
node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1))
connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T
connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id
connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node
connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id
connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node
connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id
connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1)
node _T_9 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_9 :
connect states[1].g, UInt<3>(0h2)
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_10 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_10 :
connect states[2].g, UInt<3>(0h2)
node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1))
connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T
connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id
connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node
connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id
connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node
connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id
connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3)
node _T_11 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid)
when _T_11 :
connect states[3].g, UInt<3>(0h2)
node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1))
connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T
connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id
connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node
connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id
connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node
connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id
connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4)
node _T_12 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid)
when _T_12 :
connect states[4].g, UInt<3>(0h2)
node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1))
connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T
connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id
connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node
connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id
connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node
connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id
connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5)
node _T_13 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid)
when _T_13 :
connect states[5].g, UInt<3>(0h2)
node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1))
connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T
connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id
connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node
connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id
connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node
connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id
connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6)
node _T_14 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid)
when _T_14 :
connect states[6].g, UInt<3>(0h2)
node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1))
connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T
connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id
connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node
connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id
connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node
connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id
connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7)
node _T_15 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid)
when _T_15 :
connect states[7].g, UInt<3>(0h2)
node _T_16 = and(io.router_req.ready, io.router_req.valid)
when _T_16 :
node _T_17 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_17, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_21 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_21 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_22 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_22 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_23 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_23 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_24 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_24 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_25 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id)
when _T_25 :
connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_26 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id)
when _T_26 :
connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_27 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id)
when _T_27 :
connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_28 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id)
when _T_28 :
connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2`
regreset mask : UInt<8>, clock, reset, UInt<8>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8]
wire vcalloc_vals : UInt<1>[8]
node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo)
node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo)
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1)
node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1)
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8)
node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9)
node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10)
node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11)
node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12)
node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13)
node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14)
node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15)
node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0))
node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21)
node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22)
node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23)
node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24)
node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25)
node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26)
node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27)
node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28)
node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29)
node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30)
node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31)
node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32)
node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33)
node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35)
node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_29 = and(io.router_req.ready, io.router_req.valid)
when _T_29 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_30 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_31 = or(_T_30, vcalloc_vals[2])
node _T_32 = or(_T_31, vcalloc_vals[3])
node _T_33 = or(_T_32, vcalloc_vals[4])
node _T_34 = or(_T_33, vcalloc_vals[5])
node _T_35 = or(_T_34, vcalloc_vals[6])
node _T_36 = or(_T_35, vcalloc_vals[7])
when _T_36 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = not(UInt<5>(0h0))
node _mask_T_8 = not(UInt<6>(0h0))
node _mask_T_9 = not(UInt<7>(0h0))
node _mask_T_10 = not(UInt<8>(0h0))
node _mask_T_11 = bits(vcalloc_sel, 0, 0)
node _mask_T_12 = bits(vcalloc_sel, 1, 1)
node _mask_T_13 = bits(vcalloc_sel, 2, 2)
node _mask_T_14 = bits(vcalloc_sel, 3, 3)
node _mask_T_15 = bits(vcalloc_sel, 4, 4)
node _mask_T_16 = bits(vcalloc_sel, 5, 5)
node _mask_T_17 = bits(vcalloc_sel, 6, 6)
node _mask_T_18 = bits(vcalloc_sel, 7, 7)
node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0))
node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0))
node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0))
node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0))
node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0))
node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0))
node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0))
node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0))
node _mask_T_27 = or(_mask_T_19, _mask_T_20)
node _mask_T_28 = or(_mask_T_27, _mask_T_21)
node _mask_T_29 = or(_mask_T_28, _mask_T_22)
node _mask_T_30 = or(_mask_T_29, _mask_T_23)
node _mask_T_31 = or(_mask_T_30, _mask_T_24)
node _mask_T_32 = or(_mask_T_31, _mask_T_25)
node _mask_T_33 = or(_mask_T_32, _mask_T_26)
wire _mask_WIRE : UInt<8>
connect _mask_WIRE, _mask_T_33
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4])
node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5])
node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6])
node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4)
node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5)
node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6)
node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8]
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10)
node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11)
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12)
node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13)
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25)
node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26)
node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27)
node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28)
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40)
node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41)
node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42)
node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43)
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55)
node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56)
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70)
node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71)
node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72)
node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73)
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82
connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84)
node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85)
node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86)
node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87)
node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88)
node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89)
node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97
connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99)
node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100)
node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101)
node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102)
node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103)
node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104)
node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112
connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114)
node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115)
node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116)
node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117)
node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118)
node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119)
node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127
connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8]
node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129)
node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130)
node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131)
node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132)
node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133)
node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134)
node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142
connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144)
node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145)
node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146)
node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147)
node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148)
node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149)
node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157
connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13
node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159)
node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160)
node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161)
node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162)
node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163)
node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164)
node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172
connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14
node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174)
node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175)
node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176)
node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177)
node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178)
node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179)
node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187
connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15
node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189)
node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190)
node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191)
node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192)
node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193)
node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194)
node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202
connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16
node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204)
node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205)
node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206)
node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207)
node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208)
node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209)
node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217
connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219)
node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220)
node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221)
node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222)
node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223)
node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224)
node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232
connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234)
node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235)
node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236)
node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237)
node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238)
node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239)
node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247
connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11
wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8]
node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249)
node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250)
node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251)
node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252)
node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253)
node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254)
node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262
connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264)
node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265)
node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266)
node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267)
node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268)
node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269)
node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277
connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22
node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279)
node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280)
node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281)
node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282)
node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283)
node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284)
node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285)
wire _io_vcalloc_req_bits_WIRE_23 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292
connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23
node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294)
node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295)
node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296)
node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297)
node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298)
node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299)
node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300)
wire _io_vcalloc_req_bits_WIRE_24 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307
connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24
node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309)
node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310)
node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311)
node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312)
node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313)
node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314)
node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315)
wire _io_vcalloc_req_bits_WIRE_25 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322
connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25
node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324)
node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325)
node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326)
node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327)
node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328)
node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329)
node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330)
wire _io_vcalloc_req_bits_WIRE_26 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337
connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26
node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339)
node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340)
node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341)
node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342)
node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343)
node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344)
node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345)
wire _io_vcalloc_req_bits_WIRE_27 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352
connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27
node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354)
node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355)
node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356)
node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357)
node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358)
node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359)
node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360)
wire _io_vcalloc_req_bits_WIRE_28 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367
connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369)
node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370)
node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371)
node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372)
node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373)
node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374)
node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375)
wire _io_vcalloc_req_bits_WIRE_29 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_29, _io_vcalloc_req_bits_T_382
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_29
wire _io_vcalloc_req_bits_WIRE_30 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384)
node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385)
node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386)
node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387)
node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388)
node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389)
node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390)
wire _io_vcalloc_req_bits_WIRE_31 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397
connect _io_vcalloc_req_bits_WIRE_30.egress_node_id, _io_vcalloc_req_bits_WIRE_31
node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399)
node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400)
node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401)
node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402)
node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403)
node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404)
node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405)
wire _io_vcalloc_req_bits_WIRE_32 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412
connect _io_vcalloc_req_bits_WIRE_30.egress_node, _io_vcalloc_req_bits_WIRE_32
node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414)
node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415)
node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416)
node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417)
node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418)
node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419)
node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420)
wire _io_vcalloc_req_bits_WIRE_33 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427
connect _io_vcalloc_req_bits_WIRE_30.ingress_node_id, _io_vcalloc_req_bits_WIRE_33
node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429)
node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430)
node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431)
node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432)
node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433)
node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434)
node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435)
wire _io_vcalloc_req_bits_WIRE_34 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442
connect _io_vcalloc_req_bits_WIRE_30.ingress_node, _io_vcalloc_req_bits_WIRE_34
node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444)
node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445)
node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446)
node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447)
node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448)
node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449)
node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450)
wire _io_vcalloc_req_bits_WIRE_35 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457
connect _io_vcalloc_req_bits_WIRE_30.vnet_id, _io_vcalloc_req_bits_WIRE_35
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_30
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
connect vcalloc_vals[0], UInt<1>(0h0)
invalidate vcalloc_reqs[0].vc_sel.`0`[0]
invalidate vcalloc_reqs[0].vc_sel.`0`[1]
invalidate vcalloc_reqs[0].vc_sel.`0`[2]
invalidate vcalloc_reqs[0].vc_sel.`0`[3]
invalidate vcalloc_reqs[0].vc_sel.`0`[4]
invalidate vcalloc_reqs[0].vc_sel.`0`[5]
invalidate vcalloc_reqs[0].vc_sel.`0`[6]
invalidate vcalloc_reqs[0].vc_sel.`0`[7]
invalidate vcalloc_reqs[0].vc_sel.`1`[0]
invalidate vcalloc_reqs[0].vc_sel.`1`[1]
invalidate vcalloc_reqs[0].vc_sel.`1`[2]
invalidate vcalloc_reqs[0].vc_sel.`1`[3]
invalidate vcalloc_reqs[0].vc_sel.`1`[4]
invalidate vcalloc_reqs[0].vc_sel.`1`[5]
invalidate vcalloc_reqs[0].vc_sel.`1`[6]
invalidate vcalloc_reqs[0].vc_sel.`1`[7]
invalidate vcalloc_reqs[0].vc_sel.`2`[0]
invalidate vcalloc_reqs[0].vc_sel.`2`[1]
invalidate vcalloc_reqs[0].vc_sel.`2`[2]
invalidate vcalloc_reqs[0].vc_sel.`2`[3]
invalidate vcalloc_reqs[0].vc_sel.`2`[4]
invalidate vcalloc_reqs[0].vc_sel.`2`[5]
invalidate vcalloc_reqs[0].vc_sel.`2`[6]
invalidate vcalloc_reqs[0].vc_sel.`2`[7]
invalidate vcalloc_reqs[0].in_vc
invalidate vcalloc_reqs[0].flow.egress_node_id
invalidate vcalloc_reqs[0].flow.egress_node
invalidate vcalloc_reqs[0].flow.ingress_node_id
invalidate vcalloc_reqs[0].flow.ingress_node
invalidate vcalloc_reqs[0].flow.vnet_id
node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2))
node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1)
connect vcalloc_vals[1], _vcalloc_vals_1_T_2
connect vcalloc_reqs[1].in_vc, UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1`
connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2`
connect vcalloc_reqs[1].flow, states[1].flow
node _T_37 = bits(vcalloc_sel, 1, 1)
node _T_38 = and(vcalloc_vals[1], _T_37)
node _T_39 = and(_T_38, io.vcalloc_req.ready)
when _T_39 :
connect states[1].g, UInt<3>(0h3)
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_40 = bits(vcalloc_sel, 2, 2)
node _T_41 = and(vcalloc_vals[2], _T_40)
node _T_42 = and(_T_41, io.vcalloc_req.ready)
when _T_42 :
connect states[2].g, UInt<3>(0h3)
node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2))
node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1)
connect vcalloc_vals[3], _vcalloc_vals_3_T_2
connect vcalloc_reqs[3].in_vc, UInt<2>(0h3)
connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0`
connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1`
connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2`
connect vcalloc_reqs[3].flow, states[3].flow
node _T_43 = bits(vcalloc_sel, 3, 3)
node _T_44 = and(vcalloc_vals[3], _T_43)
node _T_45 = and(_T_44, io.vcalloc_req.ready)
when _T_45 :
connect states[3].g, UInt<3>(0h3)
node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2))
node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1)
connect vcalloc_vals[4], _vcalloc_vals_4_T_2
connect vcalloc_reqs[4].in_vc, UInt<3>(0h4)
connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0`
connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1`
connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2`
connect vcalloc_reqs[4].flow, states[4].flow
node _T_46 = bits(vcalloc_sel, 4, 4)
node _T_47 = and(vcalloc_vals[4], _T_46)
node _T_48 = and(_T_47, io.vcalloc_req.ready)
when _T_48 :
connect states[4].g, UInt<3>(0h3)
node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2))
node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1)
connect vcalloc_vals[5], _vcalloc_vals_5_T_2
connect vcalloc_reqs[5].in_vc, UInt<3>(0h5)
connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0`
connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1`
connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2`
connect vcalloc_reqs[5].flow, states[5].flow
node _T_49 = bits(vcalloc_sel, 5, 5)
node _T_50 = and(vcalloc_vals[5], _T_49)
node _T_51 = and(_T_50, io.vcalloc_req.ready)
when _T_51 :
connect states[5].g, UInt<3>(0h3)
node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2))
node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1)
connect vcalloc_vals[6], _vcalloc_vals_6_T_2
connect vcalloc_reqs[6].in_vc, UInt<3>(0h6)
connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0`
connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1`
connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2`
connect vcalloc_reqs[6].flow, states[6].flow
node _T_52 = bits(vcalloc_sel, 6, 6)
node _T_53 = and(vcalloc_vals[6], _T_52)
node _T_54 = and(_T_53, io.vcalloc_req.ready)
when _T_54 :
connect states[6].g, UInt<3>(0h3)
node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2))
node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1)
connect vcalloc_vals[7], _vcalloc_vals_7_T_2
connect vcalloc_reqs[7].in_vc, UInt<3>(0h7)
connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0`
connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1`
connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2`
connect vcalloc_reqs[7].flow, states[7].flow
node _T_55 = bits(vcalloc_sel, 7, 7)
node _T_56 = and(vcalloc_vals[7], _T_55)
node _T_57 = and(_T_56, io.vcalloc_req.ready)
when _T_57 :
connect states[7].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0)
node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5])
node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0)
node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7])
node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0)
node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9)
node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0)
node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11)
node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0)
node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready)
node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_15
node _T_58 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_58 :
node _T_59 = bits(vcalloc_sel, 0, 0)
when _T_59 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].g, UInt<3>(0h3)
node _T_60 = eq(states[0].g, UInt<3>(0h2))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_60, UInt<1>(0h1), "") : assert_3
node _T_64 = bits(vcalloc_sel, 1, 1)
when _T_64 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].g, UInt<3>(0h3)
node _T_65 = eq(states[1].g, UInt<3>(0h2))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_65, UInt<1>(0h1), "") : assert_4
node _T_69 = bits(vcalloc_sel, 2, 2)
when _T_69 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].g, UInt<3>(0h3)
node _T_70 = eq(states[2].g, UInt<3>(0h2))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_70, UInt<1>(0h1), "") : assert_5
node _T_74 = bits(vcalloc_sel, 3, 3)
when _T_74 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[3].g, UInt<3>(0h3)
node _T_75 = eq(states[3].g, UInt<3>(0h2))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_75, UInt<1>(0h1), "") : assert_6
node _T_79 = bits(vcalloc_sel, 4, 4)
when _T_79 :
connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[4].g, UInt<3>(0h3)
node _T_80 = eq(states[4].g, UInt<3>(0h2))
node _T_81 = asUInt(reset)
node _T_82 = eq(_T_81, UInt<1>(0h0))
when _T_82 :
node _T_83 = eq(_T_80, UInt<1>(0h0))
when _T_83 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7
assert(clock, _T_80, UInt<1>(0h1), "") : assert_7
node _T_84 = bits(vcalloc_sel, 5, 5)
when _T_84 :
connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[5].g, UInt<3>(0h3)
node _T_85 = eq(states[5].g, UInt<3>(0h2))
node _T_86 = asUInt(reset)
node _T_87 = eq(_T_86, UInt<1>(0h0))
when _T_87 :
node _T_88 = eq(_T_85, UInt<1>(0h0))
when _T_88 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8
assert(clock, _T_85, UInt<1>(0h1), "") : assert_8
node _T_89 = bits(vcalloc_sel, 6, 6)
when _T_89 :
connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[6].g, UInt<3>(0h3)
node _T_90 = eq(states[6].g, UInt<3>(0h2))
node _T_91 = asUInt(reset)
node _T_92 = eq(_T_91, UInt<1>(0h0))
when _T_92 :
node _T_93 = eq(_T_90, UInt<1>(0h0))
when _T_93 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9
assert(clock, _T_90, UInt<1>(0h1), "") : assert_9
node _T_94 = bits(vcalloc_sel, 7, 7)
when _T_94 :
connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[7].g, UInt<3>(0h3)
node _T_95 = eq(states[7].g, UInt<3>(0h2))
node _T_96 = asUInt(reset)
node _T_97 = eq(_T_96, UInt<1>(0h0))
when _T_97 :
node _T_98 = eq(_T_95, UInt<1>(0h0))
when _T_98 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10
assert(clock, _T_95, UInt<1>(0h1), "") : assert_10
inst salloc_arb of SwitchArbiter_160
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
connect salloc_arb.io.in[0].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[0].bits.tail
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[7]
node credit_available_lo_lo = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0])
node credit_available_lo_hi = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2])
node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo)
node credit_available_hi_lo = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4])
node credit_available_hi_hi = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6])
node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo)
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node credit_available_lo_lo_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0])
node credit_available_lo_hi_1 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2])
node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1)
node credit_available_hi_lo_1 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4])
node credit_available_hi_hi_1 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6])
node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1)
node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1)
node credit_available_lo_lo_2 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0])
node credit_available_lo_hi_2 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2])
node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2)
node credit_available_hi_lo_2 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4])
node credit_available_hi_hi_2 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6])
node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2)
node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2)
node credit_available_hi_3 = cat(_credit_available_T_2, _credit_available_T_1)
node _credit_available_T_3 = cat(credit_available_hi_3, _credit_available_T)
node credit_available_lo_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_3 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3)
node credit_available_hi_lo_3 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_3 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_4 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3)
node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_3)
node credit_available_lo_lo_4 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_4 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4)
node credit_available_hi_lo_4 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_4 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4)
node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_4)
node credit_available_lo_lo_5 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_5 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_5 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5)
node credit_available_hi_lo_5 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_5 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5)
node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_5)
node credit_available_hi_7 = cat(_credit_available_T_6, _credit_available_T_5)
node _credit_available_T_7 = cat(credit_available_hi_7, _credit_available_T_4)
node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7)
node credit_available = neq(_credit_available_T_8, UInt<1>(0h0))
node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3))
node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available)
node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid)
connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2
connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7]
connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail
node _T_99 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid)
node _T_100 = and(_T_99, input_buffer.io.deq[1].bits.tail)
when _T_100 :
connect states[1].g, UInt<3>(0h0)
connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready
node credit_available_lo_lo_6 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0])
node credit_available_lo_hi_6 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2])
node credit_available_lo_6 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6)
node credit_available_hi_lo_6 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4])
node credit_available_hi_hi_6 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6])
node credit_available_hi_8 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6)
node _credit_available_T_9 = cat(credit_available_hi_8, credit_available_lo_6)
node credit_available_lo_lo_7 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0])
node credit_available_lo_hi_7 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2])
node credit_available_lo_7 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7)
node credit_available_hi_lo_7 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4])
node credit_available_hi_hi_7 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6])
node credit_available_hi_9 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7)
node _credit_available_T_10 = cat(credit_available_hi_9, credit_available_lo_7)
node credit_available_lo_lo_8 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0])
node credit_available_lo_hi_8 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2])
node credit_available_lo_8 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8)
node credit_available_hi_lo_8 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4])
node credit_available_hi_hi_8 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6])
node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8)
node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_8)
node credit_available_hi_11 = cat(_credit_available_T_11, _credit_available_T_10)
node _credit_available_T_12 = cat(credit_available_hi_11, _credit_available_T_9)
node credit_available_lo_lo_9 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_9 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_9 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9)
node credit_available_hi_lo_9 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_9 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_12 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9)
node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_9)
node credit_available_lo_lo_10 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_10 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_10 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10)
node credit_available_hi_lo_10 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_10 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_13 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10)
node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_10)
node credit_available_lo_lo_11 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_11 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_11 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11)
node credit_available_hi_lo_11 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_11 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_14 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11)
node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_11)
node credit_available_hi_15 = cat(_credit_available_T_15, _credit_available_T_14)
node _credit_available_T_16 = cat(credit_available_hi_15, _credit_available_T_13)
node _credit_available_T_17 = and(_credit_available_T_12, _credit_available_T_16)
node credit_available_1 = neq(_credit_available_T_17, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_101 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_102 = and(_T_101, input_buffer.io.deq[2].bits.tail)
when _T_102 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node credit_available_lo_lo_12 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0])
node credit_available_lo_hi_12 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2])
node credit_available_lo_12 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12)
node credit_available_hi_lo_12 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4])
node credit_available_hi_hi_12 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6])
node credit_available_hi_16 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12)
node _credit_available_T_18 = cat(credit_available_hi_16, credit_available_lo_12)
node credit_available_lo_lo_13 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0])
node credit_available_lo_hi_13 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2])
node credit_available_lo_13 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13)
node credit_available_hi_lo_13 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4])
node credit_available_hi_hi_13 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6])
node credit_available_hi_17 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13)
node _credit_available_T_19 = cat(credit_available_hi_17, credit_available_lo_13)
node credit_available_lo_lo_14 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0])
node credit_available_lo_hi_14 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2])
node credit_available_lo_14 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14)
node credit_available_hi_lo_14 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4])
node credit_available_hi_hi_14 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6])
node credit_available_hi_18 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14)
node _credit_available_T_20 = cat(credit_available_hi_18, credit_available_lo_14)
node credit_available_hi_19 = cat(_credit_available_T_20, _credit_available_T_19)
node _credit_available_T_21 = cat(credit_available_hi_19, _credit_available_T_18)
node credit_available_lo_lo_15 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_15 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_15 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15)
node credit_available_hi_lo_15 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_15 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_20 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15)
node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_15)
node credit_available_lo_lo_16 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_16 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_16 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16)
node credit_available_hi_lo_16 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_16 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_21 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16)
node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_16)
node credit_available_lo_lo_17 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_17 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_17 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17)
node credit_available_hi_lo_17 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_17 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_22 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17)
node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_17)
node credit_available_hi_23 = cat(_credit_available_T_24, _credit_available_T_23)
node _credit_available_T_25 = cat(credit_available_hi_23, _credit_available_T_22)
node _credit_available_T_26 = and(_credit_available_T_21, _credit_available_T_25)
node credit_available_2 = neq(_credit_available_T_26, UInt<1>(0h0))
node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3))
node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_2)
node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid)
connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2
connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7]
connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail
node _T_103 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid)
node _T_104 = and(_T_103, input_buffer.io.deq[3].bits.tail)
when _T_104 :
connect states[3].g, UInt<3>(0h0)
connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready
node credit_available_lo_lo_18 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0])
node credit_available_lo_hi_18 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2])
node credit_available_lo_18 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18)
node credit_available_hi_lo_18 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4])
node credit_available_hi_hi_18 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6])
node credit_available_hi_24 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18)
node _credit_available_T_27 = cat(credit_available_hi_24, credit_available_lo_18)
node credit_available_lo_lo_19 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0])
node credit_available_lo_hi_19 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2])
node credit_available_lo_19 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19)
node credit_available_hi_lo_19 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4])
node credit_available_hi_hi_19 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6])
node credit_available_hi_25 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19)
node _credit_available_T_28 = cat(credit_available_hi_25, credit_available_lo_19)
node credit_available_lo_lo_20 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0])
node credit_available_lo_hi_20 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2])
node credit_available_lo_20 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20)
node credit_available_hi_lo_20 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4])
node credit_available_hi_hi_20 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6])
node credit_available_hi_26 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20)
node _credit_available_T_29 = cat(credit_available_hi_26, credit_available_lo_20)
node credit_available_hi_27 = cat(_credit_available_T_29, _credit_available_T_28)
node _credit_available_T_30 = cat(credit_available_hi_27, _credit_available_T_27)
node credit_available_lo_lo_21 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_21 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_21 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21)
node credit_available_hi_lo_21 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_21 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_28 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21)
node _credit_available_T_31 = cat(credit_available_hi_28, credit_available_lo_21)
node credit_available_lo_lo_22 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_22 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_22 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22)
node credit_available_hi_lo_22 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_22 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_29 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22)
node _credit_available_T_32 = cat(credit_available_hi_29, credit_available_lo_22)
node credit_available_lo_lo_23 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_23 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_23 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23)
node credit_available_hi_lo_23 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_23 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_30 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23)
node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_23)
node credit_available_hi_31 = cat(_credit_available_T_33, _credit_available_T_32)
node _credit_available_T_34 = cat(credit_available_hi_31, _credit_available_T_31)
node _credit_available_T_35 = and(_credit_available_T_30, _credit_available_T_34)
node credit_available_3 = neq(_credit_available_T_35, UInt<1>(0h0))
node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3))
node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_3)
node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid)
connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2
connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7]
connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail
node _T_105 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid)
node _T_106 = and(_T_105, input_buffer.io.deq[4].bits.tail)
when _T_106 :
connect states[4].g, UInt<3>(0h0)
connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready
node credit_available_lo_lo_24 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0])
node credit_available_lo_hi_24 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2])
node credit_available_lo_24 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24)
node credit_available_hi_lo_24 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4])
node credit_available_hi_hi_24 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6])
node credit_available_hi_32 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24)
node _credit_available_T_36 = cat(credit_available_hi_32, credit_available_lo_24)
node credit_available_lo_lo_25 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0])
node credit_available_lo_hi_25 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2])
node credit_available_lo_25 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25)
node credit_available_hi_lo_25 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4])
node credit_available_hi_hi_25 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6])
node credit_available_hi_33 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25)
node _credit_available_T_37 = cat(credit_available_hi_33, credit_available_lo_25)
node credit_available_lo_lo_26 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0])
node credit_available_lo_hi_26 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2])
node credit_available_lo_26 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26)
node credit_available_hi_lo_26 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4])
node credit_available_hi_hi_26 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6])
node credit_available_hi_34 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26)
node _credit_available_T_38 = cat(credit_available_hi_34, credit_available_lo_26)
node credit_available_hi_35 = cat(_credit_available_T_38, _credit_available_T_37)
node _credit_available_T_39 = cat(credit_available_hi_35, _credit_available_T_36)
node credit_available_lo_lo_27 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_27 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_27 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27)
node credit_available_hi_lo_27 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_27 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_36 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27)
node _credit_available_T_40 = cat(credit_available_hi_36, credit_available_lo_27)
node credit_available_lo_lo_28 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_28 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_28 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28)
node credit_available_hi_lo_28 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_28 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_37 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28)
node _credit_available_T_41 = cat(credit_available_hi_37, credit_available_lo_28)
node credit_available_lo_lo_29 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_29 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_29 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29)
node credit_available_hi_lo_29 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_29 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_38 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29)
node _credit_available_T_42 = cat(credit_available_hi_38, credit_available_lo_29)
node credit_available_hi_39 = cat(_credit_available_T_42, _credit_available_T_41)
node _credit_available_T_43 = cat(credit_available_hi_39, _credit_available_T_40)
node _credit_available_T_44 = and(_credit_available_T_39, _credit_available_T_43)
node credit_available_4 = neq(_credit_available_T_44, UInt<1>(0h0))
node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3))
node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_4)
node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid)
connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2
connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7]
connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail
node _T_107 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid)
node _T_108 = and(_T_107, input_buffer.io.deq[5].bits.tail)
when _T_108 :
connect states[5].g, UInt<3>(0h0)
connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready
node credit_available_lo_lo_30 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0])
node credit_available_lo_hi_30 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2])
node credit_available_lo_30 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30)
node credit_available_hi_lo_30 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4])
node credit_available_hi_hi_30 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6])
node credit_available_hi_40 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30)
node _credit_available_T_45 = cat(credit_available_hi_40, credit_available_lo_30)
node credit_available_lo_lo_31 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0])
node credit_available_lo_hi_31 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2])
node credit_available_lo_31 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31)
node credit_available_hi_lo_31 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4])
node credit_available_hi_hi_31 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6])
node credit_available_hi_41 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31)
node _credit_available_T_46 = cat(credit_available_hi_41, credit_available_lo_31)
node credit_available_lo_lo_32 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0])
node credit_available_lo_hi_32 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2])
node credit_available_lo_32 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32)
node credit_available_hi_lo_32 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4])
node credit_available_hi_hi_32 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6])
node credit_available_hi_42 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32)
node _credit_available_T_47 = cat(credit_available_hi_42, credit_available_lo_32)
node credit_available_hi_43 = cat(_credit_available_T_47, _credit_available_T_46)
node _credit_available_T_48 = cat(credit_available_hi_43, _credit_available_T_45)
node credit_available_lo_lo_33 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_33 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_33 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33)
node credit_available_hi_lo_33 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_33 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_44 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33)
node _credit_available_T_49 = cat(credit_available_hi_44, credit_available_lo_33)
node credit_available_lo_lo_34 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_34 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_34 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34)
node credit_available_hi_lo_34 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_34 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_45 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34)
node _credit_available_T_50 = cat(credit_available_hi_45, credit_available_lo_34)
node credit_available_lo_lo_35 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_35 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_35 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35)
node credit_available_hi_lo_35 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_35 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_46 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35)
node _credit_available_T_51 = cat(credit_available_hi_46, credit_available_lo_35)
node credit_available_hi_47 = cat(_credit_available_T_51, _credit_available_T_50)
node _credit_available_T_52 = cat(credit_available_hi_47, _credit_available_T_49)
node _credit_available_T_53 = and(_credit_available_T_48, _credit_available_T_52)
node credit_available_5 = neq(_credit_available_T_53, UInt<1>(0h0))
node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3))
node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_5)
node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid)
connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2
connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7]
connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail
node _T_109 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid)
node _T_110 = and(_T_109, input_buffer.io.deq[6].bits.tail)
when _T_110 :
connect states[6].g, UInt<3>(0h0)
connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready
node credit_available_lo_lo_36 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0])
node credit_available_lo_hi_36 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2])
node credit_available_lo_36 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36)
node credit_available_hi_lo_36 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4])
node credit_available_hi_hi_36 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6])
node credit_available_hi_48 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36)
node _credit_available_T_54 = cat(credit_available_hi_48, credit_available_lo_36)
node credit_available_lo_lo_37 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0])
node credit_available_lo_hi_37 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2])
node credit_available_lo_37 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37)
node credit_available_hi_lo_37 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4])
node credit_available_hi_hi_37 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6])
node credit_available_hi_49 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37)
node _credit_available_T_55 = cat(credit_available_hi_49, credit_available_lo_37)
node credit_available_lo_lo_38 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0])
node credit_available_lo_hi_38 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2])
node credit_available_lo_38 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38)
node credit_available_hi_lo_38 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4])
node credit_available_hi_hi_38 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6])
node credit_available_hi_50 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38)
node _credit_available_T_56 = cat(credit_available_hi_50, credit_available_lo_38)
node credit_available_hi_51 = cat(_credit_available_T_56, _credit_available_T_55)
node _credit_available_T_57 = cat(credit_available_hi_51, _credit_available_T_54)
node credit_available_lo_lo_39 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_39 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_39 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39)
node credit_available_hi_lo_39 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_39 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_52 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39)
node _credit_available_T_58 = cat(credit_available_hi_52, credit_available_lo_39)
node credit_available_lo_lo_40 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_40 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_40 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40)
node credit_available_hi_lo_40 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_40 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_53 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40)
node _credit_available_T_59 = cat(credit_available_hi_53, credit_available_lo_40)
node credit_available_lo_lo_41 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_41 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_41 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41)
node credit_available_hi_lo_41 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_41 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_54 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41)
node _credit_available_T_60 = cat(credit_available_hi_54, credit_available_lo_41)
node credit_available_hi_55 = cat(_credit_available_T_60, _credit_available_T_59)
node _credit_available_T_61 = cat(credit_available_hi_55, _credit_available_T_58)
node _credit_available_T_62 = and(_credit_available_T_57, _credit_available_T_61)
node credit_available_6 = neq(_credit_available_T_62, UInt<1>(0h0))
node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3))
node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_6)
node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid)
connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2
connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7]
connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail
node _T_111 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid)
node _T_112 = and(_T_111, input_buffer.io.deq[7].bits.tail)
when _T_112 :
connect states[7].g, UInt<3>(0h0)
connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8)
node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10)
node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12)
node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14)
node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0)
node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0)
node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19)
node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0)
node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11)
node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0)
node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15)
node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0)
node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25)
node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0)
node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27)
node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_29
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10)
node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11)
node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12)
node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13)
node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14)
node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15)
node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23
node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_25
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2)
node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0)
node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1)
node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1)
node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1)
node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4)
node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _vc_sel_WIRE : UInt<1>[8]
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10)
node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11)
node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12)
node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13)
node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_22
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25)
node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26)
node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27)
node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28)
node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_37
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40)
node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41)
node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42)
node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43)
node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44)
node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_52
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54)
node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55)
node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56)
node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57)
node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58)
node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59)
node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_67
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69)
node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70)
node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71)
node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72)
node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73)
node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74)
node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_82
connect _vc_sel_WIRE[4], _vc_sel_WIRE_5
node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84)
node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85)
node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86)
node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87)
node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88)
node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89)
node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_97
connect _vc_sel_WIRE[5], _vc_sel_WIRE_6
node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99)
node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100)
node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101)
node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102)
node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103)
node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104)
node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_112
connect _vc_sel_WIRE[6], _vc_sel_WIRE_7
node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114)
node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115)
node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116)
node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117)
node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118)
node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119)
node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_127
connect _vc_sel_WIRE[7], _vc_sel_WIRE_8
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_9 : UInt<1>[8]
node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129)
node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130)
node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131)
node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132)
node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133)
node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134)
node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_142
connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10
node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144)
node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145)
node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146)
node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147)
node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148)
node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149)
node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_157
connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11
node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159)
node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160)
node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161)
node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162)
node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163)
node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164)
node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165)
wire _vc_sel_WIRE_12 : UInt<1>
connect _vc_sel_WIRE_12, _vc_sel_T_172
connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12
node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174)
node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175)
node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176)
node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177)
node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178)
node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179)
node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_187
connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13
node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189)
node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190)
node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191)
node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192)
node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193)
node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194)
node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195)
wire _vc_sel_WIRE_14 : UInt<1>
connect _vc_sel_WIRE_14, _vc_sel_T_202
connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14
node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204)
node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205)
node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206)
node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207)
node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208)
node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209)
node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210)
wire _vc_sel_WIRE_15 : UInt<1>
connect _vc_sel_WIRE_15, _vc_sel_T_217
connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15
node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219)
node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220)
node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221)
node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222)
node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223)
node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224)
node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225)
wire _vc_sel_WIRE_16 : UInt<1>
connect _vc_sel_WIRE_16, _vc_sel_T_232
connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16
node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234)
node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235)
node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236)
node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237)
node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238)
node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239)
node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240)
wire _vc_sel_WIRE_17 : UInt<1>
connect _vc_sel_WIRE_17, _vc_sel_T_247
connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17
connect vc_sel.`1`, _vc_sel_WIRE_9
wire _vc_sel_WIRE_18 : UInt<1>[8]
node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249)
node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250)
node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251)
node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252)
node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253)
node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254)
node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255)
wire _vc_sel_WIRE_19 : UInt<1>
connect _vc_sel_WIRE_19, _vc_sel_T_262
connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19
node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264)
node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265)
node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266)
node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267)
node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268)
node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269)
node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270)
wire _vc_sel_WIRE_20 : UInt<1>
connect _vc_sel_WIRE_20, _vc_sel_T_277
connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20
node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279)
node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280)
node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281)
node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282)
node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283)
node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284)
node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285)
wire _vc_sel_WIRE_21 : UInt<1>
connect _vc_sel_WIRE_21, _vc_sel_T_292
connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21
node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294)
node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295)
node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296)
node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297)
node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298)
node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299)
node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300)
wire _vc_sel_WIRE_22 : UInt<1>
connect _vc_sel_WIRE_22, _vc_sel_T_307
connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22
node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309)
node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310)
node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311)
node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312)
node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313)
node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314)
node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315)
wire _vc_sel_WIRE_23 : UInt<1>
connect _vc_sel_WIRE_23, _vc_sel_T_322
connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23
node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324)
node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325)
node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326)
node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327)
node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328)
node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329)
node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330)
wire _vc_sel_WIRE_24 : UInt<1>
connect _vc_sel_WIRE_24, _vc_sel_T_337
connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24
node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339)
node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340)
node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341)
node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342)
node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343)
node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344)
node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345)
wire _vc_sel_WIRE_25 : UInt<1>
connect _vc_sel_WIRE_25, _vc_sel_T_352
connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25
node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354)
node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355)
node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356)
node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357)
node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358)
node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359)
node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360)
wire _vc_sel_WIRE_26 : UInt<1>
connect _vc_sel_WIRE_26, _vc_sel_T_367
connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26
connect vc_sel.`2`, _vc_sel_WIRE_18
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3])
node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4])
node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5])
node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6])
node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7])
node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2])
node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3])
node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4])
node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5])
node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6])
node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7])
node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2])
node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3])
node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4])
node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5])
node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6])
node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7])
node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2])
node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo)
node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4])
node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6])
node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo)
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4)
node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0)
node _virt_channel_T_3 = orr(virt_channel_hi_2)
node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2)
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5)
node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6)
node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0])
node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2])
node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1)
node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4])
node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6])
node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1)
node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3)
node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4)
node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0)
node _virt_channel_T_9 = orr(virt_channel_hi_4)
node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4)
node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2)
node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0)
node _virt_channel_T_11 = orr(virt_channel_hi_5)
node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5)
node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1)
node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13)
node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14)
node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0])
node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2])
node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2)
node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4])
node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6])
node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2)
node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6)
node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4)
node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0)
node _virt_channel_T_17 = orr(virt_channel_hi_7)
node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7)
node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2)
node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0)
node _virt_channel_T_19 = orr(virt_channel_hi_8)
node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8)
node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1)
node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21)
node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22)
node _virt_channel_T_24 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_25 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0))
node _virt_channel_T_26 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0))
node _virt_channel_T_27 = or(_virt_channel_T_24, _virt_channel_T_25)
node _virt_channel_T_28 = or(_virt_channel_T_27, _virt_channel_T_26)
wire virt_channel : UInt<3>
connect virt_channel, _virt_channel_T_28
node _T_113 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_113 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9)
node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10)
node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11)
node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12)
node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13)
node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14)
node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15)
wire _salloc_outs_0_flit_payload_WIRE : UInt<73>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9)
node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10)
node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11)
node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12)
node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13)
node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14)
node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9)
node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10)
node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11)
node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12)
node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13)
node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14)
node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10)
node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11)
node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12)
node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13)
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25)
node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26)
node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27)
node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28)
node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29)
node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39)
node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40)
node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41)
node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42)
node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43)
node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44)
node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54)
node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55)
node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56)
node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57)
node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58)
node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59)
node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69)
node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70)
node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71)
node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72)
node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73)
node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74)
node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
invalidate states[0].fifo_deps
invalidate states[0].flow.egress_node_id
invalidate states[0].flow.egress_node
invalidate states[0].flow.ingress_node_id
invalidate states[0].flow.ingress_node
invalidate states[0].flow.vnet_id
invalidate states[0].vc_sel.`0`[0]
invalidate states[0].vc_sel.`0`[1]
invalidate states[0].vc_sel.`0`[2]
invalidate states[0].vc_sel.`0`[3]
invalidate states[0].vc_sel.`0`[4]
invalidate states[0].vc_sel.`0`[5]
invalidate states[0].vc_sel.`0`[6]
invalidate states[0].vc_sel.`0`[7]
invalidate states[0].vc_sel.`1`[0]
invalidate states[0].vc_sel.`1`[1]
invalidate states[0].vc_sel.`1`[2]
invalidate states[0].vc_sel.`1`[3]
invalidate states[0].vc_sel.`1`[4]
invalidate states[0].vc_sel.`1`[5]
invalidate states[0].vc_sel.`1`[6]
invalidate states[0].vc_sel.`1`[7]
invalidate states[0].vc_sel.`2`[0]
invalidate states[0].vc_sel.`2`[1]
invalidate states[0].vc_sel.`2`[2]
invalidate states[0].vc_sel.`2`[3]
invalidate states[0].vc_sel.`2`[4]
invalidate states[0].vc_sel.`2`[5]
invalidate states[0].vc_sel.`2`[6]
invalidate states[0].vc_sel.`2`[7]
invalidate states[0].g
connect states[1].vc_sel.`0`[0], UInt<1>(0h0)
connect states[1].vc_sel.`1`[0], UInt<1>(0h0)
connect states[1].vc_sel.`1`[1], UInt<1>(0h0)
connect states[1].vc_sel.`1`[2], UInt<1>(0h0)
connect states[1].vc_sel.`1`[3], UInt<1>(0h0)
connect states[1].vc_sel.`1`[4], UInt<1>(0h0)
connect states[1].vc_sel.`1`[5], UInt<1>(0h0)
connect states[1].vc_sel.`1`[6], UInt<1>(0h0)
connect states[1].vc_sel.`1`[7], UInt<1>(0h0)
connect states[1].vc_sel.`2`[0], UInt<1>(0h0)
connect states[1].vc_sel.`2`[1], UInt<1>(0h0)
connect states[1].vc_sel.`2`[2], UInt<1>(0h0)
connect states[1].vc_sel.`2`[3], UInt<1>(0h0)
connect states[1].vc_sel.`2`[4], UInt<1>(0h0)
connect states[1].vc_sel.`2`[5], UInt<1>(0h0)
connect states[1].vc_sel.`2`[6], UInt<1>(0h0)
connect states[1].vc_sel.`2`[7], UInt<1>(0h0)
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`1`[0], UInt<1>(0h0)
connect states[2].vc_sel.`1`[1], UInt<1>(0h0)
connect states[2].vc_sel.`1`[2], UInt<1>(0h0)
connect states[2].vc_sel.`1`[3], UInt<1>(0h0)
connect states[2].vc_sel.`1`[4], UInt<1>(0h0)
connect states[2].vc_sel.`1`[5], UInt<1>(0h0)
connect states[2].vc_sel.`1`[6], UInt<1>(0h0)
connect states[2].vc_sel.`1`[7], UInt<1>(0h0)
connect states[2].vc_sel.`2`[0], UInt<1>(0h0)
connect states[3].vc_sel.`0`[0], UInt<1>(0h0)
connect states[3].vc_sel.`1`[0], UInt<1>(0h0)
connect states[3].vc_sel.`1`[1], UInt<1>(0h0)
connect states[3].vc_sel.`1`[2], UInt<1>(0h0)
connect states[3].vc_sel.`1`[3], UInt<1>(0h0)
connect states[3].vc_sel.`1`[4], UInt<1>(0h0)
connect states[3].vc_sel.`1`[5], UInt<1>(0h0)
connect states[3].vc_sel.`1`[6], UInt<1>(0h0)
connect states[3].vc_sel.`1`[7], UInt<1>(0h0)
connect states[3].vc_sel.`2`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[0], UInt<1>(0h0)
connect states[4].vc_sel.`1`[0], UInt<1>(0h0)
connect states[4].vc_sel.`1`[1], UInt<1>(0h0)
connect states[4].vc_sel.`1`[2], UInt<1>(0h0)
connect states[4].vc_sel.`1`[3], UInt<1>(0h0)
connect states[4].vc_sel.`1`[4], UInt<1>(0h0)
connect states[4].vc_sel.`1`[5], UInt<1>(0h0)
connect states[4].vc_sel.`1`[6], UInt<1>(0h0)
connect states[4].vc_sel.`1`[7], UInt<1>(0h0)
connect states[4].vc_sel.`2`[0], UInt<1>(0h0)
connect states[5].vc_sel.`0`[0], UInt<1>(0h0)
connect states[5].vc_sel.`1`[0], UInt<1>(0h0)
connect states[5].vc_sel.`1`[1], UInt<1>(0h0)
connect states[5].vc_sel.`1`[2], UInt<1>(0h0)
connect states[5].vc_sel.`1`[3], UInt<1>(0h0)
connect states[5].vc_sel.`1`[4], UInt<1>(0h0)
connect states[5].vc_sel.`1`[5], UInt<1>(0h0)
connect states[5].vc_sel.`1`[6], UInt<1>(0h0)
connect states[5].vc_sel.`1`[7], UInt<1>(0h0)
connect states[5].vc_sel.`2`[0], UInt<1>(0h0)
connect states[6].vc_sel.`0`[0], UInt<1>(0h0)
connect states[6].vc_sel.`1`[0], UInt<1>(0h0)
connect states[6].vc_sel.`1`[1], UInt<1>(0h0)
connect states[6].vc_sel.`1`[2], UInt<1>(0h0)
connect states[6].vc_sel.`1`[3], UInt<1>(0h0)
connect states[6].vc_sel.`1`[4], UInt<1>(0h0)
connect states[6].vc_sel.`1`[5], UInt<1>(0h0)
connect states[6].vc_sel.`1`[6], UInt<1>(0h0)
connect states[6].vc_sel.`1`[7], UInt<1>(0h0)
connect states[6].vc_sel.`2`[0], UInt<1>(0h0)
connect states[7].vc_sel.`0`[0], UInt<1>(0h0)
connect states[7].vc_sel.`1`[0], UInt<1>(0h0)
connect states[7].vc_sel.`1`[1], UInt<1>(0h0)
connect states[7].vc_sel.`1`[2], UInt<1>(0h0)
connect states[7].vc_sel.`1`[3], UInt<1>(0h0)
connect states[7].vc_sel.`1`[4], UInt<1>(0h0)
connect states[7].vc_sel.`1`[5], UInt<1>(0h0)
connect states[7].vc_sel.`1`[6], UInt<1>(0h0)
connect states[7].vc_sel.`1`[7], UInt<1>(0h0)
connect states[7].vc_sel.`2`[0], UInt<1>(0h0)
node _T_114 = asUInt(reset)
when _T_114 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0)
connect states[4].g, UInt<3>(0h0)
connect states[5].g, UInt<3>(0h0)
connect states[6].g, UInt<3>(0h0)
connect states[7].g, UInt<3>(0h0) | module InputUnit_64( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [7:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [7:0] mask; // @[InputUnit.scala:250:21]
wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_6 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_7 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_72 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_104
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_72( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_104 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_11 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
wire _source_ok_WIRE : UInt<1>[5]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
node _source_ok_T_25 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_26 = or(_source_ok_T_25, _source_ok_WIRE[2])
node _source_ok_T_27 = or(_source_ok_T_26, _source_ok_WIRE[3])
node source_ok = or(_source_ok_T_27, _source_ok_WIRE[4])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = and(_T_11, _T_24)
node _T_65 = and(_T_64, _T_37)
node _T_66 = and(_T_65, _T_50)
node _T_67 = and(_T_66, _T_63)
node _T_68 = asUInt(reset)
node _T_69 = eq(_T_68, UInt<1>(0h0))
when _T_69 :
node _T_70 = eq(_T_67, UInt<1>(0h0))
when _T_70 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_67, UInt<1>(0h1), "") : assert_1
node _T_71 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_71 :
node _T_72 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_73 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_74 = and(_T_72, _T_73)
node _T_75 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_76 = shr(io.in.a.bits.source, 2)
node _T_77 = eq(_T_76, UInt<1>(0h0))
node _T_78 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_79 = and(_T_77, _T_78)
node _T_80 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_81 = and(_T_79, _T_80)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_82 = shr(io.in.a.bits.source, 2)
node _T_83 = eq(_T_82, UInt<1>(0h1))
node _T_84 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_85 = and(_T_83, _T_84)
node _T_86 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_87 = and(_T_85, _T_86)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_88 = shr(io.in.a.bits.source, 2)
node _T_89 = eq(_T_88, UInt<2>(0h2))
node _T_90 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_91 = and(_T_89, _T_90)
node _T_92 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_93 = and(_T_91, _T_92)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_94 = shr(io.in.a.bits.source, 2)
node _T_95 = eq(_T_94, UInt<2>(0h3))
node _T_96 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_97 = and(_T_95, _T_96)
node _T_98 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_99 = and(_T_97, _T_98)
node _T_100 = or(_T_75, _T_81)
node _T_101 = or(_T_100, _T_87)
node _T_102 = or(_T_101, _T_93)
node _T_103 = or(_T_102, _T_99)
node _T_104 = and(_T_74, _T_103)
node _T_105 = or(UInt<1>(0h0), _T_104)
node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_107 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<14>(0h2000)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<10>(0h200)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_118 = cvt(_T_117)
node _T_119 = and(_T_118, asSInt(UInt<13>(0h1000)))
node _T_120 = asSInt(_T_119)
node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0)))
node _T_122 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<17>(0h10000)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_128 = cvt(_T_127)
node _T_129 = and(_T_128, asSInt(UInt<18>(0h2f000)))
node _T_130 = asSInt(_T_129)
node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0)))
node _T_132 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_133 = cvt(_T_132)
node _T_134 = and(_T_133, asSInt(UInt<17>(0h10000)))
node _T_135 = asSInt(_T_134)
node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0)))
node _T_137 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_138 = cvt(_T_137)
node _T_139 = and(_T_138, asSInt(UInt<13>(0h1000)))
node _T_140 = asSInt(_T_139)
node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0)))
node _T_142 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_143 = cvt(_T_142)
node _T_144 = and(_T_143, asSInt(UInt<27>(0h4000000)))
node _T_145 = asSInt(_T_144)
node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0)))
node _T_147 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_148 = cvt(_T_147)
node _T_149 = and(_T_148, asSInt(UInt<13>(0h1000)))
node _T_150 = asSInt(_T_149)
node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0)))
node _T_152 = or(_T_111, _T_116)
node _T_153 = or(_T_152, _T_121)
node _T_154 = or(_T_153, _T_126)
node _T_155 = or(_T_154, _T_131)
node _T_156 = or(_T_155, _T_136)
node _T_157 = or(_T_156, _T_141)
node _T_158 = or(_T_157, _T_146)
node _T_159 = or(_T_158, _T_151)
node _T_160 = and(_T_106, _T_159)
node _T_161 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_162 = or(UInt<1>(0h0), _T_161)
node _T_163 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_164 = cvt(_T_163)
node _T_165 = and(_T_164, asSInt(UInt<17>(0h10000)))
node _T_166 = asSInt(_T_165)
node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0)))
node _T_168 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_169 = cvt(_T_168)
node _T_170 = and(_T_169, asSInt(UInt<29>(0h10000000)))
node _T_171 = asSInt(_T_170)
node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = or(_T_167, _T_172)
node _T_174 = and(_T_162, _T_173)
node _T_175 = or(UInt<1>(0h0), _T_160)
node _T_176 = or(_T_175, _T_174)
node _T_177 = and(_T_105, _T_176)
node _T_178 = asUInt(reset)
node _T_179 = eq(_T_178, UInt<1>(0h0))
when _T_179 :
node _T_180 = eq(_T_177, UInt<1>(0h0))
when _T_180 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_177, UInt<1>(0h1), "") : assert_2
node _T_181 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_182 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_183 = and(_T_181, _T_182)
node _T_184 = or(UInt<1>(0h0), _T_183)
node _T_185 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_186 = cvt(_T_185)
node _T_187 = and(_T_186, asSInt(UInt<14>(0h2000)))
node _T_188 = asSInt(_T_187)
node _T_189 = eq(_T_188, asSInt(UInt<1>(0h0)))
node _T_190 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_191 = cvt(_T_190)
node _T_192 = and(_T_191, asSInt(UInt<10>(0h200)))
node _T_193 = asSInt(_T_192)
node _T_194 = eq(_T_193, asSInt(UInt<1>(0h0)))
node _T_195 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_196 = cvt(_T_195)
node _T_197 = and(_T_196, asSInt(UInt<13>(0h1000)))
node _T_198 = asSInt(_T_197)
node _T_199 = eq(_T_198, asSInt(UInt<1>(0h0)))
node _T_200 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_201 = cvt(_T_200)
node _T_202 = and(_T_201, asSInt(UInt<17>(0h10000)))
node _T_203 = asSInt(_T_202)
node _T_204 = eq(_T_203, asSInt(UInt<1>(0h0)))
node _T_205 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_206 = cvt(_T_205)
node _T_207 = and(_T_206, asSInt(UInt<18>(0h2f000)))
node _T_208 = asSInt(_T_207)
node _T_209 = eq(_T_208, asSInt(UInt<1>(0h0)))
node _T_210 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_211 = cvt(_T_210)
node _T_212 = and(_T_211, asSInt(UInt<17>(0h10000)))
node _T_213 = asSInt(_T_212)
node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0)))
node _T_215 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_216 = cvt(_T_215)
node _T_217 = and(_T_216, asSInt(UInt<13>(0h1000)))
node _T_218 = asSInt(_T_217)
node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0)))
node _T_220 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_221 = cvt(_T_220)
node _T_222 = and(_T_221, asSInt(UInt<17>(0h10000)))
node _T_223 = asSInt(_T_222)
node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0)))
node _T_225 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_226 = cvt(_T_225)
node _T_227 = and(_T_226, asSInt(UInt<27>(0h4000000)))
node _T_228 = asSInt(_T_227)
node _T_229 = eq(_T_228, asSInt(UInt<1>(0h0)))
node _T_230 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_231 = cvt(_T_230)
node _T_232 = and(_T_231, asSInt(UInt<13>(0h1000)))
node _T_233 = asSInt(_T_232)
node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0)))
node _T_235 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_236 = cvt(_T_235)
node _T_237 = and(_T_236, asSInt(UInt<29>(0h10000000)))
node _T_238 = asSInt(_T_237)
node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0)))
node _T_240 = or(_T_189, _T_194)
node _T_241 = or(_T_240, _T_199)
node _T_242 = or(_T_241, _T_204)
node _T_243 = or(_T_242, _T_209)
node _T_244 = or(_T_243, _T_214)
node _T_245 = or(_T_244, _T_219)
node _T_246 = or(_T_245, _T_224)
node _T_247 = or(_T_246, _T_229)
node _T_248 = or(_T_247, _T_234)
node _T_249 = or(_T_248, _T_239)
node _T_250 = and(_T_184, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = and(UInt<1>(0h0), _T_251)
node _T_253 = asUInt(reset)
node _T_254 = eq(_T_253, UInt<1>(0h0))
when _T_254 :
node _T_255 = eq(_T_252, UInt<1>(0h0))
when _T_255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_252, UInt<1>(0h1), "") : assert_3
node _T_256 = asUInt(reset)
node _T_257 = eq(_T_256, UInt<1>(0h0))
when _T_257 :
node _T_258 = eq(source_ok, UInt<1>(0h0))
when _T_258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_259 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_259, UInt<1>(0h1), "") : assert_5
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(is_aligned, UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_266 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_267 = asUInt(reset)
node _T_268 = eq(_T_267, UInt<1>(0h0))
when _T_268 :
node _T_269 = eq(_T_266, UInt<1>(0h0))
when _T_269 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_266, UInt<1>(0h1), "") : assert_7
node _T_270 = not(io.in.a.bits.mask)
node _T_271 = eq(_T_270, UInt<1>(0h0))
node _T_272 = asUInt(reset)
node _T_273 = eq(_T_272, UInt<1>(0h0))
when _T_273 :
node _T_274 = eq(_T_271, UInt<1>(0h0))
when _T_274 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_271, UInt<1>(0h1), "") : assert_8
node _T_275 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_275, UInt<1>(0h1), "") : assert_9
node _T_279 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _T_283 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_284 = shr(io.in.a.bits.source, 2)
node _T_285 = eq(_T_284, UInt<1>(0h0))
node _T_286 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_287 = and(_T_285, _T_286)
node _T_288 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_289 = and(_T_287, _T_288)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_290 = shr(io.in.a.bits.source, 2)
node _T_291 = eq(_T_290, UInt<1>(0h1))
node _T_292 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_293 = and(_T_291, _T_292)
node _T_294 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_295 = and(_T_293, _T_294)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_296 = shr(io.in.a.bits.source, 2)
node _T_297 = eq(_T_296, UInt<2>(0h2))
node _T_298 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_299 = and(_T_297, _T_298)
node _T_300 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_301 = and(_T_299, _T_300)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_302 = shr(io.in.a.bits.source, 2)
node _T_303 = eq(_T_302, UInt<2>(0h3))
node _T_304 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_305 = and(_T_303, _T_304)
node _T_306 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_307 = and(_T_305, _T_306)
node _T_308 = or(_T_283, _T_289)
node _T_309 = or(_T_308, _T_295)
node _T_310 = or(_T_309, _T_301)
node _T_311 = or(_T_310, _T_307)
node _T_312 = and(_T_282, _T_311)
node _T_313 = or(UInt<1>(0h0), _T_312)
node _T_314 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_315 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_316 = cvt(_T_315)
node _T_317 = and(_T_316, asSInt(UInt<14>(0h2000)))
node _T_318 = asSInt(_T_317)
node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0)))
node _T_320 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_321 = cvt(_T_320)
node _T_322 = and(_T_321, asSInt(UInt<10>(0h200)))
node _T_323 = asSInt(_T_322)
node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0)))
node _T_325 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_326 = cvt(_T_325)
node _T_327 = and(_T_326, asSInt(UInt<13>(0h1000)))
node _T_328 = asSInt(_T_327)
node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0)))
node _T_330 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_336 = cvt(_T_335)
node _T_337 = and(_T_336, asSInt(UInt<18>(0h2f000)))
node _T_338 = asSInt(_T_337)
node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0)))
node _T_340 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_341 = cvt(_T_340)
node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000)))
node _T_343 = asSInt(_T_342)
node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0)))
node _T_345 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_346 = cvt(_T_345)
node _T_347 = and(_T_346, asSInt(UInt<13>(0h1000)))
node _T_348 = asSInt(_T_347)
node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0)))
node _T_350 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_351 = cvt(_T_350)
node _T_352 = and(_T_351, asSInt(UInt<27>(0h4000000)))
node _T_353 = asSInt(_T_352)
node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0)))
node _T_355 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_356 = cvt(_T_355)
node _T_357 = and(_T_356, asSInt(UInt<13>(0h1000)))
node _T_358 = asSInt(_T_357)
node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0)))
node _T_360 = or(_T_319, _T_324)
node _T_361 = or(_T_360, _T_329)
node _T_362 = or(_T_361, _T_334)
node _T_363 = or(_T_362, _T_339)
node _T_364 = or(_T_363, _T_344)
node _T_365 = or(_T_364, _T_349)
node _T_366 = or(_T_365, _T_354)
node _T_367 = or(_T_366, _T_359)
node _T_368 = and(_T_314, _T_367)
node _T_369 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_370 = or(UInt<1>(0h0), _T_369)
node _T_371 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_372 = cvt(_T_371)
node _T_373 = and(_T_372, asSInt(UInt<17>(0h10000)))
node _T_374 = asSInt(_T_373)
node _T_375 = eq(_T_374, asSInt(UInt<1>(0h0)))
node _T_376 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_377 = cvt(_T_376)
node _T_378 = and(_T_377, asSInt(UInt<29>(0h10000000)))
node _T_379 = asSInt(_T_378)
node _T_380 = eq(_T_379, asSInt(UInt<1>(0h0)))
node _T_381 = or(_T_375, _T_380)
node _T_382 = and(_T_370, _T_381)
node _T_383 = or(UInt<1>(0h0), _T_368)
node _T_384 = or(_T_383, _T_382)
node _T_385 = and(_T_313, _T_384)
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_385, UInt<1>(0h1), "") : assert_10
node _T_389 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_390 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_391 = and(_T_389, _T_390)
node _T_392 = or(UInt<1>(0h0), _T_391)
node _T_393 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_394 = cvt(_T_393)
node _T_395 = and(_T_394, asSInt(UInt<14>(0h2000)))
node _T_396 = asSInt(_T_395)
node _T_397 = eq(_T_396, asSInt(UInt<1>(0h0)))
node _T_398 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_399 = cvt(_T_398)
node _T_400 = and(_T_399, asSInt(UInt<10>(0h200)))
node _T_401 = asSInt(_T_400)
node _T_402 = eq(_T_401, asSInt(UInt<1>(0h0)))
node _T_403 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_404 = cvt(_T_403)
node _T_405 = and(_T_404, asSInt(UInt<13>(0h1000)))
node _T_406 = asSInt(_T_405)
node _T_407 = eq(_T_406, asSInt(UInt<1>(0h0)))
node _T_408 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_409 = cvt(_T_408)
node _T_410 = and(_T_409, asSInt(UInt<17>(0h10000)))
node _T_411 = asSInt(_T_410)
node _T_412 = eq(_T_411, asSInt(UInt<1>(0h0)))
node _T_413 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_414 = cvt(_T_413)
node _T_415 = and(_T_414, asSInt(UInt<18>(0h2f000)))
node _T_416 = asSInt(_T_415)
node _T_417 = eq(_T_416, asSInt(UInt<1>(0h0)))
node _T_418 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_419 = cvt(_T_418)
node _T_420 = and(_T_419, asSInt(UInt<17>(0h10000)))
node _T_421 = asSInt(_T_420)
node _T_422 = eq(_T_421, asSInt(UInt<1>(0h0)))
node _T_423 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_424 = cvt(_T_423)
node _T_425 = and(_T_424, asSInt(UInt<13>(0h1000)))
node _T_426 = asSInt(_T_425)
node _T_427 = eq(_T_426, asSInt(UInt<1>(0h0)))
node _T_428 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_429 = cvt(_T_428)
node _T_430 = and(_T_429, asSInt(UInt<17>(0h10000)))
node _T_431 = asSInt(_T_430)
node _T_432 = eq(_T_431, asSInt(UInt<1>(0h0)))
node _T_433 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_434 = cvt(_T_433)
node _T_435 = and(_T_434, asSInt(UInt<27>(0h4000000)))
node _T_436 = asSInt(_T_435)
node _T_437 = eq(_T_436, asSInt(UInt<1>(0h0)))
node _T_438 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_439 = cvt(_T_438)
node _T_440 = and(_T_439, asSInt(UInt<13>(0h1000)))
node _T_441 = asSInt(_T_440)
node _T_442 = eq(_T_441, asSInt(UInt<1>(0h0)))
node _T_443 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_444 = cvt(_T_443)
node _T_445 = and(_T_444, asSInt(UInt<29>(0h10000000)))
node _T_446 = asSInt(_T_445)
node _T_447 = eq(_T_446, asSInt(UInt<1>(0h0)))
node _T_448 = or(_T_397, _T_402)
node _T_449 = or(_T_448, _T_407)
node _T_450 = or(_T_449, _T_412)
node _T_451 = or(_T_450, _T_417)
node _T_452 = or(_T_451, _T_422)
node _T_453 = or(_T_452, _T_427)
node _T_454 = or(_T_453, _T_432)
node _T_455 = or(_T_454, _T_437)
node _T_456 = or(_T_455, _T_442)
node _T_457 = or(_T_456, _T_447)
node _T_458 = and(_T_392, _T_457)
node _T_459 = or(UInt<1>(0h0), _T_458)
node _T_460 = and(UInt<1>(0h0), _T_459)
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_460, UInt<1>(0h1), "") : assert_11
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(source_ok, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_467 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(_T_467, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_467, UInt<1>(0h1), "") : assert_13
node _T_471 = asUInt(reset)
node _T_472 = eq(_T_471, UInt<1>(0h0))
when _T_472 :
node _T_473 = eq(is_aligned, UInt<1>(0h0))
when _T_473 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_474 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_474, UInt<1>(0h1), "") : assert_15
node _T_478 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_T_478, UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_478, UInt<1>(0h1), "") : assert_16
node _T_482 = not(io.in.a.bits.mask)
node _T_483 = eq(_T_482, UInt<1>(0h0))
node _T_484 = asUInt(reset)
node _T_485 = eq(_T_484, UInt<1>(0h0))
when _T_485 :
node _T_486 = eq(_T_483, UInt<1>(0h0))
when _T_486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_483, UInt<1>(0h1), "") : assert_17
node _T_487 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_488 = asUInt(reset)
node _T_489 = eq(_T_488, UInt<1>(0h0))
when _T_489 :
node _T_490 = eq(_T_487, UInt<1>(0h0))
when _T_490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_487, UInt<1>(0h1), "") : assert_18
node _T_491 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_491 :
node _T_492 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_493 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_496 = shr(io.in.a.bits.source, 2)
node _T_497 = eq(_T_496, UInt<1>(0h0))
node _T_498 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_499 = and(_T_497, _T_498)
node _T_500 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_501 = and(_T_499, _T_500)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_502 = shr(io.in.a.bits.source, 2)
node _T_503 = eq(_T_502, UInt<1>(0h1))
node _T_504 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_505 = and(_T_503, _T_504)
node _T_506 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_507 = and(_T_505, _T_506)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_508 = shr(io.in.a.bits.source, 2)
node _T_509 = eq(_T_508, UInt<2>(0h2))
node _T_510 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_511 = and(_T_509, _T_510)
node _T_512 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_513 = and(_T_511, _T_512)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_514 = shr(io.in.a.bits.source, 2)
node _T_515 = eq(_T_514, UInt<2>(0h3))
node _T_516 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_517 = and(_T_515, _T_516)
node _T_518 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_519 = and(_T_517, _T_518)
node _T_520 = or(_T_495, _T_501)
node _T_521 = or(_T_520, _T_507)
node _T_522 = or(_T_521, _T_513)
node _T_523 = or(_T_522, _T_519)
node _T_524 = and(_T_494, _T_523)
node _T_525 = or(UInt<1>(0h0), _T_524)
node _T_526 = asUInt(reset)
node _T_527 = eq(_T_526, UInt<1>(0h0))
when _T_527 :
node _T_528 = eq(_T_525, UInt<1>(0h0))
when _T_528 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_525, UInt<1>(0h1), "") : assert_19
node _T_529 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_530 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_531 = and(_T_529, _T_530)
node _T_532 = or(UInt<1>(0h0), _T_531)
node _T_533 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_534 = cvt(_T_533)
node _T_535 = and(_T_534, asSInt(UInt<13>(0h1000)))
node _T_536 = asSInt(_T_535)
node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0)))
node _T_538 = and(_T_532, _T_537)
node _T_539 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_540 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_541 = and(_T_539, _T_540)
node _T_542 = or(UInt<1>(0h0), _T_541)
node _T_543 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_544 = cvt(_T_543)
node _T_545 = and(_T_544, asSInt(UInt<14>(0h2000)))
node _T_546 = asSInt(_T_545)
node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0)))
node _T_548 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_549 = cvt(_T_548)
node _T_550 = and(_T_549, asSInt(UInt<10>(0h200)))
node _T_551 = asSInt(_T_550)
node _T_552 = eq(_T_551, asSInt(UInt<1>(0h0)))
node _T_553 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_554 = cvt(_T_553)
node _T_555 = and(_T_554, asSInt(UInt<17>(0h10000)))
node _T_556 = asSInt(_T_555)
node _T_557 = eq(_T_556, asSInt(UInt<1>(0h0)))
node _T_558 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_559 = cvt(_T_558)
node _T_560 = and(_T_559, asSInt(UInt<18>(0h2f000)))
node _T_561 = asSInt(_T_560)
node _T_562 = eq(_T_561, asSInt(UInt<1>(0h0)))
node _T_563 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_564 = cvt(_T_563)
node _T_565 = and(_T_564, asSInt(UInt<17>(0h10000)))
node _T_566 = asSInt(_T_565)
node _T_567 = eq(_T_566, asSInt(UInt<1>(0h0)))
node _T_568 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_569 = cvt(_T_568)
node _T_570 = and(_T_569, asSInt(UInt<13>(0h1000)))
node _T_571 = asSInt(_T_570)
node _T_572 = eq(_T_571, asSInt(UInt<1>(0h0)))
node _T_573 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_574 = cvt(_T_573)
node _T_575 = and(_T_574, asSInt(UInt<17>(0h10000)))
node _T_576 = asSInt(_T_575)
node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0)))
node _T_578 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_579 = cvt(_T_578)
node _T_580 = and(_T_579, asSInt(UInt<27>(0h4000000)))
node _T_581 = asSInt(_T_580)
node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0)))
node _T_583 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_584 = cvt(_T_583)
node _T_585 = and(_T_584, asSInt(UInt<13>(0h1000)))
node _T_586 = asSInt(_T_585)
node _T_587 = eq(_T_586, asSInt(UInt<1>(0h0)))
node _T_588 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_589 = cvt(_T_588)
node _T_590 = and(_T_589, asSInt(UInt<29>(0h10000000)))
node _T_591 = asSInt(_T_590)
node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0)))
node _T_593 = or(_T_547, _T_552)
node _T_594 = or(_T_593, _T_557)
node _T_595 = or(_T_594, _T_562)
node _T_596 = or(_T_595, _T_567)
node _T_597 = or(_T_596, _T_572)
node _T_598 = or(_T_597, _T_577)
node _T_599 = or(_T_598, _T_582)
node _T_600 = or(_T_599, _T_587)
node _T_601 = or(_T_600, _T_592)
node _T_602 = and(_T_542, _T_601)
node _T_603 = or(UInt<1>(0h0), _T_538)
node _T_604 = or(_T_603, _T_602)
node _T_605 = asUInt(reset)
node _T_606 = eq(_T_605, UInt<1>(0h0))
when _T_606 :
node _T_607 = eq(_T_604, UInt<1>(0h0))
when _T_607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_604, UInt<1>(0h1), "") : assert_20
node _T_608 = asUInt(reset)
node _T_609 = eq(_T_608, UInt<1>(0h0))
when _T_609 :
node _T_610 = eq(source_ok, UInt<1>(0h0))
when _T_610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_611 = asUInt(reset)
node _T_612 = eq(_T_611, UInt<1>(0h0))
when _T_612 :
node _T_613 = eq(is_aligned, UInt<1>(0h0))
when _T_613 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_614 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_614, UInt<1>(0h1), "") : assert_23
node _T_618 = eq(io.in.a.bits.mask, mask)
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_618, UInt<1>(0h1), "") : assert_24
node _T_622 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_622, UInt<1>(0h1), "") : assert_25
node _T_626 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_626 :
node _T_627 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_628 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_629 = and(_T_627, _T_628)
node _T_630 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_631 = shr(io.in.a.bits.source, 2)
node _T_632 = eq(_T_631, UInt<1>(0h0))
node _T_633 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_634 = and(_T_632, _T_633)
node _T_635 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_636 = and(_T_634, _T_635)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_637 = shr(io.in.a.bits.source, 2)
node _T_638 = eq(_T_637, UInt<1>(0h1))
node _T_639 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_640 = and(_T_638, _T_639)
node _T_641 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_642 = and(_T_640, _T_641)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_643 = shr(io.in.a.bits.source, 2)
node _T_644 = eq(_T_643, UInt<2>(0h2))
node _T_645 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_646 = and(_T_644, _T_645)
node _T_647 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_648 = and(_T_646, _T_647)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_649 = shr(io.in.a.bits.source, 2)
node _T_650 = eq(_T_649, UInt<2>(0h3))
node _T_651 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_652 = and(_T_650, _T_651)
node _T_653 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_654 = and(_T_652, _T_653)
node _T_655 = or(_T_630, _T_636)
node _T_656 = or(_T_655, _T_642)
node _T_657 = or(_T_656, _T_648)
node _T_658 = or(_T_657, _T_654)
node _T_659 = and(_T_629, _T_658)
node _T_660 = or(UInt<1>(0h0), _T_659)
node _T_661 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_662 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_663 = and(_T_661, _T_662)
node _T_664 = or(UInt<1>(0h0), _T_663)
node _T_665 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_666 = cvt(_T_665)
node _T_667 = and(_T_666, asSInt(UInt<13>(0h1000)))
node _T_668 = asSInt(_T_667)
node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0)))
node _T_670 = and(_T_664, _T_669)
node _T_671 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_672 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_673 = and(_T_671, _T_672)
node _T_674 = or(UInt<1>(0h0), _T_673)
node _T_675 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_676 = cvt(_T_675)
node _T_677 = and(_T_676, asSInt(UInt<14>(0h2000)))
node _T_678 = asSInt(_T_677)
node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0)))
node _T_680 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_681 = cvt(_T_680)
node _T_682 = and(_T_681, asSInt(UInt<10>(0h200)))
node _T_683 = asSInt(_T_682)
node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0)))
node _T_685 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_686 = cvt(_T_685)
node _T_687 = and(_T_686, asSInt(UInt<18>(0h2f000)))
node _T_688 = asSInt(_T_687)
node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0)))
node _T_690 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_691 = cvt(_T_690)
node _T_692 = and(_T_691, asSInt(UInt<17>(0h10000)))
node _T_693 = asSInt(_T_692)
node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0)))
node _T_695 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_696 = cvt(_T_695)
node _T_697 = and(_T_696, asSInt(UInt<13>(0h1000)))
node _T_698 = asSInt(_T_697)
node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0)))
node _T_700 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_701 = cvt(_T_700)
node _T_702 = and(_T_701, asSInt(UInt<17>(0h10000)))
node _T_703 = asSInt(_T_702)
node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0)))
node _T_705 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_706 = cvt(_T_705)
node _T_707 = and(_T_706, asSInt(UInt<27>(0h4000000)))
node _T_708 = asSInt(_T_707)
node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0)))
node _T_710 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_711 = cvt(_T_710)
node _T_712 = and(_T_711, asSInt(UInt<13>(0h1000)))
node _T_713 = asSInt(_T_712)
node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0)))
node _T_715 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_716 = cvt(_T_715)
node _T_717 = and(_T_716, asSInt(UInt<29>(0h10000000)))
node _T_718 = asSInt(_T_717)
node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0)))
node _T_720 = or(_T_679, _T_684)
node _T_721 = or(_T_720, _T_689)
node _T_722 = or(_T_721, _T_694)
node _T_723 = or(_T_722, _T_699)
node _T_724 = or(_T_723, _T_704)
node _T_725 = or(_T_724, _T_709)
node _T_726 = or(_T_725, _T_714)
node _T_727 = or(_T_726, _T_719)
node _T_728 = and(_T_674, _T_727)
node _T_729 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_730 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_731 = cvt(_T_730)
node _T_732 = and(_T_731, asSInt(UInt<17>(0h10000)))
node _T_733 = asSInt(_T_732)
node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0)))
node _T_735 = and(_T_729, _T_734)
node _T_736 = or(UInt<1>(0h0), _T_670)
node _T_737 = or(_T_736, _T_728)
node _T_738 = or(_T_737, _T_735)
node _T_739 = and(_T_660, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_739, UInt<1>(0h1), "") : assert_26
node _T_743 = asUInt(reset)
node _T_744 = eq(_T_743, UInt<1>(0h0))
when _T_744 :
node _T_745 = eq(source_ok, UInt<1>(0h0))
when _T_745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_746 = asUInt(reset)
node _T_747 = eq(_T_746, UInt<1>(0h0))
when _T_747 :
node _T_748 = eq(is_aligned, UInt<1>(0h0))
when _T_748 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_749 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_750 = asUInt(reset)
node _T_751 = eq(_T_750, UInt<1>(0h0))
when _T_751 :
node _T_752 = eq(_T_749, UInt<1>(0h0))
when _T_752 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_749, UInt<1>(0h1), "") : assert_29
node _T_753 = eq(io.in.a.bits.mask, mask)
node _T_754 = asUInt(reset)
node _T_755 = eq(_T_754, UInt<1>(0h0))
when _T_755 :
node _T_756 = eq(_T_753, UInt<1>(0h0))
when _T_756 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_753, UInt<1>(0h1), "") : assert_30
node _T_757 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_757 :
node _T_758 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_759 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_760 = and(_T_758, _T_759)
node _T_761 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_762 = shr(io.in.a.bits.source, 2)
node _T_763 = eq(_T_762, UInt<1>(0h0))
node _T_764 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_765 = and(_T_763, _T_764)
node _T_766 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_767 = and(_T_765, _T_766)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_768 = shr(io.in.a.bits.source, 2)
node _T_769 = eq(_T_768, UInt<1>(0h1))
node _T_770 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_771 = and(_T_769, _T_770)
node _T_772 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_773 = and(_T_771, _T_772)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_774 = shr(io.in.a.bits.source, 2)
node _T_775 = eq(_T_774, UInt<2>(0h2))
node _T_776 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_777 = and(_T_775, _T_776)
node _T_778 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_779 = and(_T_777, _T_778)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_780 = shr(io.in.a.bits.source, 2)
node _T_781 = eq(_T_780, UInt<2>(0h3))
node _T_782 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_783 = and(_T_781, _T_782)
node _T_784 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_785 = and(_T_783, _T_784)
node _T_786 = or(_T_761, _T_767)
node _T_787 = or(_T_786, _T_773)
node _T_788 = or(_T_787, _T_779)
node _T_789 = or(_T_788, _T_785)
node _T_790 = and(_T_760, _T_789)
node _T_791 = or(UInt<1>(0h0), _T_790)
node _T_792 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_793 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_794 = and(_T_792, _T_793)
node _T_795 = or(UInt<1>(0h0), _T_794)
node _T_796 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_797 = cvt(_T_796)
node _T_798 = and(_T_797, asSInt(UInt<13>(0h1000)))
node _T_799 = asSInt(_T_798)
node _T_800 = eq(_T_799, asSInt(UInt<1>(0h0)))
node _T_801 = and(_T_795, _T_800)
node _T_802 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_803 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_804 = and(_T_802, _T_803)
node _T_805 = or(UInt<1>(0h0), _T_804)
node _T_806 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_807 = cvt(_T_806)
node _T_808 = and(_T_807, asSInt(UInt<14>(0h2000)))
node _T_809 = asSInt(_T_808)
node _T_810 = eq(_T_809, asSInt(UInt<1>(0h0)))
node _T_811 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_812 = cvt(_T_811)
node _T_813 = and(_T_812, asSInt(UInt<10>(0h200)))
node _T_814 = asSInt(_T_813)
node _T_815 = eq(_T_814, asSInt(UInt<1>(0h0)))
node _T_816 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_817 = cvt(_T_816)
node _T_818 = and(_T_817, asSInt(UInt<18>(0h2f000)))
node _T_819 = asSInt(_T_818)
node _T_820 = eq(_T_819, asSInt(UInt<1>(0h0)))
node _T_821 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_822 = cvt(_T_821)
node _T_823 = and(_T_822, asSInt(UInt<17>(0h10000)))
node _T_824 = asSInt(_T_823)
node _T_825 = eq(_T_824, asSInt(UInt<1>(0h0)))
node _T_826 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_827 = cvt(_T_826)
node _T_828 = and(_T_827, asSInt(UInt<13>(0h1000)))
node _T_829 = asSInt(_T_828)
node _T_830 = eq(_T_829, asSInt(UInt<1>(0h0)))
node _T_831 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_832 = cvt(_T_831)
node _T_833 = and(_T_832, asSInt(UInt<17>(0h10000)))
node _T_834 = asSInt(_T_833)
node _T_835 = eq(_T_834, asSInt(UInt<1>(0h0)))
node _T_836 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_837 = cvt(_T_836)
node _T_838 = and(_T_837, asSInt(UInt<27>(0h4000000)))
node _T_839 = asSInt(_T_838)
node _T_840 = eq(_T_839, asSInt(UInt<1>(0h0)))
node _T_841 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_842 = cvt(_T_841)
node _T_843 = and(_T_842, asSInt(UInt<13>(0h1000)))
node _T_844 = asSInt(_T_843)
node _T_845 = eq(_T_844, asSInt(UInt<1>(0h0)))
node _T_846 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_847 = cvt(_T_846)
node _T_848 = and(_T_847, asSInt(UInt<29>(0h10000000)))
node _T_849 = asSInt(_T_848)
node _T_850 = eq(_T_849, asSInt(UInt<1>(0h0)))
node _T_851 = or(_T_810, _T_815)
node _T_852 = or(_T_851, _T_820)
node _T_853 = or(_T_852, _T_825)
node _T_854 = or(_T_853, _T_830)
node _T_855 = or(_T_854, _T_835)
node _T_856 = or(_T_855, _T_840)
node _T_857 = or(_T_856, _T_845)
node _T_858 = or(_T_857, _T_850)
node _T_859 = and(_T_805, _T_858)
node _T_860 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_861 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_862 = cvt(_T_861)
node _T_863 = and(_T_862, asSInt(UInt<17>(0h10000)))
node _T_864 = asSInt(_T_863)
node _T_865 = eq(_T_864, asSInt(UInt<1>(0h0)))
node _T_866 = and(_T_860, _T_865)
node _T_867 = or(UInt<1>(0h0), _T_801)
node _T_868 = or(_T_867, _T_859)
node _T_869 = or(_T_868, _T_866)
node _T_870 = and(_T_791, _T_869)
node _T_871 = asUInt(reset)
node _T_872 = eq(_T_871, UInt<1>(0h0))
when _T_872 :
node _T_873 = eq(_T_870, UInt<1>(0h0))
when _T_873 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_870, UInt<1>(0h1), "") : assert_31
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(source_ok, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_877 = asUInt(reset)
node _T_878 = eq(_T_877, UInt<1>(0h0))
when _T_878 :
node _T_879 = eq(is_aligned, UInt<1>(0h0))
when _T_879 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_880 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_881 = asUInt(reset)
node _T_882 = eq(_T_881, UInt<1>(0h0))
when _T_882 :
node _T_883 = eq(_T_880, UInt<1>(0h0))
when _T_883 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_880, UInt<1>(0h1), "") : assert_34
node _T_884 = not(mask)
node _T_885 = and(io.in.a.bits.mask, _T_884)
node _T_886 = eq(_T_885, UInt<1>(0h0))
node _T_887 = asUInt(reset)
node _T_888 = eq(_T_887, UInt<1>(0h0))
when _T_888 :
node _T_889 = eq(_T_886, UInt<1>(0h0))
when _T_889 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_886, UInt<1>(0h1), "") : assert_35
node _T_890 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_890 :
node _T_891 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_892 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_893 = and(_T_891, _T_892)
node _T_894 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_895 = shr(io.in.a.bits.source, 2)
node _T_896 = eq(_T_895, UInt<1>(0h0))
node _T_897 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_898 = and(_T_896, _T_897)
node _T_899 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_900 = and(_T_898, _T_899)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_901 = shr(io.in.a.bits.source, 2)
node _T_902 = eq(_T_901, UInt<1>(0h1))
node _T_903 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_904 = and(_T_902, _T_903)
node _T_905 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_906 = and(_T_904, _T_905)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_907 = shr(io.in.a.bits.source, 2)
node _T_908 = eq(_T_907, UInt<2>(0h2))
node _T_909 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_910 = and(_T_908, _T_909)
node _T_911 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_912 = and(_T_910, _T_911)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_913 = shr(io.in.a.bits.source, 2)
node _T_914 = eq(_T_913, UInt<2>(0h3))
node _T_915 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_916 = and(_T_914, _T_915)
node _T_917 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_918 = and(_T_916, _T_917)
node _T_919 = or(_T_894, _T_900)
node _T_920 = or(_T_919, _T_906)
node _T_921 = or(_T_920, _T_912)
node _T_922 = or(_T_921, _T_918)
node _T_923 = and(_T_893, _T_922)
node _T_924 = or(UInt<1>(0h0), _T_923)
node _T_925 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_926 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_927 = and(_T_925, _T_926)
node _T_928 = or(UInt<1>(0h0), _T_927)
node _T_929 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_930 = cvt(_T_929)
node _T_931 = and(_T_930, asSInt(UInt<14>(0h2000)))
node _T_932 = asSInt(_T_931)
node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0)))
node _T_934 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_935 = cvt(_T_934)
node _T_936 = and(_T_935, asSInt(UInt<10>(0h200)))
node _T_937 = asSInt(_T_936)
node _T_938 = eq(_T_937, asSInt(UInt<1>(0h0)))
node _T_939 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_940 = cvt(_T_939)
node _T_941 = and(_T_940, asSInt(UInt<13>(0h1000)))
node _T_942 = asSInt(_T_941)
node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0)))
node _T_944 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_945 = cvt(_T_944)
node _T_946 = and(_T_945, asSInt(UInt<18>(0h2f000)))
node _T_947 = asSInt(_T_946)
node _T_948 = eq(_T_947, asSInt(UInt<1>(0h0)))
node _T_949 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_950 = cvt(_T_949)
node _T_951 = and(_T_950, asSInt(UInt<17>(0h10000)))
node _T_952 = asSInt(_T_951)
node _T_953 = eq(_T_952, asSInt(UInt<1>(0h0)))
node _T_954 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_955 = cvt(_T_954)
node _T_956 = and(_T_955, asSInt(UInt<13>(0h1000)))
node _T_957 = asSInt(_T_956)
node _T_958 = eq(_T_957, asSInt(UInt<1>(0h0)))
node _T_959 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_960 = cvt(_T_959)
node _T_961 = and(_T_960, asSInt(UInt<17>(0h10000)))
node _T_962 = asSInt(_T_961)
node _T_963 = eq(_T_962, asSInt(UInt<1>(0h0)))
node _T_964 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_965 = cvt(_T_964)
node _T_966 = and(_T_965, asSInt(UInt<27>(0h4000000)))
node _T_967 = asSInt(_T_966)
node _T_968 = eq(_T_967, asSInt(UInt<1>(0h0)))
node _T_969 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_970 = cvt(_T_969)
node _T_971 = and(_T_970, asSInt(UInt<13>(0h1000)))
node _T_972 = asSInt(_T_971)
node _T_973 = eq(_T_972, asSInt(UInt<1>(0h0)))
node _T_974 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_975 = cvt(_T_974)
node _T_976 = and(_T_975, asSInt(UInt<29>(0h10000000)))
node _T_977 = asSInt(_T_976)
node _T_978 = eq(_T_977, asSInt(UInt<1>(0h0)))
node _T_979 = or(_T_933, _T_938)
node _T_980 = or(_T_979, _T_943)
node _T_981 = or(_T_980, _T_948)
node _T_982 = or(_T_981, _T_953)
node _T_983 = or(_T_982, _T_958)
node _T_984 = or(_T_983, _T_963)
node _T_985 = or(_T_984, _T_968)
node _T_986 = or(_T_985, _T_973)
node _T_987 = or(_T_986, _T_978)
node _T_988 = and(_T_928, _T_987)
node _T_989 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_990 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_991 = cvt(_T_990)
node _T_992 = and(_T_991, asSInt(UInt<17>(0h10000)))
node _T_993 = asSInt(_T_992)
node _T_994 = eq(_T_993, asSInt(UInt<1>(0h0)))
node _T_995 = and(_T_989, _T_994)
node _T_996 = or(UInt<1>(0h0), _T_988)
node _T_997 = or(_T_996, _T_995)
node _T_998 = and(_T_924, _T_997)
node _T_999 = asUInt(reset)
node _T_1000 = eq(_T_999, UInt<1>(0h0))
when _T_1000 :
node _T_1001 = eq(_T_998, UInt<1>(0h0))
when _T_1001 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_998, UInt<1>(0h1), "") : assert_36
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(source_ok, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1005 = asUInt(reset)
node _T_1006 = eq(_T_1005, UInt<1>(0h0))
when _T_1006 :
node _T_1007 = eq(is_aligned, UInt<1>(0h0))
when _T_1007 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1008 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1009 = asUInt(reset)
node _T_1010 = eq(_T_1009, UInt<1>(0h0))
when _T_1010 :
node _T_1011 = eq(_T_1008, UInt<1>(0h0))
when _T_1011 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1008, UInt<1>(0h1), "") : assert_39
node _T_1012 = eq(io.in.a.bits.mask, mask)
node _T_1013 = asUInt(reset)
node _T_1014 = eq(_T_1013, UInt<1>(0h0))
when _T_1014 :
node _T_1015 = eq(_T_1012, UInt<1>(0h0))
when _T_1015 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1012, UInt<1>(0h1), "") : assert_40
node _T_1016 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1016 :
node _T_1017 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1018 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1019 = and(_T_1017, _T_1018)
node _T_1020 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_1021 = shr(io.in.a.bits.source, 2)
node _T_1022 = eq(_T_1021, UInt<1>(0h0))
node _T_1023 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_1024 = and(_T_1022, _T_1023)
node _T_1025 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_1026 = and(_T_1024, _T_1025)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_1027 = shr(io.in.a.bits.source, 2)
node _T_1028 = eq(_T_1027, UInt<1>(0h1))
node _T_1029 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_1030 = and(_T_1028, _T_1029)
node _T_1031 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_1032 = and(_T_1030, _T_1031)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_1033 = shr(io.in.a.bits.source, 2)
node _T_1034 = eq(_T_1033, UInt<2>(0h2))
node _T_1035 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_1036 = and(_T_1034, _T_1035)
node _T_1037 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_1038 = and(_T_1036, _T_1037)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_1039 = shr(io.in.a.bits.source, 2)
node _T_1040 = eq(_T_1039, UInt<2>(0h3))
node _T_1041 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_1042 = and(_T_1040, _T_1041)
node _T_1043 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_1044 = and(_T_1042, _T_1043)
node _T_1045 = or(_T_1020, _T_1026)
node _T_1046 = or(_T_1045, _T_1032)
node _T_1047 = or(_T_1046, _T_1038)
node _T_1048 = or(_T_1047, _T_1044)
node _T_1049 = and(_T_1019, _T_1048)
node _T_1050 = or(UInt<1>(0h0), _T_1049)
node _T_1051 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1052 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1053 = and(_T_1051, _T_1052)
node _T_1054 = or(UInt<1>(0h0), _T_1053)
node _T_1055 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1056 = cvt(_T_1055)
node _T_1057 = and(_T_1056, asSInt(UInt<14>(0h2000)))
node _T_1058 = asSInt(_T_1057)
node _T_1059 = eq(_T_1058, asSInt(UInt<1>(0h0)))
node _T_1060 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_1061 = cvt(_T_1060)
node _T_1062 = and(_T_1061, asSInt(UInt<10>(0h200)))
node _T_1063 = asSInt(_T_1062)
node _T_1064 = eq(_T_1063, asSInt(UInt<1>(0h0)))
node _T_1065 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1066 = cvt(_T_1065)
node _T_1067 = and(_T_1066, asSInt(UInt<13>(0h1000)))
node _T_1068 = asSInt(_T_1067)
node _T_1069 = eq(_T_1068, asSInt(UInt<1>(0h0)))
node _T_1070 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1071 = cvt(_T_1070)
node _T_1072 = and(_T_1071, asSInt(UInt<18>(0h2f000)))
node _T_1073 = asSInt(_T_1072)
node _T_1074 = eq(_T_1073, asSInt(UInt<1>(0h0)))
node _T_1075 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1076 = cvt(_T_1075)
node _T_1077 = and(_T_1076, asSInt(UInt<17>(0h10000)))
node _T_1078 = asSInt(_T_1077)
node _T_1079 = eq(_T_1078, asSInt(UInt<1>(0h0)))
node _T_1080 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1081 = cvt(_T_1080)
node _T_1082 = and(_T_1081, asSInt(UInt<13>(0h1000)))
node _T_1083 = asSInt(_T_1082)
node _T_1084 = eq(_T_1083, asSInt(UInt<1>(0h0)))
node _T_1085 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1086 = cvt(_T_1085)
node _T_1087 = and(_T_1086, asSInt(UInt<17>(0h10000)))
node _T_1088 = asSInt(_T_1087)
node _T_1089 = eq(_T_1088, asSInt(UInt<1>(0h0)))
node _T_1090 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1091 = cvt(_T_1090)
node _T_1092 = and(_T_1091, asSInt(UInt<27>(0h4000000)))
node _T_1093 = asSInt(_T_1092)
node _T_1094 = eq(_T_1093, asSInt(UInt<1>(0h0)))
node _T_1095 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1096 = cvt(_T_1095)
node _T_1097 = and(_T_1096, asSInt(UInt<13>(0h1000)))
node _T_1098 = asSInt(_T_1097)
node _T_1099 = eq(_T_1098, asSInt(UInt<1>(0h0)))
node _T_1100 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1101 = cvt(_T_1100)
node _T_1102 = and(_T_1101, asSInt(UInt<29>(0h10000000)))
node _T_1103 = asSInt(_T_1102)
node _T_1104 = eq(_T_1103, asSInt(UInt<1>(0h0)))
node _T_1105 = or(_T_1059, _T_1064)
node _T_1106 = or(_T_1105, _T_1069)
node _T_1107 = or(_T_1106, _T_1074)
node _T_1108 = or(_T_1107, _T_1079)
node _T_1109 = or(_T_1108, _T_1084)
node _T_1110 = or(_T_1109, _T_1089)
node _T_1111 = or(_T_1110, _T_1094)
node _T_1112 = or(_T_1111, _T_1099)
node _T_1113 = or(_T_1112, _T_1104)
node _T_1114 = and(_T_1054, _T_1113)
node _T_1115 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1116 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1117 = cvt(_T_1116)
node _T_1118 = and(_T_1117, asSInt(UInt<17>(0h10000)))
node _T_1119 = asSInt(_T_1118)
node _T_1120 = eq(_T_1119, asSInt(UInt<1>(0h0)))
node _T_1121 = and(_T_1115, _T_1120)
node _T_1122 = or(UInt<1>(0h0), _T_1114)
node _T_1123 = or(_T_1122, _T_1121)
node _T_1124 = and(_T_1050, _T_1123)
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_41
node _T_1128 = asUInt(reset)
node _T_1129 = eq(_T_1128, UInt<1>(0h0))
when _T_1129 :
node _T_1130 = eq(source_ok, UInt<1>(0h0))
when _T_1130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1131 = asUInt(reset)
node _T_1132 = eq(_T_1131, UInt<1>(0h0))
when _T_1132 :
node _T_1133 = eq(is_aligned, UInt<1>(0h0))
when _T_1133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1134 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_44
node _T_1138 = eq(io.in.a.bits.mask, mask)
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_45
node _T_1142 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1142 :
node _T_1143 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1144 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1145 = and(_T_1143, _T_1144)
node _T_1146 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1147 = shr(io.in.a.bits.source, 2)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
node _T_1149 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1150 = and(_T_1148, _T_1149)
node _T_1151 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1152 = and(_T_1150, _T_1151)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1153 = shr(io.in.a.bits.source, 2)
node _T_1154 = eq(_T_1153, UInt<1>(0h1))
node _T_1155 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1156 = and(_T_1154, _T_1155)
node _T_1157 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1158 = and(_T_1156, _T_1157)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1159 = shr(io.in.a.bits.source, 2)
node _T_1160 = eq(_T_1159, UInt<2>(0h2))
node _T_1161 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1162 = and(_T_1160, _T_1161)
node _T_1163 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1164 = and(_T_1162, _T_1163)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1165 = shr(io.in.a.bits.source, 2)
node _T_1166 = eq(_T_1165, UInt<2>(0h3))
node _T_1167 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1168 = and(_T_1166, _T_1167)
node _T_1169 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1170 = and(_T_1168, _T_1169)
node _T_1171 = or(_T_1146, _T_1152)
node _T_1172 = or(_T_1171, _T_1158)
node _T_1173 = or(_T_1172, _T_1164)
node _T_1174 = or(_T_1173, _T_1170)
node _T_1175 = and(_T_1145, _T_1174)
node _T_1176 = or(UInt<1>(0h0), _T_1175)
node _T_1177 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1178 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1179 = and(_T_1177, _T_1178)
node _T_1180 = or(UInt<1>(0h0), _T_1179)
node _T_1181 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1182 = cvt(_T_1181)
node _T_1183 = and(_T_1182, asSInt(UInt<13>(0h1000)))
node _T_1184 = asSInt(_T_1183)
node _T_1185 = eq(_T_1184, asSInt(UInt<1>(0h0)))
node _T_1186 = and(_T_1180, _T_1185)
node _T_1187 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1188 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1189 = cvt(_T_1188)
node _T_1190 = and(_T_1189, asSInt(UInt<14>(0h2000)))
node _T_1191 = asSInt(_T_1190)
node _T_1192 = eq(_T_1191, asSInt(UInt<1>(0h0)))
node _T_1193 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_1194 = cvt(_T_1193)
node _T_1195 = and(_T_1194, asSInt(UInt<10>(0h200)))
node _T_1196 = asSInt(_T_1195)
node _T_1197 = eq(_T_1196, asSInt(UInt<1>(0h0)))
node _T_1198 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1199 = cvt(_T_1198)
node _T_1200 = and(_T_1199, asSInt(UInt<17>(0h10000)))
node _T_1201 = asSInt(_T_1200)
node _T_1202 = eq(_T_1201, asSInt(UInt<1>(0h0)))
node _T_1203 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1204 = cvt(_T_1203)
node _T_1205 = and(_T_1204, asSInt(UInt<18>(0h2f000)))
node _T_1206 = asSInt(_T_1205)
node _T_1207 = eq(_T_1206, asSInt(UInt<1>(0h0)))
node _T_1208 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1209 = cvt(_T_1208)
node _T_1210 = and(_T_1209, asSInt(UInt<17>(0h10000)))
node _T_1211 = asSInt(_T_1210)
node _T_1212 = eq(_T_1211, asSInt(UInt<1>(0h0)))
node _T_1213 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1214 = cvt(_T_1213)
node _T_1215 = and(_T_1214, asSInt(UInt<13>(0h1000)))
node _T_1216 = asSInt(_T_1215)
node _T_1217 = eq(_T_1216, asSInt(UInt<1>(0h0)))
node _T_1218 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1219 = cvt(_T_1218)
node _T_1220 = and(_T_1219, asSInt(UInt<27>(0h4000000)))
node _T_1221 = asSInt(_T_1220)
node _T_1222 = eq(_T_1221, asSInt(UInt<1>(0h0)))
node _T_1223 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1224 = cvt(_T_1223)
node _T_1225 = and(_T_1224, asSInt(UInt<13>(0h1000)))
node _T_1226 = asSInt(_T_1225)
node _T_1227 = eq(_T_1226, asSInt(UInt<1>(0h0)))
node _T_1228 = or(_T_1192, _T_1197)
node _T_1229 = or(_T_1228, _T_1202)
node _T_1230 = or(_T_1229, _T_1207)
node _T_1231 = or(_T_1230, _T_1212)
node _T_1232 = or(_T_1231, _T_1217)
node _T_1233 = or(_T_1232, _T_1222)
node _T_1234 = or(_T_1233, _T_1227)
node _T_1235 = and(_T_1187, _T_1234)
node _T_1236 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1237 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1238 = and(_T_1236, _T_1237)
node _T_1239 = or(UInt<1>(0h0), _T_1238)
node _T_1240 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1241 = cvt(_T_1240)
node _T_1242 = and(_T_1241, asSInt(UInt<17>(0h10000)))
node _T_1243 = asSInt(_T_1242)
node _T_1244 = eq(_T_1243, asSInt(UInt<1>(0h0)))
node _T_1245 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1246 = cvt(_T_1245)
node _T_1247 = and(_T_1246, asSInt(UInt<29>(0h10000000)))
node _T_1248 = asSInt(_T_1247)
node _T_1249 = eq(_T_1248, asSInt(UInt<1>(0h0)))
node _T_1250 = or(_T_1244, _T_1249)
node _T_1251 = and(_T_1239, _T_1250)
node _T_1252 = or(UInt<1>(0h0), _T_1186)
node _T_1253 = or(_T_1252, _T_1235)
node _T_1254 = or(_T_1253, _T_1251)
node _T_1255 = and(_T_1176, _T_1254)
node _T_1256 = asUInt(reset)
node _T_1257 = eq(_T_1256, UInt<1>(0h0))
when _T_1257 :
node _T_1258 = eq(_T_1255, UInt<1>(0h0))
when _T_1258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1255, UInt<1>(0h1), "") : assert_46
node _T_1259 = asUInt(reset)
node _T_1260 = eq(_T_1259, UInt<1>(0h0))
when _T_1260 :
node _T_1261 = eq(source_ok, UInt<1>(0h0))
when _T_1261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1262 = asUInt(reset)
node _T_1263 = eq(_T_1262, UInt<1>(0h0))
when _T_1263 :
node _T_1264 = eq(is_aligned, UInt<1>(0h0))
when _T_1264 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1265 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1266 = asUInt(reset)
node _T_1267 = eq(_T_1266, UInt<1>(0h0))
when _T_1267 :
node _T_1268 = eq(_T_1265, UInt<1>(0h0))
when _T_1268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1265, UInt<1>(0h1), "") : assert_49
node _T_1269 = eq(io.in.a.bits.mask, mask)
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(_T_1269, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1269, UInt<1>(0h1), "") : assert_50
node _T_1273 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1274 = asUInt(reset)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(_T_1273, UInt<1>(0h0))
when _T_1276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1273, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1277 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1278 = asUInt(reset)
node _T_1279 = eq(_T_1278, UInt<1>(0h0))
when _T_1279 :
node _T_1280 = eq(_T_1277, UInt<1>(0h0))
when _T_1280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1277, UInt<1>(0h1), "") : assert_52
node _source_ok_T_28 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_29 = shr(io.in.d.bits.source, 2)
node _source_ok_T_30 = eq(_source_ok_T_29, UInt<1>(0h0))
node _source_ok_T_31 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31)
node _source_ok_T_33 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_35 = shr(io.in.d.bits.source, 2)
node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h1))
node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37)
node _source_ok_T_39 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_41 = shr(io.in.d.bits.source, 2)
node _source_ok_T_42 = eq(_source_ok_T_41, UInt<2>(0h2))
node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_T_45 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_47 = shr(io.in.d.bits.source, 2)
node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h3))
node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_T_51 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
wire _source_ok_WIRE_1 : UInt<1>[5]
connect _source_ok_WIRE_1[0], _source_ok_T_28
connect _source_ok_WIRE_1[1], _source_ok_T_34
connect _source_ok_WIRE_1[2], _source_ok_T_40
connect _source_ok_WIRE_1[3], _source_ok_T_46
connect _source_ok_WIRE_1[4], _source_ok_T_52
node _source_ok_T_53 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE_1[2])
node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE_1[3])
node source_ok_1 = or(_source_ok_T_55, _source_ok_WIRE_1[4])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_1281 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1281 :
node _T_1282 = asUInt(reset)
node _T_1283 = eq(_T_1282, UInt<1>(0h0))
when _T_1283 :
node _T_1284 = eq(source_ok_1, UInt<1>(0h0))
when _T_1284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1285 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1286 = asUInt(reset)
node _T_1287 = eq(_T_1286, UInt<1>(0h0))
when _T_1287 :
node _T_1288 = eq(_T_1285, UInt<1>(0h0))
when _T_1288 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1285, UInt<1>(0h1), "") : assert_54
node _T_1289 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_55
node _T_1293 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1294 = asUInt(reset)
node _T_1295 = eq(_T_1294, UInt<1>(0h0))
when _T_1295 :
node _T_1296 = eq(_T_1293, UInt<1>(0h0))
when _T_1296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1293, UInt<1>(0h1), "") : assert_56
node _T_1297 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1298 = asUInt(reset)
node _T_1299 = eq(_T_1298, UInt<1>(0h0))
when _T_1299 :
node _T_1300 = eq(_T_1297, UInt<1>(0h0))
when _T_1300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1297, UInt<1>(0h1), "") : assert_57
node _T_1301 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1301 :
node _T_1302 = asUInt(reset)
node _T_1303 = eq(_T_1302, UInt<1>(0h0))
when _T_1303 :
node _T_1304 = eq(source_ok_1, UInt<1>(0h0))
when _T_1304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1305 = asUInt(reset)
node _T_1306 = eq(_T_1305, UInt<1>(0h0))
when _T_1306 :
node _T_1307 = eq(sink_ok, UInt<1>(0h0))
when _T_1307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1308 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1309 = asUInt(reset)
node _T_1310 = eq(_T_1309, UInt<1>(0h0))
when _T_1310 :
node _T_1311 = eq(_T_1308, UInt<1>(0h0))
when _T_1311 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1308, UInt<1>(0h1), "") : assert_60
node _T_1312 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1313 = asUInt(reset)
node _T_1314 = eq(_T_1313, UInt<1>(0h0))
when _T_1314 :
node _T_1315 = eq(_T_1312, UInt<1>(0h0))
when _T_1315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1312, UInt<1>(0h1), "") : assert_61
node _T_1316 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1317 = asUInt(reset)
node _T_1318 = eq(_T_1317, UInt<1>(0h0))
when _T_1318 :
node _T_1319 = eq(_T_1316, UInt<1>(0h0))
when _T_1319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1316, UInt<1>(0h1), "") : assert_62
node _T_1320 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1321 = asUInt(reset)
node _T_1322 = eq(_T_1321, UInt<1>(0h0))
when _T_1322 :
node _T_1323 = eq(_T_1320, UInt<1>(0h0))
when _T_1323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1320, UInt<1>(0h1), "") : assert_63
node _T_1324 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1325 = or(UInt<1>(0h1), _T_1324)
node _T_1326 = asUInt(reset)
node _T_1327 = eq(_T_1326, UInt<1>(0h0))
when _T_1327 :
node _T_1328 = eq(_T_1325, UInt<1>(0h0))
when _T_1328 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1325, UInt<1>(0h1), "") : assert_64
node _T_1329 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1329 :
node _T_1330 = asUInt(reset)
node _T_1331 = eq(_T_1330, UInt<1>(0h0))
when _T_1331 :
node _T_1332 = eq(source_ok_1, UInt<1>(0h0))
when _T_1332 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1333 = asUInt(reset)
node _T_1334 = eq(_T_1333, UInt<1>(0h0))
when _T_1334 :
node _T_1335 = eq(sink_ok, UInt<1>(0h0))
when _T_1335 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1336 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1337 = asUInt(reset)
node _T_1338 = eq(_T_1337, UInt<1>(0h0))
when _T_1338 :
node _T_1339 = eq(_T_1336, UInt<1>(0h0))
when _T_1339 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1336, UInt<1>(0h1), "") : assert_67
node _T_1340 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1341 = asUInt(reset)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
when _T_1342 :
node _T_1343 = eq(_T_1340, UInt<1>(0h0))
when _T_1343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1340, UInt<1>(0h1), "") : assert_68
node _T_1344 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1345 = asUInt(reset)
node _T_1346 = eq(_T_1345, UInt<1>(0h0))
when _T_1346 :
node _T_1347 = eq(_T_1344, UInt<1>(0h0))
when _T_1347 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1344, UInt<1>(0h1), "") : assert_69
node _T_1348 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1349 = or(_T_1348, io.in.d.bits.corrupt)
node _T_1350 = asUInt(reset)
node _T_1351 = eq(_T_1350, UInt<1>(0h0))
when _T_1351 :
node _T_1352 = eq(_T_1349, UInt<1>(0h0))
when _T_1352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1349, UInt<1>(0h1), "") : assert_70
node _T_1353 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1354 = or(UInt<1>(0h1), _T_1353)
node _T_1355 = asUInt(reset)
node _T_1356 = eq(_T_1355, UInt<1>(0h0))
when _T_1356 :
node _T_1357 = eq(_T_1354, UInt<1>(0h0))
when _T_1357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1354, UInt<1>(0h1), "") : assert_71
node _T_1358 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1358 :
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(source_ok_1, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1362 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1363 = asUInt(reset)
node _T_1364 = eq(_T_1363, UInt<1>(0h0))
when _T_1364 :
node _T_1365 = eq(_T_1362, UInt<1>(0h0))
when _T_1365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1362, UInt<1>(0h1), "") : assert_73
node _T_1366 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1367 = asUInt(reset)
node _T_1368 = eq(_T_1367, UInt<1>(0h0))
when _T_1368 :
node _T_1369 = eq(_T_1366, UInt<1>(0h0))
when _T_1369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1366, UInt<1>(0h1), "") : assert_74
node _T_1370 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1371 = or(UInt<1>(0h1), _T_1370)
node _T_1372 = asUInt(reset)
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(_T_1371, UInt<1>(0h0))
when _T_1374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1371, UInt<1>(0h1), "") : assert_75
node _T_1375 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1375 :
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(source_ok_1, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1379 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1380 = asUInt(reset)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
when _T_1381 :
node _T_1382 = eq(_T_1379, UInt<1>(0h0))
when _T_1382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1379, UInt<1>(0h1), "") : assert_77
node _T_1383 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1384 = or(_T_1383, io.in.d.bits.corrupt)
node _T_1385 = asUInt(reset)
node _T_1386 = eq(_T_1385, UInt<1>(0h0))
when _T_1386 :
node _T_1387 = eq(_T_1384, UInt<1>(0h0))
when _T_1387 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1384, UInt<1>(0h1), "") : assert_78
node _T_1388 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1389 = or(UInt<1>(0h1), _T_1388)
node _T_1390 = asUInt(reset)
node _T_1391 = eq(_T_1390, UInt<1>(0h0))
when _T_1391 :
node _T_1392 = eq(_T_1389, UInt<1>(0h0))
when _T_1392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1389, UInt<1>(0h1), "") : assert_79
node _T_1393 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1393 :
node _T_1394 = asUInt(reset)
node _T_1395 = eq(_T_1394, UInt<1>(0h0))
when _T_1395 :
node _T_1396 = eq(source_ok_1, UInt<1>(0h0))
when _T_1396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1397 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1398 = asUInt(reset)
node _T_1399 = eq(_T_1398, UInt<1>(0h0))
when _T_1399 :
node _T_1400 = eq(_T_1397, UInt<1>(0h0))
when _T_1400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1397, UInt<1>(0h1), "") : assert_81
node _T_1401 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1402 = asUInt(reset)
node _T_1403 = eq(_T_1402, UInt<1>(0h0))
when _T_1403 :
node _T_1404 = eq(_T_1401, UInt<1>(0h0))
when _T_1404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1401, UInt<1>(0h1), "") : assert_82
node _T_1405 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1406 = or(UInt<1>(0h1), _T_1405)
node _T_1407 = asUInt(reset)
node _T_1408 = eq(_T_1407, UInt<1>(0h0))
when _T_1408 :
node _T_1409 = eq(_T_1406, UInt<1>(0h0))
when _T_1409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1406, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1410 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1411 = asUInt(reset)
node _T_1412 = eq(_T_1411, UInt<1>(0h0))
when _T_1412 :
node _T_1413 = eq(_T_1410, UInt<1>(0h0))
when _T_1413 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1410, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1414 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1415 = asUInt(reset)
node _T_1416 = eq(_T_1415, UInt<1>(0h0))
when _T_1416 :
node _T_1417 = eq(_T_1414, UInt<1>(0h0))
when _T_1417 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1414, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1418 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1419 = asUInt(reset)
node _T_1420 = eq(_T_1419, UInt<1>(0h0))
when _T_1420 :
node _T_1421 = eq(_T_1418, UInt<1>(0h0))
when _T_1421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1418, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1422 = eq(a_first, UInt<1>(0h0))
node _T_1423 = and(io.in.a.valid, _T_1422)
when _T_1423 :
node _T_1424 = eq(io.in.a.bits.opcode, opcode)
node _T_1425 = asUInt(reset)
node _T_1426 = eq(_T_1425, UInt<1>(0h0))
when _T_1426 :
node _T_1427 = eq(_T_1424, UInt<1>(0h0))
when _T_1427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1424, UInt<1>(0h1), "") : assert_87
node _T_1428 = eq(io.in.a.bits.param, param)
node _T_1429 = asUInt(reset)
node _T_1430 = eq(_T_1429, UInt<1>(0h0))
when _T_1430 :
node _T_1431 = eq(_T_1428, UInt<1>(0h0))
when _T_1431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1428, UInt<1>(0h1), "") : assert_88
node _T_1432 = eq(io.in.a.bits.size, size)
node _T_1433 = asUInt(reset)
node _T_1434 = eq(_T_1433, UInt<1>(0h0))
when _T_1434 :
node _T_1435 = eq(_T_1432, UInt<1>(0h0))
when _T_1435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1432, UInt<1>(0h1), "") : assert_89
node _T_1436 = eq(io.in.a.bits.source, source)
node _T_1437 = asUInt(reset)
node _T_1438 = eq(_T_1437, UInt<1>(0h0))
when _T_1438 :
node _T_1439 = eq(_T_1436, UInt<1>(0h0))
when _T_1439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1436, UInt<1>(0h1), "") : assert_90
node _T_1440 = eq(io.in.a.bits.address, address)
node _T_1441 = asUInt(reset)
node _T_1442 = eq(_T_1441, UInt<1>(0h0))
when _T_1442 :
node _T_1443 = eq(_T_1440, UInt<1>(0h0))
when _T_1443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1440, UInt<1>(0h1), "") : assert_91
node _T_1444 = and(io.in.a.ready, io.in.a.valid)
node _T_1445 = and(_T_1444, a_first)
when _T_1445 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1446 = eq(d_first, UInt<1>(0h0))
node _T_1447 = and(io.in.d.valid, _T_1446)
when _T_1447 :
node _T_1448 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1449 = asUInt(reset)
node _T_1450 = eq(_T_1449, UInt<1>(0h0))
when _T_1450 :
node _T_1451 = eq(_T_1448, UInt<1>(0h0))
when _T_1451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1448, UInt<1>(0h1), "") : assert_92
node _T_1452 = eq(io.in.d.bits.param, param_1)
node _T_1453 = asUInt(reset)
node _T_1454 = eq(_T_1453, UInt<1>(0h0))
when _T_1454 :
node _T_1455 = eq(_T_1452, UInt<1>(0h0))
when _T_1455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1452, UInt<1>(0h1), "") : assert_93
node _T_1456 = eq(io.in.d.bits.size, size_1)
node _T_1457 = asUInt(reset)
node _T_1458 = eq(_T_1457, UInt<1>(0h0))
when _T_1458 :
node _T_1459 = eq(_T_1456, UInt<1>(0h0))
when _T_1459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1456, UInt<1>(0h1), "") : assert_94
node _T_1460 = eq(io.in.d.bits.source, source_1)
node _T_1461 = asUInt(reset)
node _T_1462 = eq(_T_1461, UInt<1>(0h0))
when _T_1462 :
node _T_1463 = eq(_T_1460, UInt<1>(0h0))
when _T_1463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1460, UInt<1>(0h1), "") : assert_95
node _T_1464 = eq(io.in.d.bits.sink, sink)
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(_T_1464, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1464, UInt<1>(0h1), "") : assert_96
node _T_1468 = eq(io.in.d.bits.denied, denied)
node _T_1469 = asUInt(reset)
node _T_1470 = eq(_T_1469, UInt<1>(0h0))
when _T_1470 :
node _T_1471 = eq(_T_1468, UInt<1>(0h0))
when _T_1471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1468, UInt<1>(0h1), "") : assert_97
node _T_1472 = and(io.in.d.ready, io.in.d.valid)
node _T_1473 = and(_T_1472, d_first)
when _T_1473 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<17>, clock, reset, UInt<17>(0h0)
regreset inflight_opcodes : UInt<68>, clock, reset, UInt<68>(0h0)
regreset inflight_sizes : UInt<136>, clock, reset, UInt<136>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<17>
connect a_set, UInt<17>(0h0)
wire a_set_wo_ready : UInt<17>
connect a_set_wo_ready, UInt<17>(0h0)
wire a_opcodes_set : UInt<68>
connect a_opcodes_set, UInt<68>(0h0)
wire a_sizes_set : UInt<136>
connect a_sizes_set, UInt<136>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1474 = and(io.in.a.valid, a_first_1)
node _T_1475 = and(_T_1474, UInt<1>(0h1))
when _T_1475 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1476 = and(io.in.a.ready, io.in.a.valid)
node _T_1477 = and(_T_1476, a_first_1)
node _T_1478 = and(_T_1477, UInt<1>(0h1))
when _T_1478 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1479 = dshr(inflight, io.in.a.bits.source)
node _T_1480 = bits(_T_1479, 0, 0)
node _T_1481 = eq(_T_1480, UInt<1>(0h0))
node _T_1482 = asUInt(reset)
node _T_1483 = eq(_T_1482, UInt<1>(0h0))
when _T_1483 :
node _T_1484 = eq(_T_1481, UInt<1>(0h0))
when _T_1484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1481, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<17>
connect d_clr, UInt<17>(0h0)
wire d_clr_wo_ready : UInt<17>
connect d_clr_wo_ready, UInt<17>(0h0)
wire d_opcodes_clr : UInt<68>
connect d_opcodes_clr, UInt<68>(0h0)
wire d_sizes_clr : UInt<136>
connect d_sizes_clr, UInt<136>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1485 = and(io.in.d.valid, d_first_1)
node _T_1486 = and(_T_1485, UInt<1>(0h1))
node _T_1487 = eq(d_release_ack, UInt<1>(0h0))
node _T_1488 = and(_T_1486, _T_1487)
when _T_1488 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1489 = and(io.in.d.ready, io.in.d.valid)
node _T_1490 = and(_T_1489, d_first_1)
node _T_1491 = and(_T_1490, UInt<1>(0h1))
node _T_1492 = eq(d_release_ack, UInt<1>(0h0))
node _T_1493 = and(_T_1491, _T_1492)
when _T_1493 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1494 = and(io.in.d.valid, d_first_1)
node _T_1495 = and(_T_1494, UInt<1>(0h1))
node _T_1496 = eq(d_release_ack, UInt<1>(0h0))
node _T_1497 = and(_T_1495, _T_1496)
when _T_1497 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1498 = dshr(inflight, io.in.d.bits.source)
node _T_1499 = bits(_T_1498, 0, 0)
node _T_1500 = or(_T_1499, same_cycle_resp)
node _T_1501 = asUInt(reset)
node _T_1502 = eq(_T_1501, UInt<1>(0h0))
when _T_1502 :
node _T_1503 = eq(_T_1500, UInt<1>(0h0))
when _T_1503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1500, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1504 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1505 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1506 = or(_T_1504, _T_1505)
node _T_1507 = asUInt(reset)
node _T_1508 = eq(_T_1507, UInt<1>(0h0))
when _T_1508 :
node _T_1509 = eq(_T_1506, UInt<1>(0h0))
when _T_1509 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1506, UInt<1>(0h1), "") : assert_100
node _T_1510 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1511 = asUInt(reset)
node _T_1512 = eq(_T_1511, UInt<1>(0h0))
when _T_1512 :
node _T_1513 = eq(_T_1510, UInt<1>(0h0))
when _T_1513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1510, UInt<1>(0h1), "") : assert_101
else :
node _T_1514 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1515 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1516 = or(_T_1514, _T_1515)
node _T_1517 = asUInt(reset)
node _T_1518 = eq(_T_1517, UInt<1>(0h0))
when _T_1518 :
node _T_1519 = eq(_T_1516, UInt<1>(0h0))
when _T_1519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1516, UInt<1>(0h1), "") : assert_102
node _T_1520 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1521 = asUInt(reset)
node _T_1522 = eq(_T_1521, UInt<1>(0h0))
when _T_1522 :
node _T_1523 = eq(_T_1520, UInt<1>(0h0))
when _T_1523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1520, UInt<1>(0h1), "") : assert_103
node _T_1524 = and(io.in.d.valid, d_first_1)
node _T_1525 = and(_T_1524, a_first_1)
node _T_1526 = and(_T_1525, io.in.a.valid)
node _T_1527 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1528 = and(_T_1526, _T_1527)
node _T_1529 = eq(d_release_ack, UInt<1>(0h0))
node _T_1530 = and(_T_1528, _T_1529)
when _T_1530 :
node _T_1531 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1532 = or(_T_1531, io.in.a.ready)
node _T_1533 = asUInt(reset)
node _T_1534 = eq(_T_1533, UInt<1>(0h0))
when _T_1534 :
node _T_1535 = eq(_T_1532, UInt<1>(0h0))
when _T_1535 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1532, UInt<1>(0h1), "") : assert_104
node _T_1536 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1537 = orr(a_set_wo_ready)
node _T_1538 = eq(_T_1537, UInt<1>(0h0))
node _T_1539 = or(_T_1536, _T_1538)
node _T_1540 = asUInt(reset)
node _T_1541 = eq(_T_1540, UInt<1>(0h0))
when _T_1541 :
node _T_1542 = eq(_T_1539, UInt<1>(0h0))
when _T_1542 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1539, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_22
node _T_1543 = orr(inflight)
node _T_1544 = eq(_T_1543, UInt<1>(0h0))
node _T_1545 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1546 = or(_T_1544, _T_1545)
node _T_1547 = lt(watchdog, plusarg_reader.out)
node _T_1548 = or(_T_1546, _T_1547)
node _T_1549 = asUInt(reset)
node _T_1550 = eq(_T_1549, UInt<1>(0h0))
when _T_1550 :
node _T_1551 = eq(_T_1548, UInt<1>(0h0))
when _T_1551 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1548, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1552 = and(io.in.a.ready, io.in.a.valid)
node _T_1553 = and(io.in.d.ready, io.in.d.valid)
node _T_1554 = or(_T_1552, _T_1553)
when _T_1554 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<17>, clock, reset, UInt<17>(0h0)
regreset inflight_opcodes_1 : UInt<68>, clock, reset, UInt<68>(0h0)
regreset inflight_sizes_1 : UInt<136>, clock, reset, UInt<136>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<5>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<17>
connect c_set, UInt<17>(0h0)
wire c_set_wo_ready : UInt<17>
connect c_set_wo_ready, UInt<17>(0h0)
wire c_opcodes_set : UInt<68>
connect c_opcodes_set, UInt<68>(0h0)
wire c_sizes_set : UInt<136>
connect c_sizes_set, UInt<136>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1555 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1556 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1557 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1558 = and(_T_1556, _T_1557)
node _T_1559 = and(_T_1555, _T_1558)
when _T_1559 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1560 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1561 = and(_T_1560, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1562 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1563 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1564 = and(_T_1562, _T_1563)
node _T_1565 = and(_T_1561, _T_1564)
when _T_1565 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1566 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1567 = bits(_T_1566, 0, 0)
node _T_1568 = eq(_T_1567, UInt<1>(0h0))
node _T_1569 = asUInt(reset)
node _T_1570 = eq(_T_1569, UInt<1>(0h0))
when _T_1570 :
node _T_1571 = eq(_T_1568, UInt<1>(0h0))
when _T_1571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1568, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<17>
connect d_clr_1, UInt<17>(0h0)
wire d_clr_wo_ready_1 : UInt<17>
connect d_clr_wo_ready_1, UInt<17>(0h0)
wire d_opcodes_clr_1 : UInt<68>
connect d_opcodes_clr_1, UInt<68>(0h0)
wire d_sizes_clr_1 : UInt<136>
connect d_sizes_clr_1, UInt<136>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1572 = and(io.in.d.valid, d_first_2)
node _T_1573 = and(_T_1572, UInt<1>(0h1))
node _T_1574 = and(_T_1573, d_release_ack_1)
when _T_1574 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1575 = and(io.in.d.ready, io.in.d.valid)
node _T_1576 = and(_T_1575, d_first_2)
node _T_1577 = and(_T_1576, UInt<1>(0h1))
node _T_1578 = and(_T_1577, d_release_ack_1)
when _T_1578 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1579 = and(io.in.d.valid, d_first_2)
node _T_1580 = and(_T_1579, UInt<1>(0h1))
node _T_1581 = and(_T_1580, d_release_ack_1)
when _T_1581 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1582 = dshr(inflight_1, io.in.d.bits.source)
node _T_1583 = bits(_T_1582, 0, 0)
node _T_1584 = or(_T_1583, same_cycle_resp_1)
node _T_1585 = asUInt(reset)
node _T_1586 = eq(_T_1585, UInt<1>(0h0))
when _T_1586 :
node _T_1587 = eq(_T_1584, UInt<1>(0h0))
when _T_1587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1584, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1588 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1589 = asUInt(reset)
node _T_1590 = eq(_T_1589, UInt<1>(0h0))
when _T_1590 :
node _T_1591 = eq(_T_1588, UInt<1>(0h0))
when _T_1591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1588, UInt<1>(0h1), "") : assert_109
else :
node _T_1592 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1593 = asUInt(reset)
node _T_1594 = eq(_T_1593, UInt<1>(0h0))
when _T_1594 :
node _T_1595 = eq(_T_1592, UInt<1>(0h0))
when _T_1595 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1592, UInt<1>(0h1), "") : assert_110
node _T_1596 = and(io.in.d.valid, d_first_2)
node _T_1597 = and(_T_1596, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1598 = and(_T_1597, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1599 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1600 = and(_T_1598, _T_1599)
node _T_1601 = and(_T_1600, d_release_ack_1)
node _T_1602 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1603 = and(_T_1601, _T_1602)
when _T_1603 :
node _T_1604 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<5>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1605 = or(_T_1604, _WIRE_23.ready)
node _T_1606 = asUInt(reset)
node _T_1607 = eq(_T_1606, UInt<1>(0h0))
when _T_1607 :
node _T_1608 = eq(_T_1605, UInt<1>(0h0))
when _T_1608 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1605, UInt<1>(0h1), "") : assert_111
node _T_1609 = orr(c_set_wo_ready)
when _T_1609 :
node _T_1610 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1611 = asUInt(reset)
node _T_1612 = eq(_T_1611, UInt<1>(0h0))
when _T_1612 :
node _T_1613 = eq(_T_1610, UInt<1>(0h0))
when _T_1613 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1610, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_23
node _T_1614 = orr(inflight_1)
node _T_1615 = eq(_T_1614, UInt<1>(0h0))
node _T_1616 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1617 = or(_T_1615, _T_1616)
node _T_1618 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1619 = or(_T_1617, _T_1618)
node _T_1620 = asUInt(reset)
node _T_1621 = eq(_T_1620, UInt<1>(0h0))
when _T_1621 :
node _T_1622 = eq(_T_1619, UInt<1>(0h0))
when _T_1622 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1619, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1623 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1624 = and(io.in.d.ready, io.in.d.valid)
node _T_1625 = or(_T_1623, _T_1624)
when _T_1625 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_11( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [16:0] inflight; // @[Monitor.scala:614:27]
reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [135:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [31:0] _GEN_0 = {27'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [31:0] _GEN_3 = {27'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [16:0] inflight_1; // @[Monitor.scala:726:35]
reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_16 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T = shr(io.in.a.bits.source, 2)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_6 = shr(io.in.a.bits.source, 2)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_12 = shr(io.in.a.bits.source, 2)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_18 = shr(io.in.a.bits.source, 2)
node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3))
node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22)
wire _source_ok_WIRE : UInt<1>[4]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_11
connect _source_ok_WIRE[2], _source_ok_T_17
connect _source_ok_WIRE[3], _source_ok_T_23
node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2])
node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_4 = shr(io.in.a.bits.source, 2)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<2>(0h3))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_17 = shr(io.in.a.bits.source, 2)
node _T_18 = eq(_T_17, UInt<1>(0h1))
node _T_19 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_20 = and(_T_18, _T_19)
node _T_21 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_25 = cvt(_T_24)
node _T_26 = and(_T_25, asSInt(UInt<1>(0h0)))
node _T_27 = asSInt(_T_26)
node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0)))
node _T_29 = or(_T_23, _T_28)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_30 = shr(io.in.a.bits.source, 2)
node _T_31 = eq(_T_30, UInt<2>(0h2))
node _T_32 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_33 = and(_T_31, _T_32)
node _T_34 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_35 = and(_T_33, _T_34)
node _T_36 = eq(_T_35, UInt<1>(0h0))
node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_38 = cvt(_T_37)
node _T_39 = and(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = asSInt(_T_39)
node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0)))
node _T_42 = or(_T_36, _T_41)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_43 = shr(io.in.a.bits.source, 2)
node _T_44 = eq(_T_43, UInt<2>(0h3))
node _T_45 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_46 = and(_T_44, _T_45)
node _T_47 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(_T_48, UInt<1>(0h0))
node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_51 = cvt(_T_50)
node _T_52 = and(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = asSInt(_T_52)
node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0)))
node _T_55 = or(_T_49, _T_54)
node _T_56 = and(_T_16, _T_29)
node _T_57 = and(_T_56, _T_42)
node _T_58 = and(_T_57, _T_55)
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_T_58, UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_58, UInt<1>(0h1), "") : assert_1
node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_62 :
node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_65 = and(_T_63, _T_64)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_66 = shr(io.in.a.bits.source, 2)
node _T_67 = eq(_T_66, UInt<1>(0h0))
node _T_68 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_69 = and(_T_67, _T_68)
node _T_70 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_71 = and(_T_69, _T_70)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_72 = shr(io.in.a.bits.source, 2)
node _T_73 = eq(_T_72, UInt<1>(0h1))
node _T_74 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_75 = and(_T_73, _T_74)
node _T_76 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_77 = and(_T_75, _T_76)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_78 = shr(io.in.a.bits.source, 2)
node _T_79 = eq(_T_78, UInt<2>(0h2))
node _T_80 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_81 = and(_T_79, _T_80)
node _T_82 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_83 = and(_T_81, _T_82)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_84 = shr(io.in.a.bits.source, 2)
node _T_85 = eq(_T_84, UInt<2>(0h3))
node _T_86 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_87 = and(_T_85, _T_86)
node _T_88 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_89 = and(_T_87, _T_88)
node _T_90 = or(_T_71, _T_77)
node _T_91 = or(_T_90, _T_83)
node _T_92 = or(_T_91, _T_89)
node _T_93 = and(_T_65, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_96 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_97 = cvt(_T_96)
node _T_98 = and(_T_97, asSInt(UInt<14>(0h2000)))
node _T_99 = asSInt(_T_98)
node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_102 = cvt(_T_101)
node _T_103 = and(_T_102, asSInt(UInt<13>(0h1000)))
node _T_104 = asSInt(_T_103)
node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0)))
node _T_106 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<17>(0h10000)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_112 = cvt(_T_111)
node _T_113 = and(_T_112, asSInt(UInt<18>(0h2f000)))
node _T_114 = asSInt(_T_113)
node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0)))
node _T_116 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<17>(0h10000)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_122 = cvt(_T_121)
node _T_123 = and(_T_122, asSInt(UInt<13>(0h1000)))
node _T_124 = asSInt(_T_123)
node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_127 = cvt(_T_126)
node _T_128 = and(_T_127, asSInt(UInt<27>(0h4000000)))
node _T_129 = asSInt(_T_128)
node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0)))
node _T_131 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_132 = cvt(_T_131)
node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000)))
node _T_134 = asSInt(_T_133)
node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0)))
node _T_136 = or(_T_100, _T_105)
node _T_137 = or(_T_136, _T_110)
node _T_138 = or(_T_137, _T_115)
node _T_139 = or(_T_138, _T_120)
node _T_140 = or(_T_139, _T_125)
node _T_141 = or(_T_140, _T_130)
node _T_142 = or(_T_141, _T_135)
node _T_143 = and(_T_95, _T_142)
node _T_144 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_145 = or(UInt<1>(0h0), _T_144)
node _T_146 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<29>(0h10000000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = or(_T_150, _T_155)
node _T_157 = and(_T_145, _T_156)
node _T_158 = or(UInt<1>(0h0), _T_143)
node _T_159 = or(_T_158, _T_157)
node _T_160 = and(_T_94, _T_159)
node _T_161 = asUInt(reset)
node _T_162 = eq(_T_161, UInt<1>(0h0))
when _T_162 :
node _T_163 = eq(_T_160, UInt<1>(0h0))
when _T_163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_160, UInt<1>(0h1), "") : assert_2
node _T_164 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_165 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_166 = and(_T_164, _T_165)
node _T_167 = or(UInt<1>(0h0), _T_166)
node _T_168 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_169 = cvt(_T_168)
node _T_170 = and(_T_169, asSInt(UInt<14>(0h2000)))
node _T_171 = asSInt(_T_170)
node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_174 = cvt(_T_173)
node _T_175 = and(_T_174, asSInt(UInt<13>(0h1000)))
node _T_176 = asSInt(_T_175)
node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0)))
node _T_178 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_179 = cvt(_T_178)
node _T_180 = and(_T_179, asSInt(UInt<17>(0h10000)))
node _T_181 = asSInt(_T_180)
node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0)))
node _T_183 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_184 = cvt(_T_183)
node _T_185 = and(_T_184, asSInt(UInt<18>(0h2f000)))
node _T_186 = asSInt(_T_185)
node _T_187 = eq(_T_186, asSInt(UInt<1>(0h0)))
node _T_188 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_189 = cvt(_T_188)
node _T_190 = and(_T_189, asSInt(UInt<17>(0h10000)))
node _T_191 = asSInt(_T_190)
node _T_192 = eq(_T_191, asSInt(UInt<1>(0h0)))
node _T_193 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<13>(0h1000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_199 = cvt(_T_198)
node _T_200 = and(_T_199, asSInt(UInt<17>(0h10000)))
node _T_201 = asSInt(_T_200)
node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0)))
node _T_203 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_204 = cvt(_T_203)
node _T_205 = and(_T_204, asSInt(UInt<27>(0h4000000)))
node _T_206 = asSInt(_T_205)
node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0)))
node _T_208 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_209 = cvt(_T_208)
node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000)))
node _T_211 = asSInt(_T_210)
node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_214 = cvt(_T_213)
node _T_215 = and(_T_214, asSInt(UInt<29>(0h10000000)))
node _T_216 = asSInt(_T_215)
node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0)))
node _T_218 = or(_T_172, _T_177)
node _T_219 = or(_T_218, _T_182)
node _T_220 = or(_T_219, _T_187)
node _T_221 = or(_T_220, _T_192)
node _T_222 = or(_T_221, _T_197)
node _T_223 = or(_T_222, _T_202)
node _T_224 = or(_T_223, _T_207)
node _T_225 = or(_T_224, _T_212)
node _T_226 = or(_T_225, _T_217)
node _T_227 = and(_T_167, _T_226)
node _T_228 = or(UInt<1>(0h0), _T_227)
node _T_229 = and(UInt<1>(0h0), _T_228)
node _T_230 = asUInt(reset)
node _T_231 = eq(_T_230, UInt<1>(0h0))
when _T_231 :
node _T_232 = eq(_T_229, UInt<1>(0h0))
when _T_232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_229, UInt<1>(0h1), "") : assert_3
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(source_ok, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_236 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_237 = asUInt(reset)
node _T_238 = eq(_T_237, UInt<1>(0h0))
when _T_238 :
node _T_239 = eq(_T_236, UInt<1>(0h0))
when _T_239 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_236, UInt<1>(0h1), "") : assert_5
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(is_aligned, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_243 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_243, UInt<1>(0h1), "") : assert_7
node _T_247 = not(io.in.a.bits.mask)
node _T_248 = eq(_T_247, UInt<1>(0h0))
node _T_249 = asUInt(reset)
node _T_250 = eq(_T_249, UInt<1>(0h0))
when _T_250 :
node _T_251 = eq(_T_248, UInt<1>(0h0))
when _T_251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_248, UInt<1>(0h1), "") : assert_8
node _T_252 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_253 = asUInt(reset)
node _T_254 = eq(_T_253, UInt<1>(0h0))
when _T_254 :
node _T_255 = eq(_T_252, UInt<1>(0h0))
when _T_255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_252, UInt<1>(0h1), "") : assert_9
node _T_256 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_256 :
node _T_257 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_258 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_259 = and(_T_257, _T_258)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_260 = shr(io.in.a.bits.source, 2)
node _T_261 = eq(_T_260, UInt<1>(0h0))
node _T_262 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_263 = and(_T_261, _T_262)
node _T_264 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_265 = and(_T_263, _T_264)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_266 = shr(io.in.a.bits.source, 2)
node _T_267 = eq(_T_266, UInt<1>(0h1))
node _T_268 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_269 = and(_T_267, _T_268)
node _T_270 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_271 = and(_T_269, _T_270)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_272 = shr(io.in.a.bits.source, 2)
node _T_273 = eq(_T_272, UInt<2>(0h2))
node _T_274 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_275 = and(_T_273, _T_274)
node _T_276 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_277 = and(_T_275, _T_276)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_278 = shr(io.in.a.bits.source, 2)
node _T_279 = eq(_T_278, UInt<2>(0h3))
node _T_280 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_281 = and(_T_279, _T_280)
node _T_282 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_283 = and(_T_281, _T_282)
node _T_284 = or(_T_265, _T_271)
node _T_285 = or(_T_284, _T_277)
node _T_286 = or(_T_285, _T_283)
node _T_287 = and(_T_259, _T_286)
node _T_288 = or(UInt<1>(0h0), _T_287)
node _T_289 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_291 = cvt(_T_290)
node _T_292 = and(_T_291, asSInt(UInt<14>(0h2000)))
node _T_293 = asSInt(_T_292)
node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0)))
node _T_295 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_296 = cvt(_T_295)
node _T_297 = and(_T_296, asSInt(UInt<13>(0h1000)))
node _T_298 = asSInt(_T_297)
node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0)))
node _T_300 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_301 = cvt(_T_300)
node _T_302 = and(_T_301, asSInt(UInt<17>(0h10000)))
node _T_303 = asSInt(_T_302)
node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0)))
node _T_305 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_306 = cvt(_T_305)
node _T_307 = and(_T_306, asSInt(UInt<18>(0h2f000)))
node _T_308 = asSInt(_T_307)
node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0)))
node _T_310 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_311 = cvt(_T_310)
node _T_312 = and(_T_311, asSInt(UInt<17>(0h10000)))
node _T_313 = asSInt(_T_312)
node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0)))
node _T_315 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_316 = cvt(_T_315)
node _T_317 = and(_T_316, asSInt(UInt<13>(0h1000)))
node _T_318 = asSInt(_T_317)
node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0)))
node _T_320 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_321 = cvt(_T_320)
node _T_322 = and(_T_321, asSInt(UInt<27>(0h4000000)))
node _T_323 = asSInt(_T_322)
node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0)))
node _T_325 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_326 = cvt(_T_325)
node _T_327 = and(_T_326, asSInt(UInt<13>(0h1000)))
node _T_328 = asSInt(_T_327)
node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0)))
node _T_330 = or(_T_294, _T_299)
node _T_331 = or(_T_330, _T_304)
node _T_332 = or(_T_331, _T_309)
node _T_333 = or(_T_332, _T_314)
node _T_334 = or(_T_333, _T_319)
node _T_335 = or(_T_334, _T_324)
node _T_336 = or(_T_335, _T_329)
node _T_337 = and(_T_289, _T_336)
node _T_338 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_339 = or(UInt<1>(0h0), _T_338)
node _T_340 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_341 = cvt(_T_340)
node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000)))
node _T_343 = asSInt(_T_342)
node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0)))
node _T_345 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_346 = cvt(_T_345)
node _T_347 = and(_T_346, asSInt(UInt<29>(0h10000000)))
node _T_348 = asSInt(_T_347)
node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0)))
node _T_350 = or(_T_344, _T_349)
node _T_351 = and(_T_339, _T_350)
node _T_352 = or(UInt<1>(0h0), _T_337)
node _T_353 = or(_T_352, _T_351)
node _T_354 = and(_T_288, _T_353)
node _T_355 = asUInt(reset)
node _T_356 = eq(_T_355, UInt<1>(0h0))
when _T_356 :
node _T_357 = eq(_T_354, UInt<1>(0h0))
when _T_357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_354, UInt<1>(0h1), "") : assert_10
node _T_358 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_359 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_360 = and(_T_358, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_363 = cvt(_T_362)
node _T_364 = and(_T_363, asSInt(UInt<14>(0h2000)))
node _T_365 = asSInt(_T_364)
node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0)))
node _T_367 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_368 = cvt(_T_367)
node _T_369 = and(_T_368, asSInt(UInt<13>(0h1000)))
node _T_370 = asSInt(_T_369)
node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0)))
node _T_372 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_373 = cvt(_T_372)
node _T_374 = and(_T_373, asSInt(UInt<17>(0h10000)))
node _T_375 = asSInt(_T_374)
node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0)))
node _T_377 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_378 = cvt(_T_377)
node _T_379 = and(_T_378, asSInt(UInt<18>(0h2f000)))
node _T_380 = asSInt(_T_379)
node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0)))
node _T_382 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_383 = cvt(_T_382)
node _T_384 = and(_T_383, asSInt(UInt<17>(0h10000)))
node _T_385 = asSInt(_T_384)
node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0)))
node _T_387 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_388 = cvt(_T_387)
node _T_389 = and(_T_388, asSInt(UInt<13>(0h1000)))
node _T_390 = asSInt(_T_389)
node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0)))
node _T_392 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_393 = cvt(_T_392)
node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000)))
node _T_395 = asSInt(_T_394)
node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0)))
node _T_397 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_398 = cvt(_T_397)
node _T_399 = and(_T_398, asSInt(UInt<27>(0h4000000)))
node _T_400 = asSInt(_T_399)
node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0)))
node _T_402 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_403 = cvt(_T_402)
node _T_404 = and(_T_403, asSInt(UInt<13>(0h1000)))
node _T_405 = asSInt(_T_404)
node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0)))
node _T_407 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_408 = cvt(_T_407)
node _T_409 = and(_T_408, asSInt(UInt<29>(0h10000000)))
node _T_410 = asSInt(_T_409)
node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0)))
node _T_412 = or(_T_366, _T_371)
node _T_413 = or(_T_412, _T_376)
node _T_414 = or(_T_413, _T_381)
node _T_415 = or(_T_414, _T_386)
node _T_416 = or(_T_415, _T_391)
node _T_417 = or(_T_416, _T_396)
node _T_418 = or(_T_417, _T_401)
node _T_419 = or(_T_418, _T_406)
node _T_420 = or(_T_419, _T_411)
node _T_421 = and(_T_361, _T_420)
node _T_422 = or(UInt<1>(0h0), _T_421)
node _T_423 = and(UInt<1>(0h0), _T_422)
node _T_424 = asUInt(reset)
node _T_425 = eq(_T_424, UInt<1>(0h0))
when _T_425 :
node _T_426 = eq(_T_423, UInt<1>(0h0))
when _T_426 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_423, UInt<1>(0h1), "") : assert_11
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(source_ok, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_430 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_431 = asUInt(reset)
node _T_432 = eq(_T_431, UInt<1>(0h0))
when _T_432 :
node _T_433 = eq(_T_430, UInt<1>(0h0))
when _T_433 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_430, UInt<1>(0h1), "") : assert_13
node _T_434 = asUInt(reset)
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(is_aligned, UInt<1>(0h0))
when _T_436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_437 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_T_437, UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_437, UInt<1>(0h1), "") : assert_15
node _T_441 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(_T_441, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_441, UInt<1>(0h1), "") : assert_16
node _T_445 = not(io.in.a.bits.mask)
node _T_446 = eq(_T_445, UInt<1>(0h0))
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_T_446, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_446, UInt<1>(0h1), "") : assert_17
node _T_450 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(_T_450, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_450, UInt<1>(0h1), "") : assert_18
node _T_454 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_454 :
node _T_455 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_456 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_457 = and(_T_455, _T_456)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_458 = shr(io.in.a.bits.source, 2)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_461 = and(_T_459, _T_460)
node _T_462 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_463 = and(_T_461, _T_462)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_464 = shr(io.in.a.bits.source, 2)
node _T_465 = eq(_T_464, UInt<1>(0h1))
node _T_466 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_467 = and(_T_465, _T_466)
node _T_468 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_469 = and(_T_467, _T_468)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_470 = shr(io.in.a.bits.source, 2)
node _T_471 = eq(_T_470, UInt<2>(0h2))
node _T_472 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_473 = and(_T_471, _T_472)
node _T_474 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_475 = and(_T_473, _T_474)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_476 = shr(io.in.a.bits.source, 2)
node _T_477 = eq(_T_476, UInt<2>(0h3))
node _T_478 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_479 = and(_T_477, _T_478)
node _T_480 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_481 = and(_T_479, _T_480)
node _T_482 = or(_T_463, _T_469)
node _T_483 = or(_T_482, _T_475)
node _T_484 = or(_T_483, _T_481)
node _T_485 = and(_T_457, _T_484)
node _T_486 = or(UInt<1>(0h0), _T_485)
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_486, UInt<1>(0h1), "") : assert_19
node _T_490 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_491 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_492 = and(_T_490, _T_491)
node _T_493 = or(UInt<1>(0h0), _T_492)
node _T_494 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_495 = cvt(_T_494)
node _T_496 = and(_T_495, asSInt(UInt<13>(0h1000)))
node _T_497 = asSInt(_T_496)
node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0)))
node _T_499 = and(_T_493, _T_498)
node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_501 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_502 = and(_T_500, _T_501)
node _T_503 = or(UInt<1>(0h0), _T_502)
node _T_504 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_505 = cvt(_T_504)
node _T_506 = and(_T_505, asSInt(UInt<14>(0h2000)))
node _T_507 = asSInt(_T_506)
node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0)))
node _T_509 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_510 = cvt(_T_509)
node _T_511 = and(_T_510, asSInt(UInt<17>(0h10000)))
node _T_512 = asSInt(_T_511)
node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0)))
node _T_514 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_515 = cvt(_T_514)
node _T_516 = and(_T_515, asSInt(UInt<18>(0h2f000)))
node _T_517 = asSInt(_T_516)
node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0)))
node _T_519 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_520 = cvt(_T_519)
node _T_521 = and(_T_520, asSInt(UInt<17>(0h10000)))
node _T_522 = asSInt(_T_521)
node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0)))
node _T_524 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_525 = cvt(_T_524)
node _T_526 = and(_T_525, asSInt(UInt<13>(0h1000)))
node _T_527 = asSInt(_T_526)
node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0)))
node _T_529 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_530 = cvt(_T_529)
node _T_531 = and(_T_530, asSInt(UInt<17>(0h10000)))
node _T_532 = asSInt(_T_531)
node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0)))
node _T_534 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_535 = cvt(_T_534)
node _T_536 = and(_T_535, asSInt(UInt<27>(0h4000000)))
node _T_537 = asSInt(_T_536)
node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0)))
node _T_539 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_540 = cvt(_T_539)
node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000)))
node _T_542 = asSInt(_T_541)
node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0)))
node _T_544 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_545 = cvt(_T_544)
node _T_546 = and(_T_545, asSInt(UInt<29>(0h10000000)))
node _T_547 = asSInt(_T_546)
node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0)))
node _T_549 = or(_T_508, _T_513)
node _T_550 = or(_T_549, _T_518)
node _T_551 = or(_T_550, _T_523)
node _T_552 = or(_T_551, _T_528)
node _T_553 = or(_T_552, _T_533)
node _T_554 = or(_T_553, _T_538)
node _T_555 = or(_T_554, _T_543)
node _T_556 = or(_T_555, _T_548)
node _T_557 = and(_T_503, _T_556)
node _T_558 = or(UInt<1>(0h0), _T_499)
node _T_559 = or(_T_558, _T_557)
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_559, UInt<1>(0h1), "") : assert_20
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(source_ok, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_566 = asUInt(reset)
node _T_567 = eq(_T_566, UInt<1>(0h0))
when _T_567 :
node _T_568 = eq(is_aligned, UInt<1>(0h0))
when _T_568 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_569 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_569, UInt<1>(0h1), "") : assert_23
node _T_573 = eq(io.in.a.bits.mask, mask)
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_T_573, UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_573, UInt<1>(0h1), "") : assert_24
node _T_577 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_577, UInt<1>(0h1), "") : assert_25
node _T_581 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_581 :
node _T_582 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_583 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_584 = and(_T_582, _T_583)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_585 = shr(io.in.a.bits.source, 2)
node _T_586 = eq(_T_585, UInt<1>(0h0))
node _T_587 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_588 = and(_T_586, _T_587)
node _T_589 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_590 = and(_T_588, _T_589)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_591 = shr(io.in.a.bits.source, 2)
node _T_592 = eq(_T_591, UInt<1>(0h1))
node _T_593 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_594 = and(_T_592, _T_593)
node _T_595 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_596 = and(_T_594, _T_595)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_597 = shr(io.in.a.bits.source, 2)
node _T_598 = eq(_T_597, UInt<2>(0h2))
node _T_599 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_600 = and(_T_598, _T_599)
node _T_601 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_602 = and(_T_600, _T_601)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_603 = shr(io.in.a.bits.source, 2)
node _T_604 = eq(_T_603, UInt<2>(0h3))
node _T_605 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_606 = and(_T_604, _T_605)
node _T_607 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_608 = and(_T_606, _T_607)
node _T_609 = or(_T_590, _T_596)
node _T_610 = or(_T_609, _T_602)
node _T_611 = or(_T_610, _T_608)
node _T_612 = and(_T_584, _T_611)
node _T_613 = or(UInt<1>(0h0), _T_612)
node _T_614 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_615 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_616 = and(_T_614, _T_615)
node _T_617 = or(UInt<1>(0h0), _T_616)
node _T_618 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_619 = cvt(_T_618)
node _T_620 = and(_T_619, asSInt(UInt<13>(0h1000)))
node _T_621 = asSInt(_T_620)
node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0)))
node _T_623 = and(_T_617, _T_622)
node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_626 = and(_T_624, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_629 = cvt(_T_628)
node _T_630 = and(_T_629, asSInt(UInt<14>(0h2000)))
node _T_631 = asSInt(_T_630)
node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0)))
node _T_633 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_634 = cvt(_T_633)
node _T_635 = and(_T_634, asSInt(UInt<18>(0h2f000)))
node _T_636 = asSInt(_T_635)
node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0)))
node _T_638 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_639 = cvt(_T_638)
node _T_640 = and(_T_639, asSInt(UInt<17>(0h10000)))
node _T_641 = asSInt(_T_640)
node _T_642 = eq(_T_641, asSInt(UInt<1>(0h0)))
node _T_643 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_644 = cvt(_T_643)
node _T_645 = and(_T_644, asSInt(UInt<13>(0h1000)))
node _T_646 = asSInt(_T_645)
node _T_647 = eq(_T_646, asSInt(UInt<1>(0h0)))
node _T_648 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_649 = cvt(_T_648)
node _T_650 = and(_T_649, asSInt(UInt<17>(0h10000)))
node _T_651 = asSInt(_T_650)
node _T_652 = eq(_T_651, asSInt(UInt<1>(0h0)))
node _T_653 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<27>(0h4000000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_659 = cvt(_T_658)
node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000)))
node _T_661 = asSInt(_T_660)
node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0)))
node _T_663 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<29>(0h10000000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = or(_T_632, _T_637)
node _T_669 = or(_T_668, _T_642)
node _T_670 = or(_T_669, _T_647)
node _T_671 = or(_T_670, _T_652)
node _T_672 = or(_T_671, _T_657)
node _T_673 = or(_T_672, _T_662)
node _T_674 = or(_T_673, _T_667)
node _T_675 = and(_T_627, _T_674)
node _T_676 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_677 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_678 = cvt(_T_677)
node _T_679 = and(_T_678, asSInt(UInt<17>(0h10000)))
node _T_680 = asSInt(_T_679)
node _T_681 = eq(_T_680, asSInt(UInt<1>(0h0)))
node _T_682 = and(_T_676, _T_681)
node _T_683 = or(UInt<1>(0h0), _T_623)
node _T_684 = or(_T_683, _T_675)
node _T_685 = or(_T_684, _T_682)
node _T_686 = and(_T_613, _T_685)
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(_T_686, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_686, UInt<1>(0h1), "") : assert_26
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(source_ok, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_693 = asUInt(reset)
node _T_694 = eq(_T_693, UInt<1>(0h0))
when _T_694 :
node _T_695 = eq(is_aligned, UInt<1>(0h0))
when _T_695 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_696 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_696, UInt<1>(0h1), "") : assert_29
node _T_700 = eq(io.in.a.bits.mask, mask)
node _T_701 = asUInt(reset)
node _T_702 = eq(_T_701, UInt<1>(0h0))
when _T_702 :
node _T_703 = eq(_T_700, UInt<1>(0h0))
when _T_703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_700, UInt<1>(0h1), "") : assert_30
node _T_704 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_704 :
node _T_705 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_706 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_707 = and(_T_705, _T_706)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_708 = shr(io.in.a.bits.source, 2)
node _T_709 = eq(_T_708, UInt<1>(0h0))
node _T_710 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_711 = and(_T_709, _T_710)
node _T_712 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_713 = and(_T_711, _T_712)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_714 = shr(io.in.a.bits.source, 2)
node _T_715 = eq(_T_714, UInt<1>(0h1))
node _T_716 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_717 = and(_T_715, _T_716)
node _T_718 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_719 = and(_T_717, _T_718)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_720 = shr(io.in.a.bits.source, 2)
node _T_721 = eq(_T_720, UInt<2>(0h2))
node _T_722 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_723 = and(_T_721, _T_722)
node _T_724 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_725 = and(_T_723, _T_724)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_726 = shr(io.in.a.bits.source, 2)
node _T_727 = eq(_T_726, UInt<2>(0h3))
node _T_728 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_729 = and(_T_727, _T_728)
node _T_730 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_731 = and(_T_729, _T_730)
node _T_732 = or(_T_713, _T_719)
node _T_733 = or(_T_732, _T_725)
node _T_734 = or(_T_733, _T_731)
node _T_735 = and(_T_707, _T_734)
node _T_736 = or(UInt<1>(0h0), _T_735)
node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_738 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_739 = and(_T_737, _T_738)
node _T_740 = or(UInt<1>(0h0), _T_739)
node _T_741 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_742 = cvt(_T_741)
node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000)))
node _T_744 = asSInt(_T_743)
node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0)))
node _T_746 = and(_T_740, _T_745)
node _T_747 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_748 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_749 = and(_T_747, _T_748)
node _T_750 = or(UInt<1>(0h0), _T_749)
node _T_751 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_752 = cvt(_T_751)
node _T_753 = and(_T_752, asSInt(UInt<14>(0h2000)))
node _T_754 = asSInt(_T_753)
node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0)))
node _T_756 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_757 = cvt(_T_756)
node _T_758 = and(_T_757, asSInt(UInt<18>(0h2f000)))
node _T_759 = asSInt(_T_758)
node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0)))
node _T_761 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_762 = cvt(_T_761)
node _T_763 = and(_T_762, asSInt(UInt<17>(0h10000)))
node _T_764 = asSInt(_T_763)
node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0)))
node _T_766 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_767 = cvt(_T_766)
node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000)))
node _T_769 = asSInt(_T_768)
node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0)))
node _T_771 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_772 = cvt(_T_771)
node _T_773 = and(_T_772, asSInt(UInt<17>(0h10000)))
node _T_774 = asSInt(_T_773)
node _T_775 = eq(_T_774, asSInt(UInt<1>(0h0)))
node _T_776 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_777 = cvt(_T_776)
node _T_778 = and(_T_777, asSInt(UInt<27>(0h4000000)))
node _T_779 = asSInt(_T_778)
node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0)))
node _T_781 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_782 = cvt(_T_781)
node _T_783 = and(_T_782, asSInt(UInt<13>(0h1000)))
node _T_784 = asSInt(_T_783)
node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0)))
node _T_786 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_787 = cvt(_T_786)
node _T_788 = and(_T_787, asSInt(UInt<29>(0h10000000)))
node _T_789 = asSInt(_T_788)
node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0)))
node _T_791 = or(_T_755, _T_760)
node _T_792 = or(_T_791, _T_765)
node _T_793 = or(_T_792, _T_770)
node _T_794 = or(_T_793, _T_775)
node _T_795 = or(_T_794, _T_780)
node _T_796 = or(_T_795, _T_785)
node _T_797 = or(_T_796, _T_790)
node _T_798 = and(_T_750, _T_797)
node _T_799 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_800 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_801 = cvt(_T_800)
node _T_802 = and(_T_801, asSInt(UInt<17>(0h10000)))
node _T_803 = asSInt(_T_802)
node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0)))
node _T_805 = and(_T_799, _T_804)
node _T_806 = or(UInt<1>(0h0), _T_746)
node _T_807 = or(_T_806, _T_798)
node _T_808 = or(_T_807, _T_805)
node _T_809 = and(_T_736, _T_808)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_809, UInt<1>(0h1), "") : assert_31
node _T_813 = asUInt(reset)
node _T_814 = eq(_T_813, UInt<1>(0h0))
when _T_814 :
node _T_815 = eq(source_ok, UInt<1>(0h0))
when _T_815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_816 = asUInt(reset)
node _T_817 = eq(_T_816, UInt<1>(0h0))
when _T_817 :
node _T_818 = eq(is_aligned, UInt<1>(0h0))
when _T_818 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_819 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_820 = asUInt(reset)
node _T_821 = eq(_T_820, UInt<1>(0h0))
when _T_821 :
node _T_822 = eq(_T_819, UInt<1>(0h0))
when _T_822 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_819, UInt<1>(0h1), "") : assert_34
node _T_823 = not(mask)
node _T_824 = and(io.in.a.bits.mask, _T_823)
node _T_825 = eq(_T_824, UInt<1>(0h0))
node _T_826 = asUInt(reset)
node _T_827 = eq(_T_826, UInt<1>(0h0))
when _T_827 :
node _T_828 = eq(_T_825, UInt<1>(0h0))
when _T_828 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_825, UInt<1>(0h1), "") : assert_35
node _T_829 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_829 :
node _T_830 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_831 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_832 = and(_T_830, _T_831)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_833 = shr(io.in.a.bits.source, 2)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_836 = and(_T_834, _T_835)
node _T_837 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_838 = and(_T_836, _T_837)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_839 = shr(io.in.a.bits.source, 2)
node _T_840 = eq(_T_839, UInt<1>(0h1))
node _T_841 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_842 = and(_T_840, _T_841)
node _T_843 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_844 = and(_T_842, _T_843)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_845 = shr(io.in.a.bits.source, 2)
node _T_846 = eq(_T_845, UInt<2>(0h2))
node _T_847 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_848 = and(_T_846, _T_847)
node _T_849 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_850 = and(_T_848, _T_849)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_851 = shr(io.in.a.bits.source, 2)
node _T_852 = eq(_T_851, UInt<2>(0h3))
node _T_853 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_854 = and(_T_852, _T_853)
node _T_855 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_856 = and(_T_854, _T_855)
node _T_857 = or(_T_838, _T_844)
node _T_858 = or(_T_857, _T_850)
node _T_859 = or(_T_858, _T_856)
node _T_860 = and(_T_832, _T_859)
node _T_861 = or(UInt<1>(0h0), _T_860)
node _T_862 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_863 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_864 = and(_T_862, _T_863)
node _T_865 = or(UInt<1>(0h0), _T_864)
node _T_866 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_867 = cvt(_T_866)
node _T_868 = and(_T_867, asSInt(UInt<14>(0h2000)))
node _T_869 = asSInt(_T_868)
node _T_870 = eq(_T_869, asSInt(UInt<1>(0h0)))
node _T_871 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_872 = cvt(_T_871)
node _T_873 = and(_T_872, asSInt(UInt<13>(0h1000)))
node _T_874 = asSInt(_T_873)
node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0)))
node _T_876 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_877 = cvt(_T_876)
node _T_878 = and(_T_877, asSInt(UInt<18>(0h2f000)))
node _T_879 = asSInt(_T_878)
node _T_880 = eq(_T_879, asSInt(UInt<1>(0h0)))
node _T_881 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_882 = cvt(_T_881)
node _T_883 = and(_T_882, asSInt(UInt<17>(0h10000)))
node _T_884 = asSInt(_T_883)
node _T_885 = eq(_T_884, asSInt(UInt<1>(0h0)))
node _T_886 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_887 = cvt(_T_886)
node _T_888 = and(_T_887, asSInt(UInt<13>(0h1000)))
node _T_889 = asSInt(_T_888)
node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0)))
node _T_891 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_892 = cvt(_T_891)
node _T_893 = and(_T_892, asSInt(UInt<17>(0h10000)))
node _T_894 = asSInt(_T_893)
node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0)))
node _T_896 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_897 = cvt(_T_896)
node _T_898 = and(_T_897, asSInt(UInt<27>(0h4000000)))
node _T_899 = asSInt(_T_898)
node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0)))
node _T_901 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_902 = cvt(_T_901)
node _T_903 = and(_T_902, asSInt(UInt<13>(0h1000)))
node _T_904 = asSInt(_T_903)
node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0)))
node _T_906 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_907 = cvt(_T_906)
node _T_908 = and(_T_907, asSInt(UInt<29>(0h10000000)))
node _T_909 = asSInt(_T_908)
node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0)))
node _T_911 = or(_T_870, _T_875)
node _T_912 = or(_T_911, _T_880)
node _T_913 = or(_T_912, _T_885)
node _T_914 = or(_T_913, _T_890)
node _T_915 = or(_T_914, _T_895)
node _T_916 = or(_T_915, _T_900)
node _T_917 = or(_T_916, _T_905)
node _T_918 = or(_T_917, _T_910)
node _T_919 = and(_T_865, _T_918)
node _T_920 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_921 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_922 = cvt(_T_921)
node _T_923 = and(_T_922, asSInt(UInt<17>(0h10000)))
node _T_924 = asSInt(_T_923)
node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0)))
node _T_926 = and(_T_920, _T_925)
node _T_927 = or(UInt<1>(0h0), _T_919)
node _T_928 = or(_T_927, _T_926)
node _T_929 = and(_T_861, _T_928)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_929, UInt<1>(0h1), "") : assert_36
node _T_933 = asUInt(reset)
node _T_934 = eq(_T_933, UInt<1>(0h0))
when _T_934 :
node _T_935 = eq(source_ok, UInt<1>(0h0))
when _T_935 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_936 = asUInt(reset)
node _T_937 = eq(_T_936, UInt<1>(0h0))
when _T_937 :
node _T_938 = eq(is_aligned, UInt<1>(0h0))
when _T_938 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_939 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_940 = asUInt(reset)
node _T_941 = eq(_T_940, UInt<1>(0h0))
when _T_941 :
node _T_942 = eq(_T_939, UInt<1>(0h0))
when _T_942 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_939, UInt<1>(0h1), "") : assert_39
node _T_943 = eq(io.in.a.bits.mask, mask)
node _T_944 = asUInt(reset)
node _T_945 = eq(_T_944, UInt<1>(0h0))
when _T_945 :
node _T_946 = eq(_T_943, UInt<1>(0h0))
when _T_946 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_943, UInt<1>(0h1), "") : assert_40
node _T_947 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_947 :
node _T_948 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_949 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_950 = and(_T_948, _T_949)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_951 = shr(io.in.a.bits.source, 2)
node _T_952 = eq(_T_951, UInt<1>(0h0))
node _T_953 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_954 = and(_T_952, _T_953)
node _T_955 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_956 = and(_T_954, _T_955)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_957 = shr(io.in.a.bits.source, 2)
node _T_958 = eq(_T_957, UInt<1>(0h1))
node _T_959 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_960 = and(_T_958, _T_959)
node _T_961 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_962 = and(_T_960, _T_961)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_963 = shr(io.in.a.bits.source, 2)
node _T_964 = eq(_T_963, UInt<2>(0h2))
node _T_965 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_966 = and(_T_964, _T_965)
node _T_967 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_968 = and(_T_966, _T_967)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_969 = shr(io.in.a.bits.source, 2)
node _T_970 = eq(_T_969, UInt<2>(0h3))
node _T_971 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_972 = and(_T_970, _T_971)
node _T_973 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_974 = and(_T_972, _T_973)
node _T_975 = or(_T_956, _T_962)
node _T_976 = or(_T_975, _T_968)
node _T_977 = or(_T_976, _T_974)
node _T_978 = and(_T_950, _T_977)
node _T_979 = or(UInt<1>(0h0), _T_978)
node _T_980 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_981 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_982 = and(_T_980, _T_981)
node _T_983 = or(UInt<1>(0h0), _T_982)
node _T_984 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_985 = cvt(_T_984)
node _T_986 = and(_T_985, asSInt(UInt<14>(0h2000)))
node _T_987 = asSInt(_T_986)
node _T_988 = eq(_T_987, asSInt(UInt<1>(0h0)))
node _T_989 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_990 = cvt(_T_989)
node _T_991 = and(_T_990, asSInt(UInt<13>(0h1000)))
node _T_992 = asSInt(_T_991)
node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0)))
node _T_994 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_995 = cvt(_T_994)
node _T_996 = and(_T_995, asSInt(UInt<18>(0h2f000)))
node _T_997 = asSInt(_T_996)
node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0)))
node _T_999 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1000 = cvt(_T_999)
node _T_1001 = and(_T_1000, asSInt(UInt<17>(0h10000)))
node _T_1002 = asSInt(_T_1001)
node _T_1003 = eq(_T_1002, asSInt(UInt<1>(0h0)))
node _T_1004 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1005 = cvt(_T_1004)
node _T_1006 = and(_T_1005, asSInt(UInt<13>(0h1000)))
node _T_1007 = asSInt(_T_1006)
node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0)))
node _T_1009 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1010 = cvt(_T_1009)
node _T_1011 = and(_T_1010, asSInt(UInt<17>(0h10000)))
node _T_1012 = asSInt(_T_1011)
node _T_1013 = eq(_T_1012, asSInt(UInt<1>(0h0)))
node _T_1014 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1015 = cvt(_T_1014)
node _T_1016 = and(_T_1015, asSInt(UInt<27>(0h4000000)))
node _T_1017 = asSInt(_T_1016)
node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0)))
node _T_1019 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1020 = cvt(_T_1019)
node _T_1021 = and(_T_1020, asSInt(UInt<13>(0h1000)))
node _T_1022 = asSInt(_T_1021)
node _T_1023 = eq(_T_1022, asSInt(UInt<1>(0h0)))
node _T_1024 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1025 = cvt(_T_1024)
node _T_1026 = and(_T_1025, asSInt(UInt<29>(0h10000000)))
node _T_1027 = asSInt(_T_1026)
node _T_1028 = eq(_T_1027, asSInt(UInt<1>(0h0)))
node _T_1029 = or(_T_988, _T_993)
node _T_1030 = or(_T_1029, _T_998)
node _T_1031 = or(_T_1030, _T_1003)
node _T_1032 = or(_T_1031, _T_1008)
node _T_1033 = or(_T_1032, _T_1013)
node _T_1034 = or(_T_1033, _T_1018)
node _T_1035 = or(_T_1034, _T_1023)
node _T_1036 = or(_T_1035, _T_1028)
node _T_1037 = and(_T_983, _T_1036)
node _T_1038 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1039 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1040 = cvt(_T_1039)
node _T_1041 = and(_T_1040, asSInt(UInt<17>(0h10000)))
node _T_1042 = asSInt(_T_1041)
node _T_1043 = eq(_T_1042, asSInt(UInt<1>(0h0)))
node _T_1044 = and(_T_1038, _T_1043)
node _T_1045 = or(UInt<1>(0h0), _T_1037)
node _T_1046 = or(_T_1045, _T_1044)
node _T_1047 = and(_T_979, _T_1046)
node _T_1048 = asUInt(reset)
node _T_1049 = eq(_T_1048, UInt<1>(0h0))
when _T_1049 :
node _T_1050 = eq(_T_1047, UInt<1>(0h0))
when _T_1050 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1047, UInt<1>(0h1), "") : assert_41
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(source_ok, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(is_aligned, UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1057 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_44
node _T_1061 = eq(io.in.a.bits.mask, mask)
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_T_1061, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1061, UInt<1>(0h1), "") : assert_45
node _T_1065 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1065 :
node _T_1066 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1067 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1068 = and(_T_1066, _T_1067)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1069 = shr(io.in.a.bits.source, 2)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
node _T_1071 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1072 = and(_T_1070, _T_1071)
node _T_1073 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1074 = and(_T_1072, _T_1073)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1075 = shr(io.in.a.bits.source, 2)
node _T_1076 = eq(_T_1075, UInt<1>(0h1))
node _T_1077 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1078 = and(_T_1076, _T_1077)
node _T_1079 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1080 = and(_T_1078, _T_1079)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1081 = shr(io.in.a.bits.source, 2)
node _T_1082 = eq(_T_1081, UInt<2>(0h2))
node _T_1083 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1084 = and(_T_1082, _T_1083)
node _T_1085 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1086 = and(_T_1084, _T_1085)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1087 = shr(io.in.a.bits.source, 2)
node _T_1088 = eq(_T_1087, UInt<2>(0h3))
node _T_1089 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1090 = and(_T_1088, _T_1089)
node _T_1091 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1092 = and(_T_1090, _T_1091)
node _T_1093 = or(_T_1074, _T_1080)
node _T_1094 = or(_T_1093, _T_1086)
node _T_1095 = or(_T_1094, _T_1092)
node _T_1096 = and(_T_1068, _T_1095)
node _T_1097 = or(UInt<1>(0h0), _T_1096)
node _T_1098 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1099 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1100 = and(_T_1098, _T_1099)
node _T_1101 = or(UInt<1>(0h0), _T_1100)
node _T_1102 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1103 = cvt(_T_1102)
node _T_1104 = and(_T_1103, asSInt(UInt<13>(0h1000)))
node _T_1105 = asSInt(_T_1104)
node _T_1106 = eq(_T_1105, asSInt(UInt<1>(0h0)))
node _T_1107 = and(_T_1101, _T_1106)
node _T_1108 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1109 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1110 = cvt(_T_1109)
node _T_1111 = and(_T_1110, asSInt(UInt<14>(0h2000)))
node _T_1112 = asSInt(_T_1111)
node _T_1113 = eq(_T_1112, asSInt(UInt<1>(0h0)))
node _T_1114 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1115 = cvt(_T_1114)
node _T_1116 = and(_T_1115, asSInt(UInt<17>(0h10000)))
node _T_1117 = asSInt(_T_1116)
node _T_1118 = eq(_T_1117, asSInt(UInt<1>(0h0)))
node _T_1119 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1120 = cvt(_T_1119)
node _T_1121 = and(_T_1120, asSInt(UInt<18>(0h2f000)))
node _T_1122 = asSInt(_T_1121)
node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0)))
node _T_1124 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1125 = cvt(_T_1124)
node _T_1126 = and(_T_1125, asSInt(UInt<17>(0h10000)))
node _T_1127 = asSInt(_T_1126)
node _T_1128 = eq(_T_1127, asSInt(UInt<1>(0h0)))
node _T_1129 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1130 = cvt(_T_1129)
node _T_1131 = and(_T_1130, asSInt(UInt<13>(0h1000)))
node _T_1132 = asSInt(_T_1131)
node _T_1133 = eq(_T_1132, asSInt(UInt<1>(0h0)))
node _T_1134 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1135 = cvt(_T_1134)
node _T_1136 = and(_T_1135, asSInt(UInt<27>(0h4000000)))
node _T_1137 = asSInt(_T_1136)
node _T_1138 = eq(_T_1137, asSInt(UInt<1>(0h0)))
node _T_1139 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1140 = cvt(_T_1139)
node _T_1141 = and(_T_1140, asSInt(UInt<13>(0h1000)))
node _T_1142 = asSInt(_T_1141)
node _T_1143 = eq(_T_1142, asSInt(UInt<1>(0h0)))
node _T_1144 = or(_T_1113, _T_1118)
node _T_1145 = or(_T_1144, _T_1123)
node _T_1146 = or(_T_1145, _T_1128)
node _T_1147 = or(_T_1146, _T_1133)
node _T_1148 = or(_T_1147, _T_1138)
node _T_1149 = or(_T_1148, _T_1143)
node _T_1150 = and(_T_1108, _T_1149)
node _T_1151 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1152 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1153 = and(_T_1151, _T_1152)
node _T_1154 = or(UInt<1>(0h0), _T_1153)
node _T_1155 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1156 = cvt(_T_1155)
node _T_1157 = and(_T_1156, asSInt(UInt<17>(0h10000)))
node _T_1158 = asSInt(_T_1157)
node _T_1159 = eq(_T_1158, asSInt(UInt<1>(0h0)))
node _T_1160 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1161 = cvt(_T_1160)
node _T_1162 = and(_T_1161, asSInt(UInt<29>(0h10000000)))
node _T_1163 = asSInt(_T_1162)
node _T_1164 = eq(_T_1163, asSInt(UInt<1>(0h0)))
node _T_1165 = or(_T_1159, _T_1164)
node _T_1166 = and(_T_1154, _T_1165)
node _T_1167 = or(UInt<1>(0h0), _T_1107)
node _T_1168 = or(_T_1167, _T_1150)
node _T_1169 = or(_T_1168, _T_1166)
node _T_1170 = and(_T_1097, _T_1169)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_46
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(source_ok, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(is_aligned, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1180 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_49
node _T_1184 = eq(io.in.a.bits.mask, mask)
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_50
node _T_1188 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1189 = asUInt(reset)
node _T_1190 = eq(_T_1189, UInt<1>(0h0))
when _T_1190 :
node _T_1191 = eq(_T_1188, UInt<1>(0h0))
when _T_1191 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1188, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1192 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1193 = asUInt(reset)
node _T_1194 = eq(_T_1193, UInt<1>(0h0))
when _T_1194 :
node _T_1195 = eq(_T_1192, UInt<1>(0h0))
when _T_1195 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1192, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_26 = shr(io.in.d.bits.source, 2)
node _source_ok_T_27 = eq(_source_ok_T_26, UInt<1>(0h0))
node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28)
node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_32 = shr(io.in.d.bits.source, 2)
node _source_ok_T_33 = eq(_source_ok_T_32, UInt<1>(0h1))
node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34)
node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_38 = shr(io.in.d.bits.source, 2)
node _source_ok_T_39 = eq(_source_ok_T_38, UInt<2>(0h2))
node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40)
node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_44 = shr(io.in.d.bits.source, 2)
node _source_ok_T_45 = eq(_source_ok_T_44, UInt<2>(0h3))
node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46)
node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48)
wire _source_ok_WIRE_1 : UInt<1>[4]
connect _source_ok_WIRE_1[0], _source_ok_T_31
connect _source_ok_WIRE_1[1], _source_ok_T_37
connect _source_ok_WIRE_1[2], _source_ok_T_43
connect _source_ok_WIRE_1[3], _source_ok_T_49
node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2])
node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3])
node sink_ok = lt(io.in.d.bits.sink, UInt<6>(0h20))
node _T_1196 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1196 :
node _T_1197 = asUInt(reset)
node _T_1198 = eq(_T_1197, UInt<1>(0h0))
when _T_1198 :
node _T_1199 = eq(source_ok_1, UInt<1>(0h0))
when _T_1199 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1200 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1201 = asUInt(reset)
node _T_1202 = eq(_T_1201, UInt<1>(0h0))
when _T_1202 :
node _T_1203 = eq(_T_1200, UInt<1>(0h0))
when _T_1203 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1200, UInt<1>(0h1), "") : assert_54
node _T_1204 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1205 = asUInt(reset)
node _T_1206 = eq(_T_1205, UInt<1>(0h0))
when _T_1206 :
node _T_1207 = eq(_T_1204, UInt<1>(0h0))
when _T_1207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1204, UInt<1>(0h1), "") : assert_55
node _T_1208 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(_T_1208, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1208, UInt<1>(0h1), "") : assert_56
node _T_1212 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1213 = asUInt(reset)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
when _T_1214 :
node _T_1215 = eq(_T_1212, UInt<1>(0h0))
when _T_1215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1212, UInt<1>(0h1), "") : assert_57
node _T_1216 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1216 :
node _T_1217 = asUInt(reset)
node _T_1218 = eq(_T_1217, UInt<1>(0h0))
when _T_1218 :
node _T_1219 = eq(source_ok_1, UInt<1>(0h0))
when _T_1219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1220 = asUInt(reset)
node _T_1221 = eq(_T_1220, UInt<1>(0h0))
when _T_1221 :
node _T_1222 = eq(sink_ok, UInt<1>(0h0))
when _T_1222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1223 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1224 = asUInt(reset)
node _T_1225 = eq(_T_1224, UInt<1>(0h0))
when _T_1225 :
node _T_1226 = eq(_T_1223, UInt<1>(0h0))
when _T_1226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1223, UInt<1>(0h1), "") : assert_60
node _T_1227 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_61
node _T_1231 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1232 = asUInt(reset)
node _T_1233 = eq(_T_1232, UInt<1>(0h0))
when _T_1233 :
node _T_1234 = eq(_T_1231, UInt<1>(0h0))
when _T_1234 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1231, UInt<1>(0h1), "") : assert_62
node _T_1235 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1236 = asUInt(reset)
node _T_1237 = eq(_T_1236, UInt<1>(0h0))
when _T_1237 :
node _T_1238 = eq(_T_1235, UInt<1>(0h0))
when _T_1238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1235, UInt<1>(0h1), "") : assert_63
node _T_1239 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1240 = or(UInt<1>(0h1), _T_1239)
node _T_1241 = asUInt(reset)
node _T_1242 = eq(_T_1241, UInt<1>(0h0))
when _T_1242 :
node _T_1243 = eq(_T_1240, UInt<1>(0h0))
when _T_1243 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1240, UInt<1>(0h1), "") : assert_64
node _T_1244 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1244 :
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(source_ok_1, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1248 = asUInt(reset)
node _T_1249 = eq(_T_1248, UInt<1>(0h0))
when _T_1249 :
node _T_1250 = eq(sink_ok, UInt<1>(0h0))
when _T_1250 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1251 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1252 = asUInt(reset)
node _T_1253 = eq(_T_1252, UInt<1>(0h0))
when _T_1253 :
node _T_1254 = eq(_T_1251, UInt<1>(0h0))
when _T_1254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1251, UInt<1>(0h1), "") : assert_67
node _T_1255 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1256 = asUInt(reset)
node _T_1257 = eq(_T_1256, UInt<1>(0h0))
when _T_1257 :
node _T_1258 = eq(_T_1255, UInt<1>(0h0))
when _T_1258 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1255, UInt<1>(0h1), "") : assert_68
node _T_1259 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1260 = asUInt(reset)
node _T_1261 = eq(_T_1260, UInt<1>(0h0))
when _T_1261 :
node _T_1262 = eq(_T_1259, UInt<1>(0h0))
when _T_1262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1259, UInt<1>(0h1), "") : assert_69
node _T_1263 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1264 = or(_T_1263, io.in.d.bits.corrupt)
node _T_1265 = asUInt(reset)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
when _T_1266 :
node _T_1267 = eq(_T_1264, UInt<1>(0h0))
when _T_1267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1264, UInt<1>(0h1), "") : assert_70
node _T_1268 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1269 = or(UInt<1>(0h1), _T_1268)
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(_T_1269, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1269, UInt<1>(0h1), "") : assert_71
node _T_1273 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1273 :
node _T_1274 = asUInt(reset)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(source_ok_1, UInt<1>(0h0))
when _T_1276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1277 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1278 = asUInt(reset)
node _T_1279 = eq(_T_1278, UInt<1>(0h0))
when _T_1279 :
node _T_1280 = eq(_T_1277, UInt<1>(0h0))
when _T_1280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1277, UInt<1>(0h1), "") : assert_73
node _T_1281 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1282 = asUInt(reset)
node _T_1283 = eq(_T_1282, UInt<1>(0h0))
when _T_1283 :
node _T_1284 = eq(_T_1281, UInt<1>(0h0))
when _T_1284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1281, UInt<1>(0h1), "") : assert_74
node _T_1285 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1286 = or(UInt<1>(0h1), _T_1285)
node _T_1287 = asUInt(reset)
node _T_1288 = eq(_T_1287, UInt<1>(0h0))
when _T_1288 :
node _T_1289 = eq(_T_1286, UInt<1>(0h0))
when _T_1289 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1286, UInt<1>(0h1), "") : assert_75
node _T_1290 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1290 :
node _T_1291 = asUInt(reset)
node _T_1292 = eq(_T_1291, UInt<1>(0h0))
when _T_1292 :
node _T_1293 = eq(source_ok_1, UInt<1>(0h0))
when _T_1293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1294 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1295 = asUInt(reset)
node _T_1296 = eq(_T_1295, UInt<1>(0h0))
when _T_1296 :
node _T_1297 = eq(_T_1294, UInt<1>(0h0))
when _T_1297 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1294, UInt<1>(0h1), "") : assert_77
node _T_1298 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1299 = or(_T_1298, io.in.d.bits.corrupt)
node _T_1300 = asUInt(reset)
node _T_1301 = eq(_T_1300, UInt<1>(0h0))
when _T_1301 :
node _T_1302 = eq(_T_1299, UInt<1>(0h0))
when _T_1302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1299, UInt<1>(0h1), "") : assert_78
node _T_1303 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1304 = or(UInt<1>(0h1), _T_1303)
node _T_1305 = asUInt(reset)
node _T_1306 = eq(_T_1305, UInt<1>(0h0))
when _T_1306 :
node _T_1307 = eq(_T_1304, UInt<1>(0h0))
when _T_1307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1304, UInt<1>(0h1), "") : assert_79
node _T_1308 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1308 :
node _T_1309 = asUInt(reset)
node _T_1310 = eq(_T_1309, UInt<1>(0h0))
when _T_1310 :
node _T_1311 = eq(source_ok_1, UInt<1>(0h0))
when _T_1311 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1312 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1313 = asUInt(reset)
node _T_1314 = eq(_T_1313, UInt<1>(0h0))
when _T_1314 :
node _T_1315 = eq(_T_1312, UInt<1>(0h0))
when _T_1315 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1312, UInt<1>(0h1), "") : assert_81
node _T_1316 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1317 = asUInt(reset)
node _T_1318 = eq(_T_1317, UInt<1>(0h0))
when _T_1318 :
node _T_1319 = eq(_T_1316, UInt<1>(0h0))
when _T_1319 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1316, UInt<1>(0h1), "") : assert_82
node _T_1320 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1321 = or(UInt<1>(0h1), _T_1320)
node _T_1322 = asUInt(reset)
node _T_1323 = eq(_T_1322, UInt<1>(0h0))
when _T_1323 :
node _T_1324 = eq(_T_1321, UInt<1>(0h0))
when _T_1324 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1321, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1325 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1326 = asUInt(reset)
node _T_1327 = eq(_T_1326, UInt<1>(0h0))
when _T_1327 :
node _T_1328 = eq(_T_1325, UInt<1>(0h0))
when _T_1328 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1325, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1329 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1330 = asUInt(reset)
node _T_1331 = eq(_T_1330, UInt<1>(0h0))
when _T_1331 :
node _T_1332 = eq(_T_1329, UInt<1>(0h0))
when _T_1332 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1329, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}
connect _WIRE_4.bits.sink, UInt<5>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1333 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1334 = asUInt(reset)
node _T_1335 = eq(_T_1334, UInt<1>(0h0))
when _T_1335 :
node _T_1336 = eq(_T_1333, UInt<1>(0h0))
when _T_1336 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1333, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1337 = eq(a_first, UInt<1>(0h0))
node _T_1338 = and(io.in.a.valid, _T_1337)
when _T_1338 :
node _T_1339 = eq(io.in.a.bits.opcode, opcode)
node _T_1340 = asUInt(reset)
node _T_1341 = eq(_T_1340, UInt<1>(0h0))
when _T_1341 :
node _T_1342 = eq(_T_1339, UInt<1>(0h0))
when _T_1342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1339, UInt<1>(0h1), "") : assert_87
node _T_1343 = eq(io.in.a.bits.param, param)
node _T_1344 = asUInt(reset)
node _T_1345 = eq(_T_1344, UInt<1>(0h0))
when _T_1345 :
node _T_1346 = eq(_T_1343, UInt<1>(0h0))
when _T_1346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1343, UInt<1>(0h1), "") : assert_88
node _T_1347 = eq(io.in.a.bits.size, size)
node _T_1348 = asUInt(reset)
node _T_1349 = eq(_T_1348, UInt<1>(0h0))
when _T_1349 :
node _T_1350 = eq(_T_1347, UInt<1>(0h0))
when _T_1350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1347, UInt<1>(0h1), "") : assert_89
node _T_1351 = eq(io.in.a.bits.source, source)
node _T_1352 = asUInt(reset)
node _T_1353 = eq(_T_1352, UInt<1>(0h0))
when _T_1353 :
node _T_1354 = eq(_T_1351, UInt<1>(0h0))
when _T_1354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1351, UInt<1>(0h1), "") : assert_90
node _T_1355 = eq(io.in.a.bits.address, address)
node _T_1356 = asUInt(reset)
node _T_1357 = eq(_T_1356, UInt<1>(0h0))
when _T_1357 :
node _T_1358 = eq(_T_1355, UInt<1>(0h0))
when _T_1358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1355, UInt<1>(0h1), "") : assert_91
node _T_1359 = and(io.in.a.ready, io.in.a.valid)
node _T_1360 = and(_T_1359, a_first)
when _T_1360 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1361 = eq(d_first, UInt<1>(0h0))
node _T_1362 = and(io.in.d.valid, _T_1361)
when _T_1362 :
node _T_1363 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1364 = asUInt(reset)
node _T_1365 = eq(_T_1364, UInt<1>(0h0))
when _T_1365 :
node _T_1366 = eq(_T_1363, UInt<1>(0h0))
when _T_1366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1363, UInt<1>(0h1), "") : assert_92
node _T_1367 = eq(io.in.d.bits.param, param_1)
node _T_1368 = asUInt(reset)
node _T_1369 = eq(_T_1368, UInt<1>(0h0))
when _T_1369 :
node _T_1370 = eq(_T_1367, UInt<1>(0h0))
when _T_1370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1367, UInt<1>(0h1), "") : assert_93
node _T_1371 = eq(io.in.d.bits.size, size_1)
node _T_1372 = asUInt(reset)
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(_T_1371, UInt<1>(0h0))
when _T_1374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1371, UInt<1>(0h1), "") : assert_94
node _T_1375 = eq(io.in.d.bits.source, source_1)
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_95
node _T_1379 = eq(io.in.d.bits.sink, sink)
node _T_1380 = asUInt(reset)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
when _T_1381 :
node _T_1382 = eq(_T_1379, UInt<1>(0h0))
when _T_1382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1379, UInt<1>(0h1), "") : assert_96
node _T_1383 = eq(io.in.d.bits.denied, denied)
node _T_1384 = asUInt(reset)
node _T_1385 = eq(_T_1384, UInt<1>(0h0))
when _T_1385 :
node _T_1386 = eq(_T_1383, UInt<1>(0h0))
when _T_1386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1383, UInt<1>(0h1), "") : assert_97
node _T_1387 = and(io.in.d.ready, io.in.d.valid)
node _T_1388 = and(_T_1387, d_first)
when _T_1388 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<16>
connect a_set, UInt<16>(0h0)
wire a_set_wo_ready : UInt<16>
connect a_set_wo_ready, UInt<16>(0h0)
wire a_opcodes_set : UInt<64>
connect a_opcodes_set, UInt<64>(0h0)
wire a_sizes_set : UInt<128>
connect a_sizes_set, UInt<128>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1389 = and(io.in.a.valid, a_first_1)
node _T_1390 = and(_T_1389, UInt<1>(0h1))
when _T_1390 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1391 = and(io.in.a.ready, io.in.a.valid)
node _T_1392 = and(_T_1391, a_first_1)
node _T_1393 = and(_T_1392, UInt<1>(0h1))
when _T_1393 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1394 = dshr(inflight, io.in.a.bits.source)
node _T_1395 = bits(_T_1394, 0, 0)
node _T_1396 = eq(_T_1395, UInt<1>(0h0))
node _T_1397 = asUInt(reset)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
when _T_1398 :
node _T_1399 = eq(_T_1396, UInt<1>(0h0))
when _T_1399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1396, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<16>
connect d_clr, UInt<16>(0h0)
wire d_clr_wo_ready : UInt<16>
connect d_clr_wo_ready, UInt<16>(0h0)
wire d_opcodes_clr : UInt<64>
connect d_opcodes_clr, UInt<64>(0h0)
wire d_sizes_clr : UInt<128>
connect d_sizes_clr, UInt<128>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1400 = and(io.in.d.valid, d_first_1)
node _T_1401 = and(_T_1400, UInt<1>(0h1))
node _T_1402 = eq(d_release_ack, UInt<1>(0h0))
node _T_1403 = and(_T_1401, _T_1402)
when _T_1403 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1404 = and(io.in.d.ready, io.in.d.valid)
node _T_1405 = and(_T_1404, d_first_1)
node _T_1406 = and(_T_1405, UInt<1>(0h1))
node _T_1407 = eq(d_release_ack, UInt<1>(0h0))
node _T_1408 = and(_T_1406, _T_1407)
when _T_1408 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1409 = and(io.in.d.valid, d_first_1)
node _T_1410 = and(_T_1409, UInt<1>(0h1))
node _T_1411 = eq(d_release_ack, UInt<1>(0h0))
node _T_1412 = and(_T_1410, _T_1411)
when _T_1412 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1413 = dshr(inflight, io.in.d.bits.source)
node _T_1414 = bits(_T_1413, 0, 0)
node _T_1415 = or(_T_1414, same_cycle_resp)
node _T_1416 = asUInt(reset)
node _T_1417 = eq(_T_1416, UInt<1>(0h0))
when _T_1417 :
node _T_1418 = eq(_T_1415, UInt<1>(0h0))
when _T_1418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1415, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1419 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1420 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1421 = or(_T_1419, _T_1420)
node _T_1422 = asUInt(reset)
node _T_1423 = eq(_T_1422, UInt<1>(0h0))
when _T_1423 :
node _T_1424 = eq(_T_1421, UInt<1>(0h0))
when _T_1424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1421, UInt<1>(0h1), "") : assert_100
node _T_1425 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1426 = asUInt(reset)
node _T_1427 = eq(_T_1426, UInt<1>(0h0))
when _T_1427 :
node _T_1428 = eq(_T_1425, UInt<1>(0h0))
when _T_1428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1425, UInt<1>(0h1), "") : assert_101
else :
node _T_1429 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1430 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1431 = or(_T_1429, _T_1430)
node _T_1432 = asUInt(reset)
node _T_1433 = eq(_T_1432, UInt<1>(0h0))
when _T_1433 :
node _T_1434 = eq(_T_1431, UInt<1>(0h0))
when _T_1434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1431, UInt<1>(0h1), "") : assert_102
node _T_1435 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1436 = asUInt(reset)
node _T_1437 = eq(_T_1436, UInt<1>(0h0))
when _T_1437 :
node _T_1438 = eq(_T_1435, UInt<1>(0h0))
when _T_1438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1435, UInt<1>(0h1), "") : assert_103
node _T_1439 = and(io.in.d.valid, d_first_1)
node _T_1440 = and(_T_1439, a_first_1)
node _T_1441 = and(_T_1440, io.in.a.valid)
node _T_1442 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1443 = and(_T_1441, _T_1442)
node _T_1444 = eq(d_release_ack, UInt<1>(0h0))
node _T_1445 = and(_T_1443, _T_1444)
when _T_1445 :
node _T_1446 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1447 = or(_T_1446, io.in.a.ready)
node _T_1448 = asUInt(reset)
node _T_1449 = eq(_T_1448, UInt<1>(0h0))
when _T_1449 :
node _T_1450 = eq(_T_1447, UInt<1>(0h0))
when _T_1450 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1447, UInt<1>(0h1), "") : assert_104
node _T_1451 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1452 = orr(a_set_wo_ready)
node _T_1453 = eq(_T_1452, UInt<1>(0h0))
node _T_1454 = or(_T_1451, _T_1453)
node _T_1455 = asUInt(reset)
node _T_1456 = eq(_T_1455, UInt<1>(0h0))
when _T_1456 :
node _T_1457 = eq(_T_1454, UInt<1>(0h0))
when _T_1457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1454, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_41
node _T_1458 = orr(inflight)
node _T_1459 = eq(_T_1458, UInt<1>(0h0))
node _T_1460 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1461 = or(_T_1459, _T_1460)
node _T_1462 = lt(watchdog, plusarg_reader.out)
node _T_1463 = or(_T_1461, _T_1462)
node _T_1464 = asUInt(reset)
node _T_1465 = eq(_T_1464, UInt<1>(0h0))
when _T_1465 :
node _T_1466 = eq(_T_1463, UInt<1>(0h0))
when _T_1466 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1463, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1467 = and(io.in.a.ready, io.in.a.valid)
node _T_1468 = and(io.in.d.ready, io.in.d.valid)
node _T_1469 = or(_T_1467, _T_1468)
when _T_1469 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<16>
connect c_set, UInt<16>(0h0)
wire c_set_wo_ready : UInt<16>
connect c_set_wo_ready, UInt<16>(0h0)
wire c_opcodes_set : UInt<64>
connect c_opcodes_set, UInt<64>(0h0)
wire c_sizes_set : UInt<128>
connect c_sizes_set, UInt<128>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1470 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1471 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1472 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1473 = and(_T_1471, _T_1472)
node _T_1474 = and(_T_1470, _T_1473)
when _T_1474 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1475 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1476 = and(_T_1475, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1477 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1478 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1479 = and(_T_1477, _T_1478)
node _T_1480 = and(_T_1476, _T_1479)
when _T_1480 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1481 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1482 = bits(_T_1481, 0, 0)
node _T_1483 = eq(_T_1482, UInt<1>(0h0))
node _T_1484 = asUInt(reset)
node _T_1485 = eq(_T_1484, UInt<1>(0h0))
when _T_1485 :
node _T_1486 = eq(_T_1483, UInt<1>(0h0))
when _T_1486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1483, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<16>
connect d_clr_1, UInt<16>(0h0)
wire d_clr_wo_ready_1 : UInt<16>
connect d_clr_wo_ready_1, UInt<16>(0h0)
wire d_opcodes_clr_1 : UInt<64>
connect d_opcodes_clr_1, UInt<64>(0h0)
wire d_sizes_clr_1 : UInt<128>
connect d_sizes_clr_1, UInt<128>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1487 = and(io.in.d.valid, d_first_2)
node _T_1488 = and(_T_1487, UInt<1>(0h1))
node _T_1489 = and(_T_1488, d_release_ack_1)
when _T_1489 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1490 = and(io.in.d.ready, io.in.d.valid)
node _T_1491 = and(_T_1490, d_first_2)
node _T_1492 = and(_T_1491, UInt<1>(0h1))
node _T_1493 = and(_T_1492, d_release_ack_1)
when _T_1493 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1494 = and(io.in.d.valid, d_first_2)
node _T_1495 = and(_T_1494, UInt<1>(0h1))
node _T_1496 = and(_T_1495, d_release_ack_1)
when _T_1496 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1497 = dshr(inflight_1, io.in.d.bits.source)
node _T_1498 = bits(_T_1497, 0, 0)
node _T_1499 = or(_T_1498, same_cycle_resp_1)
node _T_1500 = asUInt(reset)
node _T_1501 = eq(_T_1500, UInt<1>(0h0))
when _T_1501 :
node _T_1502 = eq(_T_1499, UInt<1>(0h0))
when _T_1502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1499, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1503 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1504 = asUInt(reset)
node _T_1505 = eq(_T_1504, UInt<1>(0h0))
when _T_1505 :
node _T_1506 = eq(_T_1503, UInt<1>(0h0))
when _T_1506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1503, UInt<1>(0h1), "") : assert_109
else :
node _T_1507 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1508 = asUInt(reset)
node _T_1509 = eq(_T_1508, UInt<1>(0h0))
when _T_1509 :
node _T_1510 = eq(_T_1507, UInt<1>(0h0))
when _T_1510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1507, UInt<1>(0h1), "") : assert_110
node _T_1511 = and(io.in.d.valid, d_first_2)
node _T_1512 = and(_T_1511, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1513 = and(_T_1512, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1514 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1515 = and(_T_1513, _T_1514)
node _T_1516 = and(_T_1515, d_release_ack_1)
node _T_1517 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1518 = and(_T_1516, _T_1517)
when _T_1518 :
node _T_1519 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1520 = or(_T_1519, _WIRE_23.ready)
node _T_1521 = asUInt(reset)
node _T_1522 = eq(_T_1521, UInt<1>(0h0))
when _T_1522 :
node _T_1523 = eq(_T_1520, UInt<1>(0h0))
when _T_1523 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1520, UInt<1>(0h1), "") : assert_111
node _T_1524 = orr(c_set_wo_ready)
when _T_1524 :
node _T_1525 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1526 = asUInt(reset)
node _T_1527 = eq(_T_1526, UInt<1>(0h0))
when _T_1527 :
node _T_1528 = eq(_T_1525, UInt<1>(0h0))
when _T_1528 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1525, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_42
node _T_1529 = orr(inflight_1)
node _T_1530 = eq(_T_1529, UInt<1>(0h0))
node _T_1531 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1532 = or(_T_1530, _T_1531)
node _T_1533 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1534 = or(_T_1532, _T_1533)
node _T_1535 = asUInt(reset)
node _T_1536 = eq(_T_1535, UInt<1>(0h0))
when _T_1536 :
node _T_1537 = eq(_T_1534, UInt<1>(0h0))
when _T_1537 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1534, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1538 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1539 = and(io.in.d.ready, io.in.d.valid)
node _T_1540 = or(_T_1538, _T_1539)
when _T_1540 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_16( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg [4:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [15:0] inflight; // @[Monitor.scala:614:27]
reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [127:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [15:0] _GEN_0 = {12'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [15:0] _GEN_3 = {12'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [15:0] inflight_1; // @[Monitor.scala:726:35]
reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_101 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 5, 0)
node _source_ok_T = shr(io.in.a.bits.source, 6)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<6>(0h39))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits = bits(_uncommonBits_T, 5, 0)
node _T_4 = shr(io.in.a.bits.source, 6)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<6>(0h39))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 5, 0)
node _T_24 = shr(io.in.a.bits.source, 6)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<6>(0h39))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 5, 0)
node _T_86 = shr(io.in.a.bits.source, 6)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<6>(0h39))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 5, 0)
node _T_152 = shr(io.in.a.bits.source, 6)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<6>(0h39))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 5, 0)
node _T_199 = shr(io.in.a.bits.source, 6)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<6>(0h39))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 5, 0)
node _T_240 = shr(io.in.a.bits.source, 6)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<6>(0h39))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 5, 0)
node _T_283 = shr(io.in.a.bits.source, 6)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<6>(0h39))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 5, 0)
node _T_321 = shr(io.in.a.bits.source, 6)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<6>(0h39))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<6>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 5, 0)
node _T_359 = shr(io.in.a.bits.source, 6)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<6>(0h39))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<6>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 5, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 6)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<6>(0h39))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<6>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<6>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<58>, clock, reset, UInt<58>(0h0)
regreset inflight_opcodes : UInt<232>, clock, reset, UInt<232>(0h0)
regreset inflight_sizes : UInt<232>, clock, reset, UInt<232>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<58>
connect a_set, UInt<58>(0h0)
wire a_set_wo_ready : UInt<58>
connect a_set_wo_ready, UInt<58>(0h0)
wire a_opcodes_set : UInt<232>
connect a_opcodes_set, UInt<232>(0h0)
wire a_sizes_set : UInt<232>
connect a_sizes_set, UInt<232>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<58>
connect d_clr, UInt<58>(0h0)
wire d_clr_wo_ready : UInt<58>
connect d_clr_wo_ready, UInt<58>(0h0)
wire d_opcodes_clr : UInt<232>
connect d_opcodes_clr, UInt<232>(0h0)
wire d_sizes_clr : UInt<232>
connect d_sizes_clr, UInt<232>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_273
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<58>, clock, reset, UInt<58>(0h0)
regreset inflight_opcodes_1 : UInt<232>, clock, reset, UInt<232>(0h0)
regreset inflight_sizes_1 : UInt<232>, clock, reset, UInt<232>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<6>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<6>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<58>
connect c_set, UInt<58>(0h0)
wire c_set_wo_ready : UInt<58>
connect c_set_wo_ready, UInt<58>(0h0)
wire c_opcodes_set : UInt<232>
connect c_opcodes_set, UInt<232>(0h0)
wire c_sizes_set : UInt<232>
connect c_sizes_set, UInt<232>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<6>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<6>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<6>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<6>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<6>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<6>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<6>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<6>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<6>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<6>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<6>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<58>
connect d_clr_1, UInt<58>(0h0)
wire d_clr_wo_ready_1 : UInt<58>
connect d_clr_wo_ready_1, UInt<58>(0h0)
wire d_opcodes_clr_1 : UInt<232>
connect d_opcodes_clr_1, UInt<232>(0h0)
wire d_sizes_clr_1 : UInt<232>
connect d_sizes_clr_1, UInt<232>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<6>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<6>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<6>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<6>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<6>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_274
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/soc/Scratchpad.scala:39:99)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<6>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_101( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg [57:0] inflight; // @[Monitor.scala:614:27]
reg [231:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [231:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [63:0] _GEN_0 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [63:0] _GEN_3 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [57:0] inflight_1; // @[Monitor.scala:726:35]
reg [231:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLSerdesser_serial_tl_0 :
input clock : Clock
input reset : Reset
output auto : { client_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output io : { ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}[5], debug : { ser_busy : UInt<1>, des_busy : UInt<1>}}
wire clientNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate clientNodeOut.d.bits.corrupt
invalidate clientNodeOut.d.bits.data
invalidate clientNodeOut.d.bits.denied
invalidate clientNodeOut.d.bits.sink
invalidate clientNodeOut.d.bits.source
invalidate clientNodeOut.d.bits.size
invalidate clientNodeOut.d.bits.param
invalidate clientNodeOut.d.bits.opcode
invalidate clientNodeOut.d.valid
invalidate clientNodeOut.d.ready
invalidate clientNodeOut.a.bits.corrupt
invalidate clientNodeOut.a.bits.data
invalidate clientNodeOut.a.bits.mask
invalidate clientNodeOut.a.bits.address
invalidate clientNodeOut.a.bits.source
invalidate clientNodeOut.a.bits.size
invalidate clientNodeOut.a.bits.param
invalidate clientNodeOut.a.bits.opcode
invalidate clientNodeOut.a.valid
invalidate clientNodeOut.a.ready
connect auto.client_out, clientNodeOut
wire manager_tl : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, address : UInt<64>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<8>}}}
connect manager_tl.e.bits.sink, UInt<8>(0h0)
connect manager_tl.e.valid, UInt<1>(0h0)
connect manager_tl.e.ready, UInt<1>(0h0)
connect manager_tl.d.bits.corrupt, UInt<1>(0h0)
connect manager_tl.d.bits.data, UInt<64>(0h0)
connect manager_tl.d.bits.denied, UInt<1>(0h0)
connect manager_tl.d.bits.sink, UInt<8>(0h0)
connect manager_tl.d.bits.source, UInt<8>(0h0)
connect manager_tl.d.bits.size, UInt<8>(0h0)
connect manager_tl.d.bits.param, UInt<2>(0h0)
connect manager_tl.d.bits.opcode, UInt<3>(0h0)
connect manager_tl.d.valid, UInt<1>(0h0)
connect manager_tl.d.ready, UInt<1>(0h0)
connect manager_tl.c.bits.corrupt, UInt<1>(0h0)
connect manager_tl.c.bits.data, UInt<64>(0h0)
connect manager_tl.c.bits.address, UInt<64>(0h0)
connect manager_tl.c.bits.source, UInt<8>(0h0)
connect manager_tl.c.bits.size, UInt<8>(0h0)
connect manager_tl.c.bits.param, UInt<3>(0h0)
connect manager_tl.c.bits.opcode, UInt<3>(0h0)
connect manager_tl.c.valid, UInt<1>(0h0)
connect manager_tl.c.ready, UInt<1>(0h0)
connect manager_tl.b.bits.corrupt, UInt<1>(0h0)
connect manager_tl.b.bits.data, UInt<64>(0h0)
connect manager_tl.b.bits.mask, UInt<8>(0h0)
connect manager_tl.b.bits.address, UInt<64>(0h0)
connect manager_tl.b.bits.source, UInt<8>(0h0)
connect manager_tl.b.bits.size, UInt<8>(0h0)
connect manager_tl.b.bits.param, UInt<2>(0h0)
connect manager_tl.b.bits.opcode, UInt<3>(0h0)
connect manager_tl.b.valid, UInt<1>(0h0)
connect manager_tl.b.ready, UInt<1>(0h0)
connect manager_tl.a.bits.corrupt, UInt<1>(0h0)
connect manager_tl.a.bits.data, UInt<64>(0h0)
connect manager_tl.a.bits.mask, UInt<8>(0h0)
connect manager_tl.a.bits.address, UInt<64>(0h0)
connect manager_tl.a.bits.source, UInt<8>(0h0)
connect manager_tl.a.bits.size, UInt<8>(0h0)
connect manager_tl.a.bits.param, UInt<3>(0h0)
connect manager_tl.a.bits.opcode, UInt<3>(0h0)
connect manager_tl.a.valid, UInt<1>(0h0)
connect manager_tl.a.ready, UInt<1>(0h0)
inst out_channels_1_2 of TLDToBeat_serial_tl_0_a64d64s8k8z8c
connect out_channels_1_2.clock, clock
connect out_channels_1_2.reset, reset
wire _out_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _out_channels_WIRE.bits.corrupt, UInt<1>(0h0)
connect _out_channels_WIRE.bits.data, UInt<64>(0h0)
connect _out_channels_WIRE.bits.mask, UInt<8>(0h0)
connect _out_channels_WIRE.bits.address, UInt<32>(0h0)
connect _out_channels_WIRE.bits.source, UInt<4>(0h0)
connect _out_channels_WIRE.bits.size, UInt<4>(0h0)
connect _out_channels_WIRE.bits.param, UInt<2>(0h0)
connect _out_channels_WIRE.bits.opcode, UInt<3>(0h0)
connect _out_channels_WIRE.valid, UInt<1>(0h0)
connect _out_channels_WIRE.ready, UInt<1>(0h0)
wire out_channels_3_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect out_channels_3_1.bits, _out_channels_WIRE.bits
connect out_channels_3_1.valid, _out_channels_WIRE.valid
connect out_channels_3_1.ready, _out_channels_WIRE.ready
inst out_channels_3_2 of TLBToBeat_serial_tl_0_a64d64s8k8z8c
connect out_channels_3_2.clock, clock
connect out_channels_3_2.reset, reset
connect io.ser[0].out.valid, UInt<1>(0h0)
connect io.ser[1].out.valid, UInt<1>(0h0)
connect io.ser[2].out.valid, UInt<1>(0h0)
connect io.ser[3].out.valid, UInt<1>(0h0)
connect io.ser[4].out.valid, UInt<1>(0h0)
invalidate io.ser[0].out.bits.flit
invalidate io.ser[1].out.bits.flit
invalidate io.ser[2].out.bits.flit
invalidate io.ser[3].out.bits.flit
invalidate io.ser[4].out.bits.flit
connect out_channels_1_2.io.protocol, clientNodeOut.d
inst ser_1 of GenericSerializer_TLBeatw67_f32
connect ser_1.clock, clock
connect ser_1.reset, reset
connect ser_1.io.in, out_channels_1_2.io.beat
connect io.ser[1].out.bits, ser_1.io.out.bits
connect io.ser[1].out.valid, ser_1.io.out.valid
connect ser_1.io.out.ready, io.ser[1].out.ready
connect out_channels_3_2.io.protocol, out_channels_3_1
inst ser_3 of GenericSerializer_TLBeatw87_f32
connect ser_3.clock, clock
connect ser_3.reset, reset
connect ser_3.io.in, out_channels_3_2.io.beat
connect io.ser[3].out.bits, ser_3.io.out.bits
connect io.ser[3].out.valid, ser_3.io.out.valid
connect ser_3.io.out.ready, io.ser[3].out.ready
node _io_debug_ser_busy_T = or(ser_1.io.busy, ser_3.io.busy)
connect io.debug.ser_busy, _io_debug_ser_busy_T
wire _in_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}
connect _in_channels_WIRE.bits.sink, UInt<6>(0h0)
connect _in_channels_WIRE.valid, UInt<1>(0h0)
connect _in_channels_WIRE.ready, UInt<1>(0h0)
wire in_channels_0_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}}
connect in_channels_0_1.bits, _in_channels_WIRE.bits
connect in_channels_0_1.valid, _in_channels_WIRE.valid
connect in_channels_0_1.ready, _in_channels_WIRE.ready
inst in_channels_0_2 of TLEFromBeat_serial_tl_0_a64d64s8k8z8c
connect in_channels_0_2.clock, clock
connect in_channels_0_2.reset, reset
inst in_channels_1_2 of TLDFromBeat_serial_tl_0_a64d64s8k8z8c
connect in_channels_1_2.clock, clock
connect in_channels_1_2.reset, reset
wire _in_channels_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _in_channels_WIRE_1.bits.corrupt, UInt<1>(0h0)
connect _in_channels_WIRE_1.bits.data, UInt<64>(0h0)
connect _in_channels_WIRE_1.bits.address, UInt<32>(0h0)
connect _in_channels_WIRE_1.bits.source, UInt<4>(0h0)
connect _in_channels_WIRE_1.bits.size, UInt<4>(0h0)
connect _in_channels_WIRE_1.bits.param, UInt<3>(0h0)
connect _in_channels_WIRE_1.bits.opcode, UInt<3>(0h0)
connect _in_channels_WIRE_1.valid, UInt<1>(0h0)
connect _in_channels_WIRE_1.ready, UInt<1>(0h0)
wire in_channels_2_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect in_channels_2_1.bits, _in_channels_WIRE_1.bits
connect in_channels_2_1.valid, _in_channels_WIRE_1.valid
connect in_channels_2_1.ready, _in_channels_WIRE_1.ready
inst in_channels_2_2 of TLCFromBeat_serial_tl_0_a64d64s8k8z8c
connect in_channels_2_2.clock, clock
connect in_channels_2_2.reset, reset
inst in_channels_3_2 of TLBFromBeat_serial_tl_0_a64d64s8k8z8c
connect in_channels_3_2.clock, clock
connect in_channels_3_2.reset, reset
inst in_channels_4_2 of TLAFromBeat_serial_tl_0_a64d64s8k8z8c
connect in_channels_4_2.clock, clock
connect in_channels_4_2.reset, reset
connect in_channels_0_1.bits, in_channels_0_2.io.protocol.bits
connect in_channels_0_1.valid, in_channels_0_2.io.protocol.valid
connect in_channels_0_2.io.protocol.ready, in_channels_0_1.ready
inst des_0 of GenericDeserializer_TLBeatw10_f32
connect des_0.clock, clock
connect des_0.reset, reset
connect des_0.io.in, io.ser[0].in
connect in_channels_0_2.io.beat, des_0.io.out
connect manager_tl.d.bits.corrupt, in_channels_1_2.io.protocol.bits.corrupt
connect manager_tl.d.bits.data, in_channels_1_2.io.protocol.bits.data
connect manager_tl.d.bits.denied, in_channels_1_2.io.protocol.bits.denied
connect manager_tl.d.bits.sink, in_channels_1_2.io.protocol.bits.sink
connect manager_tl.d.bits.source, in_channels_1_2.io.protocol.bits.source
connect manager_tl.d.bits.size, in_channels_1_2.io.protocol.bits.size
connect manager_tl.d.bits.param, in_channels_1_2.io.protocol.bits.param
connect manager_tl.d.bits.opcode, in_channels_1_2.io.protocol.bits.opcode
connect manager_tl.d.valid, in_channels_1_2.io.protocol.valid
connect in_channels_1_2.io.protocol.ready, manager_tl.d.ready
inst des_1 of GenericDeserializer_TLBeatw67_f32
connect des_1.clock, clock
connect des_1.reset, reset
connect des_1.io.in, io.ser[1].in
connect in_channels_1_2.io.beat, des_1.io.out
connect in_channels_2_1.bits, in_channels_2_2.io.protocol.bits
connect in_channels_2_1.valid, in_channels_2_2.io.protocol.valid
connect in_channels_2_2.io.protocol.ready, in_channels_2_1.ready
inst des_2 of GenericDeserializer_TLBeatw88_f32
connect des_2.clock, clock
connect des_2.reset, reset
connect des_2.io.in, io.ser[2].in
connect in_channels_2_2.io.beat, des_2.io.out
connect manager_tl.b.bits.corrupt, in_channels_3_2.io.protocol.bits.corrupt
connect manager_tl.b.bits.data, in_channels_3_2.io.protocol.bits.data
connect manager_tl.b.bits.mask, in_channels_3_2.io.protocol.bits.mask
connect manager_tl.b.bits.address, in_channels_3_2.io.protocol.bits.address
connect manager_tl.b.bits.source, in_channels_3_2.io.protocol.bits.source
connect manager_tl.b.bits.size, in_channels_3_2.io.protocol.bits.size
connect manager_tl.b.bits.param, in_channels_3_2.io.protocol.bits.param
connect manager_tl.b.bits.opcode, in_channels_3_2.io.protocol.bits.opcode
connect manager_tl.b.valid, in_channels_3_2.io.protocol.valid
connect in_channels_3_2.io.protocol.ready, manager_tl.b.ready
inst des_3 of GenericDeserializer_TLBeatw87_f32
connect des_3.clock, clock
connect des_3.reset, reset
connect des_3.io.in, io.ser[3].in
connect in_channels_3_2.io.beat, des_3.io.out
connect clientNodeOut.a.bits, in_channels_4_2.io.protocol.bits
connect clientNodeOut.a.valid, in_channels_4_2.io.protocol.valid
connect in_channels_4_2.io.protocol.ready, clientNodeOut.a.ready
inst des_4 of GenericDeserializer_TLBeatw88_f32_1
connect des_4.clock, clock
connect des_4.reset, reset
connect des_4.io.in, io.ser[4].in
connect in_channels_4_2.io.beat, des_4.io.out
node _io_debug_des_busy_T = or(des_0.io.busy, des_1.io.busy)
node _io_debug_des_busy_T_1 = or(_io_debug_des_busy_T, des_2.io.busy)
node _io_debug_des_busy_T_2 = or(_io_debug_des_busy_T_1, des_3.io.busy)
node _io_debug_des_busy_T_3 = or(_io_debug_des_busy_T_2, des_4.io.busy)
connect io.debug.des_busy, _io_debug_des_busy_T_3 | module TLSerdesser_serial_tl_0( // @[TLSerdes.scala:39:9]
input clock, // @[TLSerdes.scala:39:9]
input reset, // @[TLSerdes.scala:39:9]
input auto_client_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_client_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_client_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_client_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_client_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_client_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_client_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_client_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_client_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_client_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_client_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_client_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_client_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_client_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_client_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_client_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_client_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_client_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_client_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_client_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_ser_0_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_0_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_1_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_1_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_1_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_1_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_1_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_2_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_2_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_3_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_3_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16]
input io_ser_3_out_ready, // @[TLSerdes.scala:40:16]
output io_ser_3_out_valid, // @[TLSerdes.scala:40:16]
output [31:0] io_ser_3_out_bits_flit, // @[TLSerdes.scala:40:16]
output io_ser_4_in_ready, // @[TLSerdes.scala:40:16]
input io_ser_4_in_valid, // @[TLSerdes.scala:40:16]
input [31:0] io_ser_4_in_bits_flit // @[TLSerdes.scala:40:16]
);
wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23]
wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23]
wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23]
wire [7:0] _in_channels_4_2_io_protocol_bits_size; // @[TLSerdes.scala:82:28]
wire [7:0] _in_channels_4_2_io_protocol_bits_source; // @[TLSerdes.scala:82:28]
wire [63:0] _in_channels_4_2_io_protocol_bits_address; // @[TLSerdes.scala:82:28]
wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28]
wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28]
wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28]
wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28]
wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28]
wire _ser_1_io_in_ready; // @[TLSerdes.scala:69:23]
wire _out_channels_3_2_io_beat_bits_head; // @[TLSerdes.scala:62:50]
wire _out_channels_3_2_io_beat_bits_tail; // @[TLSerdes.scala:62:50]
wire _out_channels_1_2_io_beat_valid; // @[TLSerdes.scala:60:50]
wire [64:0] _out_channels_1_2_io_beat_bits_payload; // @[TLSerdes.scala:60:50]
wire _out_channels_1_2_io_beat_bits_head; // @[TLSerdes.scala:60:50]
wire _out_channels_1_2_io_beat_bits_tail; // @[TLSerdes.scala:60:50]
TLDToBeat_serial_tl_0_a64d64s8k8z8c out_channels_1_2 ( // @[TLSerdes.scala:60:50]
.clock (clock),
.reset (reset),
.io_protocol_ready (auto_client_out_d_ready),
.io_protocol_valid (auto_client_out_d_valid),
.io_protocol_bits_opcode (auto_client_out_d_bits_opcode),
.io_protocol_bits_param (auto_client_out_d_bits_param),
.io_protocol_bits_size ({4'h0, auto_client_out_d_bits_size}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_source ({4'h0, auto_client_out_d_bits_source}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_sink ({2'h0, auto_client_out_d_bits_sink}), // @[TLSerdes.scala:68:21]
.io_protocol_bits_denied (auto_client_out_d_bits_denied),
.io_protocol_bits_data (auto_client_out_d_bits_data),
.io_protocol_bits_corrupt (auto_client_out_d_bits_corrupt),
.io_beat_ready (_ser_1_io_in_ready), // @[TLSerdes.scala:69:23]
.io_beat_valid (_out_channels_1_2_io_beat_valid),
.io_beat_bits_payload (_out_channels_1_2_io_beat_bits_payload),
.io_beat_bits_head (_out_channels_1_2_io_beat_bits_head),
.io_beat_bits_tail (_out_channels_1_2_io_beat_bits_tail)
); // @[TLSerdes.scala:60:50]
TLBToBeat_serial_tl_0_a64d64s8k8z8c out_channels_3_2 ( // @[TLSerdes.scala:62:50]
.clock (clock),
.reset (reset),
.io_beat_bits_head (_out_channels_3_2_io_beat_bits_head),
.io_beat_bits_tail (_out_channels_3_2_io_beat_bits_tail)
); // @[TLSerdes.scala:62:50]
GenericSerializer_TLBeatw67_f32 ser_1 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_ready (_ser_1_io_in_ready),
.io_in_valid (_out_channels_1_2_io_beat_valid), // @[TLSerdes.scala:60:50]
.io_in_bits_payload (_out_channels_1_2_io_beat_bits_payload), // @[TLSerdes.scala:60:50]
.io_in_bits_head (_out_channels_1_2_io_beat_bits_head), // @[TLSerdes.scala:60:50]
.io_in_bits_tail (_out_channels_1_2_io_beat_bits_tail), // @[TLSerdes.scala:60:50]
.io_out_ready (io_ser_1_out_ready),
.io_out_valid (io_ser_1_out_valid),
.io_out_bits_flit (io_ser_1_out_bits_flit)
); // @[TLSerdes.scala:69:23]
GenericSerializer_TLBeatw87_f32 ser_3 ( // @[TLSerdes.scala:69:23]
.clock (clock),
.reset (reset),
.io_in_bits_head (_out_channels_3_2_io_beat_bits_head), // @[TLSerdes.scala:62:50]
.io_in_bits_tail (_out_channels_3_2_io_beat_bits_tail), // @[TLSerdes.scala:62:50]
.io_out_ready (io_ser_3_out_ready),
.io_out_valid (io_ser_3_out_valid),
.io_out_bits_flit (io_ser_3_out_bits_flit)
); // @[TLSerdes.scala:69:23]
TLEFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28]
.clock (clock),
.reset (reset),
.io_beat_ready (_in_channels_0_2_io_beat_ready),
.io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:78:28]
TLDFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28]
.clock (clock),
.reset (reset),
.io_beat_ready (_in_channels_1_2_io_beat_ready),
.io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:79:28]
TLCFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28]
.clock (clock),
.reset (reset),
.io_beat_ready (_in_channels_2_2_io_beat_ready),
.io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:80:28]
TLBFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28]
.clock (clock),
.reset (reset),
.io_beat_ready (_in_channels_3_2_io_beat_ready),
.io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:81:28]
TLAFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28]
.clock (clock),
.reset (reset),
.io_protocol_ready (auto_client_out_a_ready),
.io_protocol_valid (auto_client_out_a_valid),
.io_protocol_bits_opcode (auto_client_out_a_bits_opcode),
.io_protocol_bits_param (auto_client_out_a_bits_param),
.io_protocol_bits_size (_in_channels_4_2_io_protocol_bits_size),
.io_protocol_bits_source (_in_channels_4_2_io_protocol_bits_source),
.io_protocol_bits_address (_in_channels_4_2_io_protocol_bits_address),
.io_protocol_bits_mask (auto_client_out_a_bits_mask),
.io_protocol_bits_data (auto_client_out_a_bits_data),
.io_protocol_bits_corrupt (auto_client_out_a_bits_corrupt),
.io_beat_ready (_in_channels_4_2_io_beat_ready),
.io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23]
.io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23]
.io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23]
.io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23]
); // @[TLSerdes.scala:82:28]
GenericDeserializer_TLBeatw10_f32 des_0 ( // @[TLSerdes.scala:86:23]
.io_in_ready (io_ser_0_in_ready),
.io_in_valid (io_ser_0_in_valid),
.io_in_bits_flit (io_ser_0_in_bits_flit),
.io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28]
.io_out_valid (_des_0_io_out_valid),
.io_out_bits_head (_des_0_io_out_bits_head),
.io_out_bits_tail (_des_0_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw67_f32 des_1 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_1_in_ready),
.io_in_valid (io_ser_1_in_valid),
.io_in_bits_flit (io_ser_1_in_bits_flit),
.io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28]
.io_out_valid (_des_1_io_out_valid),
.io_out_bits_payload (/* unused */),
.io_out_bits_head (_des_1_io_out_bits_head),
.io_out_bits_tail (_des_1_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32 des_2 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_2_in_ready),
.io_in_valid (io_ser_2_in_valid),
.io_in_bits_flit (io_ser_2_in_bits_flit),
.io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28]
.io_out_valid (_des_2_io_out_valid),
.io_out_bits_payload (/* unused */),
.io_out_bits_head (_des_2_io_out_bits_head),
.io_out_bits_tail (_des_2_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw87_f32 des_3 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_3_in_ready),
.io_in_valid (io_ser_3_in_valid),
.io_in_bits_flit (io_ser_3_in_bits_flit),
.io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28]
.io_out_valid (_des_3_io_out_valid),
.io_out_bits_head (_des_3_io_out_bits_head),
.io_out_bits_tail (_des_3_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
GenericDeserializer_TLBeatw88_f32 des_4 ( // @[TLSerdes.scala:86:23]
.clock (clock),
.reset (reset),
.io_in_ready (io_ser_4_in_ready),
.io_in_valid (io_ser_4_in_valid),
.io_in_bits_flit (io_ser_4_in_bits_flit),
.io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28]
.io_out_valid (_des_4_io_out_valid),
.io_out_bits_payload (_des_4_io_out_bits_payload),
.io_out_bits_head (_des_4_io_out_bits_head),
.io_out_bits_tail (_des_4_io_out_bits_tail)
); // @[TLSerdes.scala:86:23]
assign auto_client_out_a_bits_size = _in_channels_4_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:39:9, :82:28, :85:9]
assign auto_client_out_a_bits_source = _in_channels_4_2_io_protocol_bits_source[3:0]; // @[TLSerdes.scala:39:9, :82:28, :85:9]
assign auto_client_out_a_bits_address = _in_channels_4_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:39:9, :82:28, :85:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_226 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_226( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_21 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h30))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<4>(0h8))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<4>(0h9))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<4>(0ha))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<4>(0hb))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 3, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 4)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<1>(0h1))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<4>(0hf))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 3, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 4)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h0))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<4>(0hf))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE : UInt<1>[11]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_37
connect _source_ok_WIRE[8], _source_ok_T_38
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_40
node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9])
node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<4>(0h8))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<4>(0h9))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<4>(0ha))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<4>(0hb))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0)
node _T_64 = shr(io.in.a.bits.source, 4)
node _T_65 = eq(_T_64, UInt<1>(0h1))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<4>(0hf))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0)
node _T_77 = shr(io.in.a.bits.source, 4)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<4>(0hf))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _T_90 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_93 = cvt(_T_92)
node _T_94 = and(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = asSInt(_T_94)
node _T_96 = eq(_T_95, asSInt(UInt<1>(0h0)))
node _T_97 = or(_T_91, _T_96)
node _T_98 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_99 = eq(_T_98, UInt<1>(0h0))
node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_101 = cvt(_T_100)
node _T_102 = and(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = asSInt(_T_102)
node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0)))
node _T_105 = or(_T_99, _T_104)
node _T_106 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _T_114 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_115 = eq(_T_114, UInt<1>(0h0))
node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = or(_T_115, _T_120)
node _T_122 = and(_T_11, _T_24)
node _T_123 = and(_T_122, _T_37)
node _T_124 = and(_T_123, _T_50)
node _T_125 = and(_T_124, _T_63)
node _T_126 = and(_T_125, _T_76)
node _T_127 = and(_T_126, _T_89)
node _T_128 = and(_T_127, _T_97)
node _T_129 = and(_T_128, _T_105)
node _T_130 = and(_T_129, _T_113)
node _T_131 = and(_T_130, _T_121)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_131, UInt<1>(0h1), "") : assert_1
node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_135 :
node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_140 = shr(io.in.a.bits.source, 2)
node _T_141 = eq(_T_140, UInt<4>(0h8))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_145 = and(_T_143, _T_144)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_146 = shr(io.in.a.bits.source, 2)
node _T_147 = eq(_T_146, UInt<4>(0h9))
node _T_148 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_149 = and(_T_147, _T_148)
node _T_150 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_152 = shr(io.in.a.bits.source, 2)
node _T_153 = eq(_T_152, UInt<4>(0ha))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_157 = and(_T_155, _T_156)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_158 = shr(io.in.a.bits.source, 2)
node _T_159 = eq(_T_158, UInt<4>(0hb))
node _T_160 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_161 = and(_T_159, _T_160)
node _T_162 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_163 = and(_T_161, _T_162)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0)
node _T_164 = shr(io.in.a.bits.source, 4)
node _T_165 = eq(_T_164, UInt<1>(0h1))
node _T_166 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_167 = and(_T_165, _T_166)
node _T_168 = leq(uncommonBits_10, UInt<4>(0hf))
node _T_169 = and(_T_167, _T_168)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0)
node _T_170 = shr(io.in.a.bits.source, 4)
node _T_171 = eq(_T_170, UInt<1>(0h0))
node _T_172 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_173 = and(_T_171, _T_172)
node _T_174 = leq(uncommonBits_11, UInt<4>(0hf))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_177 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_178 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_179 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_180 = or(_T_139, _T_145)
node _T_181 = or(_T_180, _T_151)
node _T_182 = or(_T_181, _T_157)
node _T_183 = or(_T_182, _T_163)
node _T_184 = or(_T_183, _T_169)
node _T_185 = or(_T_184, _T_175)
node _T_186 = or(_T_185, _T_176)
node _T_187 = or(_T_186, _T_177)
node _T_188 = or(_T_187, _T_178)
node _T_189 = or(_T_188, _T_179)
node _T_190 = and(_T_138, _T_189)
node _T_191 = or(UInt<1>(0h0), _T_190)
node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_193 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<14>(0h2000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_199 = cvt(_T_198)
node _T_200 = and(_T_199, asSInt(UInt<13>(0h1000)))
node _T_201 = asSInt(_T_200)
node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0)))
node _T_203 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_204 = cvt(_T_203)
node _T_205 = and(_T_204, asSInt(UInt<17>(0h10000)))
node _T_206 = asSInt(_T_205)
node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0)))
node _T_208 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_209 = cvt(_T_208)
node _T_210 = and(_T_209, asSInt(UInt<18>(0h2f000)))
node _T_211 = asSInt(_T_210)
node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_214 = cvt(_T_213)
node _T_215 = and(_T_214, asSInt(UInt<17>(0h10000)))
node _T_216 = asSInt(_T_215)
node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0)))
node _T_218 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_219 = cvt(_T_218)
node _T_220 = and(_T_219, asSInt(UInt<13>(0h1000)))
node _T_221 = asSInt(_T_220)
node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0)))
node _T_223 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_224 = cvt(_T_223)
node _T_225 = and(_T_224, asSInt(UInt<27>(0h4000000)))
node _T_226 = asSInt(_T_225)
node _T_227 = eq(_T_226, asSInt(UInt<1>(0h0)))
node _T_228 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_229 = cvt(_T_228)
node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000)))
node _T_231 = asSInt(_T_230)
node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0)))
node _T_233 = or(_T_197, _T_202)
node _T_234 = or(_T_233, _T_207)
node _T_235 = or(_T_234, _T_212)
node _T_236 = or(_T_235, _T_217)
node _T_237 = or(_T_236, _T_222)
node _T_238 = or(_T_237, _T_227)
node _T_239 = or(_T_238, _T_232)
node _T_240 = and(_T_192, _T_239)
node _T_241 = or(UInt<1>(0h0), _T_240)
node _T_242 = and(_T_191, _T_241)
node _T_243 = asUInt(reset)
node _T_244 = eq(_T_243, UInt<1>(0h0))
when _T_244 :
node _T_245 = eq(_T_242, UInt<1>(0h0))
when _T_245 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_242, UInt<1>(0h1), "") : assert_2
node _T_246 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_247 = shr(io.in.a.bits.source, 2)
node _T_248 = eq(_T_247, UInt<4>(0h8))
node _T_249 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_250 = and(_T_248, _T_249)
node _T_251 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_252 = and(_T_250, _T_251)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_253 = shr(io.in.a.bits.source, 2)
node _T_254 = eq(_T_253, UInt<4>(0h9))
node _T_255 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_256 = and(_T_254, _T_255)
node _T_257 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_258 = and(_T_256, _T_257)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_259 = shr(io.in.a.bits.source, 2)
node _T_260 = eq(_T_259, UInt<4>(0ha))
node _T_261 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_262 = and(_T_260, _T_261)
node _T_263 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_264 = and(_T_262, _T_263)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_265 = shr(io.in.a.bits.source, 2)
node _T_266 = eq(_T_265, UInt<4>(0hb))
node _T_267 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_268 = and(_T_266, _T_267)
node _T_269 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_270 = and(_T_268, _T_269)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0)
node _T_271 = shr(io.in.a.bits.source, 4)
node _T_272 = eq(_T_271, UInt<1>(0h1))
node _T_273 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_274 = and(_T_272, _T_273)
node _T_275 = leq(uncommonBits_16, UInt<4>(0hf))
node _T_276 = and(_T_274, _T_275)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0)
node _T_277 = shr(io.in.a.bits.source, 4)
node _T_278 = eq(_T_277, UInt<1>(0h0))
node _T_279 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_280 = and(_T_278, _T_279)
node _T_281 = leq(uncommonBits_17, UInt<4>(0hf))
node _T_282 = and(_T_280, _T_281)
node _T_283 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_284 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_285 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_286 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE : UInt<1>[11]
connect _WIRE[0], _T_246
connect _WIRE[1], _T_252
connect _WIRE[2], _T_258
connect _WIRE[3], _T_264
connect _WIRE[4], _T_270
connect _WIRE[5], _T_276
connect _WIRE[6], _T_282
connect _WIRE[7], _T_283
connect _WIRE[8], _T_284
connect _WIRE[9], _T_285
connect _WIRE[10], _T_286
node _T_287 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_288 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_289 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_290 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_291 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_293 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_294 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_295 = mux(_WIRE[7], _T_287, UInt<1>(0h0))
node _T_296 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_297 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_298 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_299 = or(_T_288, _T_289)
node _T_300 = or(_T_299, _T_290)
node _T_301 = or(_T_300, _T_291)
node _T_302 = or(_T_301, _T_292)
node _T_303 = or(_T_302, _T_293)
node _T_304 = or(_T_303, _T_294)
node _T_305 = or(_T_304, _T_295)
node _T_306 = or(_T_305, _T_296)
node _T_307 = or(_T_306, _T_297)
node _T_308 = or(_T_307, _T_298)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_308
node _T_309 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_310 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_311 = and(_T_309, _T_310)
node _T_312 = or(UInt<1>(0h0), _T_311)
node _T_313 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_314 = cvt(_T_313)
node _T_315 = and(_T_314, asSInt(UInt<14>(0h2000)))
node _T_316 = asSInt(_T_315)
node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0)))
node _T_318 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_319 = cvt(_T_318)
node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000)))
node _T_321 = asSInt(_T_320)
node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0)))
node _T_323 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_324 = cvt(_T_323)
node _T_325 = and(_T_324, asSInt(UInt<17>(0h10000)))
node _T_326 = asSInt(_T_325)
node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0)))
node _T_328 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_329 = cvt(_T_328)
node _T_330 = and(_T_329, asSInt(UInt<18>(0h2f000)))
node _T_331 = asSInt(_T_330)
node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0)))
node _T_333 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_334 = cvt(_T_333)
node _T_335 = and(_T_334, asSInt(UInt<17>(0h10000)))
node _T_336 = asSInt(_T_335)
node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0)))
node _T_338 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_339 = cvt(_T_338)
node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000)))
node _T_341 = asSInt(_T_340)
node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0)))
node _T_343 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_344 = cvt(_T_343)
node _T_345 = and(_T_344, asSInt(UInt<27>(0h4000000)))
node _T_346 = asSInt(_T_345)
node _T_347 = eq(_T_346, asSInt(UInt<1>(0h0)))
node _T_348 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_349 = cvt(_T_348)
node _T_350 = and(_T_349, asSInt(UInt<13>(0h1000)))
node _T_351 = asSInt(_T_350)
node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0)))
node _T_353 = or(_T_317, _T_322)
node _T_354 = or(_T_353, _T_327)
node _T_355 = or(_T_354, _T_332)
node _T_356 = or(_T_355, _T_337)
node _T_357 = or(_T_356, _T_342)
node _T_358 = or(_T_357, _T_347)
node _T_359 = or(_T_358, _T_352)
node _T_360 = and(_T_312, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = and(_WIRE_1, _T_361)
node _T_363 = asUInt(reset)
node _T_364 = eq(_T_363, UInt<1>(0h0))
when _T_364 :
node _T_365 = eq(_T_362, UInt<1>(0h0))
when _T_365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_362, UInt<1>(0h1), "") : assert_3
node _T_366 = asUInt(reset)
node _T_367 = eq(_T_366, UInt<1>(0h0))
when _T_367 :
node _T_368 = eq(source_ok, UInt<1>(0h0))
when _T_368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_369 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(_T_369, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_369, UInt<1>(0h1), "") : assert_5
node _T_373 = asUInt(reset)
node _T_374 = eq(_T_373, UInt<1>(0h0))
when _T_374 :
node _T_375 = eq(is_aligned, UInt<1>(0h0))
when _T_375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_376 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_377 = asUInt(reset)
node _T_378 = eq(_T_377, UInt<1>(0h0))
when _T_378 :
node _T_379 = eq(_T_376, UInt<1>(0h0))
when _T_379 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_376, UInt<1>(0h1), "") : assert_7
node _T_380 = not(io.in.a.bits.mask)
node _T_381 = eq(_T_380, UInt<1>(0h0))
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(_T_381, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_381, UInt<1>(0h1), "") : assert_8
node _T_385 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_385, UInt<1>(0h1), "") : assert_9
node _T_389 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_389 :
node _T_390 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_391 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_392 = and(_T_390, _T_391)
node _T_393 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_394 = shr(io.in.a.bits.source, 2)
node _T_395 = eq(_T_394, UInt<4>(0h8))
node _T_396 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_397 = and(_T_395, _T_396)
node _T_398 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_399 = and(_T_397, _T_398)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_400 = shr(io.in.a.bits.source, 2)
node _T_401 = eq(_T_400, UInt<4>(0h9))
node _T_402 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_403 = and(_T_401, _T_402)
node _T_404 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_405 = and(_T_403, _T_404)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_406 = shr(io.in.a.bits.source, 2)
node _T_407 = eq(_T_406, UInt<4>(0ha))
node _T_408 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_409 = and(_T_407, _T_408)
node _T_410 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_411 = and(_T_409, _T_410)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_412 = shr(io.in.a.bits.source, 2)
node _T_413 = eq(_T_412, UInt<4>(0hb))
node _T_414 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_415 = and(_T_413, _T_414)
node _T_416 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_417 = and(_T_415, _T_416)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 3, 0)
node _T_418 = shr(io.in.a.bits.source, 4)
node _T_419 = eq(_T_418, UInt<1>(0h1))
node _T_420 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_421 = and(_T_419, _T_420)
node _T_422 = leq(uncommonBits_22, UInt<4>(0hf))
node _T_423 = and(_T_421, _T_422)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 3, 0)
node _T_424 = shr(io.in.a.bits.source, 4)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_427 = and(_T_425, _T_426)
node _T_428 = leq(uncommonBits_23, UInt<4>(0hf))
node _T_429 = and(_T_427, _T_428)
node _T_430 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_431 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_432 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_433 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_434 = or(_T_393, _T_399)
node _T_435 = or(_T_434, _T_405)
node _T_436 = or(_T_435, _T_411)
node _T_437 = or(_T_436, _T_417)
node _T_438 = or(_T_437, _T_423)
node _T_439 = or(_T_438, _T_429)
node _T_440 = or(_T_439, _T_430)
node _T_441 = or(_T_440, _T_431)
node _T_442 = or(_T_441, _T_432)
node _T_443 = or(_T_442, _T_433)
node _T_444 = and(_T_392, _T_443)
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_447 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_448 = cvt(_T_447)
node _T_449 = and(_T_448, asSInt(UInt<14>(0h2000)))
node _T_450 = asSInt(_T_449)
node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0)))
node _T_452 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_453 = cvt(_T_452)
node _T_454 = and(_T_453, asSInt(UInt<13>(0h1000)))
node _T_455 = asSInt(_T_454)
node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0)))
node _T_457 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_458 = cvt(_T_457)
node _T_459 = and(_T_458, asSInt(UInt<17>(0h10000)))
node _T_460 = asSInt(_T_459)
node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0)))
node _T_462 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_463 = cvt(_T_462)
node _T_464 = and(_T_463, asSInt(UInt<18>(0h2f000)))
node _T_465 = asSInt(_T_464)
node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0)))
node _T_467 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<17>(0h10000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_473 = cvt(_T_472)
node _T_474 = and(_T_473, asSInt(UInt<13>(0h1000)))
node _T_475 = asSInt(_T_474)
node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0)))
node _T_477 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_478 = cvt(_T_477)
node _T_479 = and(_T_478, asSInt(UInt<27>(0h4000000)))
node _T_480 = asSInt(_T_479)
node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0)))
node _T_482 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_483 = cvt(_T_482)
node _T_484 = and(_T_483, asSInt(UInt<13>(0h1000)))
node _T_485 = asSInt(_T_484)
node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0)))
node _T_487 = or(_T_451, _T_456)
node _T_488 = or(_T_487, _T_461)
node _T_489 = or(_T_488, _T_466)
node _T_490 = or(_T_489, _T_471)
node _T_491 = or(_T_490, _T_476)
node _T_492 = or(_T_491, _T_481)
node _T_493 = or(_T_492, _T_486)
node _T_494 = and(_T_446, _T_493)
node _T_495 = or(UInt<1>(0h0), _T_494)
node _T_496 = and(_T_445, _T_495)
node _T_497 = asUInt(reset)
node _T_498 = eq(_T_497, UInt<1>(0h0))
when _T_498 :
node _T_499 = eq(_T_496, UInt<1>(0h0))
when _T_499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_496, UInt<1>(0h1), "") : assert_10
node _T_500 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_501 = shr(io.in.a.bits.source, 2)
node _T_502 = eq(_T_501, UInt<4>(0h8))
node _T_503 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_504 = and(_T_502, _T_503)
node _T_505 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_506 = and(_T_504, _T_505)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_507 = shr(io.in.a.bits.source, 2)
node _T_508 = eq(_T_507, UInt<4>(0h9))
node _T_509 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_510 = and(_T_508, _T_509)
node _T_511 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_512 = and(_T_510, _T_511)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_513 = shr(io.in.a.bits.source, 2)
node _T_514 = eq(_T_513, UInt<4>(0ha))
node _T_515 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_516 = and(_T_514, _T_515)
node _T_517 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_518 = and(_T_516, _T_517)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_519 = shr(io.in.a.bits.source, 2)
node _T_520 = eq(_T_519, UInt<4>(0hb))
node _T_521 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_522 = and(_T_520, _T_521)
node _T_523 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_524 = and(_T_522, _T_523)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 3, 0)
node _T_525 = shr(io.in.a.bits.source, 4)
node _T_526 = eq(_T_525, UInt<1>(0h1))
node _T_527 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_528 = and(_T_526, _T_527)
node _T_529 = leq(uncommonBits_28, UInt<4>(0hf))
node _T_530 = and(_T_528, _T_529)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 3, 0)
node _T_531 = shr(io.in.a.bits.source, 4)
node _T_532 = eq(_T_531, UInt<1>(0h0))
node _T_533 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_534 = and(_T_532, _T_533)
node _T_535 = leq(uncommonBits_29, UInt<4>(0hf))
node _T_536 = and(_T_534, _T_535)
node _T_537 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_538 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_539 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_540 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE_2 : UInt<1>[11]
connect _WIRE_2[0], _T_500
connect _WIRE_2[1], _T_506
connect _WIRE_2[2], _T_512
connect _WIRE_2[3], _T_518
connect _WIRE_2[4], _T_524
connect _WIRE_2[5], _T_530
connect _WIRE_2[6], _T_536
connect _WIRE_2[7], _T_537
connect _WIRE_2[8], _T_538
connect _WIRE_2[9], _T_539
connect _WIRE_2[10], _T_540
node _T_541 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_542 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_543 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_544 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_545 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_546 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_547 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0))
node _T_548 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_549 = mux(_WIRE_2[7], _T_541, UInt<1>(0h0))
node _T_550 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_551 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_552 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_553 = or(_T_542, _T_543)
node _T_554 = or(_T_553, _T_544)
node _T_555 = or(_T_554, _T_545)
node _T_556 = or(_T_555, _T_546)
node _T_557 = or(_T_556, _T_547)
node _T_558 = or(_T_557, _T_548)
node _T_559 = or(_T_558, _T_549)
node _T_560 = or(_T_559, _T_550)
node _T_561 = or(_T_560, _T_551)
node _T_562 = or(_T_561, _T_552)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_562
node _T_563 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_564 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_565 = and(_T_563, _T_564)
node _T_566 = or(UInt<1>(0h0), _T_565)
node _T_567 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_568 = cvt(_T_567)
node _T_569 = and(_T_568, asSInt(UInt<14>(0h2000)))
node _T_570 = asSInt(_T_569)
node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0)))
node _T_572 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_573 = cvt(_T_572)
node _T_574 = and(_T_573, asSInt(UInt<13>(0h1000)))
node _T_575 = asSInt(_T_574)
node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0)))
node _T_577 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_578 = cvt(_T_577)
node _T_579 = and(_T_578, asSInt(UInt<17>(0h10000)))
node _T_580 = asSInt(_T_579)
node _T_581 = eq(_T_580, asSInt(UInt<1>(0h0)))
node _T_582 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_583 = cvt(_T_582)
node _T_584 = and(_T_583, asSInt(UInt<18>(0h2f000)))
node _T_585 = asSInt(_T_584)
node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0)))
node _T_587 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_588 = cvt(_T_587)
node _T_589 = and(_T_588, asSInt(UInt<17>(0h10000)))
node _T_590 = asSInt(_T_589)
node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0)))
node _T_592 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_593 = cvt(_T_592)
node _T_594 = and(_T_593, asSInt(UInt<13>(0h1000)))
node _T_595 = asSInt(_T_594)
node _T_596 = eq(_T_595, asSInt(UInt<1>(0h0)))
node _T_597 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_598 = cvt(_T_597)
node _T_599 = and(_T_598, asSInt(UInt<27>(0h4000000)))
node _T_600 = asSInt(_T_599)
node _T_601 = eq(_T_600, asSInt(UInt<1>(0h0)))
node _T_602 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_603 = cvt(_T_602)
node _T_604 = and(_T_603, asSInt(UInt<13>(0h1000)))
node _T_605 = asSInt(_T_604)
node _T_606 = eq(_T_605, asSInt(UInt<1>(0h0)))
node _T_607 = or(_T_571, _T_576)
node _T_608 = or(_T_607, _T_581)
node _T_609 = or(_T_608, _T_586)
node _T_610 = or(_T_609, _T_591)
node _T_611 = or(_T_610, _T_596)
node _T_612 = or(_T_611, _T_601)
node _T_613 = or(_T_612, _T_606)
node _T_614 = and(_T_566, _T_613)
node _T_615 = or(UInt<1>(0h0), _T_614)
node _T_616 = and(_WIRE_3, _T_615)
node _T_617 = asUInt(reset)
node _T_618 = eq(_T_617, UInt<1>(0h0))
when _T_618 :
node _T_619 = eq(_T_616, UInt<1>(0h0))
when _T_619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_616, UInt<1>(0h1), "") : assert_11
node _T_620 = asUInt(reset)
node _T_621 = eq(_T_620, UInt<1>(0h0))
when _T_621 :
node _T_622 = eq(source_ok, UInt<1>(0h0))
when _T_622 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_623 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_624 = asUInt(reset)
node _T_625 = eq(_T_624, UInt<1>(0h0))
when _T_625 :
node _T_626 = eq(_T_623, UInt<1>(0h0))
when _T_626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_623, UInt<1>(0h1), "") : assert_13
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(is_aligned, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_630 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_630, UInt<1>(0h1), "") : assert_15
node _T_634 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_T_634, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_634, UInt<1>(0h1), "") : assert_16
node _T_638 = not(io.in.a.bits.mask)
node _T_639 = eq(_T_638, UInt<1>(0h0))
node _T_640 = asUInt(reset)
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(_T_639, UInt<1>(0h0))
when _T_642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_639, UInt<1>(0h1), "") : assert_17
node _T_643 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_644 = asUInt(reset)
node _T_645 = eq(_T_644, UInt<1>(0h0))
when _T_645 :
node _T_646 = eq(_T_643, UInt<1>(0h0))
when _T_646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_643, UInt<1>(0h1), "") : assert_18
node _T_647 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_647 :
node _T_648 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_649 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_650 = and(_T_648, _T_649)
node _T_651 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_652 = shr(io.in.a.bits.source, 2)
node _T_653 = eq(_T_652, UInt<4>(0h8))
node _T_654 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_655 = and(_T_653, _T_654)
node _T_656 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_657 = and(_T_655, _T_656)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_658 = shr(io.in.a.bits.source, 2)
node _T_659 = eq(_T_658, UInt<4>(0h9))
node _T_660 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_661 = and(_T_659, _T_660)
node _T_662 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_663 = and(_T_661, _T_662)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_664 = shr(io.in.a.bits.source, 2)
node _T_665 = eq(_T_664, UInt<4>(0ha))
node _T_666 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_667 = and(_T_665, _T_666)
node _T_668 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_669 = and(_T_667, _T_668)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_670 = shr(io.in.a.bits.source, 2)
node _T_671 = eq(_T_670, UInt<4>(0hb))
node _T_672 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_673 = and(_T_671, _T_672)
node _T_674 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_675 = and(_T_673, _T_674)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 3, 0)
node _T_676 = shr(io.in.a.bits.source, 4)
node _T_677 = eq(_T_676, UInt<1>(0h1))
node _T_678 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_679 = and(_T_677, _T_678)
node _T_680 = leq(uncommonBits_34, UInt<4>(0hf))
node _T_681 = and(_T_679, _T_680)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 3, 0)
node _T_682 = shr(io.in.a.bits.source, 4)
node _T_683 = eq(_T_682, UInt<1>(0h0))
node _T_684 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_685 = and(_T_683, _T_684)
node _T_686 = leq(uncommonBits_35, UInt<4>(0hf))
node _T_687 = and(_T_685, _T_686)
node _T_688 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_689 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_690 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_691 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_692 = or(_T_651, _T_657)
node _T_693 = or(_T_692, _T_663)
node _T_694 = or(_T_693, _T_669)
node _T_695 = or(_T_694, _T_675)
node _T_696 = or(_T_695, _T_681)
node _T_697 = or(_T_696, _T_687)
node _T_698 = or(_T_697, _T_688)
node _T_699 = or(_T_698, _T_689)
node _T_700 = or(_T_699, _T_690)
node _T_701 = or(_T_700, _T_691)
node _T_702 = and(_T_650, _T_701)
node _T_703 = or(UInt<1>(0h0), _T_702)
node _T_704 = asUInt(reset)
node _T_705 = eq(_T_704, UInt<1>(0h0))
when _T_705 :
node _T_706 = eq(_T_703, UInt<1>(0h0))
when _T_706 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_703, UInt<1>(0h1), "") : assert_19
node _T_707 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_708 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_709 = and(_T_707, _T_708)
node _T_710 = or(UInt<1>(0h0), _T_709)
node _T_711 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_712 = cvt(_T_711)
node _T_713 = and(_T_712, asSInt(UInt<13>(0h1000)))
node _T_714 = asSInt(_T_713)
node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0)))
node _T_716 = and(_T_710, _T_715)
node _T_717 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_718 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_719 = and(_T_717, _T_718)
node _T_720 = or(UInt<1>(0h0), _T_719)
node _T_721 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_722 = cvt(_T_721)
node _T_723 = and(_T_722, asSInt(UInt<14>(0h2000)))
node _T_724 = asSInt(_T_723)
node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0)))
node _T_726 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_727 = cvt(_T_726)
node _T_728 = and(_T_727, asSInt(UInt<17>(0h10000)))
node _T_729 = asSInt(_T_728)
node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0)))
node _T_731 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_732 = cvt(_T_731)
node _T_733 = and(_T_732, asSInt(UInt<18>(0h2f000)))
node _T_734 = asSInt(_T_733)
node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0)))
node _T_736 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_737 = cvt(_T_736)
node _T_738 = and(_T_737, asSInt(UInt<17>(0h10000)))
node _T_739 = asSInt(_T_738)
node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0)))
node _T_741 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_742 = cvt(_T_741)
node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000)))
node _T_744 = asSInt(_T_743)
node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0)))
node _T_746 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_747 = cvt(_T_746)
node _T_748 = and(_T_747, asSInt(UInt<27>(0h4000000)))
node _T_749 = asSInt(_T_748)
node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0)))
node _T_751 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_752 = cvt(_T_751)
node _T_753 = and(_T_752, asSInt(UInt<13>(0h1000)))
node _T_754 = asSInt(_T_753)
node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0)))
node _T_756 = or(_T_725, _T_730)
node _T_757 = or(_T_756, _T_735)
node _T_758 = or(_T_757, _T_740)
node _T_759 = or(_T_758, _T_745)
node _T_760 = or(_T_759, _T_750)
node _T_761 = or(_T_760, _T_755)
node _T_762 = and(_T_720, _T_761)
node _T_763 = or(UInt<1>(0h0), _T_716)
node _T_764 = or(_T_763, _T_762)
node _T_765 = asUInt(reset)
node _T_766 = eq(_T_765, UInt<1>(0h0))
when _T_766 :
node _T_767 = eq(_T_764, UInt<1>(0h0))
when _T_767 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_764, UInt<1>(0h1), "") : assert_20
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(source_ok, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_771 = asUInt(reset)
node _T_772 = eq(_T_771, UInt<1>(0h0))
when _T_772 :
node _T_773 = eq(is_aligned, UInt<1>(0h0))
when _T_773 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_774 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_775 = asUInt(reset)
node _T_776 = eq(_T_775, UInt<1>(0h0))
when _T_776 :
node _T_777 = eq(_T_774, UInt<1>(0h0))
when _T_777 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_774, UInt<1>(0h1), "") : assert_23
node _T_778 = eq(io.in.a.bits.mask, mask)
node _T_779 = asUInt(reset)
node _T_780 = eq(_T_779, UInt<1>(0h0))
when _T_780 :
node _T_781 = eq(_T_778, UInt<1>(0h0))
when _T_781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_778, UInt<1>(0h1), "") : assert_24
node _T_782 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_783 = asUInt(reset)
node _T_784 = eq(_T_783, UInt<1>(0h0))
when _T_784 :
node _T_785 = eq(_T_782, UInt<1>(0h0))
when _T_785 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_782, UInt<1>(0h1), "") : assert_25
node _T_786 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_786 :
node _T_787 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_788 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_789 = and(_T_787, _T_788)
node _T_790 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_791 = shr(io.in.a.bits.source, 2)
node _T_792 = eq(_T_791, UInt<4>(0h8))
node _T_793 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_794 = and(_T_792, _T_793)
node _T_795 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_796 = and(_T_794, _T_795)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_797 = shr(io.in.a.bits.source, 2)
node _T_798 = eq(_T_797, UInt<4>(0h9))
node _T_799 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_800 = and(_T_798, _T_799)
node _T_801 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_802 = and(_T_800, _T_801)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_803 = shr(io.in.a.bits.source, 2)
node _T_804 = eq(_T_803, UInt<4>(0ha))
node _T_805 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_806 = and(_T_804, _T_805)
node _T_807 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_808 = and(_T_806, _T_807)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_809 = shr(io.in.a.bits.source, 2)
node _T_810 = eq(_T_809, UInt<4>(0hb))
node _T_811 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_812 = and(_T_810, _T_811)
node _T_813 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_814 = and(_T_812, _T_813)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 3, 0)
node _T_815 = shr(io.in.a.bits.source, 4)
node _T_816 = eq(_T_815, UInt<1>(0h1))
node _T_817 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_818 = and(_T_816, _T_817)
node _T_819 = leq(uncommonBits_40, UInt<4>(0hf))
node _T_820 = and(_T_818, _T_819)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 3, 0)
node _T_821 = shr(io.in.a.bits.source, 4)
node _T_822 = eq(_T_821, UInt<1>(0h0))
node _T_823 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_824 = and(_T_822, _T_823)
node _T_825 = leq(uncommonBits_41, UInt<4>(0hf))
node _T_826 = and(_T_824, _T_825)
node _T_827 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_828 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_829 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_830 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_831 = or(_T_790, _T_796)
node _T_832 = or(_T_831, _T_802)
node _T_833 = or(_T_832, _T_808)
node _T_834 = or(_T_833, _T_814)
node _T_835 = or(_T_834, _T_820)
node _T_836 = or(_T_835, _T_826)
node _T_837 = or(_T_836, _T_827)
node _T_838 = or(_T_837, _T_828)
node _T_839 = or(_T_838, _T_829)
node _T_840 = or(_T_839, _T_830)
node _T_841 = and(_T_789, _T_840)
node _T_842 = or(UInt<1>(0h0), _T_841)
node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_845 = and(_T_843, _T_844)
node _T_846 = or(UInt<1>(0h0), _T_845)
node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_848 = cvt(_T_847)
node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000)))
node _T_850 = asSInt(_T_849)
node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0)))
node _T_852 = and(_T_846, _T_851)
node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_854 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_855 = and(_T_853, _T_854)
node _T_856 = or(UInt<1>(0h0), _T_855)
node _T_857 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_858 = cvt(_T_857)
node _T_859 = and(_T_858, asSInt(UInt<14>(0h2000)))
node _T_860 = asSInt(_T_859)
node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0)))
node _T_862 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_863 = cvt(_T_862)
node _T_864 = and(_T_863, asSInt(UInt<18>(0h2f000)))
node _T_865 = asSInt(_T_864)
node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0)))
node _T_867 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_868 = cvt(_T_867)
node _T_869 = and(_T_868, asSInt(UInt<17>(0h10000)))
node _T_870 = asSInt(_T_869)
node _T_871 = eq(_T_870, asSInt(UInt<1>(0h0)))
node _T_872 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_873 = cvt(_T_872)
node _T_874 = and(_T_873, asSInt(UInt<13>(0h1000)))
node _T_875 = asSInt(_T_874)
node _T_876 = eq(_T_875, asSInt(UInt<1>(0h0)))
node _T_877 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_878 = cvt(_T_877)
node _T_879 = and(_T_878, asSInt(UInt<27>(0h4000000)))
node _T_880 = asSInt(_T_879)
node _T_881 = eq(_T_880, asSInt(UInt<1>(0h0)))
node _T_882 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_883 = cvt(_T_882)
node _T_884 = and(_T_883, asSInt(UInt<13>(0h1000)))
node _T_885 = asSInt(_T_884)
node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0)))
node _T_887 = or(_T_861, _T_866)
node _T_888 = or(_T_887, _T_871)
node _T_889 = or(_T_888, _T_876)
node _T_890 = or(_T_889, _T_881)
node _T_891 = or(_T_890, _T_886)
node _T_892 = and(_T_856, _T_891)
node _T_893 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_894 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_895 = cvt(_T_894)
node _T_896 = and(_T_895, asSInt(UInt<17>(0h10000)))
node _T_897 = asSInt(_T_896)
node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0)))
node _T_899 = and(_T_893, _T_898)
node _T_900 = or(UInt<1>(0h0), _T_852)
node _T_901 = or(_T_900, _T_892)
node _T_902 = or(_T_901, _T_899)
node _T_903 = and(_T_842, _T_902)
node _T_904 = asUInt(reset)
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(_T_903, UInt<1>(0h0))
when _T_906 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_903, UInt<1>(0h1), "") : assert_26
node _T_907 = asUInt(reset)
node _T_908 = eq(_T_907, UInt<1>(0h0))
when _T_908 :
node _T_909 = eq(source_ok, UInt<1>(0h0))
when _T_909 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_910 = asUInt(reset)
node _T_911 = eq(_T_910, UInt<1>(0h0))
when _T_911 :
node _T_912 = eq(is_aligned, UInt<1>(0h0))
when _T_912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_913 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_914 = asUInt(reset)
node _T_915 = eq(_T_914, UInt<1>(0h0))
when _T_915 :
node _T_916 = eq(_T_913, UInt<1>(0h0))
when _T_916 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_913, UInt<1>(0h1), "") : assert_29
node _T_917 = eq(io.in.a.bits.mask, mask)
node _T_918 = asUInt(reset)
node _T_919 = eq(_T_918, UInt<1>(0h0))
when _T_919 :
node _T_920 = eq(_T_917, UInt<1>(0h0))
when _T_920 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_917, UInt<1>(0h1), "") : assert_30
node _T_921 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_921 :
node _T_922 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_923 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_924 = and(_T_922, _T_923)
node _T_925 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_926 = shr(io.in.a.bits.source, 2)
node _T_927 = eq(_T_926, UInt<4>(0h8))
node _T_928 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_929 = and(_T_927, _T_928)
node _T_930 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_931 = and(_T_929, _T_930)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_932 = shr(io.in.a.bits.source, 2)
node _T_933 = eq(_T_932, UInt<4>(0h9))
node _T_934 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_935 = and(_T_933, _T_934)
node _T_936 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_937 = and(_T_935, _T_936)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_938 = shr(io.in.a.bits.source, 2)
node _T_939 = eq(_T_938, UInt<4>(0ha))
node _T_940 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_941 = and(_T_939, _T_940)
node _T_942 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_943 = and(_T_941, _T_942)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_944 = shr(io.in.a.bits.source, 2)
node _T_945 = eq(_T_944, UInt<4>(0hb))
node _T_946 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_947 = and(_T_945, _T_946)
node _T_948 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_949 = and(_T_947, _T_948)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 3, 0)
node _T_950 = shr(io.in.a.bits.source, 4)
node _T_951 = eq(_T_950, UInt<1>(0h1))
node _T_952 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_953 = and(_T_951, _T_952)
node _T_954 = leq(uncommonBits_46, UInt<4>(0hf))
node _T_955 = and(_T_953, _T_954)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 3, 0)
node _T_956 = shr(io.in.a.bits.source, 4)
node _T_957 = eq(_T_956, UInt<1>(0h0))
node _T_958 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_959 = and(_T_957, _T_958)
node _T_960 = leq(uncommonBits_47, UInt<4>(0hf))
node _T_961 = and(_T_959, _T_960)
node _T_962 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_963 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_964 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_965 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_966 = or(_T_925, _T_931)
node _T_967 = or(_T_966, _T_937)
node _T_968 = or(_T_967, _T_943)
node _T_969 = or(_T_968, _T_949)
node _T_970 = or(_T_969, _T_955)
node _T_971 = or(_T_970, _T_961)
node _T_972 = or(_T_971, _T_962)
node _T_973 = or(_T_972, _T_963)
node _T_974 = or(_T_973, _T_964)
node _T_975 = or(_T_974, _T_965)
node _T_976 = and(_T_924, _T_975)
node _T_977 = or(UInt<1>(0h0), _T_976)
node _T_978 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_979 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_980 = and(_T_978, _T_979)
node _T_981 = or(UInt<1>(0h0), _T_980)
node _T_982 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_983 = cvt(_T_982)
node _T_984 = and(_T_983, asSInt(UInt<13>(0h1000)))
node _T_985 = asSInt(_T_984)
node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0)))
node _T_987 = and(_T_981, _T_986)
node _T_988 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_989 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_990 = and(_T_988, _T_989)
node _T_991 = or(UInt<1>(0h0), _T_990)
node _T_992 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_993 = cvt(_T_992)
node _T_994 = and(_T_993, asSInt(UInt<14>(0h2000)))
node _T_995 = asSInt(_T_994)
node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0)))
node _T_997 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_998 = cvt(_T_997)
node _T_999 = and(_T_998, asSInt(UInt<18>(0h2f000)))
node _T_1000 = asSInt(_T_999)
node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0)))
node _T_1002 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1003 = cvt(_T_1002)
node _T_1004 = and(_T_1003, asSInt(UInt<17>(0h10000)))
node _T_1005 = asSInt(_T_1004)
node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0)))
node _T_1007 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1008 = cvt(_T_1007)
node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000)))
node _T_1010 = asSInt(_T_1009)
node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0)))
node _T_1012 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1013 = cvt(_T_1012)
node _T_1014 = and(_T_1013, asSInt(UInt<27>(0h4000000)))
node _T_1015 = asSInt(_T_1014)
node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0)))
node _T_1017 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1018 = cvt(_T_1017)
node _T_1019 = and(_T_1018, asSInt(UInt<13>(0h1000)))
node _T_1020 = asSInt(_T_1019)
node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0)))
node _T_1022 = or(_T_996, _T_1001)
node _T_1023 = or(_T_1022, _T_1006)
node _T_1024 = or(_T_1023, _T_1011)
node _T_1025 = or(_T_1024, _T_1016)
node _T_1026 = or(_T_1025, _T_1021)
node _T_1027 = and(_T_991, _T_1026)
node _T_1028 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1029 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1030 = cvt(_T_1029)
node _T_1031 = and(_T_1030, asSInt(UInt<17>(0h10000)))
node _T_1032 = asSInt(_T_1031)
node _T_1033 = eq(_T_1032, asSInt(UInt<1>(0h0)))
node _T_1034 = and(_T_1028, _T_1033)
node _T_1035 = or(UInt<1>(0h0), _T_987)
node _T_1036 = or(_T_1035, _T_1027)
node _T_1037 = or(_T_1036, _T_1034)
node _T_1038 = and(_T_977, _T_1037)
node _T_1039 = asUInt(reset)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
when _T_1040 :
node _T_1041 = eq(_T_1038, UInt<1>(0h0))
when _T_1041 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1038, UInt<1>(0h1), "") : assert_31
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(source_ok, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(is_aligned, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1048 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1049 = asUInt(reset)
node _T_1050 = eq(_T_1049, UInt<1>(0h0))
when _T_1050 :
node _T_1051 = eq(_T_1048, UInt<1>(0h0))
when _T_1051 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1048, UInt<1>(0h1), "") : assert_34
node _T_1052 = not(mask)
node _T_1053 = and(io.in.a.bits.mask, _T_1052)
node _T_1054 = eq(_T_1053, UInt<1>(0h0))
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_35
node _T_1058 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1058 :
node _T_1059 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1060 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1061 = and(_T_1059, _T_1060)
node _T_1062 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_1063 = shr(io.in.a.bits.source, 2)
node _T_1064 = eq(_T_1063, UInt<4>(0h8))
node _T_1065 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_1066 = and(_T_1064, _T_1065)
node _T_1067 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_1068 = and(_T_1066, _T_1067)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_1069 = shr(io.in.a.bits.source, 2)
node _T_1070 = eq(_T_1069, UInt<4>(0h9))
node _T_1071 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_1072 = and(_T_1070, _T_1071)
node _T_1073 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_1074 = and(_T_1072, _T_1073)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_1075 = shr(io.in.a.bits.source, 2)
node _T_1076 = eq(_T_1075, UInt<4>(0ha))
node _T_1077 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_1078 = and(_T_1076, _T_1077)
node _T_1079 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_1080 = and(_T_1078, _T_1079)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_1081 = shr(io.in.a.bits.source, 2)
node _T_1082 = eq(_T_1081, UInt<4>(0hb))
node _T_1083 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_1084 = and(_T_1082, _T_1083)
node _T_1085 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_1086 = and(_T_1084, _T_1085)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 3, 0)
node _T_1087 = shr(io.in.a.bits.source, 4)
node _T_1088 = eq(_T_1087, UInt<1>(0h1))
node _T_1089 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_1090 = and(_T_1088, _T_1089)
node _T_1091 = leq(uncommonBits_52, UInt<4>(0hf))
node _T_1092 = and(_T_1090, _T_1091)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 3, 0)
node _T_1093 = shr(io.in.a.bits.source, 4)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
node _T_1095 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_1096 = and(_T_1094, _T_1095)
node _T_1097 = leq(uncommonBits_53, UInt<4>(0hf))
node _T_1098 = and(_T_1096, _T_1097)
node _T_1099 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1100 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1101 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_1102 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1103 = or(_T_1062, _T_1068)
node _T_1104 = or(_T_1103, _T_1074)
node _T_1105 = or(_T_1104, _T_1080)
node _T_1106 = or(_T_1105, _T_1086)
node _T_1107 = or(_T_1106, _T_1092)
node _T_1108 = or(_T_1107, _T_1098)
node _T_1109 = or(_T_1108, _T_1099)
node _T_1110 = or(_T_1109, _T_1100)
node _T_1111 = or(_T_1110, _T_1101)
node _T_1112 = or(_T_1111, _T_1102)
node _T_1113 = and(_T_1061, _T_1112)
node _T_1114 = or(UInt<1>(0h0), _T_1113)
node _T_1115 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1116 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1117 = and(_T_1115, _T_1116)
node _T_1118 = or(UInt<1>(0h0), _T_1117)
node _T_1119 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1120 = cvt(_T_1119)
node _T_1121 = and(_T_1120, asSInt(UInt<14>(0h2000)))
node _T_1122 = asSInt(_T_1121)
node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0)))
node _T_1124 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1125 = cvt(_T_1124)
node _T_1126 = and(_T_1125, asSInt(UInt<13>(0h1000)))
node _T_1127 = asSInt(_T_1126)
node _T_1128 = eq(_T_1127, asSInt(UInt<1>(0h0)))
node _T_1129 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1130 = cvt(_T_1129)
node _T_1131 = and(_T_1130, asSInt(UInt<18>(0h2f000)))
node _T_1132 = asSInt(_T_1131)
node _T_1133 = eq(_T_1132, asSInt(UInt<1>(0h0)))
node _T_1134 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1135 = cvt(_T_1134)
node _T_1136 = and(_T_1135, asSInt(UInt<17>(0h10000)))
node _T_1137 = asSInt(_T_1136)
node _T_1138 = eq(_T_1137, asSInt(UInt<1>(0h0)))
node _T_1139 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1140 = cvt(_T_1139)
node _T_1141 = and(_T_1140, asSInt(UInt<13>(0h1000)))
node _T_1142 = asSInt(_T_1141)
node _T_1143 = eq(_T_1142, asSInt(UInt<1>(0h0)))
node _T_1144 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1145 = cvt(_T_1144)
node _T_1146 = and(_T_1145, asSInt(UInt<27>(0h4000000)))
node _T_1147 = asSInt(_T_1146)
node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0)))
node _T_1149 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1150 = cvt(_T_1149)
node _T_1151 = and(_T_1150, asSInt(UInt<13>(0h1000)))
node _T_1152 = asSInt(_T_1151)
node _T_1153 = eq(_T_1152, asSInt(UInt<1>(0h0)))
node _T_1154 = or(_T_1123, _T_1128)
node _T_1155 = or(_T_1154, _T_1133)
node _T_1156 = or(_T_1155, _T_1138)
node _T_1157 = or(_T_1156, _T_1143)
node _T_1158 = or(_T_1157, _T_1148)
node _T_1159 = or(_T_1158, _T_1153)
node _T_1160 = and(_T_1118, _T_1159)
node _T_1161 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1162 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1163 = cvt(_T_1162)
node _T_1164 = and(_T_1163, asSInt(UInt<17>(0h10000)))
node _T_1165 = asSInt(_T_1164)
node _T_1166 = eq(_T_1165, asSInt(UInt<1>(0h0)))
node _T_1167 = and(_T_1161, _T_1166)
node _T_1168 = or(UInt<1>(0h0), _T_1160)
node _T_1169 = or(_T_1168, _T_1167)
node _T_1170 = and(_T_1114, _T_1169)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_36
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(source_ok, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1177 = asUInt(reset)
node _T_1178 = eq(_T_1177, UInt<1>(0h0))
when _T_1178 :
node _T_1179 = eq(is_aligned, UInt<1>(0h0))
when _T_1179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1180 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_39
node _T_1184 = eq(io.in.a.bits.mask, mask)
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_40
node _T_1188 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1188 :
node _T_1189 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1190 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1191 = and(_T_1189, _T_1190)
node _T_1192 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_1193 = shr(io.in.a.bits.source, 2)
node _T_1194 = eq(_T_1193, UInt<4>(0h8))
node _T_1195 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_1196 = and(_T_1194, _T_1195)
node _T_1197 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_1198 = and(_T_1196, _T_1197)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_1199 = shr(io.in.a.bits.source, 2)
node _T_1200 = eq(_T_1199, UInt<4>(0h9))
node _T_1201 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_1202 = and(_T_1200, _T_1201)
node _T_1203 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_1204 = and(_T_1202, _T_1203)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_1205 = shr(io.in.a.bits.source, 2)
node _T_1206 = eq(_T_1205, UInt<4>(0ha))
node _T_1207 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_1208 = and(_T_1206, _T_1207)
node _T_1209 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_1210 = and(_T_1208, _T_1209)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_1211 = shr(io.in.a.bits.source, 2)
node _T_1212 = eq(_T_1211, UInt<4>(0hb))
node _T_1213 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_1214 = and(_T_1212, _T_1213)
node _T_1215 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_1216 = and(_T_1214, _T_1215)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 3, 0)
node _T_1217 = shr(io.in.a.bits.source, 4)
node _T_1218 = eq(_T_1217, UInt<1>(0h1))
node _T_1219 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_1220 = and(_T_1218, _T_1219)
node _T_1221 = leq(uncommonBits_58, UInt<4>(0hf))
node _T_1222 = and(_T_1220, _T_1221)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 3, 0)
node _T_1223 = shr(io.in.a.bits.source, 4)
node _T_1224 = eq(_T_1223, UInt<1>(0h0))
node _T_1225 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_1226 = and(_T_1224, _T_1225)
node _T_1227 = leq(uncommonBits_59, UInt<4>(0hf))
node _T_1228 = and(_T_1226, _T_1227)
node _T_1229 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1230 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1231 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_1232 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1233 = or(_T_1192, _T_1198)
node _T_1234 = or(_T_1233, _T_1204)
node _T_1235 = or(_T_1234, _T_1210)
node _T_1236 = or(_T_1235, _T_1216)
node _T_1237 = or(_T_1236, _T_1222)
node _T_1238 = or(_T_1237, _T_1228)
node _T_1239 = or(_T_1238, _T_1229)
node _T_1240 = or(_T_1239, _T_1230)
node _T_1241 = or(_T_1240, _T_1231)
node _T_1242 = or(_T_1241, _T_1232)
node _T_1243 = and(_T_1191, _T_1242)
node _T_1244 = or(UInt<1>(0h0), _T_1243)
node _T_1245 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1246 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1247 = and(_T_1245, _T_1246)
node _T_1248 = or(UInt<1>(0h0), _T_1247)
node _T_1249 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1250 = cvt(_T_1249)
node _T_1251 = and(_T_1250, asSInt(UInt<14>(0h2000)))
node _T_1252 = asSInt(_T_1251)
node _T_1253 = eq(_T_1252, asSInt(UInt<1>(0h0)))
node _T_1254 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1255 = cvt(_T_1254)
node _T_1256 = and(_T_1255, asSInt(UInt<13>(0h1000)))
node _T_1257 = asSInt(_T_1256)
node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0)))
node _T_1259 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1260 = cvt(_T_1259)
node _T_1261 = and(_T_1260, asSInt(UInt<18>(0h2f000)))
node _T_1262 = asSInt(_T_1261)
node _T_1263 = eq(_T_1262, asSInt(UInt<1>(0h0)))
node _T_1264 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1265 = cvt(_T_1264)
node _T_1266 = and(_T_1265, asSInt(UInt<17>(0h10000)))
node _T_1267 = asSInt(_T_1266)
node _T_1268 = eq(_T_1267, asSInt(UInt<1>(0h0)))
node _T_1269 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1270 = cvt(_T_1269)
node _T_1271 = and(_T_1270, asSInt(UInt<13>(0h1000)))
node _T_1272 = asSInt(_T_1271)
node _T_1273 = eq(_T_1272, asSInt(UInt<1>(0h0)))
node _T_1274 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1275 = cvt(_T_1274)
node _T_1276 = and(_T_1275, asSInt(UInt<27>(0h4000000)))
node _T_1277 = asSInt(_T_1276)
node _T_1278 = eq(_T_1277, asSInt(UInt<1>(0h0)))
node _T_1279 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1280 = cvt(_T_1279)
node _T_1281 = and(_T_1280, asSInt(UInt<13>(0h1000)))
node _T_1282 = asSInt(_T_1281)
node _T_1283 = eq(_T_1282, asSInt(UInt<1>(0h0)))
node _T_1284 = or(_T_1253, _T_1258)
node _T_1285 = or(_T_1284, _T_1263)
node _T_1286 = or(_T_1285, _T_1268)
node _T_1287 = or(_T_1286, _T_1273)
node _T_1288 = or(_T_1287, _T_1278)
node _T_1289 = or(_T_1288, _T_1283)
node _T_1290 = and(_T_1248, _T_1289)
node _T_1291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1292 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1293 = cvt(_T_1292)
node _T_1294 = and(_T_1293, asSInt(UInt<17>(0h10000)))
node _T_1295 = asSInt(_T_1294)
node _T_1296 = eq(_T_1295, asSInt(UInt<1>(0h0)))
node _T_1297 = and(_T_1291, _T_1296)
node _T_1298 = or(UInt<1>(0h0), _T_1290)
node _T_1299 = or(_T_1298, _T_1297)
node _T_1300 = and(_T_1244, _T_1299)
node _T_1301 = asUInt(reset)
node _T_1302 = eq(_T_1301, UInt<1>(0h0))
when _T_1302 :
node _T_1303 = eq(_T_1300, UInt<1>(0h0))
when _T_1303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1300, UInt<1>(0h1), "") : assert_41
node _T_1304 = asUInt(reset)
node _T_1305 = eq(_T_1304, UInt<1>(0h0))
when _T_1305 :
node _T_1306 = eq(source_ok, UInt<1>(0h0))
when _T_1306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1307 = asUInt(reset)
node _T_1308 = eq(_T_1307, UInt<1>(0h0))
when _T_1308 :
node _T_1309 = eq(is_aligned, UInt<1>(0h0))
when _T_1309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1310 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1311 = asUInt(reset)
node _T_1312 = eq(_T_1311, UInt<1>(0h0))
when _T_1312 :
node _T_1313 = eq(_T_1310, UInt<1>(0h0))
when _T_1313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1310, UInt<1>(0h1), "") : assert_44
node _T_1314 = eq(io.in.a.bits.mask, mask)
node _T_1315 = asUInt(reset)
node _T_1316 = eq(_T_1315, UInt<1>(0h0))
when _T_1316 :
node _T_1317 = eq(_T_1314, UInt<1>(0h0))
when _T_1317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1314, UInt<1>(0h1), "") : assert_45
node _T_1318 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1318 :
node _T_1319 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1320 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1321 = and(_T_1319, _T_1320)
node _T_1322 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_1323 = shr(io.in.a.bits.source, 2)
node _T_1324 = eq(_T_1323, UInt<4>(0h8))
node _T_1325 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_1326 = and(_T_1324, _T_1325)
node _T_1327 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_1328 = and(_T_1326, _T_1327)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_1329 = shr(io.in.a.bits.source, 2)
node _T_1330 = eq(_T_1329, UInt<4>(0h9))
node _T_1331 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_1332 = and(_T_1330, _T_1331)
node _T_1333 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_1334 = and(_T_1332, _T_1333)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_1335 = shr(io.in.a.bits.source, 2)
node _T_1336 = eq(_T_1335, UInt<4>(0ha))
node _T_1337 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_1338 = and(_T_1336, _T_1337)
node _T_1339 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_1340 = and(_T_1338, _T_1339)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_1341 = shr(io.in.a.bits.source, 2)
node _T_1342 = eq(_T_1341, UInt<4>(0hb))
node _T_1343 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_1344 = and(_T_1342, _T_1343)
node _T_1345 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_1346 = and(_T_1344, _T_1345)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 3, 0)
node _T_1347 = shr(io.in.a.bits.source, 4)
node _T_1348 = eq(_T_1347, UInt<1>(0h1))
node _T_1349 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_1350 = and(_T_1348, _T_1349)
node _T_1351 = leq(uncommonBits_64, UInt<4>(0hf))
node _T_1352 = and(_T_1350, _T_1351)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<4>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 3, 0)
node _T_1353 = shr(io.in.a.bits.source, 4)
node _T_1354 = eq(_T_1353, UInt<1>(0h0))
node _T_1355 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_1356 = and(_T_1354, _T_1355)
node _T_1357 = leq(uncommonBits_65, UInt<4>(0hf))
node _T_1358 = and(_T_1356, _T_1357)
node _T_1359 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1360 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1361 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_1362 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1363 = or(_T_1322, _T_1328)
node _T_1364 = or(_T_1363, _T_1334)
node _T_1365 = or(_T_1364, _T_1340)
node _T_1366 = or(_T_1365, _T_1346)
node _T_1367 = or(_T_1366, _T_1352)
node _T_1368 = or(_T_1367, _T_1358)
node _T_1369 = or(_T_1368, _T_1359)
node _T_1370 = or(_T_1369, _T_1360)
node _T_1371 = or(_T_1370, _T_1361)
node _T_1372 = or(_T_1371, _T_1362)
node _T_1373 = and(_T_1321, _T_1372)
node _T_1374 = or(UInt<1>(0h0), _T_1373)
node _T_1375 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1376 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1377 = and(_T_1375, _T_1376)
node _T_1378 = or(UInt<1>(0h0), _T_1377)
node _T_1379 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1380 = cvt(_T_1379)
node _T_1381 = and(_T_1380, asSInt(UInt<13>(0h1000)))
node _T_1382 = asSInt(_T_1381)
node _T_1383 = eq(_T_1382, asSInt(UInt<1>(0h0)))
node _T_1384 = and(_T_1378, _T_1383)
node _T_1385 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1386 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1387 = cvt(_T_1386)
node _T_1388 = and(_T_1387, asSInt(UInt<14>(0h2000)))
node _T_1389 = asSInt(_T_1388)
node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0)))
node _T_1391 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1392 = cvt(_T_1391)
node _T_1393 = and(_T_1392, asSInt(UInt<17>(0h10000)))
node _T_1394 = asSInt(_T_1393)
node _T_1395 = eq(_T_1394, asSInt(UInt<1>(0h0)))
node _T_1396 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1397 = cvt(_T_1396)
node _T_1398 = and(_T_1397, asSInt(UInt<18>(0h2f000)))
node _T_1399 = asSInt(_T_1398)
node _T_1400 = eq(_T_1399, asSInt(UInt<1>(0h0)))
node _T_1401 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1402 = cvt(_T_1401)
node _T_1403 = and(_T_1402, asSInt(UInt<17>(0h10000)))
node _T_1404 = asSInt(_T_1403)
node _T_1405 = eq(_T_1404, asSInt(UInt<1>(0h0)))
node _T_1406 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1407 = cvt(_T_1406)
node _T_1408 = and(_T_1407, asSInt(UInt<13>(0h1000)))
node _T_1409 = asSInt(_T_1408)
node _T_1410 = eq(_T_1409, asSInt(UInt<1>(0h0)))
node _T_1411 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1412 = cvt(_T_1411)
node _T_1413 = and(_T_1412, asSInt(UInt<27>(0h4000000)))
node _T_1414 = asSInt(_T_1413)
node _T_1415 = eq(_T_1414, asSInt(UInt<1>(0h0)))
node _T_1416 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1417 = cvt(_T_1416)
node _T_1418 = and(_T_1417, asSInt(UInt<13>(0h1000)))
node _T_1419 = asSInt(_T_1418)
node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0)))
node _T_1421 = or(_T_1390, _T_1395)
node _T_1422 = or(_T_1421, _T_1400)
node _T_1423 = or(_T_1422, _T_1405)
node _T_1424 = or(_T_1423, _T_1410)
node _T_1425 = or(_T_1424, _T_1415)
node _T_1426 = or(_T_1425, _T_1420)
node _T_1427 = and(_T_1385, _T_1426)
node _T_1428 = or(UInt<1>(0h0), _T_1384)
node _T_1429 = or(_T_1428, _T_1427)
node _T_1430 = and(_T_1374, _T_1429)
node _T_1431 = asUInt(reset)
node _T_1432 = eq(_T_1431, UInt<1>(0h0))
when _T_1432 :
node _T_1433 = eq(_T_1430, UInt<1>(0h0))
when _T_1433 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1430, UInt<1>(0h1), "") : assert_46
node _T_1434 = asUInt(reset)
node _T_1435 = eq(_T_1434, UInt<1>(0h0))
when _T_1435 :
node _T_1436 = eq(source_ok, UInt<1>(0h0))
when _T_1436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1437 = asUInt(reset)
node _T_1438 = eq(_T_1437, UInt<1>(0h0))
when _T_1438 :
node _T_1439 = eq(is_aligned, UInt<1>(0h0))
when _T_1439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1440 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1441 = asUInt(reset)
node _T_1442 = eq(_T_1441, UInt<1>(0h0))
when _T_1442 :
node _T_1443 = eq(_T_1440, UInt<1>(0h0))
when _T_1443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1440, UInt<1>(0h1), "") : assert_49
node _T_1444 = eq(io.in.a.bits.mask, mask)
node _T_1445 = asUInt(reset)
node _T_1446 = eq(_T_1445, UInt<1>(0h0))
when _T_1446 :
node _T_1447 = eq(_T_1444, UInt<1>(0h0))
when _T_1447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1444, UInt<1>(0h1), "") : assert_50
node _T_1448 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1449 = asUInt(reset)
node _T_1450 = eq(_T_1449, UInt<1>(0h0))
when _T_1450 :
node _T_1451 = eq(_T_1448, UInt<1>(0h0))
when _T_1451 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1448, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1452 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1453 = asUInt(reset)
node _T_1454 = eq(_T_1453, UInt<1>(0h0))
when _T_1454 :
node _T_1455 = eq(_T_1452, UInt<1>(0h0))
when _T_1455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1452, UInt<1>(0h1), "") : assert_52
node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<6>(0h30))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<4>(0h8))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_57 = shr(io.in.d.bits.source, 2)
node _source_ok_T_58 = eq(_source_ok_T_57, UInt<4>(0h9))
node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_63 = shr(io.in.d.bits.source, 2)
node _source_ok_T_64 = eq(_source_ok_T_63, UInt<4>(0ha))
node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_69 = shr(io.in.d.bits.source, 2)
node _source_ok_T_70 = eq(_source_ok_T_69, UInt<4>(0hb))
node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71)
node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 3, 0)
node _source_ok_T_75 = shr(io.in.d.bits.source, 4)
node _source_ok_T_76 = eq(_source_ok_T_75, UInt<1>(0h1))
node _source_ok_T_77 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_78 = and(_source_ok_T_76, _source_ok_T_77)
node _source_ok_T_79 = leq(source_ok_uncommonBits_10, UInt<4>(0hf))
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<4>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 3, 0)
node _source_ok_T_81 = shr(io.in.d.bits.source, 4)
node _source_ok_T_82 = eq(_source_ok_T_81, UInt<1>(0h0))
node _source_ok_T_83 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83)
node _source_ok_T_85 = leq(source_ok_uncommonBits_11, UInt<4>(0hf))
node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85)
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<7>(0h40))
node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<7>(0h41))
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<7>(0h42))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE_1 : UInt<1>[11]
connect _source_ok_WIRE_1[0], _source_ok_T_50
connect _source_ok_WIRE_1[1], _source_ok_T_56
connect _source_ok_WIRE_1[2], _source_ok_T_62
connect _source_ok_WIRE_1[3], _source_ok_T_68
connect _source_ok_WIRE_1[4], _source_ok_T_74
connect _source_ok_WIRE_1[5], _source_ok_T_80
connect _source_ok_WIRE_1[6], _source_ok_T_86
connect _source_ok_WIRE_1[7], _source_ok_T_87
connect _source_ok_WIRE_1[8], _source_ok_T_88
connect _source_ok_WIRE_1[9], _source_ok_T_89
connect _source_ok_WIRE_1[10], _source_ok_T_90
node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2])
node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3])
node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4])
node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9])
node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1456 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1456 :
node _T_1457 = asUInt(reset)
node _T_1458 = eq(_T_1457, UInt<1>(0h0))
when _T_1458 :
node _T_1459 = eq(source_ok_1, UInt<1>(0h0))
when _T_1459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1460 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1461 = asUInt(reset)
node _T_1462 = eq(_T_1461, UInt<1>(0h0))
when _T_1462 :
node _T_1463 = eq(_T_1460, UInt<1>(0h0))
when _T_1463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1460, UInt<1>(0h1), "") : assert_54
node _T_1464 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(_T_1464, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1464, UInt<1>(0h1), "") : assert_55
node _T_1468 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1469 = asUInt(reset)
node _T_1470 = eq(_T_1469, UInt<1>(0h0))
when _T_1470 :
node _T_1471 = eq(_T_1468, UInt<1>(0h0))
when _T_1471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1468, UInt<1>(0h1), "") : assert_56
node _T_1472 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1473 = asUInt(reset)
node _T_1474 = eq(_T_1473, UInt<1>(0h0))
when _T_1474 :
node _T_1475 = eq(_T_1472, UInt<1>(0h0))
when _T_1475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1472, UInt<1>(0h1), "") : assert_57
node _T_1476 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1476 :
node _T_1477 = asUInt(reset)
node _T_1478 = eq(_T_1477, UInt<1>(0h0))
when _T_1478 :
node _T_1479 = eq(source_ok_1, UInt<1>(0h0))
when _T_1479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1480 = asUInt(reset)
node _T_1481 = eq(_T_1480, UInt<1>(0h0))
when _T_1481 :
node _T_1482 = eq(sink_ok, UInt<1>(0h0))
when _T_1482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1483 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1484 = asUInt(reset)
node _T_1485 = eq(_T_1484, UInt<1>(0h0))
when _T_1485 :
node _T_1486 = eq(_T_1483, UInt<1>(0h0))
when _T_1486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1483, UInt<1>(0h1), "") : assert_60
node _T_1487 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1488 = asUInt(reset)
node _T_1489 = eq(_T_1488, UInt<1>(0h0))
when _T_1489 :
node _T_1490 = eq(_T_1487, UInt<1>(0h0))
when _T_1490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1487, UInt<1>(0h1), "") : assert_61
node _T_1491 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1492 = asUInt(reset)
node _T_1493 = eq(_T_1492, UInt<1>(0h0))
when _T_1493 :
node _T_1494 = eq(_T_1491, UInt<1>(0h0))
when _T_1494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1491, UInt<1>(0h1), "") : assert_62
node _T_1495 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1496 = asUInt(reset)
node _T_1497 = eq(_T_1496, UInt<1>(0h0))
when _T_1497 :
node _T_1498 = eq(_T_1495, UInt<1>(0h0))
when _T_1498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1495, UInt<1>(0h1), "") : assert_63
node _T_1499 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1500 = or(UInt<1>(0h1), _T_1499)
node _T_1501 = asUInt(reset)
node _T_1502 = eq(_T_1501, UInt<1>(0h0))
when _T_1502 :
node _T_1503 = eq(_T_1500, UInt<1>(0h0))
when _T_1503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1500, UInt<1>(0h1), "") : assert_64
node _T_1504 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1504 :
node _T_1505 = asUInt(reset)
node _T_1506 = eq(_T_1505, UInt<1>(0h0))
when _T_1506 :
node _T_1507 = eq(source_ok_1, UInt<1>(0h0))
when _T_1507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1508 = asUInt(reset)
node _T_1509 = eq(_T_1508, UInt<1>(0h0))
when _T_1509 :
node _T_1510 = eq(sink_ok, UInt<1>(0h0))
when _T_1510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1511 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1512 = asUInt(reset)
node _T_1513 = eq(_T_1512, UInt<1>(0h0))
when _T_1513 :
node _T_1514 = eq(_T_1511, UInt<1>(0h0))
when _T_1514 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1511, UInt<1>(0h1), "") : assert_67
node _T_1515 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1516 = asUInt(reset)
node _T_1517 = eq(_T_1516, UInt<1>(0h0))
when _T_1517 :
node _T_1518 = eq(_T_1515, UInt<1>(0h0))
when _T_1518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1515, UInt<1>(0h1), "") : assert_68
node _T_1519 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1520 = asUInt(reset)
node _T_1521 = eq(_T_1520, UInt<1>(0h0))
when _T_1521 :
node _T_1522 = eq(_T_1519, UInt<1>(0h0))
when _T_1522 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1519, UInt<1>(0h1), "") : assert_69
node _T_1523 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1524 = or(_T_1523, io.in.d.bits.corrupt)
node _T_1525 = asUInt(reset)
node _T_1526 = eq(_T_1525, UInt<1>(0h0))
when _T_1526 :
node _T_1527 = eq(_T_1524, UInt<1>(0h0))
when _T_1527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1524, UInt<1>(0h1), "") : assert_70
node _T_1528 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1529 = or(UInt<1>(0h1), _T_1528)
node _T_1530 = asUInt(reset)
node _T_1531 = eq(_T_1530, UInt<1>(0h0))
when _T_1531 :
node _T_1532 = eq(_T_1529, UInt<1>(0h0))
when _T_1532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1529, UInt<1>(0h1), "") : assert_71
node _T_1533 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1533 :
node _T_1534 = asUInt(reset)
node _T_1535 = eq(_T_1534, UInt<1>(0h0))
when _T_1535 :
node _T_1536 = eq(source_ok_1, UInt<1>(0h0))
when _T_1536 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1537 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1538 = asUInt(reset)
node _T_1539 = eq(_T_1538, UInt<1>(0h0))
when _T_1539 :
node _T_1540 = eq(_T_1537, UInt<1>(0h0))
when _T_1540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1537, UInt<1>(0h1), "") : assert_73
node _T_1541 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1542 = asUInt(reset)
node _T_1543 = eq(_T_1542, UInt<1>(0h0))
when _T_1543 :
node _T_1544 = eq(_T_1541, UInt<1>(0h0))
when _T_1544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1541, UInt<1>(0h1), "") : assert_74
node _T_1545 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1546 = or(UInt<1>(0h1), _T_1545)
node _T_1547 = asUInt(reset)
node _T_1548 = eq(_T_1547, UInt<1>(0h0))
when _T_1548 :
node _T_1549 = eq(_T_1546, UInt<1>(0h0))
when _T_1549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1546, UInt<1>(0h1), "") : assert_75
node _T_1550 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1550 :
node _T_1551 = asUInt(reset)
node _T_1552 = eq(_T_1551, UInt<1>(0h0))
when _T_1552 :
node _T_1553 = eq(source_ok_1, UInt<1>(0h0))
when _T_1553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1554 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1555 = asUInt(reset)
node _T_1556 = eq(_T_1555, UInt<1>(0h0))
when _T_1556 :
node _T_1557 = eq(_T_1554, UInt<1>(0h0))
when _T_1557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1554, UInt<1>(0h1), "") : assert_77
node _T_1558 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1559 = or(_T_1558, io.in.d.bits.corrupt)
node _T_1560 = asUInt(reset)
node _T_1561 = eq(_T_1560, UInt<1>(0h0))
when _T_1561 :
node _T_1562 = eq(_T_1559, UInt<1>(0h0))
when _T_1562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1559, UInt<1>(0h1), "") : assert_78
node _T_1563 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1564 = or(UInt<1>(0h1), _T_1563)
node _T_1565 = asUInt(reset)
node _T_1566 = eq(_T_1565, UInt<1>(0h0))
when _T_1566 :
node _T_1567 = eq(_T_1564, UInt<1>(0h0))
when _T_1567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1564, UInt<1>(0h1), "") : assert_79
node _T_1568 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1568 :
node _T_1569 = asUInt(reset)
node _T_1570 = eq(_T_1569, UInt<1>(0h0))
when _T_1570 :
node _T_1571 = eq(source_ok_1, UInt<1>(0h0))
when _T_1571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1572 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1573 = asUInt(reset)
node _T_1574 = eq(_T_1573, UInt<1>(0h0))
when _T_1574 :
node _T_1575 = eq(_T_1572, UInt<1>(0h0))
when _T_1575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1572, UInt<1>(0h1), "") : assert_81
node _T_1576 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1577 = asUInt(reset)
node _T_1578 = eq(_T_1577, UInt<1>(0h0))
when _T_1578 :
node _T_1579 = eq(_T_1576, UInt<1>(0h0))
when _T_1579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1576, UInt<1>(0h1), "") : assert_82
node _T_1580 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1581 = or(UInt<1>(0h1), _T_1580)
node _T_1582 = asUInt(reset)
node _T_1583 = eq(_T_1582, UInt<1>(0h0))
when _T_1583 :
node _T_1584 = eq(_T_1581, UInt<1>(0h0))
when _T_1584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1581, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<8>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1585 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1586 = asUInt(reset)
node _T_1587 = eq(_T_1586, UInt<1>(0h0))
when _T_1587 :
node _T_1588 = eq(_T_1585, UInt<1>(0h0))
when _T_1588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1585, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1589 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1590 = asUInt(reset)
node _T_1591 = eq(_T_1590, UInt<1>(0h0))
when _T_1591 :
node _T_1592 = eq(_T_1589, UInt<1>(0h0))
when _T_1592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1589, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1593 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1594 = asUInt(reset)
node _T_1595 = eq(_T_1594, UInt<1>(0h0))
when _T_1595 :
node _T_1596 = eq(_T_1593, UInt<1>(0h0))
when _T_1596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1593, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1597 = eq(a_first, UInt<1>(0h0))
node _T_1598 = and(io.in.a.valid, _T_1597)
when _T_1598 :
node _T_1599 = eq(io.in.a.bits.opcode, opcode)
node _T_1600 = asUInt(reset)
node _T_1601 = eq(_T_1600, UInt<1>(0h0))
when _T_1601 :
node _T_1602 = eq(_T_1599, UInt<1>(0h0))
when _T_1602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1599, UInt<1>(0h1), "") : assert_87
node _T_1603 = eq(io.in.a.bits.param, param)
node _T_1604 = asUInt(reset)
node _T_1605 = eq(_T_1604, UInt<1>(0h0))
when _T_1605 :
node _T_1606 = eq(_T_1603, UInt<1>(0h0))
when _T_1606 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1603, UInt<1>(0h1), "") : assert_88
node _T_1607 = eq(io.in.a.bits.size, size)
node _T_1608 = asUInt(reset)
node _T_1609 = eq(_T_1608, UInt<1>(0h0))
when _T_1609 :
node _T_1610 = eq(_T_1607, UInt<1>(0h0))
when _T_1610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1607, UInt<1>(0h1), "") : assert_89
node _T_1611 = eq(io.in.a.bits.source, source)
node _T_1612 = asUInt(reset)
node _T_1613 = eq(_T_1612, UInt<1>(0h0))
when _T_1613 :
node _T_1614 = eq(_T_1611, UInt<1>(0h0))
when _T_1614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1611, UInt<1>(0h1), "") : assert_90
node _T_1615 = eq(io.in.a.bits.address, address)
node _T_1616 = asUInt(reset)
node _T_1617 = eq(_T_1616, UInt<1>(0h0))
when _T_1617 :
node _T_1618 = eq(_T_1615, UInt<1>(0h0))
when _T_1618 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1615, UInt<1>(0h1), "") : assert_91
node _T_1619 = and(io.in.a.ready, io.in.a.valid)
node _T_1620 = and(_T_1619, a_first)
when _T_1620 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1621 = eq(d_first, UInt<1>(0h0))
node _T_1622 = and(io.in.d.valid, _T_1621)
when _T_1622 :
node _T_1623 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1624 = asUInt(reset)
node _T_1625 = eq(_T_1624, UInt<1>(0h0))
when _T_1625 :
node _T_1626 = eq(_T_1623, UInt<1>(0h0))
when _T_1626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1623, UInt<1>(0h1), "") : assert_92
node _T_1627 = eq(io.in.d.bits.param, param_1)
node _T_1628 = asUInt(reset)
node _T_1629 = eq(_T_1628, UInt<1>(0h0))
when _T_1629 :
node _T_1630 = eq(_T_1627, UInt<1>(0h0))
when _T_1630 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1627, UInt<1>(0h1), "") : assert_93
node _T_1631 = eq(io.in.d.bits.size, size_1)
node _T_1632 = asUInt(reset)
node _T_1633 = eq(_T_1632, UInt<1>(0h0))
when _T_1633 :
node _T_1634 = eq(_T_1631, UInt<1>(0h0))
when _T_1634 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1631, UInt<1>(0h1), "") : assert_94
node _T_1635 = eq(io.in.d.bits.source, source_1)
node _T_1636 = asUInt(reset)
node _T_1637 = eq(_T_1636, UInt<1>(0h0))
when _T_1637 :
node _T_1638 = eq(_T_1635, UInt<1>(0h0))
when _T_1638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1635, UInt<1>(0h1), "") : assert_95
node _T_1639 = eq(io.in.d.bits.sink, sink)
node _T_1640 = asUInt(reset)
node _T_1641 = eq(_T_1640, UInt<1>(0h0))
when _T_1641 :
node _T_1642 = eq(_T_1639, UInt<1>(0h0))
when _T_1642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1639, UInt<1>(0h1), "") : assert_96
node _T_1643 = eq(io.in.d.bits.denied, denied)
node _T_1644 = asUInt(reset)
node _T_1645 = eq(_T_1644, UInt<1>(0h0))
when _T_1645 :
node _T_1646 = eq(_T_1643, UInt<1>(0h0))
when _T_1646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1643, UInt<1>(0h1), "") : assert_97
node _T_1647 = and(io.in.d.ready, io.in.d.valid)
node _T_1648 = and(_T_1647, d_first)
when _T_1648 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes : UInt<1032>, clock, reset, UInt<1032>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<129>
connect a_set, UInt<129>(0h0)
wire a_set_wo_ready : UInt<129>
connect a_set_wo_ready, UInt<129>(0h0)
wire a_opcodes_set : UInt<516>
connect a_opcodes_set, UInt<516>(0h0)
wire a_sizes_set : UInt<1032>
connect a_sizes_set, UInt<1032>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1649 = and(io.in.a.valid, a_first_1)
node _T_1650 = and(_T_1649, UInt<1>(0h1))
when _T_1650 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1651 = and(io.in.a.ready, io.in.a.valid)
node _T_1652 = and(_T_1651, a_first_1)
node _T_1653 = and(_T_1652, UInt<1>(0h1))
when _T_1653 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1654 = dshr(inflight, io.in.a.bits.source)
node _T_1655 = bits(_T_1654, 0, 0)
node _T_1656 = eq(_T_1655, UInt<1>(0h0))
node _T_1657 = asUInt(reset)
node _T_1658 = eq(_T_1657, UInt<1>(0h0))
when _T_1658 :
node _T_1659 = eq(_T_1656, UInt<1>(0h0))
when _T_1659 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1656, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<129>
connect d_clr, UInt<129>(0h0)
wire d_clr_wo_ready : UInt<129>
connect d_clr_wo_ready, UInt<129>(0h0)
wire d_opcodes_clr : UInt<516>
connect d_opcodes_clr, UInt<516>(0h0)
wire d_sizes_clr : UInt<1032>
connect d_sizes_clr, UInt<1032>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1660 = and(io.in.d.valid, d_first_1)
node _T_1661 = and(_T_1660, UInt<1>(0h1))
node _T_1662 = eq(d_release_ack, UInt<1>(0h0))
node _T_1663 = and(_T_1661, _T_1662)
when _T_1663 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1664 = and(io.in.d.ready, io.in.d.valid)
node _T_1665 = and(_T_1664, d_first_1)
node _T_1666 = and(_T_1665, UInt<1>(0h1))
node _T_1667 = eq(d_release_ack, UInt<1>(0h0))
node _T_1668 = and(_T_1666, _T_1667)
when _T_1668 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1669 = and(io.in.d.valid, d_first_1)
node _T_1670 = and(_T_1669, UInt<1>(0h1))
node _T_1671 = eq(d_release_ack, UInt<1>(0h0))
node _T_1672 = and(_T_1670, _T_1671)
when _T_1672 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1673 = dshr(inflight, io.in.d.bits.source)
node _T_1674 = bits(_T_1673, 0, 0)
node _T_1675 = or(_T_1674, same_cycle_resp)
node _T_1676 = asUInt(reset)
node _T_1677 = eq(_T_1676, UInt<1>(0h0))
when _T_1677 :
node _T_1678 = eq(_T_1675, UInt<1>(0h0))
when _T_1678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1675, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1679 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1680 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1681 = or(_T_1679, _T_1680)
node _T_1682 = asUInt(reset)
node _T_1683 = eq(_T_1682, UInt<1>(0h0))
when _T_1683 :
node _T_1684 = eq(_T_1681, UInt<1>(0h0))
when _T_1684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1681, UInt<1>(0h1), "") : assert_100
node _T_1685 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1686 = asUInt(reset)
node _T_1687 = eq(_T_1686, UInt<1>(0h0))
when _T_1687 :
node _T_1688 = eq(_T_1685, UInt<1>(0h0))
when _T_1688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1685, UInt<1>(0h1), "") : assert_101
else :
node _T_1689 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1690 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1691 = or(_T_1689, _T_1690)
node _T_1692 = asUInt(reset)
node _T_1693 = eq(_T_1692, UInt<1>(0h0))
when _T_1693 :
node _T_1694 = eq(_T_1691, UInt<1>(0h0))
when _T_1694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1691, UInt<1>(0h1), "") : assert_102
node _T_1695 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1696 = asUInt(reset)
node _T_1697 = eq(_T_1696, UInt<1>(0h0))
when _T_1697 :
node _T_1698 = eq(_T_1695, UInt<1>(0h0))
when _T_1698 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1695, UInt<1>(0h1), "") : assert_103
node _T_1699 = and(io.in.d.valid, d_first_1)
node _T_1700 = and(_T_1699, a_first_1)
node _T_1701 = and(_T_1700, io.in.a.valid)
node _T_1702 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1703 = and(_T_1701, _T_1702)
node _T_1704 = eq(d_release_ack, UInt<1>(0h0))
node _T_1705 = and(_T_1703, _T_1704)
when _T_1705 :
node _T_1706 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1707 = or(_T_1706, io.in.a.ready)
node _T_1708 = asUInt(reset)
node _T_1709 = eq(_T_1708, UInt<1>(0h0))
when _T_1709 :
node _T_1710 = eq(_T_1707, UInt<1>(0h0))
when _T_1710 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1707, UInt<1>(0h1), "") : assert_104
node _T_1711 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1712 = orr(a_set_wo_ready)
node _T_1713 = eq(_T_1712, UInt<1>(0h0))
node _T_1714 = or(_T_1711, _T_1713)
node _T_1715 = asUInt(reset)
node _T_1716 = eq(_T_1715, UInt<1>(0h0))
when _T_1716 :
node _T_1717 = eq(_T_1714, UInt<1>(0h0))
when _T_1717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1714, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_42
node _T_1718 = orr(inflight)
node _T_1719 = eq(_T_1718, UInt<1>(0h0))
node _T_1720 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1721 = or(_T_1719, _T_1720)
node _T_1722 = lt(watchdog, plusarg_reader.out)
node _T_1723 = or(_T_1721, _T_1722)
node _T_1724 = asUInt(reset)
node _T_1725 = eq(_T_1724, UInt<1>(0h0))
when _T_1725 :
node _T_1726 = eq(_T_1723, UInt<1>(0h0))
when _T_1726 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1723, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1727 = and(io.in.a.ready, io.in.a.valid)
node _T_1728 = and(io.in.d.ready, io.in.d.valid)
node _T_1729 = or(_T_1727, _T_1728)
when _T_1729 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes_1 : UInt<1032>, clock, reset, UInt<1032>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<8>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<129>
connect c_set, UInt<129>(0h0)
wire c_set_wo_ready : UInt<129>
connect c_set_wo_ready, UInt<129>(0h0)
wire c_opcodes_set : UInt<516>
connect c_opcodes_set, UInt<516>(0h0)
wire c_sizes_set : UInt<1032>
connect c_sizes_set, UInt<1032>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<8>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1730 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1731 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1732 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1733 = and(_T_1731, _T_1732)
node _T_1734 = and(_T_1730, _T_1733)
when _T_1734 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<8>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1735 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1736 = and(_T_1735, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<8>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1737 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1738 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1739 = and(_T_1737, _T_1738)
node _T_1740 = and(_T_1736, _T_1739)
when _T_1740 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<8>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1741 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1742 = bits(_T_1741, 0, 0)
node _T_1743 = eq(_T_1742, UInt<1>(0h0))
node _T_1744 = asUInt(reset)
node _T_1745 = eq(_T_1744, UInt<1>(0h0))
when _T_1745 :
node _T_1746 = eq(_T_1743, UInt<1>(0h0))
when _T_1746 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1743, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<129>
connect d_clr_1, UInt<129>(0h0)
wire d_clr_wo_ready_1 : UInt<129>
connect d_clr_wo_ready_1, UInt<129>(0h0)
wire d_opcodes_clr_1 : UInt<516>
connect d_opcodes_clr_1, UInt<516>(0h0)
wire d_sizes_clr_1 : UInt<1032>
connect d_sizes_clr_1, UInt<1032>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1747 = and(io.in.d.valid, d_first_2)
node _T_1748 = and(_T_1747, UInt<1>(0h1))
node _T_1749 = and(_T_1748, d_release_ack_1)
when _T_1749 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1750 = and(io.in.d.ready, io.in.d.valid)
node _T_1751 = and(_T_1750, d_first_2)
node _T_1752 = and(_T_1751, UInt<1>(0h1))
node _T_1753 = and(_T_1752, d_release_ack_1)
when _T_1753 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1754 = and(io.in.d.valid, d_first_2)
node _T_1755 = and(_T_1754, UInt<1>(0h1))
node _T_1756 = and(_T_1755, d_release_ack_1)
when _T_1756 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1757 = dshr(inflight_1, io.in.d.bits.source)
node _T_1758 = bits(_T_1757, 0, 0)
node _T_1759 = or(_T_1758, same_cycle_resp_1)
node _T_1760 = asUInt(reset)
node _T_1761 = eq(_T_1760, UInt<1>(0h0))
when _T_1761 :
node _T_1762 = eq(_T_1759, UInt<1>(0h0))
when _T_1762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1759, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<8>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1763 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1764 = asUInt(reset)
node _T_1765 = eq(_T_1764, UInt<1>(0h0))
when _T_1765 :
node _T_1766 = eq(_T_1763, UInt<1>(0h0))
when _T_1766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1763, UInt<1>(0h1), "") : assert_109
else :
node _T_1767 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1768 = asUInt(reset)
node _T_1769 = eq(_T_1768, UInt<1>(0h0))
when _T_1769 :
node _T_1770 = eq(_T_1767, UInt<1>(0h0))
when _T_1770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1767, UInt<1>(0h1), "") : assert_110
node _T_1771 = and(io.in.d.valid, d_first_2)
node _T_1772 = and(_T_1771, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<8>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1773 = and(_T_1772, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1774 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1775 = and(_T_1773, _T_1774)
node _T_1776 = and(_T_1775, d_release_ack_1)
node _T_1777 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1778 = and(_T_1776, _T_1777)
when _T_1778 :
node _T_1779 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<8>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1780 = or(_T_1779, _WIRE_27.ready)
node _T_1781 = asUInt(reset)
node _T_1782 = eq(_T_1781, UInt<1>(0h0))
when _T_1782 :
node _T_1783 = eq(_T_1780, UInt<1>(0h0))
when _T_1783 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1780, UInt<1>(0h1), "") : assert_111
node _T_1784 = orr(c_set_wo_ready)
when _T_1784 :
node _T_1785 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1786 = asUInt(reset)
node _T_1787 = eq(_T_1786, UInt<1>(0h0))
when _T_1787 :
node _T_1788 = eq(_T_1785, UInt<1>(0h0))
when _T_1788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1785, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_43
node _T_1789 = orr(inflight_1)
node _T_1790 = eq(_T_1789, UInt<1>(0h0))
node _T_1791 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1792 = or(_T_1790, _T_1791)
node _T_1793 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1794 = or(_T_1792, _T_1793)
node _T_1795 = asUInt(reset)
node _T_1796 = eq(_T_1795, UInt<1>(0h0))
when _T_1796 :
node _T_1797 = eq(_T_1794, UInt<1>(0h0))
when _T_1797 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1794, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<8>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1798 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1799 = and(io.in.d.ready, io.in.d.valid)
node _T_1800 = or(_T_1798, _T_1799)
when _T_1800 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_21( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [1031:0] c_sizes_set = 1032'h0; // @[Monitor.scala:741:34]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 6'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 6'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 6'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31]
wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_52 = _source_ok_T_51 == 6'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = _source_ok_T_57 == 6'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = _source_ok_T_63 == 6'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_70 = _source_ok_T_69 == 6'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_75 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_81 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7]
wire _source_ok_T_76 = _source_ok_T_75 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_80; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_82 = _source_ok_T_81 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1727 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1727; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1727; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1800 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1800; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1800; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1800; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [1031:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [1031:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [1031:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [1031:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1031:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1653 = _T_1727 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1653 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1653 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1653 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1653 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1653 ? _a_sizes_set_T_1[1031:0] : 1032'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [1031:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1699 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1699 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1668 = _T_1800 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1668 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1668 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1668 ? _d_sizes_clr_T_5[1031:0] : 1032'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [1031:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [1031:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [1031:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [1031:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [1031:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [1031:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [1031:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1031:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [1031:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1771 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1771 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1753 = _T_1800 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1753 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1753 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1753 ? _d_sizes_clr_T_11[1031:0] : 1032'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [1031:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [1031:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_4 :
input clock : Clock
input reset : Reset
output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}}
wire nodeIn : UInt<1>[1]
invalidate nodeIn[0]
wire nodeOut : { sync : UInt<1>[1]}
invalidate nodeOut.sync[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
inst reg of AsyncResetRegVec_w1_i0_4
connect reg.clock, clock
connect reg.reset, reset
connect reg.io.d, nodeIn[0]
connect reg.io.en, UInt<1>(0h1)
node _T = bits(reg.io.q, 0, 0)
connect nodeOut.sync[0], _T | module IntSyncCrossingSource_n1x1_4( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset // @[Crossing.scala:41:9]
);
wire auto_in_0 = 1'h0; // @[Crossing.scala:41:9]
wire auto_out_sync_0 = 1'h0; // @[Crossing.scala:41:9]
wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
AsyncResetRegVec_w1_i0_4 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset)
); // @[AsyncResetReg.scala:86:21]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_251 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_268
connect io_out_sink_valid.clock, clock
connect io_out_sink_valid.reset, reset
connect io_out_sink_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_251( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_268 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_19 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_return : UInt<3>, vc_free : UInt<3>}}
wire _in_flight_WIRE : UInt<1>[3]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
regreset in_flight : UInt<1>[3], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_13 = and(_T_11, _T_12)
node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_20 = and(_T_18, _T_19)
node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_34 = and(_T_32, _T_33)
node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_38 = and(_T_36, _T_37)
node _T_39 = or(_T_17, _T_24)
node _T_40 = or(_T_39, _T_31)
node _T_41 = or(_T_40, _T_38)
node _T_42 = or(_T_10, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_42, UInt<1>(0h1), "") : assert_2
node _T_46 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_47 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_48 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_49 = and(_T_47, _T_48)
node _T_50 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
node _T_52 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_53 = and(_T_51, _T_52)
node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_58 = and(_T_56, _T_57)
node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_60 = and(_T_58, _T_59)
node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_62 = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h0))
node _T_63 = and(_T_61, _T_62)
node _T_64 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_65 = and(_T_63, _T_64)
node _T_66 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_67 = and(_T_65, _T_66)
node _T_68 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_69 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _T_70 = and(_T_68, _T_69)
node _T_71 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_72 = and(_T_70, _T_71)
node _T_73 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_74 = and(_T_72, _T_73)
node _T_75 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_76 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_77 = and(_T_75, _T_76)
node _T_78 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_79 = and(_T_77, _T_78)
node _T_80 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_81 = and(_T_79, _T_80)
node _T_82 = or(_T_53, _T_60)
node _T_83 = or(_T_82, _T_67)
node _T_84 = or(_T_83, _T_74)
node _T_85 = or(_T_84, _T_81)
node _T_86 = or(_T_46, _T_85)
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_86, UInt<1>(0h1), "") : assert_3 | module NoCMonitor_19( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 2'h0; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_64 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}}
wire _in_flight_WIRE : UInt<1>[8]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
connect _in_flight_WIRE[6], UInt<1>(0h0)
connect _in_flight_WIRE[7], UInt<1>(0h0)
regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_13 = and(_T_11, _T_12)
node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_20 = and(_T_18, _T_19)
node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_34 = and(_T_32, _T_33)
node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_38 = and(_T_36, _T_37)
node _T_39 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_40 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_41 = and(_T_39, _T_40)
node _T_42 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_45 = and(_T_43, _T_44)
node _T_46 = or(_T_17, _T_24)
node _T_47 = or(_T_46, _T_31)
node _T_48 = or(_T_47, _T_38)
node _T_49 = or(_T_48, _T_45)
node _T_50 = or(_T_10, _T_49)
node _T_51 = asUInt(reset)
node _T_52 = eq(_T_51, UInt<1>(0h0))
when _T_52 :
node _T_53 = eq(_T_50, UInt<1>(0h0))
when _T_53 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_50, UInt<1>(0h1), "") : assert_2
node _T_54 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_57 = and(_T_55, _T_56)
node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_59 = and(_T_57, _T_58)
node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_61 = and(_T_59, _T_60)
node _T_62 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_63 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_64 = and(_T_62, _T_63)
node _T_65 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_66 = and(_T_64, _T_65)
node _T_67 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_68 = and(_T_66, _T_67)
node _T_69 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_70 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_71 = and(_T_69, _T_70)
node _T_72 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_73 = and(_T_71, _T_72)
node _T_74 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_75 = and(_T_73, _T_74)
node _T_76 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_77 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_78 = and(_T_76, _T_77)
node _T_79 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_80 = and(_T_78, _T_79)
node _T_81 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_84 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_85 = and(_T_83, _T_84)
node _T_86 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_87 = and(_T_85, _T_86)
node _T_88 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_89 = and(_T_87, _T_88)
node _T_90 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_91 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_92 = and(_T_90, _T_91)
node _T_93 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_94 = and(_T_92, _T_93)
node _T_95 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_98 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_99 = and(_T_97, _T_98)
node _T_100 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_101 = and(_T_99, _T_100)
node _T_102 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_103 = and(_T_101, _T_102)
node _T_104 = or(_T_61, _T_68)
node _T_105 = or(_T_104, _T_75)
node _T_106 = or(_T_105, _T_82)
node _T_107 = or(_T_106, _T_89)
node _T_108 = or(_T_107, _T_96)
node _T_109 = or(_T_108, _T_103)
node _T_110 = or(_T_54, _T_109)
node _T_111 = asUInt(reset)
node _T_112 = eq(_T_111, UInt<1>(0h0))
when _T_112 :
node _T_113 = eq(_T_110, UInt<1>(0h0))
when _T_113 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_110, UInt<1>(0h1), "") : assert_3
node _T_114 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_115 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_116 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_119 = and(_T_117, _T_118)
node _T_120 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_121 = and(_T_119, _T_120)
node _T_122 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_123 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_124 = and(_T_122, _T_123)
node _T_125 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_126 = and(_T_124, _T_125)
node _T_127 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_128 = and(_T_126, _T_127)
node _T_129 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_130 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_131 = and(_T_129, _T_130)
node _T_132 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_135 = and(_T_133, _T_134)
node _T_136 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_137 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_138 = and(_T_136, _T_137)
node _T_139 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_142 = and(_T_140, _T_141)
node _T_143 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_144 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_145 = and(_T_143, _T_144)
node _T_146 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_149 = and(_T_147, _T_148)
node _T_150 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_151 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_152 = and(_T_150, _T_151)
node _T_153 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_156 = and(_T_154, _T_155)
node _T_157 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_158 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_159 = and(_T_157, _T_158)
node _T_160 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_163 = and(_T_161, _T_162)
node _T_164 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_165 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_166 = and(_T_164, _T_165)
node _T_167 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_170 = and(_T_168, _T_169)
node _T_171 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_172 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_173 = and(_T_171, _T_172)
node _T_174 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_177 = and(_T_175, _T_176)
node _T_178 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_179 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_180 = and(_T_178, _T_179)
node _T_181 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_184 = and(_T_182, _T_183)
node _T_185 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_186 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_187 = and(_T_185, _T_186)
node _T_188 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_191 = and(_T_189, _T_190)
node _T_192 = or(_T_121, _T_128)
node _T_193 = or(_T_192, _T_135)
node _T_194 = or(_T_193, _T_142)
node _T_195 = or(_T_194, _T_149)
node _T_196 = or(_T_195, _T_156)
node _T_197 = or(_T_196, _T_163)
node _T_198 = or(_T_197, _T_170)
node _T_199 = or(_T_198, _T_177)
node _T_200 = or(_T_199, _T_184)
node _T_201 = or(_T_200, _T_191)
node _T_202 = or(_T_114, _T_201)
node _T_203 = asUInt(reset)
node _T_204 = eq(_T_203, UInt<1>(0h0))
when _T_204 :
node _T_205 = eq(_T_202, UInt<1>(0h0))
when _T_205 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_202, UInt<1>(0h1), "") : assert_4
node _T_206 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_207 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_208 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_209 = and(_T_207, _T_208)
node _T_210 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_211 = and(_T_209, _T_210)
node _T_212 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_213 = and(_T_211, _T_212)
node _T_214 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_215 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_216 = and(_T_214, _T_215)
node _T_217 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_218 = and(_T_216, _T_217)
node _T_219 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_220 = and(_T_218, _T_219)
node _T_221 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_222 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_223 = and(_T_221, _T_222)
node _T_224 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_225 = and(_T_223, _T_224)
node _T_226 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_227 = and(_T_225, _T_226)
node _T_228 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_229 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_230 = and(_T_228, _T_229)
node _T_231 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_232 = and(_T_230, _T_231)
node _T_233 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_234 = and(_T_232, _T_233)
node _T_235 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_236 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_237 = and(_T_235, _T_236)
node _T_238 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_239 = and(_T_237, _T_238)
node _T_240 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_241 = and(_T_239, _T_240)
node _T_242 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_243 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_244 = and(_T_242, _T_243)
node _T_245 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_246 = and(_T_244, _T_245)
node _T_247 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_248 = and(_T_246, _T_247)
node _T_249 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_250 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_251 = and(_T_249, _T_250)
node _T_252 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_253 = and(_T_251, _T_252)
node _T_254 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_255 = and(_T_253, _T_254)
node _T_256 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_257 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_258 = and(_T_256, _T_257)
node _T_259 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_260 = and(_T_258, _T_259)
node _T_261 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_262 = and(_T_260, _T_261)
node _T_263 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_264 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_265 = and(_T_263, _T_264)
node _T_266 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_267 = and(_T_265, _T_266)
node _T_268 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_269 = and(_T_267, _T_268)
node _T_270 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_271 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_272 = and(_T_270, _T_271)
node _T_273 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_274 = and(_T_272, _T_273)
node _T_275 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_276 = and(_T_274, _T_275)
node _T_277 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_278 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_279 = and(_T_277, _T_278)
node _T_280 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_281 = and(_T_279, _T_280)
node _T_282 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_285 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_286 = and(_T_284, _T_285)
node _T_287 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_288 = and(_T_286, _T_287)
node _T_289 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_292 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_295 = and(_T_293, _T_294)
node _T_296 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_297 = and(_T_295, _T_296)
node _T_298 = or(_T_213, _T_220)
node _T_299 = or(_T_298, _T_227)
node _T_300 = or(_T_299, _T_234)
node _T_301 = or(_T_300, _T_241)
node _T_302 = or(_T_301, _T_248)
node _T_303 = or(_T_302, _T_255)
node _T_304 = or(_T_303, _T_262)
node _T_305 = or(_T_304, _T_269)
node _T_306 = or(_T_305, _T_276)
node _T_307 = or(_T_306, _T_283)
node _T_308 = or(_T_307, _T_290)
node _T_309 = or(_T_308, _T_297)
node _T_310 = or(_T_206, _T_309)
node _T_311 = asUInt(reset)
node _T_312 = eq(_T_311, UInt<1>(0h0))
when _T_312 :
node _T_313 = eq(_T_310, UInt<1>(0h0))
when _T_313 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_310, UInt<1>(0h1), "") : assert_5
node _T_314 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_315 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_316 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_317 = and(_T_315, _T_316)
node _T_318 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_319 = and(_T_317, _T_318)
node _T_320 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_323 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_326 = and(_T_324, _T_325)
node _T_327 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_328 = and(_T_326, _T_327)
node _T_329 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_330 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_331 = and(_T_329, _T_330)
node _T_332 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_333 = and(_T_331, _T_332)
node _T_334 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_335 = and(_T_333, _T_334)
node _T_336 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_337 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_338 = and(_T_336, _T_337)
node _T_339 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_340 = and(_T_338, _T_339)
node _T_341 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_342 = and(_T_340, _T_341)
node _T_343 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_344 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_345 = and(_T_343, _T_344)
node _T_346 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_347 = and(_T_345, _T_346)
node _T_348 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_349 = and(_T_347, _T_348)
node _T_350 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_351 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_352 = and(_T_350, _T_351)
node _T_353 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_354 = and(_T_352, _T_353)
node _T_355 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_356 = and(_T_354, _T_355)
node _T_357 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_358 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_359 = and(_T_357, _T_358)
node _T_360 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_361 = and(_T_359, _T_360)
node _T_362 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_363 = and(_T_361, _T_362)
node _T_364 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_365 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_366 = and(_T_364, _T_365)
node _T_367 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_368 = and(_T_366, _T_367)
node _T_369 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_370 = and(_T_368, _T_369)
node _T_371 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_372 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_373 = and(_T_371, _T_372)
node _T_374 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_375 = and(_T_373, _T_374)
node _T_376 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_377 = and(_T_375, _T_376)
node _T_378 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_379 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_380 = and(_T_378, _T_379)
node _T_381 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_382 = and(_T_380, _T_381)
node _T_383 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_384 = and(_T_382, _T_383)
node _T_385 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_386 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_387 = and(_T_385, _T_386)
node _T_388 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_389 = and(_T_387, _T_388)
node _T_390 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_391 = and(_T_389, _T_390)
node _T_392 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_393 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_394 = and(_T_392, _T_393)
node _T_395 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_398 = and(_T_396, _T_397)
node _T_399 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_400 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_401 = and(_T_399, _T_400)
node _T_402 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_405 = and(_T_403, _T_404)
node _T_406 = or(_T_321, _T_328)
node _T_407 = or(_T_406, _T_335)
node _T_408 = or(_T_407, _T_342)
node _T_409 = or(_T_408, _T_349)
node _T_410 = or(_T_409, _T_356)
node _T_411 = or(_T_410, _T_363)
node _T_412 = or(_T_411, _T_370)
node _T_413 = or(_T_412, _T_377)
node _T_414 = or(_T_413, _T_384)
node _T_415 = or(_T_414, _T_391)
node _T_416 = or(_T_415, _T_398)
node _T_417 = or(_T_416, _T_405)
node _T_418 = or(_T_314, _T_417)
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_418, UInt<1>(0h1), "") : assert_6
node _T_422 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6))
node _T_423 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_424 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_425 = and(_T_423, _T_424)
node _T_426 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_427 = and(_T_425, _T_426)
node _T_428 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_429 = and(_T_427, _T_428)
node _T_430 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_431 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_432 = and(_T_430, _T_431)
node _T_433 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_436 = and(_T_434, _T_435)
node _T_437 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_438 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_439 = and(_T_437, _T_438)
node _T_440 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_443 = and(_T_441, _T_442)
node _T_444 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_445 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_446 = and(_T_444, _T_445)
node _T_447 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_448 = and(_T_446, _T_447)
node _T_449 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_450 = and(_T_448, _T_449)
node _T_451 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_452 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_453 = and(_T_451, _T_452)
node _T_454 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_455 = and(_T_453, _T_454)
node _T_456 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_457 = and(_T_455, _T_456)
node _T_458 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_459 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_460 = and(_T_458, _T_459)
node _T_461 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_462 = and(_T_460, _T_461)
node _T_463 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_464 = and(_T_462, _T_463)
node _T_465 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_466 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_467 = and(_T_465, _T_466)
node _T_468 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_469 = and(_T_467, _T_468)
node _T_470 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_473 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_476 = and(_T_474, _T_475)
node _T_477 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_478 = and(_T_476, _T_477)
node _T_479 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_480 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_481 = and(_T_479, _T_480)
node _T_482 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_483 = and(_T_481, _T_482)
node _T_484 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_485 = and(_T_483, _T_484)
node _T_486 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_487 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_488 = and(_T_486, _T_487)
node _T_489 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_490 = and(_T_488, _T_489)
node _T_491 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_492 = and(_T_490, _T_491)
node _T_493 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_494 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_495 = and(_T_493, _T_494)
node _T_496 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_497 = and(_T_495, _T_496)
node _T_498 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_499 = and(_T_497, _T_498)
node _T_500 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_501 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_502 = and(_T_500, _T_501)
node _T_503 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_504 = and(_T_502, _T_503)
node _T_505 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_506 = and(_T_504, _T_505)
node _T_507 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_508 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_509 = and(_T_507, _T_508)
node _T_510 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_511 = and(_T_509, _T_510)
node _T_512 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_513 = and(_T_511, _T_512)
node _T_514 = or(_T_429, _T_436)
node _T_515 = or(_T_514, _T_443)
node _T_516 = or(_T_515, _T_450)
node _T_517 = or(_T_516, _T_457)
node _T_518 = or(_T_517, _T_464)
node _T_519 = or(_T_518, _T_471)
node _T_520 = or(_T_519, _T_478)
node _T_521 = or(_T_520, _T_485)
node _T_522 = or(_T_521, _T_492)
node _T_523 = or(_T_522, _T_499)
node _T_524 = or(_T_523, _T_506)
node _T_525 = or(_T_524, _T_513)
node _T_526 = or(_T_422, _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7
assert(clock, _T_526, UInt<1>(0h1), "") : assert_7
node _T_530 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7))
node _T_531 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_532 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_533 = and(_T_531, _T_532)
node _T_534 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_535 = and(_T_533, _T_534)
node _T_536 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_537 = and(_T_535, _T_536)
node _T_538 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_539 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_540 = and(_T_538, _T_539)
node _T_541 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_542 = and(_T_540, _T_541)
node _T_543 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_544 = and(_T_542, _T_543)
node _T_545 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_546 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_547 = and(_T_545, _T_546)
node _T_548 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_549 = and(_T_547, _T_548)
node _T_550 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_551 = and(_T_549, _T_550)
node _T_552 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h3))
node _T_553 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_554 = and(_T_552, _T_553)
node _T_555 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_556 = and(_T_554, _T_555)
node _T_557 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_558 = and(_T_556, _T_557)
node _T_559 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_560 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_561 = and(_T_559, _T_560)
node _T_562 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_563 = and(_T_561, _T_562)
node _T_564 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_565 = and(_T_563, _T_564)
node _T_566 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_567 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_568 = and(_T_566, _T_567)
node _T_569 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_570 = and(_T_568, _T_569)
node _T_571 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_572 = and(_T_570, _T_571)
node _T_573 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_574 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_575 = and(_T_573, _T_574)
node _T_576 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_577 = and(_T_575, _T_576)
node _T_578 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_579 = and(_T_577, _T_578)
node _T_580 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_581 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_582 = and(_T_580, _T_581)
node _T_583 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_584 = and(_T_582, _T_583)
node _T_585 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_586 = and(_T_584, _T_585)
node _T_587 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_588 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_589 = and(_T_587, _T_588)
node _T_590 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_591 = and(_T_589, _T_590)
node _T_592 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_593 = and(_T_591, _T_592)
node _T_594 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_595 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_596 = and(_T_594, _T_595)
node _T_597 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_598 = and(_T_596, _T_597)
node _T_599 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_600 = and(_T_598, _T_599)
node _T_601 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_602 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_603 = and(_T_601, _T_602)
node _T_604 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_605 = and(_T_603, _T_604)
node _T_606 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_607 = and(_T_605, _T_606)
node _T_608 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_609 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd))
node _T_610 = and(_T_608, _T_609)
node _T_611 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_612 = and(_T_610, _T_611)
node _T_613 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_614 = and(_T_612, _T_613)
node _T_615 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_616 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_617 = and(_T_615, _T_616)
node _T_618 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_619 = and(_T_617, _T_618)
node _T_620 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_621 = and(_T_619, _T_620)
node _T_622 = or(_T_537, _T_544)
node _T_623 = or(_T_622, _T_551)
node _T_624 = or(_T_623, _T_558)
node _T_625 = or(_T_624, _T_565)
node _T_626 = or(_T_625, _T_572)
node _T_627 = or(_T_626, _T_579)
node _T_628 = or(_T_627, _T_586)
node _T_629 = or(_T_628, _T_593)
node _T_630 = or(_T_629, _T_600)
node _T_631 = or(_T_630, _T_607)
node _T_632 = or(_T_631, _T_614)
node _T_633 = or(_T_632, _T_621)
node _T_634 = or(_T_530, _T_633)
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_T_634, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8
assert(clock, _T_634, UInt<1>(0h1), "") : assert_8 | module NoCMonitor_64( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_58 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<10>(0h200)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = and(_T_19, _T_24)
node _T_26 = or(UInt<1>(0h0), _T_25)
node _T_27 = and(_T_18, _T_26)
node _T_28 = asUInt(reset)
node _T_29 = eq(_T_28, UInt<1>(0h0))
when _T_29 :
node _T_30 = eq(_T_27, UInt<1>(0h0))
when _T_30 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_27, UInt<1>(0h1), "") : assert_2
node _T_31 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_32 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_33 = and(_T_31, _T_32)
node _T_34 = or(UInt<1>(0h0), _T_33)
node _T_35 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<10>(0h200)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = and(_T_34, _T_39)
node _T_41 = or(UInt<1>(0h0), _T_40)
node _T_42 = and(UInt<1>(0h0), _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_42, UInt<1>(0h1), "") : assert_3
node _T_46 = asUInt(reset)
node _T_47 = eq(_T_46, UInt<1>(0h0))
when _T_47 :
node _T_48 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_48 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_49 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_50 = asUInt(reset)
node _T_51 = eq(_T_50, UInt<1>(0h0))
when _T_51 :
node _T_52 = eq(_T_49, UInt<1>(0h0))
when _T_52 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_49, UInt<1>(0h1), "") : assert_5
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(is_aligned, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_56 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_57 = asUInt(reset)
node _T_58 = eq(_T_57, UInt<1>(0h0))
when _T_58 :
node _T_59 = eq(_T_56, UInt<1>(0h0))
when _T_59 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_56, UInt<1>(0h1), "") : assert_7
node _T_60 = not(io.in.a.bits.mask)
node _T_61 = eq(_T_60, UInt<1>(0h0))
node _T_62 = asUInt(reset)
node _T_63 = eq(_T_62, UInt<1>(0h0))
when _T_63 :
node _T_64 = eq(_T_61, UInt<1>(0h0))
when _T_64 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_61, UInt<1>(0h1), "") : assert_8
node _T_65 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_69 :
node _T_70 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_71 = and(UInt<1>(0h0), _T_70)
node _T_72 = or(UInt<1>(0h0), _T_71)
node _T_73 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<10>(0h200)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = and(_T_73, _T_78)
node _T_80 = or(UInt<1>(0h0), _T_79)
node _T_81 = and(_T_72, _T_80)
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_81, UInt<1>(0h1), "") : assert_10
node _T_85 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_86 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_87 = and(_T_85, _T_86)
node _T_88 = or(UInt<1>(0h0), _T_87)
node _T_89 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_90 = cvt(_T_89)
node _T_91 = and(_T_90, asSInt(UInt<10>(0h200)))
node _T_92 = asSInt(_T_91)
node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0)))
node _T_94 = and(_T_88, _T_93)
node _T_95 = or(UInt<1>(0h0), _T_94)
node _T_96 = and(UInt<1>(0h0), _T_95)
node _T_97 = asUInt(reset)
node _T_98 = eq(_T_97, UInt<1>(0h0))
when _T_98 :
node _T_99 = eq(_T_96, UInt<1>(0h0))
when _T_99 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_96, UInt<1>(0h1), "") : assert_11
node _T_100 = asUInt(reset)
node _T_101 = eq(_T_100, UInt<1>(0h0))
when _T_101 :
node _T_102 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_103 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_104 = asUInt(reset)
node _T_105 = eq(_T_104, UInt<1>(0h0))
when _T_105 :
node _T_106 = eq(_T_103, UInt<1>(0h0))
when _T_106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_103, UInt<1>(0h1), "") : assert_13
node _T_107 = asUInt(reset)
node _T_108 = eq(_T_107, UInt<1>(0h0))
when _T_108 :
node _T_109 = eq(is_aligned, UInt<1>(0h0))
when _T_109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_110 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_111 = asUInt(reset)
node _T_112 = eq(_T_111, UInt<1>(0h0))
when _T_112 :
node _T_113 = eq(_T_110, UInt<1>(0h0))
when _T_113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_110, UInt<1>(0h1), "") : assert_15
node _T_114 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_114, UInt<1>(0h1), "") : assert_16
node _T_118 = not(io.in.a.bits.mask)
node _T_119 = eq(_T_118, UInt<1>(0h0))
node _T_120 = asUInt(reset)
node _T_121 = eq(_T_120, UInt<1>(0h0))
when _T_121 :
node _T_122 = eq(_T_119, UInt<1>(0h0))
when _T_122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_119, UInt<1>(0h1), "") : assert_17
node _T_123 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_124 = asUInt(reset)
node _T_125 = eq(_T_124, UInt<1>(0h0))
when _T_125 :
node _T_126 = eq(_T_123, UInt<1>(0h0))
when _T_126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_123, UInt<1>(0h1), "") : assert_18
node _T_127 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_127 :
node _T_128 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_129 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_130 = and(_T_128, _T_129)
node _T_131 = or(UInt<1>(0h0), _T_130)
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_131, UInt<1>(0h1), "") : assert_19
node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_136 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_137 = and(_T_135, _T_136)
node _T_138 = or(UInt<1>(0h0), _T_137)
node _T_139 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<10>(0h200)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = and(_T_138, _T_143)
node _T_145 = or(UInt<1>(0h0), _T_144)
node _T_146 = asUInt(reset)
node _T_147 = eq(_T_146, UInt<1>(0h0))
when _T_147 :
node _T_148 = eq(_T_145, UInt<1>(0h0))
when _T_148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_145, UInt<1>(0h1), "") : assert_20
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(is_aligned, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_155 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_155, UInt<1>(0h1), "") : assert_23
node _T_159 = eq(io.in.a.bits.mask, mask)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_159, UInt<1>(0h1), "") : assert_24
node _T_163 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_164 = asUInt(reset)
node _T_165 = eq(_T_164, UInt<1>(0h0))
when _T_165 :
node _T_166 = eq(_T_163, UInt<1>(0h0))
when _T_166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_163, UInt<1>(0h1), "") : assert_25
node _T_167 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_167 :
node _T_168 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_169 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_170 = and(_T_168, _T_169)
node _T_171 = or(UInt<1>(0h0), _T_170)
node _T_172 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_173 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_174 = and(_T_172, _T_173)
node _T_175 = or(UInt<1>(0h0), _T_174)
node _T_176 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_177 = cvt(_T_176)
node _T_178 = and(_T_177, asSInt(UInt<10>(0h200)))
node _T_179 = asSInt(_T_178)
node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = and(_T_175, _T_180)
node _T_182 = or(UInt<1>(0h0), _T_181)
node _T_183 = and(_T_171, _T_182)
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_183, UInt<1>(0h1), "") : assert_26
node _T_187 = asUInt(reset)
node _T_188 = eq(_T_187, UInt<1>(0h0))
when _T_188 :
node _T_189 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(is_aligned, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_193 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_194 = asUInt(reset)
node _T_195 = eq(_T_194, UInt<1>(0h0))
when _T_195 :
node _T_196 = eq(_T_193, UInt<1>(0h0))
when _T_196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_193, UInt<1>(0h1), "") : assert_29
node _T_197 = eq(io.in.a.bits.mask, mask)
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_197, UInt<1>(0h1), "") : assert_30
node _T_201 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_201 :
node _T_202 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_203 = and(UInt<1>(0h0), _T_202)
node _T_204 = or(UInt<1>(0h0), _T_203)
node _T_205 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_206 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_207 = and(_T_205, _T_206)
node _T_208 = or(UInt<1>(0h0), _T_207)
node _T_209 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_210 = cvt(_T_209)
node _T_211 = and(_T_210, asSInt(UInt<10>(0h200)))
node _T_212 = asSInt(_T_211)
node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0)))
node _T_214 = and(_T_208, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(_T_204, _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_216, UInt<1>(0h1), "") : assert_31
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_223 = asUInt(reset)
node _T_224 = eq(_T_223, UInt<1>(0h0))
when _T_224 :
node _T_225 = eq(is_aligned, UInt<1>(0h0))
when _T_225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_226 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(_T_226, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_226, UInt<1>(0h1), "") : assert_34
node _T_230 = not(mask)
node _T_231 = and(io.in.a.bits.mask, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_232, UInt<1>(0h1), "") : assert_35
node _T_236 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_236 :
node _T_237 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_238 = and(UInt<1>(0h0), _T_237)
node _T_239 = or(UInt<1>(0h0), _T_238)
node _T_240 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_241 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_242 = cvt(_T_241)
node _T_243 = and(_T_242, asSInt(UInt<10>(0h200)))
node _T_244 = asSInt(_T_243)
node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0)))
node _T_246 = and(_T_240, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = and(_T_239, _T_247)
node _T_249 = asUInt(reset)
node _T_250 = eq(_T_249, UInt<1>(0h0))
when _T_250 :
node _T_251 = eq(_T_248, UInt<1>(0h0))
when _T_251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_248, UInt<1>(0h1), "") : assert_36
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(is_aligned, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_258 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_258, UInt<1>(0h1), "") : assert_39
node _T_262 = eq(io.in.a.bits.mask, mask)
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_T_262, UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_262, UInt<1>(0h1), "") : assert_40
node _T_266 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_266 :
node _T_267 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_268 = and(UInt<1>(0h0), _T_267)
node _T_269 = or(UInt<1>(0h0), _T_268)
node _T_270 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_271 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_272 = cvt(_T_271)
node _T_273 = and(_T_272, asSInt(UInt<10>(0h200)))
node _T_274 = asSInt(_T_273)
node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0)))
node _T_276 = and(_T_270, _T_275)
node _T_277 = or(UInt<1>(0h0), _T_276)
node _T_278 = and(_T_269, _T_277)
node _T_279 = asUInt(reset)
node _T_280 = eq(_T_279, UInt<1>(0h0))
when _T_280 :
node _T_281 = eq(_T_278, UInt<1>(0h0))
when _T_281 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_278, UInt<1>(0h1), "") : assert_41
node _T_282 = asUInt(reset)
node _T_283 = eq(_T_282, UInt<1>(0h0))
when _T_283 :
node _T_284 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_284 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(is_aligned, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_288 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_289 = asUInt(reset)
node _T_290 = eq(_T_289, UInt<1>(0h0))
when _T_290 :
node _T_291 = eq(_T_288, UInt<1>(0h0))
when _T_291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_288, UInt<1>(0h1), "") : assert_44
node _T_292 = eq(io.in.a.bits.mask, mask)
node _T_293 = asUInt(reset)
node _T_294 = eq(_T_293, UInt<1>(0h0))
when _T_294 :
node _T_295 = eq(_T_292, UInt<1>(0h0))
when _T_295 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_292, UInt<1>(0h1), "") : assert_45
node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_296 :
node _T_297 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_298 = and(UInt<1>(0h0), _T_297)
node _T_299 = or(UInt<1>(0h0), _T_298)
node _T_300 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_301 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_302 = cvt(_T_301)
node _T_303 = and(_T_302, asSInt(UInt<10>(0h200)))
node _T_304 = asSInt(_T_303)
node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0)))
node _T_306 = and(_T_300, _T_305)
node _T_307 = or(UInt<1>(0h0), _T_306)
node _T_308 = and(_T_299, _T_307)
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_308, UInt<1>(0h1), "") : assert_46
node _T_312 = asUInt(reset)
node _T_313 = eq(_T_312, UInt<1>(0h0))
when _T_313 :
node _T_314 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_315 = asUInt(reset)
node _T_316 = eq(_T_315, UInt<1>(0h0))
when _T_316 :
node _T_317 = eq(is_aligned, UInt<1>(0h0))
when _T_317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_318 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_319 = asUInt(reset)
node _T_320 = eq(_T_319, UInt<1>(0h0))
when _T_320 :
node _T_321 = eq(_T_318, UInt<1>(0h0))
when _T_321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_318, UInt<1>(0h1), "") : assert_49
node _T_322 = eq(io.in.a.bits.mask, mask)
node _T_323 = asUInt(reset)
node _T_324 = eq(_T_323, UInt<1>(0h0))
when _T_324 :
node _T_325 = eq(_T_322, UInt<1>(0h0))
when _T_325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_322, UInt<1>(0h1), "") : assert_50
node _T_326 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_327 = asUInt(reset)
node _T_328 = eq(_T_327, UInt<1>(0h0))
when _T_328 :
node _T_329 = eq(_T_326, UInt<1>(0h0))
when _T_329 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_326, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_330 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_331 = asUInt(reset)
node _T_332 = eq(_T_331, UInt<1>(0h0))
when _T_332 :
node _T_333 = eq(_T_330, UInt<1>(0h0))
when _T_333 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_330, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_334 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_334 :
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_338 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_338, UInt<1>(0h1), "") : assert_54
node _T_342 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_343 = asUInt(reset)
node _T_344 = eq(_T_343, UInt<1>(0h0))
when _T_344 :
node _T_345 = eq(_T_342, UInt<1>(0h0))
when _T_345 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_342, UInt<1>(0h1), "") : assert_55
node _T_346 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_347 = asUInt(reset)
node _T_348 = eq(_T_347, UInt<1>(0h0))
when _T_348 :
node _T_349 = eq(_T_346, UInt<1>(0h0))
when _T_349 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_346, UInt<1>(0h1), "") : assert_56
node _T_350 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(_T_350, UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_350, UInt<1>(0h1), "") : assert_57
node _T_354 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_354 :
node _T_355 = asUInt(reset)
node _T_356 = eq(_T_355, UInt<1>(0h0))
when _T_356 :
node _T_357 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(sink_ok, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_361 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_361, UInt<1>(0h1), "") : assert_60
node _T_365 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_366 = asUInt(reset)
node _T_367 = eq(_T_366, UInt<1>(0h0))
when _T_367 :
node _T_368 = eq(_T_365, UInt<1>(0h0))
when _T_368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_365, UInt<1>(0h1), "") : assert_61
node _T_369 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(_T_369, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_369, UInt<1>(0h1), "") : assert_62
node _T_373 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_373, UInt<1>(0h1), "") : assert_63
node _T_377 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_378 = or(UInt<1>(0h1), _T_377)
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_378, UInt<1>(0h1), "") : assert_64
node _T_382 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_382 :
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(sink_ok, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_389 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_389, UInt<1>(0h1), "") : assert_67
node _T_393 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_393, UInt<1>(0h1), "") : assert_68
node _T_397 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_397, UInt<1>(0h1), "") : assert_69
node _T_401 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_402 = or(_T_401, io.in.d.bits.corrupt)
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_402, UInt<1>(0h1), "") : assert_70
node _T_406 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_407 = or(UInt<1>(0h1), _T_406)
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(_T_407, UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_407, UInt<1>(0h1), "") : assert_71
node _T_411 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_411 :
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_415 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(_T_415, UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_415, UInt<1>(0h1), "") : assert_73
node _T_419 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_420 = asUInt(reset)
node _T_421 = eq(_T_420, UInt<1>(0h0))
when _T_421 :
node _T_422 = eq(_T_419, UInt<1>(0h0))
when _T_422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_419, UInt<1>(0h1), "") : assert_74
node _T_423 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_424 = or(UInt<1>(0h1), _T_423)
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(_T_424, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_424, UInt<1>(0h1), "") : assert_75
node _T_428 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_428 :
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_432 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_432, UInt<1>(0h1), "") : assert_77
node _T_436 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_437 = or(_T_436, io.in.d.bits.corrupt)
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_T_437, UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_437, UInt<1>(0h1), "") : assert_78
node _T_441 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_442 = or(UInt<1>(0h1), _T_441)
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_442, UInt<1>(0h1), "") : assert_79
node _T_446 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_450 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(_T_450, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_450, UInt<1>(0h1), "") : assert_81
node _T_454 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_454, UInt<1>(0h1), "") : assert_82
node _T_458 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_459 = or(UInt<1>(0h1), _T_458)
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_459, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_463 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_463, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_467 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_468 = asUInt(reset)
node _T_469 = eq(_T_468, UInt<1>(0h0))
when _T_469 :
node _T_470 = eq(_T_467, UInt<1>(0h0))
when _T_470 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_467, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_471 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_471, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_475 = eq(a_first, UInt<1>(0h0))
node _T_476 = and(io.in.a.valid, _T_475)
when _T_476 :
node _T_477 = eq(io.in.a.bits.opcode, opcode)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_477, UInt<1>(0h1), "") : assert_87
node _T_481 = eq(io.in.a.bits.param, param)
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_481, UInt<1>(0h1), "") : assert_88
node _T_485 = eq(io.in.a.bits.size, size)
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_485, UInt<1>(0h1), "") : assert_89
node _T_489 = eq(io.in.a.bits.source, source)
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_T_489, UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_489, UInt<1>(0h1), "") : assert_90
node _T_493 = eq(io.in.a.bits.address, address)
node _T_494 = asUInt(reset)
node _T_495 = eq(_T_494, UInt<1>(0h0))
when _T_495 :
node _T_496 = eq(_T_493, UInt<1>(0h0))
when _T_496 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_493, UInt<1>(0h1), "") : assert_91
node _T_497 = and(io.in.a.ready, io.in.a.valid)
node _T_498 = and(_T_497, a_first)
when _T_498 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_499 = eq(d_first, UInt<1>(0h0))
node _T_500 = and(io.in.d.valid, _T_499)
when _T_500 :
node _T_501 = eq(io.in.d.bits.opcode, opcode_1)
node _T_502 = asUInt(reset)
node _T_503 = eq(_T_502, UInt<1>(0h0))
when _T_503 :
node _T_504 = eq(_T_501, UInt<1>(0h0))
when _T_504 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_501, UInt<1>(0h1), "") : assert_92
node _T_505 = eq(io.in.d.bits.param, param_1)
node _T_506 = asUInt(reset)
node _T_507 = eq(_T_506, UInt<1>(0h0))
when _T_507 :
node _T_508 = eq(_T_505, UInt<1>(0h0))
when _T_508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_505, UInt<1>(0h1), "") : assert_93
node _T_509 = eq(io.in.d.bits.size, size_1)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_509, UInt<1>(0h1), "") : assert_94
node _T_513 = eq(io.in.d.bits.source, source_1)
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_T_513, UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_513, UInt<1>(0h1), "") : assert_95
node _T_517 = eq(io.in.d.bits.sink, sink)
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_517, UInt<1>(0h1), "") : assert_96
node _T_521 = eq(io.in.d.bits.denied, denied)
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_521, UInt<1>(0h1), "") : assert_97
node _T_525 = and(io.in.d.ready, io.in.d.valid)
node _T_526 = and(_T_525, d_first)
when _T_526 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_527 = and(io.in.a.valid, a_first_1)
node _T_528 = and(_T_527, UInt<1>(0h1))
when _T_528 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_529 = and(io.in.a.ready, io.in.a.valid)
node _T_530 = and(_T_529, a_first_1)
node _T_531 = and(_T_530, UInt<1>(0h1))
when _T_531 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_532 = dshr(inflight, io.in.a.bits.source)
node _T_533 = bits(_T_532, 0, 0)
node _T_534 = eq(_T_533, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_534, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_538 = and(io.in.d.valid, d_first_1)
node _T_539 = and(_T_538, UInt<1>(0h1))
node _T_540 = eq(d_release_ack, UInt<1>(0h0))
node _T_541 = and(_T_539, _T_540)
when _T_541 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_542 = and(io.in.d.ready, io.in.d.valid)
node _T_543 = and(_T_542, d_first_1)
node _T_544 = and(_T_543, UInt<1>(0h1))
node _T_545 = eq(d_release_ack, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
when _T_546 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_547 = and(io.in.d.valid, d_first_1)
node _T_548 = and(_T_547, UInt<1>(0h1))
node _T_549 = eq(d_release_ack, UInt<1>(0h0))
node _T_550 = and(_T_548, _T_549)
when _T_550 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_551 = dshr(inflight, io.in.d.bits.source)
node _T_552 = bits(_T_551, 0, 0)
node _T_553 = or(_T_552, same_cycle_resp)
node _T_554 = asUInt(reset)
node _T_555 = eq(_T_554, UInt<1>(0h0))
when _T_555 :
node _T_556 = eq(_T_553, UInt<1>(0h0))
when _T_556 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_553, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_557 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_558 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_559 = or(_T_557, _T_558)
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_559, UInt<1>(0h1), "") : assert_100
node _T_563 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_564 = asUInt(reset)
node _T_565 = eq(_T_564, UInt<1>(0h0))
when _T_565 :
node _T_566 = eq(_T_563, UInt<1>(0h0))
when _T_566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_563, UInt<1>(0h1), "") : assert_101
else :
node _T_567 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_568 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_569 = or(_T_567, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_569, UInt<1>(0h1), "") : assert_102
node _T_573 = eq(io.in.d.bits.size, a_size_lookup)
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_T_573, UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_573, UInt<1>(0h1), "") : assert_103
node _T_577 = and(io.in.d.valid, d_first_1)
node _T_578 = and(_T_577, a_first_1)
node _T_579 = and(_T_578, io.in.a.valid)
node _T_580 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_581 = and(_T_579, _T_580)
node _T_582 = eq(d_release_ack, UInt<1>(0h0))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
node _T_584 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_585 = or(_T_584, io.in.a.ready)
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(_T_585, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_585, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_117
node _T_589 = orr(inflight)
node _T_590 = eq(_T_589, UInt<1>(0h0))
node _T_591 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_592 = or(_T_590, _T_591)
node _T_593 = lt(watchdog, plusarg_reader.out)
node _T_594 = or(_T_592, _T_593)
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_594, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_598 = and(io.in.a.ready, io.in.a.valid)
node _T_599 = and(io.in.d.ready, io.in.d.valid)
node _T_600 = or(_T_598, _T_599)
when _T_600 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_601 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_602 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_603 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_604 = and(_T_602, _T_603)
node _T_605 = and(_T_601, _T_604)
when _T_605 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_606 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_607 = and(_T_606, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_608 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_609 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_610 = and(_T_608, _T_609)
node _T_611 = and(_T_607, _T_610)
when _T_611 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_612 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_613 = bits(_T_612, 0, 0)
node _T_614 = eq(_T_613, UInt<1>(0h0))
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_614, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_618 = and(io.in.d.valid, d_first_2)
node _T_619 = and(_T_618, UInt<1>(0h1))
node _T_620 = and(_T_619, d_release_ack_1)
when _T_620 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_621 = and(io.in.d.ready, io.in.d.valid)
node _T_622 = and(_T_621, d_first_2)
node _T_623 = and(_T_622, UInt<1>(0h1))
node _T_624 = and(_T_623, d_release_ack_1)
when _T_624 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_625 = and(io.in.d.valid, d_first_2)
node _T_626 = and(_T_625, UInt<1>(0h1))
node _T_627 = and(_T_626, d_release_ack_1)
when _T_627 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_628 = dshr(inflight_1, io.in.d.bits.source)
node _T_629 = bits(_T_628, 0, 0)
node _T_630 = or(_T_629, same_cycle_resp_1)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_630, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_634 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_T_634, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_634, UInt<1>(0h1), "") : assert_108
else :
node _T_638 = eq(io.in.d.bits.size, c_size_lookup)
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_638, UInt<1>(0h1), "") : assert_109
node _T_642 = and(io.in.d.valid, d_first_2)
node _T_643 = and(_T_642, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_644 = and(_T_643, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_645 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_646 = and(_T_644, _T_645)
node _T_647 = and(_T_646, d_release_ack_1)
node _T_648 = eq(c_probe_ack, UInt<1>(0h0))
node _T_649 = and(_T_647, _T_648)
when _T_649 :
node _T_650 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_651 = or(_T_650, _WIRE_23.ready)
node _T_652 = asUInt(reset)
node _T_653 = eq(_T_652, UInt<1>(0h0))
when _T_653 :
node _T_654 = eq(_T_651, UInt<1>(0h0))
when _T_654 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_651, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_118
node _T_655 = orr(inflight_1)
node _T_656 = eq(_T_655, UInt<1>(0h0))
node _T_657 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_658 = or(_T_656, _T_657)
node _T_659 = lt(watchdog_1, plusarg_reader_1.out)
node _T_660 = or(_T_658, _T_659)
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(_T_660, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:679:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_660, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_664 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_665 = and(io.in.d.ready, io.in.d.valid)
node _T_666 = or(_T_664, _T_665)
when _T_666 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_58( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46]
wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7]
wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7]
wire [3:0] mask = 4'hF; // @[Misc.scala:222:10]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74]
wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61]
wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12]
wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27]
wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire _T_598 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_598; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_598; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [8:0] address; // @[Monitor.scala:391:22]
wire _T_666 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_666; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_666; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_666; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_528 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_528; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_528; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_598 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46]
wire _T_577 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_577 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = _T_666 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21]
assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_642 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_642 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = _T_666 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21]
assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_63 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h30))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<4>(0h8))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<4>(0h9))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<4>(0ha))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<4>(0hb))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 3)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h2))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 3)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h1))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0)
node _source_ok_T_37 = shr(io.in.a.bits.source, 3)
node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0))
node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<3>(0h7))
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_42
connect _source_ok_WIRE[8], _source_ok_T_43
node _source_ok_T_44 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[2])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[3])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[4])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[5])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[6])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_50, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<4>(0h8))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<4>(0h9))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<4>(0ha))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<4>(0hb))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_64 = shr(io.in.a.bits.source, 3)
node _T_65 = eq(_T_64, UInt<2>(0h2))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<3>(0h7))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0)
node _T_77 = shr(io.in.a.bits.source, 3)
node _T_78 = eq(_T_77, UInt<1>(0h1))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<3>(0h7))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0)
node _T_90 = shr(io.in.a.bits.source, 3)
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_93 = and(_T_91, _T_92)
node _T_94 = leq(uncommonBits_6, UInt<3>(0h7))
node _T_95 = and(_T_93, _T_94)
node _T_96 = eq(_T_95, UInt<1>(0h0))
node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_98 = cvt(_T_97)
node _T_99 = and(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = asSInt(_T_99)
node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0)))
node _T_102 = or(_T_96, _T_101)
node _T_103 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<1>(0h0)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = or(_T_104, _T_109)
node _T_111 = and(_T_11, _T_24)
node _T_112 = and(_T_111, _T_37)
node _T_113 = and(_T_112, _T_50)
node _T_114 = and(_T_113, _T_63)
node _T_115 = and(_T_114, _T_76)
node _T_116 = and(_T_115, _T_89)
node _T_117 = and(_T_116, _T_102)
node _T_118 = and(_T_117, _T_110)
node _T_119 = asUInt(reset)
node _T_120 = eq(_T_119, UInt<1>(0h0))
when _T_120 :
node _T_121 = eq(_T_118, UInt<1>(0h0))
when _T_121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_118, UInt<1>(0h1), "") : assert_1
node _T_122 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_122 :
node _T_123 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_124 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_125 = and(_T_123, _T_124)
node _T_126 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_127 = shr(io.in.a.bits.source, 2)
node _T_128 = eq(_T_127, UInt<4>(0h8))
node _T_129 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_130 = and(_T_128, _T_129)
node _T_131 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_132 = and(_T_130, _T_131)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_133 = shr(io.in.a.bits.source, 2)
node _T_134 = eq(_T_133, UInt<4>(0h9))
node _T_135 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_136 = and(_T_134, _T_135)
node _T_137 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_138 = and(_T_136, _T_137)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_139 = shr(io.in.a.bits.source, 2)
node _T_140 = eq(_T_139, UInt<4>(0ha))
node _T_141 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_142 = and(_T_140, _T_141)
node _T_143 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_144 = and(_T_142, _T_143)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_145 = shr(io.in.a.bits.source, 2)
node _T_146 = eq(_T_145, UInt<4>(0hb))
node _T_147 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_148 = and(_T_146, _T_147)
node _T_149 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_150 = and(_T_148, _T_149)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0)
node _T_151 = shr(io.in.a.bits.source, 3)
node _T_152 = eq(_T_151, UInt<2>(0h2))
node _T_153 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_154 = and(_T_152, _T_153)
node _T_155 = leq(uncommonBits_11, UInt<3>(0h7))
node _T_156 = and(_T_154, _T_155)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0)
node _T_157 = shr(io.in.a.bits.source, 3)
node _T_158 = eq(_T_157, UInt<1>(0h1))
node _T_159 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_160 = and(_T_158, _T_159)
node _T_161 = leq(uncommonBits_12, UInt<3>(0h7))
node _T_162 = and(_T_160, _T_161)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0)
node _T_163 = shr(io.in.a.bits.source, 3)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_166 = and(_T_164, _T_165)
node _T_167 = leq(uncommonBits_13, UInt<3>(0h7))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_170 = or(_T_126, _T_132)
node _T_171 = or(_T_170, _T_138)
node _T_172 = or(_T_171, _T_144)
node _T_173 = or(_T_172, _T_150)
node _T_174 = or(_T_173, _T_156)
node _T_175 = or(_T_174, _T_162)
node _T_176 = or(_T_175, _T_168)
node _T_177 = or(_T_176, _T_169)
node _T_178 = and(_T_125, _T_177)
node _T_179 = or(UInt<1>(0h0), _T_178)
node _T_180 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_181 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_182 = cvt(_T_181)
node _T_183 = and(_T_182, asSInt(UInt<13>(0h1000)))
node _T_184 = asSInt(_T_183)
node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0)))
node _T_186 = and(_T_180, _T_185)
node _T_187 = or(UInt<1>(0h0), _T_186)
node _T_188 = and(_T_179, _T_187)
node _T_189 = asUInt(reset)
node _T_190 = eq(_T_189, UInt<1>(0h0))
when _T_190 :
node _T_191 = eq(_T_188, UInt<1>(0h0))
when _T_191 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_188, UInt<1>(0h1), "") : assert_2
node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_193 = shr(io.in.a.bits.source, 2)
node _T_194 = eq(_T_193, UInt<4>(0h8))
node _T_195 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_196 = and(_T_194, _T_195)
node _T_197 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_199 = shr(io.in.a.bits.source, 2)
node _T_200 = eq(_T_199, UInt<4>(0h9))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_204 = and(_T_202, _T_203)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_205 = shr(io.in.a.bits.source, 2)
node _T_206 = eq(_T_205, UInt<4>(0ha))
node _T_207 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_208 = and(_T_206, _T_207)
node _T_209 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_210 = and(_T_208, _T_209)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_211 = shr(io.in.a.bits.source, 2)
node _T_212 = eq(_T_211, UInt<4>(0hb))
node _T_213 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_214 = and(_T_212, _T_213)
node _T_215 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_216 = and(_T_214, _T_215)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0)
node _T_217 = shr(io.in.a.bits.source, 3)
node _T_218 = eq(_T_217, UInt<2>(0h2))
node _T_219 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_220 = and(_T_218, _T_219)
node _T_221 = leq(uncommonBits_18, UInt<3>(0h7))
node _T_222 = and(_T_220, _T_221)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0)
node _T_223 = shr(io.in.a.bits.source, 3)
node _T_224 = eq(_T_223, UInt<1>(0h1))
node _T_225 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_226 = and(_T_224, _T_225)
node _T_227 = leq(uncommonBits_19, UInt<3>(0h7))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0)
node _T_229 = shr(io.in.a.bits.source, 3)
node _T_230 = eq(_T_229, UInt<1>(0h0))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_20, UInt<3>(0h7))
node _T_234 = and(_T_232, _T_233)
node _T_235 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_192
connect _WIRE[1], _T_198
connect _WIRE[2], _T_204
connect _WIRE[3], _T_210
connect _WIRE[4], _T_216
connect _WIRE[5], _T_222
connect _WIRE[6], _T_228
connect _WIRE[7], _T_234
connect _WIRE[8], _T_235
node _T_236 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_237 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_238 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_239 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_240 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_241 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_242 = mux(_WIRE[5], _T_236, UInt<1>(0h0))
node _T_243 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_244 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_245 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_246 = or(_T_237, _T_238)
node _T_247 = or(_T_246, _T_239)
node _T_248 = or(_T_247, _T_240)
node _T_249 = or(_T_248, _T_241)
node _T_250 = or(_T_249, _T_242)
node _T_251 = or(_T_250, _T_243)
node _T_252 = or(_T_251, _T_244)
node _T_253 = or(_T_252, _T_245)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_253
node _T_254 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_255 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_256 = and(_T_254, _T_255)
node _T_257 = or(UInt<1>(0h0), _T_256)
node _T_258 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_259 = cvt(_T_258)
node _T_260 = and(_T_259, asSInt(UInt<13>(0h1000)))
node _T_261 = asSInt(_T_260)
node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0)))
node _T_263 = and(_T_257, _T_262)
node _T_264 = or(UInt<1>(0h0), _T_263)
node _T_265 = and(_WIRE_1, _T_264)
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(_T_265, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_265, UInt<1>(0h1), "") : assert_3
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(source_ok, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_272 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_273 = asUInt(reset)
node _T_274 = eq(_T_273, UInt<1>(0h0))
when _T_274 :
node _T_275 = eq(_T_272, UInt<1>(0h0))
when _T_275 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_272, UInt<1>(0h1), "") : assert_5
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(is_aligned, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_279 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_280 = asUInt(reset)
node _T_281 = eq(_T_280, UInt<1>(0h0))
when _T_281 :
node _T_282 = eq(_T_279, UInt<1>(0h0))
when _T_282 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_279, UInt<1>(0h1), "") : assert_7
node _T_283 = not(io.in.a.bits.mask)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_284, UInt<1>(0h1), "") : assert_8
node _T_288 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_289 = asUInt(reset)
node _T_290 = eq(_T_289, UInt<1>(0h0))
when _T_290 :
node _T_291 = eq(_T_288, UInt<1>(0h0))
when _T_291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_288, UInt<1>(0h1), "") : assert_9
node _T_292 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_292 :
node _T_293 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_294 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_295 = and(_T_293, _T_294)
node _T_296 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_297 = shr(io.in.a.bits.source, 2)
node _T_298 = eq(_T_297, UInt<4>(0h8))
node _T_299 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_300 = and(_T_298, _T_299)
node _T_301 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_302 = and(_T_300, _T_301)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_303 = shr(io.in.a.bits.source, 2)
node _T_304 = eq(_T_303, UInt<4>(0h9))
node _T_305 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_306 = and(_T_304, _T_305)
node _T_307 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_308 = and(_T_306, _T_307)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_309 = shr(io.in.a.bits.source, 2)
node _T_310 = eq(_T_309, UInt<4>(0ha))
node _T_311 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_312 = and(_T_310, _T_311)
node _T_313 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_314 = and(_T_312, _T_313)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_315 = shr(io.in.a.bits.source, 2)
node _T_316 = eq(_T_315, UInt<4>(0hb))
node _T_317 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_318 = and(_T_316, _T_317)
node _T_319 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0)
node _T_321 = shr(io.in.a.bits.source, 3)
node _T_322 = eq(_T_321, UInt<2>(0h2))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_25, UInt<3>(0h7))
node _T_326 = and(_T_324, _T_325)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0)
node _T_327 = shr(io.in.a.bits.source, 3)
node _T_328 = eq(_T_327, UInt<1>(0h1))
node _T_329 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_330 = and(_T_328, _T_329)
node _T_331 = leq(uncommonBits_26, UInt<3>(0h7))
node _T_332 = and(_T_330, _T_331)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0)
node _T_333 = shr(io.in.a.bits.source, 3)
node _T_334 = eq(_T_333, UInt<1>(0h0))
node _T_335 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_336 = and(_T_334, _T_335)
node _T_337 = leq(uncommonBits_27, UInt<3>(0h7))
node _T_338 = and(_T_336, _T_337)
node _T_339 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_340 = or(_T_296, _T_302)
node _T_341 = or(_T_340, _T_308)
node _T_342 = or(_T_341, _T_314)
node _T_343 = or(_T_342, _T_320)
node _T_344 = or(_T_343, _T_326)
node _T_345 = or(_T_344, _T_332)
node _T_346 = or(_T_345, _T_338)
node _T_347 = or(_T_346, _T_339)
node _T_348 = and(_T_295, _T_347)
node _T_349 = or(UInt<1>(0h0), _T_348)
node _T_350 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_351 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_352 = cvt(_T_351)
node _T_353 = and(_T_352, asSInt(UInt<13>(0h1000)))
node _T_354 = asSInt(_T_353)
node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0)))
node _T_356 = and(_T_350, _T_355)
node _T_357 = or(UInt<1>(0h0), _T_356)
node _T_358 = and(_T_349, _T_357)
node _T_359 = asUInt(reset)
node _T_360 = eq(_T_359, UInt<1>(0h0))
when _T_360 :
node _T_361 = eq(_T_358, UInt<1>(0h0))
when _T_361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_358, UInt<1>(0h1), "") : assert_10
node _T_362 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_363 = shr(io.in.a.bits.source, 2)
node _T_364 = eq(_T_363, UInt<4>(0h8))
node _T_365 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_366 = and(_T_364, _T_365)
node _T_367 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_368 = and(_T_366, _T_367)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_369 = shr(io.in.a.bits.source, 2)
node _T_370 = eq(_T_369, UInt<4>(0h9))
node _T_371 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_372 = and(_T_370, _T_371)
node _T_373 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_374 = and(_T_372, _T_373)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_375 = shr(io.in.a.bits.source, 2)
node _T_376 = eq(_T_375, UInt<4>(0ha))
node _T_377 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_378 = and(_T_376, _T_377)
node _T_379 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_380 = and(_T_378, _T_379)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_381 = shr(io.in.a.bits.source, 2)
node _T_382 = eq(_T_381, UInt<4>(0hb))
node _T_383 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_384 = and(_T_382, _T_383)
node _T_385 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0)
node _T_387 = shr(io.in.a.bits.source, 3)
node _T_388 = eq(_T_387, UInt<2>(0h2))
node _T_389 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_390 = and(_T_388, _T_389)
node _T_391 = leq(uncommonBits_32, UInt<3>(0h7))
node _T_392 = and(_T_390, _T_391)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0)
node _T_393 = shr(io.in.a.bits.source, 3)
node _T_394 = eq(_T_393, UInt<1>(0h1))
node _T_395 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_396 = and(_T_394, _T_395)
node _T_397 = leq(uncommonBits_33, UInt<3>(0h7))
node _T_398 = and(_T_396, _T_397)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0)
node _T_399 = shr(io.in.a.bits.source, 3)
node _T_400 = eq(_T_399, UInt<1>(0h0))
node _T_401 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_402 = and(_T_400, _T_401)
node _T_403 = leq(uncommonBits_34, UInt<3>(0h7))
node _T_404 = and(_T_402, _T_403)
node _T_405 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_362
connect _WIRE_2[1], _T_368
connect _WIRE_2[2], _T_374
connect _WIRE_2[3], _T_380
connect _WIRE_2[4], _T_386
connect _WIRE_2[5], _T_392
connect _WIRE_2[6], _T_398
connect _WIRE_2[7], _T_404
connect _WIRE_2[8], _T_405
node _T_406 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_407 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_408 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_409 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_410 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_411 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_412 = mux(_WIRE_2[5], _T_406, UInt<1>(0h0))
node _T_413 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_414 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_415 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_416 = or(_T_407, _T_408)
node _T_417 = or(_T_416, _T_409)
node _T_418 = or(_T_417, _T_410)
node _T_419 = or(_T_418, _T_411)
node _T_420 = or(_T_419, _T_412)
node _T_421 = or(_T_420, _T_413)
node _T_422 = or(_T_421, _T_414)
node _T_423 = or(_T_422, _T_415)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_423
node _T_424 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_425 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_426 = and(_T_424, _T_425)
node _T_427 = or(UInt<1>(0h0), _T_426)
node _T_428 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_429 = cvt(_T_428)
node _T_430 = and(_T_429, asSInt(UInt<13>(0h1000)))
node _T_431 = asSInt(_T_430)
node _T_432 = eq(_T_431, asSInt(UInt<1>(0h0)))
node _T_433 = and(_T_427, _T_432)
node _T_434 = or(UInt<1>(0h0), _T_433)
node _T_435 = and(_WIRE_3, _T_434)
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_435, UInt<1>(0h1), "") : assert_11
node _T_439 = asUInt(reset)
node _T_440 = eq(_T_439, UInt<1>(0h0))
when _T_440 :
node _T_441 = eq(source_ok, UInt<1>(0h0))
when _T_441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_442 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_442, UInt<1>(0h1), "") : assert_13
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(is_aligned, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_449 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_T_449, UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_449, UInt<1>(0h1), "") : assert_15
node _T_453 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_454 = asUInt(reset)
node _T_455 = eq(_T_454, UInt<1>(0h0))
when _T_455 :
node _T_456 = eq(_T_453, UInt<1>(0h0))
when _T_456 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_453, UInt<1>(0h1), "") : assert_16
node _T_457 = not(io.in.a.bits.mask)
node _T_458 = eq(_T_457, UInt<1>(0h0))
node _T_459 = asUInt(reset)
node _T_460 = eq(_T_459, UInt<1>(0h0))
when _T_460 :
node _T_461 = eq(_T_458, UInt<1>(0h0))
when _T_461 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_458, UInt<1>(0h1), "") : assert_17
node _T_462 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_463 = asUInt(reset)
node _T_464 = eq(_T_463, UInt<1>(0h0))
when _T_464 :
node _T_465 = eq(_T_462, UInt<1>(0h0))
when _T_465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_462, UInt<1>(0h1), "") : assert_18
node _T_466 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_466 :
node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_468 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_469 = and(_T_467, _T_468)
node _T_470 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_471 = shr(io.in.a.bits.source, 2)
node _T_472 = eq(_T_471, UInt<4>(0h8))
node _T_473 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_474 = and(_T_472, _T_473)
node _T_475 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_476 = and(_T_474, _T_475)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_477 = shr(io.in.a.bits.source, 2)
node _T_478 = eq(_T_477, UInt<4>(0h9))
node _T_479 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_480 = and(_T_478, _T_479)
node _T_481 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_482 = and(_T_480, _T_481)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_483 = shr(io.in.a.bits.source, 2)
node _T_484 = eq(_T_483, UInt<4>(0ha))
node _T_485 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_486 = and(_T_484, _T_485)
node _T_487 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_488 = and(_T_486, _T_487)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_489 = shr(io.in.a.bits.source, 2)
node _T_490 = eq(_T_489, UInt<4>(0hb))
node _T_491 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_492 = and(_T_490, _T_491)
node _T_493 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_494 = and(_T_492, _T_493)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0)
node _T_495 = shr(io.in.a.bits.source, 3)
node _T_496 = eq(_T_495, UInt<2>(0h2))
node _T_497 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_498 = and(_T_496, _T_497)
node _T_499 = leq(uncommonBits_39, UInt<3>(0h7))
node _T_500 = and(_T_498, _T_499)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0)
node _T_501 = shr(io.in.a.bits.source, 3)
node _T_502 = eq(_T_501, UInt<1>(0h1))
node _T_503 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_504 = and(_T_502, _T_503)
node _T_505 = leq(uncommonBits_40, UInt<3>(0h7))
node _T_506 = and(_T_504, _T_505)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0)
node _T_507 = shr(io.in.a.bits.source, 3)
node _T_508 = eq(_T_507, UInt<1>(0h0))
node _T_509 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_510 = and(_T_508, _T_509)
node _T_511 = leq(uncommonBits_41, UInt<3>(0h7))
node _T_512 = and(_T_510, _T_511)
node _T_513 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_514 = or(_T_470, _T_476)
node _T_515 = or(_T_514, _T_482)
node _T_516 = or(_T_515, _T_488)
node _T_517 = or(_T_516, _T_494)
node _T_518 = or(_T_517, _T_500)
node _T_519 = or(_T_518, _T_506)
node _T_520 = or(_T_519, _T_512)
node _T_521 = or(_T_520, _T_513)
node _T_522 = and(_T_469, _T_521)
node _T_523 = or(UInt<1>(0h0), _T_522)
node _T_524 = asUInt(reset)
node _T_525 = eq(_T_524, UInt<1>(0h0))
when _T_525 :
node _T_526 = eq(_T_523, UInt<1>(0h0))
when _T_526 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_523, UInt<1>(0h1), "") : assert_19
node _T_527 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_528 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_529 = and(_T_527, _T_528)
node _T_530 = or(UInt<1>(0h0), _T_529)
node _T_531 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_532 = cvt(_T_531)
node _T_533 = and(_T_532, asSInt(UInt<13>(0h1000)))
node _T_534 = asSInt(_T_533)
node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0)))
node _T_536 = and(_T_530, _T_535)
node _T_537 = or(UInt<1>(0h0), _T_536)
node _T_538 = asUInt(reset)
node _T_539 = eq(_T_538, UInt<1>(0h0))
when _T_539 :
node _T_540 = eq(_T_537, UInt<1>(0h0))
when _T_540 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_537, UInt<1>(0h1), "") : assert_20
node _T_541 = asUInt(reset)
node _T_542 = eq(_T_541, UInt<1>(0h0))
when _T_542 :
node _T_543 = eq(source_ok, UInt<1>(0h0))
when _T_543 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_544 = asUInt(reset)
node _T_545 = eq(_T_544, UInt<1>(0h0))
when _T_545 :
node _T_546 = eq(is_aligned, UInt<1>(0h0))
when _T_546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_547 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_548 = asUInt(reset)
node _T_549 = eq(_T_548, UInt<1>(0h0))
when _T_549 :
node _T_550 = eq(_T_547, UInt<1>(0h0))
when _T_550 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_547, UInt<1>(0h1), "") : assert_23
node _T_551 = eq(io.in.a.bits.mask, mask)
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_551, UInt<1>(0h1), "") : assert_24
node _T_555 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_556 = asUInt(reset)
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(_T_555, UInt<1>(0h0))
when _T_558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_555, UInt<1>(0h1), "") : assert_25
node _T_559 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_559 :
node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_562 = and(_T_560, _T_561)
node _T_563 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_564 = shr(io.in.a.bits.source, 2)
node _T_565 = eq(_T_564, UInt<4>(0h8))
node _T_566 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_567 = and(_T_565, _T_566)
node _T_568 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_569 = and(_T_567, _T_568)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_570 = shr(io.in.a.bits.source, 2)
node _T_571 = eq(_T_570, UInt<4>(0h9))
node _T_572 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_573 = and(_T_571, _T_572)
node _T_574 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_575 = and(_T_573, _T_574)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_576 = shr(io.in.a.bits.source, 2)
node _T_577 = eq(_T_576, UInt<4>(0ha))
node _T_578 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_579 = and(_T_577, _T_578)
node _T_580 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_581 = and(_T_579, _T_580)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_582 = shr(io.in.a.bits.source, 2)
node _T_583 = eq(_T_582, UInt<4>(0hb))
node _T_584 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_585 = and(_T_583, _T_584)
node _T_586 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_587 = and(_T_585, _T_586)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0)
node _T_588 = shr(io.in.a.bits.source, 3)
node _T_589 = eq(_T_588, UInt<2>(0h2))
node _T_590 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_591 = and(_T_589, _T_590)
node _T_592 = leq(uncommonBits_46, UInt<3>(0h7))
node _T_593 = and(_T_591, _T_592)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0)
node _T_594 = shr(io.in.a.bits.source, 3)
node _T_595 = eq(_T_594, UInt<1>(0h1))
node _T_596 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_597 = and(_T_595, _T_596)
node _T_598 = leq(uncommonBits_47, UInt<3>(0h7))
node _T_599 = and(_T_597, _T_598)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0)
node _T_600 = shr(io.in.a.bits.source, 3)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_603 = and(_T_601, _T_602)
node _T_604 = leq(uncommonBits_48, UInt<3>(0h7))
node _T_605 = and(_T_603, _T_604)
node _T_606 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_607 = or(_T_563, _T_569)
node _T_608 = or(_T_607, _T_575)
node _T_609 = or(_T_608, _T_581)
node _T_610 = or(_T_609, _T_587)
node _T_611 = or(_T_610, _T_593)
node _T_612 = or(_T_611, _T_599)
node _T_613 = or(_T_612, _T_605)
node _T_614 = or(_T_613, _T_606)
node _T_615 = and(_T_562, _T_614)
node _T_616 = or(UInt<1>(0h0), _T_615)
node _T_617 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_618 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_619 = and(_T_617, _T_618)
node _T_620 = or(UInt<1>(0h0), _T_619)
node _T_621 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_622 = cvt(_T_621)
node _T_623 = and(_T_622, asSInt(UInt<13>(0h1000)))
node _T_624 = asSInt(_T_623)
node _T_625 = eq(_T_624, asSInt(UInt<1>(0h0)))
node _T_626 = and(_T_620, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = and(_T_616, _T_627)
node _T_629 = asUInt(reset)
node _T_630 = eq(_T_629, UInt<1>(0h0))
when _T_630 :
node _T_631 = eq(_T_628, UInt<1>(0h0))
when _T_631 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_628, UInt<1>(0h1), "") : assert_26
node _T_632 = asUInt(reset)
node _T_633 = eq(_T_632, UInt<1>(0h0))
when _T_633 :
node _T_634 = eq(source_ok, UInt<1>(0h0))
when _T_634 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(is_aligned, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_638 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_638, UInt<1>(0h1), "") : assert_29
node _T_642 = eq(io.in.a.bits.mask, mask)
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_642, UInt<1>(0h1), "") : assert_30
node _T_646 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_646 :
node _T_647 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_648 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_649 = and(_T_647, _T_648)
node _T_650 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_651 = shr(io.in.a.bits.source, 2)
node _T_652 = eq(_T_651, UInt<4>(0h8))
node _T_653 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_654 = and(_T_652, _T_653)
node _T_655 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_656 = and(_T_654, _T_655)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_657 = shr(io.in.a.bits.source, 2)
node _T_658 = eq(_T_657, UInt<4>(0h9))
node _T_659 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_660 = and(_T_658, _T_659)
node _T_661 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_662 = and(_T_660, _T_661)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_663 = shr(io.in.a.bits.source, 2)
node _T_664 = eq(_T_663, UInt<4>(0ha))
node _T_665 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_666 = and(_T_664, _T_665)
node _T_667 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_668 = and(_T_666, _T_667)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_669 = shr(io.in.a.bits.source, 2)
node _T_670 = eq(_T_669, UInt<4>(0hb))
node _T_671 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_672 = and(_T_670, _T_671)
node _T_673 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_674 = and(_T_672, _T_673)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0)
node _T_675 = shr(io.in.a.bits.source, 3)
node _T_676 = eq(_T_675, UInt<2>(0h2))
node _T_677 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_678 = and(_T_676, _T_677)
node _T_679 = leq(uncommonBits_53, UInt<3>(0h7))
node _T_680 = and(_T_678, _T_679)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0)
node _T_681 = shr(io.in.a.bits.source, 3)
node _T_682 = eq(_T_681, UInt<1>(0h1))
node _T_683 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_684 = and(_T_682, _T_683)
node _T_685 = leq(uncommonBits_54, UInt<3>(0h7))
node _T_686 = and(_T_684, _T_685)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 2, 0)
node _T_687 = shr(io.in.a.bits.source, 3)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_690 = and(_T_688, _T_689)
node _T_691 = leq(uncommonBits_55, UInt<3>(0h7))
node _T_692 = and(_T_690, _T_691)
node _T_693 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_694 = or(_T_650, _T_656)
node _T_695 = or(_T_694, _T_662)
node _T_696 = or(_T_695, _T_668)
node _T_697 = or(_T_696, _T_674)
node _T_698 = or(_T_697, _T_680)
node _T_699 = or(_T_698, _T_686)
node _T_700 = or(_T_699, _T_692)
node _T_701 = or(_T_700, _T_693)
node _T_702 = and(_T_649, _T_701)
node _T_703 = or(UInt<1>(0h0), _T_702)
node _T_704 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_705 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_706 = and(_T_704, _T_705)
node _T_707 = or(UInt<1>(0h0), _T_706)
node _T_708 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_709 = cvt(_T_708)
node _T_710 = and(_T_709, asSInt(UInt<13>(0h1000)))
node _T_711 = asSInt(_T_710)
node _T_712 = eq(_T_711, asSInt(UInt<1>(0h0)))
node _T_713 = and(_T_707, _T_712)
node _T_714 = or(UInt<1>(0h0), _T_713)
node _T_715 = and(_T_703, _T_714)
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(_T_715, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_715, UInt<1>(0h1), "") : assert_31
node _T_719 = asUInt(reset)
node _T_720 = eq(_T_719, UInt<1>(0h0))
when _T_720 :
node _T_721 = eq(source_ok, UInt<1>(0h0))
when _T_721 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_722 = asUInt(reset)
node _T_723 = eq(_T_722, UInt<1>(0h0))
when _T_723 :
node _T_724 = eq(is_aligned, UInt<1>(0h0))
when _T_724 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_725 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_725, UInt<1>(0h1), "") : assert_34
node _T_729 = not(mask)
node _T_730 = and(io.in.a.bits.mask, _T_729)
node _T_731 = eq(_T_730, UInt<1>(0h0))
node _T_732 = asUInt(reset)
node _T_733 = eq(_T_732, UInt<1>(0h0))
when _T_733 :
node _T_734 = eq(_T_731, UInt<1>(0h0))
when _T_734 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_731, UInt<1>(0h1), "") : assert_35
node _T_735 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_735 :
node _T_736 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_737 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_738 = and(_T_736, _T_737)
node _T_739 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_740 = shr(io.in.a.bits.source, 2)
node _T_741 = eq(_T_740, UInt<4>(0h8))
node _T_742 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_743 = and(_T_741, _T_742)
node _T_744 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_745 = and(_T_743, _T_744)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_746 = shr(io.in.a.bits.source, 2)
node _T_747 = eq(_T_746, UInt<4>(0h9))
node _T_748 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_749 = and(_T_747, _T_748)
node _T_750 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_751 = and(_T_749, _T_750)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0)
node _T_752 = shr(io.in.a.bits.source, 2)
node _T_753 = eq(_T_752, UInt<4>(0ha))
node _T_754 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_755 = and(_T_753, _T_754)
node _T_756 = leq(uncommonBits_58, UInt<2>(0h3))
node _T_757 = and(_T_755, _T_756)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0)
node _T_758 = shr(io.in.a.bits.source, 2)
node _T_759 = eq(_T_758, UInt<4>(0hb))
node _T_760 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_761 = and(_T_759, _T_760)
node _T_762 = leq(uncommonBits_59, UInt<2>(0h3))
node _T_763 = and(_T_761, _T_762)
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 2, 0)
node _T_764 = shr(io.in.a.bits.source, 3)
node _T_765 = eq(_T_764, UInt<2>(0h2))
node _T_766 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_767 = and(_T_765, _T_766)
node _T_768 = leq(uncommonBits_60, UInt<3>(0h7))
node _T_769 = and(_T_767, _T_768)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 2, 0)
node _T_770 = shr(io.in.a.bits.source, 3)
node _T_771 = eq(_T_770, UInt<1>(0h1))
node _T_772 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_773 = and(_T_771, _T_772)
node _T_774 = leq(uncommonBits_61, UInt<3>(0h7))
node _T_775 = and(_T_773, _T_774)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 2, 0)
node _T_776 = shr(io.in.a.bits.source, 3)
node _T_777 = eq(_T_776, UInt<1>(0h0))
node _T_778 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_779 = and(_T_777, _T_778)
node _T_780 = leq(uncommonBits_62, UInt<3>(0h7))
node _T_781 = and(_T_779, _T_780)
node _T_782 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_783 = or(_T_739, _T_745)
node _T_784 = or(_T_783, _T_751)
node _T_785 = or(_T_784, _T_757)
node _T_786 = or(_T_785, _T_763)
node _T_787 = or(_T_786, _T_769)
node _T_788 = or(_T_787, _T_775)
node _T_789 = or(_T_788, _T_781)
node _T_790 = or(_T_789, _T_782)
node _T_791 = and(_T_738, _T_790)
node _T_792 = or(UInt<1>(0h0), _T_791)
node _T_793 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_794 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_795 = cvt(_T_794)
node _T_796 = and(_T_795, asSInt(UInt<13>(0h1000)))
node _T_797 = asSInt(_T_796)
node _T_798 = eq(_T_797, asSInt(UInt<1>(0h0)))
node _T_799 = and(_T_793, _T_798)
node _T_800 = or(UInt<1>(0h0), _T_799)
node _T_801 = and(_T_792, _T_800)
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(_T_801, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_801, UInt<1>(0h1), "") : assert_36
node _T_805 = asUInt(reset)
node _T_806 = eq(_T_805, UInt<1>(0h0))
when _T_806 :
node _T_807 = eq(source_ok, UInt<1>(0h0))
when _T_807 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_808 = asUInt(reset)
node _T_809 = eq(_T_808, UInt<1>(0h0))
when _T_809 :
node _T_810 = eq(is_aligned, UInt<1>(0h0))
when _T_810 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_811 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_812 = asUInt(reset)
node _T_813 = eq(_T_812, UInt<1>(0h0))
when _T_813 :
node _T_814 = eq(_T_811, UInt<1>(0h0))
when _T_814 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_811, UInt<1>(0h1), "") : assert_39
node _T_815 = eq(io.in.a.bits.mask, mask)
node _T_816 = asUInt(reset)
node _T_817 = eq(_T_816, UInt<1>(0h0))
when _T_817 :
node _T_818 = eq(_T_815, UInt<1>(0h0))
when _T_818 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_815, UInt<1>(0h1), "") : assert_40
node _T_819 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_819 :
node _T_820 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_821 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_822 = and(_T_820, _T_821)
node _T_823 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_824 = shr(io.in.a.bits.source, 2)
node _T_825 = eq(_T_824, UInt<4>(0h8))
node _T_826 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_827 = and(_T_825, _T_826)
node _T_828 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_829 = and(_T_827, _T_828)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0)
node _T_830 = shr(io.in.a.bits.source, 2)
node _T_831 = eq(_T_830, UInt<4>(0h9))
node _T_832 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_833 = and(_T_831, _T_832)
node _T_834 = leq(uncommonBits_64, UInt<2>(0h3))
node _T_835 = and(_T_833, _T_834)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0)
node _T_836 = shr(io.in.a.bits.source, 2)
node _T_837 = eq(_T_836, UInt<4>(0ha))
node _T_838 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_839 = and(_T_837, _T_838)
node _T_840 = leq(uncommonBits_65, UInt<2>(0h3))
node _T_841 = and(_T_839, _T_840)
node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0)
node _T_842 = shr(io.in.a.bits.source, 2)
node _T_843 = eq(_T_842, UInt<4>(0hb))
node _T_844 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_845 = and(_T_843, _T_844)
node _T_846 = leq(uncommonBits_66, UInt<2>(0h3))
node _T_847 = and(_T_845, _T_846)
node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 2, 0)
node _T_848 = shr(io.in.a.bits.source, 3)
node _T_849 = eq(_T_848, UInt<2>(0h2))
node _T_850 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_851 = and(_T_849, _T_850)
node _T_852 = leq(uncommonBits_67, UInt<3>(0h7))
node _T_853 = and(_T_851, _T_852)
node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 2, 0)
node _T_854 = shr(io.in.a.bits.source, 3)
node _T_855 = eq(_T_854, UInt<1>(0h1))
node _T_856 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_857 = and(_T_855, _T_856)
node _T_858 = leq(uncommonBits_68, UInt<3>(0h7))
node _T_859 = and(_T_857, _T_858)
node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0)
node _T_860 = shr(io.in.a.bits.source, 3)
node _T_861 = eq(_T_860, UInt<1>(0h0))
node _T_862 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_863 = and(_T_861, _T_862)
node _T_864 = leq(uncommonBits_69, UInt<3>(0h7))
node _T_865 = and(_T_863, _T_864)
node _T_866 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_867 = or(_T_823, _T_829)
node _T_868 = or(_T_867, _T_835)
node _T_869 = or(_T_868, _T_841)
node _T_870 = or(_T_869, _T_847)
node _T_871 = or(_T_870, _T_853)
node _T_872 = or(_T_871, _T_859)
node _T_873 = or(_T_872, _T_865)
node _T_874 = or(_T_873, _T_866)
node _T_875 = and(_T_822, _T_874)
node _T_876 = or(UInt<1>(0h0), _T_875)
node _T_877 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_878 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_879 = cvt(_T_878)
node _T_880 = and(_T_879, asSInt(UInt<13>(0h1000)))
node _T_881 = asSInt(_T_880)
node _T_882 = eq(_T_881, asSInt(UInt<1>(0h0)))
node _T_883 = and(_T_877, _T_882)
node _T_884 = or(UInt<1>(0h0), _T_883)
node _T_885 = and(_T_876, _T_884)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_885, UInt<1>(0h1), "") : assert_41
node _T_889 = asUInt(reset)
node _T_890 = eq(_T_889, UInt<1>(0h0))
when _T_890 :
node _T_891 = eq(source_ok, UInt<1>(0h0))
when _T_891 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_892 = asUInt(reset)
node _T_893 = eq(_T_892, UInt<1>(0h0))
when _T_893 :
node _T_894 = eq(is_aligned, UInt<1>(0h0))
when _T_894 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_895 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_896 = asUInt(reset)
node _T_897 = eq(_T_896, UInt<1>(0h0))
when _T_897 :
node _T_898 = eq(_T_895, UInt<1>(0h0))
when _T_898 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_895, UInt<1>(0h1), "") : assert_44
node _T_899 = eq(io.in.a.bits.mask, mask)
node _T_900 = asUInt(reset)
node _T_901 = eq(_T_900, UInt<1>(0h0))
when _T_901 :
node _T_902 = eq(_T_899, UInt<1>(0h0))
when _T_902 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_899, UInt<1>(0h1), "") : assert_45
node _T_903 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_903 :
node _T_904 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_905 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_906 = and(_T_904, _T_905)
node _T_907 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0)
node _T_908 = shr(io.in.a.bits.source, 2)
node _T_909 = eq(_T_908, UInt<4>(0h8))
node _T_910 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_911 = and(_T_909, _T_910)
node _T_912 = leq(uncommonBits_70, UInt<2>(0h3))
node _T_913 = and(_T_911, _T_912)
node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0)
node _T_914 = shr(io.in.a.bits.source, 2)
node _T_915 = eq(_T_914, UInt<4>(0h9))
node _T_916 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_917 = and(_T_915, _T_916)
node _T_918 = leq(uncommonBits_71, UInt<2>(0h3))
node _T_919 = and(_T_917, _T_918)
node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0)
node _T_920 = shr(io.in.a.bits.source, 2)
node _T_921 = eq(_T_920, UInt<4>(0ha))
node _T_922 = leq(UInt<1>(0h0), uncommonBits_72)
node _T_923 = and(_T_921, _T_922)
node _T_924 = leq(uncommonBits_72, UInt<2>(0h3))
node _T_925 = and(_T_923, _T_924)
node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0)
node _T_926 = shr(io.in.a.bits.source, 2)
node _T_927 = eq(_T_926, UInt<4>(0hb))
node _T_928 = leq(UInt<1>(0h0), uncommonBits_73)
node _T_929 = and(_T_927, _T_928)
node _T_930 = leq(uncommonBits_73, UInt<2>(0h3))
node _T_931 = and(_T_929, _T_930)
node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0)
node _T_932 = shr(io.in.a.bits.source, 3)
node _T_933 = eq(_T_932, UInt<2>(0h2))
node _T_934 = leq(UInt<1>(0h0), uncommonBits_74)
node _T_935 = and(_T_933, _T_934)
node _T_936 = leq(uncommonBits_74, UInt<3>(0h7))
node _T_937 = and(_T_935, _T_936)
node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_75 = bits(_uncommonBits_T_75, 2, 0)
node _T_938 = shr(io.in.a.bits.source, 3)
node _T_939 = eq(_T_938, UInt<1>(0h1))
node _T_940 = leq(UInt<1>(0h0), uncommonBits_75)
node _T_941 = and(_T_939, _T_940)
node _T_942 = leq(uncommonBits_75, UInt<3>(0h7))
node _T_943 = and(_T_941, _T_942)
node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_76 = bits(_uncommonBits_T_76, 2, 0)
node _T_944 = shr(io.in.a.bits.source, 3)
node _T_945 = eq(_T_944, UInt<1>(0h0))
node _T_946 = leq(UInt<1>(0h0), uncommonBits_76)
node _T_947 = and(_T_945, _T_946)
node _T_948 = leq(uncommonBits_76, UInt<3>(0h7))
node _T_949 = and(_T_947, _T_948)
node _T_950 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_951 = or(_T_907, _T_913)
node _T_952 = or(_T_951, _T_919)
node _T_953 = or(_T_952, _T_925)
node _T_954 = or(_T_953, _T_931)
node _T_955 = or(_T_954, _T_937)
node _T_956 = or(_T_955, _T_943)
node _T_957 = or(_T_956, _T_949)
node _T_958 = or(_T_957, _T_950)
node _T_959 = and(_T_906, _T_958)
node _T_960 = or(UInt<1>(0h0), _T_959)
node _T_961 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_962 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_963 = cvt(_T_962)
node _T_964 = and(_T_963, asSInt(UInt<13>(0h1000)))
node _T_965 = asSInt(_T_964)
node _T_966 = eq(_T_965, asSInt(UInt<1>(0h0)))
node _T_967 = and(_T_961, _T_966)
node _T_968 = or(UInt<1>(0h0), _T_967)
node _T_969 = and(_T_960, _T_968)
node _T_970 = asUInt(reset)
node _T_971 = eq(_T_970, UInt<1>(0h0))
when _T_971 :
node _T_972 = eq(_T_969, UInt<1>(0h0))
when _T_972 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_969, UInt<1>(0h1), "") : assert_46
node _T_973 = asUInt(reset)
node _T_974 = eq(_T_973, UInt<1>(0h0))
when _T_974 :
node _T_975 = eq(source_ok, UInt<1>(0h0))
when _T_975 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_976 = asUInt(reset)
node _T_977 = eq(_T_976, UInt<1>(0h0))
when _T_977 :
node _T_978 = eq(is_aligned, UInt<1>(0h0))
when _T_978 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_979 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(_T_979, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_979, UInt<1>(0h1), "") : assert_49
node _T_983 = eq(io.in.a.bits.mask, mask)
node _T_984 = asUInt(reset)
node _T_985 = eq(_T_984, UInt<1>(0h0))
when _T_985 :
node _T_986 = eq(_T_983, UInt<1>(0h0))
when _T_986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_983, UInt<1>(0h1), "") : assert_50
node _T_987 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_988 = asUInt(reset)
node _T_989 = eq(_T_988, UInt<1>(0h0))
when _T_989 :
node _T_990 = eq(_T_987, UInt<1>(0h0))
when _T_990 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_987, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_991 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_992 = asUInt(reset)
node _T_993 = eq(_T_992, UInt<1>(0h0))
when _T_993 :
node _T_994 = eq(_T_991, UInt<1>(0h0))
when _T_994 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_991, UInt<1>(0h1), "") : assert_52
node _source_ok_T_51 = eq(io.in.d.bits.source, UInt<6>(0h30))
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_52 = shr(io.in.d.bits.source, 2)
node _source_ok_T_53 = eq(_source_ok_T_52, UInt<4>(0h8))
node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54)
node _source_ok_T_56 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_58 = shr(io.in.d.bits.source, 2)
node _source_ok_T_59 = eq(_source_ok_T_58, UInt<4>(0h9))
node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60)
node _source_ok_T_62 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_64 = shr(io.in.d.bits.source, 2)
node _source_ok_T_65 = eq(_source_ok_T_64, UInt<4>(0ha))
node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66)
node _source_ok_T_68 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_70 = shr(io.in.d.bits.source, 2)
node _source_ok_T_71 = eq(_source_ok_T_70, UInt<4>(0hb))
node _source_ok_T_72 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72)
node _source_ok_T_74 = leq(source_ok_uncommonBits_10, UInt<2>(0h3))
node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0)
node _source_ok_T_76 = shr(io.in.d.bits.source, 3)
node _source_ok_T_77 = eq(_source_ok_T_76, UInt<2>(0h2))
node _source_ok_T_78 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_79 = and(_source_ok_T_77, _source_ok_T_78)
node _source_ok_T_80 = leq(source_ok_uncommonBits_11, UInt<3>(0h7))
node _source_ok_T_81 = and(_source_ok_T_79, _source_ok_T_80)
node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 2, 0)
node _source_ok_T_82 = shr(io.in.d.bits.source, 3)
node _source_ok_T_83 = eq(_source_ok_T_82, UInt<1>(0h1))
node _source_ok_T_84 = leq(UInt<1>(0h0), source_ok_uncommonBits_12)
node _source_ok_T_85 = and(_source_ok_T_83, _source_ok_T_84)
node _source_ok_T_86 = leq(source_ok_uncommonBits_12, UInt<3>(0h7))
node _source_ok_T_87 = and(_source_ok_T_85, _source_ok_T_86)
node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 2, 0)
node _source_ok_T_88 = shr(io.in.d.bits.source, 3)
node _source_ok_T_89 = eq(_source_ok_T_88, UInt<1>(0h0))
node _source_ok_T_90 = leq(UInt<1>(0h0), source_ok_uncommonBits_13)
node _source_ok_T_91 = and(_source_ok_T_89, _source_ok_T_90)
node _source_ok_T_92 = leq(source_ok_uncommonBits_13, UInt<3>(0h7))
node _source_ok_T_93 = and(_source_ok_T_91, _source_ok_T_92)
node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_51
connect _source_ok_WIRE_1[1], _source_ok_T_57
connect _source_ok_WIRE_1[2], _source_ok_T_63
connect _source_ok_WIRE_1[3], _source_ok_T_69
connect _source_ok_WIRE_1[4], _source_ok_T_75
connect _source_ok_WIRE_1[5], _source_ok_T_81
connect _source_ok_WIRE_1[6], _source_ok_T_87
connect _source_ok_WIRE_1[7], _source_ok_T_93
connect _source_ok_WIRE_1[8], _source_ok_T_94
node _source_ok_T_95 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[2])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[3])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[4])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[5])
node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[6])
node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_101, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_995 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_995 :
node _T_996 = asUInt(reset)
node _T_997 = eq(_T_996, UInt<1>(0h0))
when _T_997 :
node _T_998 = eq(source_ok_1, UInt<1>(0h0))
when _T_998 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_999 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1000 = asUInt(reset)
node _T_1001 = eq(_T_1000, UInt<1>(0h0))
when _T_1001 :
node _T_1002 = eq(_T_999, UInt<1>(0h0))
when _T_1002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_999, UInt<1>(0h1), "") : assert_54
node _T_1003 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1004 = asUInt(reset)
node _T_1005 = eq(_T_1004, UInt<1>(0h0))
when _T_1005 :
node _T_1006 = eq(_T_1003, UInt<1>(0h0))
when _T_1006 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1003, UInt<1>(0h1), "") : assert_55
node _T_1007 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1008 = asUInt(reset)
node _T_1009 = eq(_T_1008, UInt<1>(0h0))
when _T_1009 :
node _T_1010 = eq(_T_1007, UInt<1>(0h0))
when _T_1010 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1007, UInt<1>(0h1), "") : assert_56
node _T_1011 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1012 = asUInt(reset)
node _T_1013 = eq(_T_1012, UInt<1>(0h0))
when _T_1013 :
node _T_1014 = eq(_T_1011, UInt<1>(0h0))
when _T_1014 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1011, UInt<1>(0h1), "") : assert_57
node _T_1015 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1015 :
node _T_1016 = asUInt(reset)
node _T_1017 = eq(_T_1016, UInt<1>(0h0))
when _T_1017 :
node _T_1018 = eq(source_ok_1, UInt<1>(0h0))
when _T_1018 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(sink_ok, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1022 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_60
node _T_1026 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1027 = asUInt(reset)
node _T_1028 = eq(_T_1027, UInt<1>(0h0))
when _T_1028 :
node _T_1029 = eq(_T_1026, UInt<1>(0h0))
when _T_1029 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1026, UInt<1>(0h1), "") : assert_61
node _T_1030 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1031 = asUInt(reset)
node _T_1032 = eq(_T_1031, UInt<1>(0h0))
when _T_1032 :
node _T_1033 = eq(_T_1030, UInt<1>(0h0))
when _T_1033 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1030, UInt<1>(0h1), "") : assert_62
node _T_1034 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1035 = asUInt(reset)
node _T_1036 = eq(_T_1035, UInt<1>(0h0))
when _T_1036 :
node _T_1037 = eq(_T_1034, UInt<1>(0h0))
when _T_1037 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1034, UInt<1>(0h1), "") : assert_63
node _T_1038 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1039 = or(UInt<1>(0h0), _T_1038)
node _T_1040 = asUInt(reset)
node _T_1041 = eq(_T_1040, UInt<1>(0h0))
when _T_1041 :
node _T_1042 = eq(_T_1039, UInt<1>(0h0))
when _T_1042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1039, UInt<1>(0h1), "") : assert_64
node _T_1043 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1043 :
node _T_1044 = asUInt(reset)
node _T_1045 = eq(_T_1044, UInt<1>(0h0))
when _T_1045 :
node _T_1046 = eq(source_ok_1, UInt<1>(0h0))
when _T_1046 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1047 = asUInt(reset)
node _T_1048 = eq(_T_1047, UInt<1>(0h0))
when _T_1048 :
node _T_1049 = eq(sink_ok, UInt<1>(0h0))
when _T_1049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1050 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1051 = asUInt(reset)
node _T_1052 = eq(_T_1051, UInt<1>(0h0))
when _T_1052 :
node _T_1053 = eq(_T_1050, UInt<1>(0h0))
when _T_1053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1050, UInt<1>(0h1), "") : assert_67
node _T_1054 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1055 = asUInt(reset)
node _T_1056 = eq(_T_1055, UInt<1>(0h0))
when _T_1056 :
node _T_1057 = eq(_T_1054, UInt<1>(0h0))
when _T_1057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1054, UInt<1>(0h1), "") : assert_68
node _T_1058 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1059 = asUInt(reset)
node _T_1060 = eq(_T_1059, UInt<1>(0h0))
when _T_1060 :
node _T_1061 = eq(_T_1058, UInt<1>(0h0))
when _T_1061 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1058, UInt<1>(0h1), "") : assert_69
node _T_1062 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1063 = or(_T_1062, io.in.d.bits.corrupt)
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(_T_1063, UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1063, UInt<1>(0h1), "") : assert_70
node _T_1067 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1068 = or(UInt<1>(0h0), _T_1067)
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_71
node _T_1072 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(source_ok_1, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1076 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1077 = asUInt(reset)
node _T_1078 = eq(_T_1077, UInt<1>(0h0))
when _T_1078 :
node _T_1079 = eq(_T_1076, UInt<1>(0h0))
when _T_1079 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1076, UInt<1>(0h1), "") : assert_73
node _T_1080 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1081 = asUInt(reset)
node _T_1082 = eq(_T_1081, UInt<1>(0h0))
when _T_1082 :
node _T_1083 = eq(_T_1080, UInt<1>(0h0))
when _T_1083 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1080, UInt<1>(0h1), "") : assert_74
node _T_1084 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1085 = or(UInt<1>(0h0), _T_1084)
node _T_1086 = asUInt(reset)
node _T_1087 = eq(_T_1086, UInt<1>(0h0))
when _T_1087 :
node _T_1088 = eq(_T_1085, UInt<1>(0h0))
when _T_1088 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1085, UInt<1>(0h1), "") : assert_75
node _T_1089 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1089 :
node _T_1090 = asUInt(reset)
node _T_1091 = eq(_T_1090, UInt<1>(0h0))
when _T_1091 :
node _T_1092 = eq(source_ok_1, UInt<1>(0h0))
when _T_1092 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1093 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1094 = asUInt(reset)
node _T_1095 = eq(_T_1094, UInt<1>(0h0))
when _T_1095 :
node _T_1096 = eq(_T_1093, UInt<1>(0h0))
when _T_1096 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1093, UInt<1>(0h1), "") : assert_77
node _T_1097 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1098 = or(_T_1097, io.in.d.bits.corrupt)
node _T_1099 = asUInt(reset)
node _T_1100 = eq(_T_1099, UInt<1>(0h0))
when _T_1100 :
node _T_1101 = eq(_T_1098, UInt<1>(0h0))
when _T_1101 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1098, UInt<1>(0h1), "") : assert_78
node _T_1102 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1103 = or(UInt<1>(0h0), _T_1102)
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(_T_1103, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1103, UInt<1>(0h1), "") : assert_79
node _T_1107 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1107 :
node _T_1108 = asUInt(reset)
node _T_1109 = eq(_T_1108, UInt<1>(0h0))
when _T_1109 :
node _T_1110 = eq(source_ok_1, UInt<1>(0h0))
when _T_1110 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1111 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1112 = asUInt(reset)
node _T_1113 = eq(_T_1112, UInt<1>(0h0))
when _T_1113 :
node _T_1114 = eq(_T_1111, UInt<1>(0h0))
when _T_1114 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1111, UInt<1>(0h1), "") : assert_81
node _T_1115 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(_T_1115, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1115, UInt<1>(0h1), "") : assert_82
node _T_1119 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1120 = or(UInt<1>(0h0), _T_1119)
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<21>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1124 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1128 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(_T_1128, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1128, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1132 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1133 = asUInt(reset)
node _T_1134 = eq(_T_1133, UInt<1>(0h0))
when _T_1134 :
node _T_1135 = eq(_T_1132, UInt<1>(0h0))
when _T_1135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1132, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1136 = eq(a_first, UInt<1>(0h0))
node _T_1137 = and(io.in.a.valid, _T_1136)
when _T_1137 :
node _T_1138 = eq(io.in.a.bits.opcode, opcode)
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_T_1138, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1138, UInt<1>(0h1), "") : assert_87
node _T_1142 = eq(io.in.a.bits.param, param)
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(_T_1142, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1142, UInt<1>(0h1), "") : assert_88
node _T_1146 = eq(io.in.a.bits.size, size)
node _T_1147 = asUInt(reset)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
when _T_1148 :
node _T_1149 = eq(_T_1146, UInt<1>(0h0))
when _T_1149 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1146, UInt<1>(0h1), "") : assert_89
node _T_1150 = eq(io.in.a.bits.source, source)
node _T_1151 = asUInt(reset)
node _T_1152 = eq(_T_1151, UInt<1>(0h0))
when _T_1152 :
node _T_1153 = eq(_T_1150, UInt<1>(0h0))
when _T_1153 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1150, UInt<1>(0h1), "") : assert_90
node _T_1154 = eq(io.in.a.bits.address, address)
node _T_1155 = asUInt(reset)
node _T_1156 = eq(_T_1155, UInt<1>(0h0))
when _T_1156 :
node _T_1157 = eq(_T_1154, UInt<1>(0h0))
when _T_1157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1154, UInt<1>(0h1), "") : assert_91
node _T_1158 = and(io.in.a.ready, io.in.a.valid)
node _T_1159 = and(_T_1158, a_first)
when _T_1159 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1160 = eq(d_first, UInt<1>(0h0))
node _T_1161 = and(io.in.d.valid, _T_1160)
when _T_1161 :
node _T_1162 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1163 = asUInt(reset)
node _T_1164 = eq(_T_1163, UInt<1>(0h0))
when _T_1164 :
node _T_1165 = eq(_T_1162, UInt<1>(0h0))
when _T_1165 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1162, UInt<1>(0h1), "") : assert_92
node _T_1166 = eq(io.in.d.bits.param, param_1)
node _T_1167 = asUInt(reset)
node _T_1168 = eq(_T_1167, UInt<1>(0h0))
when _T_1168 :
node _T_1169 = eq(_T_1166, UInt<1>(0h0))
when _T_1169 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1166, UInt<1>(0h1), "") : assert_93
node _T_1170 = eq(io.in.d.bits.size, size_1)
node _T_1171 = asUInt(reset)
node _T_1172 = eq(_T_1171, UInt<1>(0h0))
when _T_1172 :
node _T_1173 = eq(_T_1170, UInt<1>(0h0))
when _T_1173 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1170, UInt<1>(0h1), "") : assert_94
node _T_1174 = eq(io.in.d.bits.source, source_1)
node _T_1175 = asUInt(reset)
node _T_1176 = eq(_T_1175, UInt<1>(0h0))
when _T_1176 :
node _T_1177 = eq(_T_1174, UInt<1>(0h0))
when _T_1177 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1174, UInt<1>(0h1), "") : assert_95
node _T_1178 = eq(io.in.d.bits.sink, sink)
node _T_1179 = asUInt(reset)
node _T_1180 = eq(_T_1179, UInt<1>(0h0))
when _T_1180 :
node _T_1181 = eq(_T_1178, UInt<1>(0h0))
when _T_1181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1178, UInt<1>(0h1), "") : assert_96
node _T_1182 = eq(io.in.d.bits.denied, denied)
node _T_1183 = asUInt(reset)
node _T_1184 = eq(_T_1183, UInt<1>(0h0))
when _T_1184 :
node _T_1185 = eq(_T_1182, UInt<1>(0h0))
when _T_1185 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1182, UInt<1>(0h1), "") : assert_97
node _T_1186 = and(io.in.d.ready, io.in.d.valid)
node _T_1187 = and(_T_1186, d_first)
when _T_1187 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1188 = and(io.in.a.valid, a_first_1)
node _T_1189 = and(_T_1188, UInt<1>(0h1))
when _T_1189 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1190 = and(io.in.a.ready, io.in.a.valid)
node _T_1191 = and(_T_1190, a_first_1)
node _T_1192 = and(_T_1191, UInt<1>(0h1))
when _T_1192 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1193 = dshr(inflight, io.in.a.bits.source)
node _T_1194 = bits(_T_1193, 0, 0)
node _T_1195 = eq(_T_1194, UInt<1>(0h0))
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1199 = and(io.in.d.valid, d_first_1)
node _T_1200 = and(_T_1199, UInt<1>(0h1))
node _T_1201 = eq(d_release_ack, UInt<1>(0h0))
node _T_1202 = and(_T_1200, _T_1201)
when _T_1202 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1203 = and(io.in.d.ready, io.in.d.valid)
node _T_1204 = and(_T_1203, d_first_1)
node _T_1205 = and(_T_1204, UInt<1>(0h1))
node _T_1206 = eq(d_release_ack, UInt<1>(0h0))
node _T_1207 = and(_T_1205, _T_1206)
when _T_1207 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1208 = and(io.in.d.valid, d_first_1)
node _T_1209 = and(_T_1208, UInt<1>(0h1))
node _T_1210 = eq(d_release_ack, UInt<1>(0h0))
node _T_1211 = and(_T_1209, _T_1210)
when _T_1211 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1212 = dshr(inflight, io.in.d.bits.source)
node _T_1213 = bits(_T_1212, 0, 0)
node _T_1214 = or(_T_1213, same_cycle_resp)
node _T_1215 = asUInt(reset)
node _T_1216 = eq(_T_1215, UInt<1>(0h0))
when _T_1216 :
node _T_1217 = eq(_T_1214, UInt<1>(0h0))
when _T_1217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1214, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1218 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1219 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1220 = or(_T_1218, _T_1219)
node _T_1221 = asUInt(reset)
node _T_1222 = eq(_T_1221, UInt<1>(0h0))
when _T_1222 :
node _T_1223 = eq(_T_1220, UInt<1>(0h0))
when _T_1223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1220, UInt<1>(0h1), "") : assert_100
node _T_1224 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1225 = asUInt(reset)
node _T_1226 = eq(_T_1225, UInt<1>(0h0))
when _T_1226 :
node _T_1227 = eq(_T_1224, UInt<1>(0h0))
when _T_1227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1224, UInt<1>(0h1), "") : assert_101
else :
node _T_1228 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1229 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1230 = or(_T_1228, _T_1229)
node _T_1231 = asUInt(reset)
node _T_1232 = eq(_T_1231, UInt<1>(0h0))
when _T_1232 :
node _T_1233 = eq(_T_1230, UInt<1>(0h0))
when _T_1233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1230, UInt<1>(0h1), "") : assert_102
node _T_1234 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1235 = asUInt(reset)
node _T_1236 = eq(_T_1235, UInt<1>(0h0))
when _T_1236 :
node _T_1237 = eq(_T_1234, UInt<1>(0h0))
when _T_1237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1234, UInt<1>(0h1), "") : assert_103
node _T_1238 = and(io.in.d.valid, d_first_1)
node _T_1239 = and(_T_1238, a_first_1)
node _T_1240 = and(_T_1239, io.in.a.valid)
node _T_1241 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1242 = and(_T_1240, _T_1241)
node _T_1243 = eq(d_release_ack, UInt<1>(0h0))
node _T_1244 = and(_T_1242, _T_1243)
when _T_1244 :
node _T_1245 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1246 = or(_T_1245, io.in.a.ready)
node _T_1247 = asUInt(reset)
node _T_1248 = eq(_T_1247, UInt<1>(0h0))
when _T_1248 :
node _T_1249 = eq(_T_1246, UInt<1>(0h0))
when _T_1249 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1246, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_129
node _T_1250 = orr(inflight)
node _T_1251 = eq(_T_1250, UInt<1>(0h0))
node _T_1252 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1253 = or(_T_1251, _T_1252)
node _T_1254 = lt(watchdog, plusarg_reader.out)
node _T_1255 = or(_T_1253, _T_1254)
node _T_1256 = asUInt(reset)
node _T_1257 = eq(_T_1256, UInt<1>(0h0))
when _T_1257 :
node _T_1258 = eq(_T_1255, UInt<1>(0h0))
when _T_1258 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1255, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1259 = and(io.in.a.ready, io.in.a.valid)
node _T_1260 = and(io.in.d.ready, io.in.d.valid)
node _T_1261 = or(_T_1259, _T_1260)
when _T_1261 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1262 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1263 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1264 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1265 = and(_T_1263, _T_1264)
node _T_1266 = and(_T_1262, _T_1265)
when _T_1266 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1267 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1268 = and(_T_1267, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1269 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1270 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1271 = and(_T_1269, _T_1270)
node _T_1272 = and(_T_1268, _T_1271)
when _T_1272 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1273 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1274 = bits(_T_1273, 0, 0)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
node _T_1276 = asUInt(reset)
node _T_1277 = eq(_T_1276, UInt<1>(0h0))
when _T_1277 :
node _T_1278 = eq(_T_1275, UInt<1>(0h0))
when _T_1278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1275, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1279 = and(io.in.d.valid, d_first_2)
node _T_1280 = and(_T_1279, UInt<1>(0h1))
node _T_1281 = and(_T_1280, d_release_ack_1)
when _T_1281 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1282 = and(io.in.d.ready, io.in.d.valid)
node _T_1283 = and(_T_1282, d_first_2)
node _T_1284 = and(_T_1283, UInt<1>(0h1))
node _T_1285 = and(_T_1284, d_release_ack_1)
when _T_1285 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1286 = and(io.in.d.valid, d_first_2)
node _T_1287 = and(_T_1286, UInt<1>(0h1))
node _T_1288 = and(_T_1287, d_release_ack_1)
when _T_1288 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1289 = dshr(inflight_1, io.in.d.bits.source)
node _T_1290 = bits(_T_1289, 0, 0)
node _T_1291 = or(_T_1290, same_cycle_resp_1)
node _T_1292 = asUInt(reset)
node _T_1293 = eq(_T_1292, UInt<1>(0h0))
when _T_1293 :
node _T_1294 = eq(_T_1291, UInt<1>(0h0))
when _T_1294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1291, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1295 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1296 = asUInt(reset)
node _T_1297 = eq(_T_1296, UInt<1>(0h0))
when _T_1297 :
node _T_1298 = eq(_T_1295, UInt<1>(0h0))
when _T_1298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1295, UInt<1>(0h1), "") : assert_108
else :
node _T_1299 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1300 = asUInt(reset)
node _T_1301 = eq(_T_1300, UInt<1>(0h0))
when _T_1301 :
node _T_1302 = eq(_T_1299, UInt<1>(0h0))
when _T_1302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1299, UInt<1>(0h1), "") : assert_109
node _T_1303 = and(io.in.d.valid, d_first_2)
node _T_1304 = and(_T_1303, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1305 = and(_T_1304, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1306 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1307 = and(_T_1305, _T_1306)
node _T_1308 = and(_T_1307, d_release_ack_1)
node _T_1309 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1310 = and(_T_1308, _T_1309)
when _T_1310 :
node _T_1311 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<21>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1312 = or(_T_1311, _WIRE_27.ready)
node _T_1313 = asUInt(reset)
node _T_1314 = eq(_T_1313, UInt<1>(0h0))
when _T_1314 :
node _T_1315 = eq(_T_1312, UInt<1>(0h0))
when _T_1315 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1312, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_130
node _T_1316 = orr(inflight_1)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
node _T_1318 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1319 = or(_T_1317, _T_1318)
node _T_1320 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1321 = or(_T_1319, _T_1320)
node _T_1322 = asUInt(reset)
node _T_1323 = eq(_T_1322, UInt<1>(0h0))
when _T_1323 :
node _T_1324 = eq(_T_1321, UInt<1>(0h0))
when _T_1324 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1321, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<21>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1325 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1326 = and(io.in.d.ready, io.in.d.valid)
node _T_1327 = or(_T_1325, _T_1326)
when _T_1327 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_63( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_86 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_92 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_37 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_38 = _source_ok_T_37 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire _source_ok_T_44 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_50 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_51 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_51; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_52 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_58 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_64 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_70 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_53 = _source_ok_T_52 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_57; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_59 = _source_ok_T_58 == 5'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_63; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_65 = _source_ok_T_64 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_69; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_71 = _source_ok_T_70 == 5'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_75; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_76 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_82 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_88 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_77 = _source_ok_T_76 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_81; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_83 = _source_ok_T_82 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_87 = _source_ok_T_85; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_89 = _source_ok_T_88 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_93 = _source_ok_T_91; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_7 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_94; // @[Parameters.scala:1138:31]
wire _source_ok_T_95 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_101 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1259 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1259; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1259; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_1327 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1327; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1327; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1327; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1192 = _T_1259 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1192 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1192 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1192 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1192 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1192 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1238 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1238 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1207 = _T_1327 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1207 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1207 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1207 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1303 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1303 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1285 = _T_1327 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1285 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1285 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1285 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_80 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_120
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_80( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_120 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_72 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0))
node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1))
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3))
node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4))
node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6))
node _roundMagUp_T = and(roundingMode_min, io.in.sign)
node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0))
node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1)
node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2)
node adjustedSig = shl(io.in.sig, 0)
node doShiftSigDown1 = bits(adjustedSig, 26, 26)
wire common_expOut : UInt<9>
wire common_fractOut : UInt<23>
wire common_overflow : UInt<1>
wire common_totalUnderflow : UInt<1>
wire common_underflow : UInt<1>
wire common_inexact : UInt<1>
node _roundMask_T = bits(io.in.sExp, 8, 0)
node _roundMask_T_1 = not(_roundMask_T)
node roundMask_msb = bits(_roundMask_T_1, 8, 8)
node roundMask_lsbs = bits(_roundMask_T_1, 7, 0)
node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7)
node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0)
node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2)
node _roundMask_T_2 = bits(roundMask_shift, 63, 42)
node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0)
node _roundMask_T_4 = shl(UInt<8>(0hff), 8)
node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4)
node _roundMask_T_6 = shr(_roundMask_T_3, 8)
node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5)
node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0)
node _roundMask_T_9 = shl(_roundMask_T_8, 8)
node _roundMask_T_10 = not(_roundMask_T_5)
node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10)
node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11)
node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0)
node _roundMask_T_14 = shl(_roundMask_T_13, 4)
node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14)
node _roundMask_T_16 = shr(_roundMask_T_12, 4)
node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15)
node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0)
node _roundMask_T_19 = shl(_roundMask_T_18, 4)
node _roundMask_T_20 = not(_roundMask_T_15)
node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20)
node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21)
node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0)
node _roundMask_T_24 = shl(_roundMask_T_23, 2)
node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24)
node _roundMask_T_26 = shr(_roundMask_T_22, 2)
node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25)
node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0)
node _roundMask_T_29 = shl(_roundMask_T_28, 2)
node _roundMask_T_30 = not(_roundMask_T_25)
node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30)
node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31)
node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0)
node _roundMask_T_34 = shl(_roundMask_T_33, 1)
node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34)
node _roundMask_T_36 = shr(_roundMask_T_32, 1)
node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35)
node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0)
node _roundMask_T_39 = shl(_roundMask_T_38, 1)
node _roundMask_T_40 = not(_roundMask_T_35)
node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40)
node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41)
node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16)
node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0)
node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0)
node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0)
node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1)
node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47)
node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2)
node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0)
node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1)
node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51)
node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52)
node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4)
node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0)
node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1)
node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56)
node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57)
node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58)
node _roundMask_T_60 = not(_roundMask_T_59)
node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60)
node _roundMask_T_62 = not(_roundMask_T_61)
node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7))
node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6)
node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0)
node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3)
node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0)
node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0)
node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0)
node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1)
node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67)
node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2)
node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69)
node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0))
node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71)
node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0))
node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1)
node roundMask = cat(_roundMask_T_74, UInt<2>(0h3))
node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask)
node shiftedRoundMask = shr(_shiftedRoundMask_T, 1)
node _roundPosMask_T = not(shiftedRoundMask)
node roundPosMask = and(_roundPosMask_T, roundMask)
node _roundPosBit_T = and(adjustedSig, roundPosMask)
node roundPosBit = orr(_roundPosBit_T)
node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask)
node anyRoundExtra = orr(_anyRoundExtra_T)
node anyRound = or(roundPosBit, anyRoundExtra)
node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit)
node _roundIncr_T_2 = and(roundMagUp, anyRound)
node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2)
node _roundedSig_T = or(adjustedSig, roundMask)
node _roundedSig_T_1 = shr(_roundedSig_T, 2)
node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1))
node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit)
node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0))
node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4)
node _roundedSig_T_6 = shr(roundMask, 1)
node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0))
node _roundedSig_T_8 = not(_roundedSig_T_7)
node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8)
node _roundedSig_T_10 = not(roundMask)
node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10)
node _roundedSig_T_12 = shr(_roundedSig_T_11, 2)
node _roundedSig_T_13 = and(roundingMode_odd, anyRound)
node _roundedSig_T_14 = shr(roundPosMask, 1)
node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0))
node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15)
node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16)
node _sRoundedExp_T = shr(roundedSig, 24)
node _sRoundedExp_T_1 = cvt(_sRoundedExp_T)
node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1)
node _common_expOut_T = bits(sRoundedExp, 8, 0)
connect common_expOut, _common_expOut_T
node _common_fractOut_T = bits(roundedSig, 23, 1)
node _common_fractOut_T_1 = bits(roundedSig, 22, 0)
node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1)
connect common_fractOut, _common_fractOut_T_2
node _common_overflow_T = shr(sRoundedExp, 7)
node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3)))
connect common_overflow, _common_overflow_T_1
node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b)))
connect common_totalUnderflow, _common_totalUnderflow_T
node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2)
node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1)
node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1)
node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2)
node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T)
node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0)
node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2)
node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3)
node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit)
node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound)
node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2)
node _roundCarry_T = bits(roundedSig, 25, 25)
node _roundCarry_T_1 = bits(roundedSig, 24, 24)
node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1)
node _common_underflow_T = shr(io.in.sExp, 8)
node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0)))
node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1)
node _common_underflow_T_3 = bits(roundMask, 3, 3)
node _common_underflow_T_4 = bits(roundMask, 2, 2)
node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4)
node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5)
node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1))
node _common_underflow_T_8 = bits(roundMask, 4, 4)
node _common_underflow_T_9 = bits(roundMask, 3, 3)
node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9)
node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0))
node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11)
node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry)
node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit)
node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr)
node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0))
node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16)
node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17)
connect common_underflow, _common_underflow_T_18
node _common_inexact_T = or(common_totalUnderflow, anyRound)
connect common_inexact, _common_inexact_T
node isNaNOut = or(io.invalidExc, io.in.isNaN)
node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf)
node _commonCase_T = eq(isNaNOut, UInt<1>(0h0))
node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0))
node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1)
node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0))
node commonCase = and(_commonCase_T_2, _commonCase_T_3)
node overflow = and(commonCase, common_overflow)
node underflow = and(commonCase, common_underflow)
node _inexact_T = and(commonCase, common_inexact)
node inexact = or(overflow, _inexact_T)
node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag)
node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp)
node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow)
node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd)
node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1)
node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0))
node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T)
node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp)
node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T)
node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign)
node _expOut_T = or(io.in.isZero, common_totalUnderflow)
node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0))
node _expOut_T_2 = not(_expOut_T_1)
node _expOut_T_3 = and(common_expOut, _expOut_T_2)
node _expOut_T_4 = not(UInt<9>(0h6b))
node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0))
node _expOut_T_6 = not(_expOut_T_5)
node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6)
node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0))
node _expOut_T_9 = not(_expOut_T_8)
node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9)
node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0))
node _expOut_T_12 = not(_expOut_T_11)
node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12)
node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0))
node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14)
node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0))
node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16)
node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0))
node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18)
node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0))
node expOut = or(_expOut_T_19, _expOut_T_20)
node _fractOut_T = or(isNaNOut, io.in.isZero)
node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow)
node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0))
node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut)
node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0))
node fractOut = or(_fractOut_T_3, _fractOut_T_4)
node _io_out_T = cat(signOut, expOut)
node _io_out_T_1 = cat(_io_out_T, fractOut)
connect io.out, _io_out_T_1
node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc)
node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow)
node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact)
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_72( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Router_17 :
input clock : Clock
input reset : Reset
output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}}
wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}
invalidate destNodesIn.vc_free
invalidate destNodesIn.credit_return
invalidate destNodesIn.flit[0].bits.virt_channel_id
invalidate destNodesIn.flit[0].bits.flow.egress_node_id
invalidate destNodesIn.flit[0].bits.flow.egress_node
invalidate destNodesIn.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn.flit[0].bits.flow.ingress_node
invalidate destNodesIn.flit[0].bits.flow.vnet_id
invalidate destNodesIn.flit[0].bits.payload
invalidate destNodesIn.flit[0].bits.tail
invalidate destNodesIn.flit[0].bits.head
invalidate destNodesIn.flit[0].valid
inst monitor of NoCMonitor_25
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.vc_free, destNodesIn.vc_free
connect monitor.io.in.credit_return, destNodesIn.credit_return
connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id
connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id
connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node
connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id
connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node
connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id
connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload
connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail
connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head
connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid
wire destNodesIn_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}
invalidate destNodesIn_1.vc_free
invalidate destNodesIn_1.credit_return
invalidate destNodesIn_1.flit[0].bits.virt_channel_id
invalidate destNodesIn_1.flit[0].bits.flow.egress_node_id
invalidate destNodesIn_1.flit[0].bits.flow.egress_node
invalidate destNodesIn_1.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn_1.flit[0].bits.flow.ingress_node
invalidate destNodesIn_1.flit[0].bits.flow.vnet_id
invalidate destNodesIn_1.flit[0].bits.payload
invalidate destNodesIn_1.flit[0].bits.tail
invalidate destNodesIn_1.flit[0].bits.head
invalidate destNodesIn_1.flit[0].valid
inst monitor_1 of NoCMonitor_26
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.vc_free, destNodesIn_1.vc_free
connect monitor_1.io.in.credit_return, destNodesIn_1.credit_return
connect monitor_1.io.in.flit[0].bits.virt_channel_id, destNodesIn_1.flit[0].bits.virt_channel_id
connect monitor_1.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_1.flit[0].bits.flow.egress_node_id
connect monitor_1.io.in.flit[0].bits.flow.egress_node, destNodesIn_1.flit[0].bits.flow.egress_node
connect monitor_1.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_1.flit[0].bits.flow.ingress_node_id
connect monitor_1.io.in.flit[0].bits.flow.ingress_node, destNodesIn_1.flit[0].bits.flow.ingress_node
connect monitor_1.io.in.flit[0].bits.flow.vnet_id, destNodesIn_1.flit[0].bits.flow.vnet_id
connect monitor_1.io.in.flit[0].bits.payload, destNodesIn_1.flit[0].bits.payload
connect monitor_1.io.in.flit[0].bits.tail, destNodesIn_1.flit[0].bits.tail
connect monitor_1.io.in.flit[0].bits.head, destNodesIn_1.flit[0].bits.head
connect monitor_1.io.in.flit[0].valid, destNodesIn_1.flit[0].valid
wire destNodesIn_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}
invalidate destNodesIn_2.vc_free
invalidate destNodesIn_2.credit_return
invalidate destNodesIn_2.flit[0].bits.virt_channel_id
invalidate destNodesIn_2.flit[0].bits.flow.egress_node_id
invalidate destNodesIn_2.flit[0].bits.flow.egress_node
invalidate destNodesIn_2.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn_2.flit[0].bits.flow.ingress_node
invalidate destNodesIn_2.flit[0].bits.flow.vnet_id
invalidate destNodesIn_2.flit[0].bits.payload
invalidate destNodesIn_2.flit[0].bits.tail
invalidate destNodesIn_2.flit[0].bits.head
invalidate destNodesIn_2.flit[0].valid
inst monitor_2 of NoCMonitor_27
connect monitor_2.clock, clock
connect monitor_2.reset, reset
connect monitor_2.io.in.vc_free, destNodesIn_2.vc_free
connect monitor_2.io.in.credit_return, destNodesIn_2.credit_return
connect monitor_2.io.in.flit[0].bits.virt_channel_id, destNodesIn_2.flit[0].bits.virt_channel_id
connect monitor_2.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_2.flit[0].bits.flow.egress_node_id
connect monitor_2.io.in.flit[0].bits.flow.egress_node, destNodesIn_2.flit[0].bits.flow.egress_node
connect monitor_2.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_2.flit[0].bits.flow.ingress_node_id
connect monitor_2.io.in.flit[0].bits.flow.ingress_node, destNodesIn_2.flit[0].bits.flow.ingress_node
connect monitor_2.io.in.flit[0].bits.flow.vnet_id, destNodesIn_2.flit[0].bits.flow.vnet_id
connect monitor_2.io.in.flit[0].bits.payload, destNodesIn_2.flit[0].bits.payload
connect monitor_2.io.in.flit[0].bits.tail, destNodesIn_2.flit[0].bits.tail
connect monitor_2.io.in.flit[0].bits.head, destNodesIn_2.flit[0].bits.head
connect monitor_2.io.in.flit[0].valid, destNodesIn_2.flit[0].valid
wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}
invalidate sourceNodesOut.vc_free
invalidate sourceNodesOut.credit_return
invalidate sourceNodesOut.flit[0].bits.virt_channel_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut.flit[0].bits.payload
invalidate sourceNodesOut.flit[0].bits.tail
invalidate sourceNodesOut.flit[0].bits.head
invalidate sourceNodesOut.flit[0].valid
wire sourceNodesOut_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}
invalidate sourceNodesOut_1.vc_free
invalidate sourceNodesOut_1.credit_return
invalidate sourceNodesOut_1.flit[0].bits.virt_channel_id
invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node
invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut_1.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut_1.flit[0].bits.payload
invalidate sourceNodesOut_1.flit[0].bits.tail
invalidate sourceNodesOut_1.flit[0].bits.head
invalidate sourceNodesOut_1.flit[0].valid
wire sourceNodesOut_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}
invalidate sourceNodesOut_2.vc_free
invalidate sourceNodesOut_2.credit_return
invalidate sourceNodesOut_2.flit[0].bits.virt_channel_id
invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node
invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut_2.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut_2.flit[0].bits.payload
invalidate sourceNodesOut_2.flit[0].bits.tail
invalidate sourceNodesOut_2.flit[0].bits.head
invalidate sourceNodesOut_2.flit[0].valid
wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate debugNodeOut.sa_stall[0]
invalidate debugNodeOut.sa_stall[1]
invalidate debugNodeOut.sa_stall[2]
invalidate debugNodeOut.va_stall[0]
invalidate debugNodeOut.va_stall[1]
invalidate debugNodeOut.va_stall[2]
connect destNodesIn, auto.dest_nodes_in_0
connect destNodesIn_1, auto.dest_nodes_in_1
connect destNodesIn_2, auto.dest_nodes_in_2
connect auto.source_nodes_out_0, sourceNodesOut
connect auto.source_nodes_out_1, sourceNodesOut_1
connect auto.source_nodes_out_2, sourceNodesOut_2
connect auto.debug_out, debugNodeOut
inst input_unit_0_from_3 of InputUnit_25
connect input_unit_0_from_3.clock, clock
connect input_unit_0_from_3.reset, reset
inst input_unit_1_from_18 of InputUnit_26
connect input_unit_1_from_18.clock, clock
connect input_unit_1_from_18.reset, reset
inst input_unit_2_from_23 of InputUnit_27
connect input_unit_2_from_23.clock, clock
connect input_unit_2_from_23.reset, reset
inst output_unit_0_to_3 of OutputUnit_25
connect output_unit_0_to_3.clock, clock
connect output_unit_0_to_3.reset, reset
inst output_unit_1_to_18 of OutputUnit_26
connect output_unit_1_to_18.clock, clock
connect output_unit_1_to_18.reset, reset
inst output_unit_2_to_23 of OutputUnit_27
connect output_unit_2_to_23.clock, clock
connect output_unit_2_to_23.reset, reset
inst switch of Switch_17
connect switch.clock, clock
connect switch.reset, reset
inst switch_allocator of SwitchAllocator_17
connect switch_allocator.clock, clock
connect switch_allocator.reset, reset
inst vc_allocator of RotatingSingleVCAllocator_17
connect vc_allocator.clock, clock
connect vc_allocator.reset, reset
inst route_computer of RouteComputer_17
connect route_computer.clock, clock
connect route_computer.reset, reset
node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid)
node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid)
node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid)
node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2)
node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0)
node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4)
node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0)
wire fires_count : UInt
connect fires_count, _fires_count_T_6
connect input_unit_0_from_3.io.in, destNodesIn
connect input_unit_1_from_18.io.in, destNodesIn_1
connect input_unit_2_from_23.io.in, destNodesIn_2
connect output_unit_0_to_3.io.out.vc_free, sourceNodesOut.vc_free
connect output_unit_0_to_3.io.out.credit_return, sourceNodesOut.credit_return
connect sourceNodesOut.flit, output_unit_0_to_3.io.out.flit
connect output_unit_1_to_18.io.out.vc_free, sourceNodesOut_1.vc_free
connect output_unit_1_to_18.io.out.credit_return, sourceNodesOut_1.credit_return
connect sourceNodesOut_1.flit, output_unit_1_to_18.io.out.flit
connect output_unit_2_to_23.io.out.vc_free, sourceNodesOut_2.vc_free
connect output_unit_2_to_23.io.out.credit_return, sourceNodesOut_2.credit_return
connect sourceNodesOut_2.flit, output_unit_2_to_23.io.out.flit
connect route_computer.io.req.`0`, input_unit_0_from_3.io.router_req
connect route_computer.io.req.`1`, input_unit_1_from_18.io.router_req
connect route_computer.io.req.`2`, input_unit_2_from_23.io.router_req
connect input_unit_0_from_3.io.router_resp, route_computer.io.resp.`0`
connect input_unit_1_from_18.io.router_resp, route_computer.io.resp.`1`
connect input_unit_2_from_23.io.router_resp, route_computer.io.resp.`2`
connect vc_allocator.io.req.`0`, input_unit_0_from_3.io.vcalloc_req
connect vc_allocator.io.req.`1`, input_unit_1_from_18.io.vcalloc_req
connect vc_allocator.io.req.`2`, input_unit_2_from_23.io.vcalloc_req
connect input_unit_0_from_3.io.vcalloc_resp, vc_allocator.io.resp.`0`
connect input_unit_1_from_18.io.vcalloc_resp, vc_allocator.io.resp.`1`
connect input_unit_2_from_23.io.vcalloc_resp, vc_allocator.io.resp.`2`
connect output_unit_0_to_3.io.allocs, vc_allocator.io.out_allocs.`0`
connect output_unit_1_to_18.io.allocs, vc_allocator.io.out_allocs.`1`
connect output_unit_2_to_23.io.allocs, vc_allocator.io.out_allocs.`2`
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_3.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_3.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_3.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_3.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_3.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_3.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_3.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_3.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_3.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_3.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_3.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_3.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_3.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_3.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_3.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_3.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_3.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_3.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_3.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_3.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_3.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_3.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_3.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_3.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_3.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_3.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_3.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_3.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_3.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_3.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_3.io.channel_status[5].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_3.io.channel_status[5].flow.egress_node
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_3.io.channel_status[5].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_3.io.channel_status[5].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_3.io.channel_status[5].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_3.io.channel_status[5].occupied
connect vc_allocator.io.channel_status.`0`[6].flow.egress_node_id, output_unit_0_to_3.io.channel_status[6].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[6].flow.egress_node, output_unit_0_to_3.io.channel_status[6].flow.egress_node
connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node_id, output_unit_0_to_3.io.channel_status[6].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node, output_unit_0_to_3.io.channel_status[6].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[6].flow.vnet_id, output_unit_0_to_3.io.channel_status[6].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[6].occupied, output_unit_0_to_3.io.channel_status[6].occupied
connect vc_allocator.io.channel_status.`0`[7].flow.egress_node_id, output_unit_0_to_3.io.channel_status[7].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[7].flow.egress_node, output_unit_0_to_3.io.channel_status[7].flow.egress_node
connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node_id, output_unit_0_to_3.io.channel_status[7].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node, output_unit_0_to_3.io.channel_status[7].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[7].flow.vnet_id, output_unit_0_to_3.io.channel_status[7].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[7].occupied, output_unit_0_to_3.io.channel_status[7].occupied
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, output_unit_1_to_18.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, output_unit_1_to_18.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, output_unit_1_to_18.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, output_unit_1_to_18.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, output_unit_1_to_18.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[0].occupied, output_unit_1_to_18.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`1`[1].flow.egress_node_id, output_unit_1_to_18.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[1].flow.egress_node, output_unit_1_to_18.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node_id, output_unit_1_to_18.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node, output_unit_1_to_18.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[1].flow.vnet_id, output_unit_1_to_18.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[1].occupied, output_unit_1_to_18.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`1`[2].flow.egress_node_id, output_unit_1_to_18.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[2].flow.egress_node, output_unit_1_to_18.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node_id, output_unit_1_to_18.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node, output_unit_1_to_18.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[2].flow.vnet_id, output_unit_1_to_18.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[2].occupied, output_unit_1_to_18.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`1`[3].flow.egress_node_id, output_unit_1_to_18.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[3].flow.egress_node, output_unit_1_to_18.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node_id, output_unit_1_to_18.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node, output_unit_1_to_18.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[3].flow.vnet_id, output_unit_1_to_18.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[3].occupied, output_unit_1_to_18.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`1`[4].flow.egress_node_id, output_unit_1_to_18.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[4].flow.egress_node, output_unit_1_to_18.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node_id, output_unit_1_to_18.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node, output_unit_1_to_18.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[4].flow.vnet_id, output_unit_1_to_18.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[4].occupied, output_unit_1_to_18.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`1`[5].flow.egress_node_id, output_unit_1_to_18.io.channel_status[5].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[5].flow.egress_node, output_unit_1_to_18.io.channel_status[5].flow.egress_node
connect vc_allocator.io.channel_status.`1`[5].flow.ingress_node_id, output_unit_1_to_18.io.channel_status[5].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[5].flow.ingress_node, output_unit_1_to_18.io.channel_status[5].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[5].flow.vnet_id, output_unit_1_to_18.io.channel_status[5].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[5].occupied, output_unit_1_to_18.io.channel_status[5].occupied
connect vc_allocator.io.channel_status.`1`[6].flow.egress_node_id, output_unit_1_to_18.io.channel_status[6].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[6].flow.egress_node, output_unit_1_to_18.io.channel_status[6].flow.egress_node
connect vc_allocator.io.channel_status.`1`[6].flow.ingress_node_id, output_unit_1_to_18.io.channel_status[6].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[6].flow.ingress_node, output_unit_1_to_18.io.channel_status[6].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[6].flow.vnet_id, output_unit_1_to_18.io.channel_status[6].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[6].occupied, output_unit_1_to_18.io.channel_status[6].occupied
connect vc_allocator.io.channel_status.`1`[7].flow.egress_node_id, output_unit_1_to_18.io.channel_status[7].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[7].flow.egress_node, output_unit_1_to_18.io.channel_status[7].flow.egress_node
connect vc_allocator.io.channel_status.`1`[7].flow.ingress_node_id, output_unit_1_to_18.io.channel_status[7].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[7].flow.ingress_node, output_unit_1_to_18.io.channel_status[7].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[7].flow.vnet_id, output_unit_1_to_18.io.channel_status[7].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[7].occupied, output_unit_1_to_18.io.channel_status[7].occupied
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, output_unit_2_to_23.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, output_unit_2_to_23.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, output_unit_2_to_23.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, output_unit_2_to_23.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, output_unit_2_to_23.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[0].occupied, output_unit_2_to_23.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`2`[1].flow.egress_node_id, output_unit_2_to_23.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[1].flow.egress_node, output_unit_2_to_23.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node_id, output_unit_2_to_23.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node, output_unit_2_to_23.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[1].flow.vnet_id, output_unit_2_to_23.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[1].occupied, output_unit_2_to_23.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`2`[2].flow.egress_node_id, output_unit_2_to_23.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[2].flow.egress_node, output_unit_2_to_23.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node_id, output_unit_2_to_23.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node, output_unit_2_to_23.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[2].flow.vnet_id, output_unit_2_to_23.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[2].occupied, output_unit_2_to_23.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`2`[3].flow.egress_node_id, output_unit_2_to_23.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[3].flow.egress_node, output_unit_2_to_23.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node_id, output_unit_2_to_23.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node, output_unit_2_to_23.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[3].flow.vnet_id, output_unit_2_to_23.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[3].occupied, output_unit_2_to_23.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`2`[4].flow.egress_node_id, output_unit_2_to_23.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[4].flow.egress_node, output_unit_2_to_23.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node_id, output_unit_2_to_23.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node, output_unit_2_to_23.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[4].flow.vnet_id, output_unit_2_to_23.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[4].occupied, output_unit_2_to_23.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`2`[5].flow.egress_node_id, output_unit_2_to_23.io.channel_status[5].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[5].flow.egress_node, output_unit_2_to_23.io.channel_status[5].flow.egress_node
connect vc_allocator.io.channel_status.`2`[5].flow.ingress_node_id, output_unit_2_to_23.io.channel_status[5].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[5].flow.ingress_node, output_unit_2_to_23.io.channel_status[5].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[5].flow.vnet_id, output_unit_2_to_23.io.channel_status[5].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[5].occupied, output_unit_2_to_23.io.channel_status[5].occupied
connect vc_allocator.io.channel_status.`2`[6].flow.egress_node_id, output_unit_2_to_23.io.channel_status[6].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[6].flow.egress_node, output_unit_2_to_23.io.channel_status[6].flow.egress_node
connect vc_allocator.io.channel_status.`2`[6].flow.ingress_node_id, output_unit_2_to_23.io.channel_status[6].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[6].flow.ingress_node, output_unit_2_to_23.io.channel_status[6].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[6].flow.vnet_id, output_unit_2_to_23.io.channel_status[6].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[6].occupied, output_unit_2_to_23.io.channel_status[6].occupied
connect vc_allocator.io.channel_status.`2`[7].flow.egress_node_id, output_unit_2_to_23.io.channel_status[7].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[7].flow.egress_node, output_unit_2_to_23.io.channel_status[7].flow.egress_node
connect vc_allocator.io.channel_status.`2`[7].flow.ingress_node_id, output_unit_2_to_23.io.channel_status[7].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[7].flow.ingress_node, output_unit_2_to_23.io.channel_status[7].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[7].flow.vnet_id, output_unit_2_to_23.io.channel_status[7].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[7].occupied, output_unit_2_to_23.io.channel_status[7].occupied
connect input_unit_0_from_3.io.out_credit_available.`0`[0], output_unit_0_to_3.io.credit_available[0]
connect input_unit_0_from_3.io.out_credit_available.`0`[1], output_unit_0_to_3.io.credit_available[1]
connect input_unit_0_from_3.io.out_credit_available.`0`[2], output_unit_0_to_3.io.credit_available[2]
connect input_unit_0_from_3.io.out_credit_available.`0`[3], output_unit_0_to_3.io.credit_available[3]
connect input_unit_0_from_3.io.out_credit_available.`0`[4], output_unit_0_to_3.io.credit_available[4]
connect input_unit_0_from_3.io.out_credit_available.`0`[5], output_unit_0_to_3.io.credit_available[5]
connect input_unit_0_from_3.io.out_credit_available.`0`[6], output_unit_0_to_3.io.credit_available[6]
connect input_unit_0_from_3.io.out_credit_available.`0`[7], output_unit_0_to_3.io.credit_available[7]
connect input_unit_0_from_3.io.out_credit_available.`1`[0], output_unit_1_to_18.io.credit_available[0]
connect input_unit_0_from_3.io.out_credit_available.`1`[1], output_unit_1_to_18.io.credit_available[1]
connect input_unit_0_from_3.io.out_credit_available.`1`[2], output_unit_1_to_18.io.credit_available[2]
connect input_unit_0_from_3.io.out_credit_available.`1`[3], output_unit_1_to_18.io.credit_available[3]
connect input_unit_0_from_3.io.out_credit_available.`1`[4], output_unit_1_to_18.io.credit_available[4]
connect input_unit_0_from_3.io.out_credit_available.`1`[5], output_unit_1_to_18.io.credit_available[5]
connect input_unit_0_from_3.io.out_credit_available.`1`[6], output_unit_1_to_18.io.credit_available[6]
connect input_unit_0_from_3.io.out_credit_available.`1`[7], output_unit_1_to_18.io.credit_available[7]
connect input_unit_0_from_3.io.out_credit_available.`2`[0], output_unit_2_to_23.io.credit_available[0]
connect input_unit_0_from_3.io.out_credit_available.`2`[1], output_unit_2_to_23.io.credit_available[1]
connect input_unit_0_from_3.io.out_credit_available.`2`[2], output_unit_2_to_23.io.credit_available[2]
connect input_unit_0_from_3.io.out_credit_available.`2`[3], output_unit_2_to_23.io.credit_available[3]
connect input_unit_0_from_3.io.out_credit_available.`2`[4], output_unit_2_to_23.io.credit_available[4]
connect input_unit_0_from_3.io.out_credit_available.`2`[5], output_unit_2_to_23.io.credit_available[5]
connect input_unit_0_from_3.io.out_credit_available.`2`[6], output_unit_2_to_23.io.credit_available[6]
connect input_unit_0_from_3.io.out_credit_available.`2`[7], output_unit_2_to_23.io.credit_available[7]
connect input_unit_1_from_18.io.out_credit_available.`0`[0], output_unit_0_to_3.io.credit_available[0]
connect input_unit_1_from_18.io.out_credit_available.`0`[1], output_unit_0_to_3.io.credit_available[1]
connect input_unit_1_from_18.io.out_credit_available.`0`[2], output_unit_0_to_3.io.credit_available[2]
connect input_unit_1_from_18.io.out_credit_available.`0`[3], output_unit_0_to_3.io.credit_available[3]
connect input_unit_1_from_18.io.out_credit_available.`0`[4], output_unit_0_to_3.io.credit_available[4]
connect input_unit_1_from_18.io.out_credit_available.`0`[5], output_unit_0_to_3.io.credit_available[5]
connect input_unit_1_from_18.io.out_credit_available.`0`[6], output_unit_0_to_3.io.credit_available[6]
connect input_unit_1_from_18.io.out_credit_available.`0`[7], output_unit_0_to_3.io.credit_available[7]
connect input_unit_1_from_18.io.out_credit_available.`1`[0], output_unit_1_to_18.io.credit_available[0]
connect input_unit_1_from_18.io.out_credit_available.`1`[1], output_unit_1_to_18.io.credit_available[1]
connect input_unit_1_from_18.io.out_credit_available.`1`[2], output_unit_1_to_18.io.credit_available[2]
connect input_unit_1_from_18.io.out_credit_available.`1`[3], output_unit_1_to_18.io.credit_available[3]
connect input_unit_1_from_18.io.out_credit_available.`1`[4], output_unit_1_to_18.io.credit_available[4]
connect input_unit_1_from_18.io.out_credit_available.`1`[5], output_unit_1_to_18.io.credit_available[5]
connect input_unit_1_from_18.io.out_credit_available.`1`[6], output_unit_1_to_18.io.credit_available[6]
connect input_unit_1_from_18.io.out_credit_available.`1`[7], output_unit_1_to_18.io.credit_available[7]
connect input_unit_1_from_18.io.out_credit_available.`2`[0], output_unit_2_to_23.io.credit_available[0]
connect input_unit_1_from_18.io.out_credit_available.`2`[1], output_unit_2_to_23.io.credit_available[1]
connect input_unit_1_from_18.io.out_credit_available.`2`[2], output_unit_2_to_23.io.credit_available[2]
connect input_unit_1_from_18.io.out_credit_available.`2`[3], output_unit_2_to_23.io.credit_available[3]
connect input_unit_1_from_18.io.out_credit_available.`2`[4], output_unit_2_to_23.io.credit_available[4]
connect input_unit_1_from_18.io.out_credit_available.`2`[5], output_unit_2_to_23.io.credit_available[5]
connect input_unit_1_from_18.io.out_credit_available.`2`[6], output_unit_2_to_23.io.credit_available[6]
connect input_unit_1_from_18.io.out_credit_available.`2`[7], output_unit_2_to_23.io.credit_available[7]
connect input_unit_2_from_23.io.out_credit_available.`0`[0], output_unit_0_to_3.io.credit_available[0]
connect input_unit_2_from_23.io.out_credit_available.`0`[1], output_unit_0_to_3.io.credit_available[1]
connect input_unit_2_from_23.io.out_credit_available.`0`[2], output_unit_0_to_3.io.credit_available[2]
connect input_unit_2_from_23.io.out_credit_available.`0`[3], output_unit_0_to_3.io.credit_available[3]
connect input_unit_2_from_23.io.out_credit_available.`0`[4], output_unit_0_to_3.io.credit_available[4]
connect input_unit_2_from_23.io.out_credit_available.`0`[5], output_unit_0_to_3.io.credit_available[5]
connect input_unit_2_from_23.io.out_credit_available.`0`[6], output_unit_0_to_3.io.credit_available[6]
connect input_unit_2_from_23.io.out_credit_available.`0`[7], output_unit_0_to_3.io.credit_available[7]
connect input_unit_2_from_23.io.out_credit_available.`1`[0], output_unit_1_to_18.io.credit_available[0]
connect input_unit_2_from_23.io.out_credit_available.`1`[1], output_unit_1_to_18.io.credit_available[1]
connect input_unit_2_from_23.io.out_credit_available.`1`[2], output_unit_1_to_18.io.credit_available[2]
connect input_unit_2_from_23.io.out_credit_available.`1`[3], output_unit_1_to_18.io.credit_available[3]
connect input_unit_2_from_23.io.out_credit_available.`1`[4], output_unit_1_to_18.io.credit_available[4]
connect input_unit_2_from_23.io.out_credit_available.`1`[5], output_unit_1_to_18.io.credit_available[5]
connect input_unit_2_from_23.io.out_credit_available.`1`[6], output_unit_1_to_18.io.credit_available[6]
connect input_unit_2_from_23.io.out_credit_available.`1`[7], output_unit_1_to_18.io.credit_available[7]
connect input_unit_2_from_23.io.out_credit_available.`2`[0], output_unit_2_to_23.io.credit_available[0]
connect input_unit_2_from_23.io.out_credit_available.`2`[1], output_unit_2_to_23.io.credit_available[1]
connect input_unit_2_from_23.io.out_credit_available.`2`[2], output_unit_2_to_23.io.credit_available[2]
connect input_unit_2_from_23.io.out_credit_available.`2`[3], output_unit_2_to_23.io.credit_available[3]
connect input_unit_2_from_23.io.out_credit_available.`2`[4], output_unit_2_to_23.io.credit_available[4]
connect input_unit_2_from_23.io.out_credit_available.`2`[5], output_unit_2_to_23.io.credit_available[5]
connect input_unit_2_from_23.io.out_credit_available.`2`[6], output_unit_2_to_23.io.credit_available[6]
connect input_unit_2_from_23.io.out_credit_available.`2`[7], output_unit_2_to_23.io.credit_available[7]
connect switch_allocator.io.req.`0`[0], input_unit_0_from_3.io.salloc_req[0]
connect switch_allocator.io.req.`1`[0], input_unit_1_from_18.io.salloc_req[0]
connect switch_allocator.io.req.`2`[0], input_unit_2_from_23.io.salloc_req[0]
connect output_unit_0_to_3.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail
connect output_unit_0_to_3.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc
connect output_unit_0_to_3.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail
connect output_unit_0_to_3.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc
connect output_unit_0_to_3.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail
connect output_unit_0_to_3.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc
connect output_unit_0_to_3.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail
connect output_unit_0_to_3.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc
connect output_unit_0_to_3.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail
connect output_unit_0_to_3.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc
connect output_unit_0_to_3.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail
connect output_unit_0_to_3.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc
connect output_unit_0_to_3.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`0`[6].tail
connect output_unit_0_to_3.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`0`[6].alloc
connect output_unit_0_to_3.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`0`[7].tail
connect output_unit_0_to_3.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`0`[7].alloc
connect output_unit_1_to_18.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail
connect output_unit_1_to_18.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc
connect output_unit_1_to_18.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`1`[1].tail
connect output_unit_1_to_18.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`1`[1].alloc
connect output_unit_1_to_18.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`1`[2].tail
connect output_unit_1_to_18.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`1`[2].alloc
connect output_unit_1_to_18.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`1`[3].tail
connect output_unit_1_to_18.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`1`[3].alloc
connect output_unit_1_to_18.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`1`[4].tail
connect output_unit_1_to_18.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`1`[4].alloc
connect output_unit_1_to_18.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`1`[5].tail
connect output_unit_1_to_18.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`1`[5].alloc
connect output_unit_1_to_18.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`1`[6].tail
connect output_unit_1_to_18.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`1`[6].alloc
connect output_unit_1_to_18.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`1`[7].tail
connect output_unit_1_to_18.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`1`[7].alloc
connect output_unit_2_to_23.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail
connect output_unit_2_to_23.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc
connect output_unit_2_to_23.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`2`[1].tail
connect output_unit_2_to_23.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`2`[1].alloc
connect output_unit_2_to_23.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`2`[2].tail
connect output_unit_2_to_23.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`2`[2].alloc
connect output_unit_2_to_23.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`2`[3].tail
connect output_unit_2_to_23.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`2`[3].alloc
connect output_unit_2_to_23.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`2`[4].tail
connect output_unit_2_to_23.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`2`[4].alloc
connect output_unit_2_to_23.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`2`[5].tail
connect output_unit_2_to_23.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`2`[5].alloc
connect output_unit_2_to_23.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`2`[6].tail
connect output_unit_2_to_23.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`2`[6].alloc
connect output_unit_2_to_23.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`2`[7].tail
connect output_unit_2_to_23.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`2`[7].alloc
connect switch.io.in.`0`[0], input_unit_0_from_3.io.out[0]
connect switch.io.in.`1`[0], input_unit_1_from_18.io.out[0]
connect switch.io.in.`2`[0], input_unit_2_from_23.io.out[0]
connect output_unit_0_to_3.io.in, switch.io.out.`0`
connect output_unit_1_to_18.io.in, switch.io.out.`1`
connect output_unit_2_to_23.io.in, switch.io.out.`2`
reg REG : { `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock
connect REG, switch_allocator.io.switch_sel
connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0]
connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0]
connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0]
connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0]
connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0]
connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0]
connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0]
connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0]
connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0]
connect input_unit_0_from_3.io.block, UInt<1>(0h0)
connect input_unit_1_from_18.io.block, UInt<1>(0h0)
connect input_unit_2_from_23.io.block, UInt<1>(0h0)
connect debugNodeOut.va_stall[0], input_unit_0_from_3.io.debug.va_stall
connect debugNodeOut.va_stall[1], input_unit_1_from_18.io.debug.va_stall
connect debugNodeOut.va_stall[2], input_unit_2_from_23.io.debug.va_stall
connect debugNodeOut.sa_stall[0], input_unit_0_from_3.io.debug.sa_stall
connect debugNodeOut.sa_stall[1], input_unit_1_from_18.io.debug.sa_stall
connect debugNodeOut.sa_stall[2], input_unit_2_from_23.io.debug.sa_stall
regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1))
node _debug_tsc_T_1 = tail(_debug_tsc_T, 1)
connect debug_tsc, _debug_tsc_T_1
regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_sample_T = add(debug_sample, UInt<1>(0h1))
node _debug_sample_T_1 = tail(_debug_sample_T, 1)
connect debug_sample, _debug_sample_T_1
inst plusarg_reader of plusarg_reader_35
node _T = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_1 = tail(_T, 1)
node _T_2 = eq(debug_sample, _T_1)
when _T_2 :
connect debug_sample, UInt<1>(0h0)
regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid)
node _util_ctr_T_1 = tail(_util_ctr_T, 1)
connect util_ctr, _util_ctr_T_1
node _fired_T = or(fired, destNodesIn.flit[0].valid)
connect fired, _fired_T
node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_5 = tail(_T_4, 1)
node _T_6 = eq(debug_sample, _T_5)
node _T_7 = and(_T_3, _T_6)
node _T_8 = and(_T_7, fired)
when _T_8 :
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "nocsample %d 3 19 %d\n", debug_tsc, util_ctr) : printf
connect fired, destNodesIn.flit[0].valid
regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_2 = add(util_ctr_1, destNodesIn_1.flit[0].valid)
node _util_ctr_T_3 = tail(_util_ctr_T_2, 1)
connect util_ctr_1, _util_ctr_T_3
node _fired_T_1 = or(fired_1, destNodesIn_1.flit[0].valid)
connect fired_1, _fired_T_1
node _T_11 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_12 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_13 = tail(_T_12, 1)
node _T_14 = eq(debug_sample, _T_13)
node _T_15 = and(_T_11, _T_14)
node _T_16 = and(_T_15, fired_1)
when _T_16 :
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
printf(clock, UInt<1>(0h1), "nocsample %d 18 19 %d\n", debug_tsc, util_ctr_1) : printf_1
connect fired_1, destNodesIn_1.flit[0].valid
regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_4 = add(util_ctr_2, destNodesIn_2.flit[0].valid)
node _util_ctr_T_5 = tail(_util_ctr_T_4, 1)
connect util_ctr_2, _util_ctr_T_5
node _fired_T_2 = or(fired_2, destNodesIn_2.flit[0].valid)
connect fired_2, _fired_T_2
node _T_19 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_20 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = eq(debug_sample, _T_21)
node _T_23 = and(_T_19, _T_22)
node _T_24 = and(_T_23, fired_2)
when _T_24 :
node _T_25 = asUInt(reset)
node _T_26 = eq(_T_25, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "nocsample %d 23 19 %d\n", debug_tsc, util_ctr_2) : printf_2
connect fired_2, destNodesIn_2.flit[0].valid | module Router_17( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_2_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_5; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_6; // @[Router.scala:136:32]
wire _route_computer_io_resp_2_vc_sel_0_7; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_5; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_6; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_7; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_2_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_2_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_2_3; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_2_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_2_5; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_2_6; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_2_7; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_3; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_5; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_6; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_1_7; // @[Router.scala:136:32]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_7; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_6; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_7; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_2_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_3_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_4_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_5_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_6_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_7_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_2_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_3_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_4_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_5_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_6_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_7_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_2_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_3_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_5_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_6_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_7_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_2_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_3_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_5_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_6_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_7_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _output_unit_2_to_23_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_2_to_23_io_credit_available_2; // @[Router.scala:122:13]
wire _output_unit_2_to_23_io_credit_available_3; // @[Router.scala:122:13]
wire _output_unit_2_to_23_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_2_to_23_io_credit_available_5; // @[Router.scala:122:13]
wire _output_unit_2_to_23_io_credit_available_6; // @[Router.scala:122:13]
wire _output_unit_2_to_23_io_credit_available_7; // @[Router.scala:122:13]
wire _output_unit_2_to_23_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_2_to_23_io_channel_status_2_occupied; // @[Router.scala:122:13]
wire _output_unit_2_to_23_io_channel_status_3_occupied; // @[Router.scala:122:13]
wire _output_unit_2_to_23_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire _output_unit_2_to_23_io_channel_status_5_occupied; // @[Router.scala:122:13]
wire _output_unit_2_to_23_io_channel_status_6_occupied; // @[Router.scala:122:13]
wire _output_unit_2_to_23_io_channel_status_7_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_18_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_1_to_18_io_credit_available_2; // @[Router.scala:122:13]
wire _output_unit_1_to_18_io_credit_available_3; // @[Router.scala:122:13]
wire _output_unit_1_to_18_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_1_to_18_io_credit_available_5; // @[Router.scala:122:13]
wire _output_unit_1_to_18_io_credit_available_6; // @[Router.scala:122:13]
wire _output_unit_1_to_18_io_credit_available_7; // @[Router.scala:122:13]
wire _output_unit_1_to_18_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_18_io_channel_status_2_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_18_io_channel_status_3_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_18_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_18_io_channel_status_5_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_18_io_channel_status_6_occupied; // @[Router.scala:122:13]
wire _output_unit_1_to_18_io_channel_status_7_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_3_io_credit_available_4; // @[Router.scala:122:13]
wire _output_unit_0_to_3_io_credit_available_5; // @[Router.scala:122:13]
wire _output_unit_0_to_3_io_credit_available_6; // @[Router.scala:122:13]
wire _output_unit_0_to_3_io_credit_available_7; // @[Router.scala:122:13]
wire _output_unit_0_to_3_io_channel_status_4_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_3_io_channel_status_5_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_3_io_channel_status_6_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_3_io_channel_status_7_occupied; // @[Router.scala:122:13]
wire [2:0] _input_unit_2_from_23_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_2_from_23_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_2_from_23_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_23_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_2_from_23_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_23_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_2_from_23_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_2_from_23_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_2_from_23_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_2_from_23_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_23_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_2_from_23_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_2_from_23_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_2_from_23_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_18_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_18_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_18_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_18_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_18_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_18_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_1_from_18_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_1_from_18_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_18_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_18_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_18_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_1_from_18_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_1_from_18_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_1_from_18_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_3_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_3_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_3_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_3_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_3_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_3_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_2_3; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_3_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_3_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_3_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_3_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_3_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_3_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_3_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_3_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_3_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_18_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_23_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg REG_2_0_2_0; // @[Router.scala:178:14]
reg REG_2_0_1_0; // @[Router.scala:178:14]
reg REG_2_0_0_0; // @[Router.scala:178:14]
reg REG_1_0_2_0; // @[Router.scala:178:14]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_2_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg REG_0_0_0_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to this FIRRTL code module PeripheryBus_cbus :
output auto : { coupler_to_prci_ctrl_fixer_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bootrom_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_debug_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_plic_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_clint_fragmenter_anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_bus_named_pbus_bus_xing_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, coupler_to_l2_ctrl_buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, fixedClockNode_anon_out_5 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_4 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_3 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_2 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_1 : { clock : Clock, reset : Reset}, fixedClockNode_anon_out_0 : { clock : Clock, reset : Reset}, flip cbus_clock_groups_in : { member : { cbus_0 : { clock : Clock, reset : Reset}}}, flip bus_xing_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
input custom_boot : UInt<1>
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst cbus_clock_groups of ClockGroupAggregator_cbus
inst clockGroup of ClockGroup_3
inst fixedClockNode of FixedClockBroadcast_7_1
inst broadcast of BundleBridgeNexus_NoOutput_3
inst fixer of TLFIFOFixer_2
connect fixer.clock, childClock
connect fixer.reset, childReset
inst in_xbar of TLXbar_cbus_in_i2_o1_a29d64s8k1z4u
connect in_xbar.clock, childClock
connect in_xbar.reset, childReset
inst out_xbar of TLXbar_cbus_out_i1_o8_a29d64s8k1z4u
connect out_xbar.clock, childClock
connect out_xbar.reset, childReset
inst buffer of TLBuffer_a29d64s8k1z4u
connect buffer.clock, childClock
connect buffer.reset, childReset
inst atomics of TLAtomicAutomata_cbus
connect atomics.clock, childClock
connect atomics.reset, childReset
inst wrapped_error_device of ErrorDeviceWrapper
connect wrapped_error_device.clock, childClock
connect wrapped_error_device.reset, childReset
inst coupler_to_l2_ctrl of TLInterconnectCoupler_cbus_to_l2_ctrl
connect coupler_to_l2_ctrl.clock, childClock
connect coupler_to_l2_ctrl.reset, childReset
inst buffer_1 of TLBuffer_a29d64s7k1z4u
connect buffer_1.clock, childClock
connect buffer_1.reset, childReset
inst coupler_to_bus_named_pbus of TLInterconnectCoupler_cbus_to_bus_named_pbus
connect coupler_to_bus_named_pbus.clock, childClock
connect coupler_to_bus_named_pbus.reset, childReset
inst coupler_to_clint of TLInterconnectCoupler_cbus_to_clint
connect coupler_to_clint.clock, childClock
connect coupler_to_clint.reset, childReset
inst coupler_to_plic of TLInterconnectCoupler_cbus_to_plic
connect coupler_to_plic.clock, childClock
connect coupler_to_plic.reset, childReset
inst coupler_to_debug of TLInterconnectCoupler_cbus_to_debug
connect coupler_to_debug.clock, childClock
connect coupler_to_debug.reset, childReset
inst coupler_to_rockettile of TLInterconnectCoupler_cbus_to_rockettile
connect coupler_to_rockettile.clock, childClock
connect coupler_to_rockettile.reset, childReset
inst coupler_to_rockettile_1 of TLInterconnectCoupler_cbus_to_rockettile_1
connect coupler_to_rockettile_1.clock, childClock
connect coupler_to_rockettile_1.reset, childReset
inst coupler_to_boom_tile of TLInterconnectCoupler_cbus_to_boom_tile
connect coupler_to_boom_tile.clock, childClock
connect coupler_to_boom_tile.reset, childReset
inst coupler_to_boom_tile_1 of TLInterconnectCoupler_cbus_to_boom_tile_1
connect coupler_to_boom_tile_1.clock, childClock
connect coupler_to_boom_tile_1.reset, childReset
inst coupler_to_bootrom of TLInterconnectCoupler_cbus_to_bootrom
connect coupler_to_bootrom.clock, childClock
connect coupler_to_bootrom.reset, childReset
inst coupler_from_port_named_custom_boot_pin of TLInterconnectCoupler_cbus_from_port_named_custom_boot_pin
connect coupler_from_port_named_custom_boot_pin.clock, childClock
connect coupler_from_port_named_custom_boot_pin.reset, childReset
inst coupler_to_prci_ctrl of TLInterconnectCoupler_cbus_to_prci_ctrl
connect coupler_to_prci_ctrl.clock, childClock
connect coupler_to_prci_ctrl.reset, childReset
wire clockSinkNodeIn : { clock : Clock, reset : Reset}
invalidate clockSinkNodeIn.reset
invalidate clockSinkNodeIn.clock
wire bus_xingOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate bus_xingOut.d.bits.corrupt
invalidate bus_xingOut.d.bits.data
invalidate bus_xingOut.d.bits.denied
invalidate bus_xingOut.d.bits.sink
invalidate bus_xingOut.d.bits.source
invalidate bus_xingOut.d.bits.size
invalidate bus_xingOut.d.bits.param
invalidate bus_xingOut.d.bits.opcode
invalidate bus_xingOut.d.valid
invalidate bus_xingOut.d.ready
invalidate bus_xingOut.a.bits.corrupt
invalidate bus_xingOut.a.bits.data
invalidate bus_xingOut.a.bits.mask
invalidate bus_xingOut.a.bits.address
invalidate bus_xingOut.a.bits.source
invalidate bus_xingOut.a.bits.size
invalidate bus_xingOut.a.bits.param
invalidate bus_xingOut.a.bits.opcode
invalidate bus_xingOut.a.valid
invalidate bus_xingOut.a.ready
wire bus_xingIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate bus_xingIn.d.bits.corrupt
invalidate bus_xingIn.d.bits.data
invalidate bus_xingIn.d.bits.denied
invalidate bus_xingIn.d.bits.sink
invalidate bus_xingIn.d.bits.source
invalidate bus_xingIn.d.bits.size
invalidate bus_xingIn.d.bits.param
invalidate bus_xingIn.d.bits.opcode
invalidate bus_xingIn.d.valid
invalidate bus_xingIn.d.ready
invalidate bus_xingIn.a.bits.corrupt
invalidate bus_xingIn.a.bits.data
invalidate bus_xingIn.a.bits.mask
invalidate bus_xingIn.a.bits.address
invalidate bus_xingIn.a.bits.source
invalidate bus_xingIn.a.bits.size
invalidate bus_xingIn.a.bits.param
invalidate bus_xingIn.a.bits.opcode
invalidate bus_xingIn.a.valid
invalidate bus_xingIn.a.ready
connect bus_xingOut, bus_xingIn
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect clockGroup.auto.in, cbus_clock_groups.auto.out
connect fixedClockNode.auto.anon_in, clockGroup.auto.out
connect clockSinkNodeIn, fixedClockNode.auto.anon_out_0
connect out_xbar.auto.anon_in, fixer.auto.anon_out
connect atomics.auto.in, in_xbar.auto.anon_out
connect wrapped_error_device.auto.buffer_in, out_xbar.auto.anon_out_0
connect coupler_to_l2_ctrl.auto.tl_in, out_xbar.auto.anon_out_1
connect coupler_to_bus_named_pbus.auto.widget_anon_in, out_xbar.auto.anon_out_2
connect coupler_to_clint.auto.tl_in, out_xbar.auto.anon_out_3
connect coupler_to_plic.auto.tl_in, out_xbar.auto.anon_out_4
connect coupler_to_debug.auto.tl_in, out_xbar.auto.anon_out_5
connect coupler_to_bootrom.auto.tl_in, out_xbar.auto.anon_out_6
connect coupler_to_prci_ctrl.auto.tl_in, out_xbar.auto.anon_out_7
connect fixer.auto.anon_in, buffer.auto.out
connect buffer.auto.in, atomics.auto.out
connect in_xbar.auto.anon_in_0, buffer_1.auto.out
connect buffer_1.auto.in, bus_xingOut
connect coupler_from_port_named_custom_boot_pin.auto.tl_in, nodeOut
connect in_xbar.auto.anon_in_1, coupler_from_port_named_custom_boot_pin.auto.tl_out
connect bus_xingIn, auto.bus_xing_in
connect cbus_clock_groups.auto.in, auto.cbus_clock_groups_in
connect auto.fixedClockNode_anon_out_0, fixedClockNode.auto.anon_out_1
connect auto.fixedClockNode_anon_out_1, fixedClockNode.auto.anon_out_2
connect auto.fixedClockNode_anon_out_2, fixedClockNode.auto.anon_out_3
connect auto.fixedClockNode_anon_out_3, fixedClockNode.auto.anon_out_4
connect auto.fixedClockNode_anon_out_4, fixedClockNode.auto.anon_out_5
connect auto.fixedClockNode_anon_out_5, fixedClockNode.auto.anon_out_6
connect coupler_to_l2_ctrl.auto.buffer_out.d, auto.coupler_to_l2_ctrl_buffer_out.d
connect auto.coupler_to_l2_ctrl_buffer_out.a.bits, coupler_to_l2_ctrl.auto.buffer_out.a.bits
connect auto.coupler_to_l2_ctrl_buffer_out.a.valid, coupler_to_l2_ctrl.auto.buffer_out.a.valid
connect coupler_to_l2_ctrl.auto.buffer_out.a.ready, auto.coupler_to_l2_ctrl_buffer_out.a.ready
connect coupler_to_bus_named_pbus.auto.bus_xing_out.d, auto.coupler_to_bus_named_pbus_bus_xing_out.d
connect auto.coupler_to_bus_named_pbus_bus_xing_out.a.bits, coupler_to_bus_named_pbus.auto.bus_xing_out.a.bits
connect auto.coupler_to_bus_named_pbus_bus_xing_out.a.valid, coupler_to_bus_named_pbus.auto.bus_xing_out.a.valid
connect coupler_to_bus_named_pbus.auto.bus_xing_out.a.ready, auto.coupler_to_bus_named_pbus_bus_xing_out.a.ready
connect coupler_to_clint.auto.fragmenter_anon_out.d, auto.coupler_to_clint_fragmenter_anon_out.d
connect auto.coupler_to_clint_fragmenter_anon_out.a.bits, coupler_to_clint.auto.fragmenter_anon_out.a.bits
connect auto.coupler_to_clint_fragmenter_anon_out.a.valid, coupler_to_clint.auto.fragmenter_anon_out.a.valid
connect coupler_to_clint.auto.fragmenter_anon_out.a.ready, auto.coupler_to_clint_fragmenter_anon_out.a.ready
connect coupler_to_plic.auto.fragmenter_anon_out.d, auto.coupler_to_plic_fragmenter_anon_out.d
connect auto.coupler_to_plic_fragmenter_anon_out.a.bits, coupler_to_plic.auto.fragmenter_anon_out.a.bits
connect auto.coupler_to_plic_fragmenter_anon_out.a.valid, coupler_to_plic.auto.fragmenter_anon_out.a.valid
connect coupler_to_plic.auto.fragmenter_anon_out.a.ready, auto.coupler_to_plic_fragmenter_anon_out.a.ready
connect coupler_to_debug.auto.fragmenter_anon_out.d, auto.coupler_to_debug_fragmenter_anon_out.d
connect auto.coupler_to_debug_fragmenter_anon_out.a.bits, coupler_to_debug.auto.fragmenter_anon_out.a.bits
connect auto.coupler_to_debug_fragmenter_anon_out.a.valid, coupler_to_debug.auto.fragmenter_anon_out.a.valid
connect coupler_to_debug.auto.fragmenter_anon_out.a.ready, auto.coupler_to_debug_fragmenter_anon_out.a.ready
connect coupler_to_bootrom.auto.fragmenter_anon_out.d, auto.coupler_to_bootrom_fragmenter_anon_out.d
connect auto.coupler_to_bootrom_fragmenter_anon_out.a.bits, coupler_to_bootrom.auto.fragmenter_anon_out.a.bits
connect auto.coupler_to_bootrom_fragmenter_anon_out.a.valid, coupler_to_bootrom.auto.fragmenter_anon_out.a.valid
connect coupler_to_bootrom.auto.fragmenter_anon_out.a.ready, auto.coupler_to_bootrom_fragmenter_anon_out.a.ready
connect coupler_to_prci_ctrl.auto.fixer_anon_out.d, auto.coupler_to_prci_ctrl_fixer_anon_out.d
connect auto.coupler_to_prci_ctrl_fixer_anon_out.a.bits, coupler_to_prci_ctrl.auto.fixer_anon_out.a.bits
connect auto.coupler_to_prci_ctrl_fixer_anon_out.a.valid, coupler_to_prci_ctrl.auto.fixer_anon_out.a.valid
connect coupler_to_prci_ctrl.auto.fixer_anon_out.a.ready, auto.coupler_to_prci_ctrl_fixer_anon_out.a.ready
regreset state : UInt<3>, childClock, childReset, UInt<3>(0h0)
connect nodeOut.a.valid, UInt<1>(0h0)
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
connect nodeOut.d.ready, UInt<1>(0h1)
node _T = eq(UInt<3>(0h0), state)
when _T :
when custom_boot :
connect state, UInt<3>(0h1)
else :
node _T_1 = eq(UInt<3>(0h1), state)
when _T_1 :
connect nodeOut.a.valid, UInt<1>(0h1)
node _nodeOut_a_bits_legal_T = leq(UInt<1>(0h0), UInt<2>(0h2))
node _nodeOut_a_bits_legal_T_1 = leq(UInt<2>(0h2), UInt<4>(0hc))
node _nodeOut_a_bits_legal_T_2 = and(_nodeOut_a_bits_legal_T, _nodeOut_a_bits_legal_T_1)
node _nodeOut_a_bits_legal_T_3 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_2)
node _nodeOut_a_bits_legal_T_4 = xor(UInt<13>(0h1000), UInt<14>(0h3000))
node _nodeOut_a_bits_legal_T_5 = cvt(_nodeOut_a_bits_legal_T_4)
node _nodeOut_a_bits_legal_T_6 = and(_nodeOut_a_bits_legal_T_5, asSInt(UInt<30>(0h1a113000)))
node _nodeOut_a_bits_legal_T_7 = asSInt(_nodeOut_a_bits_legal_T_6)
node _nodeOut_a_bits_legal_T_8 = eq(_nodeOut_a_bits_legal_T_7, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_9 = and(_nodeOut_a_bits_legal_T_3, _nodeOut_a_bits_legal_T_8)
node _nodeOut_a_bits_legal_T_10 = leq(UInt<1>(0h0), UInt<2>(0h2))
node _nodeOut_a_bits_legal_T_11 = leq(UInt<2>(0h2), UInt<3>(0h6))
node _nodeOut_a_bits_legal_T_12 = and(_nodeOut_a_bits_legal_T_10, _nodeOut_a_bits_legal_T_11)
node _nodeOut_a_bits_legal_T_13 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_12)
node _nodeOut_a_bits_legal_T_14 = xor(UInt<13>(0h1000), UInt<1>(0h0))
node _nodeOut_a_bits_legal_T_15 = cvt(_nodeOut_a_bits_legal_T_14)
node _nodeOut_a_bits_legal_T_16 = and(_nodeOut_a_bits_legal_T_15, asSInt(UInt<30>(0h1a112000)))
node _nodeOut_a_bits_legal_T_17 = asSInt(_nodeOut_a_bits_legal_T_16)
node _nodeOut_a_bits_legal_T_18 = eq(_nodeOut_a_bits_legal_T_17, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_19 = xor(UInt<13>(0h1000), UInt<21>(0h100000))
node _nodeOut_a_bits_legal_T_20 = cvt(_nodeOut_a_bits_legal_T_19)
node _nodeOut_a_bits_legal_T_21 = and(_nodeOut_a_bits_legal_T_20, asSInt(UInt<30>(0h1a103000)))
node _nodeOut_a_bits_legal_T_22 = asSInt(_nodeOut_a_bits_legal_T_21)
node _nodeOut_a_bits_legal_T_23 = eq(_nodeOut_a_bits_legal_T_22, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_24 = xor(UInt<13>(0h1000), UInt<26>(0h2000000))
node _nodeOut_a_bits_legal_T_25 = cvt(_nodeOut_a_bits_legal_T_24)
node _nodeOut_a_bits_legal_T_26 = and(_nodeOut_a_bits_legal_T_25, asSInt(UInt<30>(0h1a110000)))
node _nodeOut_a_bits_legal_T_27 = asSInt(_nodeOut_a_bits_legal_T_26)
node _nodeOut_a_bits_legal_T_28 = eq(_nodeOut_a_bits_legal_T_27, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_29 = xor(UInt<13>(0h1000), UInt<26>(0h2010000))
node _nodeOut_a_bits_legal_T_30 = cvt(_nodeOut_a_bits_legal_T_29)
node _nodeOut_a_bits_legal_T_31 = and(_nodeOut_a_bits_legal_T_30, asSInt(UInt<30>(0h1a113000)))
node _nodeOut_a_bits_legal_T_32 = asSInt(_nodeOut_a_bits_legal_T_31)
node _nodeOut_a_bits_legal_T_33 = eq(_nodeOut_a_bits_legal_T_32, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_34 = xor(UInt<13>(0h1000), UInt<28>(0h8000000))
node _nodeOut_a_bits_legal_T_35 = cvt(_nodeOut_a_bits_legal_T_34)
node _nodeOut_a_bits_legal_T_36 = and(_nodeOut_a_bits_legal_T_35, asSInt(UInt<30>(0h18000000)))
node _nodeOut_a_bits_legal_T_37 = asSInt(_nodeOut_a_bits_legal_T_36)
node _nodeOut_a_bits_legal_T_38 = eq(_nodeOut_a_bits_legal_T_37, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_39 = xor(UInt<13>(0h1000), UInt<29>(0h10000000))
node _nodeOut_a_bits_legal_T_40 = cvt(_nodeOut_a_bits_legal_T_39)
node _nodeOut_a_bits_legal_T_41 = and(_nodeOut_a_bits_legal_T_40, asSInt(UInt<30>(0h1a113000)))
node _nodeOut_a_bits_legal_T_42 = asSInt(_nodeOut_a_bits_legal_T_41)
node _nodeOut_a_bits_legal_T_43 = eq(_nodeOut_a_bits_legal_T_42, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_44 = or(_nodeOut_a_bits_legal_T_18, _nodeOut_a_bits_legal_T_23)
node _nodeOut_a_bits_legal_T_45 = or(_nodeOut_a_bits_legal_T_44, _nodeOut_a_bits_legal_T_28)
node _nodeOut_a_bits_legal_T_46 = or(_nodeOut_a_bits_legal_T_45, _nodeOut_a_bits_legal_T_33)
node _nodeOut_a_bits_legal_T_47 = or(_nodeOut_a_bits_legal_T_46, _nodeOut_a_bits_legal_T_38)
node _nodeOut_a_bits_legal_T_48 = or(_nodeOut_a_bits_legal_T_47, _nodeOut_a_bits_legal_T_43)
node _nodeOut_a_bits_legal_T_49 = and(_nodeOut_a_bits_legal_T_13, _nodeOut_a_bits_legal_T_48)
node _nodeOut_a_bits_legal_T_50 = or(UInt<1>(0h0), UInt<1>(0h0))
node _nodeOut_a_bits_legal_T_51 = xor(UInt<13>(0h1000), UInt<17>(0h10000))
node _nodeOut_a_bits_legal_T_52 = cvt(_nodeOut_a_bits_legal_T_51)
node _nodeOut_a_bits_legal_T_53 = and(_nodeOut_a_bits_legal_T_52, asSInt(UInt<30>(0h1a110000)))
node _nodeOut_a_bits_legal_T_54 = asSInt(_nodeOut_a_bits_legal_T_53)
node _nodeOut_a_bits_legal_T_55 = eq(_nodeOut_a_bits_legal_T_54, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_56 = and(_nodeOut_a_bits_legal_T_50, _nodeOut_a_bits_legal_T_55)
node _nodeOut_a_bits_legal_T_57 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_9)
node _nodeOut_a_bits_legal_T_58 = or(_nodeOut_a_bits_legal_T_57, _nodeOut_a_bits_legal_T_49)
node nodeOut_a_bits_legal = or(_nodeOut_a_bits_legal_T_58, _nodeOut_a_bits_legal_T_56)
wire nodeOut_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect nodeOut_a_bits_a.opcode, UInt<1>(0h0)
connect nodeOut_a_bits_a.param, UInt<1>(0h0)
connect nodeOut_a_bits_a.size, UInt<2>(0h2)
connect nodeOut_a_bits_a.source, UInt<1>(0h0)
connect nodeOut_a_bits_a.address, UInt<13>(0h1000)
node _nodeOut_a_bits_a_mask_sizeOH_T = or(UInt<2>(0h2), UInt<3>(0h0))
node nodeOut_a_bits_a_mask_sizeOH_shiftAmount = bits(_nodeOut_a_bits_a_mask_sizeOH_T, 1, 0)
node _nodeOut_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), nodeOut_a_bits_a_mask_sizeOH_shiftAmount)
node _nodeOut_a_bits_a_mask_sizeOH_T_2 = bits(_nodeOut_a_bits_a_mask_sizeOH_T_1, 2, 0)
node nodeOut_a_bits_a_mask_sizeOH = or(_nodeOut_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node nodeOut_a_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<2>(0h2), UInt<2>(0h3))
node nodeOut_a_bits_a_mask_sub_sub_size = bits(nodeOut_a_bits_a_mask_sizeOH, 2, 2)
node nodeOut_a_bits_a_mask_sub_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), nodeOut_a_bits_a_mask_sub_sub_nbit)
node _nodeOut_a_bits_a_mask_sub_sub_acc_T = and(nodeOut_a_bits_a_mask_sub_sub_size, nodeOut_a_bits_a_mask_sub_sub_0_2)
node nodeOut_a_bits_a_mask_sub_sub_0_1 = or(nodeOut_a_bits_a_mask_sub_sub_sub_0_1, _nodeOut_a_bits_a_mask_sub_sub_acc_T)
node nodeOut_a_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_sub_acc_T_1 = and(nodeOut_a_bits_a_mask_sub_sub_size, nodeOut_a_bits_a_mask_sub_sub_1_2)
node nodeOut_a_bits_a_mask_sub_sub_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_sub_0_1, _nodeOut_a_bits_a_mask_sub_sub_acc_T_1)
node nodeOut_a_bits_a_mask_sub_size = bits(nodeOut_a_bits_a_mask_sizeOH, 1, 1)
node nodeOut_a_bits_a_mask_sub_nbit = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_sub_0_2 = and(nodeOut_a_bits_a_mask_sub_sub_0_2, nodeOut_a_bits_a_mask_sub_nbit)
node _nodeOut_a_bits_a_mask_sub_acc_T = and(nodeOut_a_bits_a_mask_sub_size, nodeOut_a_bits_a_mask_sub_0_2)
node nodeOut_a_bits_a_mask_sub_0_1 = or(nodeOut_a_bits_a_mask_sub_sub_0_1, _nodeOut_a_bits_a_mask_sub_acc_T)
node nodeOut_a_bits_a_mask_sub_1_2 = and(nodeOut_a_bits_a_mask_sub_sub_0_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_acc_T_1 = and(nodeOut_a_bits_a_mask_sub_size, nodeOut_a_bits_a_mask_sub_1_2)
node nodeOut_a_bits_a_mask_sub_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_0_1, _nodeOut_a_bits_a_mask_sub_acc_T_1)
node nodeOut_a_bits_a_mask_sub_2_2 = and(nodeOut_a_bits_a_mask_sub_sub_1_2, nodeOut_a_bits_a_mask_sub_nbit)
node _nodeOut_a_bits_a_mask_sub_acc_T_2 = and(nodeOut_a_bits_a_mask_sub_size, nodeOut_a_bits_a_mask_sub_2_2)
node nodeOut_a_bits_a_mask_sub_2_1 = or(nodeOut_a_bits_a_mask_sub_sub_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_2)
node nodeOut_a_bits_a_mask_sub_3_2 = and(nodeOut_a_bits_a_mask_sub_sub_1_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_acc_T_3 = and(nodeOut_a_bits_a_mask_sub_size, nodeOut_a_bits_a_mask_sub_3_2)
node nodeOut_a_bits_a_mask_sub_3_1 = or(nodeOut_a_bits_a_mask_sub_sub_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_3)
node nodeOut_a_bits_a_mask_size = bits(nodeOut_a_bits_a_mask_sizeOH, 0, 0)
node nodeOut_a_bits_a_mask_nbit = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_eq = and(nodeOut_a_bits_a_mask_sub_0_2, nodeOut_a_bits_a_mask_nbit)
node _nodeOut_a_bits_a_mask_acc_T = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq)
node nodeOut_a_bits_a_mask_acc = or(nodeOut_a_bits_a_mask_sub_0_1, _nodeOut_a_bits_a_mask_acc_T)
node nodeOut_a_bits_a_mask_eq_1 = and(nodeOut_a_bits_a_mask_sub_0_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_1 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_1)
node nodeOut_a_bits_a_mask_acc_1 = or(nodeOut_a_bits_a_mask_sub_0_1, _nodeOut_a_bits_a_mask_acc_T_1)
node nodeOut_a_bits_a_mask_eq_2 = and(nodeOut_a_bits_a_mask_sub_1_2, nodeOut_a_bits_a_mask_nbit)
node _nodeOut_a_bits_a_mask_acc_T_2 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_2)
node nodeOut_a_bits_a_mask_acc_2 = or(nodeOut_a_bits_a_mask_sub_1_1, _nodeOut_a_bits_a_mask_acc_T_2)
node nodeOut_a_bits_a_mask_eq_3 = and(nodeOut_a_bits_a_mask_sub_1_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_3 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_3)
node nodeOut_a_bits_a_mask_acc_3 = or(nodeOut_a_bits_a_mask_sub_1_1, _nodeOut_a_bits_a_mask_acc_T_3)
node nodeOut_a_bits_a_mask_eq_4 = and(nodeOut_a_bits_a_mask_sub_2_2, nodeOut_a_bits_a_mask_nbit)
node _nodeOut_a_bits_a_mask_acc_T_4 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_4)
node nodeOut_a_bits_a_mask_acc_4 = or(nodeOut_a_bits_a_mask_sub_2_1, _nodeOut_a_bits_a_mask_acc_T_4)
node nodeOut_a_bits_a_mask_eq_5 = and(nodeOut_a_bits_a_mask_sub_2_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_5 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_5)
node nodeOut_a_bits_a_mask_acc_5 = or(nodeOut_a_bits_a_mask_sub_2_1, _nodeOut_a_bits_a_mask_acc_T_5)
node nodeOut_a_bits_a_mask_eq_6 = and(nodeOut_a_bits_a_mask_sub_3_2, nodeOut_a_bits_a_mask_nbit)
node _nodeOut_a_bits_a_mask_acc_T_6 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_6)
node nodeOut_a_bits_a_mask_acc_6 = or(nodeOut_a_bits_a_mask_sub_3_1, _nodeOut_a_bits_a_mask_acc_T_6)
node nodeOut_a_bits_a_mask_eq_7 = and(nodeOut_a_bits_a_mask_sub_3_2, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_7 = and(nodeOut_a_bits_a_mask_size, nodeOut_a_bits_a_mask_eq_7)
node nodeOut_a_bits_a_mask_acc_7 = or(nodeOut_a_bits_a_mask_sub_3_1, _nodeOut_a_bits_a_mask_acc_T_7)
node nodeOut_a_bits_a_mask_lo_lo = cat(nodeOut_a_bits_a_mask_acc_1, nodeOut_a_bits_a_mask_acc)
node nodeOut_a_bits_a_mask_lo_hi = cat(nodeOut_a_bits_a_mask_acc_3, nodeOut_a_bits_a_mask_acc_2)
node nodeOut_a_bits_a_mask_lo = cat(nodeOut_a_bits_a_mask_lo_hi, nodeOut_a_bits_a_mask_lo_lo)
node nodeOut_a_bits_a_mask_hi_lo = cat(nodeOut_a_bits_a_mask_acc_5, nodeOut_a_bits_a_mask_acc_4)
node nodeOut_a_bits_a_mask_hi_hi = cat(nodeOut_a_bits_a_mask_acc_7, nodeOut_a_bits_a_mask_acc_6)
node nodeOut_a_bits_a_mask_hi = cat(nodeOut_a_bits_a_mask_hi_hi, nodeOut_a_bits_a_mask_hi_lo)
node _nodeOut_a_bits_a_mask_T = cat(nodeOut_a_bits_a_mask_hi, nodeOut_a_bits_a_mask_lo)
connect nodeOut_a_bits_a.mask, _nodeOut_a_bits_a_mask_T
connect nodeOut_a_bits_a.data, UInt<32>(0h80000000)
connect nodeOut_a_bits_a.corrupt, UInt<1>(0h0)
connect nodeOut.a.bits, nodeOut_a_bits_a
node _T_2 = and(nodeOut.a.ready, nodeOut.a.valid)
when _T_2 :
connect state, UInt<3>(0h2)
else :
node _T_3 = eq(UInt<3>(0h2), state)
when _T_3 :
node _T_4 = and(nodeOut.d.ready, nodeOut.d.valid)
when _T_4 :
connect state, UInt<3>(0h3)
else :
node _T_5 = eq(UInt<3>(0h3), state)
when _T_5 :
connect nodeOut.a.valid, UInt<1>(0h1)
node _nodeOut_a_bits_legal_T_59 = leq(UInt<1>(0h0), UInt<2>(0h2))
node _nodeOut_a_bits_legal_T_60 = leq(UInt<2>(0h2), UInt<4>(0hc))
node _nodeOut_a_bits_legal_T_61 = and(_nodeOut_a_bits_legal_T_59, _nodeOut_a_bits_legal_T_60)
node _nodeOut_a_bits_legal_T_62 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_61)
node _nodeOut_a_bits_legal_T_63 = xor(UInt<26>(0h2000000), UInt<14>(0h3000))
node _nodeOut_a_bits_legal_T_64 = cvt(_nodeOut_a_bits_legal_T_63)
node _nodeOut_a_bits_legal_T_65 = and(_nodeOut_a_bits_legal_T_64, asSInt(UInt<30>(0h1a113000)))
node _nodeOut_a_bits_legal_T_66 = asSInt(_nodeOut_a_bits_legal_T_65)
node _nodeOut_a_bits_legal_T_67 = eq(_nodeOut_a_bits_legal_T_66, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_68 = and(_nodeOut_a_bits_legal_T_62, _nodeOut_a_bits_legal_T_67)
node _nodeOut_a_bits_legal_T_69 = leq(UInt<1>(0h0), UInt<2>(0h2))
node _nodeOut_a_bits_legal_T_70 = leq(UInt<2>(0h2), UInt<3>(0h6))
node _nodeOut_a_bits_legal_T_71 = and(_nodeOut_a_bits_legal_T_69, _nodeOut_a_bits_legal_T_70)
node _nodeOut_a_bits_legal_T_72 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_71)
node _nodeOut_a_bits_legal_T_73 = xor(UInt<26>(0h2000000), UInt<1>(0h0))
node _nodeOut_a_bits_legal_T_74 = cvt(_nodeOut_a_bits_legal_T_73)
node _nodeOut_a_bits_legal_T_75 = and(_nodeOut_a_bits_legal_T_74, asSInt(UInt<30>(0h1a112000)))
node _nodeOut_a_bits_legal_T_76 = asSInt(_nodeOut_a_bits_legal_T_75)
node _nodeOut_a_bits_legal_T_77 = eq(_nodeOut_a_bits_legal_T_76, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_78 = xor(UInt<26>(0h2000000), UInt<21>(0h100000))
node _nodeOut_a_bits_legal_T_79 = cvt(_nodeOut_a_bits_legal_T_78)
node _nodeOut_a_bits_legal_T_80 = and(_nodeOut_a_bits_legal_T_79, asSInt(UInt<30>(0h1a103000)))
node _nodeOut_a_bits_legal_T_81 = asSInt(_nodeOut_a_bits_legal_T_80)
node _nodeOut_a_bits_legal_T_82 = eq(_nodeOut_a_bits_legal_T_81, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_83 = xor(UInt<26>(0h2000000), UInt<26>(0h2000000))
node _nodeOut_a_bits_legal_T_84 = cvt(_nodeOut_a_bits_legal_T_83)
node _nodeOut_a_bits_legal_T_85 = and(_nodeOut_a_bits_legal_T_84, asSInt(UInt<30>(0h1a110000)))
node _nodeOut_a_bits_legal_T_86 = asSInt(_nodeOut_a_bits_legal_T_85)
node _nodeOut_a_bits_legal_T_87 = eq(_nodeOut_a_bits_legal_T_86, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_88 = xor(UInt<26>(0h2000000), UInt<26>(0h2010000))
node _nodeOut_a_bits_legal_T_89 = cvt(_nodeOut_a_bits_legal_T_88)
node _nodeOut_a_bits_legal_T_90 = and(_nodeOut_a_bits_legal_T_89, asSInt(UInt<30>(0h1a113000)))
node _nodeOut_a_bits_legal_T_91 = asSInt(_nodeOut_a_bits_legal_T_90)
node _nodeOut_a_bits_legal_T_92 = eq(_nodeOut_a_bits_legal_T_91, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_93 = xor(UInt<26>(0h2000000), UInt<28>(0h8000000))
node _nodeOut_a_bits_legal_T_94 = cvt(_nodeOut_a_bits_legal_T_93)
node _nodeOut_a_bits_legal_T_95 = and(_nodeOut_a_bits_legal_T_94, asSInt(UInt<30>(0h18000000)))
node _nodeOut_a_bits_legal_T_96 = asSInt(_nodeOut_a_bits_legal_T_95)
node _nodeOut_a_bits_legal_T_97 = eq(_nodeOut_a_bits_legal_T_96, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_98 = xor(UInt<26>(0h2000000), UInt<29>(0h10000000))
node _nodeOut_a_bits_legal_T_99 = cvt(_nodeOut_a_bits_legal_T_98)
node _nodeOut_a_bits_legal_T_100 = and(_nodeOut_a_bits_legal_T_99, asSInt(UInt<30>(0h1a113000)))
node _nodeOut_a_bits_legal_T_101 = asSInt(_nodeOut_a_bits_legal_T_100)
node _nodeOut_a_bits_legal_T_102 = eq(_nodeOut_a_bits_legal_T_101, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_103 = or(_nodeOut_a_bits_legal_T_77, _nodeOut_a_bits_legal_T_82)
node _nodeOut_a_bits_legal_T_104 = or(_nodeOut_a_bits_legal_T_103, _nodeOut_a_bits_legal_T_87)
node _nodeOut_a_bits_legal_T_105 = or(_nodeOut_a_bits_legal_T_104, _nodeOut_a_bits_legal_T_92)
node _nodeOut_a_bits_legal_T_106 = or(_nodeOut_a_bits_legal_T_105, _nodeOut_a_bits_legal_T_97)
node _nodeOut_a_bits_legal_T_107 = or(_nodeOut_a_bits_legal_T_106, _nodeOut_a_bits_legal_T_102)
node _nodeOut_a_bits_legal_T_108 = and(_nodeOut_a_bits_legal_T_72, _nodeOut_a_bits_legal_T_107)
node _nodeOut_a_bits_legal_T_109 = or(UInt<1>(0h0), UInt<1>(0h0))
node _nodeOut_a_bits_legal_T_110 = xor(UInt<26>(0h2000000), UInt<17>(0h10000))
node _nodeOut_a_bits_legal_T_111 = cvt(_nodeOut_a_bits_legal_T_110)
node _nodeOut_a_bits_legal_T_112 = and(_nodeOut_a_bits_legal_T_111, asSInt(UInt<30>(0h1a110000)))
node _nodeOut_a_bits_legal_T_113 = asSInt(_nodeOut_a_bits_legal_T_112)
node _nodeOut_a_bits_legal_T_114 = eq(_nodeOut_a_bits_legal_T_113, asSInt(UInt<1>(0h0)))
node _nodeOut_a_bits_legal_T_115 = and(_nodeOut_a_bits_legal_T_109, _nodeOut_a_bits_legal_T_114)
node _nodeOut_a_bits_legal_T_116 = or(UInt<1>(0h0), _nodeOut_a_bits_legal_T_68)
node _nodeOut_a_bits_legal_T_117 = or(_nodeOut_a_bits_legal_T_116, _nodeOut_a_bits_legal_T_108)
node nodeOut_a_bits_legal_1 = or(_nodeOut_a_bits_legal_T_117, _nodeOut_a_bits_legal_T_115)
wire nodeOut_a_bits_a_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect nodeOut_a_bits_a_1.opcode, UInt<1>(0h0)
connect nodeOut_a_bits_a_1.param, UInt<1>(0h0)
connect nodeOut_a_bits_a_1.size, UInt<2>(0h2)
connect nodeOut_a_bits_a_1.source, UInt<1>(0h0)
connect nodeOut_a_bits_a_1.address, UInt<26>(0h2000000)
node _nodeOut_a_bits_a_mask_sizeOH_T_3 = or(UInt<2>(0h2), UInt<3>(0h0))
node nodeOut_a_bits_a_mask_sizeOH_shiftAmount_1 = bits(_nodeOut_a_bits_a_mask_sizeOH_T_3, 1, 0)
node _nodeOut_a_bits_a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), nodeOut_a_bits_a_mask_sizeOH_shiftAmount_1)
node _nodeOut_a_bits_a_mask_sizeOH_T_5 = bits(_nodeOut_a_bits_a_mask_sizeOH_T_4, 2, 0)
node nodeOut_a_bits_a_mask_sizeOH_1 = or(_nodeOut_a_bits_a_mask_sizeOH_T_5, UInt<1>(0h1))
node nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1 = geq(UInt<2>(0h2), UInt<2>(0h3))
node nodeOut_a_bits_a_mask_sub_sub_size_1 = bits(nodeOut_a_bits_a_mask_sizeOH_1, 2, 2)
node nodeOut_a_bits_a_mask_sub_sub_nbit_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_sub_sub_0_2_1 = and(UInt<1>(0h1), nodeOut_a_bits_a_mask_sub_sub_nbit_1)
node _nodeOut_a_bits_a_mask_sub_sub_acc_T_2 = and(nodeOut_a_bits_a_mask_sub_sub_size_1, nodeOut_a_bits_a_mask_sub_sub_0_2_1)
node nodeOut_a_bits_a_mask_sub_sub_0_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1, _nodeOut_a_bits_a_mask_sub_sub_acc_T_2)
node nodeOut_a_bits_a_mask_sub_sub_1_2_1 = and(UInt<1>(0h1), UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_sub_acc_T_3 = and(nodeOut_a_bits_a_mask_sub_sub_size_1, nodeOut_a_bits_a_mask_sub_sub_1_2_1)
node nodeOut_a_bits_a_mask_sub_sub_1_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1, _nodeOut_a_bits_a_mask_sub_sub_acc_T_3)
node nodeOut_a_bits_a_mask_sub_size_1 = bits(nodeOut_a_bits_a_mask_sizeOH_1, 1, 1)
node nodeOut_a_bits_a_mask_sub_nbit_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_sub_0_2_1 = and(nodeOut_a_bits_a_mask_sub_sub_0_2_1, nodeOut_a_bits_a_mask_sub_nbit_1)
node _nodeOut_a_bits_a_mask_sub_acc_T_4 = and(nodeOut_a_bits_a_mask_sub_size_1, nodeOut_a_bits_a_mask_sub_0_2_1)
node nodeOut_a_bits_a_mask_sub_0_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_0_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_4)
node nodeOut_a_bits_a_mask_sub_1_2_1 = and(nodeOut_a_bits_a_mask_sub_sub_0_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_acc_T_5 = and(nodeOut_a_bits_a_mask_sub_size_1, nodeOut_a_bits_a_mask_sub_1_2_1)
node nodeOut_a_bits_a_mask_sub_1_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_0_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_5)
node nodeOut_a_bits_a_mask_sub_2_2_1 = and(nodeOut_a_bits_a_mask_sub_sub_1_2_1, nodeOut_a_bits_a_mask_sub_nbit_1)
node _nodeOut_a_bits_a_mask_sub_acc_T_6 = and(nodeOut_a_bits_a_mask_sub_size_1, nodeOut_a_bits_a_mask_sub_2_2_1)
node nodeOut_a_bits_a_mask_sub_2_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_1_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_6)
node nodeOut_a_bits_a_mask_sub_3_2_1 = and(nodeOut_a_bits_a_mask_sub_sub_1_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_sub_acc_T_7 = and(nodeOut_a_bits_a_mask_sub_size_1, nodeOut_a_bits_a_mask_sub_3_2_1)
node nodeOut_a_bits_a_mask_sub_3_1_1 = or(nodeOut_a_bits_a_mask_sub_sub_1_1_1, _nodeOut_a_bits_a_mask_sub_acc_T_7)
node nodeOut_a_bits_a_mask_size_1 = bits(nodeOut_a_bits_a_mask_sizeOH_1, 0, 0)
node nodeOut_a_bits_a_mask_nbit_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node nodeOut_a_bits_a_mask_eq_8 = and(nodeOut_a_bits_a_mask_sub_0_2_1, nodeOut_a_bits_a_mask_nbit_1)
node _nodeOut_a_bits_a_mask_acc_T_8 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_8)
node nodeOut_a_bits_a_mask_acc_8 = or(nodeOut_a_bits_a_mask_sub_0_1_1, _nodeOut_a_bits_a_mask_acc_T_8)
node nodeOut_a_bits_a_mask_eq_9 = and(nodeOut_a_bits_a_mask_sub_0_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_9 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_9)
node nodeOut_a_bits_a_mask_acc_9 = or(nodeOut_a_bits_a_mask_sub_0_1_1, _nodeOut_a_bits_a_mask_acc_T_9)
node nodeOut_a_bits_a_mask_eq_10 = and(nodeOut_a_bits_a_mask_sub_1_2_1, nodeOut_a_bits_a_mask_nbit_1)
node _nodeOut_a_bits_a_mask_acc_T_10 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_10)
node nodeOut_a_bits_a_mask_acc_10 = or(nodeOut_a_bits_a_mask_sub_1_1_1, _nodeOut_a_bits_a_mask_acc_T_10)
node nodeOut_a_bits_a_mask_eq_11 = and(nodeOut_a_bits_a_mask_sub_1_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_11 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_11)
node nodeOut_a_bits_a_mask_acc_11 = or(nodeOut_a_bits_a_mask_sub_1_1_1, _nodeOut_a_bits_a_mask_acc_T_11)
node nodeOut_a_bits_a_mask_eq_12 = and(nodeOut_a_bits_a_mask_sub_2_2_1, nodeOut_a_bits_a_mask_nbit_1)
node _nodeOut_a_bits_a_mask_acc_T_12 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_12)
node nodeOut_a_bits_a_mask_acc_12 = or(nodeOut_a_bits_a_mask_sub_2_1_1, _nodeOut_a_bits_a_mask_acc_T_12)
node nodeOut_a_bits_a_mask_eq_13 = and(nodeOut_a_bits_a_mask_sub_2_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_13 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_13)
node nodeOut_a_bits_a_mask_acc_13 = or(nodeOut_a_bits_a_mask_sub_2_1_1, _nodeOut_a_bits_a_mask_acc_T_13)
node nodeOut_a_bits_a_mask_eq_14 = and(nodeOut_a_bits_a_mask_sub_3_2_1, nodeOut_a_bits_a_mask_nbit_1)
node _nodeOut_a_bits_a_mask_acc_T_14 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_14)
node nodeOut_a_bits_a_mask_acc_14 = or(nodeOut_a_bits_a_mask_sub_3_1_1, _nodeOut_a_bits_a_mask_acc_T_14)
node nodeOut_a_bits_a_mask_eq_15 = and(nodeOut_a_bits_a_mask_sub_3_2_1, UInt<1>(0h0))
node _nodeOut_a_bits_a_mask_acc_T_15 = and(nodeOut_a_bits_a_mask_size_1, nodeOut_a_bits_a_mask_eq_15)
node nodeOut_a_bits_a_mask_acc_15 = or(nodeOut_a_bits_a_mask_sub_3_1_1, _nodeOut_a_bits_a_mask_acc_T_15)
node nodeOut_a_bits_a_mask_lo_lo_1 = cat(nodeOut_a_bits_a_mask_acc_9, nodeOut_a_bits_a_mask_acc_8)
node nodeOut_a_bits_a_mask_lo_hi_1 = cat(nodeOut_a_bits_a_mask_acc_11, nodeOut_a_bits_a_mask_acc_10)
node nodeOut_a_bits_a_mask_lo_1 = cat(nodeOut_a_bits_a_mask_lo_hi_1, nodeOut_a_bits_a_mask_lo_lo_1)
node nodeOut_a_bits_a_mask_hi_lo_1 = cat(nodeOut_a_bits_a_mask_acc_13, nodeOut_a_bits_a_mask_acc_12)
node nodeOut_a_bits_a_mask_hi_hi_1 = cat(nodeOut_a_bits_a_mask_acc_15, nodeOut_a_bits_a_mask_acc_14)
node nodeOut_a_bits_a_mask_hi_1 = cat(nodeOut_a_bits_a_mask_hi_hi_1, nodeOut_a_bits_a_mask_hi_lo_1)
node _nodeOut_a_bits_a_mask_T_1 = cat(nodeOut_a_bits_a_mask_hi_1, nodeOut_a_bits_a_mask_lo_1)
connect nodeOut_a_bits_a_1.mask, _nodeOut_a_bits_a_mask_T_1
connect nodeOut_a_bits_a_1.data, UInt<1>(0h1)
connect nodeOut_a_bits_a_1.corrupt, UInt<1>(0h0)
connect nodeOut.a.bits, nodeOut_a_bits_a_1
node _T_6 = and(nodeOut.a.ready, nodeOut.a.valid)
when _T_6 :
connect state, UInt<3>(0h4)
else :
node _T_7 = eq(UInt<3>(0h4), state)
when _T_7 :
node _T_8 = and(nodeOut.d.ready, nodeOut.d.valid)
when _T_8 :
connect state, UInt<3>(0h5)
else :
node _T_9 = eq(UInt<3>(0h5), state)
when _T_9 :
node _T_10 = eq(custom_boot, UInt<1>(0h0))
when _T_10 :
connect state, UInt<3>(0h0)
connect childClock, clockSinkNodeIn.clock
connect childReset, clockSinkNodeIn.reset
connect clock, clockSinkNodeIn.clock
connect reset, clockSinkNodeIn.reset | module PeripheryBus_cbus( // @[ClockDomain.scala:14:9]
input auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bootrom_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bootrom_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [16:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bootrom_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bootrom_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_debug_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_debug_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_debug_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_debug_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_plic_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_plic_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_plic_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_plic_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_clint_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_clint_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [25:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_clint_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_clint_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_l2_ctrl_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_l2_ctrl_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [25:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_l2_ctrl_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_l2_ctrl_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_5_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_5_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_4_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_4_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_3_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_3_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25]
input auto_cbus_clock_groups_in_member_cbus_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_cbus_clock_groups_in_member_cbus_0_reset, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input custom_boot // @[CustomBootPin.scala:36:29]
);
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [28:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [28:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [28:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire buffer_1_auto_out_d_valid; // @[Buffer.scala:40:9]
wire buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_1_auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire buffer_1_auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire [6:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_1_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_1_auto_in_d_valid; // @[Buffer.scala:40:9]
wire buffer_1_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:40:9]
wire buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:40:9]
wire [6:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_1_auto_in_a_valid; // @[Buffer.scala:40:9]
wire buffer_1_auto_in_a_ready; // @[Buffer.scala:40:9]
wire buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [28:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [6:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [28:0] fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire cbus_clock_groups_auto_out_member_cbus_0_reset; // @[ClockGroup.scala:53:9]
wire cbus_clock_groups_auto_out_member_cbus_0_clock; // @[ClockGroup.scala:53:9]
wire _coupler_to_prci_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_prci_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [1:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [7:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27]
wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27]
wire _coupler_to_bootrom_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_bootrom_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_bootrom_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [7:0] _coupler_to_bootrom_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_bootrom_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_debug_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_debug_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_debug_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_debug_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [7:0] _coupler_to_debug_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_debug_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_plic_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_plic_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_plic_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_plic_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [7:0] _coupler_to_plic_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_plic_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_clint_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_clint_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_clint_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_clint_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [7:0] _coupler_to_clint_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_clint_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_l2_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27]
wire _coupler_to_l2_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [1:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27]
wire [2:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [7:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27]
wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27]
wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27]
wire [63:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27]
wire _wrapped_error_device_auto_buffer_in_a_ready; // @[LazyScope.scala:98:27]
wire _wrapped_error_device_auto_buffer_in_d_valid; // @[LazyScope.scala:98:27]
wire [2:0] _wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyScope.scala:98:27]
wire [1:0] _wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyScope.scala:98:27]
wire [3:0] _wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyScope.scala:98:27]
wire [7:0] _wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyScope.scala:98:27]
wire _wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyScope.scala:98:27]
wire _wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyScope.scala:98:27]
wire [63:0] _wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyScope.scala:98:27]
wire _wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyScope.scala:98:27]
wire _atomics_auto_in_a_ready; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_in_d_valid; // @[AtomicAutomata.scala:289:29]
wire [2:0] _atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala:289:29]
wire [1:0] _atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala:289:29]
wire [3:0] _atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala:289:29]
wire [7:0] _atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala:289:29]
wire [63:0] _atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29]
wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29]
wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29]
wire [3:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29]
wire [7:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29]
wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29]
wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29]
wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29]
wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29]
wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28]
wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28]
wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28]
wire _out_xbar_auto_anon_out_7_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_7_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_7_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_7_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_7_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [20:0] _out_xbar_auto_anon_out_7_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_7_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_7_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_7_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_7_d_ready; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_6_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_6_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_6_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_6_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_6_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [16:0] _out_xbar_auto_anon_out_6_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_6_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_6_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_6_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_6_d_ready; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_5_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_5_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_5_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_5_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_5_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [11:0] _out_xbar_auto_anon_out_5_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_5_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_5_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_5_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_5_d_ready; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_4_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_4_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_4_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_4_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_4_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [27:0] _out_xbar_auto_anon_out_4_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_4_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_4_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_4_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_4_d_ready; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_3_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_3_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_3_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_3_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_3_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [25:0] _out_xbar_auto_anon_out_3_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_3_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_3_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_3_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_3_d_ready; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [25:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30]
wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30]
wire [3:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30]
wire [13:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30]
wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30]
wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30]
wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30]
wire _in_xbar_auto_anon_out_a_valid; // @[PeripheryBus.scala:56:29]
wire [2:0] _in_xbar_auto_anon_out_a_bits_opcode; // @[PeripheryBus.scala:56:29]
wire [2:0] _in_xbar_auto_anon_out_a_bits_param; // @[PeripheryBus.scala:56:29]
wire [3:0] _in_xbar_auto_anon_out_a_bits_size; // @[PeripheryBus.scala:56:29]
wire [7:0] _in_xbar_auto_anon_out_a_bits_source; // @[PeripheryBus.scala:56:29]
wire [28:0] _in_xbar_auto_anon_out_a_bits_address; // @[PeripheryBus.scala:56:29]
wire [7:0] _in_xbar_auto_anon_out_a_bits_mask; // @[PeripheryBus.scala:56:29]
wire [63:0] _in_xbar_auto_anon_out_a_bits_data; // @[PeripheryBus.scala:56:29]
wire _in_xbar_auto_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:56:29]
wire _in_xbar_auto_anon_out_d_ready; // @[PeripheryBus.scala:56:29]
wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bootrom_fragmenter_anon_out_a_ready_0 = auto_coupler_to_bootrom_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bootrom_fragmenter_anon_out_d_valid_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [11:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_debug_fragmenter_anon_out_a_ready_0 = auto_coupler_to_debug_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_debug_fragmenter_anon_out_d_valid_0 = auto_coupler_to_debug_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [11:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_plic_fragmenter_anon_out_a_ready_0 = auto_coupler_to_plic_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_plic_fragmenter_anon_out_d_valid_0 = auto_coupler_to_plic_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [11:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_clint_fragmenter_anon_out_a_ready_0 = auto_coupler_to_clint_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_clint_fragmenter_anon_out_d_valid_0 = auto_coupler_to_clint_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [11:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_l2_ctrl_buffer_out_a_ready_0 = auto_coupler_to_l2_ctrl_buffer_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_l2_ctrl_buffer_out_d_valid_0 = auto_coupler_to_l2_ctrl_buffer_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_size_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [11:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_source_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_data_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_cbus_clock_groups_in_member_cbus_0_clock_0 = auto_cbus_clock_groups_in_member_cbus_0_clock; // @[ClockDomain.scala:14:9]
wire auto_cbus_clock_groups_in_member_cbus_0_reset_0 = auto_cbus_clock_groups_in_member_cbus_0_reset; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [6:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [28:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] nodeOut_a_bits_a_mask_hi_lo = 2'h0; // @[Misc.scala:222:10]
wire [1:0] nodeOut_a_bits_a_mask_hi_hi = 2'h0; // @[Misc.scala:222:10]
wire [1:0] nodeOut_a_bits_a_mask_hi_lo_1 = 2'h0; // @[Misc.scala:222:10]
wire [1:0] nodeOut_a_bits_a_mask_hi_hi_1 = 2'h0; // @[Misc.scala:222:10]
wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire cbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire cbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire cbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_3 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_4 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_5 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_6 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_7 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_8 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_9 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_10 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_11 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_12 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_13 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_14 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_15 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_16 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_17 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_18 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_19 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_20 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_21 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_22 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_23 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_24 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_25 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_26 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_27 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_28 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_29 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_30 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_31 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_32 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_33 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_34 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_35 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_36 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_37 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_38 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_39 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_40 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_41 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_42 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_43 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_44 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_45 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_46 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_47 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_48 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_49 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_50 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_51 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_52 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_53 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_54 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_55 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_56 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_57 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_58 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_59 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_60 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_61 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_62 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_63 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_64 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_65 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_66 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_67 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_68 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_69 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_70 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_71 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_72 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_73 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_74 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_75 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_76 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_77 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_78 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_79 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_80 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_81 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_82 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_83 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_84 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_85 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_86 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_87 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_88 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_89 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_90 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_91 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_92 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_93 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_94 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_95 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_96 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_97 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_98 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_99 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_100 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_101 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_102 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_103 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_104 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_105 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_106 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_107 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_108 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_109 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_110 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_111 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_112 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_113 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_114 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_115 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_116 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_117 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_118 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_119 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_120 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_121 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_122 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_123 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_124 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_125 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_126 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_127 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_128 = 1'h0; // @[FIFOFixer.scala:79:35]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_tlOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire _nodeOut_a_bits_legal_T_8 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_9 = 1'h0; // @[Parameters.scala:684:54]
wire _nodeOut_a_bits_legal_T_23 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_28 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_33 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_38 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_43 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_50 = 1'h0; // @[Parameters.scala:684:29]
wire _nodeOut_a_bits_legal_T_55 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_56 = 1'h0; // @[Parameters.scala:684:54]
wire _nodeOut_a_bits_legal_T_57 = 1'h0; // @[Parameters.scala:686:26]
wire nodeOut_a_bits_a_source = 1'h0; // @[Edges.scala:480:17]
wire nodeOut_a_bits_a_corrupt = 1'h0; // @[Edges.scala:480:17]
wire nodeOut_a_bits_a_mask_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21]
wire nodeOut_a_bits_a_mask_sub_sub_1_2 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_sub_1_1 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _nodeOut_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_1_2 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_2_2 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_2_1 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_sub_3_2 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_3_1 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_eq_1 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_eq_2 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_eq_3 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_eq_4 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_4 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_eq_5 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_5 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_eq_6 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_6 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_eq_7 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_7 = 1'h0; // @[Misc.scala:215:29]
wire _nodeOut_a_bits_legal_T_67 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_68 = 1'h0; // @[Parameters.scala:684:54]
wire _nodeOut_a_bits_legal_T_77 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_82 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_92 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_97 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_102 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_103 = 1'h0; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_109 = 1'h0; // @[Parameters.scala:684:29]
wire _nodeOut_a_bits_legal_T_114 = 1'h0; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_115 = 1'h0; // @[Parameters.scala:684:54]
wire _nodeOut_a_bits_legal_T_116 = 1'h0; // @[Parameters.scala:686:26]
wire nodeOut_a_bits_a_1_source = 1'h0; // @[Edges.scala:480:17]
wire nodeOut_a_bits_a_1_corrupt = 1'h0; // @[Edges.scala:480:17]
wire nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21]
wire nodeOut_a_bits_a_mask_sub_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26]
wire _nodeOut_a_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_2_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_2_1_1 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_sub_3_2_1 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_3_1_1 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_eq_9 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_eq_10 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_eq_11 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_eq_12 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_12 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_eq_13 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_13 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_eq_14 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_14 = 1'h0; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_eq_15 = 1'h0; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_15 = 1'h0; // @[Misc.scala:215:29]
wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_opcode = 3'h1; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_mask = 8'hF; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_mask = 8'hF; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_mask = 8'hF; // @[MixedNode.scala:542:17]
wire [7:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_mask = 8'hF; // @[MixedNode.scala:551:17]
wire [7:0] nodeOut_a_bits_mask = 8'hF; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_a_mask = 8'hF; // @[Edges.scala:480:17]
wire [7:0] _nodeOut_a_bits_a_mask_T = 8'hF; // @[Misc.scala:222:10]
wire [7:0] nodeOut_a_bits_a_1_mask = 8'hF; // @[Edges.scala:480:17]
wire [7:0] _nodeOut_a_bits_a_mask_T_1 = 8'hF; // @[Misc.scala:222:10]
wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_size = 4'h2; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_size = 4'h2; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_size = 4'h2; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_size = 4'h2; // @[MixedNode.scala:551:17]
wire [3:0] nodeOut_a_bits_size = 4'h2; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_a_size = 4'h2; // @[Edges.scala:480:17]
wire [3:0] nodeOut_a_bits_a_1_size = 4'h2; // @[Edges.scala:480:17]
wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_opcode = 3'h0; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_param = 3'h0; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_opcode = 3'h0; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_param = 3'h0; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_a_bits_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_a_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] nodeOut_a_bits_a_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] nodeOut_a_bits_a_1_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] nodeOut_a_bits_a_1_param = 3'h0; // @[Edges.scala:480:17]
wire [3:0] nodeOut_a_bits_a_mask_hi = 4'h0; // @[Misc.scala:222:10]
wire [3:0] nodeOut_a_bits_a_mask_hi_1 = 4'h0; // @[Misc.scala:222:10]
wire [3:0] nodeOut_a_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] nodeOut_a_bits_a_mask_lo_1 = 4'hF; // @[Misc.scala:222:10]
wire [1:0] nodeOut_a_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] nodeOut_a_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] nodeOut_a_bits_a_mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10]
wire [1:0] nodeOut_a_bits_a_mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10]
wire fixer__a_notFIFO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire fixer__flight_T = 1'h1; // @[FIFOFixer.scala:80:65]
wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50]
wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47]
wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50]
wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47]
wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_ready = 1'h1; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_ready = 1'h1; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_tlOut_d_ready = 1'h1; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_d_ready = 1'h1; // @[MixedNode.scala:551:17]
wire nodeOut_d_ready = 1'h1; // @[MixedNode.scala:542:17]
wire _nodeOut_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _nodeOut_a_bits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _nodeOut_a_bits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _nodeOut_a_bits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _nodeOut_a_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _nodeOut_a_bits_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _nodeOut_a_bits_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _nodeOut_a_bits_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _nodeOut_a_bits_legal_T_18 = 1'h1; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_44 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_45 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_46 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_47 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_48 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_49 = 1'h1; // @[Parameters.scala:684:54]
wire _nodeOut_a_bits_legal_T_58 = 1'h1; // @[Parameters.scala:686:26]
wire nodeOut_a_bits_legal = 1'h1; // @[Parameters.scala:686:26]
wire nodeOut_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire nodeOut_a_bits_a_mask_sub_sub_nbit = 1'h1; // @[Misc.scala:211:20]
wire nodeOut_a_bits_a_mask_sub_sub_0_2 = 1'h1; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_sub_acc_T = 1'h1; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_sub_nbit = 1'h1; // @[Misc.scala:211:20]
wire nodeOut_a_bits_a_mask_sub_0_2 = 1'h1; // @[Misc.scala:214:27]
wire nodeOut_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire nodeOut_a_bits_a_mask_nbit = 1'h1; // @[Misc.scala:211:20]
wire nodeOut_a_bits_a_mask_eq = 1'h1; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T = 1'h1; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _nodeOut_a_bits_legal_T_59 = 1'h1; // @[Parameters.scala:92:28]
wire _nodeOut_a_bits_legal_T_60 = 1'h1; // @[Parameters.scala:92:38]
wire _nodeOut_a_bits_legal_T_61 = 1'h1; // @[Parameters.scala:92:33]
wire _nodeOut_a_bits_legal_T_62 = 1'h1; // @[Parameters.scala:684:29]
wire _nodeOut_a_bits_legal_T_69 = 1'h1; // @[Parameters.scala:92:28]
wire _nodeOut_a_bits_legal_T_70 = 1'h1; // @[Parameters.scala:92:38]
wire _nodeOut_a_bits_legal_T_71 = 1'h1; // @[Parameters.scala:92:33]
wire _nodeOut_a_bits_legal_T_72 = 1'h1; // @[Parameters.scala:684:29]
wire _nodeOut_a_bits_legal_T_87 = 1'h1; // @[Parameters.scala:137:59]
wire _nodeOut_a_bits_legal_T_104 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_105 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_106 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_107 = 1'h1; // @[Parameters.scala:685:42]
wire _nodeOut_a_bits_legal_T_108 = 1'h1; // @[Parameters.scala:684:54]
wire _nodeOut_a_bits_legal_T_117 = 1'h1; // @[Parameters.scala:686:26]
wire nodeOut_a_bits_legal_1 = 1'h1; // @[Parameters.scala:686:26]
wire nodeOut_a_bits_a_mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26]
wire nodeOut_a_bits_a_mask_sub_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20]
wire nodeOut_a_bits_a_mask_sub_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_2 = 1'h1; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20]
wire nodeOut_a_bits_a_mask_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27]
wire nodeOut_a_bits_a_mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_size_1 = 1'h1; // @[Misc.scala:209:26]
wire nodeOut_a_bits_a_mask_nbit_1 = 1'h1; // @[Misc.scala:211:20]
wire nodeOut_a_bits_a_mask_eq_8 = 1'h1; // @[Misc.scala:214:27]
wire _nodeOut_a_bits_a_mask_acc_T_8 = 1'h1; // @[Misc.scala:215:38]
wire nodeOut_a_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29]
wire nodeOut_a_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29]
wire [2:0] nodeOut_a_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81]
wire [2:0] nodeOut_a_bits_a_mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81]
wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27]
wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27]
wire [3:0] _nodeOut_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _nodeOut_a_bits_a_mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12]
wire [1:0] nodeOut_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [1:0] nodeOut_a_bits_a_mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49]
wire [63:0] nodeOut_a_bits_a_1_data = 64'h1; // @[Edges.scala:480:17]
wire [28:0] nodeOut_a_bits_a_1_address = 29'h2000000; // @[Edges.scala:480:17]
wire [29:0] _nodeOut_a_bits_legal_T_112 = 30'h2010000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_113 = 30'h2010000; // @[Parameters.scala:137:46]
wire [26:0] _nodeOut_a_bits_legal_T_111 = 27'h2010000; // @[Parameters.scala:137:41]
wire [29:0] _nodeOut_a_bits_legal_T_99 = 30'h12000000; // @[Parameters.scala:137:41]
wire [29:0] _nodeOut_a_bits_legal_T_100 = 30'h12000000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_101 = 30'h12000000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_36 = 30'h8000000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_37 = 30'h8000000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_95 = 30'h8000000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_96 = 30'h8000000; // @[Parameters.scala:137:46]
wire [28:0] _nodeOut_a_bits_legal_T_94 = 29'hA000000; // @[Parameters.scala:137:41]
wire [29:0] _nodeOut_a_bits_legal_T_53 = 30'h10000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_54 = 30'h10000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_90 = 30'h10000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_91 = 30'h10000; // @[Parameters.scala:137:46]
wire [26:0] _nodeOut_a_bits_legal_T_89 = 27'h10000; // @[Parameters.scala:137:41]
wire [29:0] fixer__a_notFIFO_T_2 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] fixer__a_notFIFO_T_3 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_16 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_17 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_85 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_86 = 30'h0; // @[Parameters.scala:137:46]
wire [26:0] _nodeOut_a_bits_legal_T_84 = 27'h0; // @[Parameters.scala:137:41]
wire [29:0] _nodeOut_a_bits_legal_T_80 = 30'h2100000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_81 = 30'h2100000; // @[Parameters.scala:137:46]
wire [26:0] _nodeOut_a_bits_legal_T_79 = 27'h2100000; // @[Parameters.scala:137:41]
wire [29:0] _nodeOut_a_bits_legal_T_26 = 30'h2000000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_27 = 30'h2000000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_75 = 30'h2000000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_76 = 30'h2000000; // @[Parameters.scala:137:46]
wire [26:0] _nodeOut_a_bits_legal_T_74 = 27'h2000000; // @[Parameters.scala:137:41]
wire [29:0] _nodeOut_a_bits_legal_T_65 = 30'h2003000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_66 = 30'h2003000; // @[Parameters.scala:137:46]
wire [26:0] _nodeOut_a_bits_legal_T_64 = 27'h2003000; // @[Parameters.scala:137:41]
wire [63:0] nodeOut_a_bits_a_data = 64'h80000000; // @[Edges.scala:480:17]
wire [28:0] nodeOut_a_bits_a_address = 29'h1000; // @[Edges.scala:480:17]
wire [17:0] _nodeOut_a_bits_legal_T_52 = 18'h11000; // @[Parameters.scala:137:41]
wire [29:0] _nodeOut_a_bits_legal_T_40 = 30'h10001000; // @[Parameters.scala:137:41]
wire [29:0] _nodeOut_a_bits_legal_T_41 = 30'h10001000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_42 = 30'h10001000; // @[Parameters.scala:137:46]
wire [28:0] _nodeOut_a_bits_legal_T_35 = 29'h8001000; // @[Parameters.scala:137:41]
wire [29:0] _nodeOut_a_bits_legal_T_31 = 30'h2011000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_32 = 30'h2011000; // @[Parameters.scala:137:46]
wire [26:0] _nodeOut_a_bits_legal_T_30 = 27'h2011000; // @[Parameters.scala:137:41]
wire [26:0] _nodeOut_a_bits_legal_T_25 = 27'h2001000; // @[Parameters.scala:137:41]
wire [29:0] _nodeOut_a_bits_legal_T_21 = 30'h101000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_22 = 30'h101000; // @[Parameters.scala:137:46]
wire [21:0] _nodeOut_a_bits_legal_T_20 = 22'h101000; // @[Parameters.scala:137:41]
wire [13:0] _nodeOut_a_bits_legal_T_15 = 14'h1000; // @[Parameters.scala:137:41]
wire [29:0] _nodeOut_a_bits_legal_T_6 = 30'h2000; // @[Parameters.scala:137:46]
wire [29:0] _nodeOut_a_bits_legal_T_7 = 30'h2000; // @[Parameters.scala:137:46]
wire [14:0] _nodeOut_a_bits_legal_T_5 = 15'h2000; // @[Parameters.scala:137:41]
wire [128:0] fixer__allIDs_FIFOed_T = 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[FIFOFixer.scala:127:48]
wire [28:0] _nodeOut_a_bits_legal_T_98 = 29'h12000000; // @[Parameters.scala:137:31]
wire [27:0] _nodeOut_a_bits_legal_T_93 = 28'hA000000; // @[Parameters.scala:137:31]
wire [25:0] _nodeOut_a_bits_legal_T_88 = 26'h10000; // @[Parameters.scala:137:31]
wire [25:0] _nodeOut_a_bits_legal_T_83 = 26'h0; // @[Parameters.scala:137:31]
wire [25:0] _nodeOut_a_bits_legal_T_78 = 26'h2100000; // @[Parameters.scala:137:31]
wire [25:0] _nodeOut_a_bits_legal_T_63 = 26'h2003000; // @[Parameters.scala:137:31]
wire [16:0] _nodeOut_a_bits_legal_T_51 = 17'h11000; // @[Parameters.scala:137:31]
wire [28:0] _nodeOut_a_bits_legal_T_39 = 29'h10001000; // @[Parameters.scala:137:31]
wire [27:0] _nodeOut_a_bits_legal_T_34 = 28'h8001000; // @[Parameters.scala:137:31]
wire [25:0] _nodeOut_a_bits_legal_T_29 = 26'h2011000; // @[Parameters.scala:137:31]
wire [25:0] _nodeOut_a_bits_legal_T_24 = 26'h2001000; // @[Parameters.scala:137:31]
wire [20:0] _nodeOut_a_bits_legal_T_19 = 21'h101000; // @[Parameters.scala:137:31]
wire [13:0] _nodeOut_a_bits_legal_T_4 = 14'h2000; // @[Parameters.scala:137:31]
wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T = 3'h2; // @[Misc.scala:202:34]
wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_3 = 3'h2; // @[Misc.scala:202:34]
wire [25:0] _nodeOut_a_bits_legal_T_110 = 26'h2010000; // @[Parameters.scala:137:31]
wire [25:0] _nodeOut_a_bits_legal_T_73 = 26'h2000000; // @[Parameters.scala:137:31]
wire [12:0] _nodeOut_a_bits_legal_T_14 = 13'h1000; // @[Parameters.scala:137:31]
wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [28:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire cbus_clock_groups_auto_in_member_cbus_0_clock = auto_cbus_clock_groups_in_member_cbus_0_clock_0; // @[ClockGroup.scala:53:9]
wire cbus_clock_groups_auto_in_member_cbus_0_reset = auto_cbus_clock_groups_in_member_cbus_0_reset_0; // @[ClockGroup.scala:53:9]
wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [6:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [28:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9]
wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [20:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [11:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [16:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [11:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [11:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_debug_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_debug_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [11:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [27:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_plic_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_plic_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [11:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [25:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_clint_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_clint_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [28:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [11:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [25:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_l2_ctrl_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_l2_ctrl_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [6:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire cbus_clock_groups_nodeIn_member_cbus_0_clock = cbus_clock_groups_auto_in_member_cbus_0_clock; // @[ClockGroup.scala:53:9]
wire cbus_clock_groups_nodeOut_member_cbus_0_clock; // @[MixedNode.scala:542:17]
wire cbus_clock_groups_nodeIn_member_cbus_0_reset = cbus_clock_groups_auto_in_member_cbus_0_reset; // @[ClockGroup.scala:53:9]
wire cbus_clock_groups_nodeOut_member_cbus_0_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_in_member_cbus_0_clock = cbus_clock_groups_auto_out_member_cbus_0_clock; // @[ClockGroup.scala:24:9, :53:9]
wire clockGroup_auto_in_member_cbus_0_reset = cbus_clock_groups_auto_out_member_cbus_0_reset; // @[ClockGroup.scala:24:9, :53:9]
assign cbus_clock_groups_auto_out_member_cbus_0_clock = cbus_clock_groups_nodeOut_member_cbus_0_clock; // @[ClockGroup.scala:53:9]
assign cbus_clock_groups_auto_out_member_cbus_0_reset = cbus_clock_groups_nodeOut_member_cbus_0_reset; // @[ClockGroup.scala:53:9]
assign cbus_clock_groups_nodeOut_member_cbus_0_clock = cbus_clock_groups_nodeIn_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign cbus_clock_groups_nodeOut_member_cbus_0_reset = cbus_clock_groups_nodeIn_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire clockGroup_nodeIn_member_cbus_0_clock = clockGroup_auto_in_member_cbus_0_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockGroup_nodeIn_member_cbus_0_reset = clockGroup_auto_in_member_cbus_0_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire fixer_anonIn_a_valid = fixer_auto_anon_in_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [28:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_ready = fixer_auto_anon_in_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] fixer_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire fixer_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire fixer_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire fixer_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire fixer_anonOut_a_ready = fixer_auto_anon_out_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_valid = fixer_auto_anon_out_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonOut_d_bits_param = fixer_auto_anon_out_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_d_bits_source; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_sink = fixer_auto_anon_out_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_denied = fixer_auto_anon_out_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_corrupt = fixer_auto_anon_out_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_a_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_d_bits_source; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [28:0] fixer_auto_anon_out_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33]
assign fixer_auto_anon_out_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_param = fixer_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_sink = fixer_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_denied = fixer_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_corrupt = fixer_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9]
assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33]
assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [28:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [28:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_param = fixer_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_sink = fixer_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_denied = fixer_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_d_bits_corrupt = fixer_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [29:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}]
wire [29:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}]
wire [29:0] fixer__a_id_T_2 = fixer__a_id_T_1 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] fixer__a_id_T_3 = fixer__a_id_T_2; // @[Parameters.scala:137:46]
wire fixer__a_id_T_4 = fixer__a_id_T_3 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] fixer__a_id_T_5 = {fixer_anonIn_a_bits_address[28:13], fixer_anonIn_a_bits_address[12:0] ^ 13'h1000}; // @[Parameters.scala:137:31]
wire [29:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}]
wire [29:0] fixer__a_id_T_7 = fixer__a_id_T_6 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] fixer__a_id_T_8 = fixer__a_id_T_7; // @[Parameters.scala:137:46]
wire fixer__a_id_T_9 = fixer__a_id_T_8 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] fixer__a_id_T_10 = fixer_anonIn_a_bits_address ^ 29'h10000000; // @[Parameters.scala:137:31]
wire [29:0] fixer__a_id_T_11 = {1'h0, fixer__a_id_T_10}; // @[Parameters.scala:137:{31,41}]
wire [29:0] fixer__a_id_T_12 = fixer__a_id_T_11 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] fixer__a_id_T_13 = fixer__a_id_T_12; // @[Parameters.scala:137:46]
wire fixer__a_id_T_14 = fixer__a_id_T_13 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_id_T_15 = fixer__a_id_T_9 | fixer__a_id_T_14; // @[Parameters.scala:629:89]
wire [28:0] fixer__a_id_T_16 = {fixer_anonIn_a_bits_address[28:14], fixer_anonIn_a_bits_address[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31]
wire [29:0] fixer__a_id_T_17 = {1'h0, fixer__a_id_T_16}; // @[Parameters.scala:137:{31,41}]
wire [29:0] fixer__a_id_T_18 = fixer__a_id_T_17 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] fixer__a_id_T_19 = fixer__a_id_T_18; // @[Parameters.scala:137:46]
wire fixer__a_id_T_20 = fixer__a_id_T_19 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_id_T_48 = fixer__a_id_T_20; // @[Mux.scala:30:73]
wire [28:0] fixer__a_id_T_21 = {fixer_anonIn_a_bits_address[28:17], fixer_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [29:0] fixer__a_id_T_22 = {1'h0, fixer__a_id_T_21}; // @[Parameters.scala:137:{31,41}]
wire [29:0] fixer__a_id_T_23 = fixer__a_id_T_22 & 30'h1A110000; // @[Parameters.scala:137:{41,46}]
wire [29:0] fixer__a_id_T_24 = fixer__a_id_T_23; // @[Parameters.scala:137:46]
wire fixer__a_id_T_25 = fixer__a_id_T_24 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] fixer__a_id_T_26 = {fixer_anonIn_a_bits_address[28:21], fixer_anonIn_a_bits_address[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [29:0] fixer__a_id_T_27 = {1'h0, fixer__a_id_T_26}; // @[Parameters.scala:137:{31,41}]
wire [29:0] fixer__a_id_T_28 = fixer__a_id_T_27 & 30'h1A103000; // @[Parameters.scala:137:{41,46}]
wire [29:0] fixer__a_id_T_29 = fixer__a_id_T_28; // @[Parameters.scala:137:46]
wire fixer__a_id_T_30 = fixer__a_id_T_29 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] fixer__a_id_T_31 = {fixer_anonIn_a_bits_address[28:26], fixer_anonIn_a_bits_address[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [29:0] fixer__a_id_T_32 = {1'h0, fixer__a_id_T_31}; // @[Parameters.scala:137:{31,41}]
wire [29:0] fixer__a_id_T_33 = fixer__a_id_T_32 & 30'h1A110000; // @[Parameters.scala:137:{41,46}]
wire [29:0] fixer__a_id_T_34 = fixer__a_id_T_33; // @[Parameters.scala:137:46]
wire fixer__a_id_T_35 = fixer__a_id_T_34 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] fixer__a_id_T_36 = {fixer_anonIn_a_bits_address[28:26], fixer_anonIn_a_bits_address[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31]
wire [29:0] fixer__a_id_T_37 = {1'h0, fixer__a_id_T_36}; // @[Parameters.scala:137:{31,41}]
wire [29:0] fixer__a_id_T_38 = fixer__a_id_T_37 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] fixer__a_id_T_39 = fixer__a_id_T_38; // @[Parameters.scala:137:46]
wire fixer__a_id_T_40 = fixer__a_id_T_39 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] fixer__a_id_T_41 = {fixer_anonIn_a_bits_address[28], fixer_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [29:0] fixer__a_id_T_42 = {1'h0, fixer__a_id_T_41}; // @[Parameters.scala:137:{31,41}]
wire [29:0] fixer__a_id_T_43 = fixer__a_id_T_42 & 30'h18000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] fixer__a_id_T_44 = fixer__a_id_T_43; // @[Parameters.scala:137:46]
wire fixer__a_id_T_45 = fixer__a_id_T_44 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [1:0] fixer__a_id_T_46 = {fixer__a_id_T_4, 1'h0}; // @[Mux.scala:30:73]
wire [2:0] fixer__a_id_T_47 = fixer__a_id_T_15 ? 3'h5 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] fixer__a_id_T_49 = {fixer__a_id_T_25, 2'h0}; // @[Mux.scala:30:73]
wire [2:0] fixer__a_id_T_50 = fixer__a_id_T_30 ? 3'h6 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] fixer__a_id_T_51 = {3{fixer__a_id_T_35}}; // @[Mux.scala:30:73]
wire [1:0] fixer__a_id_T_52 = {2{fixer__a_id_T_40}}; // @[Mux.scala:30:73]
wire [3:0] fixer__a_id_T_53 = {fixer__a_id_T_45, 3'h0}; // @[Mux.scala:30:73]
wire [2:0] fixer__a_id_T_54 = {1'h0, fixer__a_id_T_46} | fixer__a_id_T_47; // @[Mux.scala:30:73]
wire [2:0] fixer__a_id_T_55 = {fixer__a_id_T_54[2:1], fixer__a_id_T_54[0] | fixer__a_id_T_48}; // @[Mux.scala:30:73]
wire [2:0] fixer__a_id_T_56 = fixer__a_id_T_55 | fixer__a_id_T_49; // @[Mux.scala:30:73]
wire [2:0] fixer__a_id_T_57 = fixer__a_id_T_56 | fixer__a_id_T_50; // @[Mux.scala:30:73]
wire [2:0] fixer__a_id_T_58 = fixer__a_id_T_57 | fixer__a_id_T_51; // @[Mux.scala:30:73]
wire [2:0] fixer__a_id_T_59 = {fixer__a_id_T_58[2], fixer__a_id_T_58[1:0] | fixer__a_id_T_52}; // @[Mux.scala:30:73]
wire [3:0] fixer__a_id_T_60 = {1'h0, fixer__a_id_T_59} | fixer__a_id_T_53; // @[Mux.scala:30:73]
wire [3:0] fixer_a_id = fixer__a_id_T_60; // @[Mux.scala:30:73]
wire fixer_a_noDomain = fixer_a_id == 4'h0; // @[Mux.scala:30:73]
wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__a_first_beats1_decode_T = 27'hFFF << fixer_anonIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] fixer_a_first_counter; // @[Edges.scala:229:27]
wire [9:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire fixer_a_first = fixer_a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__a_first_last_T = fixer_a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__d_first_beats1_decode_T = 27'hFFF << fixer_anonOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] fixer_d_first_counter; // @[Edges.scala:229:27]
wire [9:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire fixer_d_first_first = fixer_d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__d_first_last_T = fixer_d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}]
reg fixer_flight_0; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1; // @[FIFOFixer.scala:79:27]
reg fixer_flight_2; // @[FIFOFixer.scala:79:27]
reg fixer_flight_3; // @[FIFOFixer.scala:79:27]
reg fixer_flight_4; // @[FIFOFixer.scala:79:27]
reg fixer_flight_5; // @[FIFOFixer.scala:79:27]
reg fixer_flight_6; // @[FIFOFixer.scala:79:27]
reg fixer_flight_7; // @[FIFOFixer.scala:79:27]
reg fixer_flight_8; // @[FIFOFixer.scala:79:27]
reg fixer_flight_9; // @[FIFOFixer.scala:79:27]
reg fixer_flight_10; // @[FIFOFixer.scala:79:27]
reg fixer_flight_11; // @[FIFOFixer.scala:79:27]
reg fixer_flight_12; // @[FIFOFixer.scala:79:27]
reg fixer_flight_13; // @[FIFOFixer.scala:79:27]
reg fixer_flight_14; // @[FIFOFixer.scala:79:27]
reg fixer_flight_15; // @[FIFOFixer.scala:79:27]
reg fixer_flight_16; // @[FIFOFixer.scala:79:27]
reg fixer_flight_17; // @[FIFOFixer.scala:79:27]
reg fixer_flight_18; // @[FIFOFixer.scala:79:27]
reg fixer_flight_19; // @[FIFOFixer.scala:79:27]
reg fixer_flight_20; // @[FIFOFixer.scala:79:27]
reg fixer_flight_21; // @[FIFOFixer.scala:79:27]
reg fixer_flight_22; // @[FIFOFixer.scala:79:27]
reg fixer_flight_23; // @[FIFOFixer.scala:79:27]
reg fixer_flight_24; // @[FIFOFixer.scala:79:27]
reg fixer_flight_25; // @[FIFOFixer.scala:79:27]
reg fixer_flight_26; // @[FIFOFixer.scala:79:27]
reg fixer_flight_27; // @[FIFOFixer.scala:79:27]
reg fixer_flight_28; // @[FIFOFixer.scala:79:27]
reg fixer_flight_29; // @[FIFOFixer.scala:79:27]
reg fixer_flight_30; // @[FIFOFixer.scala:79:27]
reg fixer_flight_31; // @[FIFOFixer.scala:79:27]
reg fixer_flight_32; // @[FIFOFixer.scala:79:27]
reg fixer_flight_33; // @[FIFOFixer.scala:79:27]
reg fixer_flight_34; // @[FIFOFixer.scala:79:27]
reg fixer_flight_35; // @[FIFOFixer.scala:79:27]
reg fixer_flight_36; // @[FIFOFixer.scala:79:27]
reg fixer_flight_37; // @[FIFOFixer.scala:79:27]
reg fixer_flight_38; // @[FIFOFixer.scala:79:27]
reg fixer_flight_39; // @[FIFOFixer.scala:79:27]
reg fixer_flight_40; // @[FIFOFixer.scala:79:27]
reg fixer_flight_41; // @[FIFOFixer.scala:79:27]
reg fixer_flight_42; // @[FIFOFixer.scala:79:27]
reg fixer_flight_43; // @[FIFOFixer.scala:79:27]
reg fixer_flight_44; // @[FIFOFixer.scala:79:27]
reg fixer_flight_45; // @[FIFOFixer.scala:79:27]
reg fixer_flight_46; // @[FIFOFixer.scala:79:27]
reg fixer_flight_47; // @[FIFOFixer.scala:79:27]
reg fixer_flight_48; // @[FIFOFixer.scala:79:27]
reg fixer_flight_49; // @[FIFOFixer.scala:79:27]
reg fixer_flight_50; // @[FIFOFixer.scala:79:27]
reg fixer_flight_51; // @[FIFOFixer.scala:79:27]
reg fixer_flight_52; // @[FIFOFixer.scala:79:27]
reg fixer_flight_53; // @[FIFOFixer.scala:79:27]
reg fixer_flight_54; // @[FIFOFixer.scala:79:27]
reg fixer_flight_55; // @[FIFOFixer.scala:79:27]
reg fixer_flight_56; // @[FIFOFixer.scala:79:27]
reg fixer_flight_57; // @[FIFOFixer.scala:79:27]
reg fixer_flight_58; // @[FIFOFixer.scala:79:27]
reg fixer_flight_59; // @[FIFOFixer.scala:79:27]
reg fixer_flight_60; // @[FIFOFixer.scala:79:27]
reg fixer_flight_61; // @[FIFOFixer.scala:79:27]
reg fixer_flight_62; // @[FIFOFixer.scala:79:27]
reg fixer_flight_63; // @[FIFOFixer.scala:79:27]
reg fixer_flight_64; // @[FIFOFixer.scala:79:27]
reg fixer_flight_65; // @[FIFOFixer.scala:79:27]
reg fixer_flight_66; // @[FIFOFixer.scala:79:27]
reg fixer_flight_67; // @[FIFOFixer.scala:79:27]
reg fixer_flight_68; // @[FIFOFixer.scala:79:27]
reg fixer_flight_69; // @[FIFOFixer.scala:79:27]
reg fixer_flight_70; // @[FIFOFixer.scala:79:27]
reg fixer_flight_71; // @[FIFOFixer.scala:79:27]
reg fixer_flight_72; // @[FIFOFixer.scala:79:27]
reg fixer_flight_73; // @[FIFOFixer.scala:79:27]
reg fixer_flight_74; // @[FIFOFixer.scala:79:27]
reg fixer_flight_75; // @[FIFOFixer.scala:79:27]
reg fixer_flight_76; // @[FIFOFixer.scala:79:27]
reg fixer_flight_77; // @[FIFOFixer.scala:79:27]
reg fixer_flight_78; // @[FIFOFixer.scala:79:27]
reg fixer_flight_79; // @[FIFOFixer.scala:79:27]
reg fixer_flight_80; // @[FIFOFixer.scala:79:27]
reg fixer_flight_81; // @[FIFOFixer.scala:79:27]
reg fixer_flight_82; // @[FIFOFixer.scala:79:27]
reg fixer_flight_83; // @[FIFOFixer.scala:79:27]
reg fixer_flight_84; // @[FIFOFixer.scala:79:27]
reg fixer_flight_85; // @[FIFOFixer.scala:79:27]
reg fixer_flight_86; // @[FIFOFixer.scala:79:27]
reg fixer_flight_87; // @[FIFOFixer.scala:79:27]
reg fixer_flight_88; // @[FIFOFixer.scala:79:27]
reg fixer_flight_89; // @[FIFOFixer.scala:79:27]
reg fixer_flight_90; // @[FIFOFixer.scala:79:27]
reg fixer_flight_91; // @[FIFOFixer.scala:79:27]
reg fixer_flight_92; // @[FIFOFixer.scala:79:27]
reg fixer_flight_93; // @[FIFOFixer.scala:79:27]
reg fixer_flight_94; // @[FIFOFixer.scala:79:27]
reg fixer_flight_95; // @[FIFOFixer.scala:79:27]
reg fixer_flight_96; // @[FIFOFixer.scala:79:27]
reg fixer_flight_97; // @[FIFOFixer.scala:79:27]
reg fixer_flight_98; // @[FIFOFixer.scala:79:27]
reg fixer_flight_99; // @[FIFOFixer.scala:79:27]
reg fixer_flight_100; // @[FIFOFixer.scala:79:27]
reg fixer_flight_101; // @[FIFOFixer.scala:79:27]
reg fixer_flight_102; // @[FIFOFixer.scala:79:27]
reg fixer_flight_103; // @[FIFOFixer.scala:79:27]
reg fixer_flight_104; // @[FIFOFixer.scala:79:27]
reg fixer_flight_105; // @[FIFOFixer.scala:79:27]
reg fixer_flight_106; // @[FIFOFixer.scala:79:27]
reg fixer_flight_107; // @[FIFOFixer.scala:79:27]
reg fixer_flight_108; // @[FIFOFixer.scala:79:27]
reg fixer_flight_109; // @[FIFOFixer.scala:79:27]
reg fixer_flight_110; // @[FIFOFixer.scala:79:27]
reg fixer_flight_111; // @[FIFOFixer.scala:79:27]
reg fixer_flight_112; // @[FIFOFixer.scala:79:27]
reg fixer_flight_113; // @[FIFOFixer.scala:79:27]
reg fixer_flight_114; // @[FIFOFixer.scala:79:27]
reg fixer_flight_115; // @[FIFOFixer.scala:79:27]
reg fixer_flight_116; // @[FIFOFixer.scala:79:27]
reg fixer_flight_117; // @[FIFOFixer.scala:79:27]
reg fixer_flight_118; // @[FIFOFixer.scala:79:27]
reg fixer_flight_119; // @[FIFOFixer.scala:79:27]
reg fixer_flight_120; // @[FIFOFixer.scala:79:27]
reg fixer_flight_121; // @[FIFOFixer.scala:79:27]
reg fixer_flight_122; // @[FIFOFixer.scala:79:27]
reg fixer_flight_123; // @[FIFOFixer.scala:79:27]
reg fixer_flight_124; // @[FIFOFixer.scala:79:27]
reg fixer_flight_125; // @[FIFOFixer.scala:79:27]
reg fixer_flight_126; // @[FIFOFixer.scala:79:27]
reg fixer_flight_127; // @[FIFOFixer.scala:79:27]
reg fixer_flight_128; // @[FIFOFixer.scala:79:27]
wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35]
assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
reg [128:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35]
wire [128:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36]
wire [128:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38]
wire [255:0] fixer__SourceIdSet_T = 256'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T ? fixer__SourceIdSet_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [255:0] fixer__SourceIdClear_T = 256'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [128:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41]
wire buffer_1_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire bus_xingOut_a_ready = buffer_1_auto_in_a_ready; // @[Buffer.scala:40:9]
wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
wire buffer_1_nodeIn_a_valid = buffer_1_auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_1_nodeIn_a_bits_opcode = buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_1_nodeIn_a_bits_param = buffer_1_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] buffer_1_nodeIn_a_bits_size = buffer_1_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [6:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [6:0] buffer_1_nodeIn_a_bits_source = buffer_1_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [28:0] buffer_1_nodeIn_a_bits_address = buffer_1_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [7:0] buffer_1_nodeIn_a_bits_mask = buffer_1_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [63:0] buffer_1_nodeIn_a_bits_data = buffer_1_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire buffer_1_nodeIn_a_bits_corrupt = buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
wire buffer_1_nodeIn_d_ready = buffer_1_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_1_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_1_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire bus_xingOut_d_valid = buffer_1_auto_in_d_valid; // @[Buffer.scala:40:9]
wire [1:0] buffer_1_nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] bus_xingOut_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] buffer_1_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] bus_xingOut_d_bits_param = buffer_1_auto_in_d_bits_param; // @[Buffer.scala:40:9]
wire [6:0] buffer_1_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] bus_xingOut_d_bits_size = buffer_1_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire buffer_1_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [6:0] bus_xingOut_d_bits_source = buffer_1_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire buffer_1_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire bus_xingOut_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:40:9]
wire [63:0] buffer_1_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire bus_xingOut_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:40:9]
wire buffer_1_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] bus_xingOut_d_bits_data = buffer_1_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire bus_xingOut_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_1_nodeOut_a_ready = buffer_1_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_1_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] buffer_1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] buffer_1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] buffer_1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] buffer_1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] buffer_1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] buffer_1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire buffer_1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire buffer_1_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire buffer_1_nodeOut_d_valid = buffer_1_auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_1_nodeOut_d_bits_opcode = buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_1_nodeOut_d_bits_param = buffer_1_auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_1_nodeOut_d_bits_size = buffer_1_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [6:0] buffer_1_nodeOut_d_bits_source = buffer_1_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire buffer_1_nodeOut_d_bits_sink = buffer_1_auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire buffer_1_nodeOut_d_bits_denied = buffer_1_auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] buffer_1_nodeOut_d_bits_data = buffer_1_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_1_nodeOut_d_bits_corrupt = buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [6:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [28:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_1_auto_out_a_valid; // @[Buffer.scala:40:9]
wire buffer_1_auto_out_d_ready; // @[Buffer.scala:40:9]
assign buffer_1_nodeIn_a_ready = buffer_1_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_auto_out_a_valid = buffer_1_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_a_bits_opcode = buffer_1_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_a_bits_param = buffer_1_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_a_bits_size = buffer_1_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_a_bits_source = buffer_1_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_a_bits_address = buffer_1_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_a_bits_mask = buffer_1_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_a_bits_data = buffer_1_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_a_bits_corrupt = buffer_1_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_1_auto_out_d_ready = buffer_1_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign buffer_1_nodeIn_d_valid = buffer_1_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeIn_d_bits_opcode = buffer_1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeIn_d_bits_param = buffer_1_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeIn_d_bits_size = buffer_1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeIn_d_bits_source = buffer_1_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeIn_d_bits_sink = buffer_1_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeIn_d_bits_denied = buffer_1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeIn_d_bits_data = buffer_1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeIn_d_bits_corrupt = buffer_1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_auto_in_a_ready = buffer_1_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign buffer_1_nodeOut_a_valid = buffer_1_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_a_bits_opcode = buffer_1_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_a_bits_param = buffer_1_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_a_bits_size = buffer_1_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_a_bits_source = buffer_1_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_a_bits_address = buffer_1_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_a_bits_mask = buffer_1_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_a_bits_data = buffer_1_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_a_bits_corrupt = buffer_1_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_nodeOut_d_ready = buffer_1_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_auto_in_d_valid = buffer_1_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_bits_opcode = buffer_1_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_bits_param = buffer_1_nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_bits_size = buffer_1_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_bits_source = buffer_1_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_bits_sink = buffer_1_nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_bits_denied = buffer_1_nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_bits_data = buffer_1_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_bits_corrupt = buffer_1_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [28:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_bus_xingOut_a_ready = coupler_to_bus_named_pbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_pbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [28:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_pbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_pbus_bus_xingOut_d_valid = coupler_to_bus_named_pbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_param = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_size = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_source = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_data = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_pbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonIn_a_valid = coupler_to_bus_named_pbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [28:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_address = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonIn_d_ready = coupler_to_bus_named_pbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_pbus_widget_anonOut_a_ready = coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_pbus_bus_xingIn_a_valid = coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [28:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [28:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_address = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_pbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_bus_xingIn_d_ready = coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_pbus_widget_anonOut_d_valid = coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [7:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_anonIn_a_ready = coupler_to_bus_named_pbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_pbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_pbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_pbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_pbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_pbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_pbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_pbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_anonIn_d_valid = coupler_to_bus_named_pbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_pbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_param = coupler_to_bus_named_pbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_size = coupler_to_bus_named_pbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_source = coupler_to_bus_named_pbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_pbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_pbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_data = coupler_to_bus_named_pbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_pbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_pbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_anonOut_a_valid = coupler_to_bus_named_pbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_pbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_param = coupler_to_bus_named_pbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_size = coupler_to_bus_named_pbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_source = coupler_to_bus_named_pbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_address = coupler_to_bus_named_pbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_pbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_data = coupler_to_bus_named_pbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_pbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_anonOut_d_ready = coupler_to_bus_named_pbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_pbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_pbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_pbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_pbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_pbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_bus_xingIn_a_ready = coupler_to_bus_named_pbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_pbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_pbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_pbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_pbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_pbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_pbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_pbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_valid = coupler_to_bus_named_pbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_pbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_param = coupler_to_bus_named_pbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_size = coupler_to_bus_named_pbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_source = coupler_to_bus_named_pbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_pbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_pbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_data = coupler_to_bus_named_pbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_pbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_pbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_bus_xingOut_a_valid = coupler_to_bus_named_pbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_pbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_param = coupler_to_bus_named_pbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_size = coupler_to_bus_named_pbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_source = coupler_to_bus_named_pbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_address = coupler_to_bus_named_pbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_pbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_data = coupler_to_bus_named_pbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_pbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_bus_xingOut_d_ready = coupler_to_bus_named_pbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_pbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_pbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_pbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_pbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_pbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_from_port_named_custom_boot_pin_tlIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready; // @[MixedNode.scala:542:17]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_a_valid = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid; // @[MixedNode.scala:551:17]
wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [28:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_address = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address; // @[MixedNode.scala:551:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire nodeOut_d_valid = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeOut_d_bits_opcode = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_d_bits_param = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_d_bits_size = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire nodeOut_d_bits_sink = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeOut_d_bits_denied = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] nodeOut_d_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlOut_a_ready = coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [28:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlOut_d_valid = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_opcode = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_param = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_size = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_sink = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_denied = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire [28:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7]
assign coupler_from_port_named_custom_boot_pin_tlIn_a_ready = coupler_from_port_named_custom_boot_pin_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid = coupler_from_port_named_custom_boot_pin_tlOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address = coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data = coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_port_named_custom_boot_pin_tlIn_d_valid = coupler_from_port_named_custom_boot_pin_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready = coupler_from_port_named_custom_boot_pin_tlIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_from_port_named_custom_boot_pin_tlOut_a_valid = coupler_from_port_named_custom_boot_pin_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address = coupler_from_port_named_custom_boot_pin_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data = coupler_from_port_named_custom_boot_pin_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid = coupler_from_port_named_custom_boot_pin_tlIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_1_auto_in_a_valid = bus_xingOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_a_bits_opcode = bus_xingOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_a_bits_param = bus_xingOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_a_bits_size = bus_xingOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_a_bits_source = bus_xingOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_a_bits_address = bus_xingOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_a_bits_mask = bus_xingOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_a_bits_data = bus_xingOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_a_bits_corrupt = bus_xingOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_1_auto_in_d_ready = bus_xingOut_d_ready; // @[Buffer.scala:40:9]
assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9]
assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid = nodeOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address = nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data = nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
reg [2:0] state; // @[CustomBootPin.scala:39:28]
wire _T_1 = state == 3'h1; // @[CustomBootPin.scala:39:28, :43:24]
assign nodeOut_a_valid = (|state) & (_T_1 | state != 3'h2 & state == 3'h3); // @[CustomBootPin.scala:39:28, :40:20, :43:24, :46:24]
assign nodeOut_a_bits_address = _T_1 ? 29'h1000 : 29'h2000000; // @[CustomBootPin.scala:43:24, :47:23]
assign nodeOut_a_bits_data = _T_1 ? 64'h80000000 : 64'h1; // @[CustomBootPin.scala:43:24, :47:23]
wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35]
wire [2:0] _GEN = state == 3'h5 & ~custom_boot ? 3'h0 : state; // @[CustomBootPin.scala:39:28, :43:24, :67:{29,43,51}]
wire [7:0][2:0] _GEN_0 = {{_GEN}, {_GEN}, {_GEN}, {nodeOut_d_valid ? 3'h5 : state}, {nodeOut_a_ready & nodeOut_a_valid ? 3'h4 : state}, {nodeOut_d_valid ? 3'h3 : state}, {nodeOut_a_ready & nodeOut_a_valid ? 3'h2 : state}, {custom_boot ? 3'h1 : state}}; // @[Decoupled.scala:51:35]
always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31]
if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31]
fixer_a_first_counter <= 9'h0; // @[Edges.scala:229:27]
fixer_d_first_counter <= 9'h0; // @[Edges.scala:229:27]
fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_3 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_4 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_5 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_6 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_7 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_8 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_9 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_10 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_11 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_12 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_13 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_14 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_15 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_16 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_17 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_18 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_19 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_20 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_21 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_22 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_23 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_24 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_25 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_26 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_27 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_28 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_29 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_30 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_31 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_32 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_33 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_34 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_35 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_36 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_37 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_38 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_39 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_40 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_41 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_42 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_43 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_44 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_45 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_46 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_47 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_48 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_49 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_50 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_51 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_52 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_53 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_54 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_55 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_56 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_57 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_58 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_59 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_60 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_61 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_62 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_63 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_64 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_65 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_66 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_67 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_68 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_69 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_70 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_71 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_72 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_73 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_74 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_75 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_76 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_77 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_78 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_79 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_80 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_81 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_82 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_83 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_84 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_85 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_86 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_87 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_88 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_89 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_90 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_91 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_92 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_93 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_94 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_95 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_96 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_97 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_98 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_99 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_100 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_101 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_102 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_103 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_104 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_105 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_106 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_107 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_108 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_109 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_110 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_111 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_112 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_113 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_114 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_115 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_116 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_117 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_118 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_119 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_120 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_121 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_122 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_123 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_124 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_125 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_126 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_127 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_128 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_SourceIdFIFOed <= 129'h0; // @[FIFOFixer.scala:115:35]
state <= 3'h0; // @[CustomBootPin.scala:39:28]
end
else begin // @[LazyModuleImp.scala:155:31]
if (fixer__a_first_T) // @[Decoupled.scala:51:35]
fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21]
if (fixer__d_first_T) // @[Decoupled.scala:51:35]
fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21]
fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h0 | fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1 | fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2 | fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_3 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3 | fixer_flight_3); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_4 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4 | fixer_flight_4); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_5 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5 | fixer_flight_5); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_6 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6 | fixer_flight_6); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_7 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7 | fixer_flight_7); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_8 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h8) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h8 | fixer_flight_8); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_9 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h9) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h9 | fixer_flight_9); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_10 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hA) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hA | fixer_flight_10); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_11 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hB) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hB | fixer_flight_11); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_12 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hC) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hC | fixer_flight_12); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_13 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hD) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hD | fixer_flight_13); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_14 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hE) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hE | fixer_flight_14); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_15 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'hF) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'hF | fixer_flight_15); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_16 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h10) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h10 | fixer_flight_16); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_17 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h11) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h11 | fixer_flight_17); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_18 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h12) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h12 | fixer_flight_18); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_19 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h13) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h13 | fixer_flight_19); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_20 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h14) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h14 | fixer_flight_20); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_21 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h15) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h15 | fixer_flight_21); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_22 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h16) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h16 | fixer_flight_22); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_23 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h17) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h17 | fixer_flight_23); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_24 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h18) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h18 | fixer_flight_24); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_25 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h19) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h19 | fixer_flight_25); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_26 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1A | fixer_flight_26); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_27 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1B | fixer_flight_27); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_28 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1C | fixer_flight_28); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_29 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1D | fixer_flight_29); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_30 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1E | fixer_flight_30); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_31 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h1F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h1F | fixer_flight_31); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_32 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h20) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h20 | fixer_flight_32); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_33 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h21) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h21 | fixer_flight_33); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_34 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h22) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h22 | fixer_flight_34); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_35 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h23) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h23 | fixer_flight_35); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_36 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h24) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h24 | fixer_flight_36); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_37 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h25) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h25 | fixer_flight_37); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_38 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h26) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h26 | fixer_flight_38); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_39 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h27) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h27 | fixer_flight_39); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_40 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h28) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h28 | fixer_flight_40); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_41 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h29) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h29 | fixer_flight_41); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_42 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2A | fixer_flight_42); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_43 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2B | fixer_flight_43); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_44 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2C | fixer_flight_44); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_45 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2D | fixer_flight_45); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_46 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2E | fixer_flight_46); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_47 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h2F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h2F | fixer_flight_47); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_48 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h30) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h30 | fixer_flight_48); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_49 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h31) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h31 | fixer_flight_49); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_50 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h32) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h32 | fixer_flight_50); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_51 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h33) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h33 | fixer_flight_51); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_52 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h34) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h34 | fixer_flight_52); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_53 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h35) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h35 | fixer_flight_53); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_54 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h36) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h36 | fixer_flight_54); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_55 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h37) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h37 | fixer_flight_55); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_56 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h38) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h38 | fixer_flight_56); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_57 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h39) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h39 | fixer_flight_57); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_58 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3A | fixer_flight_58); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_59 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3B | fixer_flight_59); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_60 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3C | fixer_flight_60); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_61 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3D | fixer_flight_61); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_62 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3E | fixer_flight_62); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_63 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h3F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h3F | fixer_flight_63); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_64 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h40) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h40 | fixer_flight_64); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_65 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h41) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h41 | fixer_flight_65); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_66 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h42) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h42 | fixer_flight_66); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_67 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h43) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h43 | fixer_flight_67); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_68 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h44) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h44 | fixer_flight_68); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_69 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h45) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h45 | fixer_flight_69); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_70 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h46) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h46 | fixer_flight_70); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_71 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h47) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h47 | fixer_flight_71); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_72 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h48) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h48 | fixer_flight_72); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_73 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h49) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h49 | fixer_flight_73); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_74 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4A | fixer_flight_74); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_75 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4B | fixer_flight_75); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_76 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4C | fixer_flight_76); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_77 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4D | fixer_flight_77); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_78 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4E | fixer_flight_78); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_79 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h4F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h4F | fixer_flight_79); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_80 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h50) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h50 | fixer_flight_80); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_81 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h51) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h51 | fixer_flight_81); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_82 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h52) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h52 | fixer_flight_82); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_83 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h53) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h53 | fixer_flight_83); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_84 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h54) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h54 | fixer_flight_84); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_85 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h55) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h55 | fixer_flight_85); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_86 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h56) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h56 | fixer_flight_86); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_87 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h57) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h57 | fixer_flight_87); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_88 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h58) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h58 | fixer_flight_88); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_89 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h59) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h59 | fixer_flight_89); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_90 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5A | fixer_flight_90); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_91 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5B | fixer_flight_91); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_92 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5C | fixer_flight_92); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_93 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5D | fixer_flight_93); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_94 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5E | fixer_flight_94); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_95 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h5F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h5F | fixer_flight_95); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_96 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h60) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h60 | fixer_flight_96); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_97 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h61) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h61 | fixer_flight_97); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_98 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h62) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h62 | fixer_flight_98); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_99 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h63) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h63 | fixer_flight_99); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_100 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h64) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h64 | fixer_flight_100); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_101 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h65) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h65 | fixer_flight_101); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_102 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h66) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h66 | fixer_flight_102); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_103 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h67) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h67 | fixer_flight_103); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_104 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h68) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h68 | fixer_flight_104); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_105 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h69) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h69 | fixer_flight_105); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_106 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6A | fixer_flight_106); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_107 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6B | fixer_flight_107); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_108 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6C | fixer_flight_108); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_109 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6D | fixer_flight_109); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_110 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6E | fixer_flight_110); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_111 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h6F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h6F | fixer_flight_111); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_112 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h70) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h70 | fixer_flight_112); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_113 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h71) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h71 | fixer_flight_113); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_114 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h72) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h72 | fixer_flight_114); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_115 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h73) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h73 | fixer_flight_115); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_116 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h74) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h74 | fixer_flight_116); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_117 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h75) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h75 | fixer_flight_117); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_118 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h76) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h76 | fixer_flight_118); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_119 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h77) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h77 | fixer_flight_119); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_120 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h78) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h78 | fixer_flight_120); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_121 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h79) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h79 | fixer_flight_121); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_122 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7A) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7A | fixer_flight_122); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_123 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7B) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7B | fixer_flight_123); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_124 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7C) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7C | fixer_flight_124); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_125 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7D) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7D | fixer_flight_125); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_126 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7E) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7E | fixer_flight_126); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_127 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h7F) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h7F | fixer_flight_127); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_flight_128 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 8'h80) & (fixer__T_1 & fixer_anonIn_a_bits_source == 8'h80 | fixer_flight_128); // @[FIFOFixer.scala:79:27, :80:{21,35,62}, :81:{21,35,62}]
fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40]
state <= _GEN_0[state]; // @[CustomBootPin.scala:39:28, :43:24, :44:46, :53:30, :55:58, :64:30, :66:50]
end
always @(posedge)
FixedClockBroadcast_7_1 fixedClockNode ( // @[ClockGroup.scala:115:114]
.auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9]
.auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9]
.auto_anon_out_6_clock (auto_fixedClockNode_anon_out_5_clock_0),
.auto_anon_out_6_reset (auto_fixedClockNode_anon_out_5_reset_0),
.auto_anon_out_5_clock (auto_fixedClockNode_anon_out_4_clock_0),
.auto_anon_out_5_reset (auto_fixedClockNode_anon_out_4_reset_0),
.auto_anon_out_4_clock (auto_fixedClockNode_anon_out_3_clock_0),
.auto_anon_out_4_reset (auto_fixedClockNode_anon_out_3_reset_0),
.auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock_0),
.auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset_0),
.auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0),
.auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0),
.auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0),
.auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0),
.auto_anon_out_0_clock (clockSinkNodeIn_clock),
.auto_anon_out_0_reset (clockSinkNodeIn_reset)
); // @[ClockGroup.scala:115:114]
TLXbar_cbus_in_i2_o1_a29d64s8k1z4u in_xbar ( // @[PeripheryBus.scala:56:29]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_1_a_ready (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready),
.auto_anon_in_1_a_valid (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_1_a_bits_address (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_1_a_bits_data (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data), // @[LazyModuleImp.scala:138:7]
.auto_anon_in_1_d_valid (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid),
.auto_anon_in_1_d_bits_opcode (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode),
.auto_anon_in_1_d_bits_param (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param),
.auto_anon_in_1_d_bits_size (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size),
.auto_anon_in_1_d_bits_sink (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink),
.auto_anon_in_1_d_bits_denied (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied),
.auto_anon_in_1_d_bits_data (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data),
.auto_anon_in_1_d_bits_corrupt (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt),
.auto_anon_in_0_a_ready (buffer_1_auto_out_a_ready),
.auto_anon_in_0_a_valid (buffer_1_auto_out_a_valid), // @[Buffer.scala:40:9]
.auto_anon_in_0_a_bits_opcode (buffer_1_auto_out_a_bits_opcode), // @[Buffer.scala:40:9]
.auto_anon_in_0_a_bits_param (buffer_1_auto_out_a_bits_param), // @[Buffer.scala:40:9]
.auto_anon_in_0_a_bits_size (buffer_1_auto_out_a_bits_size), // @[Buffer.scala:40:9]
.auto_anon_in_0_a_bits_source (buffer_1_auto_out_a_bits_source), // @[Buffer.scala:40:9]
.auto_anon_in_0_a_bits_address (buffer_1_auto_out_a_bits_address), // @[Buffer.scala:40:9]
.auto_anon_in_0_a_bits_mask (buffer_1_auto_out_a_bits_mask), // @[Buffer.scala:40:9]
.auto_anon_in_0_a_bits_data (buffer_1_auto_out_a_bits_data), // @[Buffer.scala:40:9]
.auto_anon_in_0_a_bits_corrupt (buffer_1_auto_out_a_bits_corrupt), // @[Buffer.scala:40:9]
.auto_anon_in_0_d_ready (buffer_1_auto_out_d_ready), // @[Buffer.scala:40:9]
.auto_anon_in_0_d_valid (buffer_1_auto_out_d_valid),
.auto_anon_in_0_d_bits_opcode (buffer_1_auto_out_d_bits_opcode),
.auto_anon_in_0_d_bits_param (buffer_1_auto_out_d_bits_param),
.auto_anon_in_0_d_bits_size (buffer_1_auto_out_d_bits_size),
.auto_anon_in_0_d_bits_source (buffer_1_auto_out_d_bits_source),
.auto_anon_in_0_d_bits_sink (buffer_1_auto_out_d_bits_sink),
.auto_anon_in_0_d_bits_denied (buffer_1_auto_out_d_bits_denied),
.auto_anon_in_0_d_bits_data (buffer_1_auto_out_d_bits_data),
.auto_anon_in_0_d_bits_corrupt (buffer_1_auto_out_d_bits_corrupt),
.auto_anon_out_a_ready (_atomics_auto_in_a_ready), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_a_valid (_in_xbar_auto_anon_out_a_valid),
.auto_anon_out_a_bits_opcode (_in_xbar_auto_anon_out_a_bits_opcode),
.auto_anon_out_a_bits_param (_in_xbar_auto_anon_out_a_bits_param),
.auto_anon_out_a_bits_size (_in_xbar_auto_anon_out_a_bits_size),
.auto_anon_out_a_bits_source (_in_xbar_auto_anon_out_a_bits_source),
.auto_anon_out_a_bits_address (_in_xbar_auto_anon_out_a_bits_address),
.auto_anon_out_a_bits_mask (_in_xbar_auto_anon_out_a_bits_mask),
.auto_anon_out_a_bits_data (_in_xbar_auto_anon_out_a_bits_data),
.auto_anon_out_a_bits_corrupt (_in_xbar_auto_anon_out_a_bits_corrupt),
.auto_anon_out_d_ready (_in_xbar_auto_anon_out_d_ready),
.auto_anon_out_d_valid (_atomics_auto_in_d_valid), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_d_bits_opcode (_atomics_auto_in_d_bits_opcode), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_d_bits_param (_atomics_auto_in_d_bits_param), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_d_bits_size (_atomics_auto_in_d_bits_size), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_d_bits_source (_atomics_auto_in_d_bits_source), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_d_bits_sink (_atomics_auto_in_d_bits_sink), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_d_bits_denied (_atomics_auto_in_d_bits_denied), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_d_bits_data (_atomics_auto_in_d_bits_data), // @[AtomicAutomata.scala:289:29]
.auto_anon_out_d_bits_corrupt (_atomics_auto_in_d_bits_corrupt) // @[AtomicAutomata.scala:289:29]
); // @[PeripheryBus.scala:56:29]
TLXbar_cbus_out_i1_o8_a29d64s8k1z4u out_xbar ( // @[PeripheryBus.scala:57:30]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_a_ready (fixer_auto_anon_out_a_ready),
.auto_anon_in_a_valid (fixer_auto_anon_out_a_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_opcode (fixer_auto_anon_out_a_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_param (fixer_auto_anon_out_a_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_size (fixer_auto_anon_out_a_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_source (fixer_auto_anon_out_a_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_address (fixer_auto_anon_out_a_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_mask (fixer_auto_anon_out_a_bits_mask), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_data (fixer_auto_anon_out_a_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_a_bits_corrupt (fixer_auto_anon_out_a_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_d_ready (fixer_auto_anon_out_d_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_d_valid (fixer_auto_anon_out_d_valid),
.auto_anon_in_d_bits_opcode (fixer_auto_anon_out_d_bits_opcode),
.auto_anon_in_d_bits_param (fixer_auto_anon_out_d_bits_param),
.auto_anon_in_d_bits_size (fixer_auto_anon_out_d_bits_size),
.auto_anon_in_d_bits_source (fixer_auto_anon_out_d_bits_source),
.auto_anon_in_d_bits_sink (fixer_auto_anon_out_d_bits_sink),
.auto_anon_in_d_bits_denied (fixer_auto_anon_out_d_bits_denied),
.auto_anon_in_d_bits_data (fixer_auto_anon_out_d_bits_data),
.auto_anon_in_d_bits_corrupt (fixer_auto_anon_out_d_bits_corrupt),
.auto_anon_out_7_a_ready (_coupler_to_prci_ctrl_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_7_a_valid (_out_xbar_auto_anon_out_7_a_valid),
.auto_anon_out_7_a_bits_opcode (_out_xbar_auto_anon_out_7_a_bits_opcode),
.auto_anon_out_7_a_bits_param (_out_xbar_auto_anon_out_7_a_bits_param),
.auto_anon_out_7_a_bits_size (_out_xbar_auto_anon_out_7_a_bits_size),
.auto_anon_out_7_a_bits_source (_out_xbar_auto_anon_out_7_a_bits_source),
.auto_anon_out_7_a_bits_address (_out_xbar_auto_anon_out_7_a_bits_address),
.auto_anon_out_7_a_bits_mask (_out_xbar_auto_anon_out_7_a_bits_mask),
.auto_anon_out_7_a_bits_data (_out_xbar_auto_anon_out_7_a_bits_data),
.auto_anon_out_7_a_bits_corrupt (_out_xbar_auto_anon_out_7_a_bits_corrupt),
.auto_anon_out_7_d_ready (_out_xbar_auto_anon_out_7_d_ready),
.auto_anon_out_7_d_valid (_coupler_to_prci_ctrl_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_7_d_bits_opcode (_coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_7_d_bits_param (_coupler_to_prci_ctrl_auto_tl_in_d_bits_param), // @[LazyScope.scala:98:27]
.auto_anon_out_7_d_bits_size (_coupler_to_prci_ctrl_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_7_d_bits_source (_coupler_to_prci_ctrl_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_7_d_bits_sink (_coupler_to_prci_ctrl_auto_tl_in_d_bits_sink), // @[LazyScope.scala:98:27]
.auto_anon_out_7_d_bits_denied (_coupler_to_prci_ctrl_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27]
.auto_anon_out_7_d_bits_data (_coupler_to_prci_ctrl_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_7_d_bits_corrupt (_coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27]
.auto_anon_out_6_a_ready (_coupler_to_bootrom_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_6_a_valid (_out_xbar_auto_anon_out_6_a_valid),
.auto_anon_out_6_a_bits_opcode (_out_xbar_auto_anon_out_6_a_bits_opcode),
.auto_anon_out_6_a_bits_param (_out_xbar_auto_anon_out_6_a_bits_param),
.auto_anon_out_6_a_bits_size (_out_xbar_auto_anon_out_6_a_bits_size),
.auto_anon_out_6_a_bits_source (_out_xbar_auto_anon_out_6_a_bits_source),
.auto_anon_out_6_a_bits_address (_out_xbar_auto_anon_out_6_a_bits_address),
.auto_anon_out_6_a_bits_mask (_out_xbar_auto_anon_out_6_a_bits_mask),
.auto_anon_out_6_a_bits_data (_out_xbar_auto_anon_out_6_a_bits_data),
.auto_anon_out_6_a_bits_corrupt (_out_xbar_auto_anon_out_6_a_bits_corrupt),
.auto_anon_out_6_d_ready (_out_xbar_auto_anon_out_6_d_ready),
.auto_anon_out_6_d_valid (_coupler_to_bootrom_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_6_d_bits_size (_coupler_to_bootrom_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_6_d_bits_source (_coupler_to_bootrom_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_6_d_bits_data (_coupler_to_bootrom_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_5_a_ready (_coupler_to_debug_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_5_a_valid (_out_xbar_auto_anon_out_5_a_valid),
.auto_anon_out_5_a_bits_opcode (_out_xbar_auto_anon_out_5_a_bits_opcode),
.auto_anon_out_5_a_bits_param (_out_xbar_auto_anon_out_5_a_bits_param),
.auto_anon_out_5_a_bits_size (_out_xbar_auto_anon_out_5_a_bits_size),
.auto_anon_out_5_a_bits_source (_out_xbar_auto_anon_out_5_a_bits_source),
.auto_anon_out_5_a_bits_address (_out_xbar_auto_anon_out_5_a_bits_address),
.auto_anon_out_5_a_bits_mask (_out_xbar_auto_anon_out_5_a_bits_mask),
.auto_anon_out_5_a_bits_data (_out_xbar_auto_anon_out_5_a_bits_data),
.auto_anon_out_5_a_bits_corrupt (_out_xbar_auto_anon_out_5_a_bits_corrupt),
.auto_anon_out_5_d_ready (_out_xbar_auto_anon_out_5_d_ready),
.auto_anon_out_5_d_valid (_coupler_to_debug_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_5_d_bits_opcode (_coupler_to_debug_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_5_d_bits_size (_coupler_to_debug_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_5_d_bits_source (_coupler_to_debug_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_5_d_bits_data (_coupler_to_debug_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_4_a_ready (_coupler_to_plic_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_4_a_valid (_out_xbar_auto_anon_out_4_a_valid),
.auto_anon_out_4_a_bits_opcode (_out_xbar_auto_anon_out_4_a_bits_opcode),
.auto_anon_out_4_a_bits_param (_out_xbar_auto_anon_out_4_a_bits_param),
.auto_anon_out_4_a_bits_size (_out_xbar_auto_anon_out_4_a_bits_size),
.auto_anon_out_4_a_bits_source (_out_xbar_auto_anon_out_4_a_bits_source),
.auto_anon_out_4_a_bits_address (_out_xbar_auto_anon_out_4_a_bits_address),
.auto_anon_out_4_a_bits_mask (_out_xbar_auto_anon_out_4_a_bits_mask),
.auto_anon_out_4_a_bits_data (_out_xbar_auto_anon_out_4_a_bits_data),
.auto_anon_out_4_a_bits_corrupt (_out_xbar_auto_anon_out_4_a_bits_corrupt),
.auto_anon_out_4_d_ready (_out_xbar_auto_anon_out_4_d_ready),
.auto_anon_out_4_d_valid (_coupler_to_plic_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_4_d_bits_opcode (_coupler_to_plic_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_4_d_bits_size (_coupler_to_plic_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_4_d_bits_source (_coupler_to_plic_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_4_d_bits_data (_coupler_to_plic_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_3_a_ready (_coupler_to_clint_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_3_a_valid (_out_xbar_auto_anon_out_3_a_valid),
.auto_anon_out_3_a_bits_opcode (_out_xbar_auto_anon_out_3_a_bits_opcode),
.auto_anon_out_3_a_bits_param (_out_xbar_auto_anon_out_3_a_bits_param),
.auto_anon_out_3_a_bits_size (_out_xbar_auto_anon_out_3_a_bits_size),
.auto_anon_out_3_a_bits_source (_out_xbar_auto_anon_out_3_a_bits_source),
.auto_anon_out_3_a_bits_address (_out_xbar_auto_anon_out_3_a_bits_address),
.auto_anon_out_3_a_bits_mask (_out_xbar_auto_anon_out_3_a_bits_mask),
.auto_anon_out_3_a_bits_data (_out_xbar_auto_anon_out_3_a_bits_data),
.auto_anon_out_3_a_bits_corrupt (_out_xbar_auto_anon_out_3_a_bits_corrupt),
.auto_anon_out_3_d_ready (_out_xbar_auto_anon_out_3_d_ready),
.auto_anon_out_3_d_valid (_coupler_to_clint_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_3_d_bits_opcode (_coupler_to_clint_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_3_d_bits_size (_coupler_to_clint_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_3_d_bits_source (_coupler_to_clint_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_3_d_bits_data (_coupler_to_clint_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_2_a_ready (coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_2_a_valid (coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid),
.auto_anon_out_2_a_bits_opcode (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode),
.auto_anon_out_2_a_bits_param (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param),
.auto_anon_out_2_a_bits_size (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size),
.auto_anon_out_2_a_bits_source (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source),
.auto_anon_out_2_a_bits_address (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address),
.auto_anon_out_2_a_bits_mask (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask),
.auto_anon_out_2_a_bits_data (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data),
.auto_anon_out_2_a_bits_corrupt (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt),
.auto_anon_out_2_d_ready (coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready),
.auto_anon_out_2_d_valid (coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_2_d_bits_opcode (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_2_d_bits_param (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_2_d_bits_size (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_2_d_bits_source (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_2_d_bits_sink (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_2_d_bits_denied (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_2_d_bits_data (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_2_d_bits_corrupt (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt), // @[LazyModuleImp.scala:138:7]
.auto_anon_out_1_a_ready (_coupler_to_l2_ctrl_auto_tl_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_1_a_valid (_out_xbar_auto_anon_out_1_a_valid),
.auto_anon_out_1_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode),
.auto_anon_out_1_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param),
.auto_anon_out_1_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size),
.auto_anon_out_1_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source),
.auto_anon_out_1_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address),
.auto_anon_out_1_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask),
.auto_anon_out_1_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data),
.auto_anon_out_1_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt),
.auto_anon_out_1_d_ready (_out_xbar_auto_anon_out_1_d_ready),
.auto_anon_out_1_d_valid (_coupler_to_l2_ctrl_auto_tl_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_1_d_bits_opcode (_coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_1_d_bits_param (_coupler_to_l2_ctrl_auto_tl_in_d_bits_param), // @[LazyScope.scala:98:27]
.auto_anon_out_1_d_bits_size (_coupler_to_l2_ctrl_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_1_d_bits_source (_coupler_to_l2_ctrl_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_1_d_bits_sink (_coupler_to_l2_ctrl_auto_tl_in_d_bits_sink), // @[LazyScope.scala:98:27]
.auto_anon_out_1_d_bits_denied (_coupler_to_l2_ctrl_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27]
.auto_anon_out_1_d_bits_data (_coupler_to_l2_ctrl_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_1_d_bits_corrupt (_coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27]
.auto_anon_out_0_a_ready (_wrapped_error_device_auto_buffer_in_a_ready), // @[LazyScope.scala:98:27]
.auto_anon_out_0_a_valid (_out_xbar_auto_anon_out_0_a_valid),
.auto_anon_out_0_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode),
.auto_anon_out_0_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param),
.auto_anon_out_0_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size),
.auto_anon_out_0_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source),
.auto_anon_out_0_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address),
.auto_anon_out_0_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask),
.auto_anon_out_0_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data),
.auto_anon_out_0_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt),
.auto_anon_out_0_d_ready (_out_xbar_auto_anon_out_0_d_ready),
.auto_anon_out_0_d_valid (_wrapped_error_device_auto_buffer_in_d_valid), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_opcode (_wrapped_error_device_auto_buffer_in_d_bits_opcode), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_param (_wrapped_error_device_auto_buffer_in_d_bits_param), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_size (_wrapped_error_device_auto_buffer_in_d_bits_size), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_source (_wrapped_error_device_auto_buffer_in_d_bits_source), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_sink (_wrapped_error_device_auto_buffer_in_d_bits_sink), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_denied (_wrapped_error_device_auto_buffer_in_d_bits_denied), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_data (_wrapped_error_device_auto_buffer_in_d_bits_data), // @[LazyScope.scala:98:27]
.auto_anon_out_0_d_bits_corrupt (_wrapped_error_device_auto_buffer_in_d_bits_corrupt) // @[LazyScope.scala:98:27]
); // @[PeripheryBus.scala:57:30]
TLBuffer_a29d64s8k1z4u buffer ( // @[Buffer.scala:75:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (_buffer_auto_in_a_ready),
.auto_in_a_valid (_atomics_auto_out_a_valid), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_opcode (_atomics_auto_out_a_bits_opcode), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_param (_atomics_auto_out_a_bits_param), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_size (_atomics_auto_out_a_bits_size), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_source (_atomics_auto_out_a_bits_source), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_address (_atomics_auto_out_a_bits_address), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_mask (_atomics_auto_out_a_bits_mask), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_data (_atomics_auto_out_a_bits_data), // @[AtomicAutomata.scala:289:29]
.auto_in_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), // @[AtomicAutomata.scala:289:29]
.auto_in_d_ready (_atomics_auto_out_d_ready), // @[AtomicAutomata.scala:289:29]
.auto_in_d_valid (_buffer_auto_in_d_valid),
.auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_buffer_auto_in_d_bits_param),
.auto_in_d_bits_size (_buffer_auto_in_d_bits_size),
.auto_in_d_bits_source (_buffer_auto_in_d_bits_source),
.auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied),
.auto_in_d_bits_data (_buffer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt),
.auto_out_a_ready (fixer_auto_anon_in_a_ready), // @[FIFOFixer.scala:50:9]
.auto_out_a_valid (fixer_auto_anon_in_a_valid),
.auto_out_a_bits_opcode (fixer_auto_anon_in_a_bits_opcode),
.auto_out_a_bits_param (fixer_auto_anon_in_a_bits_param),
.auto_out_a_bits_size (fixer_auto_anon_in_a_bits_size),
.auto_out_a_bits_source (fixer_auto_anon_in_a_bits_source),
.auto_out_a_bits_address (fixer_auto_anon_in_a_bits_address),
.auto_out_a_bits_mask (fixer_auto_anon_in_a_bits_mask),
.auto_out_a_bits_data (fixer_auto_anon_in_a_bits_data),
.auto_out_a_bits_corrupt (fixer_auto_anon_in_a_bits_corrupt),
.auto_out_d_ready (fixer_auto_anon_in_d_ready),
.auto_out_d_valid (fixer_auto_anon_in_d_valid), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_opcode (fixer_auto_anon_in_d_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_param (fixer_auto_anon_in_d_bits_param), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_size (fixer_auto_anon_in_d_bits_size), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_source (fixer_auto_anon_in_d_bits_source), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_sink (fixer_auto_anon_in_d_bits_sink), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_denied (fixer_auto_anon_in_d_bits_denied), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_data (fixer_auto_anon_in_d_bits_data), // @[FIFOFixer.scala:50:9]
.auto_out_d_bits_corrupt (fixer_auto_anon_in_d_bits_corrupt) // @[FIFOFixer.scala:50:9]
); // @[Buffer.scala:75:28]
TLAtomicAutomata_cbus atomics ( // @[AtomicAutomata.scala:289:29]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (_atomics_auto_in_a_ready),
.auto_in_a_valid (_in_xbar_auto_anon_out_a_valid), // @[PeripheryBus.scala:56:29]
.auto_in_a_bits_opcode (_in_xbar_auto_anon_out_a_bits_opcode), // @[PeripheryBus.scala:56:29]
.auto_in_a_bits_param (_in_xbar_auto_anon_out_a_bits_param), // @[PeripheryBus.scala:56:29]
.auto_in_a_bits_size (_in_xbar_auto_anon_out_a_bits_size), // @[PeripheryBus.scala:56:29]
.auto_in_a_bits_source (_in_xbar_auto_anon_out_a_bits_source), // @[PeripheryBus.scala:56:29]
.auto_in_a_bits_address (_in_xbar_auto_anon_out_a_bits_address), // @[PeripheryBus.scala:56:29]
.auto_in_a_bits_mask (_in_xbar_auto_anon_out_a_bits_mask), // @[PeripheryBus.scala:56:29]
.auto_in_a_bits_data (_in_xbar_auto_anon_out_a_bits_data), // @[PeripheryBus.scala:56:29]
.auto_in_a_bits_corrupt (_in_xbar_auto_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:56:29]
.auto_in_d_ready (_in_xbar_auto_anon_out_d_ready), // @[PeripheryBus.scala:56:29]
.auto_in_d_valid (_atomics_auto_in_d_valid),
.auto_in_d_bits_opcode (_atomics_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_atomics_auto_in_d_bits_param),
.auto_in_d_bits_size (_atomics_auto_in_d_bits_size),
.auto_in_d_bits_source (_atomics_auto_in_d_bits_source),
.auto_in_d_bits_sink (_atomics_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_atomics_auto_in_d_bits_denied),
.auto_in_d_bits_data (_atomics_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_atomics_auto_in_d_bits_corrupt),
.auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28]
.auto_out_a_valid (_atomics_auto_out_a_valid),
.auto_out_a_bits_opcode (_atomics_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_atomics_auto_out_a_bits_param),
.auto_out_a_bits_size (_atomics_auto_out_a_bits_size),
.auto_out_a_bits_source (_atomics_auto_out_a_bits_source),
.auto_out_a_bits_address (_atomics_auto_out_a_bits_address),
.auto_out_a_bits_mask (_atomics_auto_out_a_bits_mask),
.auto_out_a_bits_data (_atomics_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt),
.auto_out_d_ready (_atomics_auto_out_d_ready),
.auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28]
.auto_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28]
.auto_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28]
.auto_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28]
.auto_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28]
.auto_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28]
.auto_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28]
.auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28]
.auto_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28]
); // @[AtomicAutomata.scala:289:29]
ErrorDeviceWrapper wrapped_error_device ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_buffer_in_a_ready (_wrapped_error_device_auto_buffer_in_a_ready),
.auto_buffer_in_a_valid (_out_xbar_auto_anon_out_0_a_valid), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_d_ready (_out_xbar_auto_anon_out_0_d_ready), // @[PeripheryBus.scala:57:30]
.auto_buffer_in_d_valid (_wrapped_error_device_auto_buffer_in_d_valid),
.auto_buffer_in_d_bits_opcode (_wrapped_error_device_auto_buffer_in_d_bits_opcode),
.auto_buffer_in_d_bits_param (_wrapped_error_device_auto_buffer_in_d_bits_param),
.auto_buffer_in_d_bits_size (_wrapped_error_device_auto_buffer_in_d_bits_size),
.auto_buffer_in_d_bits_source (_wrapped_error_device_auto_buffer_in_d_bits_source),
.auto_buffer_in_d_bits_sink (_wrapped_error_device_auto_buffer_in_d_bits_sink),
.auto_buffer_in_d_bits_denied (_wrapped_error_device_auto_buffer_in_d_bits_denied),
.auto_buffer_in_d_bits_data (_wrapped_error_device_auto_buffer_in_d_bits_data),
.auto_buffer_in_d_bits_corrupt (_wrapped_error_device_auto_buffer_in_d_bits_corrupt)
); // @[LazyScope.scala:98:27]
TLInterconnectCoupler_cbus_to_l2_ctrl coupler_to_l2_ctrl ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_buffer_out_a_ready (auto_coupler_to_l2_ctrl_buffer_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_a_valid (auto_coupler_to_l2_ctrl_buffer_out_a_valid_0),
.auto_buffer_out_a_bits_opcode (auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0),
.auto_buffer_out_a_bits_param (auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0),
.auto_buffer_out_a_bits_size (auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0),
.auto_buffer_out_a_bits_source (auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0),
.auto_buffer_out_a_bits_address (auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0),
.auto_buffer_out_a_bits_mask (auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0),
.auto_buffer_out_a_bits_data (auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0),
.auto_buffer_out_a_bits_corrupt (auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0),
.auto_buffer_out_d_ready (auto_coupler_to_l2_ctrl_buffer_out_d_ready_0),
.auto_buffer_out_d_valid (auto_coupler_to_l2_ctrl_buffer_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_opcode (auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_size (auto_coupler_to_l2_ctrl_buffer_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_source (auto_coupler_to_l2_ctrl_buffer_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_buffer_out_d_bits_data (auto_coupler_to_l2_ctrl_buffer_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_tl_in_a_ready (_coupler_to_l2_ctrl_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_out_xbar_auto_anon_out_1_a_valid), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_ready (_out_xbar_auto_anon_out_1_d_ready), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_valid (_coupler_to_l2_ctrl_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_param (_coupler_to_l2_ctrl_auto_tl_in_d_bits_param),
.auto_tl_in_d_bits_size (_coupler_to_l2_ctrl_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_l2_ctrl_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_sink (_coupler_to_l2_ctrl_auto_tl_in_d_bits_sink),
.auto_tl_in_d_bits_denied (_coupler_to_l2_ctrl_auto_tl_in_d_bits_denied),
.auto_tl_in_d_bits_data (_coupler_to_l2_ctrl_auto_tl_in_d_bits_data),
.auto_tl_in_d_bits_corrupt (_coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt)
); // @[LazyScope.scala:98:27]
TLInterconnectCoupler_cbus_to_clint coupler_to_clint ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_fragmenter_anon_out_a_ready (auto_coupler_to_clint_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_a_valid (auto_coupler_to_clint_fragmenter_anon_out_a_valid_0),
.auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0),
.auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0),
.auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0),
.auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0),
.auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0),
.auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0),
.auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0),
.auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0),
.auto_fragmenter_anon_out_d_ready (auto_coupler_to_clint_fragmenter_anon_out_d_ready_0),
.auto_fragmenter_anon_out_d_valid (auto_coupler_to_clint_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_clint_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_clint_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_clint_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_tl_in_a_ready (_coupler_to_clint_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_out_xbar_auto_anon_out_3_a_valid), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_3_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_3_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_3_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_3_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_3_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_3_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_3_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_3_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_ready (_out_xbar_auto_anon_out_3_d_ready), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_valid (_coupler_to_clint_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_coupler_to_clint_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_size (_coupler_to_clint_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_clint_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_data (_coupler_to_clint_auto_tl_in_d_bits_data)
); // @[LazyScope.scala:98:27]
TLInterconnectCoupler_cbus_to_plic coupler_to_plic ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_fragmenter_anon_out_a_ready (auto_coupler_to_plic_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_a_valid (auto_coupler_to_plic_fragmenter_anon_out_a_valid_0),
.auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0),
.auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0),
.auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0),
.auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0),
.auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0),
.auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0),
.auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0),
.auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0),
.auto_fragmenter_anon_out_d_ready (auto_coupler_to_plic_fragmenter_anon_out_d_ready_0),
.auto_fragmenter_anon_out_d_valid (auto_coupler_to_plic_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_plic_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_plic_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_plic_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_tl_in_a_ready (_coupler_to_plic_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_out_xbar_auto_anon_out_4_a_valid), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_4_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_4_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_4_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_4_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_4_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_4_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_4_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_4_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_ready (_out_xbar_auto_anon_out_4_d_ready), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_valid (_coupler_to_plic_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_coupler_to_plic_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_size (_coupler_to_plic_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_plic_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_data (_coupler_to_plic_auto_tl_in_d_bits_data)
); // @[LazyScope.scala:98:27]
TLInterconnectCoupler_cbus_to_debug coupler_to_debug ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_fragmenter_anon_out_a_ready (auto_coupler_to_debug_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_a_valid (auto_coupler_to_debug_fragmenter_anon_out_a_valid_0),
.auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0),
.auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0),
.auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0),
.auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0),
.auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0),
.auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0),
.auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0),
.auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0),
.auto_fragmenter_anon_out_d_ready (auto_coupler_to_debug_fragmenter_anon_out_d_ready_0),
.auto_fragmenter_anon_out_d_valid (auto_coupler_to_debug_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_debug_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_debug_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_debug_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_tl_in_a_ready (_coupler_to_debug_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_out_xbar_auto_anon_out_5_a_valid), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_5_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_5_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_5_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_5_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_5_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_5_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_5_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_5_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_ready (_out_xbar_auto_anon_out_5_d_ready), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_valid (_coupler_to_debug_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_coupler_to_debug_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_size (_coupler_to_debug_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_debug_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_data (_coupler_to_debug_auto_tl_in_d_bits_data)
); // @[LazyScope.scala:98:27]
TLInterconnectCoupler_cbus_to_bootrom coupler_to_bootrom ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_fragmenter_anon_out_a_ready (auto_coupler_to_bootrom_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_a_valid (auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0),
.auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0),
.auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0),
.auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0),
.auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0),
.auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0),
.auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0),
.auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0),
.auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0),
.auto_fragmenter_anon_out_d_ready (auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0),
.auto_fragmenter_anon_out_d_valid (auto_coupler_to_bootrom_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_tl_in_a_ready (_coupler_to_bootrom_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_out_xbar_auto_anon_out_6_a_valid), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_6_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_6_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_6_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_6_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_6_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_6_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_6_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_6_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_ready (_out_xbar_auto_anon_out_6_d_ready), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_valid (_coupler_to_bootrom_auto_tl_in_d_valid),
.auto_tl_in_d_bits_size (_coupler_to_bootrom_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_bootrom_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_data (_coupler_to_bootrom_auto_tl_in_d_bits_data)
); // @[LazyScope.scala:98:27]
TLInterconnectCoupler_cbus_to_prci_ctrl coupler_to_prci_ctrl ( // @[LazyScope.scala:98:27]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_fixer_anon_out_a_ready (auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_fixer_anon_out_a_valid (auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0),
.auto_fixer_anon_out_a_bits_opcode (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0),
.auto_fixer_anon_out_a_bits_param (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0),
.auto_fixer_anon_out_a_bits_size (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0),
.auto_fixer_anon_out_a_bits_source (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0),
.auto_fixer_anon_out_a_bits_address (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0),
.auto_fixer_anon_out_a_bits_mask (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0),
.auto_fixer_anon_out_a_bits_data (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0),
.auto_fixer_anon_out_a_bits_corrupt (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0),
.auto_fixer_anon_out_d_ready (auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0),
.auto_fixer_anon_out_d_valid (auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_fixer_anon_out_d_bits_opcode (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_fixer_anon_out_d_bits_size (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_fixer_anon_out_d_bits_source (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_fixer_anon_out_d_bits_data (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_tl_in_a_ready (_coupler_to_prci_ctrl_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_out_xbar_auto_anon_out_7_a_valid), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_7_a_bits_opcode), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_7_a_bits_param), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_7_a_bits_size), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_7_a_bits_source), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_7_a_bits_address), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_7_a_bits_mask), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_7_a_bits_data), // @[PeripheryBus.scala:57:30]
.auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_7_a_bits_corrupt), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_ready (_out_xbar_auto_anon_out_7_d_ready), // @[PeripheryBus.scala:57:30]
.auto_tl_in_d_valid (_coupler_to_prci_ctrl_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_param (_coupler_to_prci_ctrl_auto_tl_in_d_bits_param),
.auto_tl_in_d_bits_size (_coupler_to_prci_ctrl_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_coupler_to_prci_ctrl_auto_tl_in_d_bits_source),
.auto_tl_in_d_bits_sink (_coupler_to_prci_ctrl_auto_tl_in_d_bits_sink),
.auto_tl_in_d_bits_denied (_coupler_to_prci_ctrl_auto_tl_in_d_bits_denied),
.auto_tl_in_d_bits_data (_coupler_to_prci_ctrl_auto_tl_in_d_bits_data),
.auto_tl_in_d_bits_corrupt (_coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt)
); // @[LazyScope.scala:98:27]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid = auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready = auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_valid = auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bootrom_fragmenter_anon_out_d_ready = auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_valid = auto_coupler_to_debug_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_param = auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_size = auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_source = auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_address = auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask = auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_data = auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_debug_fragmenter_anon_out_d_ready = auto_coupler_to_debug_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_valid = auto_coupler_to_plic_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_param = auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_size = auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_source = auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_address = auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask = auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_data = auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_plic_fragmenter_anon_out_d_ready = auto_coupler_to_plic_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_valid = auto_coupler_to_clint_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_param = auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_size = auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_source = auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_address = auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask = auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_data = auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_clint_fragmenter_anon_out_d_ready = auto_coupler_to_clint_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_l2_ctrl_buffer_out_a_valid = auto_coupler_to_l2_ctrl_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode = auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_param = auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_size = auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_source = auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_address = auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask = auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_data = auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt = auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_l2_ctrl_buffer_out_d_ready = auto_coupler_to_l2_ctrl_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_5_clock = auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_5_reset = auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_4_clock = auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_4_reset = auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_3_clock = auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_3_reset = auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_2_clock = auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_2_reset = auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BoomIOMSHR_1 :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}, mem_access : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_ack : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
reg req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>}, clock
reg grant_word : UInt<64>, clock
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
node _io_req_ready_T = eq(state, UInt<2>(0h0))
connect io.req.ready, _io_req_ready_T
wire size : UInt<2>
connect size, req.uop.mem_size
node _get_legal_T = leq(UInt<1>(0h0), req.uop.mem_size)
node _get_legal_T_1 = leq(req.uop.mem_size, UInt<4>(0hc))
node _get_legal_T_2 = and(_get_legal_T, _get_legal_T_1)
node _get_legal_T_3 = or(UInt<1>(0h0), _get_legal_T_2)
node _get_legal_T_4 = xor(req.addr, UInt<14>(0h3000))
node _get_legal_T_5 = cvt(_get_legal_T_4)
node _get_legal_T_6 = and(_get_legal_T_5, asSInt(UInt<33>(0h9a013000)))
node _get_legal_T_7 = asSInt(_get_legal_T_6)
node _get_legal_T_8 = eq(_get_legal_T_7, asSInt(UInt<1>(0h0)))
node _get_legal_T_9 = and(_get_legal_T_3, _get_legal_T_8)
node _get_legal_T_10 = leq(UInt<1>(0h0), req.uop.mem_size)
node _get_legal_T_11 = leq(req.uop.mem_size, UInt<3>(0h6))
node _get_legal_T_12 = and(_get_legal_T_10, _get_legal_T_11)
node _get_legal_T_13 = or(UInt<1>(0h0), _get_legal_T_12)
node _get_legal_T_14 = xor(req.addr, UInt<1>(0h0))
node _get_legal_T_15 = cvt(_get_legal_T_14)
node _get_legal_T_16 = and(_get_legal_T_15, asSInt(UInt<33>(0h9a012000)))
node _get_legal_T_17 = asSInt(_get_legal_T_16)
node _get_legal_T_18 = eq(_get_legal_T_17, asSInt(UInt<1>(0h0)))
node _get_legal_T_19 = xor(req.addr, UInt<17>(0h10000))
node _get_legal_T_20 = cvt(_get_legal_T_19)
node _get_legal_T_21 = and(_get_legal_T_20, asSInt(UInt<33>(0h98013000)))
node _get_legal_T_22 = asSInt(_get_legal_T_21)
node _get_legal_T_23 = eq(_get_legal_T_22, asSInt(UInt<1>(0h0)))
node _get_legal_T_24 = xor(req.addr, UInt<17>(0h10000))
node _get_legal_T_25 = cvt(_get_legal_T_24)
node _get_legal_T_26 = and(_get_legal_T_25, asSInt(UInt<33>(0h9a010000)))
node _get_legal_T_27 = asSInt(_get_legal_T_26)
node _get_legal_T_28 = eq(_get_legal_T_27, asSInt(UInt<1>(0h0)))
node _get_legal_T_29 = xor(req.addr, UInt<26>(0h2000000))
node _get_legal_T_30 = cvt(_get_legal_T_29)
node _get_legal_T_31 = and(_get_legal_T_30, asSInt(UInt<33>(0h9a010000)))
node _get_legal_T_32 = asSInt(_get_legal_T_31)
node _get_legal_T_33 = eq(_get_legal_T_32, asSInt(UInt<1>(0h0)))
node _get_legal_T_34 = xor(req.addr, UInt<28>(0h8000000))
node _get_legal_T_35 = cvt(_get_legal_T_34)
node _get_legal_T_36 = and(_get_legal_T_35, asSInt(UInt<33>(0h98000000)))
node _get_legal_T_37 = asSInt(_get_legal_T_36)
node _get_legal_T_38 = eq(_get_legal_T_37, asSInt(UInt<1>(0h0)))
node _get_legal_T_39 = xor(req.addr, UInt<28>(0h8000000))
node _get_legal_T_40 = cvt(_get_legal_T_39)
node _get_legal_T_41 = and(_get_legal_T_40, asSInt(UInt<33>(0h9a010000)))
node _get_legal_T_42 = asSInt(_get_legal_T_41)
node _get_legal_T_43 = eq(_get_legal_T_42, asSInt(UInt<1>(0h0)))
node _get_legal_T_44 = xor(req.addr, UInt<29>(0h10000000))
node _get_legal_T_45 = cvt(_get_legal_T_44)
node _get_legal_T_46 = and(_get_legal_T_45, asSInt(UInt<33>(0h9a013000)))
node _get_legal_T_47 = asSInt(_get_legal_T_46)
node _get_legal_T_48 = eq(_get_legal_T_47, asSInt(UInt<1>(0h0)))
node _get_legal_T_49 = xor(req.addr, UInt<32>(0h80000000))
node _get_legal_T_50 = cvt(_get_legal_T_49)
node _get_legal_T_51 = and(_get_legal_T_50, asSInt(UInt<33>(0h90000000)))
node _get_legal_T_52 = asSInt(_get_legal_T_51)
node _get_legal_T_53 = eq(_get_legal_T_52, asSInt(UInt<1>(0h0)))
node _get_legal_T_54 = or(_get_legal_T_18, _get_legal_T_23)
node _get_legal_T_55 = or(_get_legal_T_54, _get_legal_T_28)
node _get_legal_T_56 = or(_get_legal_T_55, _get_legal_T_33)
node _get_legal_T_57 = or(_get_legal_T_56, _get_legal_T_38)
node _get_legal_T_58 = or(_get_legal_T_57, _get_legal_T_43)
node _get_legal_T_59 = or(_get_legal_T_58, _get_legal_T_48)
node _get_legal_T_60 = or(_get_legal_T_59, _get_legal_T_53)
node _get_legal_T_61 = and(_get_legal_T_13, _get_legal_T_60)
node _get_legal_T_62 = or(UInt<1>(0h0), _get_legal_T_9)
node get_legal = or(_get_legal_T_62, _get_legal_T_61)
wire get : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect get.opcode, UInt<3>(0h4)
connect get.param, UInt<1>(0h0)
connect get.size, req.uop.mem_size
connect get.source, UInt<2>(0h3)
connect get.address, req.addr
node _get_a_mask_sizeOH_T = or(req.uop.mem_size, UInt<3>(0h0))
node get_a_mask_sizeOH_shiftAmount = bits(_get_a_mask_sizeOH_T, 1, 0)
node _get_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), get_a_mask_sizeOH_shiftAmount)
node _get_a_mask_sizeOH_T_2 = bits(_get_a_mask_sizeOH_T_1, 2, 0)
node get_a_mask_sizeOH = or(_get_a_mask_sizeOH_T_2, UInt<1>(0h1))
node get_a_mask_sub_sub_sub_0_1 = geq(req.uop.mem_size, UInt<2>(0h3))
node get_a_mask_sub_sub_size = bits(get_a_mask_sizeOH, 2, 2)
node get_a_mask_sub_sub_bit = bits(req.addr, 2, 2)
node get_a_mask_sub_sub_nbit = eq(get_a_mask_sub_sub_bit, UInt<1>(0h0))
node get_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_nbit)
node _get_a_mask_sub_sub_acc_T = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_0_2)
node get_a_mask_sub_sub_0_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T)
node get_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_bit)
node _get_a_mask_sub_sub_acc_T_1 = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_1_2)
node get_a_mask_sub_sub_1_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T_1)
node get_a_mask_sub_size = bits(get_a_mask_sizeOH, 1, 1)
node get_a_mask_sub_bit = bits(req.addr, 1, 1)
node get_a_mask_sub_nbit = eq(get_a_mask_sub_bit, UInt<1>(0h0))
node get_a_mask_sub_0_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_nbit)
node _get_a_mask_sub_acc_T = and(get_a_mask_sub_size, get_a_mask_sub_0_2)
node get_a_mask_sub_0_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T)
node get_a_mask_sub_1_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_bit)
node _get_a_mask_sub_acc_T_1 = and(get_a_mask_sub_size, get_a_mask_sub_1_2)
node get_a_mask_sub_1_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T_1)
node get_a_mask_sub_2_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_nbit)
node _get_a_mask_sub_acc_T_2 = and(get_a_mask_sub_size, get_a_mask_sub_2_2)
node get_a_mask_sub_2_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_2)
node get_a_mask_sub_3_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_bit)
node _get_a_mask_sub_acc_T_3 = and(get_a_mask_sub_size, get_a_mask_sub_3_2)
node get_a_mask_sub_3_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_3)
node get_a_mask_size = bits(get_a_mask_sizeOH, 0, 0)
node get_a_mask_bit = bits(req.addr, 0, 0)
node get_a_mask_nbit = eq(get_a_mask_bit, UInt<1>(0h0))
node get_a_mask_eq = and(get_a_mask_sub_0_2, get_a_mask_nbit)
node _get_a_mask_acc_T = and(get_a_mask_size, get_a_mask_eq)
node get_a_mask_acc = or(get_a_mask_sub_0_1, _get_a_mask_acc_T)
node get_a_mask_eq_1 = and(get_a_mask_sub_0_2, get_a_mask_bit)
node _get_a_mask_acc_T_1 = and(get_a_mask_size, get_a_mask_eq_1)
node get_a_mask_acc_1 = or(get_a_mask_sub_0_1, _get_a_mask_acc_T_1)
node get_a_mask_eq_2 = and(get_a_mask_sub_1_2, get_a_mask_nbit)
node _get_a_mask_acc_T_2 = and(get_a_mask_size, get_a_mask_eq_2)
node get_a_mask_acc_2 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_2)
node get_a_mask_eq_3 = and(get_a_mask_sub_1_2, get_a_mask_bit)
node _get_a_mask_acc_T_3 = and(get_a_mask_size, get_a_mask_eq_3)
node get_a_mask_acc_3 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_3)
node get_a_mask_eq_4 = and(get_a_mask_sub_2_2, get_a_mask_nbit)
node _get_a_mask_acc_T_4 = and(get_a_mask_size, get_a_mask_eq_4)
node get_a_mask_acc_4 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_4)
node get_a_mask_eq_5 = and(get_a_mask_sub_2_2, get_a_mask_bit)
node _get_a_mask_acc_T_5 = and(get_a_mask_size, get_a_mask_eq_5)
node get_a_mask_acc_5 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_5)
node get_a_mask_eq_6 = and(get_a_mask_sub_3_2, get_a_mask_nbit)
node _get_a_mask_acc_T_6 = and(get_a_mask_size, get_a_mask_eq_6)
node get_a_mask_acc_6 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_6)
node get_a_mask_eq_7 = and(get_a_mask_sub_3_2, get_a_mask_bit)
node _get_a_mask_acc_T_7 = and(get_a_mask_size, get_a_mask_eq_7)
node get_a_mask_acc_7 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_7)
node get_a_mask_lo_lo = cat(get_a_mask_acc_1, get_a_mask_acc)
node get_a_mask_lo_hi = cat(get_a_mask_acc_3, get_a_mask_acc_2)
node get_a_mask_lo = cat(get_a_mask_lo_hi, get_a_mask_lo_lo)
node get_a_mask_hi_lo = cat(get_a_mask_acc_5, get_a_mask_acc_4)
node get_a_mask_hi_hi = cat(get_a_mask_acc_7, get_a_mask_acc_6)
node get_a_mask_hi = cat(get_a_mask_hi_hi, get_a_mask_hi_lo)
node _get_a_mask_T = cat(get_a_mask_hi, get_a_mask_lo)
connect get.mask, _get_a_mask_T
invalidate get.data
connect get.corrupt, UInt<1>(0h0)
node _put_legal_T = leq(UInt<1>(0h0), req.uop.mem_size)
node _put_legal_T_1 = leq(req.uop.mem_size, UInt<4>(0hc))
node _put_legal_T_2 = and(_put_legal_T, _put_legal_T_1)
node _put_legal_T_3 = or(UInt<1>(0h0), _put_legal_T_2)
node _put_legal_T_4 = xor(req.addr, UInt<14>(0h3000))
node _put_legal_T_5 = cvt(_put_legal_T_4)
node _put_legal_T_6 = and(_put_legal_T_5, asSInt(UInt<33>(0h9a113000)))
node _put_legal_T_7 = asSInt(_put_legal_T_6)
node _put_legal_T_8 = eq(_put_legal_T_7, asSInt(UInt<1>(0h0)))
node _put_legal_T_9 = and(_put_legal_T_3, _put_legal_T_8)
node _put_legal_T_10 = leq(UInt<1>(0h0), req.uop.mem_size)
node _put_legal_T_11 = leq(req.uop.mem_size, UInt<3>(0h6))
node _put_legal_T_12 = and(_put_legal_T_10, _put_legal_T_11)
node _put_legal_T_13 = or(UInt<1>(0h0), _put_legal_T_12)
node _put_legal_T_14 = xor(req.addr, UInt<1>(0h0))
node _put_legal_T_15 = cvt(_put_legal_T_14)
node _put_legal_T_16 = and(_put_legal_T_15, asSInt(UInt<33>(0h9a112000)))
node _put_legal_T_17 = asSInt(_put_legal_T_16)
node _put_legal_T_18 = eq(_put_legal_T_17, asSInt(UInt<1>(0h0)))
node _put_legal_T_19 = xor(req.addr, UInt<21>(0h100000))
node _put_legal_T_20 = cvt(_put_legal_T_19)
node _put_legal_T_21 = and(_put_legal_T_20, asSInt(UInt<33>(0h9a103000)))
node _put_legal_T_22 = asSInt(_put_legal_T_21)
node _put_legal_T_23 = eq(_put_legal_T_22, asSInt(UInt<1>(0h0)))
node _put_legal_T_24 = xor(req.addr, UInt<26>(0h2000000))
node _put_legal_T_25 = cvt(_put_legal_T_24)
node _put_legal_T_26 = and(_put_legal_T_25, asSInt(UInt<33>(0h9a110000)))
node _put_legal_T_27 = asSInt(_put_legal_T_26)
node _put_legal_T_28 = eq(_put_legal_T_27, asSInt(UInt<1>(0h0)))
node _put_legal_T_29 = xor(req.addr, UInt<26>(0h2010000))
node _put_legal_T_30 = cvt(_put_legal_T_29)
node _put_legal_T_31 = and(_put_legal_T_30, asSInt(UInt<33>(0h9a113000)))
node _put_legal_T_32 = asSInt(_put_legal_T_31)
node _put_legal_T_33 = eq(_put_legal_T_32, asSInt(UInt<1>(0h0)))
node _put_legal_T_34 = xor(req.addr, UInt<28>(0h8000000))
node _put_legal_T_35 = cvt(_put_legal_T_34)
node _put_legal_T_36 = and(_put_legal_T_35, asSInt(UInt<33>(0h98000000)))
node _put_legal_T_37 = asSInt(_put_legal_T_36)
node _put_legal_T_38 = eq(_put_legal_T_37, asSInt(UInt<1>(0h0)))
node _put_legal_T_39 = xor(req.addr, UInt<28>(0h8000000))
node _put_legal_T_40 = cvt(_put_legal_T_39)
node _put_legal_T_41 = and(_put_legal_T_40, asSInt(UInt<33>(0h9a110000)))
node _put_legal_T_42 = asSInt(_put_legal_T_41)
node _put_legal_T_43 = eq(_put_legal_T_42, asSInt(UInt<1>(0h0)))
node _put_legal_T_44 = xor(req.addr, UInt<29>(0h10000000))
node _put_legal_T_45 = cvt(_put_legal_T_44)
node _put_legal_T_46 = and(_put_legal_T_45, asSInt(UInt<33>(0h9a113000)))
node _put_legal_T_47 = asSInt(_put_legal_T_46)
node _put_legal_T_48 = eq(_put_legal_T_47, asSInt(UInt<1>(0h0)))
node _put_legal_T_49 = xor(req.addr, UInt<32>(0h80000000))
node _put_legal_T_50 = cvt(_put_legal_T_49)
node _put_legal_T_51 = and(_put_legal_T_50, asSInt(UInt<33>(0h90000000)))
node _put_legal_T_52 = asSInt(_put_legal_T_51)
node _put_legal_T_53 = eq(_put_legal_T_52, asSInt(UInt<1>(0h0)))
node _put_legal_T_54 = or(_put_legal_T_18, _put_legal_T_23)
node _put_legal_T_55 = or(_put_legal_T_54, _put_legal_T_28)
node _put_legal_T_56 = or(_put_legal_T_55, _put_legal_T_33)
node _put_legal_T_57 = or(_put_legal_T_56, _put_legal_T_38)
node _put_legal_T_58 = or(_put_legal_T_57, _put_legal_T_43)
node _put_legal_T_59 = or(_put_legal_T_58, _put_legal_T_48)
node _put_legal_T_60 = or(_put_legal_T_59, _put_legal_T_53)
node _put_legal_T_61 = and(_put_legal_T_13, _put_legal_T_60)
node _put_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0))
node _put_legal_T_63 = xor(req.addr, UInt<17>(0h10000))
node _put_legal_T_64 = cvt(_put_legal_T_63)
node _put_legal_T_65 = and(_put_legal_T_64, asSInt(UInt<33>(0h9a110000)))
node _put_legal_T_66 = asSInt(_put_legal_T_65)
node _put_legal_T_67 = eq(_put_legal_T_66, asSInt(UInt<1>(0h0)))
node _put_legal_T_68 = and(_put_legal_T_62, _put_legal_T_67)
node _put_legal_T_69 = or(UInt<1>(0h0), _put_legal_T_9)
node _put_legal_T_70 = or(_put_legal_T_69, _put_legal_T_61)
node put_legal = or(_put_legal_T_70, _put_legal_T_68)
wire put : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect put.opcode, UInt<1>(0h0)
connect put.param, UInt<1>(0h0)
connect put.size, req.uop.mem_size
connect put.source, UInt<2>(0h3)
connect put.address, req.addr
node _put_a_mask_sizeOH_T = or(req.uop.mem_size, UInt<3>(0h0))
node put_a_mask_sizeOH_shiftAmount = bits(_put_a_mask_sizeOH_T, 1, 0)
node _put_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), put_a_mask_sizeOH_shiftAmount)
node _put_a_mask_sizeOH_T_2 = bits(_put_a_mask_sizeOH_T_1, 2, 0)
node put_a_mask_sizeOH = or(_put_a_mask_sizeOH_T_2, UInt<1>(0h1))
node put_a_mask_sub_sub_sub_0_1 = geq(req.uop.mem_size, UInt<2>(0h3))
node put_a_mask_sub_sub_size = bits(put_a_mask_sizeOH, 2, 2)
node put_a_mask_sub_sub_bit = bits(req.addr, 2, 2)
node put_a_mask_sub_sub_nbit = eq(put_a_mask_sub_sub_bit, UInt<1>(0h0))
node put_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_nbit)
node _put_a_mask_sub_sub_acc_T = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_0_2)
node put_a_mask_sub_sub_0_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T)
node put_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_bit)
node _put_a_mask_sub_sub_acc_T_1 = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_1_2)
node put_a_mask_sub_sub_1_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T_1)
node put_a_mask_sub_size = bits(put_a_mask_sizeOH, 1, 1)
node put_a_mask_sub_bit = bits(req.addr, 1, 1)
node put_a_mask_sub_nbit = eq(put_a_mask_sub_bit, UInt<1>(0h0))
node put_a_mask_sub_0_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_nbit)
node _put_a_mask_sub_acc_T = and(put_a_mask_sub_size, put_a_mask_sub_0_2)
node put_a_mask_sub_0_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T)
node put_a_mask_sub_1_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_bit)
node _put_a_mask_sub_acc_T_1 = and(put_a_mask_sub_size, put_a_mask_sub_1_2)
node put_a_mask_sub_1_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T_1)
node put_a_mask_sub_2_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_nbit)
node _put_a_mask_sub_acc_T_2 = and(put_a_mask_sub_size, put_a_mask_sub_2_2)
node put_a_mask_sub_2_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_2)
node put_a_mask_sub_3_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_bit)
node _put_a_mask_sub_acc_T_3 = and(put_a_mask_sub_size, put_a_mask_sub_3_2)
node put_a_mask_sub_3_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_3)
node put_a_mask_size = bits(put_a_mask_sizeOH, 0, 0)
node put_a_mask_bit = bits(req.addr, 0, 0)
node put_a_mask_nbit = eq(put_a_mask_bit, UInt<1>(0h0))
node put_a_mask_eq = and(put_a_mask_sub_0_2, put_a_mask_nbit)
node _put_a_mask_acc_T = and(put_a_mask_size, put_a_mask_eq)
node put_a_mask_acc = or(put_a_mask_sub_0_1, _put_a_mask_acc_T)
node put_a_mask_eq_1 = and(put_a_mask_sub_0_2, put_a_mask_bit)
node _put_a_mask_acc_T_1 = and(put_a_mask_size, put_a_mask_eq_1)
node put_a_mask_acc_1 = or(put_a_mask_sub_0_1, _put_a_mask_acc_T_1)
node put_a_mask_eq_2 = and(put_a_mask_sub_1_2, put_a_mask_nbit)
node _put_a_mask_acc_T_2 = and(put_a_mask_size, put_a_mask_eq_2)
node put_a_mask_acc_2 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_2)
node put_a_mask_eq_3 = and(put_a_mask_sub_1_2, put_a_mask_bit)
node _put_a_mask_acc_T_3 = and(put_a_mask_size, put_a_mask_eq_3)
node put_a_mask_acc_3 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_3)
node put_a_mask_eq_4 = and(put_a_mask_sub_2_2, put_a_mask_nbit)
node _put_a_mask_acc_T_4 = and(put_a_mask_size, put_a_mask_eq_4)
node put_a_mask_acc_4 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_4)
node put_a_mask_eq_5 = and(put_a_mask_sub_2_2, put_a_mask_bit)
node _put_a_mask_acc_T_5 = and(put_a_mask_size, put_a_mask_eq_5)
node put_a_mask_acc_5 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_5)
node put_a_mask_eq_6 = and(put_a_mask_sub_3_2, put_a_mask_nbit)
node _put_a_mask_acc_T_6 = and(put_a_mask_size, put_a_mask_eq_6)
node put_a_mask_acc_6 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_6)
node put_a_mask_eq_7 = and(put_a_mask_sub_3_2, put_a_mask_bit)
node _put_a_mask_acc_T_7 = and(put_a_mask_size, put_a_mask_eq_7)
node put_a_mask_acc_7 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_7)
node put_a_mask_lo_lo = cat(put_a_mask_acc_1, put_a_mask_acc)
node put_a_mask_lo_hi = cat(put_a_mask_acc_3, put_a_mask_acc_2)
node put_a_mask_lo = cat(put_a_mask_lo_hi, put_a_mask_lo_lo)
node put_a_mask_hi_lo = cat(put_a_mask_acc_5, put_a_mask_acc_4)
node put_a_mask_hi_hi = cat(put_a_mask_acc_7, put_a_mask_acc_6)
node put_a_mask_hi = cat(put_a_mask_hi_hi, put_a_mask_hi_lo)
node _put_a_mask_T = cat(put_a_mask_hi, put_a_mask_lo)
connect put.mask, _put_a_mask_T
connect put.data, req.data
connect put.corrupt, UInt<1>(0h0)
wire _atomics_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect _atomics_WIRE.corrupt, UInt<1>(0h0)
connect _atomics_WIRE.data, UInt<64>(0h0)
connect _atomics_WIRE.mask, UInt<8>(0h0)
connect _atomics_WIRE.address, UInt<32>(0h0)
connect _atomics_WIRE.source, UInt<2>(0h0)
connect _atomics_WIRE.size, UInt<4>(0h0)
connect _atomics_WIRE.param, UInt<3>(0h0)
connect _atomics_WIRE.opcode, UInt<3>(0h0)
node _atomics_legal_T = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_1 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_2 = and(_atomics_legal_T, _atomics_legal_T_1)
node _atomics_legal_T_3 = or(UInt<1>(0h0), _atomics_legal_T_2)
node _atomics_legal_T_4 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_5 = cvt(_atomics_legal_T_4)
node _atomics_legal_T_6 = and(_atomics_legal_T_5, asSInt(UInt<33>(0h98110000)))
node _atomics_legal_T_7 = asSInt(_atomics_legal_T_6)
node _atomics_legal_T_8 = eq(_atomics_legal_T_7, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_9 = xor(req.addr, UInt<21>(0h100000))
node _atomics_legal_T_10 = cvt(_atomics_legal_T_9)
node _atomics_legal_T_11 = and(_atomics_legal_T_10, asSInt(UInt<33>(0h9a101000)))
node _atomics_legal_T_12 = asSInt(_atomics_legal_T_11)
node _atomics_legal_T_13 = eq(_atomics_legal_T_12, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_14 = xor(req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_15 = cvt(_atomics_legal_T_14)
node _atomics_legal_T_16 = and(_atomics_legal_T_15, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_17 = asSInt(_atomics_legal_T_16)
node _atomics_legal_T_18 = eq(_atomics_legal_T_17, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_19 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_20 = cvt(_atomics_legal_T_19)
node _atomics_legal_T_21 = and(_atomics_legal_T_20, asSInt(UInt<33>(0h98000000)))
node _atomics_legal_T_22 = asSInt(_atomics_legal_T_21)
node _atomics_legal_T_23 = eq(_atomics_legal_T_22, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_24 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_25 = cvt(_atomics_legal_T_24)
node _atomics_legal_T_26 = and(_atomics_legal_T_25, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_27 = asSInt(_atomics_legal_T_26)
node _atomics_legal_T_28 = eq(_atomics_legal_T_27, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_29 = xor(req.addr, UInt<29>(0h10000000))
node _atomics_legal_T_30 = cvt(_atomics_legal_T_29)
node _atomics_legal_T_31 = and(_atomics_legal_T_30, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_32 = asSInt(_atomics_legal_T_31)
node _atomics_legal_T_33 = eq(_atomics_legal_T_32, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_34 = xor(req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_35 = cvt(_atomics_legal_T_34)
node _atomics_legal_T_36 = and(_atomics_legal_T_35, asSInt(UInt<33>(0h90000000)))
node _atomics_legal_T_37 = asSInt(_atomics_legal_T_36)
node _atomics_legal_T_38 = eq(_atomics_legal_T_37, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_39 = or(_atomics_legal_T_8, _atomics_legal_T_13)
node _atomics_legal_T_40 = or(_atomics_legal_T_39, _atomics_legal_T_18)
node _atomics_legal_T_41 = or(_atomics_legal_T_40, _atomics_legal_T_23)
node _atomics_legal_T_42 = or(_atomics_legal_T_41, _atomics_legal_T_28)
node _atomics_legal_T_43 = or(_atomics_legal_T_42, _atomics_legal_T_33)
node _atomics_legal_T_44 = or(_atomics_legal_T_43, _atomics_legal_T_38)
node _atomics_legal_T_45 = and(_atomics_legal_T_3, _atomics_legal_T_44)
node _atomics_legal_T_46 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_47 = xor(req.addr, UInt<17>(0h10000))
node _atomics_legal_T_48 = cvt(_atomics_legal_T_47)
node _atomics_legal_T_49 = and(_atomics_legal_T_48, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_50 = asSInt(_atomics_legal_T_49)
node _atomics_legal_T_51 = eq(_atomics_legal_T_50, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_52 = and(_atomics_legal_T_46, _atomics_legal_T_51)
node _atomics_legal_T_53 = or(UInt<1>(0h0), _atomics_legal_T_45)
node atomics_legal = or(_atomics_legal_T_53, _atomics_legal_T_52)
wire atomics_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a.opcode, UInt<2>(0h3)
connect atomics_a.param, UInt<3>(0h3)
connect atomics_a.size, req.uop.mem_size
connect atomics_a.source, UInt<2>(0h3)
connect atomics_a.address, req.addr
node _atomics_a_mask_sizeOH_T = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount = bits(_atomics_a_mask_sizeOH_T, 1, 0)
node _atomics_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount)
node _atomics_a_mask_sizeOH_T_2 = bits(_atomics_a_mask_sizeOH_T_1, 2, 0)
node atomics_a_mask_sizeOH = or(_atomics_a_mask_sizeOH_T_2, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size = bits(atomics_a_mask_sizeOH, 2, 2)
node atomics_a_mask_sub_sub_bit = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit = eq(atomics_a_mask_sub_sub_bit, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit)
node _atomics_a_mask_sub_sub_acc_T = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_0_2)
node atomics_a_mask_sub_sub_0_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T)
node atomics_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit)
node _atomics_a_mask_sub_sub_acc_T_1 = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_1_2)
node atomics_a_mask_sub_sub_1_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T_1)
node atomics_a_mask_sub_size = bits(atomics_a_mask_sizeOH, 1, 1)
node atomics_a_mask_sub_bit = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit = eq(atomics_a_mask_sub_bit, UInt<1>(0h0))
node atomics_a_mask_sub_0_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_nbit)
node _atomics_a_mask_sub_acc_T = and(atomics_a_mask_sub_size, atomics_a_mask_sub_0_2)
node atomics_a_mask_sub_0_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T)
node atomics_a_mask_sub_1_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_bit)
node _atomics_a_mask_sub_acc_T_1 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_1_2)
node atomics_a_mask_sub_1_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T_1)
node atomics_a_mask_sub_2_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_nbit)
node _atomics_a_mask_sub_acc_T_2 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_2_2)
node atomics_a_mask_sub_2_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_2)
node atomics_a_mask_sub_3_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_bit)
node _atomics_a_mask_sub_acc_T_3 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_3_2)
node atomics_a_mask_sub_3_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_3)
node atomics_a_mask_size = bits(atomics_a_mask_sizeOH, 0, 0)
node atomics_a_mask_bit = bits(req.addr, 0, 0)
node atomics_a_mask_nbit = eq(atomics_a_mask_bit, UInt<1>(0h0))
node atomics_a_mask_eq = and(atomics_a_mask_sub_0_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T = and(atomics_a_mask_size, atomics_a_mask_eq)
node atomics_a_mask_acc = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T)
node atomics_a_mask_eq_1 = and(atomics_a_mask_sub_0_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_1 = and(atomics_a_mask_size, atomics_a_mask_eq_1)
node atomics_a_mask_acc_1 = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T_1)
node atomics_a_mask_eq_2 = and(atomics_a_mask_sub_1_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T_2 = and(atomics_a_mask_size, atomics_a_mask_eq_2)
node atomics_a_mask_acc_2 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_2)
node atomics_a_mask_eq_3 = and(atomics_a_mask_sub_1_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_3 = and(atomics_a_mask_size, atomics_a_mask_eq_3)
node atomics_a_mask_acc_3 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_3)
node atomics_a_mask_eq_4 = and(atomics_a_mask_sub_2_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T_4 = and(atomics_a_mask_size, atomics_a_mask_eq_4)
node atomics_a_mask_acc_4 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_4)
node atomics_a_mask_eq_5 = and(atomics_a_mask_sub_2_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_5 = and(atomics_a_mask_size, atomics_a_mask_eq_5)
node atomics_a_mask_acc_5 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_5)
node atomics_a_mask_eq_6 = and(atomics_a_mask_sub_3_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T_6 = and(atomics_a_mask_size, atomics_a_mask_eq_6)
node atomics_a_mask_acc_6 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_6)
node atomics_a_mask_eq_7 = and(atomics_a_mask_sub_3_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_7 = and(atomics_a_mask_size, atomics_a_mask_eq_7)
node atomics_a_mask_acc_7 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_7)
node atomics_a_mask_lo_lo = cat(atomics_a_mask_acc_1, atomics_a_mask_acc)
node atomics_a_mask_lo_hi = cat(atomics_a_mask_acc_3, atomics_a_mask_acc_2)
node atomics_a_mask_lo = cat(atomics_a_mask_lo_hi, atomics_a_mask_lo_lo)
node atomics_a_mask_hi_lo = cat(atomics_a_mask_acc_5, atomics_a_mask_acc_4)
node atomics_a_mask_hi_hi = cat(atomics_a_mask_acc_7, atomics_a_mask_acc_6)
node atomics_a_mask_hi = cat(atomics_a_mask_hi_hi, atomics_a_mask_hi_lo)
node _atomics_a_mask_T = cat(atomics_a_mask_hi, atomics_a_mask_lo)
connect atomics_a.mask, _atomics_a_mask_T
connect atomics_a.data, req.data
connect atomics_a.corrupt, UInt<1>(0h0)
node _atomics_legal_T_54 = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_55 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_56 = and(_atomics_legal_T_54, _atomics_legal_T_55)
node _atomics_legal_T_57 = or(UInt<1>(0h0), _atomics_legal_T_56)
node _atomics_legal_T_58 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_59 = cvt(_atomics_legal_T_58)
node _atomics_legal_T_60 = and(_atomics_legal_T_59, asSInt(UInt<33>(0h98110000)))
node _atomics_legal_T_61 = asSInt(_atomics_legal_T_60)
node _atomics_legal_T_62 = eq(_atomics_legal_T_61, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_63 = xor(req.addr, UInt<21>(0h100000))
node _atomics_legal_T_64 = cvt(_atomics_legal_T_63)
node _atomics_legal_T_65 = and(_atomics_legal_T_64, asSInt(UInt<33>(0h9a101000)))
node _atomics_legal_T_66 = asSInt(_atomics_legal_T_65)
node _atomics_legal_T_67 = eq(_atomics_legal_T_66, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_68 = xor(req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_69 = cvt(_atomics_legal_T_68)
node _atomics_legal_T_70 = and(_atomics_legal_T_69, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_71 = asSInt(_atomics_legal_T_70)
node _atomics_legal_T_72 = eq(_atomics_legal_T_71, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_73 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_74 = cvt(_atomics_legal_T_73)
node _atomics_legal_T_75 = and(_atomics_legal_T_74, asSInt(UInt<33>(0h98000000)))
node _atomics_legal_T_76 = asSInt(_atomics_legal_T_75)
node _atomics_legal_T_77 = eq(_atomics_legal_T_76, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_78 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_79 = cvt(_atomics_legal_T_78)
node _atomics_legal_T_80 = and(_atomics_legal_T_79, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_81 = asSInt(_atomics_legal_T_80)
node _atomics_legal_T_82 = eq(_atomics_legal_T_81, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_83 = xor(req.addr, UInt<29>(0h10000000))
node _atomics_legal_T_84 = cvt(_atomics_legal_T_83)
node _atomics_legal_T_85 = and(_atomics_legal_T_84, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_86 = asSInt(_atomics_legal_T_85)
node _atomics_legal_T_87 = eq(_atomics_legal_T_86, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_88 = xor(req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_89 = cvt(_atomics_legal_T_88)
node _atomics_legal_T_90 = and(_atomics_legal_T_89, asSInt(UInt<33>(0h90000000)))
node _atomics_legal_T_91 = asSInt(_atomics_legal_T_90)
node _atomics_legal_T_92 = eq(_atomics_legal_T_91, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_93 = or(_atomics_legal_T_62, _atomics_legal_T_67)
node _atomics_legal_T_94 = or(_atomics_legal_T_93, _atomics_legal_T_72)
node _atomics_legal_T_95 = or(_atomics_legal_T_94, _atomics_legal_T_77)
node _atomics_legal_T_96 = or(_atomics_legal_T_95, _atomics_legal_T_82)
node _atomics_legal_T_97 = or(_atomics_legal_T_96, _atomics_legal_T_87)
node _atomics_legal_T_98 = or(_atomics_legal_T_97, _atomics_legal_T_92)
node _atomics_legal_T_99 = and(_atomics_legal_T_57, _atomics_legal_T_98)
node _atomics_legal_T_100 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_101 = xor(req.addr, UInt<17>(0h10000))
node _atomics_legal_T_102 = cvt(_atomics_legal_T_101)
node _atomics_legal_T_103 = and(_atomics_legal_T_102, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_104 = asSInt(_atomics_legal_T_103)
node _atomics_legal_T_105 = eq(_atomics_legal_T_104, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_106 = and(_atomics_legal_T_100, _atomics_legal_T_105)
node _atomics_legal_T_107 = or(UInt<1>(0h0), _atomics_legal_T_99)
node atomics_legal_1 = or(_atomics_legal_T_107, _atomics_legal_T_106)
wire atomics_a_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_1.opcode, UInt<2>(0h3)
connect atomics_a_1.param, UInt<3>(0h0)
connect atomics_a_1.size, req.uop.mem_size
connect atomics_a_1.source, UInt<2>(0h3)
connect atomics_a_1.address, req.addr
node _atomics_a_mask_sizeOH_T_3 = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_1 = bits(_atomics_a_mask_sizeOH_T_3, 1, 0)
node _atomics_a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_1)
node _atomics_a_mask_sizeOH_T_5 = bits(_atomics_a_mask_sizeOH_T_4, 2, 0)
node atomics_a_mask_sizeOH_1 = or(_atomics_a_mask_sizeOH_T_5, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_1 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 2, 2)
node atomics_a_mask_sub_sub_bit_1 = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_1 = eq(atomics_a_mask_sub_sub_bit_1, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_1)
node _atomics_a_mask_sub_sub_acc_T_2 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_0_2_1)
node atomics_a_mask_sub_sub_0_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_2)
node atomics_a_mask_sub_sub_1_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_1)
node _atomics_a_mask_sub_sub_acc_T_3 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_1_2_1)
node atomics_a_mask_sub_sub_1_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_3)
node atomics_a_mask_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 1, 1)
node atomics_a_mask_sub_bit_1 = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit_1 = eq(atomics_a_mask_sub_bit_1, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_nbit_1)
node _atomics_a_mask_sub_acc_T_4 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_0_2_1)
node atomics_a_mask_sub_0_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_4)
node atomics_a_mask_sub_1_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_bit_1)
node _atomics_a_mask_sub_acc_T_5 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_1_2_1)
node atomics_a_mask_sub_1_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_5)
node atomics_a_mask_sub_2_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_nbit_1)
node _atomics_a_mask_sub_acc_T_6 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_2_2_1)
node atomics_a_mask_sub_2_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_6)
node atomics_a_mask_sub_3_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_bit_1)
node _atomics_a_mask_sub_acc_T_7 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_3_2_1)
node atomics_a_mask_sub_3_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_7)
node atomics_a_mask_size_1 = bits(atomics_a_mask_sizeOH_1, 0, 0)
node atomics_a_mask_bit_1 = bits(req.addr, 0, 0)
node atomics_a_mask_nbit_1 = eq(atomics_a_mask_bit_1, UInt<1>(0h0))
node atomics_a_mask_eq_8 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_8 = and(atomics_a_mask_size_1, atomics_a_mask_eq_8)
node atomics_a_mask_acc_8 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_8)
node atomics_a_mask_eq_9 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_9 = and(atomics_a_mask_size_1, atomics_a_mask_eq_9)
node atomics_a_mask_acc_9 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_9)
node atomics_a_mask_eq_10 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_10 = and(atomics_a_mask_size_1, atomics_a_mask_eq_10)
node atomics_a_mask_acc_10 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_10)
node atomics_a_mask_eq_11 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_11 = and(atomics_a_mask_size_1, atomics_a_mask_eq_11)
node atomics_a_mask_acc_11 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_11)
node atomics_a_mask_eq_12 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_12 = and(atomics_a_mask_size_1, atomics_a_mask_eq_12)
node atomics_a_mask_acc_12 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_12)
node atomics_a_mask_eq_13 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_13 = and(atomics_a_mask_size_1, atomics_a_mask_eq_13)
node atomics_a_mask_acc_13 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_13)
node atomics_a_mask_eq_14 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_14 = and(atomics_a_mask_size_1, atomics_a_mask_eq_14)
node atomics_a_mask_acc_14 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_14)
node atomics_a_mask_eq_15 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_15 = and(atomics_a_mask_size_1, atomics_a_mask_eq_15)
node atomics_a_mask_acc_15 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_15)
node atomics_a_mask_lo_lo_1 = cat(atomics_a_mask_acc_9, atomics_a_mask_acc_8)
node atomics_a_mask_lo_hi_1 = cat(atomics_a_mask_acc_11, atomics_a_mask_acc_10)
node atomics_a_mask_lo_1 = cat(atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1)
node atomics_a_mask_hi_lo_1 = cat(atomics_a_mask_acc_13, atomics_a_mask_acc_12)
node atomics_a_mask_hi_hi_1 = cat(atomics_a_mask_acc_15, atomics_a_mask_acc_14)
node atomics_a_mask_hi_1 = cat(atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1)
node _atomics_a_mask_T_1 = cat(atomics_a_mask_hi_1, atomics_a_mask_lo_1)
connect atomics_a_1.mask, _atomics_a_mask_T_1
connect atomics_a_1.data, req.data
connect atomics_a_1.corrupt, UInt<1>(0h0)
node _atomics_legal_T_108 = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_109 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_110 = and(_atomics_legal_T_108, _atomics_legal_T_109)
node _atomics_legal_T_111 = or(UInt<1>(0h0), _atomics_legal_T_110)
node _atomics_legal_T_112 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_113 = cvt(_atomics_legal_T_112)
node _atomics_legal_T_114 = and(_atomics_legal_T_113, asSInt(UInt<33>(0h98110000)))
node _atomics_legal_T_115 = asSInt(_atomics_legal_T_114)
node _atomics_legal_T_116 = eq(_atomics_legal_T_115, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_117 = xor(req.addr, UInt<21>(0h100000))
node _atomics_legal_T_118 = cvt(_atomics_legal_T_117)
node _atomics_legal_T_119 = and(_atomics_legal_T_118, asSInt(UInt<33>(0h9a101000)))
node _atomics_legal_T_120 = asSInt(_atomics_legal_T_119)
node _atomics_legal_T_121 = eq(_atomics_legal_T_120, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_122 = xor(req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_123 = cvt(_atomics_legal_T_122)
node _atomics_legal_T_124 = and(_atomics_legal_T_123, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_125 = asSInt(_atomics_legal_T_124)
node _atomics_legal_T_126 = eq(_atomics_legal_T_125, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_127 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_128 = cvt(_atomics_legal_T_127)
node _atomics_legal_T_129 = and(_atomics_legal_T_128, asSInt(UInt<33>(0h98000000)))
node _atomics_legal_T_130 = asSInt(_atomics_legal_T_129)
node _atomics_legal_T_131 = eq(_atomics_legal_T_130, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_132 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_133 = cvt(_atomics_legal_T_132)
node _atomics_legal_T_134 = and(_atomics_legal_T_133, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_135 = asSInt(_atomics_legal_T_134)
node _atomics_legal_T_136 = eq(_atomics_legal_T_135, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_137 = xor(req.addr, UInt<29>(0h10000000))
node _atomics_legal_T_138 = cvt(_atomics_legal_T_137)
node _atomics_legal_T_139 = and(_atomics_legal_T_138, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_140 = asSInt(_atomics_legal_T_139)
node _atomics_legal_T_141 = eq(_atomics_legal_T_140, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_142 = xor(req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_143 = cvt(_atomics_legal_T_142)
node _atomics_legal_T_144 = and(_atomics_legal_T_143, asSInt(UInt<33>(0h90000000)))
node _atomics_legal_T_145 = asSInt(_atomics_legal_T_144)
node _atomics_legal_T_146 = eq(_atomics_legal_T_145, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_147 = or(_atomics_legal_T_116, _atomics_legal_T_121)
node _atomics_legal_T_148 = or(_atomics_legal_T_147, _atomics_legal_T_126)
node _atomics_legal_T_149 = or(_atomics_legal_T_148, _atomics_legal_T_131)
node _atomics_legal_T_150 = or(_atomics_legal_T_149, _atomics_legal_T_136)
node _atomics_legal_T_151 = or(_atomics_legal_T_150, _atomics_legal_T_141)
node _atomics_legal_T_152 = or(_atomics_legal_T_151, _atomics_legal_T_146)
node _atomics_legal_T_153 = and(_atomics_legal_T_111, _atomics_legal_T_152)
node _atomics_legal_T_154 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_155 = xor(req.addr, UInt<17>(0h10000))
node _atomics_legal_T_156 = cvt(_atomics_legal_T_155)
node _atomics_legal_T_157 = and(_atomics_legal_T_156, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_158 = asSInt(_atomics_legal_T_157)
node _atomics_legal_T_159 = eq(_atomics_legal_T_158, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_160 = and(_atomics_legal_T_154, _atomics_legal_T_159)
node _atomics_legal_T_161 = or(UInt<1>(0h0), _atomics_legal_T_153)
node atomics_legal_2 = or(_atomics_legal_T_161, _atomics_legal_T_160)
wire atomics_a_2 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_2.opcode, UInt<2>(0h3)
connect atomics_a_2.param, UInt<3>(0h1)
connect atomics_a_2.size, req.uop.mem_size
connect atomics_a_2.source, UInt<2>(0h3)
connect atomics_a_2.address, req.addr
node _atomics_a_mask_sizeOH_T_6 = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_2 = bits(_atomics_a_mask_sizeOH_T_6, 1, 0)
node _atomics_a_mask_sizeOH_T_7 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_2)
node _atomics_a_mask_sizeOH_T_8 = bits(_atomics_a_mask_sizeOH_T_7, 2, 0)
node atomics_a_mask_sizeOH_2 = or(_atomics_a_mask_sizeOH_T_8, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_2 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 2, 2)
node atomics_a_mask_sub_sub_bit_2 = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_2 = eq(atomics_a_mask_sub_sub_bit_2, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_2)
node _atomics_a_mask_sub_sub_acc_T_4 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_0_2_2)
node atomics_a_mask_sub_sub_0_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_4)
node atomics_a_mask_sub_sub_1_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_2)
node _atomics_a_mask_sub_sub_acc_T_5 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_1_2_2)
node atomics_a_mask_sub_sub_1_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_5)
node atomics_a_mask_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 1, 1)
node atomics_a_mask_sub_bit_2 = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit_2 = eq(atomics_a_mask_sub_bit_2, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_nbit_2)
node _atomics_a_mask_sub_acc_T_8 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_0_2_2)
node atomics_a_mask_sub_0_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_8)
node atomics_a_mask_sub_1_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_bit_2)
node _atomics_a_mask_sub_acc_T_9 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_1_2_2)
node atomics_a_mask_sub_1_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_9)
node atomics_a_mask_sub_2_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_nbit_2)
node _atomics_a_mask_sub_acc_T_10 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_2_2_2)
node atomics_a_mask_sub_2_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_10)
node atomics_a_mask_sub_3_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_bit_2)
node _atomics_a_mask_sub_acc_T_11 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_3_2_2)
node atomics_a_mask_sub_3_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_11)
node atomics_a_mask_size_2 = bits(atomics_a_mask_sizeOH_2, 0, 0)
node atomics_a_mask_bit_2 = bits(req.addr, 0, 0)
node atomics_a_mask_nbit_2 = eq(atomics_a_mask_bit_2, UInt<1>(0h0))
node atomics_a_mask_eq_16 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_16 = and(atomics_a_mask_size_2, atomics_a_mask_eq_16)
node atomics_a_mask_acc_16 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_16)
node atomics_a_mask_eq_17 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_17 = and(atomics_a_mask_size_2, atomics_a_mask_eq_17)
node atomics_a_mask_acc_17 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_17)
node atomics_a_mask_eq_18 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_18 = and(atomics_a_mask_size_2, atomics_a_mask_eq_18)
node atomics_a_mask_acc_18 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_18)
node atomics_a_mask_eq_19 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_19 = and(atomics_a_mask_size_2, atomics_a_mask_eq_19)
node atomics_a_mask_acc_19 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_19)
node atomics_a_mask_eq_20 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_20 = and(atomics_a_mask_size_2, atomics_a_mask_eq_20)
node atomics_a_mask_acc_20 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_20)
node atomics_a_mask_eq_21 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_21 = and(atomics_a_mask_size_2, atomics_a_mask_eq_21)
node atomics_a_mask_acc_21 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_21)
node atomics_a_mask_eq_22 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_22 = and(atomics_a_mask_size_2, atomics_a_mask_eq_22)
node atomics_a_mask_acc_22 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_22)
node atomics_a_mask_eq_23 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_23 = and(atomics_a_mask_size_2, atomics_a_mask_eq_23)
node atomics_a_mask_acc_23 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_23)
node atomics_a_mask_lo_lo_2 = cat(atomics_a_mask_acc_17, atomics_a_mask_acc_16)
node atomics_a_mask_lo_hi_2 = cat(atomics_a_mask_acc_19, atomics_a_mask_acc_18)
node atomics_a_mask_lo_2 = cat(atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2)
node atomics_a_mask_hi_lo_2 = cat(atomics_a_mask_acc_21, atomics_a_mask_acc_20)
node atomics_a_mask_hi_hi_2 = cat(atomics_a_mask_acc_23, atomics_a_mask_acc_22)
node atomics_a_mask_hi_2 = cat(atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2)
node _atomics_a_mask_T_2 = cat(atomics_a_mask_hi_2, atomics_a_mask_lo_2)
connect atomics_a_2.mask, _atomics_a_mask_T_2
connect atomics_a_2.data, req.data
connect atomics_a_2.corrupt, UInt<1>(0h0)
node _atomics_legal_T_162 = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_163 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_164 = and(_atomics_legal_T_162, _atomics_legal_T_163)
node _atomics_legal_T_165 = or(UInt<1>(0h0), _atomics_legal_T_164)
node _atomics_legal_T_166 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_167 = cvt(_atomics_legal_T_166)
node _atomics_legal_T_168 = and(_atomics_legal_T_167, asSInt(UInt<33>(0h98110000)))
node _atomics_legal_T_169 = asSInt(_atomics_legal_T_168)
node _atomics_legal_T_170 = eq(_atomics_legal_T_169, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_171 = xor(req.addr, UInt<21>(0h100000))
node _atomics_legal_T_172 = cvt(_atomics_legal_T_171)
node _atomics_legal_T_173 = and(_atomics_legal_T_172, asSInt(UInt<33>(0h9a101000)))
node _atomics_legal_T_174 = asSInt(_atomics_legal_T_173)
node _atomics_legal_T_175 = eq(_atomics_legal_T_174, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_176 = xor(req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_177 = cvt(_atomics_legal_T_176)
node _atomics_legal_T_178 = and(_atomics_legal_T_177, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_179 = asSInt(_atomics_legal_T_178)
node _atomics_legal_T_180 = eq(_atomics_legal_T_179, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_181 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_182 = cvt(_atomics_legal_T_181)
node _atomics_legal_T_183 = and(_atomics_legal_T_182, asSInt(UInt<33>(0h98000000)))
node _atomics_legal_T_184 = asSInt(_atomics_legal_T_183)
node _atomics_legal_T_185 = eq(_atomics_legal_T_184, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_186 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_187 = cvt(_atomics_legal_T_186)
node _atomics_legal_T_188 = and(_atomics_legal_T_187, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_189 = asSInt(_atomics_legal_T_188)
node _atomics_legal_T_190 = eq(_atomics_legal_T_189, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_191 = xor(req.addr, UInt<29>(0h10000000))
node _atomics_legal_T_192 = cvt(_atomics_legal_T_191)
node _atomics_legal_T_193 = and(_atomics_legal_T_192, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_194 = asSInt(_atomics_legal_T_193)
node _atomics_legal_T_195 = eq(_atomics_legal_T_194, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_196 = xor(req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_197 = cvt(_atomics_legal_T_196)
node _atomics_legal_T_198 = and(_atomics_legal_T_197, asSInt(UInt<33>(0h90000000)))
node _atomics_legal_T_199 = asSInt(_atomics_legal_T_198)
node _atomics_legal_T_200 = eq(_atomics_legal_T_199, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_201 = or(_atomics_legal_T_170, _atomics_legal_T_175)
node _atomics_legal_T_202 = or(_atomics_legal_T_201, _atomics_legal_T_180)
node _atomics_legal_T_203 = or(_atomics_legal_T_202, _atomics_legal_T_185)
node _atomics_legal_T_204 = or(_atomics_legal_T_203, _atomics_legal_T_190)
node _atomics_legal_T_205 = or(_atomics_legal_T_204, _atomics_legal_T_195)
node _atomics_legal_T_206 = or(_atomics_legal_T_205, _atomics_legal_T_200)
node _atomics_legal_T_207 = and(_atomics_legal_T_165, _atomics_legal_T_206)
node _atomics_legal_T_208 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_209 = xor(req.addr, UInt<17>(0h10000))
node _atomics_legal_T_210 = cvt(_atomics_legal_T_209)
node _atomics_legal_T_211 = and(_atomics_legal_T_210, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_212 = asSInt(_atomics_legal_T_211)
node _atomics_legal_T_213 = eq(_atomics_legal_T_212, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_214 = and(_atomics_legal_T_208, _atomics_legal_T_213)
node _atomics_legal_T_215 = or(UInt<1>(0h0), _atomics_legal_T_207)
node atomics_legal_3 = or(_atomics_legal_T_215, _atomics_legal_T_214)
wire atomics_a_3 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_3.opcode, UInt<2>(0h3)
connect atomics_a_3.param, UInt<3>(0h2)
connect atomics_a_3.size, req.uop.mem_size
connect atomics_a_3.source, UInt<2>(0h3)
connect atomics_a_3.address, req.addr
node _atomics_a_mask_sizeOH_T_9 = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_3 = bits(_atomics_a_mask_sizeOH_T_9, 1, 0)
node _atomics_a_mask_sizeOH_T_10 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_3)
node _atomics_a_mask_sizeOH_T_11 = bits(_atomics_a_mask_sizeOH_T_10, 2, 0)
node atomics_a_mask_sizeOH_3 = or(_atomics_a_mask_sizeOH_T_11, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_3 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 2, 2)
node atomics_a_mask_sub_sub_bit_3 = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_3 = eq(atomics_a_mask_sub_sub_bit_3, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_3)
node _atomics_a_mask_sub_sub_acc_T_6 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_0_2_3)
node atomics_a_mask_sub_sub_0_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_6)
node atomics_a_mask_sub_sub_1_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_3)
node _atomics_a_mask_sub_sub_acc_T_7 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_1_2_3)
node atomics_a_mask_sub_sub_1_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_7)
node atomics_a_mask_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 1, 1)
node atomics_a_mask_sub_bit_3 = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit_3 = eq(atomics_a_mask_sub_bit_3, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_nbit_3)
node _atomics_a_mask_sub_acc_T_12 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_0_2_3)
node atomics_a_mask_sub_0_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_12)
node atomics_a_mask_sub_1_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_bit_3)
node _atomics_a_mask_sub_acc_T_13 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_1_2_3)
node atomics_a_mask_sub_1_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_13)
node atomics_a_mask_sub_2_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_nbit_3)
node _atomics_a_mask_sub_acc_T_14 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_2_2_3)
node atomics_a_mask_sub_2_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_14)
node atomics_a_mask_sub_3_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_bit_3)
node _atomics_a_mask_sub_acc_T_15 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_3_2_3)
node atomics_a_mask_sub_3_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_15)
node atomics_a_mask_size_3 = bits(atomics_a_mask_sizeOH_3, 0, 0)
node atomics_a_mask_bit_3 = bits(req.addr, 0, 0)
node atomics_a_mask_nbit_3 = eq(atomics_a_mask_bit_3, UInt<1>(0h0))
node atomics_a_mask_eq_24 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_24 = and(atomics_a_mask_size_3, atomics_a_mask_eq_24)
node atomics_a_mask_acc_24 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_24)
node atomics_a_mask_eq_25 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_25 = and(atomics_a_mask_size_3, atomics_a_mask_eq_25)
node atomics_a_mask_acc_25 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_25)
node atomics_a_mask_eq_26 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_26 = and(atomics_a_mask_size_3, atomics_a_mask_eq_26)
node atomics_a_mask_acc_26 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_26)
node atomics_a_mask_eq_27 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_27 = and(atomics_a_mask_size_3, atomics_a_mask_eq_27)
node atomics_a_mask_acc_27 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_27)
node atomics_a_mask_eq_28 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_28 = and(atomics_a_mask_size_3, atomics_a_mask_eq_28)
node atomics_a_mask_acc_28 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_28)
node atomics_a_mask_eq_29 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_29 = and(atomics_a_mask_size_3, atomics_a_mask_eq_29)
node atomics_a_mask_acc_29 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_29)
node atomics_a_mask_eq_30 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_30 = and(atomics_a_mask_size_3, atomics_a_mask_eq_30)
node atomics_a_mask_acc_30 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_30)
node atomics_a_mask_eq_31 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_31 = and(atomics_a_mask_size_3, atomics_a_mask_eq_31)
node atomics_a_mask_acc_31 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_31)
node atomics_a_mask_lo_lo_3 = cat(atomics_a_mask_acc_25, atomics_a_mask_acc_24)
node atomics_a_mask_lo_hi_3 = cat(atomics_a_mask_acc_27, atomics_a_mask_acc_26)
node atomics_a_mask_lo_3 = cat(atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3)
node atomics_a_mask_hi_lo_3 = cat(atomics_a_mask_acc_29, atomics_a_mask_acc_28)
node atomics_a_mask_hi_hi_3 = cat(atomics_a_mask_acc_31, atomics_a_mask_acc_30)
node atomics_a_mask_hi_3 = cat(atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3)
node _atomics_a_mask_T_3 = cat(atomics_a_mask_hi_3, atomics_a_mask_lo_3)
connect atomics_a_3.mask, _atomics_a_mask_T_3
connect atomics_a_3.data, req.data
connect atomics_a_3.corrupt, UInt<1>(0h0)
node _atomics_legal_T_216 = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_217 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_218 = and(_atomics_legal_T_216, _atomics_legal_T_217)
node _atomics_legal_T_219 = or(UInt<1>(0h0), _atomics_legal_T_218)
node _atomics_legal_T_220 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_221 = cvt(_atomics_legal_T_220)
node _atomics_legal_T_222 = and(_atomics_legal_T_221, asSInt(UInt<33>(0h98110000)))
node _atomics_legal_T_223 = asSInt(_atomics_legal_T_222)
node _atomics_legal_T_224 = eq(_atomics_legal_T_223, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_225 = xor(req.addr, UInt<21>(0h100000))
node _atomics_legal_T_226 = cvt(_atomics_legal_T_225)
node _atomics_legal_T_227 = and(_atomics_legal_T_226, asSInt(UInt<33>(0h9a101000)))
node _atomics_legal_T_228 = asSInt(_atomics_legal_T_227)
node _atomics_legal_T_229 = eq(_atomics_legal_T_228, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_230 = xor(req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_231 = cvt(_atomics_legal_T_230)
node _atomics_legal_T_232 = and(_atomics_legal_T_231, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_233 = asSInt(_atomics_legal_T_232)
node _atomics_legal_T_234 = eq(_atomics_legal_T_233, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_235 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_236 = cvt(_atomics_legal_T_235)
node _atomics_legal_T_237 = and(_atomics_legal_T_236, asSInt(UInt<33>(0h98000000)))
node _atomics_legal_T_238 = asSInt(_atomics_legal_T_237)
node _atomics_legal_T_239 = eq(_atomics_legal_T_238, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_240 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_241 = cvt(_atomics_legal_T_240)
node _atomics_legal_T_242 = and(_atomics_legal_T_241, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_243 = asSInt(_atomics_legal_T_242)
node _atomics_legal_T_244 = eq(_atomics_legal_T_243, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_245 = xor(req.addr, UInt<29>(0h10000000))
node _atomics_legal_T_246 = cvt(_atomics_legal_T_245)
node _atomics_legal_T_247 = and(_atomics_legal_T_246, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_248 = asSInt(_atomics_legal_T_247)
node _atomics_legal_T_249 = eq(_atomics_legal_T_248, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_250 = xor(req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_251 = cvt(_atomics_legal_T_250)
node _atomics_legal_T_252 = and(_atomics_legal_T_251, asSInt(UInt<33>(0h90000000)))
node _atomics_legal_T_253 = asSInt(_atomics_legal_T_252)
node _atomics_legal_T_254 = eq(_atomics_legal_T_253, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_255 = or(_atomics_legal_T_224, _atomics_legal_T_229)
node _atomics_legal_T_256 = or(_atomics_legal_T_255, _atomics_legal_T_234)
node _atomics_legal_T_257 = or(_atomics_legal_T_256, _atomics_legal_T_239)
node _atomics_legal_T_258 = or(_atomics_legal_T_257, _atomics_legal_T_244)
node _atomics_legal_T_259 = or(_atomics_legal_T_258, _atomics_legal_T_249)
node _atomics_legal_T_260 = or(_atomics_legal_T_259, _atomics_legal_T_254)
node _atomics_legal_T_261 = and(_atomics_legal_T_219, _atomics_legal_T_260)
node _atomics_legal_T_262 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_263 = xor(req.addr, UInt<17>(0h10000))
node _atomics_legal_T_264 = cvt(_atomics_legal_T_263)
node _atomics_legal_T_265 = and(_atomics_legal_T_264, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_266 = asSInt(_atomics_legal_T_265)
node _atomics_legal_T_267 = eq(_atomics_legal_T_266, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_268 = and(_atomics_legal_T_262, _atomics_legal_T_267)
node _atomics_legal_T_269 = or(UInt<1>(0h0), _atomics_legal_T_261)
node atomics_legal_4 = or(_atomics_legal_T_269, _atomics_legal_T_268)
wire atomics_a_4 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_4.opcode, UInt<2>(0h2)
connect atomics_a_4.param, UInt<3>(0h4)
connect atomics_a_4.size, req.uop.mem_size
connect atomics_a_4.source, UInt<2>(0h3)
connect atomics_a_4.address, req.addr
node _atomics_a_mask_sizeOH_T_12 = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_4 = bits(_atomics_a_mask_sizeOH_T_12, 1, 0)
node _atomics_a_mask_sizeOH_T_13 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_4)
node _atomics_a_mask_sizeOH_T_14 = bits(_atomics_a_mask_sizeOH_T_13, 2, 0)
node atomics_a_mask_sizeOH_4 = or(_atomics_a_mask_sizeOH_T_14, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_4 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 2, 2)
node atomics_a_mask_sub_sub_bit_4 = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_4 = eq(atomics_a_mask_sub_sub_bit_4, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_4)
node _atomics_a_mask_sub_sub_acc_T_8 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_0_2_4)
node atomics_a_mask_sub_sub_0_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_8)
node atomics_a_mask_sub_sub_1_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_4)
node _atomics_a_mask_sub_sub_acc_T_9 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_1_2_4)
node atomics_a_mask_sub_sub_1_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_9)
node atomics_a_mask_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 1, 1)
node atomics_a_mask_sub_bit_4 = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit_4 = eq(atomics_a_mask_sub_bit_4, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_nbit_4)
node _atomics_a_mask_sub_acc_T_16 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_0_2_4)
node atomics_a_mask_sub_0_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_16)
node atomics_a_mask_sub_1_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_bit_4)
node _atomics_a_mask_sub_acc_T_17 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_1_2_4)
node atomics_a_mask_sub_1_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_17)
node atomics_a_mask_sub_2_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_nbit_4)
node _atomics_a_mask_sub_acc_T_18 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_2_2_4)
node atomics_a_mask_sub_2_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_18)
node atomics_a_mask_sub_3_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_bit_4)
node _atomics_a_mask_sub_acc_T_19 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_3_2_4)
node atomics_a_mask_sub_3_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_19)
node atomics_a_mask_size_4 = bits(atomics_a_mask_sizeOH_4, 0, 0)
node atomics_a_mask_bit_4 = bits(req.addr, 0, 0)
node atomics_a_mask_nbit_4 = eq(atomics_a_mask_bit_4, UInt<1>(0h0))
node atomics_a_mask_eq_32 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_32 = and(atomics_a_mask_size_4, atomics_a_mask_eq_32)
node atomics_a_mask_acc_32 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_32)
node atomics_a_mask_eq_33 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_33 = and(atomics_a_mask_size_4, atomics_a_mask_eq_33)
node atomics_a_mask_acc_33 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_33)
node atomics_a_mask_eq_34 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_34 = and(atomics_a_mask_size_4, atomics_a_mask_eq_34)
node atomics_a_mask_acc_34 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_34)
node atomics_a_mask_eq_35 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_35 = and(atomics_a_mask_size_4, atomics_a_mask_eq_35)
node atomics_a_mask_acc_35 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_35)
node atomics_a_mask_eq_36 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_36 = and(atomics_a_mask_size_4, atomics_a_mask_eq_36)
node atomics_a_mask_acc_36 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_36)
node atomics_a_mask_eq_37 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_37 = and(atomics_a_mask_size_4, atomics_a_mask_eq_37)
node atomics_a_mask_acc_37 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_37)
node atomics_a_mask_eq_38 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_38 = and(atomics_a_mask_size_4, atomics_a_mask_eq_38)
node atomics_a_mask_acc_38 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_38)
node atomics_a_mask_eq_39 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_39 = and(atomics_a_mask_size_4, atomics_a_mask_eq_39)
node atomics_a_mask_acc_39 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_39)
node atomics_a_mask_lo_lo_4 = cat(atomics_a_mask_acc_33, atomics_a_mask_acc_32)
node atomics_a_mask_lo_hi_4 = cat(atomics_a_mask_acc_35, atomics_a_mask_acc_34)
node atomics_a_mask_lo_4 = cat(atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4)
node atomics_a_mask_hi_lo_4 = cat(atomics_a_mask_acc_37, atomics_a_mask_acc_36)
node atomics_a_mask_hi_hi_4 = cat(atomics_a_mask_acc_39, atomics_a_mask_acc_38)
node atomics_a_mask_hi_4 = cat(atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4)
node _atomics_a_mask_T_4 = cat(atomics_a_mask_hi_4, atomics_a_mask_lo_4)
connect atomics_a_4.mask, _atomics_a_mask_T_4
connect atomics_a_4.data, req.data
connect atomics_a_4.corrupt, UInt<1>(0h0)
node _atomics_legal_T_270 = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_271 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_272 = and(_atomics_legal_T_270, _atomics_legal_T_271)
node _atomics_legal_T_273 = or(UInt<1>(0h0), _atomics_legal_T_272)
node _atomics_legal_T_274 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_275 = cvt(_atomics_legal_T_274)
node _atomics_legal_T_276 = and(_atomics_legal_T_275, asSInt(UInt<33>(0h98110000)))
node _atomics_legal_T_277 = asSInt(_atomics_legal_T_276)
node _atomics_legal_T_278 = eq(_atomics_legal_T_277, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_279 = xor(req.addr, UInt<21>(0h100000))
node _atomics_legal_T_280 = cvt(_atomics_legal_T_279)
node _atomics_legal_T_281 = and(_atomics_legal_T_280, asSInt(UInt<33>(0h9a101000)))
node _atomics_legal_T_282 = asSInt(_atomics_legal_T_281)
node _atomics_legal_T_283 = eq(_atomics_legal_T_282, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_284 = xor(req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_285 = cvt(_atomics_legal_T_284)
node _atomics_legal_T_286 = and(_atomics_legal_T_285, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_287 = asSInt(_atomics_legal_T_286)
node _atomics_legal_T_288 = eq(_atomics_legal_T_287, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_289 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_290 = cvt(_atomics_legal_T_289)
node _atomics_legal_T_291 = and(_atomics_legal_T_290, asSInt(UInt<33>(0h98000000)))
node _atomics_legal_T_292 = asSInt(_atomics_legal_T_291)
node _atomics_legal_T_293 = eq(_atomics_legal_T_292, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_294 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_295 = cvt(_atomics_legal_T_294)
node _atomics_legal_T_296 = and(_atomics_legal_T_295, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_297 = asSInt(_atomics_legal_T_296)
node _atomics_legal_T_298 = eq(_atomics_legal_T_297, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_299 = xor(req.addr, UInt<29>(0h10000000))
node _atomics_legal_T_300 = cvt(_atomics_legal_T_299)
node _atomics_legal_T_301 = and(_atomics_legal_T_300, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_302 = asSInt(_atomics_legal_T_301)
node _atomics_legal_T_303 = eq(_atomics_legal_T_302, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_304 = xor(req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_305 = cvt(_atomics_legal_T_304)
node _atomics_legal_T_306 = and(_atomics_legal_T_305, asSInt(UInt<33>(0h90000000)))
node _atomics_legal_T_307 = asSInt(_atomics_legal_T_306)
node _atomics_legal_T_308 = eq(_atomics_legal_T_307, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_309 = or(_atomics_legal_T_278, _atomics_legal_T_283)
node _atomics_legal_T_310 = or(_atomics_legal_T_309, _atomics_legal_T_288)
node _atomics_legal_T_311 = or(_atomics_legal_T_310, _atomics_legal_T_293)
node _atomics_legal_T_312 = or(_atomics_legal_T_311, _atomics_legal_T_298)
node _atomics_legal_T_313 = or(_atomics_legal_T_312, _atomics_legal_T_303)
node _atomics_legal_T_314 = or(_atomics_legal_T_313, _atomics_legal_T_308)
node _atomics_legal_T_315 = and(_atomics_legal_T_273, _atomics_legal_T_314)
node _atomics_legal_T_316 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_317 = xor(req.addr, UInt<17>(0h10000))
node _atomics_legal_T_318 = cvt(_atomics_legal_T_317)
node _atomics_legal_T_319 = and(_atomics_legal_T_318, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_320 = asSInt(_atomics_legal_T_319)
node _atomics_legal_T_321 = eq(_atomics_legal_T_320, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_322 = and(_atomics_legal_T_316, _atomics_legal_T_321)
node _atomics_legal_T_323 = or(UInt<1>(0h0), _atomics_legal_T_315)
node atomics_legal_5 = or(_atomics_legal_T_323, _atomics_legal_T_322)
wire atomics_a_5 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_5.opcode, UInt<2>(0h2)
connect atomics_a_5.param, UInt<3>(0h0)
connect atomics_a_5.size, req.uop.mem_size
connect atomics_a_5.source, UInt<2>(0h3)
connect atomics_a_5.address, req.addr
node _atomics_a_mask_sizeOH_T_15 = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_5 = bits(_atomics_a_mask_sizeOH_T_15, 1, 0)
node _atomics_a_mask_sizeOH_T_16 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_5)
node _atomics_a_mask_sizeOH_T_17 = bits(_atomics_a_mask_sizeOH_T_16, 2, 0)
node atomics_a_mask_sizeOH_5 = or(_atomics_a_mask_sizeOH_T_17, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_5 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 2, 2)
node atomics_a_mask_sub_sub_bit_5 = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_5 = eq(atomics_a_mask_sub_sub_bit_5, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_5)
node _atomics_a_mask_sub_sub_acc_T_10 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_0_2_5)
node atomics_a_mask_sub_sub_0_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_10)
node atomics_a_mask_sub_sub_1_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_5)
node _atomics_a_mask_sub_sub_acc_T_11 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_1_2_5)
node atomics_a_mask_sub_sub_1_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_11)
node atomics_a_mask_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 1, 1)
node atomics_a_mask_sub_bit_5 = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit_5 = eq(atomics_a_mask_sub_bit_5, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_nbit_5)
node _atomics_a_mask_sub_acc_T_20 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_0_2_5)
node atomics_a_mask_sub_0_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_20)
node atomics_a_mask_sub_1_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_bit_5)
node _atomics_a_mask_sub_acc_T_21 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_1_2_5)
node atomics_a_mask_sub_1_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_21)
node atomics_a_mask_sub_2_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_nbit_5)
node _atomics_a_mask_sub_acc_T_22 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_2_2_5)
node atomics_a_mask_sub_2_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_22)
node atomics_a_mask_sub_3_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_bit_5)
node _atomics_a_mask_sub_acc_T_23 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_3_2_5)
node atomics_a_mask_sub_3_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_23)
node atomics_a_mask_size_5 = bits(atomics_a_mask_sizeOH_5, 0, 0)
node atomics_a_mask_bit_5 = bits(req.addr, 0, 0)
node atomics_a_mask_nbit_5 = eq(atomics_a_mask_bit_5, UInt<1>(0h0))
node atomics_a_mask_eq_40 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_40 = and(atomics_a_mask_size_5, atomics_a_mask_eq_40)
node atomics_a_mask_acc_40 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_40)
node atomics_a_mask_eq_41 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_41 = and(atomics_a_mask_size_5, atomics_a_mask_eq_41)
node atomics_a_mask_acc_41 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_41)
node atomics_a_mask_eq_42 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_42 = and(atomics_a_mask_size_5, atomics_a_mask_eq_42)
node atomics_a_mask_acc_42 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_42)
node atomics_a_mask_eq_43 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_43 = and(atomics_a_mask_size_5, atomics_a_mask_eq_43)
node atomics_a_mask_acc_43 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_43)
node atomics_a_mask_eq_44 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_44 = and(atomics_a_mask_size_5, atomics_a_mask_eq_44)
node atomics_a_mask_acc_44 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_44)
node atomics_a_mask_eq_45 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_45 = and(atomics_a_mask_size_5, atomics_a_mask_eq_45)
node atomics_a_mask_acc_45 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_45)
node atomics_a_mask_eq_46 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_46 = and(atomics_a_mask_size_5, atomics_a_mask_eq_46)
node atomics_a_mask_acc_46 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_46)
node atomics_a_mask_eq_47 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_47 = and(atomics_a_mask_size_5, atomics_a_mask_eq_47)
node atomics_a_mask_acc_47 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_47)
node atomics_a_mask_lo_lo_5 = cat(atomics_a_mask_acc_41, atomics_a_mask_acc_40)
node atomics_a_mask_lo_hi_5 = cat(atomics_a_mask_acc_43, atomics_a_mask_acc_42)
node atomics_a_mask_lo_5 = cat(atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5)
node atomics_a_mask_hi_lo_5 = cat(atomics_a_mask_acc_45, atomics_a_mask_acc_44)
node atomics_a_mask_hi_hi_5 = cat(atomics_a_mask_acc_47, atomics_a_mask_acc_46)
node atomics_a_mask_hi_5 = cat(atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5)
node _atomics_a_mask_T_5 = cat(atomics_a_mask_hi_5, atomics_a_mask_lo_5)
connect atomics_a_5.mask, _atomics_a_mask_T_5
connect atomics_a_5.data, req.data
connect atomics_a_5.corrupt, UInt<1>(0h0)
node _atomics_legal_T_324 = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_325 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_326 = and(_atomics_legal_T_324, _atomics_legal_T_325)
node _atomics_legal_T_327 = or(UInt<1>(0h0), _atomics_legal_T_326)
node _atomics_legal_T_328 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_329 = cvt(_atomics_legal_T_328)
node _atomics_legal_T_330 = and(_atomics_legal_T_329, asSInt(UInt<33>(0h98110000)))
node _atomics_legal_T_331 = asSInt(_atomics_legal_T_330)
node _atomics_legal_T_332 = eq(_atomics_legal_T_331, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_333 = xor(req.addr, UInt<21>(0h100000))
node _atomics_legal_T_334 = cvt(_atomics_legal_T_333)
node _atomics_legal_T_335 = and(_atomics_legal_T_334, asSInt(UInt<33>(0h9a101000)))
node _atomics_legal_T_336 = asSInt(_atomics_legal_T_335)
node _atomics_legal_T_337 = eq(_atomics_legal_T_336, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_338 = xor(req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_339 = cvt(_atomics_legal_T_338)
node _atomics_legal_T_340 = and(_atomics_legal_T_339, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_341 = asSInt(_atomics_legal_T_340)
node _atomics_legal_T_342 = eq(_atomics_legal_T_341, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_343 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_344 = cvt(_atomics_legal_T_343)
node _atomics_legal_T_345 = and(_atomics_legal_T_344, asSInt(UInt<33>(0h98000000)))
node _atomics_legal_T_346 = asSInt(_atomics_legal_T_345)
node _atomics_legal_T_347 = eq(_atomics_legal_T_346, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_348 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_349 = cvt(_atomics_legal_T_348)
node _atomics_legal_T_350 = and(_atomics_legal_T_349, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_351 = asSInt(_atomics_legal_T_350)
node _atomics_legal_T_352 = eq(_atomics_legal_T_351, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_353 = xor(req.addr, UInt<29>(0h10000000))
node _atomics_legal_T_354 = cvt(_atomics_legal_T_353)
node _atomics_legal_T_355 = and(_atomics_legal_T_354, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_356 = asSInt(_atomics_legal_T_355)
node _atomics_legal_T_357 = eq(_atomics_legal_T_356, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_358 = xor(req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_359 = cvt(_atomics_legal_T_358)
node _atomics_legal_T_360 = and(_atomics_legal_T_359, asSInt(UInt<33>(0h90000000)))
node _atomics_legal_T_361 = asSInt(_atomics_legal_T_360)
node _atomics_legal_T_362 = eq(_atomics_legal_T_361, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_363 = or(_atomics_legal_T_332, _atomics_legal_T_337)
node _atomics_legal_T_364 = or(_atomics_legal_T_363, _atomics_legal_T_342)
node _atomics_legal_T_365 = or(_atomics_legal_T_364, _atomics_legal_T_347)
node _atomics_legal_T_366 = or(_atomics_legal_T_365, _atomics_legal_T_352)
node _atomics_legal_T_367 = or(_atomics_legal_T_366, _atomics_legal_T_357)
node _atomics_legal_T_368 = or(_atomics_legal_T_367, _atomics_legal_T_362)
node _atomics_legal_T_369 = and(_atomics_legal_T_327, _atomics_legal_T_368)
node _atomics_legal_T_370 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_371 = xor(req.addr, UInt<17>(0h10000))
node _atomics_legal_T_372 = cvt(_atomics_legal_T_371)
node _atomics_legal_T_373 = and(_atomics_legal_T_372, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_374 = asSInt(_atomics_legal_T_373)
node _atomics_legal_T_375 = eq(_atomics_legal_T_374, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_376 = and(_atomics_legal_T_370, _atomics_legal_T_375)
node _atomics_legal_T_377 = or(UInt<1>(0h0), _atomics_legal_T_369)
node atomics_legal_6 = or(_atomics_legal_T_377, _atomics_legal_T_376)
wire atomics_a_6 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_6.opcode, UInt<2>(0h2)
connect atomics_a_6.param, UInt<3>(0h1)
connect atomics_a_6.size, req.uop.mem_size
connect atomics_a_6.source, UInt<2>(0h3)
connect atomics_a_6.address, req.addr
node _atomics_a_mask_sizeOH_T_18 = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_6 = bits(_atomics_a_mask_sizeOH_T_18, 1, 0)
node _atomics_a_mask_sizeOH_T_19 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_6)
node _atomics_a_mask_sizeOH_T_20 = bits(_atomics_a_mask_sizeOH_T_19, 2, 0)
node atomics_a_mask_sizeOH_6 = or(_atomics_a_mask_sizeOH_T_20, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_6 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 2, 2)
node atomics_a_mask_sub_sub_bit_6 = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_6 = eq(atomics_a_mask_sub_sub_bit_6, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_6)
node _atomics_a_mask_sub_sub_acc_T_12 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_0_2_6)
node atomics_a_mask_sub_sub_0_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_12)
node atomics_a_mask_sub_sub_1_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_6)
node _atomics_a_mask_sub_sub_acc_T_13 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_1_2_6)
node atomics_a_mask_sub_sub_1_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_13)
node atomics_a_mask_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 1, 1)
node atomics_a_mask_sub_bit_6 = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit_6 = eq(atomics_a_mask_sub_bit_6, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_nbit_6)
node _atomics_a_mask_sub_acc_T_24 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_0_2_6)
node atomics_a_mask_sub_0_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_24)
node atomics_a_mask_sub_1_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_bit_6)
node _atomics_a_mask_sub_acc_T_25 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_1_2_6)
node atomics_a_mask_sub_1_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_25)
node atomics_a_mask_sub_2_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_nbit_6)
node _atomics_a_mask_sub_acc_T_26 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_2_2_6)
node atomics_a_mask_sub_2_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_26)
node atomics_a_mask_sub_3_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_bit_6)
node _atomics_a_mask_sub_acc_T_27 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_3_2_6)
node atomics_a_mask_sub_3_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_27)
node atomics_a_mask_size_6 = bits(atomics_a_mask_sizeOH_6, 0, 0)
node atomics_a_mask_bit_6 = bits(req.addr, 0, 0)
node atomics_a_mask_nbit_6 = eq(atomics_a_mask_bit_6, UInt<1>(0h0))
node atomics_a_mask_eq_48 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_48 = and(atomics_a_mask_size_6, atomics_a_mask_eq_48)
node atomics_a_mask_acc_48 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_48)
node atomics_a_mask_eq_49 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_49 = and(atomics_a_mask_size_6, atomics_a_mask_eq_49)
node atomics_a_mask_acc_49 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_49)
node atomics_a_mask_eq_50 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_50 = and(atomics_a_mask_size_6, atomics_a_mask_eq_50)
node atomics_a_mask_acc_50 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_50)
node atomics_a_mask_eq_51 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_51 = and(atomics_a_mask_size_6, atomics_a_mask_eq_51)
node atomics_a_mask_acc_51 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_51)
node atomics_a_mask_eq_52 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_52 = and(atomics_a_mask_size_6, atomics_a_mask_eq_52)
node atomics_a_mask_acc_52 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_52)
node atomics_a_mask_eq_53 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_53 = and(atomics_a_mask_size_6, atomics_a_mask_eq_53)
node atomics_a_mask_acc_53 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_53)
node atomics_a_mask_eq_54 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_54 = and(atomics_a_mask_size_6, atomics_a_mask_eq_54)
node atomics_a_mask_acc_54 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_54)
node atomics_a_mask_eq_55 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_55 = and(atomics_a_mask_size_6, atomics_a_mask_eq_55)
node atomics_a_mask_acc_55 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_55)
node atomics_a_mask_lo_lo_6 = cat(atomics_a_mask_acc_49, atomics_a_mask_acc_48)
node atomics_a_mask_lo_hi_6 = cat(atomics_a_mask_acc_51, atomics_a_mask_acc_50)
node atomics_a_mask_lo_6 = cat(atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6)
node atomics_a_mask_hi_lo_6 = cat(atomics_a_mask_acc_53, atomics_a_mask_acc_52)
node atomics_a_mask_hi_hi_6 = cat(atomics_a_mask_acc_55, atomics_a_mask_acc_54)
node atomics_a_mask_hi_6 = cat(atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6)
node _atomics_a_mask_T_6 = cat(atomics_a_mask_hi_6, atomics_a_mask_lo_6)
connect atomics_a_6.mask, _atomics_a_mask_T_6
connect atomics_a_6.data, req.data
connect atomics_a_6.corrupt, UInt<1>(0h0)
node _atomics_legal_T_378 = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_379 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_380 = and(_atomics_legal_T_378, _atomics_legal_T_379)
node _atomics_legal_T_381 = or(UInt<1>(0h0), _atomics_legal_T_380)
node _atomics_legal_T_382 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_383 = cvt(_atomics_legal_T_382)
node _atomics_legal_T_384 = and(_atomics_legal_T_383, asSInt(UInt<33>(0h98110000)))
node _atomics_legal_T_385 = asSInt(_atomics_legal_T_384)
node _atomics_legal_T_386 = eq(_atomics_legal_T_385, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_387 = xor(req.addr, UInt<21>(0h100000))
node _atomics_legal_T_388 = cvt(_atomics_legal_T_387)
node _atomics_legal_T_389 = and(_atomics_legal_T_388, asSInt(UInt<33>(0h9a101000)))
node _atomics_legal_T_390 = asSInt(_atomics_legal_T_389)
node _atomics_legal_T_391 = eq(_atomics_legal_T_390, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_392 = xor(req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_393 = cvt(_atomics_legal_T_392)
node _atomics_legal_T_394 = and(_atomics_legal_T_393, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_395 = asSInt(_atomics_legal_T_394)
node _atomics_legal_T_396 = eq(_atomics_legal_T_395, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_397 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_398 = cvt(_atomics_legal_T_397)
node _atomics_legal_T_399 = and(_atomics_legal_T_398, asSInt(UInt<33>(0h98000000)))
node _atomics_legal_T_400 = asSInt(_atomics_legal_T_399)
node _atomics_legal_T_401 = eq(_atomics_legal_T_400, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_402 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_403 = cvt(_atomics_legal_T_402)
node _atomics_legal_T_404 = and(_atomics_legal_T_403, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_405 = asSInt(_atomics_legal_T_404)
node _atomics_legal_T_406 = eq(_atomics_legal_T_405, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_407 = xor(req.addr, UInt<29>(0h10000000))
node _atomics_legal_T_408 = cvt(_atomics_legal_T_407)
node _atomics_legal_T_409 = and(_atomics_legal_T_408, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_410 = asSInt(_atomics_legal_T_409)
node _atomics_legal_T_411 = eq(_atomics_legal_T_410, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_412 = xor(req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_413 = cvt(_atomics_legal_T_412)
node _atomics_legal_T_414 = and(_atomics_legal_T_413, asSInt(UInt<33>(0h90000000)))
node _atomics_legal_T_415 = asSInt(_atomics_legal_T_414)
node _atomics_legal_T_416 = eq(_atomics_legal_T_415, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_417 = or(_atomics_legal_T_386, _atomics_legal_T_391)
node _atomics_legal_T_418 = or(_atomics_legal_T_417, _atomics_legal_T_396)
node _atomics_legal_T_419 = or(_atomics_legal_T_418, _atomics_legal_T_401)
node _atomics_legal_T_420 = or(_atomics_legal_T_419, _atomics_legal_T_406)
node _atomics_legal_T_421 = or(_atomics_legal_T_420, _atomics_legal_T_411)
node _atomics_legal_T_422 = or(_atomics_legal_T_421, _atomics_legal_T_416)
node _atomics_legal_T_423 = and(_atomics_legal_T_381, _atomics_legal_T_422)
node _atomics_legal_T_424 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_425 = xor(req.addr, UInt<17>(0h10000))
node _atomics_legal_T_426 = cvt(_atomics_legal_T_425)
node _atomics_legal_T_427 = and(_atomics_legal_T_426, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_428 = asSInt(_atomics_legal_T_427)
node _atomics_legal_T_429 = eq(_atomics_legal_T_428, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_430 = and(_atomics_legal_T_424, _atomics_legal_T_429)
node _atomics_legal_T_431 = or(UInt<1>(0h0), _atomics_legal_T_423)
node atomics_legal_7 = or(_atomics_legal_T_431, _atomics_legal_T_430)
wire atomics_a_7 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_7.opcode, UInt<2>(0h2)
connect atomics_a_7.param, UInt<3>(0h2)
connect atomics_a_7.size, req.uop.mem_size
connect atomics_a_7.source, UInt<2>(0h3)
connect atomics_a_7.address, req.addr
node _atomics_a_mask_sizeOH_T_21 = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_7 = bits(_atomics_a_mask_sizeOH_T_21, 1, 0)
node _atomics_a_mask_sizeOH_T_22 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_7)
node _atomics_a_mask_sizeOH_T_23 = bits(_atomics_a_mask_sizeOH_T_22, 2, 0)
node atomics_a_mask_sizeOH_7 = or(_atomics_a_mask_sizeOH_T_23, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_7 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 2, 2)
node atomics_a_mask_sub_sub_bit_7 = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_7 = eq(atomics_a_mask_sub_sub_bit_7, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_7)
node _atomics_a_mask_sub_sub_acc_T_14 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_0_2_7)
node atomics_a_mask_sub_sub_0_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_14)
node atomics_a_mask_sub_sub_1_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_7)
node _atomics_a_mask_sub_sub_acc_T_15 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_1_2_7)
node atomics_a_mask_sub_sub_1_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_15)
node atomics_a_mask_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 1, 1)
node atomics_a_mask_sub_bit_7 = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit_7 = eq(atomics_a_mask_sub_bit_7, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_nbit_7)
node _atomics_a_mask_sub_acc_T_28 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_0_2_7)
node atomics_a_mask_sub_0_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_28)
node atomics_a_mask_sub_1_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_bit_7)
node _atomics_a_mask_sub_acc_T_29 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_1_2_7)
node atomics_a_mask_sub_1_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_29)
node atomics_a_mask_sub_2_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_nbit_7)
node _atomics_a_mask_sub_acc_T_30 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_2_2_7)
node atomics_a_mask_sub_2_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_30)
node atomics_a_mask_sub_3_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_bit_7)
node _atomics_a_mask_sub_acc_T_31 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_3_2_7)
node atomics_a_mask_sub_3_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_31)
node atomics_a_mask_size_7 = bits(atomics_a_mask_sizeOH_7, 0, 0)
node atomics_a_mask_bit_7 = bits(req.addr, 0, 0)
node atomics_a_mask_nbit_7 = eq(atomics_a_mask_bit_7, UInt<1>(0h0))
node atomics_a_mask_eq_56 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_56 = and(atomics_a_mask_size_7, atomics_a_mask_eq_56)
node atomics_a_mask_acc_56 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_56)
node atomics_a_mask_eq_57 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_57 = and(atomics_a_mask_size_7, atomics_a_mask_eq_57)
node atomics_a_mask_acc_57 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_57)
node atomics_a_mask_eq_58 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_58 = and(atomics_a_mask_size_7, atomics_a_mask_eq_58)
node atomics_a_mask_acc_58 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_58)
node atomics_a_mask_eq_59 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_59 = and(atomics_a_mask_size_7, atomics_a_mask_eq_59)
node atomics_a_mask_acc_59 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_59)
node atomics_a_mask_eq_60 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_60 = and(atomics_a_mask_size_7, atomics_a_mask_eq_60)
node atomics_a_mask_acc_60 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_60)
node atomics_a_mask_eq_61 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_61 = and(atomics_a_mask_size_7, atomics_a_mask_eq_61)
node atomics_a_mask_acc_61 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_61)
node atomics_a_mask_eq_62 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_62 = and(atomics_a_mask_size_7, atomics_a_mask_eq_62)
node atomics_a_mask_acc_62 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_62)
node atomics_a_mask_eq_63 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_63 = and(atomics_a_mask_size_7, atomics_a_mask_eq_63)
node atomics_a_mask_acc_63 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_63)
node atomics_a_mask_lo_lo_7 = cat(atomics_a_mask_acc_57, atomics_a_mask_acc_56)
node atomics_a_mask_lo_hi_7 = cat(atomics_a_mask_acc_59, atomics_a_mask_acc_58)
node atomics_a_mask_lo_7 = cat(atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7)
node atomics_a_mask_hi_lo_7 = cat(atomics_a_mask_acc_61, atomics_a_mask_acc_60)
node atomics_a_mask_hi_hi_7 = cat(atomics_a_mask_acc_63, atomics_a_mask_acc_62)
node atomics_a_mask_hi_7 = cat(atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7)
node _atomics_a_mask_T_7 = cat(atomics_a_mask_hi_7, atomics_a_mask_lo_7)
connect atomics_a_7.mask, _atomics_a_mask_T_7
connect atomics_a_7.data, req.data
connect atomics_a_7.corrupt, UInt<1>(0h0)
node _atomics_legal_T_432 = leq(UInt<1>(0h0), req.uop.mem_size)
node _atomics_legal_T_433 = leq(req.uop.mem_size, UInt<2>(0h3))
node _atomics_legal_T_434 = and(_atomics_legal_T_432, _atomics_legal_T_433)
node _atomics_legal_T_435 = or(UInt<1>(0h0), _atomics_legal_T_434)
node _atomics_legal_T_436 = xor(req.addr, UInt<1>(0h0))
node _atomics_legal_T_437 = cvt(_atomics_legal_T_436)
node _atomics_legal_T_438 = and(_atomics_legal_T_437, asSInt(UInt<33>(0h98110000)))
node _atomics_legal_T_439 = asSInt(_atomics_legal_T_438)
node _atomics_legal_T_440 = eq(_atomics_legal_T_439, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_441 = xor(req.addr, UInt<21>(0h100000))
node _atomics_legal_T_442 = cvt(_atomics_legal_T_441)
node _atomics_legal_T_443 = and(_atomics_legal_T_442, asSInt(UInt<33>(0h9a101000)))
node _atomics_legal_T_444 = asSInt(_atomics_legal_T_443)
node _atomics_legal_T_445 = eq(_atomics_legal_T_444, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_446 = xor(req.addr, UInt<26>(0h2010000))
node _atomics_legal_T_447 = cvt(_atomics_legal_T_446)
node _atomics_legal_T_448 = and(_atomics_legal_T_447, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_449 = asSInt(_atomics_legal_T_448)
node _atomics_legal_T_450 = eq(_atomics_legal_T_449, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_451 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_452 = cvt(_atomics_legal_T_451)
node _atomics_legal_T_453 = and(_atomics_legal_T_452, asSInt(UInt<33>(0h98000000)))
node _atomics_legal_T_454 = asSInt(_atomics_legal_T_453)
node _atomics_legal_T_455 = eq(_atomics_legal_T_454, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_456 = xor(req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_457 = cvt(_atomics_legal_T_456)
node _atomics_legal_T_458 = and(_atomics_legal_T_457, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_459 = asSInt(_atomics_legal_T_458)
node _atomics_legal_T_460 = eq(_atomics_legal_T_459, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_461 = xor(req.addr, UInt<29>(0h10000000))
node _atomics_legal_T_462 = cvt(_atomics_legal_T_461)
node _atomics_legal_T_463 = and(_atomics_legal_T_462, asSInt(UInt<33>(0h9a111000)))
node _atomics_legal_T_464 = asSInt(_atomics_legal_T_463)
node _atomics_legal_T_465 = eq(_atomics_legal_T_464, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_466 = xor(req.addr, UInt<32>(0h80000000))
node _atomics_legal_T_467 = cvt(_atomics_legal_T_466)
node _atomics_legal_T_468 = and(_atomics_legal_T_467, asSInt(UInt<33>(0h90000000)))
node _atomics_legal_T_469 = asSInt(_atomics_legal_T_468)
node _atomics_legal_T_470 = eq(_atomics_legal_T_469, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_471 = or(_atomics_legal_T_440, _atomics_legal_T_445)
node _atomics_legal_T_472 = or(_atomics_legal_T_471, _atomics_legal_T_450)
node _atomics_legal_T_473 = or(_atomics_legal_T_472, _atomics_legal_T_455)
node _atomics_legal_T_474 = or(_atomics_legal_T_473, _atomics_legal_T_460)
node _atomics_legal_T_475 = or(_atomics_legal_T_474, _atomics_legal_T_465)
node _atomics_legal_T_476 = or(_atomics_legal_T_475, _atomics_legal_T_470)
node _atomics_legal_T_477 = and(_atomics_legal_T_435, _atomics_legal_T_476)
node _atomics_legal_T_478 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_479 = xor(req.addr, UInt<17>(0h10000))
node _atomics_legal_T_480 = cvt(_atomics_legal_T_479)
node _atomics_legal_T_481 = and(_atomics_legal_T_480, asSInt(UInt<33>(0h9a110000)))
node _atomics_legal_T_482 = asSInt(_atomics_legal_T_481)
node _atomics_legal_T_483 = eq(_atomics_legal_T_482, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_484 = and(_atomics_legal_T_478, _atomics_legal_T_483)
node _atomics_legal_T_485 = or(UInt<1>(0h0), _atomics_legal_T_477)
node atomics_legal_8 = or(_atomics_legal_T_485, _atomics_legal_T_484)
wire atomics_a_8 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_8.opcode, UInt<2>(0h2)
connect atomics_a_8.param, UInt<3>(0h3)
connect atomics_a_8.size, req.uop.mem_size
connect atomics_a_8.source, UInt<2>(0h3)
connect atomics_a_8.address, req.addr
node _atomics_a_mask_sizeOH_T_24 = or(req.uop.mem_size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_8 = bits(_atomics_a_mask_sizeOH_T_24, 1, 0)
node _atomics_a_mask_sizeOH_T_25 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_8)
node _atomics_a_mask_sizeOH_T_26 = bits(_atomics_a_mask_sizeOH_T_25, 2, 0)
node atomics_a_mask_sizeOH_8 = or(_atomics_a_mask_sizeOH_T_26, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_8 = geq(req.uop.mem_size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 2, 2)
node atomics_a_mask_sub_sub_bit_8 = bits(req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_8 = eq(atomics_a_mask_sub_sub_bit_8, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_8)
node _atomics_a_mask_sub_sub_acc_T_16 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_0_2_8)
node atomics_a_mask_sub_sub_0_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_16)
node atomics_a_mask_sub_sub_1_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_8)
node _atomics_a_mask_sub_sub_acc_T_17 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_1_2_8)
node atomics_a_mask_sub_sub_1_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_17)
node atomics_a_mask_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 1, 1)
node atomics_a_mask_sub_bit_8 = bits(req.addr, 1, 1)
node atomics_a_mask_sub_nbit_8 = eq(atomics_a_mask_sub_bit_8, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_nbit_8)
node _atomics_a_mask_sub_acc_T_32 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_0_2_8)
node atomics_a_mask_sub_0_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_32)
node atomics_a_mask_sub_1_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_bit_8)
node _atomics_a_mask_sub_acc_T_33 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_1_2_8)
node atomics_a_mask_sub_1_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_33)
node atomics_a_mask_sub_2_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_nbit_8)
node _atomics_a_mask_sub_acc_T_34 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_2_2_8)
node atomics_a_mask_sub_2_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_34)
node atomics_a_mask_sub_3_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_bit_8)
node _atomics_a_mask_sub_acc_T_35 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_3_2_8)
node atomics_a_mask_sub_3_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_35)
node atomics_a_mask_size_8 = bits(atomics_a_mask_sizeOH_8, 0, 0)
node atomics_a_mask_bit_8 = bits(req.addr, 0, 0)
node atomics_a_mask_nbit_8 = eq(atomics_a_mask_bit_8, UInt<1>(0h0))
node atomics_a_mask_eq_64 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_64 = and(atomics_a_mask_size_8, atomics_a_mask_eq_64)
node atomics_a_mask_acc_64 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_64)
node atomics_a_mask_eq_65 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_65 = and(atomics_a_mask_size_8, atomics_a_mask_eq_65)
node atomics_a_mask_acc_65 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_65)
node atomics_a_mask_eq_66 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_66 = and(atomics_a_mask_size_8, atomics_a_mask_eq_66)
node atomics_a_mask_acc_66 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_66)
node atomics_a_mask_eq_67 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_67 = and(atomics_a_mask_size_8, atomics_a_mask_eq_67)
node atomics_a_mask_acc_67 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_67)
node atomics_a_mask_eq_68 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_68 = and(atomics_a_mask_size_8, atomics_a_mask_eq_68)
node atomics_a_mask_acc_68 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_68)
node atomics_a_mask_eq_69 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_69 = and(atomics_a_mask_size_8, atomics_a_mask_eq_69)
node atomics_a_mask_acc_69 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_69)
node atomics_a_mask_eq_70 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_70 = and(atomics_a_mask_size_8, atomics_a_mask_eq_70)
node atomics_a_mask_acc_70 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_70)
node atomics_a_mask_eq_71 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_71 = and(atomics_a_mask_size_8, atomics_a_mask_eq_71)
node atomics_a_mask_acc_71 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_71)
node atomics_a_mask_lo_lo_8 = cat(atomics_a_mask_acc_65, atomics_a_mask_acc_64)
node atomics_a_mask_lo_hi_8 = cat(atomics_a_mask_acc_67, atomics_a_mask_acc_66)
node atomics_a_mask_lo_8 = cat(atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8)
node atomics_a_mask_hi_lo_8 = cat(atomics_a_mask_acc_69, atomics_a_mask_acc_68)
node atomics_a_mask_hi_hi_8 = cat(atomics_a_mask_acc_71, atomics_a_mask_acc_70)
node atomics_a_mask_hi_8 = cat(atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8)
node _atomics_a_mask_T_8 = cat(atomics_a_mask_hi_8, atomics_a_mask_lo_8)
connect atomics_a_8.mask, _atomics_a_mask_T_8
connect atomics_a_8.data, req.data
connect atomics_a_8.corrupt, UInt<1>(0h0)
node _atomics_T = eq(UInt<3>(0h4), req.uop.mem_cmd)
node _atomics_T_1 = mux(_atomics_T, atomics_a, _atomics_WIRE)
node _atomics_T_2 = eq(UInt<4>(0h9), req.uop.mem_cmd)
node _atomics_T_3 = mux(_atomics_T_2, atomics_a_1, _atomics_T_1)
node _atomics_T_4 = eq(UInt<4>(0ha), req.uop.mem_cmd)
node _atomics_T_5 = mux(_atomics_T_4, atomics_a_2, _atomics_T_3)
node _atomics_T_6 = eq(UInt<4>(0hb), req.uop.mem_cmd)
node _atomics_T_7 = mux(_atomics_T_6, atomics_a_3, _atomics_T_5)
node _atomics_T_8 = eq(UInt<4>(0h8), req.uop.mem_cmd)
node _atomics_T_9 = mux(_atomics_T_8, atomics_a_4, _atomics_T_7)
node _atomics_T_10 = eq(UInt<4>(0hc), req.uop.mem_cmd)
node _atomics_T_11 = mux(_atomics_T_10, atomics_a_5, _atomics_T_9)
node _atomics_T_12 = eq(UInt<4>(0hd), req.uop.mem_cmd)
node _atomics_T_13 = mux(_atomics_T_12, atomics_a_6, _atomics_T_11)
node _atomics_T_14 = eq(UInt<4>(0he), req.uop.mem_cmd)
node _atomics_T_15 = mux(_atomics_T_14, atomics_a_7, _atomics_T_13)
node _atomics_T_16 = eq(UInt<4>(0hf), req.uop.mem_cmd)
node atomics = mux(_atomics_T_16, atomics_a_8, _atomics_T_15)
node _T = eq(state, UInt<2>(0h0))
node _T_1 = neq(req.uop.mem_cmd, UInt<3>(0h7))
node _T_2 = or(_T, _T_1)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:454 assert(state === s_idle || req.uop.mem_cmd =/= M_XSC)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_mem_access_valid_T = eq(state, UInt<2>(0h1))
connect io.mem_access.valid, _io_mem_access_valid_T
node _io_mem_access_bits_T = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _io_mem_access_bits_T_1 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _io_mem_access_bits_T_2 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _io_mem_access_bits_T_3 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _io_mem_access_bits_T_4 = or(_io_mem_access_bits_T, _io_mem_access_bits_T_1)
node _io_mem_access_bits_T_5 = or(_io_mem_access_bits_T_4, _io_mem_access_bits_T_2)
node _io_mem_access_bits_T_6 = or(_io_mem_access_bits_T_5, _io_mem_access_bits_T_3)
node _io_mem_access_bits_T_7 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _io_mem_access_bits_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _io_mem_access_bits_T_9 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _io_mem_access_bits_T_10 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _io_mem_access_bits_T_11 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _io_mem_access_bits_T_12 = or(_io_mem_access_bits_T_7, _io_mem_access_bits_T_8)
node _io_mem_access_bits_T_13 = or(_io_mem_access_bits_T_12, _io_mem_access_bits_T_9)
node _io_mem_access_bits_T_14 = or(_io_mem_access_bits_T_13, _io_mem_access_bits_T_10)
node _io_mem_access_bits_T_15 = or(_io_mem_access_bits_T_14, _io_mem_access_bits_T_11)
node _io_mem_access_bits_T_16 = or(_io_mem_access_bits_T_6, _io_mem_access_bits_T_15)
node _io_mem_access_bits_T_17 = eq(req.uop.mem_cmd, UInt<1>(0h0))
node _io_mem_access_bits_T_18 = eq(req.uop.mem_cmd, UInt<5>(0h10))
node _io_mem_access_bits_T_19 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _io_mem_access_bits_T_20 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _io_mem_access_bits_T_21 = or(_io_mem_access_bits_T_17, _io_mem_access_bits_T_18)
node _io_mem_access_bits_T_22 = or(_io_mem_access_bits_T_21, _io_mem_access_bits_T_19)
node _io_mem_access_bits_T_23 = or(_io_mem_access_bits_T_22, _io_mem_access_bits_T_20)
node _io_mem_access_bits_T_24 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _io_mem_access_bits_T_25 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _io_mem_access_bits_T_26 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _io_mem_access_bits_T_27 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _io_mem_access_bits_T_28 = or(_io_mem_access_bits_T_24, _io_mem_access_bits_T_25)
node _io_mem_access_bits_T_29 = or(_io_mem_access_bits_T_28, _io_mem_access_bits_T_26)
node _io_mem_access_bits_T_30 = or(_io_mem_access_bits_T_29, _io_mem_access_bits_T_27)
node _io_mem_access_bits_T_31 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _io_mem_access_bits_T_32 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _io_mem_access_bits_T_33 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _io_mem_access_bits_T_34 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _io_mem_access_bits_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _io_mem_access_bits_T_36 = or(_io_mem_access_bits_T_31, _io_mem_access_bits_T_32)
node _io_mem_access_bits_T_37 = or(_io_mem_access_bits_T_36, _io_mem_access_bits_T_33)
node _io_mem_access_bits_T_38 = or(_io_mem_access_bits_T_37, _io_mem_access_bits_T_34)
node _io_mem_access_bits_T_39 = or(_io_mem_access_bits_T_38, _io_mem_access_bits_T_35)
node _io_mem_access_bits_T_40 = or(_io_mem_access_bits_T_30, _io_mem_access_bits_T_39)
node _io_mem_access_bits_T_41 = or(_io_mem_access_bits_T_23, _io_mem_access_bits_T_40)
node _io_mem_access_bits_T_42 = mux(_io_mem_access_bits_T_41, get, put)
node _io_mem_access_bits_T_43 = mux(_io_mem_access_bits_T_16, atomics, _io_mem_access_bits_T_42)
connect io.mem_access.bits, _io_mem_access_bits_T_43
node _send_resp_T = eq(req.uop.mem_cmd, UInt<1>(0h0))
node _send_resp_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h10))
node _send_resp_T_2 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _send_resp_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _send_resp_T_4 = or(_send_resp_T, _send_resp_T_1)
node _send_resp_T_5 = or(_send_resp_T_4, _send_resp_T_2)
node _send_resp_T_6 = or(_send_resp_T_5, _send_resp_T_3)
node _send_resp_T_7 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _send_resp_T_8 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _send_resp_T_9 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _send_resp_T_10 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _send_resp_T_11 = or(_send_resp_T_7, _send_resp_T_8)
node _send_resp_T_12 = or(_send_resp_T_11, _send_resp_T_9)
node _send_resp_T_13 = or(_send_resp_T_12, _send_resp_T_10)
node _send_resp_T_14 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _send_resp_T_15 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _send_resp_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _send_resp_T_17 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _send_resp_T_18 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _send_resp_T_19 = or(_send_resp_T_14, _send_resp_T_15)
node _send_resp_T_20 = or(_send_resp_T_19, _send_resp_T_16)
node _send_resp_T_21 = or(_send_resp_T_20, _send_resp_T_17)
node _send_resp_T_22 = or(_send_resp_T_21, _send_resp_T_18)
node _send_resp_T_23 = or(_send_resp_T_13, _send_resp_T_22)
node send_resp = or(_send_resp_T_6, _send_resp_T_23)
node _io_resp_valid_T = eq(state, UInt<2>(0h3))
node _io_resp_valid_T_1 = and(_io_resp_valid_T, send_resp)
connect io.resp.valid, _io_resp_valid_T_1
connect io.resp.bits.is_hella, req.is_hella
connect io.resp.bits.uop, req.uop
node _io_resp_bits_data_shifted_T = bits(req.addr, 2, 2)
node _io_resp_bits_data_shifted_T_1 = bits(grant_word, 63, 32)
node _io_resp_bits_data_shifted_T_2 = bits(grant_word, 31, 0)
node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2)
node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted)
node _io_resp_bits_data_T = eq(size, UInt<2>(0h2))
node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero)
node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31)
node _io_resp_bits_data_T_3 = and(req.uop.mem_signed, _io_resp_bits_data_T_2)
node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_resp_bits_data_T_5 = bits(grant_word, 63, 32)
node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5)
node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed)
node _io_resp_bits_data_shifted_T_3 = bits(req.addr, 1, 1)
node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16)
node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0)
node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5)
node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1)
node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1))
node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1)
node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15)
node _io_resp_bits_data_T_11 = and(req.uop.mem_signed, _io_resp_bits_data_T_10)
node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16)
node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13)
node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1)
node _io_resp_bits_data_shifted_T_6 = bits(req.addr, 0, 0)
node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8)
node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0)
node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8)
node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0))
node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2)
node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0))
node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2)
node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7)
node _io_resp_bits_data_T_19 = and(req.uop.mem_signed, _io_resp_bits_data_T_18)
node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8)
node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21)
node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2)
connect io.resp.bits.data, _io_resp_bits_data_T_23
node _T_6 = and(io.req.ready, io.req.valid)
when _T_6 :
connect req, io.req.bits
connect state, UInt<2>(0h1)
node _T_7 = and(io.mem_access.ready, io.mem_access.valid)
when _T_7 :
connect state, UInt<2>(0h2)
node _T_8 = eq(state, UInt<2>(0h2))
node _T_9 = and(_T_8, io.mem_ack.valid)
when _T_9 :
connect state, UInt<2>(0h3)
node _T_10 = eq(req.uop.mem_cmd, UInt<1>(0h0))
node _T_11 = eq(req.uop.mem_cmd, UInt<5>(0h10))
node _T_12 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _T_13 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _T_14 = or(_T_10, _T_11)
node _T_15 = or(_T_14, _T_12)
node _T_16 = or(_T_15, _T_13)
node _T_17 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _T_18 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _T_19 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _T_20 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _T_21 = or(_T_17, _T_18)
node _T_22 = or(_T_21, _T_19)
node _T_23 = or(_T_22, _T_20)
node _T_24 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _T_25 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _T_26 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _T_27 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _T_28 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _T_29 = or(_T_24, _T_25)
node _T_30 = or(_T_29, _T_26)
node _T_31 = or(_T_30, _T_27)
node _T_32 = or(_T_31, _T_28)
node _T_33 = or(_T_23, _T_32)
node _T_34 = or(_T_16, _T_33)
when _T_34 :
node grant_word_shift = cat(UInt<1>(0h0), UInt<6>(0h0))
node _grant_word_T = dshr(io.mem_ack.bits.data, grant_word_shift)
node _grant_word_T_1 = bits(_grant_word_T, 63, 0)
connect grant_word, _grant_word_T_1
node _T_35 = eq(state, UInt<2>(0h3))
when _T_35 :
node _T_36 = eq(send_resp, UInt<1>(0h0))
node _T_37 = and(io.resp.ready, io.resp.valid)
node _T_38 = or(_T_36, _T_37)
when _T_38 :
connect state, UInt<2>(0h0) | module BoomIOMSHR_1( // @[mshrs.scala:402:7]
input clock, // @[mshrs.scala:402:7]
input reset, // @[mshrs.scala:402:7]
output io_req_ready, // @[mshrs.scala:405:14]
input io_req_valid, // @[mshrs.scala:405:14]
input [6:0] io_req_bits_uop_uopc, // @[mshrs.scala:405:14]
input [31:0] io_req_bits_uop_inst, // @[mshrs.scala:405:14]
input [31:0] io_req_bits_uop_debug_inst, // @[mshrs.scala:405:14]
input io_req_bits_uop_is_rvc, // @[mshrs.scala:405:14]
input [39:0] io_req_bits_uop_debug_pc, // @[mshrs.scala:405:14]
input [2:0] io_req_bits_uop_iq_type, // @[mshrs.scala:405:14]
input [9:0] io_req_bits_uop_fu_code, // @[mshrs.scala:405:14]
input [3:0] io_req_bits_uop_ctrl_br_type, // @[mshrs.scala:405:14]
input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[mshrs.scala:405:14]
input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[mshrs.scala:405:14]
input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[mshrs.scala:405:14]
input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[mshrs.scala:405:14]
input io_req_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:405:14]
input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:405:14]
input io_req_bits_uop_ctrl_is_load, // @[mshrs.scala:405:14]
input io_req_bits_uop_ctrl_is_sta, // @[mshrs.scala:405:14]
input io_req_bits_uop_ctrl_is_std, // @[mshrs.scala:405:14]
input [1:0] io_req_bits_uop_iw_state, // @[mshrs.scala:405:14]
input io_req_bits_uop_iw_p1_poisoned, // @[mshrs.scala:405:14]
input io_req_bits_uop_iw_p2_poisoned, // @[mshrs.scala:405:14]
input io_req_bits_uop_is_br, // @[mshrs.scala:405:14]
input io_req_bits_uop_is_jalr, // @[mshrs.scala:405:14]
input io_req_bits_uop_is_jal, // @[mshrs.scala:405:14]
input io_req_bits_uop_is_sfb, // @[mshrs.scala:405:14]
input [7:0] io_req_bits_uop_br_mask, // @[mshrs.scala:405:14]
input [2:0] io_req_bits_uop_br_tag, // @[mshrs.scala:405:14]
input [3:0] io_req_bits_uop_ftq_idx, // @[mshrs.scala:405:14]
input io_req_bits_uop_edge_inst, // @[mshrs.scala:405:14]
input [5:0] io_req_bits_uop_pc_lob, // @[mshrs.scala:405:14]
input io_req_bits_uop_taken, // @[mshrs.scala:405:14]
input [19:0] io_req_bits_uop_imm_packed, // @[mshrs.scala:405:14]
input [11:0] io_req_bits_uop_csr_addr, // @[mshrs.scala:405:14]
input [4:0] io_req_bits_uop_rob_idx, // @[mshrs.scala:405:14]
input [2:0] io_req_bits_uop_ldq_idx, // @[mshrs.scala:405:14]
input [2:0] io_req_bits_uop_stq_idx, // @[mshrs.scala:405:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[mshrs.scala:405:14]
input [5:0] io_req_bits_uop_pdst, // @[mshrs.scala:405:14]
input [5:0] io_req_bits_uop_prs1, // @[mshrs.scala:405:14]
input [5:0] io_req_bits_uop_prs2, // @[mshrs.scala:405:14]
input [5:0] io_req_bits_uop_prs3, // @[mshrs.scala:405:14]
input [3:0] io_req_bits_uop_ppred, // @[mshrs.scala:405:14]
input io_req_bits_uop_prs1_busy, // @[mshrs.scala:405:14]
input io_req_bits_uop_prs2_busy, // @[mshrs.scala:405:14]
input io_req_bits_uop_prs3_busy, // @[mshrs.scala:405:14]
input io_req_bits_uop_ppred_busy, // @[mshrs.scala:405:14]
input [5:0] io_req_bits_uop_stale_pdst, // @[mshrs.scala:405:14]
input io_req_bits_uop_exception, // @[mshrs.scala:405:14]
input [63:0] io_req_bits_uop_exc_cause, // @[mshrs.scala:405:14]
input io_req_bits_uop_bypassable, // @[mshrs.scala:405:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[mshrs.scala:405:14]
input [1:0] io_req_bits_uop_mem_size, // @[mshrs.scala:405:14]
input io_req_bits_uop_mem_signed, // @[mshrs.scala:405:14]
input io_req_bits_uop_is_fence, // @[mshrs.scala:405:14]
input io_req_bits_uop_is_fencei, // @[mshrs.scala:405:14]
input io_req_bits_uop_is_amo, // @[mshrs.scala:405:14]
input io_req_bits_uop_uses_ldq, // @[mshrs.scala:405:14]
input io_req_bits_uop_uses_stq, // @[mshrs.scala:405:14]
input io_req_bits_uop_is_sys_pc2epc, // @[mshrs.scala:405:14]
input io_req_bits_uop_is_unique, // @[mshrs.scala:405:14]
input io_req_bits_uop_flush_on_commit, // @[mshrs.scala:405:14]
input io_req_bits_uop_ldst_is_rs1, // @[mshrs.scala:405:14]
input [5:0] io_req_bits_uop_ldst, // @[mshrs.scala:405:14]
input [5:0] io_req_bits_uop_lrs1, // @[mshrs.scala:405:14]
input [5:0] io_req_bits_uop_lrs2, // @[mshrs.scala:405:14]
input [5:0] io_req_bits_uop_lrs3, // @[mshrs.scala:405:14]
input io_req_bits_uop_ldst_val, // @[mshrs.scala:405:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[mshrs.scala:405:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[mshrs.scala:405:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[mshrs.scala:405:14]
input io_req_bits_uop_frs3_en, // @[mshrs.scala:405:14]
input io_req_bits_uop_fp_val, // @[mshrs.scala:405:14]
input io_req_bits_uop_fp_single, // @[mshrs.scala:405:14]
input io_req_bits_uop_xcpt_pf_if, // @[mshrs.scala:405:14]
input io_req_bits_uop_xcpt_ae_if, // @[mshrs.scala:405:14]
input io_req_bits_uop_xcpt_ma_if, // @[mshrs.scala:405:14]
input io_req_bits_uop_bp_debug_if, // @[mshrs.scala:405:14]
input io_req_bits_uop_bp_xcpt_if, // @[mshrs.scala:405:14]
input [1:0] io_req_bits_uop_debug_fsrc, // @[mshrs.scala:405:14]
input [1:0] io_req_bits_uop_debug_tsrc, // @[mshrs.scala:405:14]
input [39:0] io_req_bits_addr, // @[mshrs.scala:405:14]
input [63:0] io_req_bits_data, // @[mshrs.scala:405:14]
input io_req_bits_is_hella, // @[mshrs.scala:405:14]
input io_resp_ready, // @[mshrs.scala:405:14]
output io_resp_valid, // @[mshrs.scala:405:14]
output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:405:14]
output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:405:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:405:14]
output io_resp_bits_uop_is_rvc, // @[mshrs.scala:405:14]
output [39:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:405:14]
output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:405:14]
output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:405:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:405:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:405:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:405:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:405:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:405:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:405:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:405:14]
output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:405:14]
output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:405:14]
output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:405:14]
output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:405:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:405:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:405:14]
output io_resp_bits_uop_is_br, // @[mshrs.scala:405:14]
output io_resp_bits_uop_is_jalr, // @[mshrs.scala:405:14]
output io_resp_bits_uop_is_jal, // @[mshrs.scala:405:14]
output io_resp_bits_uop_is_sfb, // @[mshrs.scala:405:14]
output [7:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:405:14]
output [2:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:405:14]
output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:405:14]
output io_resp_bits_uop_edge_inst, // @[mshrs.scala:405:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:405:14]
output io_resp_bits_uop_taken, // @[mshrs.scala:405:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:405:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:405:14]
output [4:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:405:14]
output [2:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:405:14]
output [2:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:405:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:405:14]
output [5:0] io_resp_bits_uop_pdst, // @[mshrs.scala:405:14]
output [5:0] io_resp_bits_uop_prs1, // @[mshrs.scala:405:14]
output [5:0] io_resp_bits_uop_prs2, // @[mshrs.scala:405:14]
output [5:0] io_resp_bits_uop_prs3, // @[mshrs.scala:405:14]
output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:405:14]
output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:405:14]
output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:405:14]
output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:405:14]
output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:405:14]
output [5:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:405:14]
output io_resp_bits_uop_exception, // @[mshrs.scala:405:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:405:14]
output io_resp_bits_uop_bypassable, // @[mshrs.scala:405:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:405:14]
output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:405:14]
output io_resp_bits_uop_mem_signed, // @[mshrs.scala:405:14]
output io_resp_bits_uop_is_fence, // @[mshrs.scala:405:14]
output io_resp_bits_uop_is_fencei, // @[mshrs.scala:405:14]
output io_resp_bits_uop_is_amo, // @[mshrs.scala:405:14]
output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:405:14]
output io_resp_bits_uop_uses_stq, // @[mshrs.scala:405:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:405:14]
output io_resp_bits_uop_is_unique, // @[mshrs.scala:405:14]
output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:405:14]
output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:405:14]
output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:405:14]
output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:405:14]
output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:405:14]
output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:405:14]
output io_resp_bits_uop_ldst_val, // @[mshrs.scala:405:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:405:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:405:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:405:14]
output io_resp_bits_uop_frs3_en, // @[mshrs.scala:405:14]
output io_resp_bits_uop_fp_val, // @[mshrs.scala:405:14]
output io_resp_bits_uop_fp_single, // @[mshrs.scala:405:14]
output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:405:14]
output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:405:14]
output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:405:14]
output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:405:14]
output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:405:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:405:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:405:14]
output [63:0] io_resp_bits_data, // @[mshrs.scala:405:14]
output io_resp_bits_is_hella, // @[mshrs.scala:405:14]
input io_mem_access_ready, // @[mshrs.scala:405:14]
output io_mem_access_valid, // @[mshrs.scala:405:14]
output [2:0] io_mem_access_bits_opcode, // @[mshrs.scala:405:14]
output [2:0] io_mem_access_bits_param, // @[mshrs.scala:405:14]
output [3:0] io_mem_access_bits_size, // @[mshrs.scala:405:14]
output [1:0] io_mem_access_bits_source, // @[mshrs.scala:405:14]
output [31:0] io_mem_access_bits_address, // @[mshrs.scala:405:14]
output [7:0] io_mem_access_bits_mask, // @[mshrs.scala:405:14]
output [63:0] io_mem_access_bits_data, // @[mshrs.scala:405:14]
input io_mem_ack_valid, // @[mshrs.scala:405:14]
input [2:0] io_mem_ack_bits_opcode, // @[mshrs.scala:405:14]
input [1:0] io_mem_ack_bits_param, // @[mshrs.scala:405:14]
input [3:0] io_mem_ack_bits_size, // @[mshrs.scala:405:14]
input [1:0] io_mem_ack_bits_source, // @[mshrs.scala:405:14]
input [2:0] io_mem_ack_bits_sink, // @[mshrs.scala:405:14]
input io_mem_ack_bits_denied, // @[mshrs.scala:405:14]
input [63:0] io_mem_ack_bits_data, // @[mshrs.scala:405:14]
input io_mem_ack_bits_corrupt // @[mshrs.scala:405:14]
);
wire io_req_valid_0 = io_req_valid; // @[mshrs.scala:402:7]
wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[mshrs.scala:402:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[mshrs.scala:402:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[mshrs.scala:402:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[mshrs.scala:402:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[mshrs.scala:402:7]
wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[mshrs.scala:402:7]
wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[mshrs.scala:402:7]
wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[mshrs.scala:402:7]
wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[mshrs.scala:402:7]
wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[mshrs.scala:402:7]
wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[mshrs.scala:402:7]
wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[mshrs.scala:402:7]
wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:402:7]
wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:402:7]
wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[mshrs.scala:402:7]
wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[mshrs.scala:402:7]
wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[mshrs.scala:402:7]
wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[mshrs.scala:402:7]
wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[mshrs.scala:402:7]
wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[mshrs.scala:402:7]
wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[mshrs.scala:402:7]
wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[mshrs.scala:402:7]
wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[mshrs.scala:402:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[mshrs.scala:402:7]
wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[mshrs.scala:402:7]
wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[mshrs.scala:402:7]
wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[mshrs.scala:402:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[mshrs.scala:402:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[mshrs.scala:402:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[mshrs.scala:402:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[mshrs.scala:402:7]
wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[mshrs.scala:402:7]
wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[mshrs.scala:402:7]
wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[mshrs.scala:402:7]
wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[mshrs.scala:402:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[mshrs.scala:402:7]
wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[mshrs.scala:402:7]
wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[mshrs.scala:402:7]
wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[mshrs.scala:402:7]
wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[mshrs.scala:402:7]
wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[mshrs.scala:402:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[mshrs.scala:402:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[mshrs.scala:402:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[mshrs.scala:402:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[mshrs.scala:402:7]
wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[mshrs.scala:402:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[mshrs.scala:402:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[mshrs.scala:402:7]
wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[mshrs.scala:402:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[mshrs.scala:402:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[mshrs.scala:402:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[mshrs.scala:402:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[mshrs.scala:402:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[mshrs.scala:402:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[mshrs.scala:402:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[mshrs.scala:402:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[mshrs.scala:402:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[mshrs.scala:402:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[mshrs.scala:402:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[mshrs.scala:402:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[mshrs.scala:402:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[mshrs.scala:402:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[mshrs.scala:402:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[mshrs.scala:402:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[mshrs.scala:402:7]
wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[mshrs.scala:402:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[mshrs.scala:402:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[mshrs.scala:402:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[mshrs.scala:402:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[mshrs.scala:402:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[mshrs.scala:402:7]
wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[mshrs.scala:402:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[mshrs.scala:402:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[mshrs.scala:402:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[mshrs.scala:402:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[mshrs.scala:402:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[mshrs.scala:402:7]
wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[mshrs.scala:402:7]
wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[mshrs.scala:402:7]
wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[mshrs.scala:402:7]
wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[mshrs.scala:402:7]
wire io_req_bits_is_hella_0 = io_req_bits_is_hella; // @[mshrs.scala:402:7]
wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:402:7]
wire io_mem_access_ready_0 = io_mem_access_ready; // @[mshrs.scala:402:7]
wire io_mem_ack_valid_0 = io_mem_ack_valid; // @[mshrs.scala:402:7]
wire [2:0] io_mem_ack_bits_opcode_0 = io_mem_ack_bits_opcode; // @[mshrs.scala:402:7]
wire [1:0] io_mem_ack_bits_param_0 = io_mem_ack_bits_param; // @[mshrs.scala:402:7]
wire [3:0] io_mem_ack_bits_size_0 = io_mem_ack_bits_size; // @[mshrs.scala:402:7]
wire [1:0] io_mem_ack_bits_source_0 = io_mem_ack_bits_source; // @[mshrs.scala:402:7]
wire [2:0] io_mem_ack_bits_sink_0 = io_mem_ack_bits_sink; // @[mshrs.scala:402:7]
wire io_mem_ack_bits_denied_0 = io_mem_ack_bits_denied; // @[mshrs.scala:402:7]
wire [63:0] io_mem_ack_bits_data_0 = io_mem_ack_bits_data; // @[mshrs.scala:402:7]
wire io_mem_ack_bits_corrupt_0 = io_mem_ack_bits_corrupt; // @[mshrs.scala:402:7]
wire io_mem_access_bits_corrupt = 1'h0; // @[mshrs.scala:402:7]
wire get_corrupt = 1'h0; // @[Edges.scala:460:17]
wire _put_legal_T_62 = 1'h0; // @[Parameters.scala:684:29]
wire _put_legal_T_68 = 1'h0; // @[Parameters.scala:684:54]
wire put_corrupt = 1'h0; // @[Edges.scala:480:17]
wire _atomics_WIRE_corrupt = 1'h0; // @[mshrs.scala:439:46]
wire _atomics_legal_T_46 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_52 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_100 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_106 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_154 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_160 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_208 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_214 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_262 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_268 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_316 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_322 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_370 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_376 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_424 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_430 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_478 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_484 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_T_1_corrupt = 1'h0; // @[mshrs.scala:439:75]
wire _atomics_T_3_corrupt = 1'h0; // @[mshrs.scala:439:75]
wire _atomics_T_5_corrupt = 1'h0; // @[mshrs.scala:439:75]
wire _atomics_T_7_corrupt = 1'h0; // @[mshrs.scala:439:75]
wire _atomics_T_9_corrupt = 1'h0; // @[mshrs.scala:439:75]
wire _atomics_T_11_corrupt = 1'h0; // @[mshrs.scala:439:75]
wire _atomics_T_13_corrupt = 1'h0; // @[mshrs.scala:439:75]
wire _atomics_T_15_corrupt = 1'h0; // @[mshrs.scala:439:75]
wire atomics_corrupt = 1'h0; // @[mshrs.scala:439:75]
wire _io_mem_access_bits_T_42_corrupt = 1'h0; // @[mshrs.scala:457:66]
wire _io_mem_access_bits_T_43_corrupt = 1'h0; // @[mshrs.scala:457:29]
wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire [6:0] grant_word_shift = 7'h0; // @[mshrs.scala:417:20]
wire [1:0] get_source = 2'h3; // @[Edges.scala:460:17]
wire [1:0] put_source = 2'h3; // @[Edges.scala:480:17]
wire [1:0] atomics_a_source = 2'h3; // @[Edges.scala:534:17]
wire [1:0] atomics_a_1_source = 2'h3; // @[Edges.scala:534:17]
wire [1:0] atomics_a_2_source = 2'h3; // @[Edges.scala:534:17]
wire [1:0] atomics_a_3_source = 2'h3; // @[Edges.scala:534:17]
wire [1:0] atomics_a_4_source = 2'h3; // @[Edges.scala:517:17]
wire [1:0] atomics_a_5_source = 2'h3; // @[Edges.scala:517:17]
wire [1:0] atomics_a_6_source = 2'h3; // @[Edges.scala:517:17]
wire [1:0] atomics_a_7_source = 2'h3; // @[Edges.scala:517:17]
wire [1:0] atomics_a_8_source = 2'h3; // @[Edges.scala:517:17]
wire [1:0] _io_mem_access_bits_T_42_source = 2'h3; // @[mshrs.scala:457:66]
wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17]
wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[mshrs.scala:439:46]
wire [2:0] _atomics_WIRE_param = 3'h0; // @[mshrs.scala:439:46]
wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17]
wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17]
wire [2:0] _io_mem_access_bits_T_42_param = 3'h0; // @[mshrs.scala:457:66]
wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17]
wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17]
wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17]
wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_54 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_55 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_56 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_57 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_108 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_109 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_110 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_111 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_162 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_163 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_164 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_165 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_216 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_217 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_218 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_219 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_270 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_271 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_272 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_273 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_324 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_325 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_326 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_327 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_378 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_379 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_380 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_381 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_432 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_433 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_434 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_435 = 1'h1; // @[Parameters.scala:684:29]
wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17]
wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17]
wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17]
wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17]
wire [63:0] get_data = 64'h0; // @[Edges.scala:460:17]
wire [63:0] _atomics_WIRE_data = 64'h0; // @[mshrs.scala:439:46]
wire [7:0] _atomics_WIRE_mask = 8'h0; // @[mshrs.scala:439:46]
wire [31:0] _atomics_WIRE_address = 32'h0; // @[mshrs.scala:439:46]
wire [1:0] _atomics_WIRE_source = 2'h0; // @[mshrs.scala:439:46]
wire [3:0] _atomics_WIRE_size = 4'h0; // @[mshrs.scala:439:46]
wire _io_req_ready_T; // @[mshrs.scala:427:25]
wire _io_resp_valid_T_1; // @[mshrs.scala:461:43]
wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _io_mem_access_valid_T; // @[mshrs.scala:456:32]
wire [2:0] _io_mem_access_bits_T_43_opcode; // @[mshrs.scala:457:29]
wire [2:0] _io_mem_access_bits_T_43_param; // @[mshrs.scala:457:29]
wire [3:0] _io_mem_access_bits_T_43_size; // @[mshrs.scala:457:29]
wire [1:0] _io_mem_access_bits_T_43_source; // @[mshrs.scala:457:29]
wire [31:0] _io_mem_access_bits_T_43_address; // @[mshrs.scala:457:29]
wire [7:0] _io_mem_access_bits_T_43_mask; // @[mshrs.scala:457:29]
wire [63:0] _io_mem_access_bits_T_43_data; // @[mshrs.scala:457:29]
wire [63:0] _grant_word_T = io_mem_ack_bits_data_0; // @[mshrs.scala:402:7, :418:10]
wire io_req_ready_0; // @[mshrs.scala:402:7]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:402:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:402:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:402:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:402:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:402:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:402:7]
wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:402:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:402:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:402:7]
wire [39:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:402:7]
wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:402:7]
wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:402:7]
wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:402:7]
wire [7:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:402:7]
wire [2:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:402:7]
wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:402:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_taken_0; // @[mshrs.scala:402:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:402:7]
wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:402:7]
wire [4:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:402:7]
wire [2:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:402:7]
wire [2:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:402:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:402:7]
wire [5:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:402:7]
wire [5:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:402:7]
wire [5:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:402:7]
wire [5:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:402:7]
wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:402:7]
wire [5:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_exception_0; // @[mshrs.scala:402:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:402:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:402:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:402:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:402:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:402:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:402:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:402:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:402:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:402:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:402:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:402:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:402:7]
wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:402:7]
wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:402:7]
wire io_resp_bits_is_hella_0; // @[mshrs.scala:402:7]
wire io_resp_valid_0; // @[mshrs.scala:402:7]
wire [2:0] io_mem_access_bits_opcode_0; // @[mshrs.scala:402:7]
wire [2:0] io_mem_access_bits_param_0; // @[mshrs.scala:402:7]
wire [3:0] io_mem_access_bits_size_0; // @[mshrs.scala:402:7]
wire [1:0] io_mem_access_bits_source_0; // @[mshrs.scala:402:7]
wire [31:0] io_mem_access_bits_address_0; // @[mshrs.scala:402:7]
wire [7:0] io_mem_access_bits_mask_0; // @[mshrs.scala:402:7]
wire [63:0] io_mem_access_bits_data_0; // @[mshrs.scala:402:7]
wire io_mem_access_valid_0; // @[mshrs.scala:402:7]
reg [6:0] req_uop_uopc; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_uopc_0 = req_uop_uopc; // @[mshrs.scala:402:7, :421:16]
reg [31:0] req_uop_inst; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_inst_0 = req_uop_inst; // @[mshrs.scala:402:7, :421:16]
reg [31:0] req_uop_debug_inst; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_debug_inst_0 = req_uop_debug_inst; // @[mshrs.scala:402:7, :421:16]
reg req_uop_is_rvc; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_is_rvc_0 = req_uop_is_rvc; // @[mshrs.scala:402:7, :421:16]
reg [39:0] req_uop_debug_pc; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_debug_pc_0 = req_uop_debug_pc; // @[mshrs.scala:402:7, :421:16]
reg [2:0] req_uop_iq_type; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_iq_type_0 = req_uop_iq_type; // @[mshrs.scala:402:7, :421:16]
reg [9:0] req_uop_fu_code; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_fu_code_0 = req_uop_fu_code; // @[mshrs.scala:402:7, :421:16]
reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ctrl_br_type_0 = req_uop_ctrl_br_type; // @[mshrs.scala:402:7, :421:16]
reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ctrl_op1_sel_0 = req_uop_ctrl_op1_sel; // @[mshrs.scala:402:7, :421:16]
reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ctrl_op2_sel_0 = req_uop_ctrl_op2_sel; // @[mshrs.scala:402:7, :421:16]
reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ctrl_imm_sel_0 = req_uop_ctrl_imm_sel; // @[mshrs.scala:402:7, :421:16]
reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ctrl_op_fcn_0 = req_uop_ctrl_op_fcn; // @[mshrs.scala:402:7, :421:16]
reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ctrl_fcn_dw_0 = req_uop_ctrl_fcn_dw; // @[mshrs.scala:402:7, :421:16]
reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ctrl_csr_cmd_0 = req_uop_ctrl_csr_cmd; // @[mshrs.scala:402:7, :421:16]
reg req_uop_ctrl_is_load; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ctrl_is_load_0 = req_uop_ctrl_is_load; // @[mshrs.scala:402:7, :421:16]
reg req_uop_ctrl_is_sta; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ctrl_is_sta_0 = req_uop_ctrl_is_sta; // @[mshrs.scala:402:7, :421:16]
reg req_uop_ctrl_is_std; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ctrl_is_std_0 = req_uop_ctrl_is_std; // @[mshrs.scala:402:7, :421:16]
reg [1:0] req_uop_iw_state; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_iw_state_0 = req_uop_iw_state; // @[mshrs.scala:402:7, :421:16]
reg req_uop_iw_p1_poisoned; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_iw_p1_poisoned_0 = req_uop_iw_p1_poisoned; // @[mshrs.scala:402:7, :421:16]
reg req_uop_iw_p2_poisoned; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_iw_p2_poisoned_0 = req_uop_iw_p2_poisoned; // @[mshrs.scala:402:7, :421:16]
reg req_uop_is_br; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_is_br_0 = req_uop_is_br; // @[mshrs.scala:402:7, :421:16]
reg req_uop_is_jalr; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_is_jalr_0 = req_uop_is_jalr; // @[mshrs.scala:402:7, :421:16]
reg req_uop_is_jal; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_is_jal_0 = req_uop_is_jal; // @[mshrs.scala:402:7, :421:16]
reg req_uop_is_sfb; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_is_sfb_0 = req_uop_is_sfb; // @[mshrs.scala:402:7, :421:16]
reg [7:0] req_uop_br_mask; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_br_mask_0 = req_uop_br_mask; // @[mshrs.scala:402:7, :421:16]
reg [2:0] req_uop_br_tag; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_br_tag_0 = req_uop_br_tag; // @[mshrs.scala:402:7, :421:16]
reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ftq_idx_0 = req_uop_ftq_idx; // @[mshrs.scala:402:7, :421:16]
reg req_uop_edge_inst; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_edge_inst_0 = req_uop_edge_inst; // @[mshrs.scala:402:7, :421:16]
reg [5:0] req_uop_pc_lob; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_pc_lob_0 = req_uop_pc_lob; // @[mshrs.scala:402:7, :421:16]
reg req_uop_taken; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_taken_0 = req_uop_taken; // @[mshrs.scala:402:7, :421:16]
reg [19:0] req_uop_imm_packed; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_imm_packed_0 = req_uop_imm_packed; // @[mshrs.scala:402:7, :421:16]
reg [11:0] req_uop_csr_addr; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_csr_addr_0 = req_uop_csr_addr; // @[mshrs.scala:402:7, :421:16]
reg [4:0] req_uop_rob_idx; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_rob_idx_0 = req_uop_rob_idx; // @[mshrs.scala:402:7, :421:16]
reg [2:0] req_uop_ldq_idx; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ldq_idx_0 = req_uop_ldq_idx; // @[mshrs.scala:402:7, :421:16]
reg [2:0] req_uop_stq_idx; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_stq_idx_0 = req_uop_stq_idx; // @[mshrs.scala:402:7, :421:16]
reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_rxq_idx_0 = req_uop_rxq_idx; // @[mshrs.scala:402:7, :421:16]
reg [5:0] req_uop_pdst; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_pdst_0 = req_uop_pdst; // @[mshrs.scala:402:7, :421:16]
reg [5:0] req_uop_prs1; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_prs1_0 = req_uop_prs1; // @[mshrs.scala:402:7, :421:16]
reg [5:0] req_uop_prs2; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_prs2_0 = req_uop_prs2; // @[mshrs.scala:402:7, :421:16]
reg [5:0] req_uop_prs3; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_prs3_0 = req_uop_prs3; // @[mshrs.scala:402:7, :421:16]
reg [3:0] req_uop_ppred; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ppred_0 = req_uop_ppred; // @[mshrs.scala:402:7, :421:16]
reg req_uop_prs1_busy; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_prs1_busy_0 = req_uop_prs1_busy; // @[mshrs.scala:402:7, :421:16]
reg req_uop_prs2_busy; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_prs2_busy_0 = req_uop_prs2_busy; // @[mshrs.scala:402:7, :421:16]
reg req_uop_prs3_busy; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_prs3_busy_0 = req_uop_prs3_busy; // @[mshrs.scala:402:7, :421:16]
reg req_uop_ppred_busy; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ppred_busy_0 = req_uop_ppred_busy; // @[mshrs.scala:402:7, :421:16]
reg [5:0] req_uop_stale_pdst; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_stale_pdst_0 = req_uop_stale_pdst; // @[mshrs.scala:402:7, :421:16]
reg req_uop_exception; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_exception_0 = req_uop_exception; // @[mshrs.scala:402:7, :421:16]
reg [63:0] req_uop_exc_cause; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_exc_cause_0 = req_uop_exc_cause; // @[mshrs.scala:402:7, :421:16]
reg req_uop_bypassable; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_bypassable_0 = req_uop_bypassable; // @[mshrs.scala:402:7, :421:16]
reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_mem_cmd_0 = req_uop_mem_cmd; // @[mshrs.scala:402:7, :421:16]
reg [1:0] req_uop_mem_size; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_mem_size_0 = req_uop_mem_size; // @[mshrs.scala:402:7, :421:16]
wire [1:0] size = req_uop_mem_size; // @[AMOALU.scala:11:18]
reg req_uop_mem_signed; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_mem_signed_0 = req_uop_mem_signed; // @[mshrs.scala:402:7, :421:16]
reg req_uop_is_fence; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_is_fence_0 = req_uop_is_fence; // @[mshrs.scala:402:7, :421:16]
reg req_uop_is_fencei; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_is_fencei_0 = req_uop_is_fencei; // @[mshrs.scala:402:7, :421:16]
reg req_uop_is_amo; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_is_amo_0 = req_uop_is_amo; // @[mshrs.scala:402:7, :421:16]
reg req_uop_uses_ldq; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_uses_ldq_0 = req_uop_uses_ldq; // @[mshrs.scala:402:7, :421:16]
reg req_uop_uses_stq; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_uses_stq_0 = req_uop_uses_stq; // @[mshrs.scala:402:7, :421:16]
reg req_uop_is_sys_pc2epc; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_is_sys_pc2epc_0 = req_uop_is_sys_pc2epc; // @[mshrs.scala:402:7, :421:16]
reg req_uop_is_unique; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_is_unique_0 = req_uop_is_unique; // @[mshrs.scala:402:7, :421:16]
reg req_uop_flush_on_commit; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_flush_on_commit_0 = req_uop_flush_on_commit; // @[mshrs.scala:402:7, :421:16]
reg req_uop_ldst_is_rs1; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ldst_is_rs1_0 = req_uop_ldst_is_rs1; // @[mshrs.scala:402:7, :421:16]
reg [5:0] req_uop_ldst; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ldst_0 = req_uop_ldst; // @[mshrs.scala:402:7, :421:16]
reg [5:0] req_uop_lrs1; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_lrs1_0 = req_uop_lrs1; // @[mshrs.scala:402:7, :421:16]
reg [5:0] req_uop_lrs2; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_lrs2_0 = req_uop_lrs2; // @[mshrs.scala:402:7, :421:16]
reg [5:0] req_uop_lrs3; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_lrs3_0 = req_uop_lrs3; // @[mshrs.scala:402:7, :421:16]
reg req_uop_ldst_val; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_ldst_val_0 = req_uop_ldst_val; // @[mshrs.scala:402:7, :421:16]
reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_dst_rtype_0 = req_uop_dst_rtype; // @[mshrs.scala:402:7, :421:16]
reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_lrs1_rtype_0 = req_uop_lrs1_rtype; // @[mshrs.scala:402:7, :421:16]
reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_lrs2_rtype_0 = req_uop_lrs2_rtype; // @[mshrs.scala:402:7, :421:16]
reg req_uop_frs3_en; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_frs3_en_0 = req_uop_frs3_en; // @[mshrs.scala:402:7, :421:16]
reg req_uop_fp_val; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_fp_val_0 = req_uop_fp_val; // @[mshrs.scala:402:7, :421:16]
reg req_uop_fp_single; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_fp_single_0 = req_uop_fp_single; // @[mshrs.scala:402:7, :421:16]
reg req_uop_xcpt_pf_if; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_xcpt_pf_if_0 = req_uop_xcpt_pf_if; // @[mshrs.scala:402:7, :421:16]
reg req_uop_xcpt_ae_if; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_xcpt_ae_if_0 = req_uop_xcpt_ae_if; // @[mshrs.scala:402:7, :421:16]
reg req_uop_xcpt_ma_if; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_xcpt_ma_if_0 = req_uop_xcpt_ma_if; // @[mshrs.scala:402:7, :421:16]
reg req_uop_bp_debug_if; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_bp_debug_if_0 = req_uop_bp_debug_if; // @[mshrs.scala:402:7, :421:16]
reg req_uop_bp_xcpt_if; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_bp_xcpt_if_0 = req_uop_bp_xcpt_if; // @[mshrs.scala:402:7, :421:16]
reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_debug_fsrc_0 = req_uop_debug_fsrc; // @[mshrs.scala:402:7, :421:16]
reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:421:16]
assign io_resp_bits_uop_debug_tsrc_0 = req_uop_debug_tsrc; // @[mshrs.scala:402:7, :421:16]
reg [39:0] req_addr; // @[mshrs.scala:421:16]
wire [39:0] _get_legal_T_14 = req_addr; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_14 = req_addr; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_4 = req_addr; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_58 = req_addr; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_112 = req_addr; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_166 = req_addr; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_220 = req_addr; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_274 = req_addr; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_328 = req_addr; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_382 = req_addr; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_436 = req_addr; // @[Parameters.scala:137:31]
reg [63:0] req_data; // @[mshrs.scala:421:16]
wire [63:0] put_data = req_data; // @[Edges.scala:480:17]
wire [63:0] atomics_a_data = req_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_1_data = req_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_2_data = req_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_3_data = req_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_4_data = req_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_5_data = req_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_6_data = req_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_7_data = req_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_8_data = req_data; // @[Edges.scala:517:17]
reg req_is_hella; // @[mshrs.scala:421:16]
assign io_resp_bits_is_hella_0 = req_is_hella; // @[mshrs.scala:402:7, :421:16]
reg [63:0] grant_word; // @[mshrs.scala:422:23]
reg [1:0] state; // @[mshrs.scala:426:22]
assign _io_req_ready_T = state == 2'h0; // @[mshrs.scala:426:22, :427:25]
assign io_req_ready_0 = _io_req_ready_T; // @[mshrs.scala:402:7, :427:25]
wire [39:0] _GEN = {req_addr[39:14], req_addr[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31]
wire [39:0] _get_legal_T_4; // @[Parameters.scala:137:31]
assign _get_legal_T_4 = _GEN; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_4; // @[Parameters.scala:137:31]
assign _put_legal_T_4 = _GEN; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_6 = _get_legal_T_5 & 41'h9A013000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46]
wire _get_legal_T_8 = _get_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54]
wire _get_legal_T_62 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_16 = _get_legal_T_15 & 41'h9A012000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46]
wire _get_legal_T_18 = _get_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_0 = {req_addr[39:17], req_addr[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [39:0] _get_legal_T_19; // @[Parameters.scala:137:31]
assign _get_legal_T_19 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _get_legal_T_24; // @[Parameters.scala:137:31]
assign _get_legal_T_24 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_63; // @[Parameters.scala:137:31]
assign _put_legal_T_63 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_47; // @[Parameters.scala:137:31]
assign _atomics_legal_T_47 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_101; // @[Parameters.scala:137:31]
assign _atomics_legal_T_101 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_155; // @[Parameters.scala:137:31]
assign _atomics_legal_T_155 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_209; // @[Parameters.scala:137:31]
assign _atomics_legal_T_209 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_263; // @[Parameters.scala:137:31]
assign _atomics_legal_T_263 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_317; // @[Parameters.scala:137:31]
assign _atomics_legal_T_317 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_371; // @[Parameters.scala:137:31]
assign _atomics_legal_T_371 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_425; // @[Parameters.scala:137:31]
assign _atomics_legal_T_425 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_479; // @[Parameters.scala:137:31]
assign _atomics_legal_T_479 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_21 = _get_legal_T_20 & 41'h98013000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46]
wire _get_legal_T_23 = _get_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_26 = _get_legal_T_25 & 41'h9A010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46]
wire _get_legal_T_28 = _get_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_1 = {req_addr[39:26], req_addr[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [39:0] _get_legal_T_29; // @[Parameters.scala:137:31]
assign _get_legal_T_29 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_24; // @[Parameters.scala:137:31]
assign _put_legal_T_24 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_31 = _get_legal_T_30 & 41'h9A010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46]
wire _get_legal_T_33 = _get_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_2 = {req_addr[39:28], req_addr[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [39:0] _get_legal_T_34; // @[Parameters.scala:137:31]
assign _get_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _get_legal_T_39; // @[Parameters.scala:137:31]
assign _get_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_34; // @[Parameters.scala:137:31]
assign _put_legal_T_34 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_39; // @[Parameters.scala:137:31]
assign _put_legal_T_39 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_19; // @[Parameters.scala:137:31]
assign _atomics_legal_T_19 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_24; // @[Parameters.scala:137:31]
assign _atomics_legal_T_24 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_73; // @[Parameters.scala:137:31]
assign _atomics_legal_T_73 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_78; // @[Parameters.scala:137:31]
assign _atomics_legal_T_78 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_127; // @[Parameters.scala:137:31]
assign _atomics_legal_T_127 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_132; // @[Parameters.scala:137:31]
assign _atomics_legal_T_132 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_181; // @[Parameters.scala:137:31]
assign _atomics_legal_T_181 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_186; // @[Parameters.scala:137:31]
assign _atomics_legal_T_186 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_235; // @[Parameters.scala:137:31]
assign _atomics_legal_T_235 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_240; // @[Parameters.scala:137:31]
assign _atomics_legal_T_240 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_289; // @[Parameters.scala:137:31]
assign _atomics_legal_T_289 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_294; // @[Parameters.scala:137:31]
assign _atomics_legal_T_294 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_343; // @[Parameters.scala:137:31]
assign _atomics_legal_T_343 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_348; // @[Parameters.scala:137:31]
assign _atomics_legal_T_348 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_397; // @[Parameters.scala:137:31]
assign _atomics_legal_T_397 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_402; // @[Parameters.scala:137:31]
assign _atomics_legal_T_402 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_451; // @[Parameters.scala:137:31]
assign _atomics_legal_T_451 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_456; // @[Parameters.scala:137:31]
assign _atomics_legal_T_456 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_36 = _get_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46]
wire _get_legal_T_38 = _get_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_41 = _get_legal_T_40 & 41'h9A010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46]
wire _get_legal_T_43 = _get_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_3 = {req_addr[39:29], req_addr[28:0] ^ 29'h10000000}; // @[Parameters.scala:137:31]
wire [39:0] _get_legal_T_44; // @[Parameters.scala:137:31]
assign _get_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_44; // @[Parameters.scala:137:31]
assign _put_legal_T_44 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_29; // @[Parameters.scala:137:31]
assign _atomics_legal_T_29 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_83; // @[Parameters.scala:137:31]
assign _atomics_legal_T_83 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_137; // @[Parameters.scala:137:31]
assign _atomics_legal_T_137 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_191; // @[Parameters.scala:137:31]
assign _atomics_legal_T_191 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_245; // @[Parameters.scala:137:31]
assign _atomics_legal_T_245 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_299; // @[Parameters.scala:137:31]
assign _atomics_legal_T_299 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_353; // @[Parameters.scala:137:31]
assign _atomics_legal_T_353 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_407; // @[Parameters.scala:137:31]
assign _atomics_legal_T_407 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_461; // @[Parameters.scala:137:31]
assign _atomics_legal_T_461 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_46 = _get_legal_T_45 & 41'h9A013000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46]
wire _get_legal_T_48 = _get_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] get_address = req_addr[31:0]; // @[Edges.scala:460:17]
wire [31:0] put_address = req_addr[31:0]; // @[Edges.scala:480:17]
wire [31:0] atomics_a_address = req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_1_address = req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_2_address = req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_3_address = req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_4_address = req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_5_address = req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_6_address = req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_7_address = req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_8_address = req_addr[31:0]; // @[Edges.scala:517:17]
wire [39:0] _GEN_4 = {req_addr[39:32], req_addr[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31]
wire [39:0] _get_legal_T_49; // @[Parameters.scala:137:31]
assign _get_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_49; // @[Parameters.scala:137:31]
assign _put_legal_T_49 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_34; // @[Parameters.scala:137:31]
assign _atomics_legal_T_34 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_88; // @[Parameters.scala:137:31]
assign _atomics_legal_T_88 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_142; // @[Parameters.scala:137:31]
assign _atomics_legal_T_142 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_196; // @[Parameters.scala:137:31]
assign _atomics_legal_T_196 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_250; // @[Parameters.scala:137:31]
assign _atomics_legal_T_250 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_304; // @[Parameters.scala:137:31]
assign _atomics_legal_T_304 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_358; // @[Parameters.scala:137:31]
assign _atomics_legal_T_358 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_412; // @[Parameters.scala:137:31]
assign _atomics_legal_T_412 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_466; // @[Parameters.scala:137:31]
assign _atomics_legal_T_466 = _GEN_4; // @[Parameters.scala:137:31]
wire [40:0] _get_legal_T_50 = {1'h0, _get_legal_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _get_legal_T_51 = _get_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _get_legal_T_52 = _get_legal_T_51; // @[Parameters.scala:137:46]
wire _get_legal_T_53 = _get_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _get_legal_T_54 = _get_legal_T_18 | _get_legal_T_23; // @[Parameters.scala:685:42]
wire _get_legal_T_55 = _get_legal_T_54 | _get_legal_T_28; // @[Parameters.scala:685:42]
wire _get_legal_T_56 = _get_legal_T_55 | _get_legal_T_33; // @[Parameters.scala:685:42]
wire _get_legal_T_57 = _get_legal_T_56 | _get_legal_T_38; // @[Parameters.scala:685:42]
wire _get_legal_T_58 = _get_legal_T_57 | _get_legal_T_43; // @[Parameters.scala:685:42]
wire _get_legal_T_59 = _get_legal_T_58 | _get_legal_T_48; // @[Parameters.scala:685:42]
wire _get_legal_T_60 = _get_legal_T_59 | _get_legal_T_53; // @[Parameters.scala:685:42]
wire _get_legal_T_61 = _get_legal_T_60; // @[Parameters.scala:684:54, :685:42]
wire get_legal = _get_legal_T_62 | _get_legal_T_61; // @[Parameters.scala:684:54, :686:26]
wire [7:0] _get_a_mask_T; // @[Misc.scala:222:10]
wire [3:0] get_size; // @[Edges.scala:460:17]
wire [7:0] get_mask; // @[Edges.scala:460:17]
wire [3:0] _GEN_5 = {2'h0, req_uop_mem_size}; // @[Edges.scala:463:15]
assign get_size = _GEN_5; // @[Edges.scala:460:17, :463:15]
wire [3:0] put_size; // @[Edges.scala:480:17]
assign put_size = _GEN_5; // @[Edges.scala:463:15, :480:17]
wire [3:0] atomics_a_size; // @[Edges.scala:534:17]
assign atomics_a_size = _GEN_5; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17]
assign atomics_a_1_size = _GEN_5; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17]
assign atomics_a_2_size = _GEN_5; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17]
assign atomics_a_3_size = _GEN_5; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17]
assign atomics_a_4_size = _GEN_5; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17]
assign atomics_a_5_size = _GEN_5; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17]
assign atomics_a_6_size = _GEN_5; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17]
assign atomics_a_7_size = _GEN_5; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17]
assign atomics_a_8_size = _GEN_5; // @[Edges.scala:463:15, :517:17]
wire [2:0] _GEN_6 = {1'h0, req_uop_mem_size}; // @[Misc.scala:202:34]
wire [2:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _get_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _put_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_3 = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_6 = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_9 = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_12 = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_15 = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_18 = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_21 = _GEN_6; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_24 = _GEN_6; // @[Misc.scala:202:34]
wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire get_a_mask_sub_sub_sub_0_1 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26]
wire put_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_1 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_2 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_3 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_4 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_5 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_6 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_7 = req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_8 = req_addr[2]; // @[Misc.scala:210:26]
wire _io_resp_bits_data_shifted_T = req_addr[2]; // @[Misc.scala:210:26]
wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26]
wire put_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_1 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_2 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_3 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_4 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_5 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_6 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_7 = req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_8 = req_addr[1]; // @[Misc.scala:210:26]
wire _io_resp_bits_data_shifted_T_3 = req_addr[1]; // @[Misc.scala:210:26]
wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26]
wire put_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_1 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_2 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_3 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_4 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_5 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_6 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_7 = req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_8 = req_addr[0]; // @[Misc.scala:210:26]
wire _io_resp_bits_data_shifted_T_6 = req_addr[0]; // @[Misc.scala:210:26]
wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc = get_a_mask_sub_0_1 | _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_1 = get_a_mask_sub_0_1 | _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_2 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_3 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_4 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_5 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_6 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_7 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] get_a_mask_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] get_a_mask_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] get_a_mask_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] get_a_mask_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10]
assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10]
wire [40:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_6 = _put_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46]
wire _put_legal_T_8 = _put_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54]
wire _put_legal_T_69 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_16 = _put_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46]
wire _put_legal_T_18 = _put_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_7 = {req_addr[39:21], req_addr[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_19; // @[Parameters.scala:137:31]
assign _put_legal_T_19 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_9; // @[Parameters.scala:137:31]
assign _atomics_legal_T_9 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_63; // @[Parameters.scala:137:31]
assign _atomics_legal_T_63 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_117; // @[Parameters.scala:137:31]
assign _atomics_legal_T_117 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_171; // @[Parameters.scala:137:31]
assign _atomics_legal_T_171 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_225; // @[Parameters.scala:137:31]
assign _atomics_legal_T_225 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_279; // @[Parameters.scala:137:31]
assign _atomics_legal_T_279 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_333; // @[Parameters.scala:137:31]
assign _atomics_legal_T_333 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_387; // @[Parameters.scala:137:31]
assign _atomics_legal_T_387 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_441; // @[Parameters.scala:137:31]
assign _atomics_legal_T_441 = _GEN_7; // @[Parameters.scala:137:31]
wire [40:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_21 = _put_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46]
wire _put_legal_T_23 = _put_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_26 = _put_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46]
wire _put_legal_T_28 = _put_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_8 = {req_addr[39:26], req_addr[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31]
wire [39:0] _put_legal_T_29; // @[Parameters.scala:137:31]
assign _put_legal_T_29 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_14; // @[Parameters.scala:137:31]
assign _atomics_legal_T_14 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_68; // @[Parameters.scala:137:31]
assign _atomics_legal_T_68 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_122; // @[Parameters.scala:137:31]
assign _atomics_legal_T_122 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_176; // @[Parameters.scala:137:31]
assign _atomics_legal_T_176 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_230; // @[Parameters.scala:137:31]
assign _atomics_legal_T_230 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_284; // @[Parameters.scala:137:31]
assign _atomics_legal_T_284 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_338; // @[Parameters.scala:137:31]
assign _atomics_legal_T_338 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_392; // @[Parameters.scala:137:31]
assign _atomics_legal_T_392 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _atomics_legal_T_446; // @[Parameters.scala:137:31]
assign _atomics_legal_T_446 = _GEN_8; // @[Parameters.scala:137:31]
wire [40:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_31 = _put_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46]
wire _put_legal_T_33 = _put_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_36 = _put_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46]
wire _put_legal_T_38 = _put_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_40 = {1'h0, _put_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_41 = _put_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_42 = _put_legal_T_41; // @[Parameters.scala:137:46]
wire _put_legal_T_43 = _put_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_45 = {1'h0, _put_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_46 = _put_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_47 = _put_legal_T_46; // @[Parameters.scala:137:46]
wire _put_legal_T_48 = _put_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _put_legal_T_50 = {1'h0, _put_legal_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_51 = _put_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_52 = _put_legal_T_51; // @[Parameters.scala:137:46]
wire _put_legal_T_53 = _put_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_54 = _put_legal_T_18 | _put_legal_T_23; // @[Parameters.scala:685:42]
wire _put_legal_T_55 = _put_legal_T_54 | _put_legal_T_28; // @[Parameters.scala:685:42]
wire _put_legal_T_56 = _put_legal_T_55 | _put_legal_T_33; // @[Parameters.scala:685:42]
wire _put_legal_T_57 = _put_legal_T_56 | _put_legal_T_38; // @[Parameters.scala:685:42]
wire _put_legal_T_58 = _put_legal_T_57 | _put_legal_T_43; // @[Parameters.scala:685:42]
wire _put_legal_T_59 = _put_legal_T_58 | _put_legal_T_48; // @[Parameters.scala:685:42]
wire _put_legal_T_60 = _put_legal_T_59 | _put_legal_T_53; // @[Parameters.scala:685:42]
wire _put_legal_T_61 = _put_legal_T_60; // @[Parameters.scala:684:54, :685:42]
wire [40:0] _put_legal_T_64 = {1'h0, _put_legal_T_63}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _put_legal_T_65 = _put_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _put_legal_T_66 = _put_legal_T_65; // @[Parameters.scala:137:46]
wire _put_legal_T_67 = _put_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_70 = _put_legal_T_69 | _put_legal_T_61; // @[Parameters.scala:684:54, :686:26]
wire put_legal = _put_legal_T_70; // @[Parameters.scala:686:26]
wire [7:0] _put_a_mask_T; // @[Misc.scala:222:10]
wire [7:0] put_mask; // @[Edges.scala:480:17]
wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire put_a_mask_sub_sub_sub_0_1 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc = put_a_mask_sub_0_1 | _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_1 = put_a_mask_sub_0_1 | _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_2 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_3 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_4 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_5 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_6 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_7 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] put_a_mask_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] put_a_mask_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] put_a_mask_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] put_a_mask_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10]
assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46]
wire _atomics_legal_T_8 = _atomics_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46]
wire _atomics_legal_T_13 = _atomics_legal_T_12 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46]
wire _atomics_legal_T_18 = _atomics_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_20 = {1'h0, _atomics_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_21 = _atomics_legal_T_20 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_22 = _atomics_legal_T_21; // @[Parameters.scala:137:46]
wire _atomics_legal_T_23 = _atomics_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_26 = _atomics_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_27 = _atomics_legal_T_26; // @[Parameters.scala:137:46]
wire _atomics_legal_T_28 = _atomics_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_30 = {1'h0, _atomics_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_31 = _atomics_legal_T_30 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_32 = _atomics_legal_T_31; // @[Parameters.scala:137:46]
wire _atomics_legal_T_33 = _atomics_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_35 = {1'h0, _atomics_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_36 = _atomics_legal_T_35 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_37 = _atomics_legal_T_36; // @[Parameters.scala:137:46]
wire _atomics_legal_T_38 = _atomics_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_39 = _atomics_legal_T_8 | _atomics_legal_T_13; // @[Parameters.scala:685:42]
wire _atomics_legal_T_40 = _atomics_legal_T_39 | _atomics_legal_T_18; // @[Parameters.scala:685:42]
wire _atomics_legal_T_41 = _atomics_legal_T_40 | _atomics_legal_T_23; // @[Parameters.scala:685:42]
wire _atomics_legal_T_42 = _atomics_legal_T_41 | _atomics_legal_T_28; // @[Parameters.scala:685:42]
wire _atomics_legal_T_43 = _atomics_legal_T_42 | _atomics_legal_T_33; // @[Parameters.scala:685:42]
wire _atomics_legal_T_44 = _atomics_legal_T_43 | _atomics_legal_T_38; // @[Parameters.scala:685:42]
wire _atomics_legal_T_45 = _atomics_legal_T_44; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_53 = _atomics_legal_T_45; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_48 = {1'h0, _atomics_legal_T_47}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_49 = _atomics_legal_T_48 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_50 = _atomics_legal_T_49; // @[Parameters.scala:137:46]
wire _atomics_legal_T_51 = _atomics_legal_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal = _atomics_legal_T_53; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T; // @[Misc.scala:222:10]
wire [7:0] atomics_a_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10]
assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_59 = {1'h0, _atomics_legal_T_58}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_60 = _atomics_legal_T_59 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_61 = _atomics_legal_T_60; // @[Parameters.scala:137:46]
wire _atomics_legal_T_62 = _atomics_legal_T_61 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_64 = {1'h0, _atomics_legal_T_63}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_65 = _atomics_legal_T_64 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_66 = _atomics_legal_T_65; // @[Parameters.scala:137:46]
wire _atomics_legal_T_67 = _atomics_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_69 = {1'h0, _atomics_legal_T_68}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_70 = _atomics_legal_T_69 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_71 = _atomics_legal_T_70; // @[Parameters.scala:137:46]
wire _atomics_legal_T_72 = _atomics_legal_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_74 = {1'h0, _atomics_legal_T_73}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_75 = _atomics_legal_T_74 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_76 = _atomics_legal_T_75; // @[Parameters.scala:137:46]
wire _atomics_legal_T_77 = _atomics_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_79 = {1'h0, _atomics_legal_T_78}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_80 = _atomics_legal_T_79 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:137:46]
wire _atomics_legal_T_82 = _atomics_legal_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46]
wire _atomics_legal_T_87 = _atomics_legal_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_89 = {1'h0, _atomics_legal_T_88}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_90 = _atomics_legal_T_89 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_91 = _atomics_legal_T_90; // @[Parameters.scala:137:46]
wire _atomics_legal_T_92 = _atomics_legal_T_91 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_93 = _atomics_legal_T_62 | _atomics_legal_T_67; // @[Parameters.scala:685:42]
wire _atomics_legal_T_94 = _atomics_legal_T_93 | _atomics_legal_T_72; // @[Parameters.scala:685:42]
wire _atomics_legal_T_95 = _atomics_legal_T_94 | _atomics_legal_T_77; // @[Parameters.scala:685:42]
wire _atomics_legal_T_96 = _atomics_legal_T_95 | _atomics_legal_T_82; // @[Parameters.scala:685:42]
wire _atomics_legal_T_97 = _atomics_legal_T_96 | _atomics_legal_T_87; // @[Parameters.scala:685:42]
wire _atomics_legal_T_98 = _atomics_legal_T_97 | _atomics_legal_T_92; // @[Parameters.scala:685:42]
wire _atomics_legal_T_99 = _atomics_legal_T_98; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_107 = _atomics_legal_T_99; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_102 = {1'h0, _atomics_legal_T_101}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_103 = _atomics_legal_T_102 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_104 = _atomics_legal_T_103; // @[Parameters.scala:137:46]
wire _atomics_legal_T_105 = _atomics_legal_T_104 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_1 = _atomics_legal_T_107; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10]
wire [7:0] atomics_a_1_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_1 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_8 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size_1 & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_8 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_9 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size_1 & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_9 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_10 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size_1 & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_10 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_11 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size_1 & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_11 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_12 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size_1 & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_12 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_13 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size_1 & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_13 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_14 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size_1 & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_14 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_15 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size_1 & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_15 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10]
assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_113 = {1'h0, _atomics_legal_T_112}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_114 = _atomics_legal_T_113 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_115 = _atomics_legal_T_114; // @[Parameters.scala:137:46]
wire _atomics_legal_T_116 = _atomics_legal_T_115 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_118 = {1'h0, _atomics_legal_T_117}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_119 = _atomics_legal_T_118 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_120 = _atomics_legal_T_119; // @[Parameters.scala:137:46]
wire _atomics_legal_T_121 = _atomics_legal_T_120 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_123 = {1'h0, _atomics_legal_T_122}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_124 = _atomics_legal_T_123 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_125 = _atomics_legal_T_124; // @[Parameters.scala:137:46]
wire _atomics_legal_T_126 = _atomics_legal_T_125 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_128 = {1'h0, _atomics_legal_T_127}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_129 = _atomics_legal_T_128 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_130 = _atomics_legal_T_129; // @[Parameters.scala:137:46]
wire _atomics_legal_T_131 = _atomics_legal_T_130 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_133 = {1'h0, _atomics_legal_T_132}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_134 = _atomics_legal_T_133 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_135 = _atomics_legal_T_134; // @[Parameters.scala:137:46]
wire _atomics_legal_T_136 = _atomics_legal_T_135 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_138 = {1'h0, _atomics_legal_T_137}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_139 = _atomics_legal_T_138 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_140 = _atomics_legal_T_139; // @[Parameters.scala:137:46]
wire _atomics_legal_T_141 = _atomics_legal_T_140 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_143 = {1'h0, _atomics_legal_T_142}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_144 = _atomics_legal_T_143 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_145 = _atomics_legal_T_144; // @[Parameters.scala:137:46]
wire _atomics_legal_T_146 = _atomics_legal_T_145 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_147 = _atomics_legal_T_116 | _atomics_legal_T_121; // @[Parameters.scala:685:42]
wire _atomics_legal_T_148 = _atomics_legal_T_147 | _atomics_legal_T_126; // @[Parameters.scala:685:42]
wire _atomics_legal_T_149 = _atomics_legal_T_148 | _atomics_legal_T_131; // @[Parameters.scala:685:42]
wire _atomics_legal_T_150 = _atomics_legal_T_149 | _atomics_legal_T_136; // @[Parameters.scala:685:42]
wire _atomics_legal_T_151 = _atomics_legal_T_150 | _atomics_legal_T_141; // @[Parameters.scala:685:42]
wire _atomics_legal_T_152 = _atomics_legal_T_151 | _atomics_legal_T_146; // @[Parameters.scala:685:42]
wire _atomics_legal_T_153 = _atomics_legal_T_152; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_161 = _atomics_legal_T_153; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_156 = {1'h0, _atomics_legal_T_155}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_157 = _atomics_legal_T_156 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_158 = _atomics_legal_T_157; // @[Parameters.scala:137:46]
wire _atomics_legal_T_159 = _atomics_legal_T_158 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_2 = _atomics_legal_T_161; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10]
wire [7:0] atomics_a_2_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_2 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_2 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_2 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_2 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_2 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_2 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_2 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_2 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_2 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10]
assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_167 = {1'h0, _atomics_legal_T_166}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_168 = _atomics_legal_T_167 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_169 = _atomics_legal_T_168; // @[Parameters.scala:137:46]
wire _atomics_legal_T_170 = _atomics_legal_T_169 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_172 = {1'h0, _atomics_legal_T_171}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_173 = _atomics_legal_T_172 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_174 = _atomics_legal_T_173; // @[Parameters.scala:137:46]
wire _atomics_legal_T_175 = _atomics_legal_T_174 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_177 = {1'h0, _atomics_legal_T_176}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_178 = _atomics_legal_T_177 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_179 = _atomics_legal_T_178; // @[Parameters.scala:137:46]
wire _atomics_legal_T_180 = _atomics_legal_T_179 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_182 = {1'h0, _atomics_legal_T_181}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_183 = _atomics_legal_T_182 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_184 = _atomics_legal_T_183; // @[Parameters.scala:137:46]
wire _atomics_legal_T_185 = _atomics_legal_T_184 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_187 = {1'h0, _atomics_legal_T_186}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_188 = _atomics_legal_T_187 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_189 = _atomics_legal_T_188; // @[Parameters.scala:137:46]
wire _atomics_legal_T_190 = _atomics_legal_T_189 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_192 = {1'h0, _atomics_legal_T_191}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_193 = _atomics_legal_T_192 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_194 = _atomics_legal_T_193; // @[Parameters.scala:137:46]
wire _atomics_legal_T_195 = _atomics_legal_T_194 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_197 = {1'h0, _atomics_legal_T_196}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_198 = _atomics_legal_T_197 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_199 = _atomics_legal_T_198; // @[Parameters.scala:137:46]
wire _atomics_legal_T_200 = _atomics_legal_T_199 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_201 = _atomics_legal_T_170 | _atomics_legal_T_175; // @[Parameters.scala:685:42]
wire _atomics_legal_T_202 = _atomics_legal_T_201 | _atomics_legal_T_180; // @[Parameters.scala:685:42]
wire _atomics_legal_T_203 = _atomics_legal_T_202 | _atomics_legal_T_185; // @[Parameters.scala:685:42]
wire _atomics_legal_T_204 = _atomics_legal_T_203 | _atomics_legal_T_190; // @[Parameters.scala:685:42]
wire _atomics_legal_T_205 = _atomics_legal_T_204 | _atomics_legal_T_195; // @[Parameters.scala:685:42]
wire _atomics_legal_T_206 = _atomics_legal_T_205 | _atomics_legal_T_200; // @[Parameters.scala:685:42]
wire _atomics_legal_T_207 = _atomics_legal_T_206; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_215 = _atomics_legal_T_207; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_210 = {1'h0, _atomics_legal_T_209}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_211 = _atomics_legal_T_210 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_212 = _atomics_legal_T_211; // @[Parameters.scala:137:46]
wire _atomics_legal_T_213 = _atomics_legal_T_212 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_3 = _atomics_legal_T_215; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10]
wire [7:0] atomics_a_3_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_3 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_24 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_3 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_24 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_25 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_3 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_25 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_26 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_3 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_26 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_27 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_3 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_27 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_28 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_3 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_28 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_29 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_3 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_29 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_30 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_3 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_30 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_31 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_3 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_31 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10]
assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_221 = {1'h0, _atomics_legal_T_220}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_222 = _atomics_legal_T_221 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_223 = _atomics_legal_T_222; // @[Parameters.scala:137:46]
wire _atomics_legal_T_224 = _atomics_legal_T_223 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_226 = {1'h0, _atomics_legal_T_225}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_227 = _atomics_legal_T_226 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_228 = _atomics_legal_T_227; // @[Parameters.scala:137:46]
wire _atomics_legal_T_229 = _atomics_legal_T_228 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_231 = {1'h0, _atomics_legal_T_230}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_232 = _atomics_legal_T_231 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_233 = _atomics_legal_T_232; // @[Parameters.scala:137:46]
wire _atomics_legal_T_234 = _atomics_legal_T_233 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_236 = {1'h0, _atomics_legal_T_235}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_237 = _atomics_legal_T_236 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_238 = _atomics_legal_T_237; // @[Parameters.scala:137:46]
wire _atomics_legal_T_239 = _atomics_legal_T_238 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_241 = {1'h0, _atomics_legal_T_240}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_242 = _atomics_legal_T_241 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_243 = _atomics_legal_T_242; // @[Parameters.scala:137:46]
wire _atomics_legal_T_244 = _atomics_legal_T_243 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_246 = {1'h0, _atomics_legal_T_245}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_247 = _atomics_legal_T_246 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_248 = _atomics_legal_T_247; // @[Parameters.scala:137:46]
wire _atomics_legal_T_249 = _atomics_legal_T_248 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_251 = {1'h0, _atomics_legal_T_250}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_252 = _atomics_legal_T_251 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_253 = _atomics_legal_T_252; // @[Parameters.scala:137:46]
wire _atomics_legal_T_254 = _atomics_legal_T_253 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_255 = _atomics_legal_T_224 | _atomics_legal_T_229; // @[Parameters.scala:685:42]
wire _atomics_legal_T_256 = _atomics_legal_T_255 | _atomics_legal_T_234; // @[Parameters.scala:685:42]
wire _atomics_legal_T_257 = _atomics_legal_T_256 | _atomics_legal_T_239; // @[Parameters.scala:685:42]
wire _atomics_legal_T_258 = _atomics_legal_T_257 | _atomics_legal_T_244; // @[Parameters.scala:685:42]
wire _atomics_legal_T_259 = _atomics_legal_T_258 | _atomics_legal_T_249; // @[Parameters.scala:685:42]
wire _atomics_legal_T_260 = _atomics_legal_T_259 | _atomics_legal_T_254; // @[Parameters.scala:685:42]
wire _atomics_legal_T_261 = _atomics_legal_T_260; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_269 = _atomics_legal_T_261; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_264 = {1'h0, _atomics_legal_T_263}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_265 = _atomics_legal_T_264 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_266 = _atomics_legal_T_265; // @[Parameters.scala:137:46]
wire _atomics_legal_T_267 = _atomics_legal_T_266 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_4 = _atomics_legal_T_269; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10]
wire [7:0] atomics_a_4_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_4 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_4 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_4 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_4 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_4 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_4 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_4 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_4 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_4 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10]
assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_275 = {1'h0, _atomics_legal_T_274}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_276 = _atomics_legal_T_275 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_277 = _atomics_legal_T_276; // @[Parameters.scala:137:46]
wire _atomics_legal_T_278 = _atomics_legal_T_277 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_280 = {1'h0, _atomics_legal_T_279}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_281 = _atomics_legal_T_280 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_282 = _atomics_legal_T_281; // @[Parameters.scala:137:46]
wire _atomics_legal_T_283 = _atomics_legal_T_282 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_285 = {1'h0, _atomics_legal_T_284}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_286 = _atomics_legal_T_285 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_287 = _atomics_legal_T_286; // @[Parameters.scala:137:46]
wire _atomics_legal_T_288 = _atomics_legal_T_287 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_290 = {1'h0, _atomics_legal_T_289}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_291 = _atomics_legal_T_290 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_292 = _atomics_legal_T_291; // @[Parameters.scala:137:46]
wire _atomics_legal_T_293 = _atomics_legal_T_292 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_295 = {1'h0, _atomics_legal_T_294}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_296 = _atomics_legal_T_295 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_297 = _atomics_legal_T_296; // @[Parameters.scala:137:46]
wire _atomics_legal_T_298 = _atomics_legal_T_297 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_300 = {1'h0, _atomics_legal_T_299}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_301 = _atomics_legal_T_300 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_302 = _atomics_legal_T_301; // @[Parameters.scala:137:46]
wire _atomics_legal_T_303 = _atomics_legal_T_302 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_305 = {1'h0, _atomics_legal_T_304}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_306 = _atomics_legal_T_305 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_307 = _atomics_legal_T_306; // @[Parameters.scala:137:46]
wire _atomics_legal_T_308 = _atomics_legal_T_307 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_309 = _atomics_legal_T_278 | _atomics_legal_T_283; // @[Parameters.scala:685:42]
wire _atomics_legal_T_310 = _atomics_legal_T_309 | _atomics_legal_T_288; // @[Parameters.scala:685:42]
wire _atomics_legal_T_311 = _atomics_legal_T_310 | _atomics_legal_T_293; // @[Parameters.scala:685:42]
wire _atomics_legal_T_312 = _atomics_legal_T_311 | _atomics_legal_T_298; // @[Parameters.scala:685:42]
wire _atomics_legal_T_313 = _atomics_legal_T_312 | _atomics_legal_T_303; // @[Parameters.scala:685:42]
wire _atomics_legal_T_314 = _atomics_legal_T_313 | _atomics_legal_T_308; // @[Parameters.scala:685:42]
wire _atomics_legal_T_315 = _atomics_legal_T_314; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_323 = _atomics_legal_T_315; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_318 = {1'h0, _atomics_legal_T_317}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_319 = _atomics_legal_T_318 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_320 = _atomics_legal_T_319; // @[Parameters.scala:137:46]
wire _atomics_legal_T_321 = _atomics_legal_T_320 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_5 = _atomics_legal_T_323; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10]
wire [7:0] atomics_a_5_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_5 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_40 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_5 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_40 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_41 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_5 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_41 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_42 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_5 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_42 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_43 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_5 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_43 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_44 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_5 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_44 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_45 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_5 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_45 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_46 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_5 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_46 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_47 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_5 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_47 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10]
assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_329 = {1'h0, _atomics_legal_T_328}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_330 = _atomics_legal_T_329 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_331 = _atomics_legal_T_330; // @[Parameters.scala:137:46]
wire _atomics_legal_T_332 = _atomics_legal_T_331 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_334 = {1'h0, _atomics_legal_T_333}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_335 = _atomics_legal_T_334 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_336 = _atomics_legal_T_335; // @[Parameters.scala:137:46]
wire _atomics_legal_T_337 = _atomics_legal_T_336 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_339 = {1'h0, _atomics_legal_T_338}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_340 = _atomics_legal_T_339 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_341 = _atomics_legal_T_340; // @[Parameters.scala:137:46]
wire _atomics_legal_T_342 = _atomics_legal_T_341 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_344 = {1'h0, _atomics_legal_T_343}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_345 = _atomics_legal_T_344 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_346 = _atomics_legal_T_345; // @[Parameters.scala:137:46]
wire _atomics_legal_T_347 = _atomics_legal_T_346 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_349 = {1'h0, _atomics_legal_T_348}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_350 = _atomics_legal_T_349 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_351 = _atomics_legal_T_350; // @[Parameters.scala:137:46]
wire _atomics_legal_T_352 = _atomics_legal_T_351 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_354 = {1'h0, _atomics_legal_T_353}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_355 = _atomics_legal_T_354 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_356 = _atomics_legal_T_355; // @[Parameters.scala:137:46]
wire _atomics_legal_T_357 = _atomics_legal_T_356 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_359 = {1'h0, _atomics_legal_T_358}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_360 = _atomics_legal_T_359 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_361 = _atomics_legal_T_360; // @[Parameters.scala:137:46]
wire _atomics_legal_T_362 = _atomics_legal_T_361 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_363 = _atomics_legal_T_332 | _atomics_legal_T_337; // @[Parameters.scala:685:42]
wire _atomics_legal_T_364 = _atomics_legal_T_363 | _atomics_legal_T_342; // @[Parameters.scala:685:42]
wire _atomics_legal_T_365 = _atomics_legal_T_364 | _atomics_legal_T_347; // @[Parameters.scala:685:42]
wire _atomics_legal_T_366 = _atomics_legal_T_365 | _atomics_legal_T_352; // @[Parameters.scala:685:42]
wire _atomics_legal_T_367 = _atomics_legal_T_366 | _atomics_legal_T_357; // @[Parameters.scala:685:42]
wire _atomics_legal_T_368 = _atomics_legal_T_367 | _atomics_legal_T_362; // @[Parameters.scala:685:42]
wire _atomics_legal_T_369 = _atomics_legal_T_368; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_377 = _atomics_legal_T_369; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_372 = {1'h0, _atomics_legal_T_371}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_373 = _atomics_legal_T_372 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_374 = _atomics_legal_T_373; // @[Parameters.scala:137:46]
wire _atomics_legal_T_375 = _atomics_legal_T_374 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_6 = _atomics_legal_T_377; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10]
wire [7:0] atomics_a_6_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_6 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_6 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_6 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_6 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_6 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_6 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_6 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_6 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_6 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10]
assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_383 = {1'h0, _atomics_legal_T_382}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_384 = _atomics_legal_T_383 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_385 = _atomics_legal_T_384; // @[Parameters.scala:137:46]
wire _atomics_legal_T_386 = _atomics_legal_T_385 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_388 = {1'h0, _atomics_legal_T_387}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_389 = _atomics_legal_T_388 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_390 = _atomics_legal_T_389; // @[Parameters.scala:137:46]
wire _atomics_legal_T_391 = _atomics_legal_T_390 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_393 = {1'h0, _atomics_legal_T_392}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_394 = _atomics_legal_T_393 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_395 = _atomics_legal_T_394; // @[Parameters.scala:137:46]
wire _atomics_legal_T_396 = _atomics_legal_T_395 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_398 = {1'h0, _atomics_legal_T_397}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_399 = _atomics_legal_T_398 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_400 = _atomics_legal_T_399; // @[Parameters.scala:137:46]
wire _atomics_legal_T_401 = _atomics_legal_T_400 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_403 = {1'h0, _atomics_legal_T_402}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_404 = _atomics_legal_T_403 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_405 = _atomics_legal_T_404; // @[Parameters.scala:137:46]
wire _atomics_legal_T_406 = _atomics_legal_T_405 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_408 = {1'h0, _atomics_legal_T_407}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_409 = _atomics_legal_T_408 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_410 = _atomics_legal_T_409; // @[Parameters.scala:137:46]
wire _atomics_legal_T_411 = _atomics_legal_T_410 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_413 = {1'h0, _atomics_legal_T_412}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_414 = _atomics_legal_T_413 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_415 = _atomics_legal_T_414; // @[Parameters.scala:137:46]
wire _atomics_legal_T_416 = _atomics_legal_T_415 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_417 = _atomics_legal_T_386 | _atomics_legal_T_391; // @[Parameters.scala:685:42]
wire _atomics_legal_T_418 = _atomics_legal_T_417 | _atomics_legal_T_396; // @[Parameters.scala:685:42]
wire _atomics_legal_T_419 = _atomics_legal_T_418 | _atomics_legal_T_401; // @[Parameters.scala:685:42]
wire _atomics_legal_T_420 = _atomics_legal_T_419 | _atomics_legal_T_406; // @[Parameters.scala:685:42]
wire _atomics_legal_T_421 = _atomics_legal_T_420 | _atomics_legal_T_411; // @[Parameters.scala:685:42]
wire _atomics_legal_T_422 = _atomics_legal_T_421 | _atomics_legal_T_416; // @[Parameters.scala:685:42]
wire _atomics_legal_T_423 = _atomics_legal_T_422; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_431 = _atomics_legal_T_423; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_426 = {1'h0, _atomics_legal_T_425}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_427 = _atomics_legal_T_426 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_428 = _atomics_legal_T_427; // @[Parameters.scala:137:46]
wire _atomics_legal_T_429 = _atomics_legal_T_428 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_7 = _atomics_legal_T_431; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10]
wire [7:0] atomics_a_7_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_7 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_56 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_7 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_56 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_57 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_7 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_57 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_58 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_7 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_58 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_59 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_7 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_59 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_60 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_7 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_60 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_61 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_7 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_61 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_62 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_7 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_62 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_63 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_7 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_63 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10]
assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10]
wire [40:0] _atomics_legal_T_437 = {1'h0, _atomics_legal_T_436}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_438 = _atomics_legal_T_437 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_439 = _atomics_legal_T_438; // @[Parameters.scala:137:46]
wire _atomics_legal_T_440 = _atomics_legal_T_439 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_442 = {1'h0, _atomics_legal_T_441}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_443 = _atomics_legal_T_442 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_444 = _atomics_legal_T_443; // @[Parameters.scala:137:46]
wire _atomics_legal_T_445 = _atomics_legal_T_444 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_447 = {1'h0, _atomics_legal_T_446}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_448 = _atomics_legal_T_447 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_449 = _atomics_legal_T_448; // @[Parameters.scala:137:46]
wire _atomics_legal_T_450 = _atomics_legal_T_449 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_452 = {1'h0, _atomics_legal_T_451}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_453 = _atomics_legal_T_452 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_454 = _atomics_legal_T_453; // @[Parameters.scala:137:46]
wire _atomics_legal_T_455 = _atomics_legal_T_454 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_457 = {1'h0, _atomics_legal_T_456}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_458 = _atomics_legal_T_457 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_459 = _atomics_legal_T_458; // @[Parameters.scala:137:46]
wire _atomics_legal_T_460 = _atomics_legal_T_459 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_462 = {1'h0, _atomics_legal_T_461}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_463 = _atomics_legal_T_462 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_464 = _atomics_legal_T_463; // @[Parameters.scala:137:46]
wire _atomics_legal_T_465 = _atomics_legal_T_464 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _atomics_legal_T_467 = {1'h0, _atomics_legal_T_466}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_468 = _atomics_legal_T_467 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_469 = _atomics_legal_T_468; // @[Parameters.scala:137:46]
wire _atomics_legal_T_470 = _atomics_legal_T_469 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_471 = _atomics_legal_T_440 | _atomics_legal_T_445; // @[Parameters.scala:685:42]
wire _atomics_legal_T_472 = _atomics_legal_T_471 | _atomics_legal_T_450; // @[Parameters.scala:685:42]
wire _atomics_legal_T_473 = _atomics_legal_T_472 | _atomics_legal_T_455; // @[Parameters.scala:685:42]
wire _atomics_legal_T_474 = _atomics_legal_T_473 | _atomics_legal_T_460; // @[Parameters.scala:685:42]
wire _atomics_legal_T_475 = _atomics_legal_T_474 | _atomics_legal_T_465; // @[Parameters.scala:685:42]
wire _atomics_legal_T_476 = _atomics_legal_T_475 | _atomics_legal_T_470; // @[Parameters.scala:685:42]
wire _atomics_legal_T_477 = _atomics_legal_T_476; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_485 = _atomics_legal_T_477; // @[Parameters.scala:684:54, :686:26]
wire [40:0] _atomics_legal_T_480 = {1'h0, _atomics_legal_T_479}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _atomics_legal_T_481 = _atomics_legal_T_480 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _atomics_legal_T_482 = _atomics_legal_T_481; // @[Parameters.scala:137:46]
wire _atomics_legal_T_483 = _atomics_legal_T_482 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire atomics_legal_8 = _atomics_legal_T_485; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10]
wire [7:0] atomics_a_8_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_8 = &req_uop_mem_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_8 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_8 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_8 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_8 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_8 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_8 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_8 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_8 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10]
assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10]
wire _T_17 = req_uop_mem_cmd == 5'h4; // @[mshrs.scala:421:16, :439:75]
wire _atomics_T; // @[mshrs.scala:439:75]
assign _atomics_T = _T_17; // @[mshrs.scala:439:75]
wire _io_mem_access_bits_T; // @[package.scala:16:47]
assign _io_mem_access_bits_T = _T_17; // @[package.scala:16:47]
wire _io_mem_access_bits_T_24; // @[package.scala:16:47]
assign _io_mem_access_bits_T_24 = _T_17; // @[package.scala:16:47]
wire _send_resp_T_7; // @[package.scala:16:47]
assign _send_resp_T_7 = _T_17; // @[package.scala:16:47]
wire [2:0] _GEN_9 = _atomics_T ? 3'h3 : 3'h0; // @[mshrs.scala:439:75]
wire [2:0] _atomics_T_1_opcode; // @[mshrs.scala:439:75]
assign _atomics_T_1_opcode = _GEN_9; // @[mshrs.scala:439:75]
wire [2:0] _atomics_T_1_param; // @[mshrs.scala:439:75]
assign _atomics_T_1_param = _GEN_9; // @[mshrs.scala:439:75]
wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17]
wire [1:0] _atomics_T_1_source = {2{_atomics_T}}; // @[mshrs.scala:439:75]
wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 8'h0; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 64'h0; // @[Edges.scala:534:17]
wire _T_18 = req_uop_mem_cmd == 5'h9; // @[mshrs.scala:421:16, :439:75]
wire _atomics_T_2; // @[mshrs.scala:439:75]
assign _atomics_T_2 = _T_18; // @[mshrs.scala:439:75]
wire _io_mem_access_bits_T_1; // @[package.scala:16:47]
assign _io_mem_access_bits_T_1 = _T_18; // @[package.scala:16:47]
wire _io_mem_access_bits_T_25; // @[package.scala:16:47]
assign _io_mem_access_bits_T_25 = _T_18; // @[package.scala:16:47]
wire _send_resp_T_8; // @[package.scala:16:47]
assign _send_resp_T_8 = _T_18; // @[package.scala:16:47]
wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[mshrs.scala:439:75]
wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[mshrs.scala:439:75]
wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17]
wire [1:0] _atomics_T_3_source = _atomics_T_2 ? 2'h3 : _atomics_T_1_source; // @[mshrs.scala:439:75]
wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17]
wire _T_19 = req_uop_mem_cmd == 5'hA; // @[mshrs.scala:421:16, :439:75]
wire _atomics_T_4; // @[mshrs.scala:439:75]
assign _atomics_T_4 = _T_19; // @[mshrs.scala:439:75]
wire _io_mem_access_bits_T_2; // @[package.scala:16:47]
assign _io_mem_access_bits_T_2 = _T_19; // @[package.scala:16:47]
wire _io_mem_access_bits_T_26; // @[package.scala:16:47]
assign _io_mem_access_bits_T_26 = _T_19; // @[package.scala:16:47]
wire _send_resp_T_9; // @[package.scala:16:47]
assign _send_resp_T_9 = _T_19; // @[package.scala:16:47]
wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[mshrs.scala:439:75]
wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[mshrs.scala:439:75]
wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17]
wire [1:0] _atomics_T_5_source = _atomics_T_4 ? 2'h3 : _atomics_T_3_source; // @[mshrs.scala:439:75]
wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17]
wire _T_20 = req_uop_mem_cmd == 5'hB; // @[mshrs.scala:421:16, :439:75]
wire _atomics_T_6; // @[mshrs.scala:439:75]
assign _atomics_T_6 = _T_20; // @[mshrs.scala:439:75]
wire _io_mem_access_bits_T_3; // @[package.scala:16:47]
assign _io_mem_access_bits_T_3 = _T_20; // @[package.scala:16:47]
wire _io_mem_access_bits_T_27; // @[package.scala:16:47]
assign _io_mem_access_bits_T_27 = _T_20; // @[package.scala:16:47]
wire _send_resp_T_10; // @[package.scala:16:47]
assign _send_resp_T_10 = _T_20; // @[package.scala:16:47]
wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[mshrs.scala:439:75]
wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[mshrs.scala:439:75]
wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17]
wire [1:0] _atomics_T_7_source = _atomics_T_6 ? 2'h3 : _atomics_T_5_source; // @[mshrs.scala:439:75]
wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17]
wire _T_24 = req_uop_mem_cmd == 5'h8; // @[mshrs.scala:421:16, :439:75]
wire _atomics_T_8; // @[mshrs.scala:439:75]
assign _atomics_T_8 = _T_24; // @[mshrs.scala:439:75]
wire _io_mem_access_bits_T_7; // @[package.scala:16:47]
assign _io_mem_access_bits_T_7 = _T_24; // @[package.scala:16:47]
wire _io_mem_access_bits_T_31; // @[package.scala:16:47]
assign _io_mem_access_bits_T_31 = _T_24; // @[package.scala:16:47]
wire _send_resp_T_14; // @[package.scala:16:47]
assign _send_resp_T_14 = _T_24; // @[package.scala:16:47]
wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[mshrs.scala:439:75]
wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[mshrs.scala:439:75]
wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17]
wire [1:0] _atomics_T_9_source = _atomics_T_8 ? 2'h3 : _atomics_T_7_source; // @[mshrs.scala:439:75]
wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17]
wire _T_25 = req_uop_mem_cmd == 5'hC; // @[mshrs.scala:421:16, :439:75]
wire _atomics_T_10; // @[mshrs.scala:439:75]
assign _atomics_T_10 = _T_25; // @[mshrs.scala:439:75]
wire _io_mem_access_bits_T_8; // @[package.scala:16:47]
assign _io_mem_access_bits_T_8 = _T_25; // @[package.scala:16:47]
wire _io_mem_access_bits_T_32; // @[package.scala:16:47]
assign _io_mem_access_bits_T_32 = _T_25; // @[package.scala:16:47]
wire _send_resp_T_15; // @[package.scala:16:47]
assign _send_resp_T_15 = _T_25; // @[package.scala:16:47]
wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[mshrs.scala:439:75]
wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[mshrs.scala:439:75]
wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17]
wire [1:0] _atomics_T_11_source = _atomics_T_10 ? 2'h3 : _atomics_T_9_source; // @[mshrs.scala:439:75]
wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17]
wire _T_26 = req_uop_mem_cmd == 5'hD; // @[mshrs.scala:421:16, :439:75]
wire _atomics_T_12; // @[mshrs.scala:439:75]
assign _atomics_T_12 = _T_26; // @[mshrs.scala:439:75]
wire _io_mem_access_bits_T_9; // @[package.scala:16:47]
assign _io_mem_access_bits_T_9 = _T_26; // @[package.scala:16:47]
wire _io_mem_access_bits_T_33; // @[package.scala:16:47]
assign _io_mem_access_bits_T_33 = _T_26; // @[package.scala:16:47]
wire _send_resp_T_16; // @[package.scala:16:47]
assign _send_resp_T_16 = _T_26; // @[package.scala:16:47]
wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[mshrs.scala:439:75]
wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[mshrs.scala:439:75]
wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17]
wire [1:0] _atomics_T_13_source = _atomics_T_12 ? 2'h3 : _atomics_T_11_source; // @[mshrs.scala:439:75]
wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17]
wire _T_27 = req_uop_mem_cmd == 5'hE; // @[mshrs.scala:421:16, :439:75]
wire _atomics_T_14; // @[mshrs.scala:439:75]
assign _atomics_T_14 = _T_27; // @[mshrs.scala:439:75]
wire _io_mem_access_bits_T_10; // @[package.scala:16:47]
assign _io_mem_access_bits_T_10 = _T_27; // @[package.scala:16:47]
wire _io_mem_access_bits_T_34; // @[package.scala:16:47]
assign _io_mem_access_bits_T_34 = _T_27; // @[package.scala:16:47]
wire _send_resp_T_17; // @[package.scala:16:47]
assign _send_resp_T_17 = _T_27; // @[package.scala:16:47]
wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[mshrs.scala:439:75]
wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[mshrs.scala:439:75]
wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17]
wire [1:0] _atomics_T_15_source = _atomics_T_14 ? 2'h3 : _atomics_T_13_source; // @[mshrs.scala:439:75]
wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17]
wire _T_28 = req_uop_mem_cmd == 5'hF; // @[mshrs.scala:421:16, :439:75]
wire _atomics_T_16; // @[mshrs.scala:439:75]
assign _atomics_T_16 = _T_28; // @[mshrs.scala:439:75]
wire _io_mem_access_bits_T_11; // @[package.scala:16:47]
assign _io_mem_access_bits_T_11 = _T_28; // @[package.scala:16:47]
wire _io_mem_access_bits_T_35; // @[package.scala:16:47]
assign _io_mem_access_bits_T_35 = _T_28; // @[package.scala:16:47]
wire _send_resp_T_18; // @[package.scala:16:47]
assign _send_resp_T_18 = _T_28; // @[package.scala:16:47]
wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[mshrs.scala:439:75]
wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[mshrs.scala:439:75]
wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17]
wire [1:0] atomics_source = _atomics_T_16 ? 2'h3 : _atomics_T_15_source; // @[mshrs.scala:439:75]
wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17]
wire [7:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17]
wire [63:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17] |
Generate the Verilog code corresponding to this FIRRTL code module SinkC :
input clock : Clock
input reset : Reset
output io : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}}, resp : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<9>, param : UInt<3>, data : UInt<1>}}, flip c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<9>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, set : UInt<10>, flip way : UInt<3>, bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, bs_dat : { data : UInt<64>}, flip rel_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, rel_beat : { data : UInt<64>, corrupt : UInt<1>}}
inst c_q of Queue2_TLBundleC_a32d64s9k3z3c
connect c_q.clock, clock
connect c_q.reset, reset
connect c_q.io.enq.valid, io.c.valid
connect c_q.io.enq.bits.corrupt, io.c.bits.corrupt
connect c_q.io.enq.bits.data, io.c.bits.data
connect c_q.io.enq.bits.address, io.c.bits.address
connect c_q.io.enq.bits.source, io.c.bits.source
connect c_q.io.enq.bits.size, io.c.bits.size
connect c_q.io.enq.bits.param, io.c.bits.param
connect c_q.io.enq.bits.opcode, io.c.bits.opcode
connect io.c.ready, c_q.io.enq.ready
node _offset_T = bits(c_q.io.deq.bits.address, 0, 0)
node _offset_T_1 = bits(c_q.io.deq.bits.address, 1, 1)
node _offset_T_2 = bits(c_q.io.deq.bits.address, 2, 2)
node _offset_T_3 = bits(c_q.io.deq.bits.address, 3, 3)
node _offset_T_4 = bits(c_q.io.deq.bits.address, 4, 4)
node _offset_T_5 = bits(c_q.io.deq.bits.address, 5, 5)
node _offset_T_6 = bits(c_q.io.deq.bits.address, 6, 6)
node _offset_T_7 = bits(c_q.io.deq.bits.address, 7, 7)
node _offset_T_8 = bits(c_q.io.deq.bits.address, 8, 8)
node _offset_T_9 = bits(c_q.io.deq.bits.address, 9, 9)
node _offset_T_10 = bits(c_q.io.deq.bits.address, 10, 10)
node _offset_T_11 = bits(c_q.io.deq.bits.address, 11, 11)
node _offset_T_12 = bits(c_q.io.deq.bits.address, 12, 12)
node _offset_T_13 = bits(c_q.io.deq.bits.address, 13, 13)
node _offset_T_14 = bits(c_q.io.deq.bits.address, 14, 14)
node _offset_T_15 = bits(c_q.io.deq.bits.address, 15, 15)
node _offset_T_16 = bits(c_q.io.deq.bits.address, 16, 16)
node _offset_T_17 = bits(c_q.io.deq.bits.address, 17, 17)
node _offset_T_18 = bits(c_q.io.deq.bits.address, 18, 18)
node _offset_T_19 = bits(c_q.io.deq.bits.address, 19, 19)
node _offset_T_20 = bits(c_q.io.deq.bits.address, 20, 20)
node _offset_T_21 = bits(c_q.io.deq.bits.address, 21, 21)
node _offset_T_22 = bits(c_q.io.deq.bits.address, 22, 22)
node _offset_T_23 = bits(c_q.io.deq.bits.address, 23, 23)
node _offset_T_24 = bits(c_q.io.deq.bits.address, 24, 24)
node _offset_T_25 = bits(c_q.io.deq.bits.address, 25, 25)
node _offset_T_26 = bits(c_q.io.deq.bits.address, 26, 26)
node _offset_T_27 = bits(c_q.io.deq.bits.address, 27, 27)
node _offset_T_28 = bits(c_q.io.deq.bits.address, 31, 31)
node offset_lo_lo_lo_hi = cat(_offset_T_2, _offset_T_1)
node offset_lo_lo_lo = cat(offset_lo_lo_lo_hi, _offset_T)
node offset_lo_lo_hi_lo = cat(_offset_T_4, _offset_T_3)
node offset_lo_lo_hi_hi = cat(_offset_T_6, _offset_T_5)
node offset_lo_lo_hi = cat(offset_lo_lo_hi_hi, offset_lo_lo_hi_lo)
node offset_lo_lo = cat(offset_lo_lo_hi, offset_lo_lo_lo)
node offset_lo_hi_lo_hi = cat(_offset_T_9, _offset_T_8)
node offset_lo_hi_lo = cat(offset_lo_hi_lo_hi, _offset_T_7)
node offset_lo_hi_hi_lo = cat(_offset_T_11, _offset_T_10)
node offset_lo_hi_hi_hi = cat(_offset_T_13, _offset_T_12)
node offset_lo_hi_hi = cat(offset_lo_hi_hi_hi, offset_lo_hi_hi_lo)
node offset_lo_hi = cat(offset_lo_hi_hi, offset_lo_hi_lo)
node offset_lo = cat(offset_lo_hi, offset_lo_lo)
node offset_hi_lo_lo_hi = cat(_offset_T_16, _offset_T_15)
node offset_hi_lo_lo = cat(offset_hi_lo_lo_hi, _offset_T_14)
node offset_hi_lo_hi_lo = cat(_offset_T_18, _offset_T_17)
node offset_hi_lo_hi_hi = cat(_offset_T_20, _offset_T_19)
node offset_hi_lo_hi = cat(offset_hi_lo_hi_hi, offset_hi_lo_hi_lo)
node offset_hi_lo = cat(offset_hi_lo_hi, offset_hi_lo_lo)
node offset_hi_hi_lo_lo = cat(_offset_T_22, _offset_T_21)
node offset_hi_hi_lo_hi = cat(_offset_T_24, _offset_T_23)
node offset_hi_hi_lo = cat(offset_hi_hi_lo_hi, offset_hi_hi_lo_lo)
node offset_hi_hi_hi_lo = cat(_offset_T_26, _offset_T_25)
node offset_hi_hi_hi_hi = cat(_offset_T_28, _offset_T_27)
node offset_hi_hi_hi = cat(offset_hi_hi_hi_hi, offset_hi_hi_hi_lo)
node offset_hi_hi = cat(offset_hi_hi_hi, offset_hi_hi_lo)
node offset_hi = cat(offset_hi_hi, offset_hi_lo)
node offset = cat(offset_hi, offset_lo)
node set = shr(offset, 6)
node tag = shr(set, 10)
node tag_1 = bits(tag, 12, 0)
node set_1 = bits(set, 9, 0)
node offset_1 = bits(offset, 5, 0)
node _T = and(c_q.io.deq.ready, c_q.io.deq.valid)
node _r_beats1_decode_T = dshl(UInt<6>(0h3f), c_q.io.deq.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 5, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 3)
node r_beats1_opdata = bits(c_q.io.deq.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node first = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node last = or(_r_last_T, _r_last_T_1)
node r_3 = and(last, _T)
node _r_count_T = not(r_counter1)
node beat = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(first, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node hasData = bits(c_q.io.deq.bits.opcode, 0, 0)
node _raw_resp_T = eq(c_q.io.deq.bits.opcode, UInt<3>(0h4))
node _raw_resp_T_1 = eq(c_q.io.deq.bits.opcode, UInt<3>(0h5))
node raw_resp = or(_raw_resp_T, _raw_resp_T_1)
reg resp_r : UInt<1>, clock
when c_q.io.deq.valid :
connect resp_r, raw_resp
node resp = mux(c_q.io.deq.valid, raw_resp, resp_r)
node _T_1 = and(c_q.io.deq.valid, c_q.io.deq.bits.corrupt)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed: Data poisoning unavailable\n at SinkC.scala:90 assert (!(c.valid && c.bits.corrupt), \"Data poisoning unavailable\")\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
reg io_set_r : UInt<10>, clock
when c_q.io.deq.valid :
connect io_set_r, set_1
node _io_set_T = mux(c_q.io.deq.valid, set_1, io_set_r)
connect io.set, _io_set_T
wire bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}
inst io_bs_adr_q of Queue1_BankedStoreInnerAddress
connect io_bs_adr_q.clock, clock
connect io_bs_adr_q.reset, reset
connect io_bs_adr_q.io.enq.valid, bs_adr.valid
connect io_bs_adr_q.io.enq.bits.mask, bs_adr.bits.mask
connect io_bs_adr_q.io.enq.bits.beat, bs_adr.bits.beat
connect io_bs_adr_q.io.enq.bits.set, bs_adr.bits.set
connect io_bs_adr_q.io.enq.bits.way, bs_adr.bits.way
connect io_bs_adr_q.io.enq.bits.noop, bs_adr.bits.noop
connect bs_adr.ready, io_bs_adr_q.io.enq.ready
connect io.bs_adr.bits, io_bs_adr_q.io.deq.bits
connect io.bs_adr.valid, io_bs_adr_q.io.deq.valid
connect io_bs_adr_q.io.deq.ready, io.bs_adr.ready
node _io_bs_dat_data_T = and(bs_adr.ready, bs_adr.valid)
reg io_bs_dat_data_r : UInt<64>, clock
when _io_bs_dat_data_T :
connect io_bs_dat_data_r, c_q.io.deq.bits.data
connect io.bs_dat.data, io_bs_dat_data_r
node _bs_adr_valid_T = eq(first, UInt<1>(0h0))
node _bs_adr_valid_T_1 = and(c_q.io.deq.valid, hasData)
node _bs_adr_valid_T_2 = or(_bs_adr_valid_T, _bs_adr_valid_T_1)
node _bs_adr_valid_T_3 = and(resp, _bs_adr_valid_T_2)
connect bs_adr.valid, _bs_adr_valid_T_3
node _bs_adr_bits_noop_T = eq(c_q.io.deq.valid, UInt<1>(0h0))
connect bs_adr.bits.noop, _bs_adr_bits_noop_T
connect bs_adr.bits.way, io.way
connect bs_adr.bits.set, io.set
node _bs_adr_bits_beat_T = add(beat, bs_adr.ready)
node _bs_adr_bits_beat_T_1 = tail(_bs_adr_bits_beat_T, 1)
reg bs_adr_bits_beat_r : UInt<3>, clock
when c_q.io.deq.valid :
connect bs_adr_bits_beat_r, _bs_adr_bits_beat_T_1
node _bs_adr_bits_beat_T_2 = mux(c_q.io.deq.valid, beat, bs_adr_bits_beat_r)
connect bs_adr.bits.beat, _bs_adr_bits_beat_T_2
node _bs_adr_bits_mask_T = not(UInt<1>(0h0))
connect bs_adr.bits.mask, _bs_adr_bits_mask_T
node _T_6 = eq(bs_adr.ready, UInt<1>(0h0))
node _T_7 = and(bs_adr.valid, _T_6)
node _io_resp_valid_T = and(resp, c_q.io.deq.valid)
node _io_resp_valid_T_1 = or(first, last)
node _io_resp_valid_T_2 = and(_io_resp_valid_T, _io_resp_valid_T_1)
node _io_resp_valid_T_3 = eq(hasData, UInt<1>(0h0))
node _io_resp_valid_T_4 = or(_io_resp_valid_T_3, bs_adr.ready)
node _io_resp_valid_T_5 = and(_io_resp_valid_T_2, _io_resp_valid_T_4)
connect io.resp.valid, _io_resp_valid_T_5
connect io.resp.bits.last, last
connect io.resp.bits.set, set_1
connect io.resp.bits.tag, tag_1
connect io.resp.bits.source, c_q.io.deq.bits.source
connect io.resp.bits.param, c_q.io.deq.bits.param
connect io.resp.bits.data, hasData
inst putbuffer of ListBuffer_PutBufferCEntry_q2_e16
connect putbuffer.clock, clock
connect putbuffer.reset, reset
regreset lists : UInt<2>, clock, reset, UInt<2>(0h0)
wire lists_set : UInt<2>
connect lists_set, UInt<2>(0h0)
wire lists_clr : UInt<2>
connect lists_clr, UInt<2>(0h0)
node _lists_T = or(lists, lists_set)
node _lists_T_1 = not(lists_clr)
node _lists_T_2 = and(_lists_T, _lists_T_1)
connect lists, _lists_T_2
node _free_T = andr(lists)
node free = eq(_free_T, UInt<1>(0h0))
node _freeOH_T = not(lists)
node _freeOH_T_1 = shl(_freeOH_T, 1)
node _freeOH_T_2 = bits(_freeOH_T_1, 1, 0)
node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2)
node _freeOH_T_4 = bits(_freeOH_T_3, 1, 0)
node _freeOH_T_5 = shl(_freeOH_T_4, 1)
node _freeOH_T_6 = not(_freeOH_T_5)
node _freeOH_T_7 = not(lists)
node freeOH = and(_freeOH_T_6, _freeOH_T_7)
node freeIdx_hi = bits(freeOH, 2, 2)
node freeIdx_lo = bits(freeOH, 1, 0)
node _freeIdx_T = orr(freeIdx_hi)
node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo)
node _freeIdx_T_2 = bits(_freeIdx_T_1, 1, 1)
node freeIdx = cat(_freeIdx_T, _freeIdx_T_2)
node _req_block_T = eq(io.req.ready, UInt<1>(0h0))
node req_block = and(first, _req_block_T)
node _buf_block_T = eq(putbuffer.io.push.ready, UInt<1>(0h0))
node buf_block = and(hasData, _buf_block_T)
node _set_block_T = and(hasData, first)
node _set_block_T_1 = eq(free, UInt<1>(0h0))
node set_block = and(_set_block_T, _set_block_T_1)
node _T_8 = eq(raw_resp, UInt<1>(0h0))
node _T_9 = and(c_q.io.deq.valid, _T_8)
node _T_10 = and(_T_9, req_block)
node _T_11 = eq(raw_resp, UInt<1>(0h0))
node _T_12 = and(c_q.io.deq.valid, _T_11)
node _T_13 = and(_T_12, buf_block)
node _T_14 = eq(raw_resp, UInt<1>(0h0))
node _T_15 = and(c_q.io.deq.valid, _T_14)
node _T_16 = and(_T_15, set_block)
node _q_io_deq_ready_T = eq(hasData, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = or(_q_io_deq_ready_T, bs_adr.ready)
node _q_io_deq_ready_T_2 = eq(req_block, UInt<1>(0h0))
node _q_io_deq_ready_T_3 = eq(buf_block, UInt<1>(0h0))
node _q_io_deq_ready_T_4 = and(_q_io_deq_ready_T_2, _q_io_deq_ready_T_3)
node _q_io_deq_ready_T_5 = eq(set_block, UInt<1>(0h0))
node _q_io_deq_ready_T_6 = and(_q_io_deq_ready_T_4, _q_io_deq_ready_T_5)
node _q_io_deq_ready_T_7 = mux(raw_resp, _q_io_deq_ready_T_1, _q_io_deq_ready_T_6)
connect c_q.io.deq.ready, _q_io_deq_ready_T_7
node _io_req_valid_T = eq(resp, UInt<1>(0h0))
node _io_req_valid_T_1 = and(_io_req_valid_T, c_q.io.deq.valid)
node _io_req_valid_T_2 = and(_io_req_valid_T_1, first)
node _io_req_valid_T_3 = eq(buf_block, UInt<1>(0h0))
node _io_req_valid_T_4 = and(_io_req_valid_T_2, _io_req_valid_T_3)
node _io_req_valid_T_5 = eq(set_block, UInt<1>(0h0))
node _io_req_valid_T_6 = and(_io_req_valid_T_4, _io_req_valid_T_5)
connect io.req.valid, _io_req_valid_T_6
node _putbuffer_io_push_valid_T = eq(resp, UInt<1>(0h0))
node _putbuffer_io_push_valid_T_1 = and(_putbuffer_io_push_valid_T, c_q.io.deq.valid)
node _putbuffer_io_push_valid_T_2 = and(_putbuffer_io_push_valid_T_1, hasData)
node _putbuffer_io_push_valid_T_3 = eq(req_block, UInt<1>(0h0))
node _putbuffer_io_push_valid_T_4 = and(_putbuffer_io_push_valid_T_2, _putbuffer_io_push_valid_T_3)
node _putbuffer_io_push_valid_T_5 = eq(set_block, UInt<1>(0h0))
node _putbuffer_io_push_valid_T_6 = and(_putbuffer_io_push_valid_T_4, _putbuffer_io_push_valid_T_5)
connect putbuffer.io.push.valid, _putbuffer_io_push_valid_T_6
node _T_17 = eq(resp, UInt<1>(0h0))
node _T_18 = and(_T_17, c_q.io.deq.valid)
node _T_19 = and(_T_18, first)
node _T_20 = and(_T_19, hasData)
node _T_21 = eq(req_block, UInt<1>(0h0))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(buf_block, UInt<1>(0h0))
node _T_24 = and(_T_22, _T_23)
when _T_24 :
connect lists_set, freeOH
reg put_r : UInt<2>, clock
when first :
connect put_r, freeIdx
node put = mux(first, freeIdx, put_r)
wire _WIRE : UInt<1>[3]
connect _WIRE[0], UInt<1>(0h0)
connect _WIRE[1], UInt<1>(0h0)
connect _WIRE[2], UInt<1>(0h1)
connect io.req.bits.prio, _WIRE
connect io.req.bits.control, UInt<1>(0h0)
connect io.req.bits.opcode, c_q.io.deq.bits.opcode
connect io.req.bits.param, c_q.io.deq.bits.param
connect io.req.bits.size, c_q.io.deq.bits.size
connect io.req.bits.source, c_q.io.deq.bits.source
connect io.req.bits.offset, offset_1
connect io.req.bits.set, set_1
connect io.req.bits.tag, tag_1
connect io.req.bits.put, put
connect putbuffer.io.push.bits.index, put
connect putbuffer.io.push.bits.data.data, c_q.io.deq.bits.data
connect putbuffer.io.push.bits.data.corrupt, c_q.io.deq.bits.corrupt
connect putbuffer.io.pop.bits, io.rel_pop.bits.index
node _putbuffer_io_pop_valid_T = and(io.rel_pop.ready, io.rel_pop.valid)
connect putbuffer.io.pop.valid, _putbuffer_io_pop_valid_T
node _io_rel_pop_ready_T = bits(io.rel_pop.bits.index, 0, 0)
node _io_rel_pop_ready_T_1 = dshr(putbuffer.io.valid, _io_rel_pop_ready_T)
node _io_rel_pop_ready_T_2 = bits(_io_rel_pop_ready_T_1, 0, 0)
connect io.rel_pop.ready, _io_rel_pop_ready_T_2
connect io.rel_beat, putbuffer.io.data
node _T_25 = and(io.rel_pop.ready, io.rel_pop.valid)
node _T_26 = and(_T_25, io.rel_pop.bits.last)
when _T_26 :
node lists_clr_shiftAmount = bits(io.rel_pop.bits.index, 0, 0)
node _lists_clr_T = dshl(UInt<1>(0h1), lists_clr_shiftAmount)
node _lists_clr_T_1 = bits(_lists_clr_T, 1, 0)
connect lists_clr, _lists_clr_T_1 | module SinkC( // @[SinkC.scala:41:7]
input clock, // @[SinkC.scala:41:7]
input reset, // @[SinkC.scala:41:7]
input io_req_ready, // @[SinkC.scala:43:14]
output io_req_valid, // @[SinkC.scala:43:14]
output [2:0] io_req_bits_opcode, // @[SinkC.scala:43:14]
output [2:0] io_req_bits_param, // @[SinkC.scala:43:14]
output [2:0] io_req_bits_size, // @[SinkC.scala:43:14]
output [8:0] io_req_bits_source, // @[SinkC.scala:43:14]
output [12:0] io_req_bits_tag, // @[SinkC.scala:43:14]
output [5:0] io_req_bits_offset, // @[SinkC.scala:43:14]
output [5:0] io_req_bits_put, // @[SinkC.scala:43:14]
output [9:0] io_req_bits_set, // @[SinkC.scala:43:14]
output io_resp_valid, // @[SinkC.scala:43:14]
output io_resp_bits_last, // @[SinkC.scala:43:14]
output [9:0] io_resp_bits_set, // @[SinkC.scala:43:14]
output [12:0] io_resp_bits_tag, // @[SinkC.scala:43:14]
output [8:0] io_resp_bits_source, // @[SinkC.scala:43:14]
output [2:0] io_resp_bits_param, // @[SinkC.scala:43:14]
output io_resp_bits_data, // @[SinkC.scala:43:14]
output io_c_ready, // @[SinkC.scala:43:14]
input io_c_valid, // @[SinkC.scala:43:14]
input [2:0] io_c_bits_opcode, // @[SinkC.scala:43:14]
input [2:0] io_c_bits_param, // @[SinkC.scala:43:14]
input [2:0] io_c_bits_size, // @[SinkC.scala:43:14]
input [8:0] io_c_bits_source, // @[SinkC.scala:43:14]
input [31:0] io_c_bits_address, // @[SinkC.scala:43:14]
input [63:0] io_c_bits_data, // @[SinkC.scala:43:14]
input io_c_bits_corrupt, // @[SinkC.scala:43:14]
output [9:0] io_set, // @[SinkC.scala:43:14]
input [2:0] io_way, // @[SinkC.scala:43:14]
input io_bs_adr_ready, // @[SinkC.scala:43:14]
output io_bs_adr_valid, // @[SinkC.scala:43:14]
output io_bs_adr_bits_noop, // @[SinkC.scala:43:14]
output [2:0] io_bs_adr_bits_way, // @[SinkC.scala:43:14]
output [9:0] io_bs_adr_bits_set, // @[SinkC.scala:43:14]
output [2:0] io_bs_adr_bits_beat, // @[SinkC.scala:43:14]
output io_bs_adr_bits_mask, // @[SinkC.scala:43:14]
output [63:0] io_bs_dat_data, // @[SinkC.scala:43:14]
output io_rel_pop_ready, // @[SinkC.scala:43:14]
input io_rel_pop_valid, // @[SinkC.scala:43:14]
input [5:0] io_rel_pop_bits_index, // @[SinkC.scala:43:14]
input io_rel_pop_bits_last, // @[SinkC.scala:43:14]
output [63:0] io_rel_beat_data, // @[SinkC.scala:43:14]
output io_rel_beat_corrupt // @[SinkC.scala:43:14]
);
wire io_rel_pop_ready_0; // @[SinkC.scala:160:43]
wire _putbuffer_io_push_ready; // @[SinkC.scala:115:27]
wire [1:0] _putbuffer_io_valid; // @[SinkC.scala:115:27]
wire _io_bs_adr_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _c_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _c_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [2:0] _c_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _c_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [8:0] _c_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [31:0] _c_q_io_deq_bits_address; // @[Decoupled.scala:362:21]
wire [63:0] _c_q_io_deq_bits_data; // @[Decoupled.scala:362:21]
wire _c_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire [12:0] tag = {_c_q_io_deq_bits_address[31], _c_q_io_deq_bits_address[27:16]}; // @[Decoupled.scala:362:21]
wire [12:0] _r_beats1_decode_T = 13'h3F << _c_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [2:0] r_beats1 = _c_q_io_deq_bits_opcode[0] ? ~(_r_beats1_decode_T[5:3]) : 3'h0; // @[Decoupled.scala:362:21]
reg [2:0] r_counter; // @[Edges.scala:229:27]
wire [2:0] _r_counter1_T = r_counter - 3'h1; // @[Edges.scala:229:27, :230:28]
wire last = r_counter == 3'h1 | r_beats1 == 3'h0; // @[Edges.scala:221:14, :229:27, :232:{25,33,43}]
wire [2:0] beat = r_beats1 & ~_r_counter1_T; // @[Edges.scala:221:14, :230:28, :234:{25,27}]
wire raw_resp = _c_q_io_deq_bits_opcode == 3'h4 | _c_q_io_deq_bits_opcode == 3'h5; // @[Decoupled.scala:362:21]
reg resp_r; // @[SinkC.scala:79:48]
wire resp = _c_q_io_deq_valid ? raw_resp : resp_r; // @[Decoupled.scala:362:21] |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x5_1 :
input clock : Clock
input reset : Reset
output auto : { flip in : UInt<1>[5], out : { sync : UInt<1>[5]}}
wire nodeIn : UInt<1>[5]
invalidate nodeIn[0]
invalidate nodeIn[1]
invalidate nodeIn[2]
invalidate nodeIn[3]
invalidate nodeIn[4]
wire nodeOut : { sync : UInt<1>[5]}
invalidate nodeOut.sync[0]
invalidate nodeOut.sync[1]
invalidate nodeOut.sync[2]
invalidate nodeOut.sync[3]
invalidate nodeOut.sync[4]
connect auto.out, nodeOut
connect nodeIn, auto.in
node lo = cat(nodeIn[1], nodeIn[0])
node hi_hi = cat(nodeIn[4], nodeIn[3])
node hi = cat(hi_hi, nodeIn[2])
node _T = cat(hi, lo)
inst reg of AsyncResetRegVec_w5_i0_1
connect reg.clock, clock
connect reg.reset, reset
connect reg.io.d, _T
connect reg.io.en, UInt<1>(0h1)
node _T_1 = bits(reg.io.q, 0, 0)
node _T_2 = bits(reg.io.q, 1, 1)
node _T_3 = bits(reg.io.q, 2, 2)
node _T_4 = bits(reg.io.q, 3, 3)
node _T_5 = bits(reg.io.q, 4, 4)
connect nodeOut.sync[0], _T_1
connect nodeOut.sync[1], _T_2
connect nodeOut.sync[2], _T_3
connect nodeOut.sync[3], _T_4
connect nodeOut.sync[4], _T_5 | module IntSyncCrossingSource_n1x5_1( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset, // @[Crossing.scala:41:9]
input auto_in_0, // @[LazyModuleImp.scala:107:25]
input auto_in_1, // @[LazyModuleImp.scala:107:25]
input auto_in_2, // @[LazyModuleImp.scala:107:25]
input auto_in_3, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_1, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_2, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_3, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_4 // @[LazyModuleImp.scala:107:25]
);
wire [4:0] _reg_io_q; // @[AsyncResetReg.scala:86:21]
wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9]
wire auto_in_1_0 = auto_in_1; // @[Crossing.scala:41:9]
wire auto_in_2_0 = auto_in_2; // @[Crossing.scala:41:9]
wire auto_in_3_0 = auto_in_3; // @[Crossing.scala:41:9]
wire auto_in_4 = 1'h0; // @[Crossing.scala:41:9]
wire nodeIn_4 = 1'h0; // @[Crossing.scala:41:9]
wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9]
wire nodeIn_1 = auto_in_1_0; // @[Crossing.scala:41:9]
wire nodeIn_2 = auto_in_2_0; // @[Crossing.scala:41:9]
wire nodeIn_3 = auto_in_3_0; // @[Crossing.scala:41:9]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire nodeOut_sync_1; // @[MixedNode.scala:542:17]
wire nodeOut_sync_2; // @[MixedNode.scala:542:17]
wire nodeOut_sync_3; // @[MixedNode.scala:542:17]
wire nodeOut_sync_4; // @[MixedNode.scala:542:17]
wire auto_out_sync_0_0; // @[Crossing.scala:41:9]
wire auto_out_sync_1_0; // @[Crossing.scala:41:9]
wire auto_out_sync_2_0; // @[Crossing.scala:41:9]
wire auto_out_sync_3_0; // @[Crossing.scala:41:9]
wire auto_out_sync_4_0; // @[Crossing.scala:41:9]
assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9]
assign auto_out_sync_1_0 = nodeOut_sync_1; // @[Crossing.scala:41:9]
assign auto_out_sync_2_0 = nodeOut_sync_2; // @[Crossing.scala:41:9]
assign auto_out_sync_3_0 = nodeOut_sync_3; // @[Crossing.scala:41:9]
assign auto_out_sync_4_0 = nodeOut_sync_4; // @[Crossing.scala:41:9]
wire [1:0] lo = {nodeIn_1, nodeIn_0}; // @[Crossing.scala:45:36]
wire [1:0] hi_hi = {1'h0, nodeIn_3}; // @[Crossing.scala:41:9, :45:36]
wire [2:0] hi = {hi_hi, nodeIn_2}; // @[Crossing.scala:45:36]
assign nodeOut_sync_0 = _reg_io_q[0]; // @[AsyncResetReg.scala:86:21]
assign nodeOut_sync_1 = _reg_io_q[1]; // @[AsyncResetReg.scala:86:21]
assign nodeOut_sync_2 = _reg_io_q[2]; // @[AsyncResetReg.scala:86:21]
assign nodeOut_sync_3 = _reg_io_q[3]; // @[AsyncResetReg.scala:86:21]
assign nodeOut_sync_4 = _reg_io_q[4]; // @[AsyncResetReg.scala:86:21]
AsyncResetRegVec_w5_i0_1 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset),
.io_d ({hi, lo}), // @[Crossing.scala:45:36]
.io_q (_reg_io_q)
); // @[AsyncResetReg.scala:86:21]
assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9]
assign auto_out_sync_1 = auto_out_sync_1_0; // @[Crossing.scala:41:9]
assign auto_out_sync_2 = auto_out_sync_2_0; // @[Crossing.scala:41:9]
assign auto_out_sync_3 = auto_out_sync_3_0; // @[Crossing.scala:41:9]
assign auto_out_sync_4 = auto_out_sync_4_0; // @[Crossing.scala:41:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BankBinder :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_37
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
connect nodeOut, nodeIn | module BankBinder( // @[BankBinder.scala:61:9]
input clock, // @[BankBinder.scala:61:9]
input reset, // @[BankBinder.scala:61:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[BankBinder.scala:61:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BankBinder.scala:61:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BankBinder.scala:61:9]
wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BankBinder.scala:61:9]
wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BankBinder.scala:61:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BankBinder.scala:61:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BankBinder.scala:61:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BankBinder.scala:61:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BankBinder.scala:61:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[BankBinder.scala:61:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[BankBinder.scala:61:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[BankBinder.scala:61:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[BankBinder.scala:61:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[BankBinder.scala:61:9]
wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[BankBinder.scala:61:9]
wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[BankBinder.scala:61:9]
wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[BankBinder.scala:61:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[BankBinder.scala:61:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[BankBinder.scala:61:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[BankBinder.scala:61:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[BankBinder.scala:61:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BankBinder.scala:61:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BankBinder.scala:61:9]
wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BankBinder.scala:61:9]
wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BankBinder.scala:61:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BankBinder.scala:61:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BankBinder.scala:61:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BankBinder.scala:61:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BankBinder.scala:61:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[BankBinder.scala:61:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[BankBinder.scala:61:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[BankBinder.scala:61:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[BankBinder.scala:61:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[BankBinder.scala:61:9]
wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[BankBinder.scala:61:9]
wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[BankBinder.scala:61:9]
wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[BankBinder.scala:61:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[BankBinder.scala:61:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[BankBinder.scala:61:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[BankBinder.scala:61:9]
wire auto_in_a_ready_0; // @[BankBinder.scala:61:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[BankBinder.scala:61:9]
wire [1:0] auto_in_d_bits_param_0; // @[BankBinder.scala:61:9]
wire [2:0] auto_in_d_bits_size_0; // @[BankBinder.scala:61:9]
wire [3:0] auto_in_d_bits_source_0; // @[BankBinder.scala:61:9]
wire auto_in_d_bits_sink_0; // @[BankBinder.scala:61:9]
wire auto_in_d_bits_denied_0; // @[BankBinder.scala:61:9]
wire [63:0] auto_in_d_bits_data_0; // @[BankBinder.scala:61:9]
wire auto_in_d_bits_corrupt_0; // @[BankBinder.scala:61:9]
wire auto_in_d_valid_0; // @[BankBinder.scala:61:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[BankBinder.scala:61:9]
wire [2:0] auto_out_a_bits_param_0; // @[BankBinder.scala:61:9]
wire [2:0] auto_out_a_bits_size_0; // @[BankBinder.scala:61:9]
wire [3:0] auto_out_a_bits_source_0; // @[BankBinder.scala:61:9]
wire [31:0] auto_out_a_bits_address_0; // @[BankBinder.scala:61:9]
wire [7:0] auto_out_a_bits_mask_0; // @[BankBinder.scala:61:9]
wire [63:0] auto_out_a_bits_data_0; // @[BankBinder.scala:61:9]
wire auto_out_a_bits_corrupt_0; // @[BankBinder.scala:61:9]
wire auto_out_a_valid_0; // @[BankBinder.scala:61:9]
wire auto_out_d_ready_0; // @[BankBinder.scala:61:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BankBinder.scala:61:9]
assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BankBinder.scala:61:9]
assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[BankBinder.scala:61:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[BankBinder.scala:61:9]
assign nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_denied = nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
TLMonitor_37 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_a_ready = auto_in_a_ready_0; // @[BankBinder.scala:61:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BankBinder.scala:61:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[BankBinder.scala:61:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[BankBinder.scala:61:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_150 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_150( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module FullyPortedRF_4 :
input clock : Clock
input reset : Reset
output io : { flip arb_read_reqs : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>}[6], rrd_read_resps : UInt<20>[6], flip write_ports : { valid : UInt<1>, bits : { addr : UInt<7>, data : UInt<20>}}[3]}
node _T = eq(io.write_ports[0].valid, UInt<1>(0h0))
node _T_1 = eq(io.write_ports[1].valid, UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = neq(io.write_ports[0].bits.addr, io.write_ports[1].bits.addr)
node _T_4 = or(_T_2, _T_3)
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
node _T_8 = eq(io.write_ports[0].valid, UInt<1>(0h0))
node _T_9 = eq(io.write_ports[2].valid, UInt<1>(0h0))
node _T_10 = or(_T_8, _T_9)
node _T_11 = neq(io.write_ports[0].bits.addr, io.write_ports[2].bits.addr)
node _T_12 = or(_T_10, _T_11)
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
node _T_15 = eq(_T_12, UInt<1>(0h0))
when _T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf_1
assert(clock, _T_12, UInt<1>(0h1), "") : assert_1
node _T_16 = eq(io.write_ports[1].valid, UInt<1>(0h0))
node _T_17 = eq(io.write_ports[2].valid, UInt<1>(0h0))
node _T_18 = or(_T_16, _T_17)
node _T_19 = neq(io.write_ports[1].bits.addr, io.write_ports[2].bits.addr)
node _T_20 = or(_T_18, _T_19)
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
node _T_23 = eq(_T_20, UInt<1>(0h0))
when _T_23 :
printf(clock, UInt<1>(0h1), "Assertion failed: [regfile] too many writers a register\n at regfile.scala:45 assert(!io.write_ports(i).valid ||\n") : printf_2
assert(clock, _T_20, UInt<1>(0h1), "") : assert_2
connect io.arb_read_reqs[0].ready, UInt<1>(0h1)
connect io.arb_read_reqs[1].ready, UInt<1>(0h1)
connect io.arb_read_reqs[2].ready, UInt<1>(0h1)
connect io.arb_read_reqs[3].ready, UInt<1>(0h1)
connect io.arb_read_reqs[4].ready, UInt<1>(0h1)
connect io.arb_read_reqs[5].ready, UInt<1>(0h1)
cmem regfile : UInt<20> [32]
reg io_rrd_read_resps_0_REG : UInt, clock
connect io_rrd_read_resps_0_REG, io.arb_read_reqs[0].bits
node _io_rrd_read_resps_0_T = or(io_rrd_read_resps_0_REG, UInt<5>(0h0))
node _io_rrd_read_resps_0_T_1 = bits(_io_rrd_read_resps_0_T, 4, 0)
infer mport io_rrd_read_resps_0_MPORT = regfile[_io_rrd_read_resps_0_T_1], clock
connect io.rrd_read_resps[0], io_rrd_read_resps_0_MPORT
reg io_rrd_read_resps_1_REG : UInt, clock
connect io_rrd_read_resps_1_REG, io.arb_read_reqs[1].bits
node _io_rrd_read_resps_1_T = or(io_rrd_read_resps_1_REG, UInt<5>(0h0))
node _io_rrd_read_resps_1_T_1 = bits(_io_rrd_read_resps_1_T, 4, 0)
infer mport io_rrd_read_resps_1_MPORT = regfile[_io_rrd_read_resps_1_T_1], clock
connect io.rrd_read_resps[1], io_rrd_read_resps_1_MPORT
reg io_rrd_read_resps_2_REG : UInt, clock
connect io_rrd_read_resps_2_REG, io.arb_read_reqs[2].bits
node _io_rrd_read_resps_2_T = or(io_rrd_read_resps_2_REG, UInt<5>(0h0))
node _io_rrd_read_resps_2_T_1 = bits(_io_rrd_read_resps_2_T, 4, 0)
infer mport io_rrd_read_resps_2_MPORT = regfile[_io_rrd_read_resps_2_T_1], clock
connect io.rrd_read_resps[2], io_rrd_read_resps_2_MPORT
reg io_rrd_read_resps_3_REG : UInt, clock
connect io_rrd_read_resps_3_REG, io.arb_read_reqs[3].bits
node _io_rrd_read_resps_3_T = or(io_rrd_read_resps_3_REG, UInt<5>(0h0))
node _io_rrd_read_resps_3_T_1 = bits(_io_rrd_read_resps_3_T, 4, 0)
infer mport io_rrd_read_resps_3_MPORT = regfile[_io_rrd_read_resps_3_T_1], clock
connect io.rrd_read_resps[3], io_rrd_read_resps_3_MPORT
reg io_rrd_read_resps_4_REG : UInt, clock
connect io_rrd_read_resps_4_REG, io.arb_read_reqs[4].bits
node _io_rrd_read_resps_4_T = or(io_rrd_read_resps_4_REG, UInt<5>(0h0))
node _io_rrd_read_resps_4_T_1 = bits(_io_rrd_read_resps_4_T, 4, 0)
infer mport io_rrd_read_resps_4_MPORT = regfile[_io_rrd_read_resps_4_T_1], clock
connect io.rrd_read_resps[4], io_rrd_read_resps_4_MPORT
reg io_rrd_read_resps_5_REG : UInt, clock
connect io_rrd_read_resps_5_REG, io.arb_read_reqs[5].bits
node _io_rrd_read_resps_5_T = or(io_rrd_read_resps_5_REG, UInt<5>(0h0))
node _io_rrd_read_resps_5_T_1 = bits(_io_rrd_read_resps_5_T, 4, 0)
infer mport io_rrd_read_resps_5_MPORT = regfile[_io_rrd_read_resps_5_T_1], clock
connect io.rrd_read_resps[5], io_rrd_read_resps_5_MPORT
when io.write_ports[0].valid :
node _T_24 = bits(io.write_ports[0].bits.addr, 4, 0)
infer mport MPORT = regfile[_T_24], clock
connect MPORT, io.write_ports[0].bits.data
when io.write_ports[1].valid :
node _T_25 = bits(io.write_ports[1].bits.addr, 4, 0)
infer mport MPORT_1 = regfile[_T_25], clock
connect MPORT_1, io.write_ports[1].bits.data
when io.write_ports[2].valid :
node _T_26 = bits(io.write_ports[2].bits.addr, 4, 0)
infer mport MPORT_2 = regfile[_T_26], clock
connect MPORT_2, io.write_ports[2].bits.data | module FullyPortedRF_4( // @[regfile.scala:186:7]
input clock, // @[regfile.scala:186:7]
input reset, // @[regfile.scala:186:7]
input io_arb_read_reqs_0_valid, // @[regfile.scala:31:14]
input [4:0] io_arb_read_reqs_0_bits, // @[regfile.scala:31:14]
input io_arb_read_reqs_1_valid, // @[regfile.scala:31:14]
input [4:0] io_arb_read_reqs_1_bits, // @[regfile.scala:31:14]
input io_arb_read_reqs_2_valid, // @[regfile.scala:31:14]
input [4:0] io_arb_read_reqs_2_bits, // @[regfile.scala:31:14]
input io_arb_read_reqs_3_valid, // @[regfile.scala:31:14]
input [4:0] io_arb_read_reqs_3_bits, // @[regfile.scala:31:14]
input io_arb_read_reqs_4_valid, // @[regfile.scala:31:14]
input [4:0] io_arb_read_reqs_4_bits, // @[regfile.scala:31:14]
input io_arb_read_reqs_5_valid, // @[regfile.scala:31:14]
input [4:0] io_arb_read_reqs_5_bits, // @[regfile.scala:31:14]
output [19:0] io_rrd_read_resps_0, // @[regfile.scala:31:14]
output [19:0] io_rrd_read_resps_1, // @[regfile.scala:31:14]
output [19:0] io_rrd_read_resps_2, // @[regfile.scala:31:14]
output [19:0] io_rrd_read_resps_3, // @[regfile.scala:31:14]
output [19:0] io_rrd_read_resps_4, // @[regfile.scala:31:14]
output [19:0] io_rrd_read_resps_5, // @[regfile.scala:31:14]
input io_write_ports_0_valid, // @[regfile.scala:31:14]
input [6:0] io_write_ports_0_bits_addr, // @[regfile.scala:31:14]
input [19:0] io_write_ports_0_bits_data, // @[regfile.scala:31:14]
input io_write_ports_1_valid, // @[regfile.scala:31:14]
input [6:0] io_write_ports_1_bits_addr, // @[regfile.scala:31:14]
input [19:0] io_write_ports_1_bits_data, // @[regfile.scala:31:14]
input io_write_ports_2_valid, // @[regfile.scala:31:14]
input [6:0] io_write_ports_2_bits_addr, // @[regfile.scala:31:14]
input [19:0] io_write_ports_2_bits_data // @[regfile.scala:31:14]
);
wire io_arb_read_reqs_0_valid_0 = io_arb_read_reqs_0_valid; // @[regfile.scala:186:7]
wire [4:0] io_arb_read_reqs_0_bits_0 = io_arb_read_reqs_0_bits; // @[regfile.scala:186:7]
wire io_arb_read_reqs_1_valid_0 = io_arb_read_reqs_1_valid; // @[regfile.scala:186:7]
wire [4:0] io_arb_read_reqs_1_bits_0 = io_arb_read_reqs_1_bits; // @[regfile.scala:186:7]
wire io_arb_read_reqs_2_valid_0 = io_arb_read_reqs_2_valid; // @[regfile.scala:186:7]
wire [4:0] io_arb_read_reqs_2_bits_0 = io_arb_read_reqs_2_bits; // @[regfile.scala:186:7]
wire io_arb_read_reqs_3_valid_0 = io_arb_read_reqs_3_valid; // @[regfile.scala:186:7]
wire [4:0] io_arb_read_reqs_3_bits_0 = io_arb_read_reqs_3_bits; // @[regfile.scala:186:7]
wire io_arb_read_reqs_4_valid_0 = io_arb_read_reqs_4_valid; // @[regfile.scala:186:7]
wire [4:0] io_arb_read_reqs_4_bits_0 = io_arb_read_reqs_4_bits; // @[regfile.scala:186:7]
wire io_arb_read_reqs_5_valid_0 = io_arb_read_reqs_5_valid; // @[regfile.scala:186:7]
wire [4:0] io_arb_read_reqs_5_bits_0 = io_arb_read_reqs_5_bits; // @[regfile.scala:186:7]
wire io_write_ports_0_valid_0 = io_write_ports_0_valid; // @[regfile.scala:186:7]
wire [6:0] io_write_ports_0_bits_addr_0 = io_write_ports_0_bits_addr; // @[regfile.scala:186:7]
wire [19:0] io_write_ports_0_bits_data_0 = io_write_ports_0_bits_data; // @[regfile.scala:186:7]
wire io_write_ports_1_valid_0 = io_write_ports_1_valid; // @[regfile.scala:186:7]
wire [6:0] io_write_ports_1_bits_addr_0 = io_write_ports_1_bits_addr; // @[regfile.scala:186:7]
wire [19:0] io_write_ports_1_bits_data_0 = io_write_ports_1_bits_data; // @[regfile.scala:186:7]
wire io_write_ports_2_valid_0 = io_write_ports_2_valid; // @[regfile.scala:186:7]
wire [6:0] io_write_ports_2_bits_addr_0 = io_write_ports_2_bits_addr; // @[regfile.scala:186:7]
wire [19:0] io_write_ports_2_bits_data_0 = io_write_ports_2_bits_data; // @[regfile.scala:186:7]
wire io_arb_read_reqs_0_ready = 1'h1; // @[regfile.scala:186:7]
wire io_arb_read_reqs_1_ready = 1'h1; // @[regfile.scala:186:7]
wire io_arb_read_reqs_2_ready = 1'h1; // @[regfile.scala:186:7]
wire io_arb_read_reqs_3_ready = 1'h1; // @[regfile.scala:186:7]
wire io_arb_read_reqs_4_ready = 1'h1; // @[regfile.scala:186:7]
wire io_arb_read_reqs_5_ready = 1'h1; // @[regfile.scala:186:7]
wire [19:0] io_rrd_read_resps_0_0; // @[regfile.scala:186:7]
wire [19:0] io_rrd_read_resps_1_0; // @[regfile.scala:186:7]
wire [19:0] io_rrd_read_resps_2_0; // @[regfile.scala:186:7]
wire [19:0] io_rrd_read_resps_3_0; // @[regfile.scala:186:7]
wire [19:0] io_rrd_read_resps_4_0; // @[regfile.scala:186:7]
wire [19:0] io_rrd_read_resps_5_0; // @[regfile.scala:186:7] |
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_34 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}}
regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1)
reg flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock
inst q of Queue2_EgressFlit_34
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.valid, io.in[0].valid
connect q.io.enq.bits.head, io.in[0].bits.head
connect q.io.enq.bits.tail, io.in[0].bits.tail
node _q_io_enq_bits_ingress_id_T = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1)
node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<4>(0he), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4)
node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7)
node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10)
node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<4>(0hc), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13)
node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16)
node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<4>(0hd), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19)
node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22)
node _q_io_enq_bits_ingress_id_T_24 = eq(UInt<4>(0hb), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_25 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_26 = and(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25)
node _q_io_enq_bits_ingress_id_T_27 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_28 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_29 = and(_q_io_enq_bits_ingress_id_T_27, _q_io_enq_bits_ingress_id_T_28)
node _q_io_enq_bits_ingress_id_T_30 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_31 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_32 = and(_q_io_enq_bits_ingress_id_T_30, _q_io_enq_bits_ingress_id_T_31)
node _q_io_enq_bits_ingress_id_T_33 = eq(UInt<4>(0hf), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_34 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_35 = and(_q_io_enq_bits_ingress_id_T_33, _q_io_enq_bits_ingress_id_T_34)
node _q_io_enq_bits_ingress_id_T_36 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0h2), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_37 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0hb), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_38 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h5), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_39 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h3), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_40 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h9), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_41 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<5>(0h6), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_42 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<5>(0ha), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_43 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<5>(0h1), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_44 = mux(_q_io_enq_bits_ingress_id_T_26, UInt<5>(0h8), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_45 = mux(_q_io_enq_bits_ingress_id_T_29, UInt<5>(0h4), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_46 = mux(_q_io_enq_bits_ingress_id_T_32, UInt<5>(0h7), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_47 = mux(_q_io_enq_bits_ingress_id_T_35, UInt<5>(0hc), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_48 = or(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_37)
node _q_io_enq_bits_ingress_id_T_49 = or(_q_io_enq_bits_ingress_id_T_48, _q_io_enq_bits_ingress_id_T_38)
node _q_io_enq_bits_ingress_id_T_50 = or(_q_io_enq_bits_ingress_id_T_49, _q_io_enq_bits_ingress_id_T_39)
node _q_io_enq_bits_ingress_id_T_51 = or(_q_io_enq_bits_ingress_id_T_50, _q_io_enq_bits_ingress_id_T_40)
node _q_io_enq_bits_ingress_id_T_52 = or(_q_io_enq_bits_ingress_id_T_51, _q_io_enq_bits_ingress_id_T_41)
node _q_io_enq_bits_ingress_id_T_53 = or(_q_io_enq_bits_ingress_id_T_52, _q_io_enq_bits_ingress_id_T_42)
node _q_io_enq_bits_ingress_id_T_54 = or(_q_io_enq_bits_ingress_id_T_53, _q_io_enq_bits_ingress_id_T_43)
node _q_io_enq_bits_ingress_id_T_55 = or(_q_io_enq_bits_ingress_id_T_54, _q_io_enq_bits_ingress_id_T_44)
node _q_io_enq_bits_ingress_id_T_56 = or(_q_io_enq_bits_ingress_id_T_55, _q_io_enq_bits_ingress_id_T_45)
node _q_io_enq_bits_ingress_id_T_57 = or(_q_io_enq_bits_ingress_id_T_56, _q_io_enq_bits_ingress_id_T_46)
node _q_io_enq_bits_ingress_id_T_58 = or(_q_io_enq_bits_ingress_id_T_57, _q_io_enq_bits_ingress_id_T_47)
wire _q_io_enq_bits_ingress_id_WIRE : UInt<5>
connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_58
connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE
connect q.io.enq.bits.payload, io.in[0].bits.payload
connect io.out.bits, q.io.deq.bits
connect io.out.valid, q.io.deq.valid
connect q.io.deq.ready, io.out.ready
node _T = eq(q.io.enq.ready, UInt<1>(0h0))
node _T_1 = and(q.io.enq.valid, _T)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0))
connect io.credit_available[0], _io_credit_available_0_T
node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0))
connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T
connect io.channel_status[0].flow, flow
node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail)
when _T_6 :
connect channel_empty, UInt<1>(0h1)
when io.allocs[0].alloc :
connect channel_empty, UInt<1>(0h0)
connect flow, io.allocs[0].flow | module EgressUnit_34( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [36:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [36:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_34 = io_in_0_bits_flow_ingress_node_id == 2'h0; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_285 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_533
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_285( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_533 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCacheBankScheduler_5 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip ways : UInt<16>[8], flip divs : UInt<11>[8], flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { address : UInt<32>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { fail : UInt<1>}}}
inst sourceA of SourceA_5
connect sourceA.clock, clock
connect sourceA.reset, reset
inst sourceB of SourceB_5
connect sourceB.clock, clock
connect sourceB.reset, reset
inst sourceC of SourceC_5
connect sourceC.clock, clock
connect sourceC.reset, reset
inst sourceD of SourceD_5
connect sourceD.clock, clock
connect sourceD.reset, reset
inst sourceE of SourceE_5
connect sourceE.clock, clock
connect sourceE.reset, reset
inst sourceX of SourceX_5
connect sourceX.clock, clock
connect sourceX.reset, reset
connect io.out.a.bits, sourceA.io.a.bits
connect io.out.a.valid, sourceA.io.a.valid
connect sourceA.io.a.ready, io.out.a.ready
connect io.out.c.bits, sourceC.io.c.bits
connect io.out.c.valid, sourceC.io.c.valid
connect sourceC.io.c.ready, io.out.c.ready
connect io.out.e.bits, sourceE.io.e.bits
connect io.out.e.valid, sourceE.io.e.valid
connect sourceE.io.e.ready, io.out.e.ready
connect io.in.b.bits, sourceB.io.b.bits
connect io.in.b.valid, sourceB.io.b.valid
connect sourceB.io.b.ready, io.in.b.ready
connect io.in.d.bits, sourceD.io.d.bits
connect io.in.d.valid, sourceD.io.d.valid
connect sourceD.io.d.ready, io.in.d.ready
connect io.resp.bits, sourceX.io.x.bits
connect io.resp.valid, sourceX.io.x.valid
connect sourceX.io.x.ready, io.resp.ready
inst sinkA of SinkA_5
connect sinkA.clock, clock
connect sinkA.reset, reset
inst sinkC of SinkC_5
connect sinkC.clock, clock
connect sinkC.reset, reset
inst sinkD of SinkD_5
connect sinkD.clock, clock
connect sinkD.reset, reset
inst sinkE of SinkE_5
connect sinkE.clock, clock
connect sinkE.reset, reset
inst sinkX of SinkX_5
connect sinkX.clock, clock
connect sinkX.reset, reset
connect sinkA.io.a, io.in.a
connect sinkC.io.c, io.in.c
connect sinkE.io.e, io.in.e
connect sinkD.io.d, io.out.d
connect sinkX.io.x, io.req
connect io.out.b.ready, UInt<1>(0h1)
inst directory of Directory_5
connect directory.clock, clock
connect directory.reset, reset
inst bankedStore of BankedStore_5
connect bankedStore.clock, clock
connect bankedStore.reset, reset
inst requests of ListBuffer_QueuedRequest_q36_e28_5
connect requests.clock, clock
connect requests.reset, reset
inst mshrs_0 of MSHR_60
connect mshrs_0.clock, clock
connect mshrs_0.reset, reset
inst mshrs_1 of MSHR_61
connect mshrs_1.clock, clock
connect mshrs_1.reset, reset
inst mshrs_2 of MSHR_62
connect mshrs_2.clock, clock
connect mshrs_2.reset, reset
inst mshrs_3 of MSHR_63
connect mshrs_3.clock, clock
connect mshrs_3.reset, reset
inst mshrs_4 of MSHR_64
connect mshrs_4.clock, clock
connect mshrs_4.reset, reset
inst mshrs_5 of MSHR_65
connect mshrs_5.clock, clock
connect mshrs_5.reset, reset
inst mshrs_6 of MSHR_66
connect mshrs_6.clock, clock
connect mshrs_6.reset, reset
inst mshrs_7 of MSHR_67
connect mshrs_7.clock, clock
connect mshrs_7.reset, reset
inst mshrs_8 of MSHR_68
connect mshrs_8.clock, clock
connect mshrs_8.reset, reset
inst mshrs_9 of MSHR_69
connect mshrs_9.clock, clock
connect mshrs_9.reset, reset
inst mshrs_10 of MSHR_70
connect mshrs_10.clock, clock
connect mshrs_10.reset, reset
inst mshrs_11 of MSHR_71
connect mshrs_11.clock, clock
connect mshrs_11.reset, reset
wire nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}
node _mshrs_0_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_0.io.status.bits.set)
node _mshrs_0_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_0_io_sinkc_valid_T)
connect mshrs_0.io.sinkc.valid, _mshrs_0_io_sinkc_valid_T_1
node _mshrs_0_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<1>(0h0))
node _mshrs_0_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_0_io_sinkd_valid_T)
connect mshrs_0.io.sinkd.valid, _mshrs_0_io_sinkd_valid_T_1
node _mshrs_0_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<1>(0h0))
node _mshrs_0_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_0_io_sinke_valid_T)
connect mshrs_0.io.sinke.valid, _mshrs_0_io_sinke_valid_T_1
connect mshrs_0.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_0.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_0.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_0.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_0.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_0.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_0.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_0.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_0.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_0.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_0.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_0.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_0.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_0.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_0.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_0.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_0.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_0.io.nestedwb.tag, nestedwb.tag
connect mshrs_0.io.nestedwb.set, nestedwb.set
node _mshrs_1_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_1.io.status.bits.set)
node _mshrs_1_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_1_io_sinkc_valid_T)
connect mshrs_1.io.sinkc.valid, _mshrs_1_io_sinkc_valid_T_1
node _mshrs_1_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<1>(0h1))
node _mshrs_1_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_1_io_sinkd_valid_T)
connect mshrs_1.io.sinkd.valid, _mshrs_1_io_sinkd_valid_T_1
node _mshrs_1_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<1>(0h1))
node _mshrs_1_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_1_io_sinke_valid_T)
connect mshrs_1.io.sinke.valid, _mshrs_1_io_sinke_valid_T_1
connect mshrs_1.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_1.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_1.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_1.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_1.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_1.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_1.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_1.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_1.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_1.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_1.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_1.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_1.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_1.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_1.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_1.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_1.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_1.io.nestedwb.tag, nestedwb.tag
connect mshrs_1.io.nestedwb.set, nestedwb.set
node _mshrs_2_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_2.io.status.bits.set)
node _mshrs_2_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_2_io_sinkc_valid_T)
connect mshrs_2.io.sinkc.valid, _mshrs_2_io_sinkc_valid_T_1
node _mshrs_2_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<2>(0h2))
node _mshrs_2_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_2_io_sinkd_valid_T)
connect mshrs_2.io.sinkd.valid, _mshrs_2_io_sinkd_valid_T_1
node _mshrs_2_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<2>(0h2))
node _mshrs_2_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_2_io_sinke_valid_T)
connect mshrs_2.io.sinke.valid, _mshrs_2_io_sinke_valid_T_1
connect mshrs_2.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_2.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_2.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_2.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_2.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_2.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_2.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_2.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_2.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_2.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_2.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_2.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_2.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_2.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_2.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_2.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_2.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_2.io.nestedwb.tag, nestedwb.tag
connect mshrs_2.io.nestedwb.set, nestedwb.set
node _mshrs_3_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_3.io.status.bits.set)
node _mshrs_3_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_3_io_sinkc_valid_T)
connect mshrs_3.io.sinkc.valid, _mshrs_3_io_sinkc_valid_T_1
node _mshrs_3_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<2>(0h3))
node _mshrs_3_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_3_io_sinkd_valid_T)
connect mshrs_3.io.sinkd.valid, _mshrs_3_io_sinkd_valid_T_1
node _mshrs_3_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<2>(0h3))
node _mshrs_3_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_3_io_sinke_valid_T)
connect mshrs_3.io.sinke.valid, _mshrs_3_io_sinke_valid_T_1
connect mshrs_3.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_3.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_3.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_3.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_3.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_3.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_3.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_3.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_3.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_3.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_3.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_3.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_3.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_3.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_3.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_3.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_3.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_3.io.nestedwb.tag, nestedwb.tag
connect mshrs_3.io.nestedwb.set, nestedwb.set
node _mshrs_4_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_4.io.status.bits.set)
node _mshrs_4_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_4_io_sinkc_valid_T)
connect mshrs_4.io.sinkc.valid, _mshrs_4_io_sinkc_valid_T_1
node _mshrs_4_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h4))
node _mshrs_4_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_4_io_sinkd_valid_T)
connect mshrs_4.io.sinkd.valid, _mshrs_4_io_sinkd_valid_T_1
node _mshrs_4_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h4))
node _mshrs_4_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_4_io_sinke_valid_T)
connect mshrs_4.io.sinke.valid, _mshrs_4_io_sinke_valid_T_1
connect mshrs_4.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_4.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_4.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_4.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_4.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_4.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_4.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_4.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_4.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_4.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_4.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_4.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_4.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_4.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_4.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_4.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_4.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_4.io.nestedwb.tag, nestedwb.tag
connect mshrs_4.io.nestedwb.set, nestedwb.set
node _mshrs_5_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_5.io.status.bits.set)
node _mshrs_5_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_5_io_sinkc_valid_T)
connect mshrs_5.io.sinkc.valid, _mshrs_5_io_sinkc_valid_T_1
node _mshrs_5_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h5))
node _mshrs_5_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_5_io_sinkd_valid_T)
connect mshrs_5.io.sinkd.valid, _mshrs_5_io_sinkd_valid_T_1
node _mshrs_5_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h5))
node _mshrs_5_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_5_io_sinke_valid_T)
connect mshrs_5.io.sinke.valid, _mshrs_5_io_sinke_valid_T_1
connect mshrs_5.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_5.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_5.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_5.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_5.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_5.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_5.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_5.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_5.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_5.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_5.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_5.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_5.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_5.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_5.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_5.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_5.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_5.io.nestedwb.tag, nestedwb.tag
connect mshrs_5.io.nestedwb.set, nestedwb.set
node _mshrs_6_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_6.io.status.bits.set)
node _mshrs_6_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_6_io_sinkc_valid_T)
connect mshrs_6.io.sinkc.valid, _mshrs_6_io_sinkc_valid_T_1
node _mshrs_6_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h6))
node _mshrs_6_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_6_io_sinkd_valid_T)
connect mshrs_6.io.sinkd.valid, _mshrs_6_io_sinkd_valid_T_1
node _mshrs_6_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h6))
node _mshrs_6_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_6_io_sinke_valid_T)
connect mshrs_6.io.sinke.valid, _mshrs_6_io_sinke_valid_T_1
connect mshrs_6.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_6.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_6.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_6.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_6.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_6.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_6.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_6.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_6.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_6.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_6.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_6.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_6.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_6.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_6.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_6.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_6.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_6.io.nestedwb.tag, nestedwb.tag
connect mshrs_6.io.nestedwb.set, nestedwb.set
node _mshrs_7_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_7.io.status.bits.set)
node _mshrs_7_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_7_io_sinkc_valid_T)
connect mshrs_7.io.sinkc.valid, _mshrs_7_io_sinkc_valid_T_1
node _mshrs_7_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h7))
node _mshrs_7_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_7_io_sinkd_valid_T)
connect mshrs_7.io.sinkd.valid, _mshrs_7_io_sinkd_valid_T_1
node _mshrs_7_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h7))
node _mshrs_7_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_7_io_sinke_valid_T)
connect mshrs_7.io.sinke.valid, _mshrs_7_io_sinke_valid_T_1
connect mshrs_7.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_7.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_7.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_7.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_7.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_7.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_7.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_7.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_7.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_7.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_7.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_7.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_7.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_7.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_7.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_7.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_7.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_7.io.nestedwb.tag, nestedwb.tag
connect mshrs_7.io.nestedwb.set, nestedwb.set
node _mshrs_8_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_8.io.status.bits.set)
node _mshrs_8_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_8_io_sinkc_valid_T)
connect mshrs_8.io.sinkc.valid, _mshrs_8_io_sinkc_valid_T_1
node _mshrs_8_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0h8))
node _mshrs_8_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_8_io_sinkd_valid_T)
connect mshrs_8.io.sinkd.valid, _mshrs_8_io_sinkd_valid_T_1
node _mshrs_8_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0h8))
node _mshrs_8_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_8_io_sinke_valid_T)
connect mshrs_8.io.sinke.valid, _mshrs_8_io_sinke_valid_T_1
connect mshrs_8.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_8.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_8.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_8.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_8.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_8.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_8.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_8.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_8.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_8.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_8.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_8.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_8.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_8.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_8.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_8.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_8.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_8.io.nestedwb.tag, nestedwb.tag
connect mshrs_8.io.nestedwb.set, nestedwb.set
node _mshrs_9_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_9.io.status.bits.set)
node _mshrs_9_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_9_io_sinkc_valid_T)
connect mshrs_9.io.sinkc.valid, _mshrs_9_io_sinkc_valid_T_1
node _mshrs_9_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0h9))
node _mshrs_9_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_9_io_sinkd_valid_T)
connect mshrs_9.io.sinkd.valid, _mshrs_9_io_sinkd_valid_T_1
node _mshrs_9_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0h9))
node _mshrs_9_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_9_io_sinke_valid_T)
connect mshrs_9.io.sinke.valid, _mshrs_9_io_sinke_valid_T_1
connect mshrs_9.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_9.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_9.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_9.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_9.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_9.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_9.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_9.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_9.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_9.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_9.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_9.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_9.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_9.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_9.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_9.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_9.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_9.io.nestedwb.tag, nestedwb.tag
connect mshrs_9.io.nestedwb.set, nestedwb.set
node _mshrs_10_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_10.io.status.bits.set)
node _mshrs_10_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_10_io_sinkc_valid_T)
connect mshrs_10.io.sinkc.valid, _mshrs_10_io_sinkc_valid_T_1
node _mshrs_10_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0ha))
node _mshrs_10_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_10_io_sinkd_valid_T)
connect mshrs_10.io.sinkd.valid, _mshrs_10_io_sinkd_valid_T_1
node _mshrs_10_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0ha))
node _mshrs_10_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_10_io_sinke_valid_T)
connect mshrs_10.io.sinke.valid, _mshrs_10_io_sinke_valid_T_1
connect mshrs_10.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_10.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_10.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_10.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_10.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_10.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_10.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_10.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_10.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_10.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_10.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_10.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_10.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_10.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_10.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_10.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_10.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_10.io.nestedwb.tag, nestedwb.tag
connect mshrs_10.io.nestedwb.set, nestedwb.set
node _mshrs_11_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_11.io.status.bits.set)
node _mshrs_11_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_11_io_sinkc_valid_T)
connect mshrs_11.io.sinkc.valid, _mshrs_11_io_sinkc_valid_T_1
node _mshrs_11_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0hb))
node _mshrs_11_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_11_io_sinkd_valid_T)
connect mshrs_11.io.sinkd.valid, _mshrs_11_io_sinkd_valid_T_1
node _mshrs_11_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0hb))
node _mshrs_11_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_11_io_sinke_valid_T)
connect mshrs_11.io.sinke.valid, _mshrs_11_io_sinke_valid_T_1
connect mshrs_11.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_11.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_11.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_11.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_11.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_11.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_11.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_11.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_11.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_11.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_11.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_11.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_11.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_11.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_11.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_11.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_11.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_11.io.nestedwb.tag, nestedwb.tag
connect mshrs_11.io.nestedwb.set, nestedwb.set
node _mshr_stall_abc_T = eq(mshrs_0.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_1 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T)
node _mshr_stall_abc_T_2 = eq(mshrs_0.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_3 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_2)
node mshr_stall_abc_0 = or(_mshr_stall_abc_T_1, _mshr_stall_abc_T_3)
node _mshr_stall_abc_T_4 = eq(mshrs_1.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_5 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_4)
node _mshr_stall_abc_T_6 = eq(mshrs_1.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_7 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_6)
node mshr_stall_abc_1 = or(_mshr_stall_abc_T_5, _mshr_stall_abc_T_7)
node _mshr_stall_abc_T_8 = eq(mshrs_2.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_9 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_8)
node _mshr_stall_abc_T_10 = eq(mshrs_2.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_11 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_10)
node mshr_stall_abc_2 = or(_mshr_stall_abc_T_9, _mshr_stall_abc_T_11)
node _mshr_stall_abc_T_12 = eq(mshrs_3.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_13 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_12)
node _mshr_stall_abc_T_14 = eq(mshrs_3.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_15 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_14)
node mshr_stall_abc_3 = or(_mshr_stall_abc_T_13, _mshr_stall_abc_T_15)
node _mshr_stall_abc_T_16 = eq(mshrs_4.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_17 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_16)
node _mshr_stall_abc_T_18 = eq(mshrs_4.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_19 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_18)
node mshr_stall_abc_4 = or(_mshr_stall_abc_T_17, _mshr_stall_abc_T_19)
node _mshr_stall_abc_T_20 = eq(mshrs_5.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_21 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_20)
node _mshr_stall_abc_T_22 = eq(mshrs_5.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_23 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_22)
node mshr_stall_abc_5 = or(_mshr_stall_abc_T_21, _mshr_stall_abc_T_23)
node _mshr_stall_abc_T_24 = eq(mshrs_6.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_25 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_24)
node _mshr_stall_abc_T_26 = eq(mshrs_6.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_27 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_26)
node mshr_stall_abc_6 = or(_mshr_stall_abc_T_25, _mshr_stall_abc_T_27)
node _mshr_stall_abc_T_28 = eq(mshrs_7.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_29 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_28)
node _mshr_stall_abc_T_30 = eq(mshrs_7.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_31 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_30)
node mshr_stall_abc_7 = or(_mshr_stall_abc_T_29, _mshr_stall_abc_T_31)
node _mshr_stall_abc_T_32 = eq(mshrs_8.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_33 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_32)
node _mshr_stall_abc_T_34 = eq(mshrs_8.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_35 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_34)
node mshr_stall_abc_8 = or(_mshr_stall_abc_T_33, _mshr_stall_abc_T_35)
node _mshr_stall_abc_T_36 = eq(mshrs_9.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_37 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_36)
node _mshr_stall_abc_T_38 = eq(mshrs_9.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_39 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_38)
node mshr_stall_abc_9 = or(_mshr_stall_abc_T_37, _mshr_stall_abc_T_39)
node _mshr_stall_bc_T = eq(mshrs_10.io.status.bits.set, mshrs_11.io.status.bits.set)
node mshr_stall_bc = and(mshrs_11.io.status.valid, _mshr_stall_bc_T)
node stall_abc_0 = and(mshr_stall_abc_0, mshrs_0.io.status.valid)
node stall_abc_1 = and(mshr_stall_abc_1, mshrs_1.io.status.valid)
node stall_abc_2 = and(mshr_stall_abc_2, mshrs_2.io.status.valid)
node stall_abc_3 = and(mshr_stall_abc_3, mshrs_3.io.status.valid)
node stall_abc_4 = and(mshr_stall_abc_4, mshrs_4.io.status.valid)
node stall_abc_5 = and(mshr_stall_abc_5, mshrs_5.io.status.valid)
node stall_abc_6 = and(mshr_stall_abc_6, mshrs_6.io.status.valid)
node stall_abc_7 = and(mshr_stall_abc_7, mshrs_7.io.status.valid)
node stall_abc_8 = and(mshr_stall_abc_8, mshrs_8.io.status.valid)
node stall_abc_9 = and(mshr_stall_abc_9, mshrs_9.io.status.valid)
node _T = or(stall_abc_0, stall_abc_1)
node _T_1 = or(_T, stall_abc_2)
node _T_2 = or(_T_1, stall_abc_3)
node _T_3 = or(_T_2, stall_abc_4)
node _T_4 = or(_T_3, stall_abc_5)
node _T_5 = or(_T_4, stall_abc_6)
node _T_6 = or(_T_5, stall_abc_7)
node _T_7 = or(_T_6, stall_abc_8)
node _T_8 = or(_T_7, stall_abc_9)
node _mshr_request_T = eq(mshr_stall_abc_0, UInt<1>(0h0))
node _mshr_request_T_1 = and(mshrs_0.io.schedule.valid, _mshr_request_T)
node _mshr_request_T_2 = eq(mshrs_0.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_3 = or(sourceA.io.req.ready, _mshr_request_T_2)
node _mshr_request_T_4 = and(_mshr_request_T_1, _mshr_request_T_3)
node _mshr_request_T_5 = eq(mshrs_0.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_6 = or(sourceB.io.req.ready, _mshr_request_T_5)
node _mshr_request_T_7 = and(_mshr_request_T_4, _mshr_request_T_6)
node _mshr_request_T_8 = eq(mshrs_0.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_9 = or(sourceC.io.req.ready, _mshr_request_T_8)
node _mshr_request_T_10 = and(_mshr_request_T_7, _mshr_request_T_9)
node _mshr_request_T_11 = eq(mshrs_0.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_12 = or(sourceD.io.req.ready, _mshr_request_T_11)
node _mshr_request_T_13 = and(_mshr_request_T_10, _mshr_request_T_12)
node _mshr_request_T_14 = eq(mshrs_0.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_15 = or(sourceE.io.req.ready, _mshr_request_T_14)
node _mshr_request_T_16 = and(_mshr_request_T_13, _mshr_request_T_15)
node _mshr_request_T_17 = eq(mshrs_0.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_18 = or(sourceX.io.req.ready, _mshr_request_T_17)
node _mshr_request_T_19 = and(_mshr_request_T_16, _mshr_request_T_18)
node _mshr_request_T_20 = eq(mshrs_0.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_21 = or(directory.io.write.ready, _mshr_request_T_20)
node _mshr_request_T_22 = and(_mshr_request_T_19, _mshr_request_T_21)
node _mshr_request_T_23 = eq(mshr_stall_abc_1, UInt<1>(0h0))
node _mshr_request_T_24 = and(mshrs_1.io.schedule.valid, _mshr_request_T_23)
node _mshr_request_T_25 = eq(mshrs_1.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_26 = or(sourceA.io.req.ready, _mshr_request_T_25)
node _mshr_request_T_27 = and(_mshr_request_T_24, _mshr_request_T_26)
node _mshr_request_T_28 = eq(mshrs_1.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_29 = or(sourceB.io.req.ready, _mshr_request_T_28)
node _mshr_request_T_30 = and(_mshr_request_T_27, _mshr_request_T_29)
node _mshr_request_T_31 = eq(mshrs_1.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_32 = or(sourceC.io.req.ready, _mshr_request_T_31)
node _mshr_request_T_33 = and(_mshr_request_T_30, _mshr_request_T_32)
node _mshr_request_T_34 = eq(mshrs_1.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_35 = or(sourceD.io.req.ready, _mshr_request_T_34)
node _mshr_request_T_36 = and(_mshr_request_T_33, _mshr_request_T_35)
node _mshr_request_T_37 = eq(mshrs_1.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_38 = or(sourceE.io.req.ready, _mshr_request_T_37)
node _mshr_request_T_39 = and(_mshr_request_T_36, _mshr_request_T_38)
node _mshr_request_T_40 = eq(mshrs_1.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_41 = or(sourceX.io.req.ready, _mshr_request_T_40)
node _mshr_request_T_42 = and(_mshr_request_T_39, _mshr_request_T_41)
node _mshr_request_T_43 = eq(mshrs_1.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_44 = or(directory.io.write.ready, _mshr_request_T_43)
node _mshr_request_T_45 = and(_mshr_request_T_42, _mshr_request_T_44)
node _mshr_request_T_46 = eq(mshr_stall_abc_2, UInt<1>(0h0))
node _mshr_request_T_47 = and(mshrs_2.io.schedule.valid, _mshr_request_T_46)
node _mshr_request_T_48 = eq(mshrs_2.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_49 = or(sourceA.io.req.ready, _mshr_request_T_48)
node _mshr_request_T_50 = and(_mshr_request_T_47, _mshr_request_T_49)
node _mshr_request_T_51 = eq(mshrs_2.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_52 = or(sourceB.io.req.ready, _mshr_request_T_51)
node _mshr_request_T_53 = and(_mshr_request_T_50, _mshr_request_T_52)
node _mshr_request_T_54 = eq(mshrs_2.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_55 = or(sourceC.io.req.ready, _mshr_request_T_54)
node _mshr_request_T_56 = and(_mshr_request_T_53, _mshr_request_T_55)
node _mshr_request_T_57 = eq(mshrs_2.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_58 = or(sourceD.io.req.ready, _mshr_request_T_57)
node _mshr_request_T_59 = and(_mshr_request_T_56, _mshr_request_T_58)
node _mshr_request_T_60 = eq(mshrs_2.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_61 = or(sourceE.io.req.ready, _mshr_request_T_60)
node _mshr_request_T_62 = and(_mshr_request_T_59, _mshr_request_T_61)
node _mshr_request_T_63 = eq(mshrs_2.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_64 = or(sourceX.io.req.ready, _mshr_request_T_63)
node _mshr_request_T_65 = and(_mshr_request_T_62, _mshr_request_T_64)
node _mshr_request_T_66 = eq(mshrs_2.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_67 = or(directory.io.write.ready, _mshr_request_T_66)
node _mshr_request_T_68 = and(_mshr_request_T_65, _mshr_request_T_67)
node _mshr_request_T_69 = eq(mshr_stall_abc_3, UInt<1>(0h0))
node _mshr_request_T_70 = and(mshrs_3.io.schedule.valid, _mshr_request_T_69)
node _mshr_request_T_71 = eq(mshrs_3.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_72 = or(sourceA.io.req.ready, _mshr_request_T_71)
node _mshr_request_T_73 = and(_mshr_request_T_70, _mshr_request_T_72)
node _mshr_request_T_74 = eq(mshrs_3.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_75 = or(sourceB.io.req.ready, _mshr_request_T_74)
node _mshr_request_T_76 = and(_mshr_request_T_73, _mshr_request_T_75)
node _mshr_request_T_77 = eq(mshrs_3.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_78 = or(sourceC.io.req.ready, _mshr_request_T_77)
node _mshr_request_T_79 = and(_mshr_request_T_76, _mshr_request_T_78)
node _mshr_request_T_80 = eq(mshrs_3.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_81 = or(sourceD.io.req.ready, _mshr_request_T_80)
node _mshr_request_T_82 = and(_mshr_request_T_79, _mshr_request_T_81)
node _mshr_request_T_83 = eq(mshrs_3.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_84 = or(sourceE.io.req.ready, _mshr_request_T_83)
node _mshr_request_T_85 = and(_mshr_request_T_82, _mshr_request_T_84)
node _mshr_request_T_86 = eq(mshrs_3.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_87 = or(sourceX.io.req.ready, _mshr_request_T_86)
node _mshr_request_T_88 = and(_mshr_request_T_85, _mshr_request_T_87)
node _mshr_request_T_89 = eq(mshrs_3.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_90 = or(directory.io.write.ready, _mshr_request_T_89)
node _mshr_request_T_91 = and(_mshr_request_T_88, _mshr_request_T_90)
node _mshr_request_T_92 = eq(mshr_stall_abc_4, UInt<1>(0h0))
node _mshr_request_T_93 = and(mshrs_4.io.schedule.valid, _mshr_request_T_92)
node _mshr_request_T_94 = eq(mshrs_4.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_95 = or(sourceA.io.req.ready, _mshr_request_T_94)
node _mshr_request_T_96 = and(_mshr_request_T_93, _mshr_request_T_95)
node _mshr_request_T_97 = eq(mshrs_4.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_98 = or(sourceB.io.req.ready, _mshr_request_T_97)
node _mshr_request_T_99 = and(_mshr_request_T_96, _mshr_request_T_98)
node _mshr_request_T_100 = eq(mshrs_4.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_101 = or(sourceC.io.req.ready, _mshr_request_T_100)
node _mshr_request_T_102 = and(_mshr_request_T_99, _mshr_request_T_101)
node _mshr_request_T_103 = eq(mshrs_4.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_104 = or(sourceD.io.req.ready, _mshr_request_T_103)
node _mshr_request_T_105 = and(_mshr_request_T_102, _mshr_request_T_104)
node _mshr_request_T_106 = eq(mshrs_4.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_107 = or(sourceE.io.req.ready, _mshr_request_T_106)
node _mshr_request_T_108 = and(_mshr_request_T_105, _mshr_request_T_107)
node _mshr_request_T_109 = eq(mshrs_4.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_110 = or(sourceX.io.req.ready, _mshr_request_T_109)
node _mshr_request_T_111 = and(_mshr_request_T_108, _mshr_request_T_110)
node _mshr_request_T_112 = eq(mshrs_4.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_113 = or(directory.io.write.ready, _mshr_request_T_112)
node _mshr_request_T_114 = and(_mshr_request_T_111, _mshr_request_T_113)
node _mshr_request_T_115 = eq(mshr_stall_abc_5, UInt<1>(0h0))
node _mshr_request_T_116 = and(mshrs_5.io.schedule.valid, _mshr_request_T_115)
node _mshr_request_T_117 = eq(mshrs_5.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_118 = or(sourceA.io.req.ready, _mshr_request_T_117)
node _mshr_request_T_119 = and(_mshr_request_T_116, _mshr_request_T_118)
node _mshr_request_T_120 = eq(mshrs_5.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_121 = or(sourceB.io.req.ready, _mshr_request_T_120)
node _mshr_request_T_122 = and(_mshr_request_T_119, _mshr_request_T_121)
node _mshr_request_T_123 = eq(mshrs_5.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_124 = or(sourceC.io.req.ready, _mshr_request_T_123)
node _mshr_request_T_125 = and(_mshr_request_T_122, _mshr_request_T_124)
node _mshr_request_T_126 = eq(mshrs_5.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_127 = or(sourceD.io.req.ready, _mshr_request_T_126)
node _mshr_request_T_128 = and(_mshr_request_T_125, _mshr_request_T_127)
node _mshr_request_T_129 = eq(mshrs_5.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_130 = or(sourceE.io.req.ready, _mshr_request_T_129)
node _mshr_request_T_131 = and(_mshr_request_T_128, _mshr_request_T_130)
node _mshr_request_T_132 = eq(mshrs_5.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_133 = or(sourceX.io.req.ready, _mshr_request_T_132)
node _mshr_request_T_134 = and(_mshr_request_T_131, _mshr_request_T_133)
node _mshr_request_T_135 = eq(mshrs_5.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_136 = or(directory.io.write.ready, _mshr_request_T_135)
node _mshr_request_T_137 = and(_mshr_request_T_134, _mshr_request_T_136)
node _mshr_request_T_138 = eq(mshr_stall_abc_6, UInt<1>(0h0))
node _mshr_request_T_139 = and(mshrs_6.io.schedule.valid, _mshr_request_T_138)
node _mshr_request_T_140 = eq(mshrs_6.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_141 = or(sourceA.io.req.ready, _mshr_request_T_140)
node _mshr_request_T_142 = and(_mshr_request_T_139, _mshr_request_T_141)
node _mshr_request_T_143 = eq(mshrs_6.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_144 = or(sourceB.io.req.ready, _mshr_request_T_143)
node _mshr_request_T_145 = and(_mshr_request_T_142, _mshr_request_T_144)
node _mshr_request_T_146 = eq(mshrs_6.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_147 = or(sourceC.io.req.ready, _mshr_request_T_146)
node _mshr_request_T_148 = and(_mshr_request_T_145, _mshr_request_T_147)
node _mshr_request_T_149 = eq(mshrs_6.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_150 = or(sourceD.io.req.ready, _mshr_request_T_149)
node _mshr_request_T_151 = and(_mshr_request_T_148, _mshr_request_T_150)
node _mshr_request_T_152 = eq(mshrs_6.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_153 = or(sourceE.io.req.ready, _mshr_request_T_152)
node _mshr_request_T_154 = and(_mshr_request_T_151, _mshr_request_T_153)
node _mshr_request_T_155 = eq(mshrs_6.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_156 = or(sourceX.io.req.ready, _mshr_request_T_155)
node _mshr_request_T_157 = and(_mshr_request_T_154, _mshr_request_T_156)
node _mshr_request_T_158 = eq(mshrs_6.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_159 = or(directory.io.write.ready, _mshr_request_T_158)
node _mshr_request_T_160 = and(_mshr_request_T_157, _mshr_request_T_159)
node _mshr_request_T_161 = eq(mshr_stall_abc_7, UInt<1>(0h0))
node _mshr_request_T_162 = and(mshrs_7.io.schedule.valid, _mshr_request_T_161)
node _mshr_request_T_163 = eq(mshrs_7.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_164 = or(sourceA.io.req.ready, _mshr_request_T_163)
node _mshr_request_T_165 = and(_mshr_request_T_162, _mshr_request_T_164)
node _mshr_request_T_166 = eq(mshrs_7.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_167 = or(sourceB.io.req.ready, _mshr_request_T_166)
node _mshr_request_T_168 = and(_mshr_request_T_165, _mshr_request_T_167)
node _mshr_request_T_169 = eq(mshrs_7.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_170 = or(sourceC.io.req.ready, _mshr_request_T_169)
node _mshr_request_T_171 = and(_mshr_request_T_168, _mshr_request_T_170)
node _mshr_request_T_172 = eq(mshrs_7.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_173 = or(sourceD.io.req.ready, _mshr_request_T_172)
node _mshr_request_T_174 = and(_mshr_request_T_171, _mshr_request_T_173)
node _mshr_request_T_175 = eq(mshrs_7.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_176 = or(sourceE.io.req.ready, _mshr_request_T_175)
node _mshr_request_T_177 = and(_mshr_request_T_174, _mshr_request_T_176)
node _mshr_request_T_178 = eq(mshrs_7.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_179 = or(sourceX.io.req.ready, _mshr_request_T_178)
node _mshr_request_T_180 = and(_mshr_request_T_177, _mshr_request_T_179)
node _mshr_request_T_181 = eq(mshrs_7.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_182 = or(directory.io.write.ready, _mshr_request_T_181)
node _mshr_request_T_183 = and(_mshr_request_T_180, _mshr_request_T_182)
node _mshr_request_T_184 = eq(mshr_stall_abc_8, UInt<1>(0h0))
node _mshr_request_T_185 = and(mshrs_8.io.schedule.valid, _mshr_request_T_184)
node _mshr_request_T_186 = eq(mshrs_8.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_187 = or(sourceA.io.req.ready, _mshr_request_T_186)
node _mshr_request_T_188 = and(_mshr_request_T_185, _mshr_request_T_187)
node _mshr_request_T_189 = eq(mshrs_8.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_190 = or(sourceB.io.req.ready, _mshr_request_T_189)
node _mshr_request_T_191 = and(_mshr_request_T_188, _mshr_request_T_190)
node _mshr_request_T_192 = eq(mshrs_8.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_193 = or(sourceC.io.req.ready, _mshr_request_T_192)
node _mshr_request_T_194 = and(_mshr_request_T_191, _mshr_request_T_193)
node _mshr_request_T_195 = eq(mshrs_8.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_196 = or(sourceD.io.req.ready, _mshr_request_T_195)
node _mshr_request_T_197 = and(_mshr_request_T_194, _mshr_request_T_196)
node _mshr_request_T_198 = eq(mshrs_8.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_199 = or(sourceE.io.req.ready, _mshr_request_T_198)
node _mshr_request_T_200 = and(_mshr_request_T_197, _mshr_request_T_199)
node _mshr_request_T_201 = eq(mshrs_8.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_202 = or(sourceX.io.req.ready, _mshr_request_T_201)
node _mshr_request_T_203 = and(_mshr_request_T_200, _mshr_request_T_202)
node _mshr_request_T_204 = eq(mshrs_8.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_205 = or(directory.io.write.ready, _mshr_request_T_204)
node _mshr_request_T_206 = and(_mshr_request_T_203, _mshr_request_T_205)
node _mshr_request_T_207 = eq(mshr_stall_abc_9, UInt<1>(0h0))
node _mshr_request_T_208 = and(mshrs_9.io.schedule.valid, _mshr_request_T_207)
node _mshr_request_T_209 = eq(mshrs_9.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_210 = or(sourceA.io.req.ready, _mshr_request_T_209)
node _mshr_request_T_211 = and(_mshr_request_T_208, _mshr_request_T_210)
node _mshr_request_T_212 = eq(mshrs_9.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_213 = or(sourceB.io.req.ready, _mshr_request_T_212)
node _mshr_request_T_214 = and(_mshr_request_T_211, _mshr_request_T_213)
node _mshr_request_T_215 = eq(mshrs_9.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_216 = or(sourceC.io.req.ready, _mshr_request_T_215)
node _mshr_request_T_217 = and(_mshr_request_T_214, _mshr_request_T_216)
node _mshr_request_T_218 = eq(mshrs_9.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_219 = or(sourceD.io.req.ready, _mshr_request_T_218)
node _mshr_request_T_220 = and(_mshr_request_T_217, _mshr_request_T_219)
node _mshr_request_T_221 = eq(mshrs_9.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_222 = or(sourceE.io.req.ready, _mshr_request_T_221)
node _mshr_request_T_223 = and(_mshr_request_T_220, _mshr_request_T_222)
node _mshr_request_T_224 = eq(mshrs_9.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_225 = or(sourceX.io.req.ready, _mshr_request_T_224)
node _mshr_request_T_226 = and(_mshr_request_T_223, _mshr_request_T_225)
node _mshr_request_T_227 = eq(mshrs_9.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_228 = or(directory.io.write.ready, _mshr_request_T_227)
node _mshr_request_T_229 = and(_mshr_request_T_226, _mshr_request_T_228)
node _mshr_request_T_230 = eq(mshr_stall_bc, UInt<1>(0h0))
node _mshr_request_T_231 = and(mshrs_10.io.schedule.valid, _mshr_request_T_230)
node _mshr_request_T_232 = eq(mshrs_10.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_233 = or(sourceA.io.req.ready, _mshr_request_T_232)
node _mshr_request_T_234 = and(_mshr_request_T_231, _mshr_request_T_233)
node _mshr_request_T_235 = eq(mshrs_10.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_236 = or(sourceB.io.req.ready, _mshr_request_T_235)
node _mshr_request_T_237 = and(_mshr_request_T_234, _mshr_request_T_236)
node _mshr_request_T_238 = eq(mshrs_10.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_239 = or(sourceC.io.req.ready, _mshr_request_T_238)
node _mshr_request_T_240 = and(_mshr_request_T_237, _mshr_request_T_239)
node _mshr_request_T_241 = eq(mshrs_10.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_242 = or(sourceD.io.req.ready, _mshr_request_T_241)
node _mshr_request_T_243 = and(_mshr_request_T_240, _mshr_request_T_242)
node _mshr_request_T_244 = eq(mshrs_10.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_245 = or(sourceE.io.req.ready, _mshr_request_T_244)
node _mshr_request_T_246 = and(_mshr_request_T_243, _mshr_request_T_245)
node _mshr_request_T_247 = eq(mshrs_10.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_248 = or(sourceX.io.req.ready, _mshr_request_T_247)
node _mshr_request_T_249 = and(_mshr_request_T_246, _mshr_request_T_248)
node _mshr_request_T_250 = eq(mshrs_10.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_251 = or(directory.io.write.ready, _mshr_request_T_250)
node _mshr_request_T_252 = and(_mshr_request_T_249, _mshr_request_T_251)
node _mshr_request_T_253 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _mshr_request_T_254 = and(mshrs_11.io.schedule.valid, _mshr_request_T_253)
node _mshr_request_T_255 = eq(mshrs_11.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_256 = or(sourceA.io.req.ready, _mshr_request_T_255)
node _mshr_request_T_257 = and(_mshr_request_T_254, _mshr_request_T_256)
node _mshr_request_T_258 = eq(mshrs_11.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_259 = or(sourceB.io.req.ready, _mshr_request_T_258)
node _mshr_request_T_260 = and(_mshr_request_T_257, _mshr_request_T_259)
node _mshr_request_T_261 = eq(mshrs_11.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_262 = or(sourceC.io.req.ready, _mshr_request_T_261)
node _mshr_request_T_263 = and(_mshr_request_T_260, _mshr_request_T_262)
node _mshr_request_T_264 = eq(mshrs_11.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_265 = or(sourceD.io.req.ready, _mshr_request_T_264)
node _mshr_request_T_266 = and(_mshr_request_T_263, _mshr_request_T_265)
node _mshr_request_T_267 = eq(mshrs_11.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_268 = or(sourceE.io.req.ready, _mshr_request_T_267)
node _mshr_request_T_269 = and(_mshr_request_T_266, _mshr_request_T_268)
node _mshr_request_T_270 = eq(mshrs_11.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_271 = or(sourceX.io.req.ready, _mshr_request_T_270)
node _mshr_request_T_272 = and(_mshr_request_T_269, _mshr_request_T_271)
node _mshr_request_T_273 = eq(mshrs_11.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_274 = or(directory.io.write.ready, _mshr_request_T_273)
node _mshr_request_T_275 = and(_mshr_request_T_272, _mshr_request_T_274)
node mshr_request_lo_lo_hi = cat(_mshr_request_T_68, _mshr_request_T_45)
node mshr_request_lo_lo = cat(mshr_request_lo_lo_hi, _mshr_request_T_22)
node mshr_request_lo_hi_hi = cat(_mshr_request_T_137, _mshr_request_T_114)
node mshr_request_lo_hi = cat(mshr_request_lo_hi_hi, _mshr_request_T_91)
node mshr_request_lo = cat(mshr_request_lo_hi, mshr_request_lo_lo)
node mshr_request_hi_lo_hi = cat(_mshr_request_T_206, _mshr_request_T_183)
node mshr_request_hi_lo = cat(mshr_request_hi_lo_hi, _mshr_request_T_160)
node mshr_request_hi_hi_hi = cat(_mshr_request_T_275, _mshr_request_T_252)
node mshr_request_hi_hi = cat(mshr_request_hi_hi_hi, _mshr_request_T_229)
node mshr_request_hi = cat(mshr_request_hi_hi, mshr_request_hi_lo)
node mshr_request = cat(mshr_request_hi, mshr_request_lo)
regreset robin_filter : UInt<12>, clock, reset, UInt<12>(0h0)
node _robin_request_T = and(mshr_request, robin_filter)
node robin_request = cat(mshr_request, _robin_request_T)
node _mshr_selectOH2_T = shl(robin_request, 1)
node _mshr_selectOH2_T_1 = bits(_mshr_selectOH2_T, 23, 0)
node _mshr_selectOH2_T_2 = or(robin_request, _mshr_selectOH2_T_1)
node _mshr_selectOH2_T_3 = shl(_mshr_selectOH2_T_2, 2)
node _mshr_selectOH2_T_4 = bits(_mshr_selectOH2_T_3, 23, 0)
node _mshr_selectOH2_T_5 = or(_mshr_selectOH2_T_2, _mshr_selectOH2_T_4)
node _mshr_selectOH2_T_6 = shl(_mshr_selectOH2_T_5, 4)
node _mshr_selectOH2_T_7 = bits(_mshr_selectOH2_T_6, 23, 0)
node _mshr_selectOH2_T_8 = or(_mshr_selectOH2_T_5, _mshr_selectOH2_T_7)
node _mshr_selectOH2_T_9 = shl(_mshr_selectOH2_T_8, 8)
node _mshr_selectOH2_T_10 = bits(_mshr_selectOH2_T_9, 23, 0)
node _mshr_selectOH2_T_11 = or(_mshr_selectOH2_T_8, _mshr_selectOH2_T_10)
node _mshr_selectOH2_T_12 = shl(_mshr_selectOH2_T_11, 16)
node _mshr_selectOH2_T_13 = bits(_mshr_selectOH2_T_12, 23, 0)
node _mshr_selectOH2_T_14 = or(_mshr_selectOH2_T_11, _mshr_selectOH2_T_13)
node _mshr_selectOH2_T_15 = bits(_mshr_selectOH2_T_14, 23, 0)
node _mshr_selectOH2_T_16 = shl(_mshr_selectOH2_T_15, 1)
node _mshr_selectOH2_T_17 = not(_mshr_selectOH2_T_16)
node mshr_selectOH2 = and(_mshr_selectOH2_T_17, robin_request)
node _mshr_selectOH_T = bits(mshr_selectOH2, 23, 12)
node _mshr_selectOH_T_1 = bits(mshr_selectOH2, 11, 0)
node mshr_selectOH = or(_mshr_selectOH_T, _mshr_selectOH_T_1)
node mshr_select_hi = bits(mshr_selectOH, 11, 8)
node mshr_select_lo = bits(mshr_selectOH, 7, 0)
node _mshr_select_T = orr(mshr_select_hi)
node _mshr_select_T_1 = or(mshr_select_hi, mshr_select_lo)
node mshr_select_hi_1 = bits(_mshr_select_T_1, 7, 4)
node mshr_select_lo_1 = bits(_mshr_select_T_1, 3, 0)
node _mshr_select_T_2 = orr(mshr_select_hi_1)
node _mshr_select_T_3 = or(mshr_select_hi_1, mshr_select_lo_1)
node mshr_select_hi_2 = bits(_mshr_select_T_3, 3, 2)
node mshr_select_lo_2 = bits(_mshr_select_T_3, 1, 0)
node _mshr_select_T_4 = orr(mshr_select_hi_2)
node _mshr_select_T_5 = or(mshr_select_hi_2, mshr_select_lo_2)
node _mshr_select_T_6 = bits(_mshr_select_T_5, 1, 1)
node _mshr_select_T_7 = cat(_mshr_select_T_4, _mshr_select_T_6)
node _mshr_select_T_8 = cat(_mshr_select_T_2, _mshr_select_T_7)
node mshr_select = cat(_mshr_select_T, _mshr_select_T_8)
node _schedule_T = bits(mshr_selectOH, 0, 0)
node _schedule_T_1 = bits(mshr_selectOH, 1, 1)
node _schedule_T_2 = bits(mshr_selectOH, 2, 2)
node _schedule_T_3 = bits(mshr_selectOH, 3, 3)
node _schedule_T_4 = bits(mshr_selectOH, 4, 4)
node _schedule_T_5 = bits(mshr_selectOH, 5, 5)
node _schedule_T_6 = bits(mshr_selectOH, 6, 6)
node _schedule_T_7 = bits(mshr_selectOH, 7, 7)
node _schedule_T_8 = bits(mshr_selectOH, 8, 8)
node _schedule_T_9 = bits(mshr_selectOH, 9, 9)
node _schedule_T_10 = bits(mshr_selectOH, 10, 10)
node _schedule_T_11 = bits(mshr_selectOH, 11, 11)
wire schedule : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}
node _schedule_T_12 = mux(_schedule_T, mshrs_0.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_13 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_14 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_15 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_16 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_17 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_18 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_19 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_20 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_21 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_22 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_23 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_24 = or(_schedule_T_12, _schedule_T_13)
node _schedule_T_25 = or(_schedule_T_24, _schedule_T_14)
node _schedule_T_26 = or(_schedule_T_25, _schedule_T_15)
node _schedule_T_27 = or(_schedule_T_26, _schedule_T_16)
node _schedule_T_28 = or(_schedule_T_27, _schedule_T_17)
node _schedule_T_29 = or(_schedule_T_28, _schedule_T_18)
node _schedule_T_30 = or(_schedule_T_29, _schedule_T_19)
node _schedule_T_31 = or(_schedule_T_30, _schedule_T_20)
node _schedule_T_32 = or(_schedule_T_31, _schedule_T_21)
node _schedule_T_33 = or(_schedule_T_32, _schedule_T_22)
node _schedule_T_34 = or(_schedule_T_33, _schedule_T_23)
wire _schedule_WIRE : UInt<1>
connect _schedule_WIRE, _schedule_T_34
connect schedule.reload, _schedule_WIRE
wire _schedule_WIRE_1 : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}
wire _schedule_WIRE_2 : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}
wire _schedule_WIRE_3 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
node _schedule_T_35 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_36 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_37 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_38 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_39 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_40 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_41 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_42 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_43 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_44 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_45 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_46 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_47 = or(_schedule_T_35, _schedule_T_36)
node _schedule_T_48 = or(_schedule_T_47, _schedule_T_37)
node _schedule_T_49 = or(_schedule_T_48, _schedule_T_38)
node _schedule_T_50 = or(_schedule_T_49, _schedule_T_39)
node _schedule_T_51 = or(_schedule_T_50, _schedule_T_40)
node _schedule_T_52 = or(_schedule_T_51, _schedule_T_41)
node _schedule_T_53 = or(_schedule_T_52, _schedule_T_42)
node _schedule_T_54 = or(_schedule_T_53, _schedule_T_43)
node _schedule_T_55 = or(_schedule_T_54, _schedule_T_44)
node _schedule_T_56 = or(_schedule_T_55, _schedule_T_45)
node _schedule_T_57 = or(_schedule_T_56, _schedule_T_46)
wire _schedule_WIRE_4 : UInt<9>
connect _schedule_WIRE_4, _schedule_T_57
connect _schedule_WIRE_3.tag, _schedule_WIRE_4
node _schedule_T_58 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_59 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_60 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_61 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_62 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_63 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_64 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_65 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_66 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_67 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_68 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_69 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_70 = or(_schedule_T_58, _schedule_T_59)
node _schedule_T_71 = or(_schedule_T_70, _schedule_T_60)
node _schedule_T_72 = or(_schedule_T_71, _schedule_T_61)
node _schedule_T_73 = or(_schedule_T_72, _schedule_T_62)
node _schedule_T_74 = or(_schedule_T_73, _schedule_T_63)
node _schedule_T_75 = or(_schedule_T_74, _schedule_T_64)
node _schedule_T_76 = or(_schedule_T_75, _schedule_T_65)
node _schedule_T_77 = or(_schedule_T_76, _schedule_T_66)
node _schedule_T_78 = or(_schedule_T_77, _schedule_T_67)
node _schedule_T_79 = or(_schedule_T_78, _schedule_T_68)
node _schedule_T_80 = or(_schedule_T_79, _schedule_T_69)
wire _schedule_WIRE_5 : UInt<1>
connect _schedule_WIRE_5, _schedule_T_80
connect _schedule_WIRE_3.clients, _schedule_WIRE_5
node _schedule_T_81 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_82 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_83 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_84 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_85 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_86 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_87 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_88 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_89 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_90 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_91 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_92 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_93 = or(_schedule_T_81, _schedule_T_82)
node _schedule_T_94 = or(_schedule_T_93, _schedule_T_83)
node _schedule_T_95 = or(_schedule_T_94, _schedule_T_84)
node _schedule_T_96 = or(_schedule_T_95, _schedule_T_85)
node _schedule_T_97 = or(_schedule_T_96, _schedule_T_86)
node _schedule_T_98 = or(_schedule_T_97, _schedule_T_87)
node _schedule_T_99 = or(_schedule_T_98, _schedule_T_88)
node _schedule_T_100 = or(_schedule_T_99, _schedule_T_89)
node _schedule_T_101 = or(_schedule_T_100, _schedule_T_90)
node _schedule_T_102 = or(_schedule_T_101, _schedule_T_91)
node _schedule_T_103 = or(_schedule_T_102, _schedule_T_92)
wire _schedule_WIRE_6 : UInt<2>
connect _schedule_WIRE_6, _schedule_T_103
connect _schedule_WIRE_3.state, _schedule_WIRE_6
node _schedule_T_104 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_105 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_106 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_107 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_108 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_109 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_110 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_111 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_112 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_113 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_114 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_115 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_116 = or(_schedule_T_104, _schedule_T_105)
node _schedule_T_117 = or(_schedule_T_116, _schedule_T_106)
node _schedule_T_118 = or(_schedule_T_117, _schedule_T_107)
node _schedule_T_119 = or(_schedule_T_118, _schedule_T_108)
node _schedule_T_120 = or(_schedule_T_119, _schedule_T_109)
node _schedule_T_121 = or(_schedule_T_120, _schedule_T_110)
node _schedule_T_122 = or(_schedule_T_121, _schedule_T_111)
node _schedule_T_123 = or(_schedule_T_122, _schedule_T_112)
node _schedule_T_124 = or(_schedule_T_123, _schedule_T_113)
node _schedule_T_125 = or(_schedule_T_124, _schedule_T_114)
node _schedule_T_126 = or(_schedule_T_125, _schedule_T_115)
wire _schedule_WIRE_7 : UInt<1>
connect _schedule_WIRE_7, _schedule_T_126
connect _schedule_WIRE_3.dirty, _schedule_WIRE_7
connect _schedule_WIRE_2.data, _schedule_WIRE_3
node _schedule_T_127 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_128 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_129 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_130 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_131 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_132 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_133 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_134 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_135 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_136 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_137 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_138 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_139 = or(_schedule_T_127, _schedule_T_128)
node _schedule_T_140 = or(_schedule_T_139, _schedule_T_129)
node _schedule_T_141 = or(_schedule_T_140, _schedule_T_130)
node _schedule_T_142 = or(_schedule_T_141, _schedule_T_131)
node _schedule_T_143 = or(_schedule_T_142, _schedule_T_132)
node _schedule_T_144 = or(_schedule_T_143, _schedule_T_133)
node _schedule_T_145 = or(_schedule_T_144, _schedule_T_134)
node _schedule_T_146 = or(_schedule_T_145, _schedule_T_135)
node _schedule_T_147 = or(_schedule_T_146, _schedule_T_136)
node _schedule_T_148 = or(_schedule_T_147, _schedule_T_137)
node _schedule_T_149 = or(_schedule_T_148, _schedule_T_138)
wire _schedule_WIRE_8 : UInt<4>
connect _schedule_WIRE_8, _schedule_T_149
connect _schedule_WIRE_2.way, _schedule_WIRE_8
node _schedule_T_150 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_151 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_152 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_153 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_154 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_155 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_156 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_157 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_158 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_159 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_160 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_161 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_162 = or(_schedule_T_150, _schedule_T_151)
node _schedule_T_163 = or(_schedule_T_162, _schedule_T_152)
node _schedule_T_164 = or(_schedule_T_163, _schedule_T_153)
node _schedule_T_165 = or(_schedule_T_164, _schedule_T_154)
node _schedule_T_166 = or(_schedule_T_165, _schedule_T_155)
node _schedule_T_167 = or(_schedule_T_166, _schedule_T_156)
node _schedule_T_168 = or(_schedule_T_167, _schedule_T_157)
node _schedule_T_169 = or(_schedule_T_168, _schedule_T_158)
node _schedule_T_170 = or(_schedule_T_169, _schedule_T_159)
node _schedule_T_171 = or(_schedule_T_170, _schedule_T_160)
node _schedule_T_172 = or(_schedule_T_171, _schedule_T_161)
wire _schedule_WIRE_9 : UInt<11>
connect _schedule_WIRE_9, _schedule_T_172
connect _schedule_WIRE_2.set, _schedule_WIRE_9
connect _schedule_WIRE_1.bits, _schedule_WIRE_2
node _schedule_T_173 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_174 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_175 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_176 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_177 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_178 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_179 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_180 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_181 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_182 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_183 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_184 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_185 = or(_schedule_T_173, _schedule_T_174)
node _schedule_T_186 = or(_schedule_T_185, _schedule_T_175)
node _schedule_T_187 = or(_schedule_T_186, _schedule_T_176)
node _schedule_T_188 = or(_schedule_T_187, _schedule_T_177)
node _schedule_T_189 = or(_schedule_T_188, _schedule_T_178)
node _schedule_T_190 = or(_schedule_T_189, _schedule_T_179)
node _schedule_T_191 = or(_schedule_T_190, _schedule_T_180)
node _schedule_T_192 = or(_schedule_T_191, _schedule_T_181)
node _schedule_T_193 = or(_schedule_T_192, _schedule_T_182)
node _schedule_T_194 = or(_schedule_T_193, _schedule_T_183)
node _schedule_T_195 = or(_schedule_T_194, _schedule_T_184)
wire _schedule_WIRE_10 : UInt<1>
connect _schedule_WIRE_10, _schedule_T_195
connect _schedule_WIRE_1.valid, _schedule_WIRE_10
connect schedule.dir, _schedule_WIRE_1
wire _schedule_WIRE_11 : { valid : UInt<1>, bits : { fail : UInt<1>}}
wire _schedule_WIRE_12 : { fail : UInt<1>}
node _schedule_T_196 = mux(_schedule_T, mshrs_0.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_197 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_198 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_199 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_200 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_201 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_202 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_203 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_204 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_205 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_206 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_207 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_208 = or(_schedule_T_196, _schedule_T_197)
node _schedule_T_209 = or(_schedule_T_208, _schedule_T_198)
node _schedule_T_210 = or(_schedule_T_209, _schedule_T_199)
node _schedule_T_211 = or(_schedule_T_210, _schedule_T_200)
node _schedule_T_212 = or(_schedule_T_211, _schedule_T_201)
node _schedule_T_213 = or(_schedule_T_212, _schedule_T_202)
node _schedule_T_214 = or(_schedule_T_213, _schedule_T_203)
node _schedule_T_215 = or(_schedule_T_214, _schedule_T_204)
node _schedule_T_216 = or(_schedule_T_215, _schedule_T_205)
node _schedule_T_217 = or(_schedule_T_216, _schedule_T_206)
node _schedule_T_218 = or(_schedule_T_217, _schedule_T_207)
wire _schedule_WIRE_13 : UInt<1>
connect _schedule_WIRE_13, _schedule_T_218
connect _schedule_WIRE_12.fail, _schedule_WIRE_13
connect _schedule_WIRE_11.bits, _schedule_WIRE_12
node _schedule_T_219 = mux(_schedule_T, mshrs_0.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_220 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_221 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_222 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_223 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_224 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_225 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_226 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_227 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_228 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_229 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_230 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_231 = or(_schedule_T_219, _schedule_T_220)
node _schedule_T_232 = or(_schedule_T_231, _schedule_T_221)
node _schedule_T_233 = or(_schedule_T_232, _schedule_T_222)
node _schedule_T_234 = or(_schedule_T_233, _schedule_T_223)
node _schedule_T_235 = or(_schedule_T_234, _schedule_T_224)
node _schedule_T_236 = or(_schedule_T_235, _schedule_T_225)
node _schedule_T_237 = or(_schedule_T_236, _schedule_T_226)
node _schedule_T_238 = or(_schedule_T_237, _schedule_T_227)
node _schedule_T_239 = or(_schedule_T_238, _schedule_T_228)
node _schedule_T_240 = or(_schedule_T_239, _schedule_T_229)
node _schedule_T_241 = or(_schedule_T_240, _schedule_T_230)
wire _schedule_WIRE_14 : UInt<1>
connect _schedule_WIRE_14, _schedule_T_241
connect _schedule_WIRE_11.valid, _schedule_WIRE_14
connect schedule.x, _schedule_WIRE_11
wire _schedule_WIRE_15 : { valid : UInt<1>, bits : { sink : UInt<3>}}
wire _schedule_WIRE_16 : { sink : UInt<3>}
node _schedule_T_242 = mux(_schedule_T, mshrs_0.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_243 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_244 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_245 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_246 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_247 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_248 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_249 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_250 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_251 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_252 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_253 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_254 = or(_schedule_T_242, _schedule_T_243)
node _schedule_T_255 = or(_schedule_T_254, _schedule_T_244)
node _schedule_T_256 = or(_schedule_T_255, _schedule_T_245)
node _schedule_T_257 = or(_schedule_T_256, _schedule_T_246)
node _schedule_T_258 = or(_schedule_T_257, _schedule_T_247)
node _schedule_T_259 = or(_schedule_T_258, _schedule_T_248)
node _schedule_T_260 = or(_schedule_T_259, _schedule_T_249)
node _schedule_T_261 = or(_schedule_T_260, _schedule_T_250)
node _schedule_T_262 = or(_schedule_T_261, _schedule_T_251)
node _schedule_T_263 = or(_schedule_T_262, _schedule_T_252)
node _schedule_T_264 = or(_schedule_T_263, _schedule_T_253)
wire _schedule_WIRE_17 : UInt<3>
connect _schedule_WIRE_17, _schedule_T_264
connect _schedule_WIRE_16.sink, _schedule_WIRE_17
connect _schedule_WIRE_15.bits, _schedule_WIRE_16
node _schedule_T_265 = mux(_schedule_T, mshrs_0.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_266 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_267 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_268 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_269 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_270 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_271 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_272 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_273 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_274 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_275 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_276 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_277 = or(_schedule_T_265, _schedule_T_266)
node _schedule_T_278 = or(_schedule_T_277, _schedule_T_267)
node _schedule_T_279 = or(_schedule_T_278, _schedule_T_268)
node _schedule_T_280 = or(_schedule_T_279, _schedule_T_269)
node _schedule_T_281 = or(_schedule_T_280, _schedule_T_270)
node _schedule_T_282 = or(_schedule_T_281, _schedule_T_271)
node _schedule_T_283 = or(_schedule_T_282, _schedule_T_272)
node _schedule_T_284 = or(_schedule_T_283, _schedule_T_273)
node _schedule_T_285 = or(_schedule_T_284, _schedule_T_274)
node _schedule_T_286 = or(_schedule_T_285, _schedule_T_275)
node _schedule_T_287 = or(_schedule_T_286, _schedule_T_276)
wire _schedule_WIRE_18 : UInt<1>
connect _schedule_WIRE_18, _schedule_T_287
connect _schedule_WIRE_15.valid, _schedule_WIRE_18
connect schedule.e, _schedule_WIRE_15
wire _schedule_WIRE_19 : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}
wire _schedule_WIRE_20 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}
node _schedule_T_288 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_289 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_290 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_291 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_292 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_293 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_294 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_295 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_296 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_297 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_298 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_299 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_300 = or(_schedule_T_288, _schedule_T_289)
node _schedule_T_301 = or(_schedule_T_300, _schedule_T_290)
node _schedule_T_302 = or(_schedule_T_301, _schedule_T_291)
node _schedule_T_303 = or(_schedule_T_302, _schedule_T_292)
node _schedule_T_304 = or(_schedule_T_303, _schedule_T_293)
node _schedule_T_305 = or(_schedule_T_304, _schedule_T_294)
node _schedule_T_306 = or(_schedule_T_305, _schedule_T_295)
node _schedule_T_307 = or(_schedule_T_306, _schedule_T_296)
node _schedule_T_308 = or(_schedule_T_307, _schedule_T_297)
node _schedule_T_309 = or(_schedule_T_308, _schedule_T_298)
node _schedule_T_310 = or(_schedule_T_309, _schedule_T_299)
wire _schedule_WIRE_21 : UInt<1>
connect _schedule_WIRE_21, _schedule_T_310
connect _schedule_WIRE_20.bad, _schedule_WIRE_21
node _schedule_T_311 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_312 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_313 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_314 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_315 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_316 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_317 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_318 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_319 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_320 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_321 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_322 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_323 = or(_schedule_T_311, _schedule_T_312)
node _schedule_T_324 = or(_schedule_T_323, _schedule_T_313)
node _schedule_T_325 = or(_schedule_T_324, _schedule_T_314)
node _schedule_T_326 = or(_schedule_T_325, _schedule_T_315)
node _schedule_T_327 = or(_schedule_T_326, _schedule_T_316)
node _schedule_T_328 = or(_schedule_T_327, _schedule_T_317)
node _schedule_T_329 = or(_schedule_T_328, _schedule_T_318)
node _schedule_T_330 = or(_schedule_T_329, _schedule_T_319)
node _schedule_T_331 = or(_schedule_T_330, _schedule_T_320)
node _schedule_T_332 = or(_schedule_T_331, _schedule_T_321)
node _schedule_T_333 = or(_schedule_T_332, _schedule_T_322)
wire _schedule_WIRE_22 : UInt<4>
connect _schedule_WIRE_22, _schedule_T_333
connect _schedule_WIRE_20.way, _schedule_WIRE_22
node _schedule_T_334 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_335 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_336 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_337 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_338 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_339 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_340 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_341 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_342 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_343 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_344 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_345 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_346 = or(_schedule_T_334, _schedule_T_335)
node _schedule_T_347 = or(_schedule_T_346, _schedule_T_336)
node _schedule_T_348 = or(_schedule_T_347, _schedule_T_337)
node _schedule_T_349 = or(_schedule_T_348, _schedule_T_338)
node _schedule_T_350 = or(_schedule_T_349, _schedule_T_339)
node _schedule_T_351 = or(_schedule_T_350, _schedule_T_340)
node _schedule_T_352 = or(_schedule_T_351, _schedule_T_341)
node _schedule_T_353 = or(_schedule_T_352, _schedule_T_342)
node _schedule_T_354 = or(_schedule_T_353, _schedule_T_343)
node _schedule_T_355 = or(_schedule_T_354, _schedule_T_344)
node _schedule_T_356 = or(_schedule_T_355, _schedule_T_345)
wire _schedule_WIRE_23 : UInt<4>
connect _schedule_WIRE_23, _schedule_T_356
connect _schedule_WIRE_20.sink, _schedule_WIRE_23
node _schedule_T_357 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_358 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_359 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_360 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_361 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_362 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_363 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_364 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_365 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_366 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_367 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_368 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_369 = or(_schedule_T_357, _schedule_T_358)
node _schedule_T_370 = or(_schedule_T_369, _schedule_T_359)
node _schedule_T_371 = or(_schedule_T_370, _schedule_T_360)
node _schedule_T_372 = or(_schedule_T_371, _schedule_T_361)
node _schedule_T_373 = or(_schedule_T_372, _schedule_T_362)
node _schedule_T_374 = or(_schedule_T_373, _schedule_T_363)
node _schedule_T_375 = or(_schedule_T_374, _schedule_T_364)
node _schedule_T_376 = or(_schedule_T_375, _schedule_T_365)
node _schedule_T_377 = or(_schedule_T_376, _schedule_T_366)
node _schedule_T_378 = or(_schedule_T_377, _schedule_T_367)
node _schedule_T_379 = or(_schedule_T_378, _schedule_T_368)
wire _schedule_WIRE_24 : UInt<11>
connect _schedule_WIRE_24, _schedule_T_379
connect _schedule_WIRE_20.set, _schedule_WIRE_24
node _schedule_T_380 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_381 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_382 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_383 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_384 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_385 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_386 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_387 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_388 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_389 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_390 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_391 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_392 = or(_schedule_T_380, _schedule_T_381)
node _schedule_T_393 = or(_schedule_T_392, _schedule_T_382)
node _schedule_T_394 = or(_schedule_T_393, _schedule_T_383)
node _schedule_T_395 = or(_schedule_T_394, _schedule_T_384)
node _schedule_T_396 = or(_schedule_T_395, _schedule_T_385)
node _schedule_T_397 = or(_schedule_T_396, _schedule_T_386)
node _schedule_T_398 = or(_schedule_T_397, _schedule_T_387)
node _schedule_T_399 = or(_schedule_T_398, _schedule_T_388)
node _schedule_T_400 = or(_schedule_T_399, _schedule_T_389)
node _schedule_T_401 = or(_schedule_T_400, _schedule_T_390)
node _schedule_T_402 = or(_schedule_T_401, _schedule_T_391)
wire _schedule_WIRE_25 : UInt<6>
connect _schedule_WIRE_25, _schedule_T_402
connect _schedule_WIRE_20.put, _schedule_WIRE_25
node _schedule_T_403 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_404 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_405 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_406 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_407 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_408 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_409 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_410 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_411 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_412 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_413 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_414 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_415 = or(_schedule_T_403, _schedule_T_404)
node _schedule_T_416 = or(_schedule_T_415, _schedule_T_405)
node _schedule_T_417 = or(_schedule_T_416, _schedule_T_406)
node _schedule_T_418 = or(_schedule_T_417, _schedule_T_407)
node _schedule_T_419 = or(_schedule_T_418, _schedule_T_408)
node _schedule_T_420 = or(_schedule_T_419, _schedule_T_409)
node _schedule_T_421 = or(_schedule_T_420, _schedule_T_410)
node _schedule_T_422 = or(_schedule_T_421, _schedule_T_411)
node _schedule_T_423 = or(_schedule_T_422, _schedule_T_412)
node _schedule_T_424 = or(_schedule_T_423, _schedule_T_413)
node _schedule_T_425 = or(_schedule_T_424, _schedule_T_414)
wire _schedule_WIRE_26 : UInt<6>
connect _schedule_WIRE_26, _schedule_T_425
connect _schedule_WIRE_20.offset, _schedule_WIRE_26
node _schedule_T_426 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_427 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_428 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_429 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_430 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_431 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_432 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_433 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_434 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_435 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_436 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_437 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_438 = or(_schedule_T_426, _schedule_T_427)
node _schedule_T_439 = or(_schedule_T_438, _schedule_T_428)
node _schedule_T_440 = or(_schedule_T_439, _schedule_T_429)
node _schedule_T_441 = or(_schedule_T_440, _schedule_T_430)
node _schedule_T_442 = or(_schedule_T_441, _schedule_T_431)
node _schedule_T_443 = or(_schedule_T_442, _schedule_T_432)
node _schedule_T_444 = or(_schedule_T_443, _schedule_T_433)
node _schedule_T_445 = or(_schedule_T_444, _schedule_T_434)
node _schedule_T_446 = or(_schedule_T_445, _schedule_T_435)
node _schedule_T_447 = or(_schedule_T_446, _schedule_T_436)
node _schedule_T_448 = or(_schedule_T_447, _schedule_T_437)
wire _schedule_WIRE_27 : UInt<9>
connect _schedule_WIRE_27, _schedule_T_448
connect _schedule_WIRE_20.tag, _schedule_WIRE_27
node _schedule_T_449 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_450 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_451 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_452 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_453 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_454 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_455 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_456 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_457 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_458 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_459 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_460 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_461 = or(_schedule_T_449, _schedule_T_450)
node _schedule_T_462 = or(_schedule_T_461, _schedule_T_451)
node _schedule_T_463 = or(_schedule_T_462, _schedule_T_452)
node _schedule_T_464 = or(_schedule_T_463, _schedule_T_453)
node _schedule_T_465 = or(_schedule_T_464, _schedule_T_454)
node _schedule_T_466 = or(_schedule_T_465, _schedule_T_455)
node _schedule_T_467 = or(_schedule_T_466, _schedule_T_456)
node _schedule_T_468 = or(_schedule_T_467, _schedule_T_457)
node _schedule_T_469 = or(_schedule_T_468, _schedule_T_458)
node _schedule_T_470 = or(_schedule_T_469, _schedule_T_459)
node _schedule_T_471 = or(_schedule_T_470, _schedule_T_460)
wire _schedule_WIRE_28 : UInt<6>
connect _schedule_WIRE_28, _schedule_T_471
connect _schedule_WIRE_20.source, _schedule_WIRE_28
node _schedule_T_472 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_473 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_474 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_475 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_476 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_477 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_478 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_479 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_480 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_481 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_482 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_483 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_484 = or(_schedule_T_472, _schedule_T_473)
node _schedule_T_485 = or(_schedule_T_484, _schedule_T_474)
node _schedule_T_486 = or(_schedule_T_485, _schedule_T_475)
node _schedule_T_487 = or(_schedule_T_486, _schedule_T_476)
node _schedule_T_488 = or(_schedule_T_487, _schedule_T_477)
node _schedule_T_489 = or(_schedule_T_488, _schedule_T_478)
node _schedule_T_490 = or(_schedule_T_489, _schedule_T_479)
node _schedule_T_491 = or(_schedule_T_490, _schedule_T_480)
node _schedule_T_492 = or(_schedule_T_491, _schedule_T_481)
node _schedule_T_493 = or(_schedule_T_492, _schedule_T_482)
node _schedule_T_494 = or(_schedule_T_493, _schedule_T_483)
wire _schedule_WIRE_29 : UInt<3>
connect _schedule_WIRE_29, _schedule_T_494
connect _schedule_WIRE_20.size, _schedule_WIRE_29
node _schedule_T_495 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_496 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_497 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_498 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_499 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_500 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_501 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_502 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_503 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_504 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_505 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_506 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_507 = or(_schedule_T_495, _schedule_T_496)
node _schedule_T_508 = or(_schedule_T_507, _schedule_T_497)
node _schedule_T_509 = or(_schedule_T_508, _schedule_T_498)
node _schedule_T_510 = or(_schedule_T_509, _schedule_T_499)
node _schedule_T_511 = or(_schedule_T_510, _schedule_T_500)
node _schedule_T_512 = or(_schedule_T_511, _schedule_T_501)
node _schedule_T_513 = or(_schedule_T_512, _schedule_T_502)
node _schedule_T_514 = or(_schedule_T_513, _schedule_T_503)
node _schedule_T_515 = or(_schedule_T_514, _schedule_T_504)
node _schedule_T_516 = or(_schedule_T_515, _schedule_T_505)
node _schedule_T_517 = or(_schedule_T_516, _schedule_T_506)
wire _schedule_WIRE_30 : UInt<3>
connect _schedule_WIRE_30, _schedule_T_517
connect _schedule_WIRE_20.param, _schedule_WIRE_30
node _schedule_T_518 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_519 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_520 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_521 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_522 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_523 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_524 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_525 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_526 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_527 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_528 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_529 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_530 = or(_schedule_T_518, _schedule_T_519)
node _schedule_T_531 = or(_schedule_T_530, _schedule_T_520)
node _schedule_T_532 = or(_schedule_T_531, _schedule_T_521)
node _schedule_T_533 = or(_schedule_T_532, _schedule_T_522)
node _schedule_T_534 = or(_schedule_T_533, _schedule_T_523)
node _schedule_T_535 = or(_schedule_T_534, _schedule_T_524)
node _schedule_T_536 = or(_schedule_T_535, _schedule_T_525)
node _schedule_T_537 = or(_schedule_T_536, _schedule_T_526)
node _schedule_T_538 = or(_schedule_T_537, _schedule_T_527)
node _schedule_T_539 = or(_schedule_T_538, _schedule_T_528)
node _schedule_T_540 = or(_schedule_T_539, _schedule_T_529)
wire _schedule_WIRE_31 : UInt<3>
connect _schedule_WIRE_31, _schedule_T_540
connect _schedule_WIRE_20.opcode, _schedule_WIRE_31
node _schedule_T_541 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_542 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_543 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_544 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_545 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_546 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_547 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_548 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_549 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_550 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_551 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_552 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_553 = or(_schedule_T_541, _schedule_T_542)
node _schedule_T_554 = or(_schedule_T_553, _schedule_T_543)
node _schedule_T_555 = or(_schedule_T_554, _schedule_T_544)
node _schedule_T_556 = or(_schedule_T_555, _schedule_T_545)
node _schedule_T_557 = or(_schedule_T_556, _schedule_T_546)
node _schedule_T_558 = or(_schedule_T_557, _schedule_T_547)
node _schedule_T_559 = or(_schedule_T_558, _schedule_T_548)
node _schedule_T_560 = or(_schedule_T_559, _schedule_T_549)
node _schedule_T_561 = or(_schedule_T_560, _schedule_T_550)
node _schedule_T_562 = or(_schedule_T_561, _schedule_T_551)
node _schedule_T_563 = or(_schedule_T_562, _schedule_T_552)
wire _schedule_WIRE_32 : UInt<1>
connect _schedule_WIRE_32, _schedule_T_563
connect _schedule_WIRE_20.control, _schedule_WIRE_32
wire _schedule_WIRE_33 : UInt<1>[3]
node _schedule_T_564 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_565 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_566 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_567 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_568 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_569 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_570 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_571 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_572 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_573 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_574 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_575 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_576 = or(_schedule_T_564, _schedule_T_565)
node _schedule_T_577 = or(_schedule_T_576, _schedule_T_566)
node _schedule_T_578 = or(_schedule_T_577, _schedule_T_567)
node _schedule_T_579 = or(_schedule_T_578, _schedule_T_568)
node _schedule_T_580 = or(_schedule_T_579, _schedule_T_569)
node _schedule_T_581 = or(_schedule_T_580, _schedule_T_570)
node _schedule_T_582 = or(_schedule_T_581, _schedule_T_571)
node _schedule_T_583 = or(_schedule_T_582, _schedule_T_572)
node _schedule_T_584 = or(_schedule_T_583, _schedule_T_573)
node _schedule_T_585 = or(_schedule_T_584, _schedule_T_574)
node _schedule_T_586 = or(_schedule_T_585, _schedule_T_575)
wire _schedule_WIRE_34 : UInt<1>
connect _schedule_WIRE_34, _schedule_T_586
connect _schedule_WIRE_33[0], _schedule_WIRE_34
node _schedule_T_587 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_588 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_589 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_590 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_591 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_592 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_593 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_594 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_595 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_596 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_597 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_598 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_599 = or(_schedule_T_587, _schedule_T_588)
node _schedule_T_600 = or(_schedule_T_599, _schedule_T_589)
node _schedule_T_601 = or(_schedule_T_600, _schedule_T_590)
node _schedule_T_602 = or(_schedule_T_601, _schedule_T_591)
node _schedule_T_603 = or(_schedule_T_602, _schedule_T_592)
node _schedule_T_604 = or(_schedule_T_603, _schedule_T_593)
node _schedule_T_605 = or(_schedule_T_604, _schedule_T_594)
node _schedule_T_606 = or(_schedule_T_605, _schedule_T_595)
node _schedule_T_607 = or(_schedule_T_606, _schedule_T_596)
node _schedule_T_608 = or(_schedule_T_607, _schedule_T_597)
node _schedule_T_609 = or(_schedule_T_608, _schedule_T_598)
wire _schedule_WIRE_35 : UInt<1>
connect _schedule_WIRE_35, _schedule_T_609
connect _schedule_WIRE_33[1], _schedule_WIRE_35
node _schedule_T_610 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_611 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_612 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_613 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_614 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_615 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_616 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_617 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_618 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_619 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_620 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_621 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_622 = or(_schedule_T_610, _schedule_T_611)
node _schedule_T_623 = or(_schedule_T_622, _schedule_T_612)
node _schedule_T_624 = or(_schedule_T_623, _schedule_T_613)
node _schedule_T_625 = or(_schedule_T_624, _schedule_T_614)
node _schedule_T_626 = or(_schedule_T_625, _schedule_T_615)
node _schedule_T_627 = or(_schedule_T_626, _schedule_T_616)
node _schedule_T_628 = or(_schedule_T_627, _schedule_T_617)
node _schedule_T_629 = or(_schedule_T_628, _schedule_T_618)
node _schedule_T_630 = or(_schedule_T_629, _schedule_T_619)
node _schedule_T_631 = or(_schedule_T_630, _schedule_T_620)
node _schedule_T_632 = or(_schedule_T_631, _schedule_T_621)
wire _schedule_WIRE_36 : UInt<1>
connect _schedule_WIRE_36, _schedule_T_632
connect _schedule_WIRE_33[2], _schedule_WIRE_36
connect _schedule_WIRE_20.prio, _schedule_WIRE_33
connect _schedule_WIRE_19.bits, _schedule_WIRE_20
node _schedule_T_633 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_634 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_635 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_636 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_637 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_638 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_639 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_640 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_641 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_642 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_643 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_644 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_645 = or(_schedule_T_633, _schedule_T_634)
node _schedule_T_646 = or(_schedule_T_645, _schedule_T_635)
node _schedule_T_647 = or(_schedule_T_646, _schedule_T_636)
node _schedule_T_648 = or(_schedule_T_647, _schedule_T_637)
node _schedule_T_649 = or(_schedule_T_648, _schedule_T_638)
node _schedule_T_650 = or(_schedule_T_649, _schedule_T_639)
node _schedule_T_651 = or(_schedule_T_650, _schedule_T_640)
node _schedule_T_652 = or(_schedule_T_651, _schedule_T_641)
node _schedule_T_653 = or(_schedule_T_652, _schedule_T_642)
node _schedule_T_654 = or(_schedule_T_653, _schedule_T_643)
node _schedule_T_655 = or(_schedule_T_654, _schedule_T_644)
wire _schedule_WIRE_37 : UInt<1>
connect _schedule_WIRE_37, _schedule_T_655
connect _schedule_WIRE_19.valid, _schedule_WIRE_37
connect schedule.d, _schedule_WIRE_19
wire _schedule_WIRE_38 : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}
wire _schedule_WIRE_39 : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}
node _schedule_T_656 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_657 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_658 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_659 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_660 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_661 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_662 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_663 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_664 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_665 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_666 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_667 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_668 = or(_schedule_T_656, _schedule_T_657)
node _schedule_T_669 = or(_schedule_T_668, _schedule_T_658)
node _schedule_T_670 = or(_schedule_T_669, _schedule_T_659)
node _schedule_T_671 = or(_schedule_T_670, _schedule_T_660)
node _schedule_T_672 = or(_schedule_T_671, _schedule_T_661)
node _schedule_T_673 = or(_schedule_T_672, _schedule_T_662)
node _schedule_T_674 = or(_schedule_T_673, _schedule_T_663)
node _schedule_T_675 = or(_schedule_T_674, _schedule_T_664)
node _schedule_T_676 = or(_schedule_T_675, _schedule_T_665)
node _schedule_T_677 = or(_schedule_T_676, _schedule_T_666)
node _schedule_T_678 = or(_schedule_T_677, _schedule_T_667)
wire _schedule_WIRE_40 : UInt<1>
connect _schedule_WIRE_40, _schedule_T_678
connect _schedule_WIRE_39.dirty, _schedule_WIRE_40
node _schedule_T_679 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_680 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_681 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_682 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_683 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_684 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_685 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_686 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_687 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_688 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_689 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_690 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_691 = or(_schedule_T_679, _schedule_T_680)
node _schedule_T_692 = or(_schedule_T_691, _schedule_T_681)
node _schedule_T_693 = or(_schedule_T_692, _schedule_T_682)
node _schedule_T_694 = or(_schedule_T_693, _schedule_T_683)
node _schedule_T_695 = or(_schedule_T_694, _schedule_T_684)
node _schedule_T_696 = or(_schedule_T_695, _schedule_T_685)
node _schedule_T_697 = or(_schedule_T_696, _schedule_T_686)
node _schedule_T_698 = or(_schedule_T_697, _schedule_T_687)
node _schedule_T_699 = or(_schedule_T_698, _schedule_T_688)
node _schedule_T_700 = or(_schedule_T_699, _schedule_T_689)
node _schedule_T_701 = or(_schedule_T_700, _schedule_T_690)
wire _schedule_WIRE_41 : UInt<4>
connect _schedule_WIRE_41, _schedule_T_701
connect _schedule_WIRE_39.way, _schedule_WIRE_41
node _schedule_T_702 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_703 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_704 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_705 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_706 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_707 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_708 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_709 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_710 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_711 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_712 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_713 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_714 = or(_schedule_T_702, _schedule_T_703)
node _schedule_T_715 = or(_schedule_T_714, _schedule_T_704)
node _schedule_T_716 = or(_schedule_T_715, _schedule_T_705)
node _schedule_T_717 = or(_schedule_T_716, _schedule_T_706)
node _schedule_T_718 = or(_schedule_T_717, _schedule_T_707)
node _schedule_T_719 = or(_schedule_T_718, _schedule_T_708)
node _schedule_T_720 = or(_schedule_T_719, _schedule_T_709)
node _schedule_T_721 = or(_schedule_T_720, _schedule_T_710)
node _schedule_T_722 = or(_schedule_T_721, _schedule_T_711)
node _schedule_T_723 = or(_schedule_T_722, _schedule_T_712)
node _schedule_T_724 = or(_schedule_T_723, _schedule_T_713)
wire _schedule_WIRE_42 : UInt<11>
connect _schedule_WIRE_42, _schedule_T_724
connect _schedule_WIRE_39.set, _schedule_WIRE_42
node _schedule_T_725 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_726 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_727 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_728 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_729 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_730 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_731 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_732 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_733 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_734 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_735 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_736 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_737 = or(_schedule_T_725, _schedule_T_726)
node _schedule_T_738 = or(_schedule_T_737, _schedule_T_727)
node _schedule_T_739 = or(_schedule_T_738, _schedule_T_728)
node _schedule_T_740 = or(_schedule_T_739, _schedule_T_729)
node _schedule_T_741 = or(_schedule_T_740, _schedule_T_730)
node _schedule_T_742 = or(_schedule_T_741, _schedule_T_731)
node _schedule_T_743 = or(_schedule_T_742, _schedule_T_732)
node _schedule_T_744 = or(_schedule_T_743, _schedule_T_733)
node _schedule_T_745 = or(_schedule_T_744, _schedule_T_734)
node _schedule_T_746 = or(_schedule_T_745, _schedule_T_735)
node _schedule_T_747 = or(_schedule_T_746, _schedule_T_736)
wire _schedule_WIRE_43 : UInt<9>
connect _schedule_WIRE_43, _schedule_T_747
connect _schedule_WIRE_39.tag, _schedule_WIRE_43
node _schedule_T_748 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_749 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_750 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_751 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_752 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_753 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_754 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_755 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_756 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_757 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_758 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_759 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_760 = or(_schedule_T_748, _schedule_T_749)
node _schedule_T_761 = or(_schedule_T_760, _schedule_T_750)
node _schedule_T_762 = or(_schedule_T_761, _schedule_T_751)
node _schedule_T_763 = or(_schedule_T_762, _schedule_T_752)
node _schedule_T_764 = or(_schedule_T_763, _schedule_T_753)
node _schedule_T_765 = or(_schedule_T_764, _schedule_T_754)
node _schedule_T_766 = or(_schedule_T_765, _schedule_T_755)
node _schedule_T_767 = or(_schedule_T_766, _schedule_T_756)
node _schedule_T_768 = or(_schedule_T_767, _schedule_T_757)
node _schedule_T_769 = or(_schedule_T_768, _schedule_T_758)
node _schedule_T_770 = or(_schedule_T_769, _schedule_T_759)
wire _schedule_WIRE_44 : UInt<4>
connect _schedule_WIRE_44, _schedule_T_770
connect _schedule_WIRE_39.source, _schedule_WIRE_44
node _schedule_T_771 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_772 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_773 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_774 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_775 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_776 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_777 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_778 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_779 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_780 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_781 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_782 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_783 = or(_schedule_T_771, _schedule_T_772)
node _schedule_T_784 = or(_schedule_T_783, _schedule_T_773)
node _schedule_T_785 = or(_schedule_T_784, _schedule_T_774)
node _schedule_T_786 = or(_schedule_T_785, _schedule_T_775)
node _schedule_T_787 = or(_schedule_T_786, _schedule_T_776)
node _schedule_T_788 = or(_schedule_T_787, _schedule_T_777)
node _schedule_T_789 = or(_schedule_T_788, _schedule_T_778)
node _schedule_T_790 = or(_schedule_T_789, _schedule_T_779)
node _schedule_T_791 = or(_schedule_T_790, _schedule_T_780)
node _schedule_T_792 = or(_schedule_T_791, _schedule_T_781)
node _schedule_T_793 = or(_schedule_T_792, _schedule_T_782)
wire _schedule_WIRE_45 : UInt<3>
connect _schedule_WIRE_45, _schedule_T_793
connect _schedule_WIRE_39.param, _schedule_WIRE_45
node _schedule_T_794 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_795 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_796 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_797 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_798 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_799 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_800 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_801 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_802 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_803 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_804 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_805 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_806 = or(_schedule_T_794, _schedule_T_795)
node _schedule_T_807 = or(_schedule_T_806, _schedule_T_796)
node _schedule_T_808 = or(_schedule_T_807, _schedule_T_797)
node _schedule_T_809 = or(_schedule_T_808, _schedule_T_798)
node _schedule_T_810 = or(_schedule_T_809, _schedule_T_799)
node _schedule_T_811 = or(_schedule_T_810, _schedule_T_800)
node _schedule_T_812 = or(_schedule_T_811, _schedule_T_801)
node _schedule_T_813 = or(_schedule_T_812, _schedule_T_802)
node _schedule_T_814 = or(_schedule_T_813, _schedule_T_803)
node _schedule_T_815 = or(_schedule_T_814, _schedule_T_804)
node _schedule_T_816 = or(_schedule_T_815, _schedule_T_805)
wire _schedule_WIRE_46 : UInt<3>
connect _schedule_WIRE_46, _schedule_T_816
connect _schedule_WIRE_39.opcode, _schedule_WIRE_46
connect _schedule_WIRE_38.bits, _schedule_WIRE_39
node _schedule_T_817 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_818 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_819 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_820 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_821 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_822 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_823 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_824 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_825 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_826 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_827 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_828 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_829 = or(_schedule_T_817, _schedule_T_818)
node _schedule_T_830 = or(_schedule_T_829, _schedule_T_819)
node _schedule_T_831 = or(_schedule_T_830, _schedule_T_820)
node _schedule_T_832 = or(_schedule_T_831, _schedule_T_821)
node _schedule_T_833 = or(_schedule_T_832, _schedule_T_822)
node _schedule_T_834 = or(_schedule_T_833, _schedule_T_823)
node _schedule_T_835 = or(_schedule_T_834, _schedule_T_824)
node _schedule_T_836 = or(_schedule_T_835, _schedule_T_825)
node _schedule_T_837 = or(_schedule_T_836, _schedule_T_826)
node _schedule_T_838 = or(_schedule_T_837, _schedule_T_827)
node _schedule_T_839 = or(_schedule_T_838, _schedule_T_828)
wire _schedule_WIRE_47 : UInt<1>
connect _schedule_WIRE_47, _schedule_T_839
connect _schedule_WIRE_38.valid, _schedule_WIRE_47
connect schedule.c, _schedule_WIRE_38
wire _schedule_WIRE_48 : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}
wire _schedule_WIRE_49 : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}
node _schedule_T_840 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_841 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_842 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_843 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_844 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_845 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_846 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_847 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_848 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_849 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_850 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_851 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_852 = or(_schedule_T_840, _schedule_T_841)
node _schedule_T_853 = or(_schedule_T_852, _schedule_T_842)
node _schedule_T_854 = or(_schedule_T_853, _schedule_T_843)
node _schedule_T_855 = or(_schedule_T_854, _schedule_T_844)
node _schedule_T_856 = or(_schedule_T_855, _schedule_T_845)
node _schedule_T_857 = or(_schedule_T_856, _schedule_T_846)
node _schedule_T_858 = or(_schedule_T_857, _schedule_T_847)
node _schedule_T_859 = or(_schedule_T_858, _schedule_T_848)
node _schedule_T_860 = or(_schedule_T_859, _schedule_T_849)
node _schedule_T_861 = or(_schedule_T_860, _schedule_T_850)
node _schedule_T_862 = or(_schedule_T_861, _schedule_T_851)
wire _schedule_WIRE_50 : UInt<1>
connect _schedule_WIRE_50, _schedule_T_862
connect _schedule_WIRE_49.clients, _schedule_WIRE_50
node _schedule_T_863 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_864 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_865 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_866 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_867 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_868 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_869 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_870 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_871 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_872 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_873 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_874 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_875 = or(_schedule_T_863, _schedule_T_864)
node _schedule_T_876 = or(_schedule_T_875, _schedule_T_865)
node _schedule_T_877 = or(_schedule_T_876, _schedule_T_866)
node _schedule_T_878 = or(_schedule_T_877, _schedule_T_867)
node _schedule_T_879 = or(_schedule_T_878, _schedule_T_868)
node _schedule_T_880 = or(_schedule_T_879, _schedule_T_869)
node _schedule_T_881 = or(_schedule_T_880, _schedule_T_870)
node _schedule_T_882 = or(_schedule_T_881, _schedule_T_871)
node _schedule_T_883 = or(_schedule_T_882, _schedule_T_872)
node _schedule_T_884 = or(_schedule_T_883, _schedule_T_873)
node _schedule_T_885 = or(_schedule_T_884, _schedule_T_874)
wire _schedule_WIRE_51 : UInt<11>
connect _schedule_WIRE_51, _schedule_T_885
connect _schedule_WIRE_49.set, _schedule_WIRE_51
node _schedule_T_886 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_887 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_888 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_889 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_890 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_891 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_892 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_893 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_894 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_895 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_896 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_897 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_898 = or(_schedule_T_886, _schedule_T_887)
node _schedule_T_899 = or(_schedule_T_898, _schedule_T_888)
node _schedule_T_900 = or(_schedule_T_899, _schedule_T_889)
node _schedule_T_901 = or(_schedule_T_900, _schedule_T_890)
node _schedule_T_902 = or(_schedule_T_901, _schedule_T_891)
node _schedule_T_903 = or(_schedule_T_902, _schedule_T_892)
node _schedule_T_904 = or(_schedule_T_903, _schedule_T_893)
node _schedule_T_905 = or(_schedule_T_904, _schedule_T_894)
node _schedule_T_906 = or(_schedule_T_905, _schedule_T_895)
node _schedule_T_907 = or(_schedule_T_906, _schedule_T_896)
node _schedule_T_908 = or(_schedule_T_907, _schedule_T_897)
wire _schedule_WIRE_52 : UInt<9>
connect _schedule_WIRE_52, _schedule_T_908
connect _schedule_WIRE_49.tag, _schedule_WIRE_52
node _schedule_T_909 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_910 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_911 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_912 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_913 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_914 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_915 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_916 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_917 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_918 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_919 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_920 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_921 = or(_schedule_T_909, _schedule_T_910)
node _schedule_T_922 = or(_schedule_T_921, _schedule_T_911)
node _schedule_T_923 = or(_schedule_T_922, _schedule_T_912)
node _schedule_T_924 = or(_schedule_T_923, _schedule_T_913)
node _schedule_T_925 = or(_schedule_T_924, _schedule_T_914)
node _schedule_T_926 = or(_schedule_T_925, _schedule_T_915)
node _schedule_T_927 = or(_schedule_T_926, _schedule_T_916)
node _schedule_T_928 = or(_schedule_T_927, _schedule_T_917)
node _schedule_T_929 = or(_schedule_T_928, _schedule_T_918)
node _schedule_T_930 = or(_schedule_T_929, _schedule_T_919)
node _schedule_T_931 = or(_schedule_T_930, _schedule_T_920)
wire _schedule_WIRE_53 : UInt<3>
connect _schedule_WIRE_53, _schedule_T_931
connect _schedule_WIRE_49.param, _schedule_WIRE_53
connect _schedule_WIRE_48.bits, _schedule_WIRE_49
node _schedule_T_932 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_933 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_934 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_935 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_936 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_937 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_938 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_939 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_940 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_941 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_942 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_943 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_944 = or(_schedule_T_932, _schedule_T_933)
node _schedule_T_945 = or(_schedule_T_944, _schedule_T_934)
node _schedule_T_946 = or(_schedule_T_945, _schedule_T_935)
node _schedule_T_947 = or(_schedule_T_946, _schedule_T_936)
node _schedule_T_948 = or(_schedule_T_947, _schedule_T_937)
node _schedule_T_949 = or(_schedule_T_948, _schedule_T_938)
node _schedule_T_950 = or(_schedule_T_949, _schedule_T_939)
node _schedule_T_951 = or(_schedule_T_950, _schedule_T_940)
node _schedule_T_952 = or(_schedule_T_951, _schedule_T_941)
node _schedule_T_953 = or(_schedule_T_952, _schedule_T_942)
node _schedule_T_954 = or(_schedule_T_953, _schedule_T_943)
wire _schedule_WIRE_54 : UInt<1>
connect _schedule_WIRE_54, _schedule_T_954
connect _schedule_WIRE_48.valid, _schedule_WIRE_54
connect schedule.b, _schedule_WIRE_48
wire _schedule_WIRE_55 : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}
wire _schedule_WIRE_56 : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}
node _schedule_T_955 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_956 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_957 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_958 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_959 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_960 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_961 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_962 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_963 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_964 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_965 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_966 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_967 = or(_schedule_T_955, _schedule_T_956)
node _schedule_T_968 = or(_schedule_T_967, _schedule_T_957)
node _schedule_T_969 = or(_schedule_T_968, _schedule_T_958)
node _schedule_T_970 = or(_schedule_T_969, _schedule_T_959)
node _schedule_T_971 = or(_schedule_T_970, _schedule_T_960)
node _schedule_T_972 = or(_schedule_T_971, _schedule_T_961)
node _schedule_T_973 = or(_schedule_T_972, _schedule_T_962)
node _schedule_T_974 = or(_schedule_T_973, _schedule_T_963)
node _schedule_T_975 = or(_schedule_T_974, _schedule_T_964)
node _schedule_T_976 = or(_schedule_T_975, _schedule_T_965)
node _schedule_T_977 = or(_schedule_T_976, _schedule_T_966)
wire _schedule_WIRE_57 : UInt<1>
connect _schedule_WIRE_57, _schedule_T_977
connect _schedule_WIRE_56.block, _schedule_WIRE_57
node _schedule_T_978 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_979 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_980 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_981 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_982 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_983 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_984 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_985 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_986 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_987 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_988 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_989 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_990 = or(_schedule_T_978, _schedule_T_979)
node _schedule_T_991 = or(_schedule_T_990, _schedule_T_980)
node _schedule_T_992 = or(_schedule_T_991, _schedule_T_981)
node _schedule_T_993 = or(_schedule_T_992, _schedule_T_982)
node _schedule_T_994 = or(_schedule_T_993, _schedule_T_983)
node _schedule_T_995 = or(_schedule_T_994, _schedule_T_984)
node _schedule_T_996 = or(_schedule_T_995, _schedule_T_985)
node _schedule_T_997 = or(_schedule_T_996, _schedule_T_986)
node _schedule_T_998 = or(_schedule_T_997, _schedule_T_987)
node _schedule_T_999 = or(_schedule_T_998, _schedule_T_988)
node _schedule_T_1000 = or(_schedule_T_999, _schedule_T_989)
wire _schedule_WIRE_58 : UInt<4>
connect _schedule_WIRE_58, _schedule_T_1000
connect _schedule_WIRE_56.source, _schedule_WIRE_58
node _schedule_T_1001 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1002 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1003 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1004 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1005 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1006 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1007 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1008 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1009 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1010 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1011 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1012 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1013 = or(_schedule_T_1001, _schedule_T_1002)
node _schedule_T_1014 = or(_schedule_T_1013, _schedule_T_1003)
node _schedule_T_1015 = or(_schedule_T_1014, _schedule_T_1004)
node _schedule_T_1016 = or(_schedule_T_1015, _schedule_T_1005)
node _schedule_T_1017 = or(_schedule_T_1016, _schedule_T_1006)
node _schedule_T_1018 = or(_schedule_T_1017, _schedule_T_1007)
node _schedule_T_1019 = or(_schedule_T_1018, _schedule_T_1008)
node _schedule_T_1020 = or(_schedule_T_1019, _schedule_T_1009)
node _schedule_T_1021 = or(_schedule_T_1020, _schedule_T_1010)
node _schedule_T_1022 = or(_schedule_T_1021, _schedule_T_1011)
node _schedule_T_1023 = or(_schedule_T_1022, _schedule_T_1012)
wire _schedule_WIRE_59 : UInt<3>
connect _schedule_WIRE_59, _schedule_T_1023
connect _schedule_WIRE_56.param, _schedule_WIRE_59
node _schedule_T_1024 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1025 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1026 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1027 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1028 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1029 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1030 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1031 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1032 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1033 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1034 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1035 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1036 = or(_schedule_T_1024, _schedule_T_1025)
node _schedule_T_1037 = or(_schedule_T_1036, _schedule_T_1026)
node _schedule_T_1038 = or(_schedule_T_1037, _schedule_T_1027)
node _schedule_T_1039 = or(_schedule_T_1038, _schedule_T_1028)
node _schedule_T_1040 = or(_schedule_T_1039, _schedule_T_1029)
node _schedule_T_1041 = or(_schedule_T_1040, _schedule_T_1030)
node _schedule_T_1042 = or(_schedule_T_1041, _schedule_T_1031)
node _schedule_T_1043 = or(_schedule_T_1042, _schedule_T_1032)
node _schedule_T_1044 = or(_schedule_T_1043, _schedule_T_1033)
node _schedule_T_1045 = or(_schedule_T_1044, _schedule_T_1034)
node _schedule_T_1046 = or(_schedule_T_1045, _schedule_T_1035)
wire _schedule_WIRE_60 : UInt<11>
connect _schedule_WIRE_60, _schedule_T_1046
connect _schedule_WIRE_56.set, _schedule_WIRE_60
node _schedule_T_1047 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1048 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1049 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1050 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1051 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1052 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1053 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1054 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1055 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1056 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1057 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1058 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1059 = or(_schedule_T_1047, _schedule_T_1048)
node _schedule_T_1060 = or(_schedule_T_1059, _schedule_T_1049)
node _schedule_T_1061 = or(_schedule_T_1060, _schedule_T_1050)
node _schedule_T_1062 = or(_schedule_T_1061, _schedule_T_1051)
node _schedule_T_1063 = or(_schedule_T_1062, _schedule_T_1052)
node _schedule_T_1064 = or(_schedule_T_1063, _schedule_T_1053)
node _schedule_T_1065 = or(_schedule_T_1064, _schedule_T_1054)
node _schedule_T_1066 = or(_schedule_T_1065, _schedule_T_1055)
node _schedule_T_1067 = or(_schedule_T_1066, _schedule_T_1056)
node _schedule_T_1068 = or(_schedule_T_1067, _schedule_T_1057)
node _schedule_T_1069 = or(_schedule_T_1068, _schedule_T_1058)
wire _schedule_WIRE_61 : UInt<9>
connect _schedule_WIRE_61, _schedule_T_1069
connect _schedule_WIRE_56.tag, _schedule_WIRE_61
connect _schedule_WIRE_55.bits, _schedule_WIRE_56
node _schedule_T_1070 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1071 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1072 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1073 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1074 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1075 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1076 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1077 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1078 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1079 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1080 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1081 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1082 = or(_schedule_T_1070, _schedule_T_1071)
node _schedule_T_1083 = or(_schedule_T_1082, _schedule_T_1072)
node _schedule_T_1084 = or(_schedule_T_1083, _schedule_T_1073)
node _schedule_T_1085 = or(_schedule_T_1084, _schedule_T_1074)
node _schedule_T_1086 = or(_schedule_T_1085, _schedule_T_1075)
node _schedule_T_1087 = or(_schedule_T_1086, _schedule_T_1076)
node _schedule_T_1088 = or(_schedule_T_1087, _schedule_T_1077)
node _schedule_T_1089 = or(_schedule_T_1088, _schedule_T_1078)
node _schedule_T_1090 = or(_schedule_T_1089, _schedule_T_1079)
node _schedule_T_1091 = or(_schedule_T_1090, _schedule_T_1080)
node _schedule_T_1092 = or(_schedule_T_1091, _schedule_T_1081)
wire _schedule_WIRE_62 : UInt<1>
connect _schedule_WIRE_62, _schedule_T_1092
connect _schedule_WIRE_55.valid, _schedule_WIRE_62
connect schedule.a, _schedule_WIRE_55
node _scheduleTag_T = bits(mshr_selectOH, 0, 0)
node _scheduleTag_T_1 = bits(mshr_selectOH, 1, 1)
node _scheduleTag_T_2 = bits(mshr_selectOH, 2, 2)
node _scheduleTag_T_3 = bits(mshr_selectOH, 3, 3)
node _scheduleTag_T_4 = bits(mshr_selectOH, 4, 4)
node _scheduleTag_T_5 = bits(mshr_selectOH, 5, 5)
node _scheduleTag_T_6 = bits(mshr_selectOH, 6, 6)
node _scheduleTag_T_7 = bits(mshr_selectOH, 7, 7)
node _scheduleTag_T_8 = bits(mshr_selectOH, 8, 8)
node _scheduleTag_T_9 = bits(mshr_selectOH, 9, 9)
node _scheduleTag_T_10 = bits(mshr_selectOH, 10, 10)
node _scheduleTag_T_11 = bits(mshr_selectOH, 11, 11)
node _scheduleTag_T_12 = mux(_scheduleTag_T, mshrs_0.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_13 = mux(_scheduleTag_T_1, mshrs_1.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_14 = mux(_scheduleTag_T_2, mshrs_2.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_15 = mux(_scheduleTag_T_3, mshrs_3.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_16 = mux(_scheduleTag_T_4, mshrs_4.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_17 = mux(_scheduleTag_T_5, mshrs_5.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_18 = mux(_scheduleTag_T_6, mshrs_6.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_19 = mux(_scheduleTag_T_7, mshrs_7.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_20 = mux(_scheduleTag_T_8, mshrs_8.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_21 = mux(_scheduleTag_T_9, mshrs_9.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_22 = mux(_scheduleTag_T_10, mshrs_10.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_23 = mux(_scheduleTag_T_11, mshrs_11.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_24 = or(_scheduleTag_T_12, _scheduleTag_T_13)
node _scheduleTag_T_25 = or(_scheduleTag_T_24, _scheduleTag_T_14)
node _scheduleTag_T_26 = or(_scheduleTag_T_25, _scheduleTag_T_15)
node _scheduleTag_T_27 = or(_scheduleTag_T_26, _scheduleTag_T_16)
node _scheduleTag_T_28 = or(_scheduleTag_T_27, _scheduleTag_T_17)
node _scheduleTag_T_29 = or(_scheduleTag_T_28, _scheduleTag_T_18)
node _scheduleTag_T_30 = or(_scheduleTag_T_29, _scheduleTag_T_19)
node _scheduleTag_T_31 = or(_scheduleTag_T_30, _scheduleTag_T_20)
node _scheduleTag_T_32 = or(_scheduleTag_T_31, _scheduleTag_T_21)
node _scheduleTag_T_33 = or(_scheduleTag_T_32, _scheduleTag_T_22)
node _scheduleTag_T_34 = or(_scheduleTag_T_33, _scheduleTag_T_23)
wire scheduleTag : UInt<9>
connect scheduleTag, _scheduleTag_T_34
node _scheduleSet_T = bits(mshr_selectOH, 0, 0)
node _scheduleSet_T_1 = bits(mshr_selectOH, 1, 1)
node _scheduleSet_T_2 = bits(mshr_selectOH, 2, 2)
node _scheduleSet_T_3 = bits(mshr_selectOH, 3, 3)
node _scheduleSet_T_4 = bits(mshr_selectOH, 4, 4)
node _scheduleSet_T_5 = bits(mshr_selectOH, 5, 5)
node _scheduleSet_T_6 = bits(mshr_selectOH, 6, 6)
node _scheduleSet_T_7 = bits(mshr_selectOH, 7, 7)
node _scheduleSet_T_8 = bits(mshr_selectOH, 8, 8)
node _scheduleSet_T_9 = bits(mshr_selectOH, 9, 9)
node _scheduleSet_T_10 = bits(mshr_selectOH, 10, 10)
node _scheduleSet_T_11 = bits(mshr_selectOH, 11, 11)
node _scheduleSet_T_12 = mux(_scheduleSet_T, mshrs_0.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_13 = mux(_scheduleSet_T_1, mshrs_1.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_14 = mux(_scheduleSet_T_2, mshrs_2.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_15 = mux(_scheduleSet_T_3, mshrs_3.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_16 = mux(_scheduleSet_T_4, mshrs_4.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_17 = mux(_scheduleSet_T_5, mshrs_5.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_18 = mux(_scheduleSet_T_6, mshrs_6.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_19 = mux(_scheduleSet_T_7, mshrs_7.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_20 = mux(_scheduleSet_T_8, mshrs_8.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_21 = mux(_scheduleSet_T_9, mshrs_9.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_22 = mux(_scheduleSet_T_10, mshrs_10.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_23 = mux(_scheduleSet_T_11, mshrs_11.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_24 = or(_scheduleSet_T_12, _scheduleSet_T_13)
node _scheduleSet_T_25 = or(_scheduleSet_T_24, _scheduleSet_T_14)
node _scheduleSet_T_26 = or(_scheduleSet_T_25, _scheduleSet_T_15)
node _scheduleSet_T_27 = or(_scheduleSet_T_26, _scheduleSet_T_16)
node _scheduleSet_T_28 = or(_scheduleSet_T_27, _scheduleSet_T_17)
node _scheduleSet_T_29 = or(_scheduleSet_T_28, _scheduleSet_T_18)
node _scheduleSet_T_30 = or(_scheduleSet_T_29, _scheduleSet_T_19)
node _scheduleSet_T_31 = or(_scheduleSet_T_30, _scheduleSet_T_20)
node _scheduleSet_T_32 = or(_scheduleSet_T_31, _scheduleSet_T_21)
node _scheduleSet_T_33 = or(_scheduleSet_T_32, _scheduleSet_T_22)
node _scheduleSet_T_34 = or(_scheduleSet_T_33, _scheduleSet_T_23)
wire scheduleSet : UInt<11>
connect scheduleSet, _scheduleSet_T_34
node _T_9 = orr(mshr_request)
when _T_9 :
node _robin_filter_T = shr(mshr_selectOH, 1)
node _robin_filter_T_1 = or(mshr_selectOH, _robin_filter_T)
node _robin_filter_T_2 = shr(_robin_filter_T_1, 2)
node _robin_filter_T_3 = or(_robin_filter_T_1, _robin_filter_T_2)
node _robin_filter_T_4 = shr(_robin_filter_T_3, 4)
node _robin_filter_T_5 = or(_robin_filter_T_3, _robin_filter_T_4)
node _robin_filter_T_6 = shr(_robin_filter_T_5, 8)
node _robin_filter_T_7 = or(_robin_filter_T_5, _robin_filter_T_6)
node _robin_filter_T_8 = bits(_robin_filter_T_7, 11, 0)
node _robin_filter_T_9 = not(_robin_filter_T_8)
connect robin_filter, _robin_filter_T_9
connect schedule.a.bits.source, mshr_select
node _schedule_c_bits_source_T = bits(schedule.c.bits.opcode, 1, 1)
node _schedule_c_bits_source_T_1 = mux(_schedule_c_bits_source_T, mshr_select, UInt<1>(0h0))
connect schedule.c.bits.source, _schedule_c_bits_source_T_1
connect schedule.d.bits.sink, mshr_select
connect sourceA.io.req.valid, schedule.a.valid
connect sourceB.io.req.valid, schedule.b.valid
connect sourceC.io.req.valid, schedule.c.valid
connect sourceD.io.req.valid, schedule.d.valid
connect sourceE.io.req.valid, schedule.e.valid
connect sourceX.io.req.valid, schedule.x.valid
connect sourceA.io.req.bits.block, schedule.a.bits.block
connect sourceA.io.req.bits.source, schedule.a.bits.source
connect sourceA.io.req.bits.param, schedule.a.bits.param
connect sourceA.io.req.bits.set, schedule.a.bits.set
connect sourceA.io.req.bits.tag, schedule.a.bits.tag
connect sourceB.io.req.bits.clients, schedule.b.bits.clients
connect sourceB.io.req.bits.set, schedule.b.bits.set
connect sourceB.io.req.bits.tag, schedule.b.bits.tag
connect sourceB.io.req.bits.param, schedule.b.bits.param
connect sourceC.io.req.bits.dirty, schedule.c.bits.dirty
connect sourceC.io.req.bits.way, schedule.c.bits.way
connect sourceC.io.req.bits.set, schedule.c.bits.set
connect sourceC.io.req.bits.tag, schedule.c.bits.tag
connect sourceC.io.req.bits.source, schedule.c.bits.source
connect sourceC.io.req.bits.param, schedule.c.bits.param
connect sourceC.io.req.bits.opcode, schedule.c.bits.opcode
connect sourceD.io.req.bits.bad, schedule.d.bits.bad
connect sourceD.io.req.bits.way, schedule.d.bits.way
connect sourceD.io.req.bits.sink, schedule.d.bits.sink
connect sourceD.io.req.bits.set, schedule.d.bits.set
connect sourceD.io.req.bits.put, schedule.d.bits.put
connect sourceD.io.req.bits.offset, schedule.d.bits.offset
connect sourceD.io.req.bits.tag, schedule.d.bits.tag
connect sourceD.io.req.bits.source, schedule.d.bits.source
connect sourceD.io.req.bits.size, schedule.d.bits.size
connect sourceD.io.req.bits.param, schedule.d.bits.param
connect sourceD.io.req.bits.opcode, schedule.d.bits.opcode
connect sourceD.io.req.bits.control, schedule.d.bits.control
connect sourceD.io.req.bits.prio[0], schedule.d.bits.prio[0]
connect sourceD.io.req.bits.prio[1], schedule.d.bits.prio[1]
connect sourceD.io.req.bits.prio[2], schedule.d.bits.prio[2]
connect sourceE.io.req.bits.sink, schedule.e.bits.sink
connect sourceX.io.req.bits.fail, schedule.x.bits.fail
connect directory.io.write.valid, schedule.dir.valid
connect directory.io.write.bits.data.tag, schedule.dir.bits.data.tag
connect directory.io.write.bits.data.clients, schedule.dir.bits.data.clients
connect directory.io.write.bits.data.state, schedule.dir.bits.data.state
connect directory.io.write.bits.data.dirty, schedule.dir.bits.data.dirty
connect directory.io.write.bits.way, schedule.dir.bits.way
connect directory.io.write.bits.set, schedule.dir.bits.set
node select_c = bits(mshr_selectOH, 11, 11)
node select_bc = bits(mshr_selectOH, 10, 10)
node _nestedwb_set_T = mux(select_c, mshrs_11.io.status.bits.set, mshrs_10.io.status.bits.set)
connect nestedwb.set, _nestedwb_set_T
node _nestedwb_tag_T = mux(select_c, mshrs_11.io.status.bits.tag, mshrs_10.io.status.bits.tag)
connect nestedwb.tag, _nestedwb_tag_T
node _nestedwb_b_toN_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid)
node _nestedwb_b_toN_T_1 = eq(mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<2>(0h0))
node _nestedwb_b_toN_T_2 = and(_nestedwb_b_toN_T, _nestedwb_b_toN_T_1)
connect nestedwb.b_toN, _nestedwb_b_toN_T_2
node _nestedwb_b_toB_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid)
node _nestedwb_b_toB_T_1 = eq(mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<2>(0h1))
node _nestedwb_b_toB_T_2 = and(_nestedwb_b_toB_T, _nestedwb_b_toB_T_1)
connect nestedwb.b_toB, _nestedwb_b_toB_T_2
node _nestedwb_b_clr_dirty_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid)
connect nestedwb.b_clr_dirty, _nestedwb_b_clr_dirty_T
node _nestedwb_c_set_dirty_T = and(select_c, mshrs_11.io.schedule.bits.dir.valid)
node _nestedwb_c_set_dirty_T_1 = and(_nestedwb_c_set_dirty_T, mshrs_11.io.schedule.bits.dir.bits.data.dirty)
connect nestedwb.c_set_dirty, _nestedwb_c_set_dirty_T_1
wire request : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}}
node _request_valid_T = or(sinkA.io.req.valid, sinkX.io.req.valid)
node _request_valid_T_1 = or(_request_valid_T, sinkC.io.req.valid)
node _request_valid_T_2 = and(directory.io.ready, _request_valid_T_1)
connect request.valid, _request_valid_T_2
node _request_bits_T = mux(sinkX.io.req.valid, sinkX.io.req.bits, sinkA.io.req.bits)
node _request_bits_T_1 = mux(sinkC.io.req.valid, sinkC.io.req.bits, _request_bits_T)
connect request.bits, _request_bits_T_1
node _sinkC_io_req_ready_T = and(directory.io.ready, request.ready)
connect sinkC.io.req.ready, _sinkC_io_req_ready_T
node _sinkX_io_req_ready_T = and(directory.io.ready, request.ready)
node _sinkX_io_req_ready_T_1 = eq(sinkC.io.req.valid, UInt<1>(0h0))
node _sinkX_io_req_ready_T_2 = and(_sinkX_io_req_ready_T, _sinkX_io_req_ready_T_1)
connect sinkX.io.req.ready, _sinkX_io_req_ready_T_2
node _sinkA_io_req_ready_T = and(directory.io.ready, request.ready)
node _sinkA_io_req_ready_T_1 = eq(sinkC.io.req.valid, UInt<1>(0h0))
node _sinkA_io_req_ready_T_2 = and(_sinkA_io_req_ready_T, _sinkA_io_req_ready_T_1)
node _sinkA_io_req_ready_T_3 = eq(sinkX.io.req.valid, UInt<1>(0h0))
node _sinkA_io_req_ready_T_4 = and(_sinkA_io_req_ready_T_2, _sinkA_io_req_ready_T_3)
connect sinkA.io.req.ready, _sinkA_io_req_ready_T_4
node _setMatches_T = eq(mshrs_0.io.status.bits.set, request.bits.set)
node _setMatches_T_1 = and(mshrs_0.io.status.valid, _setMatches_T)
node _setMatches_T_2 = eq(mshrs_1.io.status.bits.set, request.bits.set)
node _setMatches_T_3 = and(mshrs_1.io.status.valid, _setMatches_T_2)
node _setMatches_T_4 = eq(mshrs_2.io.status.bits.set, request.bits.set)
node _setMatches_T_5 = and(mshrs_2.io.status.valid, _setMatches_T_4)
node _setMatches_T_6 = eq(mshrs_3.io.status.bits.set, request.bits.set)
node _setMatches_T_7 = and(mshrs_3.io.status.valid, _setMatches_T_6)
node _setMatches_T_8 = eq(mshrs_4.io.status.bits.set, request.bits.set)
node _setMatches_T_9 = and(mshrs_4.io.status.valid, _setMatches_T_8)
node _setMatches_T_10 = eq(mshrs_5.io.status.bits.set, request.bits.set)
node _setMatches_T_11 = and(mshrs_5.io.status.valid, _setMatches_T_10)
node _setMatches_T_12 = eq(mshrs_6.io.status.bits.set, request.bits.set)
node _setMatches_T_13 = and(mshrs_6.io.status.valid, _setMatches_T_12)
node _setMatches_T_14 = eq(mshrs_7.io.status.bits.set, request.bits.set)
node _setMatches_T_15 = and(mshrs_7.io.status.valid, _setMatches_T_14)
node _setMatches_T_16 = eq(mshrs_8.io.status.bits.set, request.bits.set)
node _setMatches_T_17 = and(mshrs_8.io.status.valid, _setMatches_T_16)
node _setMatches_T_18 = eq(mshrs_9.io.status.bits.set, request.bits.set)
node _setMatches_T_19 = and(mshrs_9.io.status.valid, _setMatches_T_18)
node _setMatches_T_20 = eq(mshrs_10.io.status.bits.set, request.bits.set)
node _setMatches_T_21 = and(mshrs_10.io.status.valid, _setMatches_T_20)
node _setMatches_T_22 = eq(mshrs_11.io.status.bits.set, request.bits.set)
node _setMatches_T_23 = and(mshrs_11.io.status.valid, _setMatches_T_22)
node setMatches_lo_lo_hi = cat(_setMatches_T_5, _setMatches_T_3)
node setMatches_lo_lo = cat(setMatches_lo_lo_hi, _setMatches_T_1)
node setMatches_lo_hi_hi = cat(_setMatches_T_11, _setMatches_T_9)
node setMatches_lo_hi = cat(setMatches_lo_hi_hi, _setMatches_T_7)
node setMatches_lo = cat(setMatches_lo_hi, setMatches_lo_lo)
node setMatches_hi_lo_hi = cat(_setMatches_T_17, _setMatches_T_15)
node setMatches_hi_lo = cat(setMatches_hi_lo_hi, _setMatches_T_13)
node setMatches_hi_hi_hi = cat(_setMatches_T_23, _setMatches_T_21)
node setMatches_hi_hi = cat(setMatches_hi_hi_hi, _setMatches_T_19)
node setMatches_hi = cat(setMatches_hi_hi, setMatches_hi_lo)
node setMatches = cat(setMatches_hi, setMatches_lo)
node _alloc_T = orr(setMatches)
node alloc = eq(_alloc_T, UInt<1>(0h0))
node _blockB_T = bits(setMatches, 0, 0)
node _blockB_T_1 = bits(setMatches, 1, 1)
node _blockB_T_2 = bits(setMatches, 2, 2)
node _blockB_T_3 = bits(setMatches, 3, 3)
node _blockB_T_4 = bits(setMatches, 4, 4)
node _blockB_T_5 = bits(setMatches, 5, 5)
node _blockB_T_6 = bits(setMatches, 6, 6)
node _blockB_T_7 = bits(setMatches, 7, 7)
node _blockB_T_8 = bits(setMatches, 8, 8)
node _blockB_T_9 = bits(setMatches, 9, 9)
node _blockB_T_10 = bits(setMatches, 10, 10)
node _blockB_T_11 = bits(setMatches, 11, 11)
node _blockB_T_12 = mux(_blockB_T, mshrs_0.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_13 = mux(_blockB_T_1, mshrs_1.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_14 = mux(_blockB_T_2, mshrs_2.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_15 = mux(_blockB_T_3, mshrs_3.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_16 = mux(_blockB_T_4, mshrs_4.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_17 = mux(_blockB_T_5, mshrs_5.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_18 = mux(_blockB_T_6, mshrs_6.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_19 = mux(_blockB_T_7, mshrs_7.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_20 = mux(_blockB_T_8, mshrs_8.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_21 = mux(_blockB_T_9, mshrs_9.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_22 = mux(_blockB_T_10, mshrs_10.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_23 = mux(_blockB_T_11, mshrs_11.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_24 = or(_blockB_T_12, _blockB_T_13)
node _blockB_T_25 = or(_blockB_T_24, _blockB_T_14)
node _blockB_T_26 = or(_blockB_T_25, _blockB_T_15)
node _blockB_T_27 = or(_blockB_T_26, _blockB_T_16)
node _blockB_T_28 = or(_blockB_T_27, _blockB_T_17)
node _blockB_T_29 = or(_blockB_T_28, _blockB_T_18)
node _blockB_T_30 = or(_blockB_T_29, _blockB_T_19)
node _blockB_T_31 = or(_blockB_T_30, _blockB_T_20)
node _blockB_T_32 = or(_blockB_T_31, _blockB_T_21)
node _blockB_T_33 = or(_blockB_T_32, _blockB_T_22)
node _blockB_T_34 = or(_blockB_T_33, _blockB_T_23)
wire _blockB_WIRE : UInt<1>
connect _blockB_WIRE, _blockB_T_34
node blockB = and(_blockB_WIRE, request.bits.prio[1])
node _blockC_T = bits(setMatches, 0, 0)
node _blockC_T_1 = bits(setMatches, 1, 1)
node _blockC_T_2 = bits(setMatches, 2, 2)
node _blockC_T_3 = bits(setMatches, 3, 3)
node _blockC_T_4 = bits(setMatches, 4, 4)
node _blockC_T_5 = bits(setMatches, 5, 5)
node _blockC_T_6 = bits(setMatches, 6, 6)
node _blockC_T_7 = bits(setMatches, 7, 7)
node _blockC_T_8 = bits(setMatches, 8, 8)
node _blockC_T_9 = bits(setMatches, 9, 9)
node _blockC_T_10 = bits(setMatches, 10, 10)
node _blockC_T_11 = bits(setMatches, 11, 11)
node _blockC_T_12 = mux(_blockC_T, mshrs_0.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_13 = mux(_blockC_T_1, mshrs_1.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_14 = mux(_blockC_T_2, mshrs_2.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_15 = mux(_blockC_T_3, mshrs_3.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_16 = mux(_blockC_T_4, mshrs_4.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_17 = mux(_blockC_T_5, mshrs_5.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_18 = mux(_blockC_T_6, mshrs_6.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_19 = mux(_blockC_T_7, mshrs_7.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_20 = mux(_blockC_T_8, mshrs_8.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_21 = mux(_blockC_T_9, mshrs_9.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_22 = mux(_blockC_T_10, mshrs_10.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_23 = mux(_blockC_T_11, mshrs_11.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_24 = or(_blockC_T_12, _blockC_T_13)
node _blockC_T_25 = or(_blockC_T_24, _blockC_T_14)
node _blockC_T_26 = or(_blockC_T_25, _blockC_T_15)
node _blockC_T_27 = or(_blockC_T_26, _blockC_T_16)
node _blockC_T_28 = or(_blockC_T_27, _blockC_T_17)
node _blockC_T_29 = or(_blockC_T_28, _blockC_T_18)
node _blockC_T_30 = or(_blockC_T_29, _blockC_T_19)
node _blockC_T_31 = or(_blockC_T_30, _blockC_T_20)
node _blockC_T_32 = or(_blockC_T_31, _blockC_T_21)
node _blockC_T_33 = or(_blockC_T_32, _blockC_T_22)
node _blockC_T_34 = or(_blockC_T_33, _blockC_T_23)
wire _blockC_WIRE : UInt<1>
connect _blockC_WIRE, _blockC_T_34
node blockC = and(_blockC_WIRE, request.bits.prio[2])
node _nestB_T = bits(setMatches, 0, 0)
node _nestB_T_1 = bits(setMatches, 1, 1)
node _nestB_T_2 = bits(setMatches, 2, 2)
node _nestB_T_3 = bits(setMatches, 3, 3)
node _nestB_T_4 = bits(setMatches, 4, 4)
node _nestB_T_5 = bits(setMatches, 5, 5)
node _nestB_T_6 = bits(setMatches, 6, 6)
node _nestB_T_7 = bits(setMatches, 7, 7)
node _nestB_T_8 = bits(setMatches, 8, 8)
node _nestB_T_9 = bits(setMatches, 9, 9)
node _nestB_T_10 = bits(setMatches, 10, 10)
node _nestB_T_11 = bits(setMatches, 11, 11)
node _nestB_T_12 = mux(_nestB_T, mshrs_0.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_13 = mux(_nestB_T_1, mshrs_1.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_14 = mux(_nestB_T_2, mshrs_2.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_15 = mux(_nestB_T_3, mshrs_3.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_16 = mux(_nestB_T_4, mshrs_4.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_17 = mux(_nestB_T_5, mshrs_5.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_18 = mux(_nestB_T_6, mshrs_6.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_19 = mux(_nestB_T_7, mshrs_7.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_20 = mux(_nestB_T_8, mshrs_8.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_21 = mux(_nestB_T_9, mshrs_9.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_22 = mux(_nestB_T_10, mshrs_10.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_23 = mux(_nestB_T_11, mshrs_11.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_24 = or(_nestB_T_12, _nestB_T_13)
node _nestB_T_25 = or(_nestB_T_24, _nestB_T_14)
node _nestB_T_26 = or(_nestB_T_25, _nestB_T_15)
node _nestB_T_27 = or(_nestB_T_26, _nestB_T_16)
node _nestB_T_28 = or(_nestB_T_27, _nestB_T_17)
node _nestB_T_29 = or(_nestB_T_28, _nestB_T_18)
node _nestB_T_30 = or(_nestB_T_29, _nestB_T_19)
node _nestB_T_31 = or(_nestB_T_30, _nestB_T_20)
node _nestB_T_32 = or(_nestB_T_31, _nestB_T_21)
node _nestB_T_33 = or(_nestB_T_32, _nestB_T_22)
node _nestB_T_34 = or(_nestB_T_33, _nestB_T_23)
wire _nestB_WIRE : UInt<1>
connect _nestB_WIRE, _nestB_T_34
node nestB = and(_nestB_WIRE, request.bits.prio[1])
node _nestC_T = bits(setMatches, 0, 0)
node _nestC_T_1 = bits(setMatches, 1, 1)
node _nestC_T_2 = bits(setMatches, 2, 2)
node _nestC_T_3 = bits(setMatches, 3, 3)
node _nestC_T_4 = bits(setMatches, 4, 4)
node _nestC_T_5 = bits(setMatches, 5, 5)
node _nestC_T_6 = bits(setMatches, 6, 6)
node _nestC_T_7 = bits(setMatches, 7, 7)
node _nestC_T_8 = bits(setMatches, 8, 8)
node _nestC_T_9 = bits(setMatches, 9, 9)
node _nestC_T_10 = bits(setMatches, 10, 10)
node _nestC_T_11 = bits(setMatches, 11, 11)
node _nestC_T_12 = mux(_nestC_T, mshrs_0.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_13 = mux(_nestC_T_1, mshrs_1.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_14 = mux(_nestC_T_2, mshrs_2.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_15 = mux(_nestC_T_3, mshrs_3.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_16 = mux(_nestC_T_4, mshrs_4.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_17 = mux(_nestC_T_5, mshrs_5.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_18 = mux(_nestC_T_6, mshrs_6.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_19 = mux(_nestC_T_7, mshrs_7.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_20 = mux(_nestC_T_8, mshrs_8.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_21 = mux(_nestC_T_9, mshrs_9.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_22 = mux(_nestC_T_10, mshrs_10.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_23 = mux(_nestC_T_11, mshrs_11.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_24 = or(_nestC_T_12, _nestC_T_13)
node _nestC_T_25 = or(_nestC_T_24, _nestC_T_14)
node _nestC_T_26 = or(_nestC_T_25, _nestC_T_15)
node _nestC_T_27 = or(_nestC_T_26, _nestC_T_16)
node _nestC_T_28 = or(_nestC_T_27, _nestC_T_17)
node _nestC_T_29 = or(_nestC_T_28, _nestC_T_18)
node _nestC_T_30 = or(_nestC_T_29, _nestC_T_19)
node _nestC_T_31 = or(_nestC_T_30, _nestC_T_20)
node _nestC_T_32 = or(_nestC_T_31, _nestC_T_21)
node _nestC_T_33 = or(_nestC_T_32, _nestC_T_22)
node _nestC_T_34 = or(_nestC_T_33, _nestC_T_23)
wire _nestC_WIRE : UInt<1>
connect _nestC_WIRE, _nestC_T_34
node nestC = and(_nestC_WIRE, request.bits.prio[2])
node _prioFilter_T = eq(request.bits.prio[0], UInt<1>(0h0))
node _prioFilter_T_1 = not(UInt<10>(0h0))
node prioFilter_hi = cat(request.bits.prio[2], _prioFilter_T)
node prioFilter = cat(prioFilter_hi, _prioFilter_T_1)
node lowerMatches = and(setMatches, prioFilter)
node _queue_T = orr(lowerMatches)
node _queue_T_1 = eq(nestB, UInt<1>(0h0))
node _queue_T_2 = and(_queue_T, _queue_T_1)
node _queue_T_3 = eq(nestC, UInt<1>(0h0))
node _queue_T_4 = and(_queue_T_2, _queue_T_3)
node _queue_T_5 = eq(blockB, UInt<1>(0h0))
node _queue_T_6 = and(_queue_T_4, _queue_T_5)
node _queue_T_7 = eq(blockC, UInt<1>(0h0))
node queue = and(_queue_T_6, _queue_T_7)
node _T_10 = and(request.valid, blockC)
node _T_11 = and(request.valid, nestC)
node _T_12 = and(request.valid, queue)
node _lowerMatches1_T = bits(lowerMatches, 11, 11)
node _lowerMatches1_T_1 = shl(UInt<1>(0h1), 11)
node _lowerMatches1_T_2 = bits(lowerMatches, 10, 10)
node _lowerMatches1_T_3 = shl(UInt<1>(0h1), 10)
node _lowerMatches1_T_4 = mux(_lowerMatches1_T_2, _lowerMatches1_T_3, lowerMatches)
node lowerMatches1 = mux(_lowerMatches1_T, _lowerMatches1_T_1, _lowerMatches1_T_4)
node selected_requests_hi = cat(mshr_selectOH, mshr_selectOH)
node _selected_requests_T = cat(selected_requests_hi, mshr_selectOH)
node selected_requests = and(_selected_requests_T, requests.io.valid)
node _a_pop_T = bits(selected_requests, 11, 0)
node a_pop = orr(_a_pop_T)
node _b_pop_T = bits(selected_requests, 23, 12)
node b_pop = orr(_b_pop_T)
node _c_pop_T = bits(selected_requests, 35, 24)
node c_pop = orr(_c_pop_T)
node _bypassMatches_T = and(mshr_selectOH, lowerMatches1)
node _bypassMatches_T_1 = orr(_bypassMatches_T)
node _bypassMatches_T_2 = or(c_pop, request.bits.prio[2])
node _bypassMatches_T_3 = eq(c_pop, UInt<1>(0h0))
node _bypassMatches_T_4 = or(b_pop, request.bits.prio[1])
node _bypassMatches_T_5 = eq(b_pop, UInt<1>(0h0))
node _bypassMatches_T_6 = eq(a_pop, UInt<1>(0h0))
node _bypassMatches_T_7 = mux(_bypassMatches_T_4, _bypassMatches_T_5, _bypassMatches_T_6)
node _bypassMatches_T_8 = mux(_bypassMatches_T_2, _bypassMatches_T_3, _bypassMatches_T_7)
node bypassMatches = and(_bypassMatches_T_1, _bypassMatches_T_8)
node _may_pop_T = or(a_pop, b_pop)
node may_pop = or(_may_pop_T, c_pop)
node _bypass_T = and(request.valid, queue)
node bypass = and(_bypass_T, bypassMatches)
node _will_reload_T = or(may_pop, bypass)
node will_reload = and(schedule.reload, _will_reload_T)
node _will_pop_T = and(schedule.reload, may_pop)
node _will_pop_T_1 = eq(bypass, UInt<1>(0h0))
node will_pop = and(_will_pop_T, _will_pop_T_1)
node _T_13 = orr(mshr_selectOH)
node _T_14 = and(_T_13, bypass)
node _T_15 = orr(mshr_selectOH)
node _T_16 = and(_T_15, will_reload)
node _T_17 = orr(mshr_selectOH)
node _T_18 = and(_T_17, will_pop)
node sel = bits(mshr_selectOH, 0, 0)
connect mshrs_0.io.schedule.ready, sel
node a_pop_1 = bits(requests.io.valid, 0, 0)
node b_pop_1 = bits(requests.io.valid, 12, 12)
node c_pop_1 = bits(requests.io.valid, 24, 24)
node _bypassMatches_T_9 = bits(lowerMatches1, 0, 0)
node _bypassMatches_T_10 = or(c_pop_1, request.bits.prio[2])
node _bypassMatches_T_11 = eq(c_pop_1, UInt<1>(0h0))
node _bypassMatches_T_12 = or(b_pop_1, request.bits.prio[1])
node _bypassMatches_T_13 = eq(b_pop_1, UInt<1>(0h0))
node _bypassMatches_T_14 = eq(a_pop_1, UInt<1>(0h0))
node _bypassMatches_T_15 = mux(_bypassMatches_T_12, _bypassMatches_T_13, _bypassMatches_T_14)
node _bypassMatches_T_16 = mux(_bypassMatches_T_10, _bypassMatches_T_11, _bypassMatches_T_15)
node bypassMatches_1 = and(_bypassMatches_T_9, _bypassMatches_T_16)
node _may_pop_T_1 = or(a_pop_1, b_pop_1)
node may_pop_1 = or(_may_pop_T_1, c_pop_1)
node _bypass_T_1 = and(request.valid, queue)
node bypass_1 = and(_bypass_T_1, bypassMatches_1)
node _will_reload_T_1 = or(may_pop_1, bypass_1)
node will_reload_1 = and(mshrs_0.io.schedule.bits.reload, _will_reload_T_1)
wire _view__WIRE : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE.put, request.bits.put
connect _view__WIRE.offset, request.bits.offset
connect _view__WIRE.tag, request.bits.tag
connect _view__WIRE.source, request.bits.source
connect _view__WIRE.size, request.bits.size
connect _view__WIRE.param, request.bits.param
connect _view__WIRE.opcode, request.bits.opcode
connect _view__WIRE.control, request.bits.control
connect _view__WIRE.prio, request.bits.prio
node _view__T = mux(bypass_1, _view__WIRE, requests.io.data)
connect mshrs_0.io.allocate.bits.put, _view__T.put
connect mshrs_0.io.allocate.bits.offset, _view__T.offset
connect mshrs_0.io.allocate.bits.tag, _view__T.tag
connect mshrs_0.io.allocate.bits.source, _view__T.source
connect mshrs_0.io.allocate.bits.size, _view__T.size
connect mshrs_0.io.allocate.bits.param, _view__T.param
connect mshrs_0.io.allocate.bits.opcode, _view__T.opcode
connect mshrs_0.io.allocate.bits.control, _view__T.control
connect mshrs_0.io.allocate.bits.prio[0], _view__T.prio[0]
connect mshrs_0.io.allocate.bits.prio[1], _view__T.prio[1]
connect mshrs_0.io.allocate.bits.prio[2], _view__T.prio[2]
connect mshrs_0.io.allocate.bits.set, mshrs_0.io.status.bits.set
node _mshrs_0_io_allocate_bits_repeat_T = eq(mshrs_0.io.allocate.bits.tag, mshrs_0.io.status.bits.tag)
connect mshrs_0.io.allocate.bits.repeat, _mshrs_0_io_allocate_bits_repeat_T
node _mshrs_0_io_allocate_valid_T = and(sel, will_reload_1)
connect mshrs_0.io.allocate.valid, _mshrs_0_io_allocate_valid_T
node sel_1 = bits(mshr_selectOH, 1, 1)
connect mshrs_1.io.schedule.ready, sel_1
node a_pop_2 = bits(requests.io.valid, 1, 1)
node b_pop_2 = bits(requests.io.valid, 13, 13)
node c_pop_2 = bits(requests.io.valid, 25, 25)
node _bypassMatches_T_17 = bits(lowerMatches1, 1, 1)
node _bypassMatches_T_18 = or(c_pop_2, request.bits.prio[2])
node _bypassMatches_T_19 = eq(c_pop_2, UInt<1>(0h0))
node _bypassMatches_T_20 = or(b_pop_2, request.bits.prio[1])
node _bypassMatches_T_21 = eq(b_pop_2, UInt<1>(0h0))
node _bypassMatches_T_22 = eq(a_pop_2, UInt<1>(0h0))
node _bypassMatches_T_23 = mux(_bypassMatches_T_20, _bypassMatches_T_21, _bypassMatches_T_22)
node _bypassMatches_T_24 = mux(_bypassMatches_T_18, _bypassMatches_T_19, _bypassMatches_T_23)
node bypassMatches_2 = and(_bypassMatches_T_17, _bypassMatches_T_24)
node _may_pop_T_2 = or(a_pop_2, b_pop_2)
node may_pop_2 = or(_may_pop_T_2, c_pop_2)
node _bypass_T_2 = and(request.valid, queue)
node bypass_2 = and(_bypass_T_2, bypassMatches_2)
node _will_reload_T_2 = or(may_pop_2, bypass_2)
node will_reload_2 = and(mshrs_1.io.schedule.bits.reload, _will_reload_T_2)
wire _view__WIRE_1 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_1.put, request.bits.put
connect _view__WIRE_1.offset, request.bits.offset
connect _view__WIRE_1.tag, request.bits.tag
connect _view__WIRE_1.source, request.bits.source
connect _view__WIRE_1.size, request.bits.size
connect _view__WIRE_1.param, request.bits.param
connect _view__WIRE_1.opcode, request.bits.opcode
connect _view__WIRE_1.control, request.bits.control
connect _view__WIRE_1.prio, request.bits.prio
node _view__T_1 = mux(bypass_2, _view__WIRE_1, requests.io.data)
connect mshrs_1.io.allocate.bits.put, _view__T_1.put
connect mshrs_1.io.allocate.bits.offset, _view__T_1.offset
connect mshrs_1.io.allocate.bits.tag, _view__T_1.tag
connect mshrs_1.io.allocate.bits.source, _view__T_1.source
connect mshrs_1.io.allocate.bits.size, _view__T_1.size
connect mshrs_1.io.allocate.bits.param, _view__T_1.param
connect mshrs_1.io.allocate.bits.opcode, _view__T_1.opcode
connect mshrs_1.io.allocate.bits.control, _view__T_1.control
connect mshrs_1.io.allocate.bits.prio[0], _view__T_1.prio[0]
connect mshrs_1.io.allocate.bits.prio[1], _view__T_1.prio[1]
connect mshrs_1.io.allocate.bits.prio[2], _view__T_1.prio[2]
connect mshrs_1.io.allocate.bits.set, mshrs_1.io.status.bits.set
node _mshrs_1_io_allocate_bits_repeat_T = eq(mshrs_1.io.allocate.bits.tag, mshrs_1.io.status.bits.tag)
connect mshrs_1.io.allocate.bits.repeat, _mshrs_1_io_allocate_bits_repeat_T
node _mshrs_1_io_allocate_valid_T = and(sel_1, will_reload_2)
connect mshrs_1.io.allocate.valid, _mshrs_1_io_allocate_valid_T
node sel_2 = bits(mshr_selectOH, 2, 2)
connect mshrs_2.io.schedule.ready, sel_2
node a_pop_3 = bits(requests.io.valid, 2, 2)
node b_pop_3 = bits(requests.io.valid, 14, 14)
node c_pop_3 = bits(requests.io.valid, 26, 26)
node _bypassMatches_T_25 = bits(lowerMatches1, 2, 2)
node _bypassMatches_T_26 = or(c_pop_3, request.bits.prio[2])
node _bypassMatches_T_27 = eq(c_pop_3, UInt<1>(0h0))
node _bypassMatches_T_28 = or(b_pop_3, request.bits.prio[1])
node _bypassMatches_T_29 = eq(b_pop_3, UInt<1>(0h0))
node _bypassMatches_T_30 = eq(a_pop_3, UInt<1>(0h0))
node _bypassMatches_T_31 = mux(_bypassMatches_T_28, _bypassMatches_T_29, _bypassMatches_T_30)
node _bypassMatches_T_32 = mux(_bypassMatches_T_26, _bypassMatches_T_27, _bypassMatches_T_31)
node bypassMatches_3 = and(_bypassMatches_T_25, _bypassMatches_T_32)
node _may_pop_T_3 = or(a_pop_3, b_pop_3)
node may_pop_3 = or(_may_pop_T_3, c_pop_3)
node _bypass_T_3 = and(request.valid, queue)
node bypass_3 = and(_bypass_T_3, bypassMatches_3)
node _will_reload_T_3 = or(may_pop_3, bypass_3)
node will_reload_3 = and(mshrs_2.io.schedule.bits.reload, _will_reload_T_3)
wire _view__WIRE_2 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_2.put, request.bits.put
connect _view__WIRE_2.offset, request.bits.offset
connect _view__WIRE_2.tag, request.bits.tag
connect _view__WIRE_2.source, request.bits.source
connect _view__WIRE_2.size, request.bits.size
connect _view__WIRE_2.param, request.bits.param
connect _view__WIRE_2.opcode, request.bits.opcode
connect _view__WIRE_2.control, request.bits.control
connect _view__WIRE_2.prio, request.bits.prio
node _view__T_2 = mux(bypass_3, _view__WIRE_2, requests.io.data)
connect mshrs_2.io.allocate.bits.put, _view__T_2.put
connect mshrs_2.io.allocate.bits.offset, _view__T_2.offset
connect mshrs_2.io.allocate.bits.tag, _view__T_2.tag
connect mshrs_2.io.allocate.bits.source, _view__T_2.source
connect mshrs_2.io.allocate.bits.size, _view__T_2.size
connect mshrs_2.io.allocate.bits.param, _view__T_2.param
connect mshrs_2.io.allocate.bits.opcode, _view__T_2.opcode
connect mshrs_2.io.allocate.bits.control, _view__T_2.control
connect mshrs_2.io.allocate.bits.prio[0], _view__T_2.prio[0]
connect mshrs_2.io.allocate.bits.prio[1], _view__T_2.prio[1]
connect mshrs_2.io.allocate.bits.prio[2], _view__T_2.prio[2]
connect mshrs_2.io.allocate.bits.set, mshrs_2.io.status.bits.set
node _mshrs_2_io_allocate_bits_repeat_T = eq(mshrs_2.io.allocate.bits.tag, mshrs_2.io.status.bits.tag)
connect mshrs_2.io.allocate.bits.repeat, _mshrs_2_io_allocate_bits_repeat_T
node _mshrs_2_io_allocate_valid_T = and(sel_2, will_reload_3)
connect mshrs_2.io.allocate.valid, _mshrs_2_io_allocate_valid_T
node sel_3 = bits(mshr_selectOH, 3, 3)
connect mshrs_3.io.schedule.ready, sel_3
node a_pop_4 = bits(requests.io.valid, 3, 3)
node b_pop_4 = bits(requests.io.valid, 15, 15)
node c_pop_4 = bits(requests.io.valid, 27, 27)
node _bypassMatches_T_33 = bits(lowerMatches1, 3, 3)
node _bypassMatches_T_34 = or(c_pop_4, request.bits.prio[2])
node _bypassMatches_T_35 = eq(c_pop_4, UInt<1>(0h0))
node _bypassMatches_T_36 = or(b_pop_4, request.bits.prio[1])
node _bypassMatches_T_37 = eq(b_pop_4, UInt<1>(0h0))
node _bypassMatches_T_38 = eq(a_pop_4, UInt<1>(0h0))
node _bypassMatches_T_39 = mux(_bypassMatches_T_36, _bypassMatches_T_37, _bypassMatches_T_38)
node _bypassMatches_T_40 = mux(_bypassMatches_T_34, _bypassMatches_T_35, _bypassMatches_T_39)
node bypassMatches_4 = and(_bypassMatches_T_33, _bypassMatches_T_40)
node _may_pop_T_4 = or(a_pop_4, b_pop_4)
node may_pop_4 = or(_may_pop_T_4, c_pop_4)
node _bypass_T_4 = and(request.valid, queue)
node bypass_4 = and(_bypass_T_4, bypassMatches_4)
node _will_reload_T_4 = or(may_pop_4, bypass_4)
node will_reload_4 = and(mshrs_3.io.schedule.bits.reload, _will_reload_T_4)
wire _view__WIRE_3 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_3.put, request.bits.put
connect _view__WIRE_3.offset, request.bits.offset
connect _view__WIRE_3.tag, request.bits.tag
connect _view__WIRE_3.source, request.bits.source
connect _view__WIRE_3.size, request.bits.size
connect _view__WIRE_3.param, request.bits.param
connect _view__WIRE_3.opcode, request.bits.opcode
connect _view__WIRE_3.control, request.bits.control
connect _view__WIRE_3.prio, request.bits.prio
node _view__T_3 = mux(bypass_4, _view__WIRE_3, requests.io.data)
connect mshrs_3.io.allocate.bits.put, _view__T_3.put
connect mshrs_3.io.allocate.bits.offset, _view__T_3.offset
connect mshrs_3.io.allocate.bits.tag, _view__T_3.tag
connect mshrs_3.io.allocate.bits.source, _view__T_3.source
connect mshrs_3.io.allocate.bits.size, _view__T_3.size
connect mshrs_3.io.allocate.bits.param, _view__T_3.param
connect mshrs_3.io.allocate.bits.opcode, _view__T_3.opcode
connect mshrs_3.io.allocate.bits.control, _view__T_3.control
connect mshrs_3.io.allocate.bits.prio[0], _view__T_3.prio[0]
connect mshrs_3.io.allocate.bits.prio[1], _view__T_3.prio[1]
connect mshrs_3.io.allocate.bits.prio[2], _view__T_3.prio[2]
connect mshrs_3.io.allocate.bits.set, mshrs_3.io.status.bits.set
node _mshrs_3_io_allocate_bits_repeat_T = eq(mshrs_3.io.allocate.bits.tag, mshrs_3.io.status.bits.tag)
connect mshrs_3.io.allocate.bits.repeat, _mshrs_3_io_allocate_bits_repeat_T
node _mshrs_3_io_allocate_valid_T = and(sel_3, will_reload_4)
connect mshrs_3.io.allocate.valid, _mshrs_3_io_allocate_valid_T
node sel_4 = bits(mshr_selectOH, 4, 4)
connect mshrs_4.io.schedule.ready, sel_4
node a_pop_5 = bits(requests.io.valid, 4, 4)
node b_pop_5 = bits(requests.io.valid, 16, 16)
node c_pop_5 = bits(requests.io.valid, 28, 28)
node _bypassMatches_T_41 = bits(lowerMatches1, 4, 4)
node _bypassMatches_T_42 = or(c_pop_5, request.bits.prio[2])
node _bypassMatches_T_43 = eq(c_pop_5, UInt<1>(0h0))
node _bypassMatches_T_44 = or(b_pop_5, request.bits.prio[1])
node _bypassMatches_T_45 = eq(b_pop_5, UInt<1>(0h0))
node _bypassMatches_T_46 = eq(a_pop_5, UInt<1>(0h0))
node _bypassMatches_T_47 = mux(_bypassMatches_T_44, _bypassMatches_T_45, _bypassMatches_T_46)
node _bypassMatches_T_48 = mux(_bypassMatches_T_42, _bypassMatches_T_43, _bypassMatches_T_47)
node bypassMatches_5 = and(_bypassMatches_T_41, _bypassMatches_T_48)
node _may_pop_T_5 = or(a_pop_5, b_pop_5)
node may_pop_5 = or(_may_pop_T_5, c_pop_5)
node _bypass_T_5 = and(request.valid, queue)
node bypass_5 = and(_bypass_T_5, bypassMatches_5)
node _will_reload_T_5 = or(may_pop_5, bypass_5)
node will_reload_5 = and(mshrs_4.io.schedule.bits.reload, _will_reload_T_5)
wire _view__WIRE_4 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_4.put, request.bits.put
connect _view__WIRE_4.offset, request.bits.offset
connect _view__WIRE_4.tag, request.bits.tag
connect _view__WIRE_4.source, request.bits.source
connect _view__WIRE_4.size, request.bits.size
connect _view__WIRE_4.param, request.bits.param
connect _view__WIRE_4.opcode, request.bits.opcode
connect _view__WIRE_4.control, request.bits.control
connect _view__WIRE_4.prio, request.bits.prio
node _view__T_4 = mux(bypass_5, _view__WIRE_4, requests.io.data)
connect mshrs_4.io.allocate.bits.put, _view__T_4.put
connect mshrs_4.io.allocate.bits.offset, _view__T_4.offset
connect mshrs_4.io.allocate.bits.tag, _view__T_4.tag
connect mshrs_4.io.allocate.bits.source, _view__T_4.source
connect mshrs_4.io.allocate.bits.size, _view__T_4.size
connect mshrs_4.io.allocate.bits.param, _view__T_4.param
connect mshrs_4.io.allocate.bits.opcode, _view__T_4.opcode
connect mshrs_4.io.allocate.bits.control, _view__T_4.control
connect mshrs_4.io.allocate.bits.prio[0], _view__T_4.prio[0]
connect mshrs_4.io.allocate.bits.prio[1], _view__T_4.prio[1]
connect mshrs_4.io.allocate.bits.prio[2], _view__T_4.prio[2]
connect mshrs_4.io.allocate.bits.set, mshrs_4.io.status.bits.set
node _mshrs_4_io_allocate_bits_repeat_T = eq(mshrs_4.io.allocate.bits.tag, mshrs_4.io.status.bits.tag)
connect mshrs_4.io.allocate.bits.repeat, _mshrs_4_io_allocate_bits_repeat_T
node _mshrs_4_io_allocate_valid_T = and(sel_4, will_reload_5)
connect mshrs_4.io.allocate.valid, _mshrs_4_io_allocate_valid_T
node sel_5 = bits(mshr_selectOH, 5, 5)
connect mshrs_5.io.schedule.ready, sel_5
node a_pop_6 = bits(requests.io.valid, 5, 5)
node b_pop_6 = bits(requests.io.valid, 17, 17)
node c_pop_6 = bits(requests.io.valid, 29, 29)
node _bypassMatches_T_49 = bits(lowerMatches1, 5, 5)
node _bypassMatches_T_50 = or(c_pop_6, request.bits.prio[2])
node _bypassMatches_T_51 = eq(c_pop_6, UInt<1>(0h0))
node _bypassMatches_T_52 = or(b_pop_6, request.bits.prio[1])
node _bypassMatches_T_53 = eq(b_pop_6, UInt<1>(0h0))
node _bypassMatches_T_54 = eq(a_pop_6, UInt<1>(0h0))
node _bypassMatches_T_55 = mux(_bypassMatches_T_52, _bypassMatches_T_53, _bypassMatches_T_54)
node _bypassMatches_T_56 = mux(_bypassMatches_T_50, _bypassMatches_T_51, _bypassMatches_T_55)
node bypassMatches_6 = and(_bypassMatches_T_49, _bypassMatches_T_56)
node _may_pop_T_6 = or(a_pop_6, b_pop_6)
node may_pop_6 = or(_may_pop_T_6, c_pop_6)
node _bypass_T_6 = and(request.valid, queue)
node bypass_6 = and(_bypass_T_6, bypassMatches_6)
node _will_reload_T_6 = or(may_pop_6, bypass_6)
node will_reload_6 = and(mshrs_5.io.schedule.bits.reload, _will_reload_T_6)
wire _view__WIRE_5 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_5.put, request.bits.put
connect _view__WIRE_5.offset, request.bits.offset
connect _view__WIRE_5.tag, request.bits.tag
connect _view__WIRE_5.source, request.bits.source
connect _view__WIRE_5.size, request.bits.size
connect _view__WIRE_5.param, request.bits.param
connect _view__WIRE_5.opcode, request.bits.opcode
connect _view__WIRE_5.control, request.bits.control
connect _view__WIRE_5.prio, request.bits.prio
node _view__T_5 = mux(bypass_6, _view__WIRE_5, requests.io.data)
connect mshrs_5.io.allocate.bits.put, _view__T_5.put
connect mshrs_5.io.allocate.bits.offset, _view__T_5.offset
connect mshrs_5.io.allocate.bits.tag, _view__T_5.tag
connect mshrs_5.io.allocate.bits.source, _view__T_5.source
connect mshrs_5.io.allocate.bits.size, _view__T_5.size
connect mshrs_5.io.allocate.bits.param, _view__T_5.param
connect mshrs_5.io.allocate.bits.opcode, _view__T_5.opcode
connect mshrs_5.io.allocate.bits.control, _view__T_5.control
connect mshrs_5.io.allocate.bits.prio[0], _view__T_5.prio[0]
connect mshrs_5.io.allocate.bits.prio[1], _view__T_5.prio[1]
connect mshrs_5.io.allocate.bits.prio[2], _view__T_5.prio[2]
connect mshrs_5.io.allocate.bits.set, mshrs_5.io.status.bits.set
node _mshrs_5_io_allocate_bits_repeat_T = eq(mshrs_5.io.allocate.bits.tag, mshrs_5.io.status.bits.tag)
connect mshrs_5.io.allocate.bits.repeat, _mshrs_5_io_allocate_bits_repeat_T
node _mshrs_5_io_allocate_valid_T = and(sel_5, will_reload_6)
connect mshrs_5.io.allocate.valid, _mshrs_5_io_allocate_valid_T
node sel_6 = bits(mshr_selectOH, 6, 6)
connect mshrs_6.io.schedule.ready, sel_6
node a_pop_7 = bits(requests.io.valid, 6, 6)
node b_pop_7 = bits(requests.io.valid, 18, 18)
node c_pop_7 = bits(requests.io.valid, 30, 30)
node _bypassMatches_T_57 = bits(lowerMatches1, 6, 6)
node _bypassMatches_T_58 = or(c_pop_7, request.bits.prio[2])
node _bypassMatches_T_59 = eq(c_pop_7, UInt<1>(0h0))
node _bypassMatches_T_60 = or(b_pop_7, request.bits.prio[1])
node _bypassMatches_T_61 = eq(b_pop_7, UInt<1>(0h0))
node _bypassMatches_T_62 = eq(a_pop_7, UInt<1>(0h0))
node _bypassMatches_T_63 = mux(_bypassMatches_T_60, _bypassMatches_T_61, _bypassMatches_T_62)
node _bypassMatches_T_64 = mux(_bypassMatches_T_58, _bypassMatches_T_59, _bypassMatches_T_63)
node bypassMatches_7 = and(_bypassMatches_T_57, _bypassMatches_T_64)
node _may_pop_T_7 = or(a_pop_7, b_pop_7)
node may_pop_7 = or(_may_pop_T_7, c_pop_7)
node _bypass_T_7 = and(request.valid, queue)
node bypass_7 = and(_bypass_T_7, bypassMatches_7)
node _will_reload_T_7 = or(may_pop_7, bypass_7)
node will_reload_7 = and(mshrs_6.io.schedule.bits.reload, _will_reload_T_7)
wire _view__WIRE_6 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_6.put, request.bits.put
connect _view__WIRE_6.offset, request.bits.offset
connect _view__WIRE_6.tag, request.bits.tag
connect _view__WIRE_6.source, request.bits.source
connect _view__WIRE_6.size, request.bits.size
connect _view__WIRE_6.param, request.bits.param
connect _view__WIRE_6.opcode, request.bits.opcode
connect _view__WIRE_6.control, request.bits.control
connect _view__WIRE_6.prio, request.bits.prio
node _view__T_6 = mux(bypass_7, _view__WIRE_6, requests.io.data)
connect mshrs_6.io.allocate.bits.put, _view__T_6.put
connect mshrs_6.io.allocate.bits.offset, _view__T_6.offset
connect mshrs_6.io.allocate.bits.tag, _view__T_6.tag
connect mshrs_6.io.allocate.bits.source, _view__T_6.source
connect mshrs_6.io.allocate.bits.size, _view__T_6.size
connect mshrs_6.io.allocate.bits.param, _view__T_6.param
connect mshrs_6.io.allocate.bits.opcode, _view__T_6.opcode
connect mshrs_6.io.allocate.bits.control, _view__T_6.control
connect mshrs_6.io.allocate.bits.prio[0], _view__T_6.prio[0]
connect mshrs_6.io.allocate.bits.prio[1], _view__T_6.prio[1]
connect mshrs_6.io.allocate.bits.prio[2], _view__T_6.prio[2]
connect mshrs_6.io.allocate.bits.set, mshrs_6.io.status.bits.set
node _mshrs_6_io_allocate_bits_repeat_T = eq(mshrs_6.io.allocate.bits.tag, mshrs_6.io.status.bits.tag)
connect mshrs_6.io.allocate.bits.repeat, _mshrs_6_io_allocate_bits_repeat_T
node _mshrs_6_io_allocate_valid_T = and(sel_6, will_reload_7)
connect mshrs_6.io.allocate.valid, _mshrs_6_io_allocate_valid_T
node sel_7 = bits(mshr_selectOH, 7, 7)
connect mshrs_7.io.schedule.ready, sel_7
node a_pop_8 = bits(requests.io.valid, 7, 7)
node b_pop_8 = bits(requests.io.valid, 19, 19)
node c_pop_8 = bits(requests.io.valid, 31, 31)
node _bypassMatches_T_65 = bits(lowerMatches1, 7, 7)
node _bypassMatches_T_66 = or(c_pop_8, request.bits.prio[2])
node _bypassMatches_T_67 = eq(c_pop_8, UInt<1>(0h0))
node _bypassMatches_T_68 = or(b_pop_8, request.bits.prio[1])
node _bypassMatches_T_69 = eq(b_pop_8, UInt<1>(0h0))
node _bypassMatches_T_70 = eq(a_pop_8, UInt<1>(0h0))
node _bypassMatches_T_71 = mux(_bypassMatches_T_68, _bypassMatches_T_69, _bypassMatches_T_70)
node _bypassMatches_T_72 = mux(_bypassMatches_T_66, _bypassMatches_T_67, _bypassMatches_T_71)
node bypassMatches_8 = and(_bypassMatches_T_65, _bypassMatches_T_72)
node _may_pop_T_8 = or(a_pop_8, b_pop_8)
node may_pop_8 = or(_may_pop_T_8, c_pop_8)
node _bypass_T_8 = and(request.valid, queue)
node bypass_8 = and(_bypass_T_8, bypassMatches_8)
node _will_reload_T_8 = or(may_pop_8, bypass_8)
node will_reload_8 = and(mshrs_7.io.schedule.bits.reload, _will_reload_T_8)
wire _view__WIRE_7 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_7.put, request.bits.put
connect _view__WIRE_7.offset, request.bits.offset
connect _view__WIRE_7.tag, request.bits.tag
connect _view__WIRE_7.source, request.bits.source
connect _view__WIRE_7.size, request.bits.size
connect _view__WIRE_7.param, request.bits.param
connect _view__WIRE_7.opcode, request.bits.opcode
connect _view__WIRE_7.control, request.bits.control
connect _view__WIRE_7.prio, request.bits.prio
node _view__T_7 = mux(bypass_8, _view__WIRE_7, requests.io.data)
connect mshrs_7.io.allocate.bits.put, _view__T_7.put
connect mshrs_7.io.allocate.bits.offset, _view__T_7.offset
connect mshrs_7.io.allocate.bits.tag, _view__T_7.tag
connect mshrs_7.io.allocate.bits.source, _view__T_7.source
connect mshrs_7.io.allocate.bits.size, _view__T_7.size
connect mshrs_7.io.allocate.bits.param, _view__T_7.param
connect mshrs_7.io.allocate.bits.opcode, _view__T_7.opcode
connect mshrs_7.io.allocate.bits.control, _view__T_7.control
connect mshrs_7.io.allocate.bits.prio[0], _view__T_7.prio[0]
connect mshrs_7.io.allocate.bits.prio[1], _view__T_7.prio[1]
connect mshrs_7.io.allocate.bits.prio[2], _view__T_7.prio[2]
connect mshrs_7.io.allocate.bits.set, mshrs_7.io.status.bits.set
node _mshrs_7_io_allocate_bits_repeat_T = eq(mshrs_7.io.allocate.bits.tag, mshrs_7.io.status.bits.tag)
connect mshrs_7.io.allocate.bits.repeat, _mshrs_7_io_allocate_bits_repeat_T
node _mshrs_7_io_allocate_valid_T = and(sel_7, will_reload_8)
connect mshrs_7.io.allocate.valid, _mshrs_7_io_allocate_valid_T
node sel_8 = bits(mshr_selectOH, 8, 8)
connect mshrs_8.io.schedule.ready, sel_8
node a_pop_9 = bits(requests.io.valid, 8, 8)
node b_pop_9 = bits(requests.io.valid, 20, 20)
node c_pop_9 = bits(requests.io.valid, 32, 32)
node _bypassMatches_T_73 = bits(lowerMatches1, 8, 8)
node _bypassMatches_T_74 = or(c_pop_9, request.bits.prio[2])
node _bypassMatches_T_75 = eq(c_pop_9, UInt<1>(0h0))
node _bypassMatches_T_76 = or(b_pop_9, request.bits.prio[1])
node _bypassMatches_T_77 = eq(b_pop_9, UInt<1>(0h0))
node _bypassMatches_T_78 = eq(a_pop_9, UInt<1>(0h0))
node _bypassMatches_T_79 = mux(_bypassMatches_T_76, _bypassMatches_T_77, _bypassMatches_T_78)
node _bypassMatches_T_80 = mux(_bypassMatches_T_74, _bypassMatches_T_75, _bypassMatches_T_79)
node bypassMatches_9 = and(_bypassMatches_T_73, _bypassMatches_T_80)
node _may_pop_T_9 = or(a_pop_9, b_pop_9)
node may_pop_9 = or(_may_pop_T_9, c_pop_9)
node _bypass_T_9 = and(request.valid, queue)
node bypass_9 = and(_bypass_T_9, bypassMatches_9)
node _will_reload_T_9 = or(may_pop_9, bypass_9)
node will_reload_9 = and(mshrs_8.io.schedule.bits.reload, _will_reload_T_9)
wire _view__WIRE_8 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_8.put, request.bits.put
connect _view__WIRE_8.offset, request.bits.offset
connect _view__WIRE_8.tag, request.bits.tag
connect _view__WIRE_8.source, request.bits.source
connect _view__WIRE_8.size, request.bits.size
connect _view__WIRE_8.param, request.bits.param
connect _view__WIRE_8.opcode, request.bits.opcode
connect _view__WIRE_8.control, request.bits.control
connect _view__WIRE_8.prio, request.bits.prio
node _view__T_8 = mux(bypass_9, _view__WIRE_8, requests.io.data)
connect mshrs_8.io.allocate.bits.put, _view__T_8.put
connect mshrs_8.io.allocate.bits.offset, _view__T_8.offset
connect mshrs_8.io.allocate.bits.tag, _view__T_8.tag
connect mshrs_8.io.allocate.bits.source, _view__T_8.source
connect mshrs_8.io.allocate.bits.size, _view__T_8.size
connect mshrs_8.io.allocate.bits.param, _view__T_8.param
connect mshrs_8.io.allocate.bits.opcode, _view__T_8.opcode
connect mshrs_8.io.allocate.bits.control, _view__T_8.control
connect mshrs_8.io.allocate.bits.prio[0], _view__T_8.prio[0]
connect mshrs_8.io.allocate.bits.prio[1], _view__T_8.prio[1]
connect mshrs_8.io.allocate.bits.prio[2], _view__T_8.prio[2]
connect mshrs_8.io.allocate.bits.set, mshrs_8.io.status.bits.set
node _mshrs_8_io_allocate_bits_repeat_T = eq(mshrs_8.io.allocate.bits.tag, mshrs_8.io.status.bits.tag)
connect mshrs_8.io.allocate.bits.repeat, _mshrs_8_io_allocate_bits_repeat_T
node _mshrs_8_io_allocate_valid_T = and(sel_8, will_reload_9)
connect mshrs_8.io.allocate.valid, _mshrs_8_io_allocate_valid_T
node sel_9 = bits(mshr_selectOH, 9, 9)
connect mshrs_9.io.schedule.ready, sel_9
node a_pop_10 = bits(requests.io.valid, 9, 9)
node b_pop_10 = bits(requests.io.valid, 21, 21)
node c_pop_10 = bits(requests.io.valid, 33, 33)
node _bypassMatches_T_81 = bits(lowerMatches1, 9, 9)
node _bypassMatches_T_82 = or(c_pop_10, request.bits.prio[2])
node _bypassMatches_T_83 = eq(c_pop_10, UInt<1>(0h0))
node _bypassMatches_T_84 = or(b_pop_10, request.bits.prio[1])
node _bypassMatches_T_85 = eq(b_pop_10, UInt<1>(0h0))
node _bypassMatches_T_86 = eq(a_pop_10, UInt<1>(0h0))
node _bypassMatches_T_87 = mux(_bypassMatches_T_84, _bypassMatches_T_85, _bypassMatches_T_86)
node _bypassMatches_T_88 = mux(_bypassMatches_T_82, _bypassMatches_T_83, _bypassMatches_T_87)
node bypassMatches_10 = and(_bypassMatches_T_81, _bypassMatches_T_88)
node _may_pop_T_10 = or(a_pop_10, b_pop_10)
node may_pop_10 = or(_may_pop_T_10, c_pop_10)
node _bypass_T_10 = and(request.valid, queue)
node bypass_10 = and(_bypass_T_10, bypassMatches_10)
node _will_reload_T_10 = or(may_pop_10, bypass_10)
node will_reload_10 = and(mshrs_9.io.schedule.bits.reload, _will_reload_T_10)
wire _view__WIRE_9 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_9.put, request.bits.put
connect _view__WIRE_9.offset, request.bits.offset
connect _view__WIRE_9.tag, request.bits.tag
connect _view__WIRE_9.source, request.bits.source
connect _view__WIRE_9.size, request.bits.size
connect _view__WIRE_9.param, request.bits.param
connect _view__WIRE_9.opcode, request.bits.opcode
connect _view__WIRE_9.control, request.bits.control
connect _view__WIRE_9.prio, request.bits.prio
node _view__T_9 = mux(bypass_10, _view__WIRE_9, requests.io.data)
connect mshrs_9.io.allocate.bits.put, _view__T_9.put
connect mshrs_9.io.allocate.bits.offset, _view__T_9.offset
connect mshrs_9.io.allocate.bits.tag, _view__T_9.tag
connect mshrs_9.io.allocate.bits.source, _view__T_9.source
connect mshrs_9.io.allocate.bits.size, _view__T_9.size
connect mshrs_9.io.allocate.bits.param, _view__T_9.param
connect mshrs_9.io.allocate.bits.opcode, _view__T_9.opcode
connect mshrs_9.io.allocate.bits.control, _view__T_9.control
connect mshrs_9.io.allocate.bits.prio[0], _view__T_9.prio[0]
connect mshrs_9.io.allocate.bits.prio[1], _view__T_9.prio[1]
connect mshrs_9.io.allocate.bits.prio[2], _view__T_9.prio[2]
connect mshrs_9.io.allocate.bits.set, mshrs_9.io.status.bits.set
node _mshrs_9_io_allocate_bits_repeat_T = eq(mshrs_9.io.allocate.bits.tag, mshrs_9.io.status.bits.tag)
connect mshrs_9.io.allocate.bits.repeat, _mshrs_9_io_allocate_bits_repeat_T
node _mshrs_9_io_allocate_valid_T = and(sel_9, will_reload_10)
connect mshrs_9.io.allocate.valid, _mshrs_9_io_allocate_valid_T
node sel_10 = bits(mshr_selectOH, 10, 10)
connect mshrs_10.io.schedule.ready, sel_10
node a_pop_11 = bits(requests.io.valid, 10, 10)
node b_pop_11 = bits(requests.io.valid, 22, 22)
node c_pop_11 = bits(requests.io.valid, 34, 34)
node _bypassMatches_T_89 = bits(lowerMatches1, 10, 10)
node _bypassMatches_T_90 = or(c_pop_11, request.bits.prio[2])
node _bypassMatches_T_91 = eq(c_pop_11, UInt<1>(0h0))
node _bypassMatches_T_92 = or(b_pop_11, request.bits.prio[1])
node _bypassMatches_T_93 = eq(b_pop_11, UInt<1>(0h0))
node _bypassMatches_T_94 = eq(a_pop_11, UInt<1>(0h0))
node _bypassMatches_T_95 = mux(_bypassMatches_T_92, _bypassMatches_T_93, _bypassMatches_T_94)
node _bypassMatches_T_96 = mux(_bypassMatches_T_90, _bypassMatches_T_91, _bypassMatches_T_95)
node bypassMatches_11 = and(_bypassMatches_T_89, _bypassMatches_T_96)
node _may_pop_T_11 = or(a_pop_11, b_pop_11)
node may_pop_11 = or(_may_pop_T_11, c_pop_11)
node _bypass_T_11 = and(request.valid, queue)
node bypass_11 = and(_bypass_T_11, bypassMatches_11)
node _will_reload_T_11 = or(may_pop_11, bypass_11)
node will_reload_11 = and(mshrs_10.io.schedule.bits.reload, _will_reload_T_11)
wire _view__WIRE_10 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_10.put, request.bits.put
connect _view__WIRE_10.offset, request.bits.offset
connect _view__WIRE_10.tag, request.bits.tag
connect _view__WIRE_10.source, request.bits.source
connect _view__WIRE_10.size, request.bits.size
connect _view__WIRE_10.param, request.bits.param
connect _view__WIRE_10.opcode, request.bits.opcode
connect _view__WIRE_10.control, request.bits.control
connect _view__WIRE_10.prio, request.bits.prio
node _view__T_10 = mux(bypass_11, _view__WIRE_10, requests.io.data)
connect mshrs_10.io.allocate.bits.put, _view__T_10.put
connect mshrs_10.io.allocate.bits.offset, _view__T_10.offset
connect mshrs_10.io.allocate.bits.tag, _view__T_10.tag
connect mshrs_10.io.allocate.bits.source, _view__T_10.source
connect mshrs_10.io.allocate.bits.size, _view__T_10.size
connect mshrs_10.io.allocate.bits.param, _view__T_10.param
connect mshrs_10.io.allocate.bits.opcode, _view__T_10.opcode
connect mshrs_10.io.allocate.bits.control, _view__T_10.control
connect mshrs_10.io.allocate.bits.prio[0], _view__T_10.prio[0]
connect mshrs_10.io.allocate.bits.prio[1], _view__T_10.prio[1]
connect mshrs_10.io.allocate.bits.prio[2], _view__T_10.prio[2]
connect mshrs_10.io.allocate.bits.set, mshrs_10.io.status.bits.set
node _mshrs_10_io_allocate_bits_repeat_T = eq(mshrs_10.io.allocate.bits.tag, mshrs_10.io.status.bits.tag)
connect mshrs_10.io.allocate.bits.repeat, _mshrs_10_io_allocate_bits_repeat_T
node _mshrs_10_io_allocate_valid_T = and(sel_10, will_reload_11)
connect mshrs_10.io.allocate.valid, _mshrs_10_io_allocate_valid_T
node sel_11 = bits(mshr_selectOH, 11, 11)
connect mshrs_11.io.schedule.ready, sel_11
node a_pop_12 = bits(requests.io.valid, 11, 11)
node b_pop_12 = bits(requests.io.valid, 23, 23)
node c_pop_12 = bits(requests.io.valid, 35, 35)
node _bypassMatches_T_97 = bits(lowerMatches1, 11, 11)
node _bypassMatches_T_98 = or(c_pop_12, request.bits.prio[2])
node _bypassMatches_T_99 = eq(c_pop_12, UInt<1>(0h0))
node _bypassMatches_T_100 = or(b_pop_12, request.bits.prio[1])
node _bypassMatches_T_101 = eq(b_pop_12, UInt<1>(0h0))
node _bypassMatches_T_102 = eq(a_pop_12, UInt<1>(0h0))
node _bypassMatches_T_103 = mux(_bypassMatches_T_100, _bypassMatches_T_101, _bypassMatches_T_102)
node _bypassMatches_T_104 = mux(_bypassMatches_T_98, _bypassMatches_T_99, _bypassMatches_T_103)
node bypassMatches_12 = and(_bypassMatches_T_97, _bypassMatches_T_104)
node _may_pop_T_12 = or(a_pop_12, b_pop_12)
node may_pop_12 = or(_may_pop_T_12, c_pop_12)
node _bypass_T_12 = and(request.valid, queue)
node bypass_12 = and(_bypass_T_12, bypassMatches_12)
node _will_reload_T_12 = or(may_pop_12, bypass_12)
node will_reload_12 = and(mshrs_11.io.schedule.bits.reload, _will_reload_T_12)
wire _view__WIRE_11 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_11.put, request.bits.put
connect _view__WIRE_11.offset, request.bits.offset
connect _view__WIRE_11.tag, request.bits.tag
connect _view__WIRE_11.source, request.bits.source
connect _view__WIRE_11.size, request.bits.size
connect _view__WIRE_11.param, request.bits.param
connect _view__WIRE_11.opcode, request.bits.opcode
connect _view__WIRE_11.control, request.bits.control
connect _view__WIRE_11.prio, request.bits.prio
node _view__T_11 = mux(bypass_12, _view__WIRE_11, requests.io.data)
connect mshrs_11.io.allocate.bits.put, _view__T_11.put
connect mshrs_11.io.allocate.bits.offset, _view__T_11.offset
connect mshrs_11.io.allocate.bits.tag, _view__T_11.tag
connect mshrs_11.io.allocate.bits.source, _view__T_11.source
connect mshrs_11.io.allocate.bits.size, _view__T_11.size
connect mshrs_11.io.allocate.bits.param, _view__T_11.param
connect mshrs_11.io.allocate.bits.opcode, _view__T_11.opcode
connect mshrs_11.io.allocate.bits.control, _view__T_11.control
connect mshrs_11.io.allocate.bits.prio[0], _view__T_11.prio[0]
connect mshrs_11.io.allocate.bits.prio[1], _view__T_11.prio[1]
connect mshrs_11.io.allocate.bits.prio[2], _view__T_11.prio[2]
connect mshrs_11.io.allocate.bits.set, mshrs_11.io.status.bits.set
node _mshrs_11_io_allocate_bits_repeat_T = eq(mshrs_11.io.allocate.bits.tag, mshrs_11.io.status.bits.tag)
connect mshrs_11.io.allocate.bits.repeat, _mshrs_11_io_allocate_bits_repeat_T
node _mshrs_11_io_allocate_valid_T = and(sel_11, will_reload_12)
connect mshrs_11.io.allocate.valid, _mshrs_11_io_allocate_valid_T
node _prio_requests_T = not(requests.io.valid)
node _prio_requests_T_1 = shr(requests.io.valid, 12)
node _prio_requests_T_2 = or(_prio_requests_T, _prio_requests_T_1)
node _prio_requests_T_3 = shr(requests.io.valid, 24)
node _prio_requests_T_4 = or(_prio_requests_T_2, _prio_requests_T_3)
node prio_requests = not(_prio_requests_T_4)
node pop_index_hi = cat(mshr_selectOH, mshr_selectOH)
node _pop_index_T = cat(pop_index_hi, mshr_selectOH)
node _pop_index_T_1 = and(_pop_index_T, prio_requests)
node pop_index_hi_1 = bits(_pop_index_T_1, 35, 32)
node pop_index_lo = bits(_pop_index_T_1, 31, 0)
node _pop_index_T_2 = orr(pop_index_hi_1)
node _pop_index_T_3 = or(pop_index_hi_1, pop_index_lo)
node pop_index_hi_2 = bits(_pop_index_T_3, 31, 16)
node pop_index_lo_1 = bits(_pop_index_T_3, 15, 0)
node _pop_index_T_4 = orr(pop_index_hi_2)
node _pop_index_T_5 = or(pop_index_hi_2, pop_index_lo_1)
node pop_index_hi_3 = bits(_pop_index_T_5, 15, 8)
node pop_index_lo_2 = bits(_pop_index_T_5, 7, 0)
node _pop_index_T_6 = orr(pop_index_hi_3)
node _pop_index_T_7 = or(pop_index_hi_3, pop_index_lo_2)
node pop_index_hi_4 = bits(_pop_index_T_7, 7, 4)
node pop_index_lo_3 = bits(_pop_index_T_7, 3, 0)
node _pop_index_T_8 = orr(pop_index_hi_4)
node _pop_index_T_9 = or(pop_index_hi_4, pop_index_lo_3)
node pop_index_hi_5 = bits(_pop_index_T_9, 3, 2)
node pop_index_lo_4 = bits(_pop_index_T_9, 1, 0)
node _pop_index_T_10 = orr(pop_index_hi_5)
node _pop_index_T_11 = or(pop_index_hi_5, pop_index_lo_4)
node _pop_index_T_12 = bits(_pop_index_T_11, 1, 1)
node _pop_index_T_13 = cat(_pop_index_T_10, _pop_index_T_12)
node _pop_index_T_14 = cat(_pop_index_T_8, _pop_index_T_13)
node _pop_index_T_15 = cat(_pop_index_T_6, _pop_index_T_14)
node _pop_index_T_16 = cat(_pop_index_T_4, _pop_index_T_15)
node pop_index = cat(_pop_index_T_2, _pop_index_T_16)
connect requests.io.pop.valid, will_pop
connect requests.io.pop.bits, pop_index
node lb_tag_mismatch = neq(scheduleTag, requests.io.data.tag)
node _mshr_uses_directory_assuming_no_bypass_T = and(schedule.reload, may_pop)
node mshr_uses_directory_assuming_no_bypass = and(_mshr_uses_directory_assuming_no_bypass_T, lb_tag_mismatch)
node mshr_uses_directory_for_lb = and(will_pop, lb_tag_mismatch)
node _mshr_uses_directory_T = mux(bypass, request.bits.tag, requests.io.data.tag)
node _mshr_uses_directory_T_1 = neq(scheduleTag, _mshr_uses_directory_T)
node mshr_uses_directory = and(will_reload, _mshr_uses_directory_T_1)
node mshr_validOH_lo_lo_hi = cat(mshrs_2.io.status.valid, mshrs_1.io.status.valid)
node mshr_validOH_lo_lo = cat(mshr_validOH_lo_lo_hi, mshrs_0.io.status.valid)
node mshr_validOH_lo_hi_hi = cat(mshrs_5.io.status.valid, mshrs_4.io.status.valid)
node mshr_validOH_lo_hi = cat(mshr_validOH_lo_hi_hi, mshrs_3.io.status.valid)
node mshr_validOH_lo = cat(mshr_validOH_lo_hi, mshr_validOH_lo_lo)
node mshr_validOH_hi_lo_hi = cat(mshrs_8.io.status.valid, mshrs_7.io.status.valid)
node mshr_validOH_hi_lo = cat(mshr_validOH_hi_lo_hi, mshrs_6.io.status.valid)
node mshr_validOH_hi_hi_hi = cat(mshrs_11.io.status.valid, mshrs_10.io.status.valid)
node mshr_validOH_hi_hi = cat(mshr_validOH_hi_hi_hi, mshrs_9.io.status.valid)
node mshr_validOH_hi = cat(mshr_validOH_hi_hi, mshr_validOH_hi_lo)
node mshr_validOH = cat(mshr_validOH_hi, mshr_validOH_lo)
node _mshr_free_T = not(mshr_validOH)
node _mshr_free_T_1 = and(_mshr_free_T, prioFilter)
node mshr_free = orr(_mshr_free_T_1)
node bypassQueue = and(schedule.reload, bypassMatches)
node _request_alloc_cases_T = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _request_alloc_cases_T_1 = and(alloc, _request_alloc_cases_T)
node _request_alloc_cases_T_2 = and(_request_alloc_cases_T_1, mshr_free)
node _request_alloc_cases_T_3 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _request_alloc_cases_T_4 = and(nestB, _request_alloc_cases_T_3)
node _request_alloc_cases_T_5 = eq(mshrs_10.io.status.valid, UInt<1>(0h0))
node _request_alloc_cases_T_6 = and(_request_alloc_cases_T_4, _request_alloc_cases_T_5)
node _request_alloc_cases_T_7 = eq(mshrs_11.io.status.valid, UInt<1>(0h0))
node _request_alloc_cases_T_8 = and(_request_alloc_cases_T_6, _request_alloc_cases_T_7)
node _request_alloc_cases_T_9 = or(_request_alloc_cases_T_2, _request_alloc_cases_T_8)
node _request_alloc_cases_T_10 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _request_alloc_cases_T_11 = and(nestC, _request_alloc_cases_T_10)
node _request_alloc_cases_T_12 = eq(mshrs_11.io.status.valid, UInt<1>(0h0))
node _request_alloc_cases_T_13 = and(_request_alloc_cases_T_11, _request_alloc_cases_T_12)
node request_alloc_cases = or(_request_alloc_cases_T_9, _request_alloc_cases_T_13)
node _request_ready_T = or(bypassQueue, requests.io.push.ready)
node _request_ready_T_1 = and(queue, _request_ready_T)
node _request_ready_T_2 = or(request_alloc_cases, _request_ready_T_1)
connect request.ready, _request_ready_T_2
node alloc_uses_directory = and(request.valid, request_alloc_cases)
node _directory_io_read_valid_T = or(mshr_uses_directory, alloc_uses_directory)
connect directory.io.read.valid, _directory_io_read_valid_T
node _directory_io_read_bits_set_T = mux(mshr_uses_directory_for_lb, scheduleSet, request.bits.set)
connect directory.io.read.bits.set, _directory_io_read_bits_set_T
node _directory_io_read_bits_tag_T = mux(mshr_uses_directory_for_lb, requests.io.data.tag, request.bits.tag)
connect directory.io.read.bits.tag, _directory_io_read_bits_tag_T
node _requests_io_push_valid_T = and(request.valid, queue)
node _requests_io_push_valid_T_1 = eq(bypassQueue, UInt<1>(0h0))
node _requests_io_push_valid_T_2 = and(_requests_io_push_valid_T, _requests_io_push_valid_T_1)
connect requests.io.push.valid, _requests_io_push_valid_T_2
connect requests.io.push.bits.data.put, request.bits.put
connect requests.io.push.bits.data.offset, request.bits.offset
connect requests.io.push.bits.data.tag, request.bits.tag
connect requests.io.push.bits.data.source, request.bits.source
connect requests.io.push.bits.data.size, request.bits.size
connect requests.io.push.bits.data.param, request.bits.param
connect requests.io.push.bits.data.opcode, request.bits.opcode
connect requests.io.push.bits.data.control, request.bits.control
connect requests.io.push.bits.data.prio[0], request.bits.prio[0]
connect requests.io.push.bits.data.prio[1], request.bits.prio[1]
connect requests.io.push.bits.data.prio[2], request.bits.prio[2]
node _requests_io_push_bits_index_T = shl(lowerMatches1, 0)
node requests_io_push_bits_index_hi = bits(_requests_io_push_bits_index_T, 11, 8)
node requests_io_push_bits_index_lo = bits(_requests_io_push_bits_index_T, 7, 0)
node _requests_io_push_bits_index_T_1 = orr(requests_io_push_bits_index_hi)
node _requests_io_push_bits_index_T_2 = or(requests_io_push_bits_index_hi, requests_io_push_bits_index_lo)
node requests_io_push_bits_index_hi_1 = bits(_requests_io_push_bits_index_T_2, 7, 4)
node requests_io_push_bits_index_lo_1 = bits(_requests_io_push_bits_index_T_2, 3, 0)
node _requests_io_push_bits_index_T_3 = orr(requests_io_push_bits_index_hi_1)
node _requests_io_push_bits_index_T_4 = or(requests_io_push_bits_index_hi_1, requests_io_push_bits_index_lo_1)
node requests_io_push_bits_index_hi_2 = bits(_requests_io_push_bits_index_T_4, 3, 2)
node requests_io_push_bits_index_lo_2 = bits(_requests_io_push_bits_index_T_4, 1, 0)
node _requests_io_push_bits_index_T_5 = orr(requests_io_push_bits_index_hi_2)
node _requests_io_push_bits_index_T_6 = or(requests_io_push_bits_index_hi_2, requests_io_push_bits_index_lo_2)
node _requests_io_push_bits_index_T_7 = bits(_requests_io_push_bits_index_T_6, 1, 1)
node _requests_io_push_bits_index_T_8 = cat(_requests_io_push_bits_index_T_5, _requests_io_push_bits_index_T_7)
node _requests_io_push_bits_index_T_9 = cat(_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_8)
node _requests_io_push_bits_index_T_10 = cat(_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_9)
node _requests_io_push_bits_index_T_11 = shl(lowerMatches1, 12)
node requests_io_push_bits_index_hi_3 = bits(_requests_io_push_bits_index_T_11, 23, 16)
node requests_io_push_bits_index_lo_3 = bits(_requests_io_push_bits_index_T_11, 15, 0)
node _requests_io_push_bits_index_T_12 = orr(requests_io_push_bits_index_hi_3)
node _requests_io_push_bits_index_T_13 = or(requests_io_push_bits_index_hi_3, requests_io_push_bits_index_lo_3)
node requests_io_push_bits_index_hi_4 = bits(_requests_io_push_bits_index_T_13, 15, 8)
node requests_io_push_bits_index_lo_4 = bits(_requests_io_push_bits_index_T_13, 7, 0)
node _requests_io_push_bits_index_T_14 = orr(requests_io_push_bits_index_hi_4)
node _requests_io_push_bits_index_T_15 = or(requests_io_push_bits_index_hi_4, requests_io_push_bits_index_lo_4)
node requests_io_push_bits_index_hi_5 = bits(_requests_io_push_bits_index_T_15, 7, 4)
node requests_io_push_bits_index_lo_5 = bits(_requests_io_push_bits_index_T_15, 3, 0)
node _requests_io_push_bits_index_T_16 = orr(requests_io_push_bits_index_hi_5)
node _requests_io_push_bits_index_T_17 = or(requests_io_push_bits_index_hi_5, requests_io_push_bits_index_lo_5)
node requests_io_push_bits_index_hi_6 = bits(_requests_io_push_bits_index_T_17, 3, 2)
node requests_io_push_bits_index_lo_6 = bits(_requests_io_push_bits_index_T_17, 1, 0)
node _requests_io_push_bits_index_T_18 = orr(requests_io_push_bits_index_hi_6)
node _requests_io_push_bits_index_T_19 = or(requests_io_push_bits_index_hi_6, requests_io_push_bits_index_lo_6)
node _requests_io_push_bits_index_T_20 = bits(_requests_io_push_bits_index_T_19, 1, 1)
node _requests_io_push_bits_index_T_21 = cat(_requests_io_push_bits_index_T_18, _requests_io_push_bits_index_T_20)
node _requests_io_push_bits_index_T_22 = cat(_requests_io_push_bits_index_T_16, _requests_io_push_bits_index_T_21)
node _requests_io_push_bits_index_T_23 = cat(_requests_io_push_bits_index_T_14, _requests_io_push_bits_index_T_22)
node _requests_io_push_bits_index_T_24 = cat(_requests_io_push_bits_index_T_12, _requests_io_push_bits_index_T_23)
node _requests_io_push_bits_index_T_25 = shl(lowerMatches1, 24)
node requests_io_push_bits_index_hi_7 = bits(_requests_io_push_bits_index_T_25, 35, 32)
node requests_io_push_bits_index_lo_7 = bits(_requests_io_push_bits_index_T_25, 31, 0)
node _requests_io_push_bits_index_T_26 = orr(requests_io_push_bits_index_hi_7)
node _requests_io_push_bits_index_T_27 = or(requests_io_push_bits_index_hi_7, requests_io_push_bits_index_lo_7)
node requests_io_push_bits_index_hi_8 = bits(_requests_io_push_bits_index_T_27, 31, 16)
node requests_io_push_bits_index_lo_8 = bits(_requests_io_push_bits_index_T_27, 15, 0)
node _requests_io_push_bits_index_T_28 = orr(requests_io_push_bits_index_hi_8)
node _requests_io_push_bits_index_T_29 = or(requests_io_push_bits_index_hi_8, requests_io_push_bits_index_lo_8)
node requests_io_push_bits_index_hi_9 = bits(_requests_io_push_bits_index_T_29, 15, 8)
node requests_io_push_bits_index_lo_9 = bits(_requests_io_push_bits_index_T_29, 7, 0)
node _requests_io_push_bits_index_T_30 = orr(requests_io_push_bits_index_hi_9)
node _requests_io_push_bits_index_T_31 = or(requests_io_push_bits_index_hi_9, requests_io_push_bits_index_lo_9)
node requests_io_push_bits_index_hi_10 = bits(_requests_io_push_bits_index_T_31, 7, 4)
node requests_io_push_bits_index_lo_10 = bits(_requests_io_push_bits_index_T_31, 3, 0)
node _requests_io_push_bits_index_T_32 = orr(requests_io_push_bits_index_hi_10)
node _requests_io_push_bits_index_T_33 = or(requests_io_push_bits_index_hi_10, requests_io_push_bits_index_lo_10)
node requests_io_push_bits_index_hi_11 = bits(_requests_io_push_bits_index_T_33, 3, 2)
node requests_io_push_bits_index_lo_11 = bits(_requests_io_push_bits_index_T_33, 1, 0)
node _requests_io_push_bits_index_T_34 = orr(requests_io_push_bits_index_hi_11)
node _requests_io_push_bits_index_T_35 = or(requests_io_push_bits_index_hi_11, requests_io_push_bits_index_lo_11)
node _requests_io_push_bits_index_T_36 = bits(_requests_io_push_bits_index_T_35, 1, 1)
node _requests_io_push_bits_index_T_37 = cat(_requests_io_push_bits_index_T_34, _requests_io_push_bits_index_T_36)
node _requests_io_push_bits_index_T_38 = cat(_requests_io_push_bits_index_T_32, _requests_io_push_bits_index_T_37)
node _requests_io_push_bits_index_T_39 = cat(_requests_io_push_bits_index_T_30, _requests_io_push_bits_index_T_38)
node _requests_io_push_bits_index_T_40 = cat(_requests_io_push_bits_index_T_28, _requests_io_push_bits_index_T_39)
node _requests_io_push_bits_index_T_41 = cat(_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_40)
node _requests_io_push_bits_index_T_42 = mux(request.bits.prio[0], _requests_io_push_bits_index_T_10, UInt<1>(0h0))
node _requests_io_push_bits_index_T_43 = mux(request.bits.prio[1], _requests_io_push_bits_index_T_24, UInt<1>(0h0))
node _requests_io_push_bits_index_T_44 = mux(request.bits.prio[2], _requests_io_push_bits_index_T_41, UInt<1>(0h0))
node _requests_io_push_bits_index_T_45 = or(_requests_io_push_bits_index_T_42, _requests_io_push_bits_index_T_43)
node _requests_io_push_bits_index_T_46 = or(_requests_io_push_bits_index_T_45, _requests_io_push_bits_index_T_44)
wire _requests_io_push_bits_index_WIRE : UInt<6>
connect _requests_io_push_bits_index_WIRE, _requests_io_push_bits_index_T_46
connect requests.io.push.bits.index, _requests_io_push_bits_index_WIRE
node _mshr_insertOH_T = not(mshr_validOH)
node _mshr_insertOH_T_1 = shl(_mshr_insertOH_T, 1)
node _mshr_insertOH_T_2 = bits(_mshr_insertOH_T_1, 11, 0)
node _mshr_insertOH_T_3 = or(_mshr_insertOH_T, _mshr_insertOH_T_2)
node _mshr_insertOH_T_4 = shl(_mshr_insertOH_T_3, 2)
node _mshr_insertOH_T_5 = bits(_mshr_insertOH_T_4, 11, 0)
node _mshr_insertOH_T_6 = or(_mshr_insertOH_T_3, _mshr_insertOH_T_5)
node _mshr_insertOH_T_7 = shl(_mshr_insertOH_T_6, 4)
node _mshr_insertOH_T_8 = bits(_mshr_insertOH_T_7, 11, 0)
node _mshr_insertOH_T_9 = or(_mshr_insertOH_T_6, _mshr_insertOH_T_8)
node _mshr_insertOH_T_10 = shl(_mshr_insertOH_T_9, 8)
node _mshr_insertOH_T_11 = bits(_mshr_insertOH_T_10, 11, 0)
node _mshr_insertOH_T_12 = or(_mshr_insertOH_T_9, _mshr_insertOH_T_11)
node _mshr_insertOH_T_13 = bits(_mshr_insertOH_T_12, 11, 0)
node _mshr_insertOH_T_14 = shl(_mshr_insertOH_T_13, 1)
node _mshr_insertOH_T_15 = not(_mshr_insertOH_T_14)
node _mshr_insertOH_T_16 = not(mshr_validOH)
node _mshr_insertOH_T_17 = and(_mshr_insertOH_T_15, _mshr_insertOH_T_16)
node mshr_insertOH = and(_mshr_insertOH_T_17, prioFilter)
node _T_19 = bits(mshr_insertOH, 0, 0)
node _T_20 = bits(mshr_insertOH, 1, 1)
node _T_21 = bits(mshr_insertOH, 2, 2)
node _T_22 = bits(mshr_insertOH, 3, 3)
node _T_23 = bits(mshr_insertOH, 4, 4)
node _T_24 = bits(mshr_insertOH, 5, 5)
node _T_25 = bits(mshr_insertOH, 6, 6)
node _T_26 = bits(mshr_insertOH, 7, 7)
node _T_27 = bits(mshr_insertOH, 8, 8)
node _T_28 = bits(mshr_insertOH, 9, 9)
node _T_29 = bits(mshr_insertOH, 10, 10)
node _T_30 = bits(mshr_insertOH, 11, 11)
node _T_31 = bits(mshr_insertOH, 12, 12)
node _T_32 = and(request.valid, alloc)
node _T_33 = and(_T_32, _T_19)
node _T_34 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_35 = and(_T_33, _T_34)
when _T_35 :
connect mshrs_0.io.allocate.valid, UInt<1>(0h1)
connect mshrs_0.io.allocate.bits.set, request.bits.set
connect mshrs_0.io.allocate.bits.put, request.bits.put
connect mshrs_0.io.allocate.bits.offset, request.bits.offset
connect mshrs_0.io.allocate.bits.tag, request.bits.tag
connect mshrs_0.io.allocate.bits.source, request.bits.source
connect mshrs_0.io.allocate.bits.size, request.bits.size
connect mshrs_0.io.allocate.bits.param, request.bits.param
connect mshrs_0.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_0.io.allocate.bits.control, request.bits.control
connect mshrs_0.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_0.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_0.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_0.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_36 = and(request.valid, alloc)
node _T_37 = and(_T_36, _T_20)
node _T_38 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38)
when _T_39 :
connect mshrs_1.io.allocate.valid, UInt<1>(0h1)
connect mshrs_1.io.allocate.bits.set, request.bits.set
connect mshrs_1.io.allocate.bits.put, request.bits.put
connect mshrs_1.io.allocate.bits.offset, request.bits.offset
connect mshrs_1.io.allocate.bits.tag, request.bits.tag
connect mshrs_1.io.allocate.bits.source, request.bits.source
connect mshrs_1.io.allocate.bits.size, request.bits.size
connect mshrs_1.io.allocate.bits.param, request.bits.param
connect mshrs_1.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_1.io.allocate.bits.control, request.bits.control
connect mshrs_1.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_1.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_1.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_1.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_40 = and(request.valid, alloc)
node _T_41 = and(_T_40, _T_21)
node _T_42 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_43 = and(_T_41, _T_42)
when _T_43 :
connect mshrs_2.io.allocate.valid, UInt<1>(0h1)
connect mshrs_2.io.allocate.bits.set, request.bits.set
connect mshrs_2.io.allocate.bits.put, request.bits.put
connect mshrs_2.io.allocate.bits.offset, request.bits.offset
connect mshrs_2.io.allocate.bits.tag, request.bits.tag
connect mshrs_2.io.allocate.bits.source, request.bits.source
connect mshrs_2.io.allocate.bits.size, request.bits.size
connect mshrs_2.io.allocate.bits.param, request.bits.param
connect mshrs_2.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_2.io.allocate.bits.control, request.bits.control
connect mshrs_2.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_2.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_2.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_2.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_44 = and(request.valid, alloc)
node _T_45 = and(_T_44, _T_22)
node _T_46 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_47 = and(_T_45, _T_46)
when _T_47 :
connect mshrs_3.io.allocate.valid, UInt<1>(0h1)
connect mshrs_3.io.allocate.bits.set, request.bits.set
connect mshrs_3.io.allocate.bits.put, request.bits.put
connect mshrs_3.io.allocate.bits.offset, request.bits.offset
connect mshrs_3.io.allocate.bits.tag, request.bits.tag
connect mshrs_3.io.allocate.bits.source, request.bits.source
connect mshrs_3.io.allocate.bits.size, request.bits.size
connect mshrs_3.io.allocate.bits.param, request.bits.param
connect mshrs_3.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_3.io.allocate.bits.control, request.bits.control
connect mshrs_3.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_3.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_3.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_3.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_48 = and(request.valid, alloc)
node _T_49 = and(_T_48, _T_23)
node _T_50 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
when _T_51 :
connect mshrs_4.io.allocate.valid, UInt<1>(0h1)
connect mshrs_4.io.allocate.bits.set, request.bits.set
connect mshrs_4.io.allocate.bits.put, request.bits.put
connect mshrs_4.io.allocate.bits.offset, request.bits.offset
connect mshrs_4.io.allocate.bits.tag, request.bits.tag
connect mshrs_4.io.allocate.bits.source, request.bits.source
connect mshrs_4.io.allocate.bits.size, request.bits.size
connect mshrs_4.io.allocate.bits.param, request.bits.param
connect mshrs_4.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_4.io.allocate.bits.control, request.bits.control
connect mshrs_4.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_4.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_4.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_4.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_52 = and(request.valid, alloc)
node _T_53 = and(_T_52, _T_24)
node _T_54 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_55 = and(_T_53, _T_54)
when _T_55 :
connect mshrs_5.io.allocate.valid, UInt<1>(0h1)
connect mshrs_5.io.allocate.bits.set, request.bits.set
connect mshrs_5.io.allocate.bits.put, request.bits.put
connect mshrs_5.io.allocate.bits.offset, request.bits.offset
connect mshrs_5.io.allocate.bits.tag, request.bits.tag
connect mshrs_5.io.allocate.bits.source, request.bits.source
connect mshrs_5.io.allocate.bits.size, request.bits.size
connect mshrs_5.io.allocate.bits.param, request.bits.param
connect mshrs_5.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_5.io.allocate.bits.control, request.bits.control
connect mshrs_5.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_5.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_5.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_5.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_56 = and(request.valid, alloc)
node _T_57 = and(_T_56, _T_25)
node _T_58 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_59 = and(_T_57, _T_58)
when _T_59 :
connect mshrs_6.io.allocate.valid, UInt<1>(0h1)
connect mshrs_6.io.allocate.bits.set, request.bits.set
connect mshrs_6.io.allocate.bits.put, request.bits.put
connect mshrs_6.io.allocate.bits.offset, request.bits.offset
connect mshrs_6.io.allocate.bits.tag, request.bits.tag
connect mshrs_6.io.allocate.bits.source, request.bits.source
connect mshrs_6.io.allocate.bits.size, request.bits.size
connect mshrs_6.io.allocate.bits.param, request.bits.param
connect mshrs_6.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_6.io.allocate.bits.control, request.bits.control
connect mshrs_6.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_6.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_6.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_6.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_60 = and(request.valid, alloc)
node _T_61 = and(_T_60, _T_26)
node _T_62 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_63 = and(_T_61, _T_62)
when _T_63 :
connect mshrs_7.io.allocate.valid, UInt<1>(0h1)
connect mshrs_7.io.allocate.bits.set, request.bits.set
connect mshrs_7.io.allocate.bits.put, request.bits.put
connect mshrs_7.io.allocate.bits.offset, request.bits.offset
connect mshrs_7.io.allocate.bits.tag, request.bits.tag
connect mshrs_7.io.allocate.bits.source, request.bits.source
connect mshrs_7.io.allocate.bits.size, request.bits.size
connect mshrs_7.io.allocate.bits.param, request.bits.param
connect mshrs_7.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_7.io.allocate.bits.control, request.bits.control
connect mshrs_7.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_7.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_7.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_7.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_64 = and(request.valid, alloc)
node _T_65 = and(_T_64, _T_27)
node _T_66 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_67 = and(_T_65, _T_66)
when _T_67 :
connect mshrs_8.io.allocate.valid, UInt<1>(0h1)
connect mshrs_8.io.allocate.bits.set, request.bits.set
connect mshrs_8.io.allocate.bits.put, request.bits.put
connect mshrs_8.io.allocate.bits.offset, request.bits.offset
connect mshrs_8.io.allocate.bits.tag, request.bits.tag
connect mshrs_8.io.allocate.bits.source, request.bits.source
connect mshrs_8.io.allocate.bits.size, request.bits.size
connect mshrs_8.io.allocate.bits.param, request.bits.param
connect mshrs_8.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_8.io.allocate.bits.control, request.bits.control
connect mshrs_8.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_8.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_8.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_8.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_68 = and(request.valid, alloc)
node _T_69 = and(_T_68, _T_28)
node _T_70 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_71 = and(_T_69, _T_70)
when _T_71 :
connect mshrs_9.io.allocate.valid, UInt<1>(0h1)
connect mshrs_9.io.allocate.bits.set, request.bits.set
connect mshrs_9.io.allocate.bits.put, request.bits.put
connect mshrs_9.io.allocate.bits.offset, request.bits.offset
connect mshrs_9.io.allocate.bits.tag, request.bits.tag
connect mshrs_9.io.allocate.bits.source, request.bits.source
connect mshrs_9.io.allocate.bits.size, request.bits.size
connect mshrs_9.io.allocate.bits.param, request.bits.param
connect mshrs_9.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_9.io.allocate.bits.control, request.bits.control
connect mshrs_9.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_9.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_9.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_9.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_72 = and(request.valid, alloc)
node _T_73 = and(_T_72, _T_29)
node _T_74 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_75 = and(_T_73, _T_74)
when _T_75 :
connect mshrs_10.io.allocate.valid, UInt<1>(0h1)
connect mshrs_10.io.allocate.bits.set, request.bits.set
connect mshrs_10.io.allocate.bits.put, request.bits.put
connect mshrs_10.io.allocate.bits.offset, request.bits.offset
connect mshrs_10.io.allocate.bits.tag, request.bits.tag
connect mshrs_10.io.allocate.bits.source, request.bits.source
connect mshrs_10.io.allocate.bits.size, request.bits.size
connect mshrs_10.io.allocate.bits.param, request.bits.param
connect mshrs_10.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_10.io.allocate.bits.control, request.bits.control
connect mshrs_10.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_10.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_10.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_10.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_76 = and(request.valid, alloc)
node _T_77 = and(_T_76, _T_30)
node _T_78 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_79 = and(_T_77, _T_78)
when _T_79 :
connect mshrs_11.io.allocate.valid, UInt<1>(0h1)
connect mshrs_11.io.allocate.bits.set, request.bits.set
connect mshrs_11.io.allocate.bits.put, request.bits.put
connect mshrs_11.io.allocate.bits.offset, request.bits.offset
connect mshrs_11.io.allocate.bits.tag, request.bits.tag
connect mshrs_11.io.allocate.bits.source, request.bits.source
connect mshrs_11.io.allocate.bits.size, request.bits.size
connect mshrs_11.io.allocate.bits.param, request.bits.param
connect mshrs_11.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_11.io.allocate.bits.control, request.bits.control
connect mshrs_11.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_11.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_11.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_11.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_80 = and(request.valid, nestB)
node _T_81 = eq(mshrs_10.io.status.valid, UInt<1>(0h0))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(mshrs_11.io.status.valid, UInt<1>(0h0))
node _T_84 = and(_T_82, _T_83)
node _T_85 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_86 = and(_T_84, _T_85)
when _T_86 :
connect mshrs_10.io.allocate.valid, UInt<1>(0h1)
connect mshrs_10.io.allocate.bits.set, request.bits.set
connect mshrs_10.io.allocate.bits.put, request.bits.put
connect mshrs_10.io.allocate.bits.offset, request.bits.offset
connect mshrs_10.io.allocate.bits.tag, request.bits.tag
connect mshrs_10.io.allocate.bits.source, request.bits.source
connect mshrs_10.io.allocate.bits.size, request.bits.size
connect mshrs_10.io.allocate.bits.param, request.bits.param
connect mshrs_10.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_10.io.allocate.bits.control, request.bits.control
connect mshrs_10.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_10.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_10.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_10.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_87 = eq(request.bits.prio[0], UInt<1>(0h0))
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:291 assert (!request.bits.prio(0))\n") : printf
assert(clock, _T_87, UInt<1>(0h1), "") : assert
connect mshrs_10.io.allocate.bits.prio[0], UInt<1>(0h0)
node _T_91 = and(request.valid, nestC)
node _T_92 = eq(mshrs_11.io.status.valid, UInt<1>(0h0))
node _T_93 = and(_T_91, _T_92)
node _T_94 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_95 = and(_T_93, _T_94)
when _T_95 :
connect mshrs_11.io.allocate.valid, UInt<1>(0h1)
connect mshrs_11.io.allocate.bits.set, request.bits.set
connect mshrs_11.io.allocate.bits.put, request.bits.put
connect mshrs_11.io.allocate.bits.offset, request.bits.offset
connect mshrs_11.io.allocate.bits.tag, request.bits.tag
connect mshrs_11.io.allocate.bits.source, request.bits.source
connect mshrs_11.io.allocate.bits.size, request.bits.size
connect mshrs_11.io.allocate.bits.param, request.bits.param
connect mshrs_11.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_11.io.allocate.bits.control, request.bits.control
connect mshrs_11.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_11.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_11.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_11.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_96 = eq(request.bits.prio[0], UInt<1>(0h0))
node _T_97 = asUInt(reset)
node _T_98 = eq(_T_97, UInt<1>(0h0))
when _T_98 :
node _T_99 = eq(_T_96, UInt<1>(0h0))
when _T_99 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:299 assert (!request.bits.prio(0))\n") : printf_1
assert(clock, _T_96, UInt<1>(0h1), "") : assert_1
node _T_100 = eq(request.bits.prio[1], UInt<1>(0h0))
node _T_101 = asUInt(reset)
node _T_102 = eq(_T_101, UInt<1>(0h0))
when _T_102 :
node _T_103 = eq(_T_100, UInt<1>(0h0))
when _T_103 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:300 assert (!request.bits.prio(1))\n") : printf_2
assert(clock, _T_100, UInt<1>(0h1), "") : assert_2
connect mshrs_11.io.allocate.bits.prio[0], UInt<1>(0h0)
connect mshrs_11.io.allocate.bits.prio[1], UInt<1>(0h0)
node _dirTarget_T = mux(nestB, UInt<11>(0h400), UInt<12>(0h800))
node dirTarget = mux(alloc, mshr_insertOH, _dirTarget_T)
node _directoryFanout_T = mux(alloc_uses_directory, dirTarget, UInt<1>(0h0))
node _directoryFanout_T_1 = mux(mshr_uses_directory, mshr_selectOH, _directoryFanout_T)
reg directoryFanout : UInt, clock
connect directoryFanout, _directoryFanout_T_1
node _mshrs_0_io_directory_valid_T = bits(directoryFanout, 0, 0)
connect mshrs_0.io.directory.valid, _mshrs_0_io_directory_valid_T
connect mshrs_0.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_0.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_0.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_0.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_0.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_0.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_1_io_directory_valid_T = bits(directoryFanout, 1, 1)
connect mshrs_1.io.directory.valid, _mshrs_1_io_directory_valid_T
connect mshrs_1.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_1.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_1.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_1.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_1.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_1.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_2_io_directory_valid_T = bits(directoryFanout, 2, 2)
connect mshrs_2.io.directory.valid, _mshrs_2_io_directory_valid_T
connect mshrs_2.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_2.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_2.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_2.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_2.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_2.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_3_io_directory_valid_T = bits(directoryFanout, 3, 3)
connect mshrs_3.io.directory.valid, _mshrs_3_io_directory_valid_T
connect mshrs_3.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_3.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_3.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_3.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_3.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_3.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_4_io_directory_valid_T = bits(directoryFanout, 4, 4)
connect mshrs_4.io.directory.valid, _mshrs_4_io_directory_valid_T
connect mshrs_4.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_4.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_4.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_4.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_4.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_4.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_5_io_directory_valid_T = bits(directoryFanout, 5, 5)
connect mshrs_5.io.directory.valid, _mshrs_5_io_directory_valid_T
connect mshrs_5.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_5.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_5.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_5.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_5.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_5.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_6_io_directory_valid_T = bits(directoryFanout, 6, 6)
connect mshrs_6.io.directory.valid, _mshrs_6_io_directory_valid_T
connect mshrs_6.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_6.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_6.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_6.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_6.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_6.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_7_io_directory_valid_T = bits(directoryFanout, 7, 7)
connect mshrs_7.io.directory.valid, _mshrs_7_io_directory_valid_T
connect mshrs_7.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_7.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_7.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_7.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_7.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_7.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_8_io_directory_valid_T = bits(directoryFanout, 8, 8)
connect mshrs_8.io.directory.valid, _mshrs_8_io_directory_valid_T
connect mshrs_8.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_8.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_8.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_8.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_8.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_8.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_9_io_directory_valid_T = bits(directoryFanout, 9, 9)
connect mshrs_9.io.directory.valid, _mshrs_9_io_directory_valid_T
connect mshrs_9.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_9.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_9.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_9.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_9.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_9.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_10_io_directory_valid_T = bits(directoryFanout, 10, 10)
connect mshrs_10.io.directory.valid, _mshrs_10_io_directory_valid_T
connect mshrs_10.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_10.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_10.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_10.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_10.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_10.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_11_io_directory_valid_T = bits(directoryFanout, 11, 11)
connect mshrs_11.io.directory.valid, _mshrs_11_io_directory_valid_T
connect mshrs_11.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_11.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_11.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_11.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_11.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_11.io.directory.bits.dirty, directory.io.result.bits.dirty
node _sinkC_io_way_T = eq(mshrs_10.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_1 = and(mshrs_10.io.status.valid, _sinkC_io_way_T)
node _sinkC_io_way_T_2 = eq(mshrs_0.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_3 = and(mshrs_0.io.status.valid, _sinkC_io_way_T_2)
node _sinkC_io_way_T_4 = eq(mshrs_1.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_5 = and(mshrs_1.io.status.valid, _sinkC_io_way_T_4)
node _sinkC_io_way_T_6 = eq(mshrs_2.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_7 = and(mshrs_2.io.status.valid, _sinkC_io_way_T_6)
node _sinkC_io_way_T_8 = eq(mshrs_3.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_9 = and(mshrs_3.io.status.valid, _sinkC_io_way_T_8)
node _sinkC_io_way_T_10 = eq(mshrs_4.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_11 = and(mshrs_4.io.status.valid, _sinkC_io_way_T_10)
node _sinkC_io_way_T_12 = eq(mshrs_5.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_13 = and(mshrs_5.io.status.valid, _sinkC_io_way_T_12)
node _sinkC_io_way_T_14 = eq(mshrs_6.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_15 = and(mshrs_6.io.status.valid, _sinkC_io_way_T_14)
node _sinkC_io_way_T_16 = eq(mshrs_7.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_17 = and(mshrs_7.io.status.valid, _sinkC_io_way_T_16)
node _sinkC_io_way_T_18 = eq(mshrs_8.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_19 = and(mshrs_8.io.status.valid, _sinkC_io_way_T_18)
node _sinkC_io_way_T_20 = eq(mshrs_9.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_21 = and(mshrs_9.io.status.valid, _sinkC_io_way_T_20)
node _sinkC_io_way_T_22 = mux(_sinkC_io_way_T_3, mshrs_0.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_23 = mux(_sinkC_io_way_T_5, mshrs_1.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_24 = mux(_sinkC_io_way_T_7, mshrs_2.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_25 = mux(_sinkC_io_way_T_9, mshrs_3.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_26 = mux(_sinkC_io_way_T_11, mshrs_4.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_27 = mux(_sinkC_io_way_T_13, mshrs_5.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_28 = mux(_sinkC_io_way_T_15, mshrs_6.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_29 = mux(_sinkC_io_way_T_17, mshrs_7.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_30 = mux(_sinkC_io_way_T_19, mshrs_8.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_31 = mux(_sinkC_io_way_T_21, mshrs_9.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_32 = or(_sinkC_io_way_T_22, _sinkC_io_way_T_23)
node _sinkC_io_way_T_33 = or(_sinkC_io_way_T_32, _sinkC_io_way_T_24)
node _sinkC_io_way_T_34 = or(_sinkC_io_way_T_33, _sinkC_io_way_T_25)
node _sinkC_io_way_T_35 = or(_sinkC_io_way_T_34, _sinkC_io_way_T_26)
node _sinkC_io_way_T_36 = or(_sinkC_io_way_T_35, _sinkC_io_way_T_27)
node _sinkC_io_way_T_37 = or(_sinkC_io_way_T_36, _sinkC_io_way_T_28)
node _sinkC_io_way_T_38 = or(_sinkC_io_way_T_37, _sinkC_io_way_T_29)
node _sinkC_io_way_T_39 = or(_sinkC_io_way_T_38, _sinkC_io_way_T_30)
node _sinkC_io_way_T_40 = or(_sinkC_io_way_T_39, _sinkC_io_way_T_31)
wire _sinkC_io_way_WIRE : UInt<4>
connect _sinkC_io_way_WIRE, _sinkC_io_way_T_40
node _sinkC_io_way_T_41 = mux(_sinkC_io_way_T_1, mshrs_10.io.status.bits.way, _sinkC_io_way_WIRE)
connect sinkC.io.way, _sinkC_io_way_T_41
wire _sinkD_io_way_WIRE : UInt<4>[12]
connect _sinkD_io_way_WIRE[0], mshrs_0.io.status.bits.way
connect _sinkD_io_way_WIRE[1], mshrs_1.io.status.bits.way
connect _sinkD_io_way_WIRE[2], mshrs_2.io.status.bits.way
connect _sinkD_io_way_WIRE[3], mshrs_3.io.status.bits.way
connect _sinkD_io_way_WIRE[4], mshrs_4.io.status.bits.way
connect _sinkD_io_way_WIRE[5], mshrs_5.io.status.bits.way
connect _sinkD_io_way_WIRE[6], mshrs_6.io.status.bits.way
connect _sinkD_io_way_WIRE[7], mshrs_7.io.status.bits.way
connect _sinkD_io_way_WIRE[8], mshrs_8.io.status.bits.way
connect _sinkD_io_way_WIRE[9], mshrs_9.io.status.bits.way
connect _sinkD_io_way_WIRE[10], mshrs_10.io.status.bits.way
connect _sinkD_io_way_WIRE[11], mshrs_11.io.status.bits.way
connect sinkD.io.way, _sinkD_io_way_WIRE[sinkD.io.source]
wire _sinkD_io_set_WIRE : UInt<11>[12]
connect _sinkD_io_set_WIRE[0], mshrs_0.io.status.bits.set
connect _sinkD_io_set_WIRE[1], mshrs_1.io.status.bits.set
connect _sinkD_io_set_WIRE[2], mshrs_2.io.status.bits.set
connect _sinkD_io_set_WIRE[3], mshrs_3.io.status.bits.set
connect _sinkD_io_set_WIRE[4], mshrs_4.io.status.bits.set
connect _sinkD_io_set_WIRE[5], mshrs_5.io.status.bits.set
connect _sinkD_io_set_WIRE[6], mshrs_6.io.status.bits.set
connect _sinkD_io_set_WIRE[7], mshrs_7.io.status.bits.set
connect _sinkD_io_set_WIRE[8], mshrs_8.io.status.bits.set
connect _sinkD_io_set_WIRE[9], mshrs_9.io.status.bits.set
connect _sinkD_io_set_WIRE[10], mshrs_10.io.status.bits.set
connect _sinkD_io_set_WIRE[11], mshrs_11.io.status.bits.set
connect sinkD.io.set, _sinkD_io_set_WIRE[sinkD.io.source]
connect sinkA.io.pb_pop, sourceD.io.pb_pop
connect sourceD.io.pb_beat.corrupt, sinkA.io.pb_beat.corrupt
connect sourceD.io.pb_beat.mask, sinkA.io.pb_beat.mask
connect sourceD.io.pb_beat.data, sinkA.io.pb_beat.data
connect sinkC.io.rel_pop, sourceD.io.rel_pop
connect sourceD.io.rel_beat.corrupt, sinkC.io.rel_beat.corrupt
connect sourceD.io.rel_beat.data, sinkC.io.rel_beat.data
connect bankedStore.io.sinkC_adr, sinkC.io.bs_adr
connect bankedStore.io.sinkC_dat.data, sinkC.io.bs_dat.data
connect bankedStore.io.sinkD_adr, sinkD.io.bs_adr
connect bankedStore.io.sinkD_dat.data, sinkD.io.bs_dat.data
connect bankedStore.io.sourceC_adr, sourceC.io.bs_adr
connect bankedStore.io.sourceD_radr, sourceD.io.bs_radr
connect bankedStore.io.sourceD_wadr, sourceD.io.bs_wadr
connect bankedStore.io.sourceD_wdat.data, sourceD.io.bs_wdat.data
connect sourceC.io.bs_dat.data, bankedStore.io.sourceC_dat.data
connect sourceD.io.bs_rdat.data, bankedStore.io.sourceD_rdat.data
connect sourceD.io.evict_req.way, sourceC.io.evict_req.way
connect sourceD.io.evict_req.set, sourceC.io.evict_req.set
connect sourceD.io.grant_req.way, sinkD.io.grant_req.way
connect sourceD.io.grant_req.set, sinkD.io.grant_req.set
connect sourceC.io.evict_safe, sourceD.io.evict_safe
connect sinkD.io.grant_safe, sourceD.io.grant_safe | module InclusiveCacheBankScheduler_5( // @[Scheduler.scala:27:7]
input clock, // @[Scheduler.scala:27:7]
input reset, // @[Scheduler.scala:27:7]
output io_in_a_ready, // @[Scheduler.scala:29:14]
input io_in_a_valid, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_opcode, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_size, // @[Scheduler.scala:29:14]
input [5:0] io_in_a_bits_source, // @[Scheduler.scala:29:14]
input [31:0] io_in_a_bits_address, // @[Scheduler.scala:29:14]
input [15:0] io_in_a_bits_mask, // @[Scheduler.scala:29:14]
input [127:0] io_in_a_bits_data, // @[Scheduler.scala:29:14]
input io_in_a_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_b_ready, // @[Scheduler.scala:29:14]
output io_in_b_valid, // @[Scheduler.scala:29:14]
output [1:0] io_in_b_bits_param, // @[Scheduler.scala:29:14]
output [31:0] io_in_b_bits_address, // @[Scheduler.scala:29:14]
output io_in_c_ready, // @[Scheduler.scala:29:14]
input io_in_c_valid, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_opcode, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_size, // @[Scheduler.scala:29:14]
input [5:0] io_in_c_bits_source, // @[Scheduler.scala:29:14]
input [31:0] io_in_c_bits_address, // @[Scheduler.scala:29:14]
input [127:0] io_in_c_bits_data, // @[Scheduler.scala:29:14]
input io_in_c_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_d_ready, // @[Scheduler.scala:29:14]
output io_in_d_valid, // @[Scheduler.scala:29:14]
output [2:0] io_in_d_bits_opcode, // @[Scheduler.scala:29:14]
output [1:0] io_in_d_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_in_d_bits_size, // @[Scheduler.scala:29:14]
output [5:0] io_in_d_bits_source, // @[Scheduler.scala:29:14]
output [3:0] io_in_d_bits_sink, // @[Scheduler.scala:29:14]
output io_in_d_bits_denied, // @[Scheduler.scala:29:14]
output [127:0] io_in_d_bits_data, // @[Scheduler.scala:29:14]
output io_in_d_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_e_valid, // @[Scheduler.scala:29:14]
input [3:0] io_in_e_bits_sink, // @[Scheduler.scala:29:14]
input io_out_a_ready, // @[Scheduler.scala:29:14]
output io_out_a_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_opcode, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_size, // @[Scheduler.scala:29:14]
output [3:0] io_out_a_bits_source, // @[Scheduler.scala:29:14]
output [31:0] io_out_a_bits_address, // @[Scheduler.scala:29:14]
output [7:0] io_out_a_bits_mask, // @[Scheduler.scala:29:14]
output [63:0] io_out_a_bits_data, // @[Scheduler.scala:29:14]
output io_out_a_bits_corrupt, // @[Scheduler.scala:29:14]
input io_out_c_ready, // @[Scheduler.scala:29:14]
output io_out_c_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_opcode, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_size, // @[Scheduler.scala:29:14]
output [3:0] io_out_c_bits_source, // @[Scheduler.scala:29:14]
output [31:0] io_out_c_bits_address, // @[Scheduler.scala:29:14]
output [63:0] io_out_c_bits_data, // @[Scheduler.scala:29:14]
output io_out_c_bits_corrupt, // @[Scheduler.scala:29:14]
output io_out_d_ready, // @[Scheduler.scala:29:14]
input io_out_d_valid, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_opcode, // @[Scheduler.scala:29:14]
input [1:0] io_out_d_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_size, // @[Scheduler.scala:29:14]
input [3:0] io_out_d_bits_source, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_sink, // @[Scheduler.scala:29:14]
input io_out_d_bits_denied, // @[Scheduler.scala:29:14]
input [63:0] io_out_d_bits_data, // @[Scheduler.scala:29:14]
input io_out_d_bits_corrupt, // @[Scheduler.scala:29:14]
output io_out_e_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_e_bits_sink, // @[Scheduler.scala:29:14]
output io_req_ready, // @[Scheduler.scala:29:14]
input io_req_valid, // @[Scheduler.scala:29:14]
input [31:0] io_req_bits_address, // @[Scheduler.scala:29:14]
output io_resp_valid // @[Scheduler.scala:29:14]
);
wire [8:0] mshrs_11_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :295:103, :297:73]
wire [8:0] mshrs_10_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :287:131, :289:74]
wire [8:0] mshrs_9_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_8_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_7_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_6_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_5_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_4_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_3_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_2_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_1_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [8:0] mshrs_0_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [5:0] request_bits_put; // @[Scheduler.scala:163:21]
wire [5:0] request_bits_offset; // @[Scheduler.scala:163:21]
wire [8:0] request_bits_tag; // @[Scheduler.scala:163:21]
wire [5:0] request_bits_source; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_size; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_param; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_opcode; // @[Scheduler.scala:163:21]
wire request_bits_control; // @[Scheduler.scala:163:21]
wire request_bits_prio_2; // @[Scheduler.scala:163:21]
wire request_bits_prio_0; // @[Scheduler.scala:163:21]
wire _mshrs_11_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_11_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_11_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_11_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_11_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_11_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_11_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_11_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_11_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_11_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_10_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_10_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_10_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_10_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_10_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_10_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_10_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_10_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_10_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_10_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_9_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_9_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_9_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_9_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_9_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_9_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_9_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_9_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_9_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_9_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_8_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_8_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_8_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_8_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_8_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_8_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_8_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_8_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_8_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_8_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_7_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_7_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_7_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_7_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_7_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_7_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_7_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_7_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_7_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_7_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_6_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_6_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_6_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_6_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_6_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_6_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_6_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_6_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_6_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_6_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_5_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_5_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_5_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_5_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_5_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_5_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_5_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_5_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_5_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_5_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_4_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_4_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_4_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_4_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_4_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_4_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_4_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_4_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_4_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_4_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_3_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_3_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_3_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_3_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_3_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_3_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_3_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_3_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_3_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_3_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_2_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_2_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_2_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_2_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_2_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_2_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_2_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_2_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_2_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_2_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_1_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_1_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_1_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_1_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_1_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_1_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_1_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_1_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_1_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_1_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_0_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_0_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_0_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_0_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_0_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_0_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [10:0] _mshrs_0_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [3:0] _mshrs_0_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_0_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [8:0] _mshrs_0_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _requests_io_push_ready; // @[Scheduler.scala:70:24]
wire [35:0] _requests_io_valid; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_0; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_1; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_2; // @[Scheduler.scala:70:24]
wire _requests_io_data_control; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_opcode; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_param; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_size; // @[Scheduler.scala:70:24]
wire [5:0] _requests_io_data_source; // @[Scheduler.scala:70:24]
wire [8:0] _requests_io_data_tag; // @[Scheduler.scala:70:24]
wire [5:0] _requests_io_data_offset; // @[Scheduler.scala:70:24]
wire [5:0] _requests_io_data_put; // @[Scheduler.scala:70:24]
wire _bankedStore_io_sinkC_adr_ready; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sinkD_adr_ready; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceC_adr_ready; // @[Scheduler.scala:69:27]
wire [63:0] _bankedStore_io_sourceC_dat_data; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceD_radr_ready; // @[Scheduler.scala:69:27]
wire [127:0] _bankedStore_io_sourceD_rdat_data; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceD_wadr_ready; // @[Scheduler.scala:69:27]
wire _directory_io_write_ready; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_dirty; // @[Scheduler.scala:68:25]
wire [1:0] _directory_io_result_bits_state; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_clients; // @[Scheduler.scala:68:25]
wire [8:0] _directory_io_result_bits_tag; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_hit; // @[Scheduler.scala:68:25]
wire [3:0] _directory_io_result_bits_way; // @[Scheduler.scala:68:25]
wire _directory_io_ready; // @[Scheduler.scala:68:25]
wire _sinkX_io_req_valid; // @[Scheduler.scala:58:21]
wire [8:0] _sinkX_io_req_bits_tag; // @[Scheduler.scala:58:21]
wire [10:0] _sinkX_io_req_bits_set; // @[Scheduler.scala:58:21]
wire _sinkE_io_resp_valid; // @[Scheduler.scala:57:21]
wire [3:0] _sinkE_io_resp_bits_sink; // @[Scheduler.scala:57:21]
wire _sinkD_io_resp_valid; // @[Scheduler.scala:56:21]
wire _sinkD_io_resp_bits_last; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_opcode; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_param; // @[Scheduler.scala:56:21]
wire [3:0] _sinkD_io_resp_bits_source; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_sink; // @[Scheduler.scala:56:21]
wire _sinkD_io_resp_bits_denied; // @[Scheduler.scala:56:21]
wire [3:0] _sinkD_io_source; // @[Scheduler.scala:56:21]
wire _sinkD_io_bs_adr_valid; // @[Scheduler.scala:56:21]
wire _sinkD_io_bs_adr_bits_noop; // @[Scheduler.scala:56:21]
wire [3:0] _sinkD_io_bs_adr_bits_way; // @[Scheduler.scala:56:21]
wire [10:0] _sinkD_io_bs_adr_bits_set; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_bs_adr_bits_beat; // @[Scheduler.scala:56:21]
wire [63:0] _sinkD_io_bs_dat_data; // @[Scheduler.scala:56:21]
wire [10:0] _sinkD_io_grant_req_set; // @[Scheduler.scala:56:21]
wire [3:0] _sinkD_io_grant_req_way; // @[Scheduler.scala:56:21]
wire _sinkC_io_req_valid; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_opcode; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_param; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_size; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_req_bits_source; // @[Scheduler.scala:55:21]
wire [8:0] _sinkC_io_req_bits_tag; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_req_bits_offset; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_req_bits_put; // @[Scheduler.scala:55:21]
wire [10:0] _sinkC_io_req_bits_set; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_valid; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_bits_last; // @[Scheduler.scala:55:21]
wire [10:0] _sinkC_io_resp_bits_set; // @[Scheduler.scala:55:21]
wire [8:0] _sinkC_io_resp_bits_tag; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_resp_bits_source; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_resp_bits_param; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_bits_data; // @[Scheduler.scala:55:21]
wire [10:0] _sinkC_io_set; // @[Scheduler.scala:55:21]
wire _sinkC_io_bs_adr_valid; // @[Scheduler.scala:55:21]
wire _sinkC_io_bs_adr_bits_noop; // @[Scheduler.scala:55:21]
wire [3:0] _sinkC_io_bs_adr_bits_way; // @[Scheduler.scala:55:21]
wire [10:0] _sinkC_io_bs_adr_bits_set; // @[Scheduler.scala:55:21]
wire [1:0] _sinkC_io_bs_adr_bits_beat; // @[Scheduler.scala:55:21]
wire [1:0] _sinkC_io_bs_adr_bits_mask; // @[Scheduler.scala:55:21]
wire [127:0] _sinkC_io_bs_dat_data; // @[Scheduler.scala:55:21]
wire _sinkC_io_rel_pop_ready; // @[Scheduler.scala:55:21]
wire [127:0] _sinkC_io_rel_beat_data; // @[Scheduler.scala:55:21]
wire _sinkC_io_rel_beat_corrupt; // @[Scheduler.scala:55:21]
wire _sinkA_io_req_valid; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21]
wire [5:0] _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21]
wire [8:0] _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21]
wire [5:0] _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21]
wire [5:0] _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21]
wire [10:0] _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21]
wire _sinkA_io_pb_pop_ready; // @[Scheduler.scala:54:21]
wire [127:0] _sinkA_io_pb_beat_data; // @[Scheduler.scala:54:21]
wire [15:0] _sinkA_io_pb_beat_mask; // @[Scheduler.scala:54:21]
wire _sinkA_io_pb_beat_corrupt; // @[Scheduler.scala:54:21]
wire _sourceX_io_req_ready; // @[Scheduler.scala:45:23]
wire _sourceE_io_req_ready; // @[Scheduler.scala:44:23]
wire _sourceD_io_req_ready; // @[Scheduler.scala:43:23]
wire _sourceD_io_pb_pop_valid; // @[Scheduler.scala:43:23]
wire [5:0] _sourceD_io_pb_pop_bits_index; // @[Scheduler.scala:43:23]
wire _sourceD_io_pb_pop_bits_last; // @[Scheduler.scala:43:23]
wire _sourceD_io_rel_pop_valid; // @[Scheduler.scala:43:23]
wire [5:0] _sourceD_io_rel_pop_bits_index; // @[Scheduler.scala:43:23]
wire _sourceD_io_rel_pop_bits_last; // @[Scheduler.scala:43:23]
wire _sourceD_io_bs_radr_valid; // @[Scheduler.scala:43:23]
wire [3:0] _sourceD_io_bs_radr_bits_way; // @[Scheduler.scala:43:23]
wire [10:0] _sourceD_io_bs_radr_bits_set; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_radr_bits_beat; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_radr_bits_mask; // @[Scheduler.scala:43:23]
wire _sourceD_io_bs_wadr_valid; // @[Scheduler.scala:43:23]
wire [3:0] _sourceD_io_bs_wadr_bits_way; // @[Scheduler.scala:43:23]
wire [10:0] _sourceD_io_bs_wadr_bits_set; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_wadr_bits_beat; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_wadr_bits_mask; // @[Scheduler.scala:43:23]
wire [127:0] _sourceD_io_bs_wdat_data; // @[Scheduler.scala:43:23]
wire _sourceD_io_evict_safe; // @[Scheduler.scala:43:23]
wire _sourceD_io_grant_safe; // @[Scheduler.scala:43:23]
wire _sourceC_io_req_ready; // @[Scheduler.scala:42:23]
wire _sourceC_io_bs_adr_valid; // @[Scheduler.scala:42:23]
wire [3:0] _sourceC_io_bs_adr_bits_way; // @[Scheduler.scala:42:23]
wire [10:0] _sourceC_io_bs_adr_bits_set; // @[Scheduler.scala:42:23]
wire [2:0] _sourceC_io_bs_adr_bits_beat; // @[Scheduler.scala:42:23]
wire [10:0] _sourceC_io_evict_req_set; // @[Scheduler.scala:42:23]
wire [3:0] _sourceC_io_evict_req_way; // @[Scheduler.scala:42:23]
wire _sourceB_io_req_ready; // @[Scheduler.scala:41:23]
wire _sourceA_io_req_ready; // @[Scheduler.scala:40:23]
wire io_in_a_valid_0 = io_in_a_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Scheduler.scala:27:7]
wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Scheduler.scala:27:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Scheduler.scala:27:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Scheduler.scala:27:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Scheduler.scala:27:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Scheduler.scala:27:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Scheduler.scala:27:7]
wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Scheduler.scala:27:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Scheduler.scala:27:7]
wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Scheduler.scala:27:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Scheduler.scala:27:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Scheduler.scala:27:7]
wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Scheduler.scala:27:7]
wire io_out_a_ready_0 = io_out_a_ready; // @[Scheduler.scala:27:7]
wire io_out_c_ready_0 = io_out_c_ready; // @[Scheduler.scala:27:7]
wire io_out_d_valid_0 = io_out_d_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_opcode_0 = io_out_d_bits_opcode; // @[Scheduler.scala:27:7]
wire [1:0] io_out_d_bits_param_0 = io_out_d_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_size_0 = io_out_d_bits_size; // @[Scheduler.scala:27:7]
wire [3:0] io_out_d_bits_source_0 = io_out_d_bits_source; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_sink_0 = io_out_d_bits_sink; // @[Scheduler.scala:27:7]
wire io_out_d_bits_denied_0 = io_out_d_bits_denied; // @[Scheduler.scala:27:7]
wire [63:0] io_out_d_bits_data_0 = io_out_d_bits_data; // @[Scheduler.scala:27:7]
wire io_out_d_bits_corrupt_0 = io_out_d_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_req_valid_0 = io_req_valid; // @[Scheduler.scala:27:7]
wire [31:0] io_req_bits_address_0 = io_req_bits_address; // @[Scheduler.scala:27:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7]
wire io_out_b_valid = 1'h0; // @[Scheduler.scala:27:7]
wire io_out_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7]
wire io_resp_bits_fail = 1'h0; // @[Scheduler.scala:27:7]
wire schedule_x_bits_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_11_bits_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_12_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_196 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_197 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_198 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_199 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_200 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_201 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_202 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_203 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_204 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_205 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_206 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_207 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_208 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_209 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_210 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_211 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_212 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_213 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_214 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_215 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_216 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_217 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_218 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_13 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_574 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_575 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_598 = 1'h0; // @[Mux.scala:30:73]
wire request_bits_prio_1 = 1'h0; // @[Scheduler.scala:163:21]
wire _request_bits_T_prio_1 = 1'h0; // @[Scheduler.scala:166:22]
wire _request_bits_T_prio_2 = 1'h0; // @[Scheduler.scala:166:22]
wire _request_bits_T_1_prio_1 = 1'h0; // @[Scheduler.scala:165:22]
wire blockB = 1'h0; // @[Scheduler.scala:175:70]
wire nestB = 1'h0; // @[Scheduler.scala:179:70]
wire _view__WIRE_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_1_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_2_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_3_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_4_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_5_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_6_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_7_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_8_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_9_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_10_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_11_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _request_alloc_cases_T_4 = 1'h0; // @[Scheduler.scala:259:13]
wire _request_alloc_cases_T_6 = 1'h0; // @[Scheduler.scala:259:56]
wire _request_alloc_cases_T_8 = 1'h0; // @[Scheduler.scala:259:84]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Scheduler.scala:27:7]
wire [2:0] io_in_b_bits_size = 3'h6; // @[Scheduler.scala:27:7]
wire [5:0] io_in_b_bits_source = 6'h28; // @[Scheduler.scala:27:7]
wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Scheduler.scala:27:7]
wire [127:0] io_in_b_bits_data = 128'h0; // @[Scheduler.scala:27:7]
wire io_in_e_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_out_b_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_out_e_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_resp_ready = 1'h1; // @[Scheduler.scala:27:7]
wire _mshr_request_T_253 = 1'h1; // @[Scheduler.scala:107:28]
wire _request_bits_T_prio_0 = 1'h1; // @[Scheduler.scala:166:22]
wire _queue_T_1 = 1'h1; // @[Scheduler.scala:185:35]
wire _queue_T_5 = 1'h1; // @[Scheduler.scala:185:55]
wire [2:0] io_out_b_bits_opcode = 3'h0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_b_bits_size = 3'h0; // @[Scheduler.scala:27:7]
wire [1:0] io_out_b_bits_param = 2'h0; // @[Scheduler.scala:27:7]
wire [3:0] io_out_b_bits_source = 4'h0; // @[Scheduler.scala:27:7]
wire [3:0] _schedule_WIRE_19_bits_sink = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_20_sink = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_334 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_335 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_336 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_337 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_338 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_339 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_340 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_341 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_342 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_343 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_344 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_345 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_346 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_347 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_348 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_349 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_350 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_351 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_352 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_353 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_354 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_355 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_356 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_23 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_38_bits_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_39_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_748 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_749 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_750 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_751 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_752 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_753 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_754 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_755 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_756 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_757 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_758 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_759 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_760 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_761 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_762 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_763 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_764 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_765 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_766 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_767 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_768 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_769 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_770 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_44 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_55_bits_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_56_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_978 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_979 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_980 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_981 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_982 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_983 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_984 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_985 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_986 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_987 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_988 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_989 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_990 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_991 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_992 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_993 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_994 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_995 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_996 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_997 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_998 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_999 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_1000 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_58 = 4'h0; // @[Mux.scala:30:73]
wire [31:0] io_out_b_bits_address = 32'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_out_b_bits_mask = 8'h0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_b_bits_data = 64'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_0 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_1 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_2 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_3 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_4 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_5 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_6 = 16'h0; // @[Scheduler.scala:27:7]
wire [15:0] io_ways_7 = 16'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_0 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_1 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_2 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_3 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_4 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_5 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_6 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_7 = 11'h0; // @[Scheduler.scala:27:7]
wire [11:0] _lowerMatches1_T_1 = 12'h800; // @[Scheduler.scala:200:43]
wire [11:0] _dirTarget_T = 12'h800; // @[Scheduler.scala:306:48]
wire [4:0] _requests_io_push_bits_index_T_43 = 5'h0; // @[Mux.scala:30:73]
wire [9:0] _prioFilter_T_1 = 10'h3FF; // @[Scheduler.scala:182:69]
wire [10:0] _lowerMatches1_T_3 = 11'h400; // @[Scheduler.scala:201:43]
wire io_in_a_ready_0; // @[Scheduler.scala:27:7]
wire [1:0] io_in_b_bits_param_0; // @[Scheduler.scala:27:7]
wire [31:0] io_in_b_bits_address_0; // @[Scheduler.scala:27:7]
wire io_in_b_valid_0; // @[Scheduler.scala:27:7]
wire io_in_c_ready_0; // @[Scheduler.scala:27:7]
wire [2:0] io_in_d_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [1:0] io_in_d_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_in_d_bits_size_0; // @[Scheduler.scala:27:7]
wire [5:0] io_in_d_bits_source_0; // @[Scheduler.scala:27:7]
wire [3:0] io_in_d_bits_sink_0; // @[Scheduler.scala:27:7]
wire io_in_d_bits_denied_0; // @[Scheduler.scala:27:7]
wire [127:0] io_in_d_bits_data_0; // @[Scheduler.scala:27:7]
wire io_in_d_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_in_d_valid_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_size_0; // @[Scheduler.scala:27:7]
wire [3:0] io_out_a_bits_source_0; // @[Scheduler.scala:27:7]
wire [31:0] io_out_a_bits_address_0; // @[Scheduler.scala:27:7]
wire [7:0] io_out_a_bits_mask_0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_a_bits_data_0; // @[Scheduler.scala:27:7]
wire io_out_a_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_out_a_valid_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_size_0; // @[Scheduler.scala:27:7]
wire [3:0] io_out_c_bits_source_0; // @[Scheduler.scala:27:7]
wire [31:0] io_out_c_bits_address_0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_c_bits_data_0; // @[Scheduler.scala:27:7]
wire io_out_c_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_out_c_valid_0; // @[Scheduler.scala:27:7]
wire io_out_d_ready_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_e_bits_sink_0; // @[Scheduler.scala:27:7]
wire io_out_e_valid_0; // @[Scheduler.scala:27:7]
wire io_req_ready_0; // @[Scheduler.scala:27:7]
wire io_resp_valid_0; // @[Scheduler.scala:27:7]
wire [10:0] _nestedwb_set_T; // @[Scheduler.scala:155:24]
wire [8:0] _nestedwb_tag_T; // @[Scheduler.scala:156:24]
wire _nestedwb_b_toN_T_2; // @[Scheduler.scala:157:75]
wire _nestedwb_b_toB_T_2; // @[Scheduler.scala:158:75]
wire _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:159:37]
wire _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:160:75]
wire [10:0] nestedwb_set; // @[Scheduler.scala:75:22]
wire [8:0] nestedwb_tag; // @[Scheduler.scala:75:22]
wire nestedwb_b_toN; // @[Scheduler.scala:75:22]
wire nestedwb_b_toB; // @[Scheduler.scala:75:22]
wire nestedwb_b_clr_dirty; // @[Scheduler.scala:75:22]
wire nestedwb_c_set_dirty; // @[Scheduler.scala:75:22]
wire _mshrs_0_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_0_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_0_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_0_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_0_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h0; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_0_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_0_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_0_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h0; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_0_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_0_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_1_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_1_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_1_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_1_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_1_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h1; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_1_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_1_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_1_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h1; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_1_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_1_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_2_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_2_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_2_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_2_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_2_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h2; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_2_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_2_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_2_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h2; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_2_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_2_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_3_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_3_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_3_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_3_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_3_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h3; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_3_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_3_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_3_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h3; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_3_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_3_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_4_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_4_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_4_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_4_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_4_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h4; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_4_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_4_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_4_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h4; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_4_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_4_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_5_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_5_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_5_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_5_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h5; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_5_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_5_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_5_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h5; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_5_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_5_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_6_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_6_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_6_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_6_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h6; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_6_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_6_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_6_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h6; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_6_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_6_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_7_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_7_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_7_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_7_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_7_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h7; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_7_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_7_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_7_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h7; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_7_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_7_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_8_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_8_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_8_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_8_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_8_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h8; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_8_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_8_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_8_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h8; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_8_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_8_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_9_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_9_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_9_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_9_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_9_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h9; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_9_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_9_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_9_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h9; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_9_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_9_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_10_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_10_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_10_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_10_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'hA; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_10_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_10_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_10_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'hA; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_10_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_10_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_11_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_11_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_11_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_11_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'hB; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_11_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_11_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_11_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'hB; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_11_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_11_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshr_stall_abc_T = _mshrs_0_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_1 = _mshrs_10_io_status_valid & _mshr_stall_abc_T; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_2 = _mshrs_0_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_3 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_2; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_0 = _mshr_stall_abc_T_1 | _mshr_stall_abc_T_3; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_4 = _mshrs_1_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_5 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_4; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_6 = _mshrs_1_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_7 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_6; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_1 = _mshr_stall_abc_T_5 | _mshr_stall_abc_T_7; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_8 = _mshrs_2_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_9 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_8; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_10 = _mshrs_2_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_11 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_10; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_2 = _mshr_stall_abc_T_9 | _mshr_stall_abc_T_11; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_12 = _mshrs_3_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_13 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_12; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_14 = _mshrs_3_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_15 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_14; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_3 = _mshr_stall_abc_T_13 | _mshr_stall_abc_T_15; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_16 = _mshrs_4_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_17 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_16; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_18 = _mshrs_4_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_19 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_18; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_4 = _mshr_stall_abc_T_17 | _mshr_stall_abc_T_19; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_20 = _mshrs_5_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_21 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_20; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_22 = _mshrs_5_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_23 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_22; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_5 = _mshr_stall_abc_T_21 | _mshr_stall_abc_T_23; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_24 = _mshrs_6_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_25 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_24; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_26 = _mshrs_6_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_27 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_26; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_6 = _mshr_stall_abc_T_25 | _mshr_stall_abc_T_27; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_28 = _mshrs_7_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_29 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_28; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_30 = _mshrs_7_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_31 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_30; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_7 = _mshr_stall_abc_T_29 | _mshr_stall_abc_T_31; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_32 = _mshrs_8_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_33 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_32; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_34 = _mshrs_8_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_35 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_34; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_8 = _mshr_stall_abc_T_33 | _mshr_stall_abc_T_35; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_36 = _mshrs_9_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_37 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_36; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_38 = _mshrs_9_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_39 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_38; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_9 = _mshr_stall_abc_T_37 | _mshr_stall_abc_T_39; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_bc_T = _mshrs_10_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :94:58]
wire mshr_stall_bc = _mshrs_11_io_status_valid & _mshr_stall_bc_T; // @[Scheduler.scala:71:46, :94:{28,58}]
wire stall_abc_0 = mshr_stall_abc_0 & _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_1 = mshr_stall_abc_1 & _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_2 = mshr_stall_abc_2 & _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_3 = mshr_stall_abc_3 & _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_4 = mshr_stall_abc_4 & _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_5 = mshr_stall_abc_5 & _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_6 = mshr_stall_abc_6 & _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_7 = mshr_stall_abc_7 & _mshrs_7_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_8 = mshr_stall_abc_8 & _mshrs_8_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_9 = mshr_stall_abc_9 & _mshrs_9_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire _mshr_request_T = ~mshr_stall_abc_0; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_1 = _mshrs_0_io_schedule_valid & _mshr_request_T; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_2 = ~_mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_3 = _sourceA_io_req_ready | _mshr_request_T_2; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_4 = _mshr_request_T_1 & _mshr_request_T_3; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_5 = ~_mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_6 = _sourceB_io_req_ready | _mshr_request_T_5; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_7 = _mshr_request_T_4 & _mshr_request_T_6; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_8 = ~_mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_9 = _sourceC_io_req_ready | _mshr_request_T_8; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_10 = _mshr_request_T_7 & _mshr_request_T_9; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_11 = ~_mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_12 = _sourceD_io_req_ready | _mshr_request_T_11; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_13 = _mshr_request_T_10 & _mshr_request_T_12; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_14 = ~_mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_15 = _sourceE_io_req_ready | _mshr_request_T_14; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_16 = _mshr_request_T_13 & _mshr_request_T_15; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_17 = ~_mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_18 = _sourceX_io_req_ready | _mshr_request_T_17; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_19 = _mshr_request_T_16 & _mshr_request_T_18; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_20 = ~_mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_21 = _directory_io_write_ready | _mshr_request_T_20; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_22 = _mshr_request_T_19 & _mshr_request_T_21; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_23 = ~mshr_stall_abc_1; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_24 = _mshrs_1_io_schedule_valid & _mshr_request_T_23; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_25 = ~_mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_26 = _sourceA_io_req_ready | _mshr_request_T_25; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_27 = _mshr_request_T_24 & _mshr_request_T_26; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_28 = ~_mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_29 = _sourceB_io_req_ready | _mshr_request_T_28; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_30 = _mshr_request_T_27 & _mshr_request_T_29; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_31 = ~_mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_32 = _sourceC_io_req_ready | _mshr_request_T_31; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_33 = _mshr_request_T_30 & _mshr_request_T_32; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_34 = ~_mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_35 = _sourceD_io_req_ready | _mshr_request_T_34; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_36 = _mshr_request_T_33 & _mshr_request_T_35; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_37 = ~_mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_38 = _sourceE_io_req_ready | _mshr_request_T_37; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_39 = _mshr_request_T_36 & _mshr_request_T_38; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_40 = ~_mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_41 = _sourceX_io_req_ready | _mshr_request_T_40; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_42 = _mshr_request_T_39 & _mshr_request_T_41; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_43 = ~_mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_44 = _directory_io_write_ready | _mshr_request_T_43; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_45 = _mshr_request_T_42 & _mshr_request_T_44; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_46 = ~mshr_stall_abc_2; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_47 = _mshrs_2_io_schedule_valid & _mshr_request_T_46; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_48 = ~_mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_49 = _sourceA_io_req_ready | _mshr_request_T_48; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_50 = _mshr_request_T_47 & _mshr_request_T_49; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_51 = ~_mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_52 = _sourceB_io_req_ready | _mshr_request_T_51; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_53 = _mshr_request_T_50 & _mshr_request_T_52; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_54 = ~_mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_55 = _sourceC_io_req_ready | _mshr_request_T_54; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_56 = _mshr_request_T_53 & _mshr_request_T_55; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_57 = ~_mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_58 = _sourceD_io_req_ready | _mshr_request_T_57; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_59 = _mshr_request_T_56 & _mshr_request_T_58; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_60 = ~_mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_61 = _sourceE_io_req_ready | _mshr_request_T_60; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_62 = _mshr_request_T_59 & _mshr_request_T_61; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_63 = ~_mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_64 = _sourceX_io_req_ready | _mshr_request_T_63; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_65 = _mshr_request_T_62 & _mshr_request_T_64; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_66 = ~_mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_67 = _directory_io_write_ready | _mshr_request_T_66; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_68 = _mshr_request_T_65 & _mshr_request_T_67; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_69 = ~mshr_stall_abc_3; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_70 = _mshrs_3_io_schedule_valid & _mshr_request_T_69; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_71 = ~_mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_72 = _sourceA_io_req_ready | _mshr_request_T_71; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_73 = _mshr_request_T_70 & _mshr_request_T_72; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_74 = ~_mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_75 = _sourceB_io_req_ready | _mshr_request_T_74; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_76 = _mshr_request_T_73 & _mshr_request_T_75; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_77 = ~_mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_78 = _sourceC_io_req_ready | _mshr_request_T_77; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_79 = _mshr_request_T_76 & _mshr_request_T_78; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_80 = ~_mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_81 = _sourceD_io_req_ready | _mshr_request_T_80; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_82 = _mshr_request_T_79 & _mshr_request_T_81; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_83 = ~_mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_84 = _sourceE_io_req_ready | _mshr_request_T_83; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_85 = _mshr_request_T_82 & _mshr_request_T_84; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_86 = ~_mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_87 = _sourceX_io_req_ready | _mshr_request_T_86; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_88 = _mshr_request_T_85 & _mshr_request_T_87; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_89 = ~_mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_90 = _directory_io_write_ready | _mshr_request_T_89; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_91 = _mshr_request_T_88 & _mshr_request_T_90; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_92 = ~mshr_stall_abc_4; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_93 = _mshrs_4_io_schedule_valid & _mshr_request_T_92; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_94 = ~_mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_95 = _sourceA_io_req_ready | _mshr_request_T_94; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_96 = _mshr_request_T_93 & _mshr_request_T_95; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_97 = ~_mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_98 = _sourceB_io_req_ready | _mshr_request_T_97; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_99 = _mshr_request_T_96 & _mshr_request_T_98; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_100 = ~_mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_101 = _sourceC_io_req_ready | _mshr_request_T_100; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_102 = _mshr_request_T_99 & _mshr_request_T_101; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_103 = ~_mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_104 = _sourceD_io_req_ready | _mshr_request_T_103; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_105 = _mshr_request_T_102 & _mshr_request_T_104; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_106 = ~_mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_107 = _sourceE_io_req_ready | _mshr_request_T_106; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_108 = _mshr_request_T_105 & _mshr_request_T_107; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_109 = ~_mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_110 = _sourceX_io_req_ready | _mshr_request_T_109; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_111 = _mshr_request_T_108 & _mshr_request_T_110; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_112 = ~_mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_113 = _directory_io_write_ready | _mshr_request_T_112; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_114 = _mshr_request_T_111 & _mshr_request_T_113; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_115 = ~mshr_stall_abc_5; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_116 = _mshrs_5_io_schedule_valid & _mshr_request_T_115; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_117 = ~_mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_118 = _sourceA_io_req_ready | _mshr_request_T_117; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_119 = _mshr_request_T_116 & _mshr_request_T_118; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_120 = ~_mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_121 = _sourceB_io_req_ready | _mshr_request_T_120; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_122 = _mshr_request_T_119 & _mshr_request_T_121; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_123 = ~_mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_124 = _sourceC_io_req_ready | _mshr_request_T_123; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_125 = _mshr_request_T_122 & _mshr_request_T_124; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_126 = ~_mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_127 = _sourceD_io_req_ready | _mshr_request_T_126; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_128 = _mshr_request_T_125 & _mshr_request_T_127; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_129 = ~_mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_130 = _sourceE_io_req_ready | _mshr_request_T_129; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_131 = _mshr_request_T_128 & _mshr_request_T_130; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_132 = ~_mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_133 = _sourceX_io_req_ready | _mshr_request_T_132; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_134 = _mshr_request_T_131 & _mshr_request_T_133; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_135 = ~_mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_136 = _directory_io_write_ready | _mshr_request_T_135; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_137 = _mshr_request_T_134 & _mshr_request_T_136; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_138 = ~mshr_stall_abc_6; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_139 = _mshrs_6_io_schedule_valid & _mshr_request_T_138; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_140 = ~_mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_141 = _sourceA_io_req_ready | _mshr_request_T_140; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_142 = _mshr_request_T_139 & _mshr_request_T_141; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_143 = ~_mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_144 = _sourceB_io_req_ready | _mshr_request_T_143; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_145 = _mshr_request_T_142 & _mshr_request_T_144; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_146 = ~_mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_147 = _sourceC_io_req_ready | _mshr_request_T_146; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_148 = _mshr_request_T_145 & _mshr_request_T_147; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_149 = ~_mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_150 = _sourceD_io_req_ready | _mshr_request_T_149; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_151 = _mshr_request_T_148 & _mshr_request_T_150; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_152 = ~_mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_153 = _sourceE_io_req_ready | _mshr_request_T_152; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_154 = _mshr_request_T_151 & _mshr_request_T_153; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_155 = ~_mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_156 = _sourceX_io_req_ready | _mshr_request_T_155; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_157 = _mshr_request_T_154 & _mshr_request_T_156; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_158 = ~_mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_159 = _directory_io_write_ready | _mshr_request_T_158; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_160 = _mshr_request_T_157 & _mshr_request_T_159; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_161 = ~mshr_stall_abc_7; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_162 = _mshrs_7_io_schedule_valid & _mshr_request_T_161; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_163 = ~_mshrs_7_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_164 = _sourceA_io_req_ready | _mshr_request_T_163; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_165 = _mshr_request_T_162 & _mshr_request_T_164; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_166 = ~_mshrs_7_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_167 = _sourceB_io_req_ready | _mshr_request_T_166; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_168 = _mshr_request_T_165 & _mshr_request_T_167; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_169 = ~_mshrs_7_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_170 = _sourceC_io_req_ready | _mshr_request_T_169; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_171 = _mshr_request_T_168 & _mshr_request_T_170; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_172 = ~_mshrs_7_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_173 = _sourceD_io_req_ready | _mshr_request_T_172; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_174 = _mshr_request_T_171 & _mshr_request_T_173; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_175 = ~_mshrs_7_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_176 = _sourceE_io_req_ready | _mshr_request_T_175; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_177 = _mshr_request_T_174 & _mshr_request_T_176; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_178 = ~_mshrs_7_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_179 = _sourceX_io_req_ready | _mshr_request_T_178; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_180 = _mshr_request_T_177 & _mshr_request_T_179; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_181 = ~_mshrs_7_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_182 = _directory_io_write_ready | _mshr_request_T_181; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_183 = _mshr_request_T_180 & _mshr_request_T_182; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_184 = ~mshr_stall_abc_8; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_185 = _mshrs_8_io_schedule_valid & _mshr_request_T_184; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_186 = ~_mshrs_8_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_187 = _sourceA_io_req_ready | _mshr_request_T_186; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_188 = _mshr_request_T_185 & _mshr_request_T_187; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_189 = ~_mshrs_8_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_190 = _sourceB_io_req_ready | _mshr_request_T_189; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_191 = _mshr_request_T_188 & _mshr_request_T_190; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_192 = ~_mshrs_8_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_193 = _sourceC_io_req_ready | _mshr_request_T_192; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_194 = _mshr_request_T_191 & _mshr_request_T_193; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_195 = ~_mshrs_8_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_196 = _sourceD_io_req_ready | _mshr_request_T_195; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_197 = _mshr_request_T_194 & _mshr_request_T_196; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_198 = ~_mshrs_8_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_199 = _sourceE_io_req_ready | _mshr_request_T_198; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_200 = _mshr_request_T_197 & _mshr_request_T_199; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_201 = ~_mshrs_8_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_202 = _sourceX_io_req_ready | _mshr_request_T_201; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_203 = _mshr_request_T_200 & _mshr_request_T_202; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_204 = ~_mshrs_8_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_205 = _directory_io_write_ready | _mshr_request_T_204; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_206 = _mshr_request_T_203 & _mshr_request_T_205; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_207 = ~mshr_stall_abc_9; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_208 = _mshrs_9_io_schedule_valid & _mshr_request_T_207; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_209 = ~_mshrs_9_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_210 = _sourceA_io_req_ready | _mshr_request_T_209; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_211 = _mshr_request_T_208 & _mshr_request_T_210; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_212 = ~_mshrs_9_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_213 = _sourceB_io_req_ready | _mshr_request_T_212; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_214 = _mshr_request_T_211 & _mshr_request_T_213; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_215 = ~_mshrs_9_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_216 = _sourceC_io_req_ready | _mshr_request_T_215; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_217 = _mshr_request_T_214 & _mshr_request_T_216; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_218 = ~_mshrs_9_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_219 = _sourceD_io_req_ready | _mshr_request_T_218; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_220 = _mshr_request_T_217 & _mshr_request_T_219; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_221 = ~_mshrs_9_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_222 = _sourceE_io_req_ready | _mshr_request_T_221; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_223 = _mshr_request_T_220 & _mshr_request_T_222; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_224 = ~_mshrs_9_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_225 = _sourceX_io_req_ready | _mshr_request_T_224; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_226 = _mshr_request_T_223 & _mshr_request_T_225; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_227 = ~_mshrs_9_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_228 = _directory_io_write_ready | _mshr_request_T_227; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_229 = _mshr_request_T_226 & _mshr_request_T_228; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_230 = ~mshr_stall_bc; // @[Scheduler.scala:94:28, :107:28]
wire _mshr_request_T_231 = _mshrs_10_io_schedule_valid & _mshr_request_T_230; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_232 = ~_mshrs_10_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_233 = _sourceA_io_req_ready | _mshr_request_T_232; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_234 = _mshr_request_T_231 & _mshr_request_T_233; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_235 = ~_mshrs_10_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_236 = _sourceB_io_req_ready | _mshr_request_T_235; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_237 = _mshr_request_T_234 & _mshr_request_T_236; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_238 = ~_mshrs_10_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_239 = _sourceC_io_req_ready | _mshr_request_T_238; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_240 = _mshr_request_T_237 & _mshr_request_T_239; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_241 = ~_mshrs_10_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_242 = _sourceD_io_req_ready | _mshr_request_T_241; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_243 = _mshr_request_T_240 & _mshr_request_T_242; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_244 = ~_mshrs_10_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_245 = _sourceE_io_req_ready | _mshr_request_T_244; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_246 = _mshr_request_T_243 & _mshr_request_T_245; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_247 = ~_mshrs_10_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_248 = _sourceX_io_req_ready | _mshr_request_T_247; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_249 = _mshr_request_T_246 & _mshr_request_T_248; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_250 = ~_mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_251 = _directory_io_write_ready | _mshr_request_T_250; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_252 = _mshr_request_T_249 & _mshr_request_T_251; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_255 = ~_mshrs_11_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_256 = _sourceA_io_req_ready | _mshr_request_T_255; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_254; // @[Scheduler.scala:107:25]
wire _mshr_request_T_257 = _mshr_request_T_254 & _mshr_request_T_256; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_258 = ~_mshrs_11_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_259 = _sourceB_io_req_ready | _mshr_request_T_258; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_260 = _mshr_request_T_257 & _mshr_request_T_259; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_261 = ~_mshrs_11_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_262 = _sourceC_io_req_ready | _mshr_request_T_261; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_263 = _mshr_request_T_260 & _mshr_request_T_262; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_264 = ~_mshrs_11_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_265 = _sourceD_io_req_ready | _mshr_request_T_264; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_266 = _mshr_request_T_263 & _mshr_request_T_265; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_267 = ~_mshrs_11_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_268 = _sourceE_io_req_ready | _mshr_request_T_267; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_269 = _mshr_request_T_266 & _mshr_request_T_268; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_270 = ~_mshrs_11_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_271 = _sourceX_io_req_ready | _mshr_request_T_270; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_272 = _mshr_request_T_269 & _mshr_request_T_271; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_273 = ~_mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_274 = _directory_io_write_ready | _mshr_request_T_273; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_275 = _mshr_request_T_272 & _mshr_request_T_274; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire [1:0] mshr_request_lo_lo_hi = {_mshr_request_T_68, _mshr_request_T_45}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_lo_lo = {mshr_request_lo_lo_hi, _mshr_request_T_22}; // @[Scheduler.scala:106:25, :113:61]
wire [1:0] mshr_request_lo_hi_hi = {_mshr_request_T_137, _mshr_request_T_114}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_lo_hi = {mshr_request_lo_hi_hi, _mshr_request_T_91}; // @[Scheduler.scala:106:25, :113:61]
wire [5:0] mshr_request_lo = {mshr_request_lo_hi, mshr_request_lo_lo}; // @[Scheduler.scala:106:25]
wire [1:0] mshr_request_hi_lo_hi = {_mshr_request_T_206, _mshr_request_T_183}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_hi_lo = {mshr_request_hi_lo_hi, _mshr_request_T_160}; // @[Scheduler.scala:106:25, :113:61]
wire [1:0] mshr_request_hi_hi_hi = {_mshr_request_T_275, _mshr_request_T_252}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_hi_hi = {mshr_request_hi_hi_hi, _mshr_request_T_229}; // @[Scheduler.scala:106:25, :113:61]
wire [5:0] mshr_request_hi = {mshr_request_hi_hi, mshr_request_hi_lo}; // @[Scheduler.scala:106:25]
wire [11:0] mshr_request = {mshr_request_hi, mshr_request_lo}; // @[Scheduler.scala:106:25]
reg [11:0] robin_filter; // @[Scheduler.scala:118:29]
wire [11:0] _robin_request_T = mshr_request & robin_filter; // @[Scheduler.scala:106:25, :118:29, :119:54]
wire [23:0] robin_request = {mshr_request, _robin_request_T}; // @[Scheduler.scala:106:25, :119:{26,54}]
wire [24:0] _mshr_selectOH2_T = {robin_request, 1'h0}; // @[package.scala:253:48]
wire [23:0] _mshr_selectOH2_T_1 = _mshr_selectOH2_T[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_2 = robin_request | _mshr_selectOH2_T_1; // @[package.scala:253:{43,53}]
wire [25:0] _mshr_selectOH2_T_3 = {_mshr_selectOH2_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_4 = _mshr_selectOH2_T_3[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_5 = _mshr_selectOH2_T_2 | _mshr_selectOH2_T_4; // @[package.scala:253:{43,53}]
wire [27:0] _mshr_selectOH2_T_6 = {_mshr_selectOH2_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_7 = _mshr_selectOH2_T_6[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_8 = _mshr_selectOH2_T_5 | _mshr_selectOH2_T_7; // @[package.scala:253:{43,53}]
wire [31:0] _mshr_selectOH2_T_9 = {_mshr_selectOH2_T_8, 8'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_10 = _mshr_selectOH2_T_9[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_11 = _mshr_selectOH2_T_8 | _mshr_selectOH2_T_10; // @[package.scala:253:{43,53}]
wire [39:0] _mshr_selectOH2_T_12 = {_mshr_selectOH2_T_11, 16'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_13 = _mshr_selectOH2_T_12[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_14 = _mshr_selectOH2_T_11 | _mshr_selectOH2_T_13; // @[package.scala:253:{43,53}]
wire [23:0] _mshr_selectOH2_T_15 = _mshr_selectOH2_T_14; // @[package.scala:253:43, :254:17]
wire [24:0] _mshr_selectOH2_T_16 = {_mshr_selectOH2_T_15, 1'h0}; // @[package.scala:254:17]
wire [24:0] _mshr_selectOH2_T_17 = ~_mshr_selectOH2_T_16; // @[Scheduler.scala:120:{24,48}]
wire [24:0] mshr_selectOH2 = {1'h0, _mshr_selectOH2_T_17[23:0] & robin_request}; // @[Scheduler.scala:119:26, :120:{24,54}]
wire [11:0] _mshr_selectOH_T = mshr_selectOH2[23:12]; // @[Scheduler.scala:120:54, :121:37]
wire [11:0] _mshr_selectOH_T_1 = mshr_selectOH2[11:0]; // @[Scheduler.scala:120:54, :121:86]
wire [11:0] mshr_selectOH = _mshr_selectOH_T | _mshr_selectOH_T_1; // @[Scheduler.scala:121:{37,70,86}]
wire [3:0] mshr_select_hi = mshr_selectOH[11:8]; // @[OneHot.scala:30:18]
wire [7:0] mshr_select_lo = mshr_selectOH[7:0]; // @[OneHot.scala:31:18]
wire _mshr_select_T = |mshr_select_hi; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _mshr_select_T_1 = {4'h0, mshr_select_hi} | mshr_select_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] mshr_select_hi_1 = _mshr_select_T_1[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] mshr_select_lo_1 = _mshr_select_T_1[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _mshr_select_T_2 = |mshr_select_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _mshr_select_T_3 = mshr_select_hi_1 | mshr_select_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] mshr_select_hi_2 = _mshr_select_T_3[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] mshr_select_lo_2 = _mshr_select_T_3[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _mshr_select_T_4 = |mshr_select_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _mshr_select_T_5 = mshr_select_hi_2 | mshr_select_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _mshr_select_T_6 = _mshr_select_T_5[1]; // @[OneHot.scala:32:28]
wire [1:0] _mshr_select_T_7 = {_mshr_select_T_4, _mshr_select_T_6}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _mshr_select_T_8 = {_mshr_select_T_2, _mshr_select_T_7}; // @[OneHot.scala:32:{10,14}]
wire [3:0] mshr_select = {_mshr_select_T, _mshr_select_T_8}; // @[OneHot.scala:32:{10,14}]
wire [3:0] schedule_a_bits_source = mshr_select; // @[OneHot.scala:32:10]
wire [3:0] schedule_d_bits_sink = mshr_select; // @[OneHot.scala:32:10]
wire _schedule_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _scheduleTag_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _scheduleSet_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire sel = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _schedule_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _scheduleTag_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _scheduleSet_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire sel_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _schedule_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _scheduleTag_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _scheduleSet_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire sel_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _schedule_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _scheduleTag_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _scheduleSet_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire sel_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _schedule_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _scheduleTag_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _scheduleSet_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire sel_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _schedule_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _scheduleTag_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _scheduleSet_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire sel_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _schedule_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _scheduleTag_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _scheduleSet_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire sel_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _schedule_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire _scheduleTag_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire _scheduleSet_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire sel_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire _schedule_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire _scheduleTag_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire _scheduleSet_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire sel_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire _schedule_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire _scheduleTag_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire _scheduleSet_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire sel_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire _schedule_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire _scheduleTag_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire _scheduleSet_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire select_bc = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire sel_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire _schedule_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire _scheduleTag_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire _scheduleSet_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire select_c = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire sel_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire _schedule_WIRE_55_valid; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73]
wire _schedule_WIRE_48_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73]
wire _schedule_WIRE_38_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73]
wire [3:0] _schedule_c_bits_source_T_1; // @[Scheduler.scala:132:32]
wire [8:0] _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73]
wire _schedule_WIRE_15_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73]
wire _schedule_WIRE_11_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_valid; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73]
wire _schedule_WIRE; // @[Mux.scala:30:73]
wire [8:0] schedule_a_bits_tag; // @[Mux.scala:30:73]
wire [10:0] schedule_a_bits_set; // @[Mux.scala:30:73]
wire [2:0] schedule_a_bits_param; // @[Mux.scala:30:73]
wire schedule_a_bits_block; // @[Mux.scala:30:73]
wire schedule_a_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_b_bits_param; // @[Mux.scala:30:73]
wire [8:0] schedule_b_bits_tag; // @[Mux.scala:30:73]
wire [10:0] schedule_b_bits_set; // @[Mux.scala:30:73]
wire schedule_b_bits_clients; // @[Mux.scala:30:73]
wire schedule_b_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_c_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] schedule_c_bits_param; // @[Mux.scala:30:73]
wire [3:0] schedule_c_bits_source; // @[Mux.scala:30:73]
wire [8:0] schedule_c_bits_tag; // @[Mux.scala:30:73]
wire [10:0] schedule_c_bits_set; // @[Mux.scala:30:73]
wire [3:0] schedule_c_bits_way; // @[Mux.scala:30:73]
wire schedule_c_bits_dirty; // @[Mux.scala:30:73]
wire schedule_c_valid; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_0; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_1; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_2; // @[Mux.scala:30:73]
wire schedule_d_bits_control; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_param; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_size; // @[Mux.scala:30:73]
wire [5:0] schedule_d_bits_source; // @[Mux.scala:30:73]
wire [8:0] schedule_d_bits_tag; // @[Mux.scala:30:73]
wire [5:0] schedule_d_bits_offset; // @[Mux.scala:30:73]
wire [5:0] schedule_d_bits_put; // @[Mux.scala:30:73]
wire [10:0] schedule_d_bits_set; // @[Mux.scala:30:73]
wire [3:0] schedule_d_bits_way; // @[Mux.scala:30:73]
wire schedule_d_bits_bad; // @[Mux.scala:30:73]
wire schedule_d_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_e_bits_sink; // @[Mux.scala:30:73]
wire schedule_e_valid; // @[Mux.scala:30:73]
wire schedule_x_valid; // @[Mux.scala:30:73]
wire schedule_dir_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] schedule_dir_bits_data_state; // @[Mux.scala:30:73]
wire schedule_dir_bits_data_clients; // @[Mux.scala:30:73]
wire [8:0] schedule_dir_bits_data_tag; // @[Mux.scala:30:73]
wire [10:0] schedule_dir_bits_set; // @[Mux.scala:30:73]
wire [3:0] schedule_dir_bits_way; // @[Mux.scala:30:73]
wire schedule_dir_valid; // @[Mux.scala:30:73]
wire schedule_reload; // @[Mux.scala:30:73]
wire _schedule_T_12 = _schedule_T & _mshrs_0_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_13 = _schedule_T_1 & _mshrs_1_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_14 = _schedule_T_2 & _mshrs_2_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_15 = _schedule_T_3 & _mshrs_3_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_16 = _schedule_T_4 & _mshrs_4_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_17 = _schedule_T_5 & _mshrs_5_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_18 = _schedule_T_6 & _mshrs_6_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_19 = _schedule_T_7 & _mshrs_7_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_20 = _schedule_T_8 & _mshrs_8_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_21 = _schedule_T_9 & _mshrs_9_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_22 = _schedule_T_10 & _mshrs_10_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_23 = _schedule_T_11 & _mshrs_11_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_24 = _schedule_T_12 | _schedule_T_13; // @[Mux.scala:30:73]
wire _schedule_T_25 = _schedule_T_24 | _schedule_T_14; // @[Mux.scala:30:73]
wire _schedule_T_26 = _schedule_T_25 | _schedule_T_15; // @[Mux.scala:30:73]
wire _schedule_T_27 = _schedule_T_26 | _schedule_T_16; // @[Mux.scala:30:73]
wire _schedule_T_28 = _schedule_T_27 | _schedule_T_17; // @[Mux.scala:30:73]
wire _schedule_T_29 = _schedule_T_28 | _schedule_T_18; // @[Mux.scala:30:73]
wire _schedule_T_30 = _schedule_T_29 | _schedule_T_19; // @[Mux.scala:30:73]
wire _schedule_T_31 = _schedule_T_30 | _schedule_T_20; // @[Mux.scala:30:73]
wire _schedule_T_32 = _schedule_T_31 | _schedule_T_21; // @[Mux.scala:30:73]
wire _schedule_T_33 = _schedule_T_32 | _schedule_T_22; // @[Mux.scala:30:73]
wire _schedule_T_34 = _schedule_T_33 | _schedule_T_23; // @[Mux.scala:30:73]
assign _schedule_WIRE = _schedule_T_34; // @[Mux.scala:30:73]
assign schedule_reload = _schedule_WIRE; // @[Mux.scala:30:73]
wire _schedule_WIRE_10; // @[Mux.scala:30:73]
assign schedule_dir_valid = _schedule_WIRE_1_valid; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_2_set; // @[Mux.scala:30:73]
assign schedule_dir_bits_set = _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_2_way; // @[Mux.scala:30:73]
assign schedule_dir_bits_way = _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_dirty = _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_2_data_state; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_state = _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_clients = _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_tag = _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_9; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_set = _schedule_WIRE_2_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_8; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_way = _schedule_WIRE_2_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_3_dirty; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_dirty = _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_3_state; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_state = _schedule_WIRE_2_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_3_clients; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_clients = _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_3_tag; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_tag = _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73]
wire _schedule_WIRE_7; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_dirty = _schedule_WIRE_3_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_6; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_state = _schedule_WIRE_3_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_5; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_clients = _schedule_WIRE_3_clients; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_4; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_tag = _schedule_WIRE_3_tag; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_35 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_36 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_37 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_38 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_39 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_40 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_41 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_42 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_43 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_44 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_45 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_46 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_47 = _schedule_T_35 | _schedule_T_36; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_48 = _schedule_T_47 | _schedule_T_37; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_49 = _schedule_T_48 | _schedule_T_38; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_50 = _schedule_T_49 | _schedule_T_39; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_51 = _schedule_T_50 | _schedule_T_40; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_52 = _schedule_T_51 | _schedule_T_41; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_53 = _schedule_T_52 | _schedule_T_42; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_54 = _schedule_T_53 | _schedule_T_43; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_55 = _schedule_T_54 | _schedule_T_44; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_56 = _schedule_T_55 | _schedule_T_45; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_57 = _schedule_T_56 | _schedule_T_46; // @[Mux.scala:30:73]
assign _schedule_WIRE_4 = _schedule_T_57; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_tag = _schedule_WIRE_4; // @[Mux.scala:30:73]
wire _schedule_T_58 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_59 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_60 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_61 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_62 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_63 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_64 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_65 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_66 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_67 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_68 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_69 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_70 = _schedule_T_58 | _schedule_T_59; // @[Mux.scala:30:73]
wire _schedule_T_71 = _schedule_T_70 | _schedule_T_60; // @[Mux.scala:30:73]
wire _schedule_T_72 = _schedule_T_71 | _schedule_T_61; // @[Mux.scala:30:73]
wire _schedule_T_73 = _schedule_T_72 | _schedule_T_62; // @[Mux.scala:30:73]
wire _schedule_T_74 = _schedule_T_73 | _schedule_T_63; // @[Mux.scala:30:73]
wire _schedule_T_75 = _schedule_T_74 | _schedule_T_64; // @[Mux.scala:30:73]
wire _schedule_T_76 = _schedule_T_75 | _schedule_T_65; // @[Mux.scala:30:73]
wire _schedule_T_77 = _schedule_T_76 | _schedule_T_66; // @[Mux.scala:30:73]
wire _schedule_T_78 = _schedule_T_77 | _schedule_T_67; // @[Mux.scala:30:73]
wire _schedule_T_79 = _schedule_T_78 | _schedule_T_68; // @[Mux.scala:30:73]
wire _schedule_T_80 = _schedule_T_79 | _schedule_T_69; // @[Mux.scala:30:73]
assign _schedule_WIRE_5 = _schedule_T_80; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_clients = _schedule_WIRE_5; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_81 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_82 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_83 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_84 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_85 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_86 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_87 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_88 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_89 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_90 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_91 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_92 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_93 = _schedule_T_81 | _schedule_T_82; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_94 = _schedule_T_93 | _schedule_T_83; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_95 = _schedule_T_94 | _schedule_T_84; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_96 = _schedule_T_95 | _schedule_T_85; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_97 = _schedule_T_96 | _schedule_T_86; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_98 = _schedule_T_97 | _schedule_T_87; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_99 = _schedule_T_98 | _schedule_T_88; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_100 = _schedule_T_99 | _schedule_T_89; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_101 = _schedule_T_100 | _schedule_T_90; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_102 = _schedule_T_101 | _schedule_T_91; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_103 = _schedule_T_102 | _schedule_T_92; // @[Mux.scala:30:73]
assign _schedule_WIRE_6 = _schedule_T_103; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_state = _schedule_WIRE_6; // @[Mux.scala:30:73]
wire _schedule_T_104 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_105 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_106 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_107 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_108 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_109 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_110 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_111 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_112 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_113 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_114 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_115 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_116 = _schedule_T_104 | _schedule_T_105; // @[Mux.scala:30:73]
wire _schedule_T_117 = _schedule_T_116 | _schedule_T_106; // @[Mux.scala:30:73]
wire _schedule_T_118 = _schedule_T_117 | _schedule_T_107; // @[Mux.scala:30:73]
wire _schedule_T_119 = _schedule_T_118 | _schedule_T_108; // @[Mux.scala:30:73]
wire _schedule_T_120 = _schedule_T_119 | _schedule_T_109; // @[Mux.scala:30:73]
wire _schedule_T_121 = _schedule_T_120 | _schedule_T_110; // @[Mux.scala:30:73]
wire _schedule_T_122 = _schedule_T_121 | _schedule_T_111; // @[Mux.scala:30:73]
wire _schedule_T_123 = _schedule_T_122 | _schedule_T_112; // @[Mux.scala:30:73]
wire _schedule_T_124 = _schedule_T_123 | _schedule_T_113; // @[Mux.scala:30:73]
wire _schedule_T_125 = _schedule_T_124 | _schedule_T_114; // @[Mux.scala:30:73]
wire _schedule_T_126 = _schedule_T_125 | _schedule_T_115; // @[Mux.scala:30:73]
assign _schedule_WIRE_7 = _schedule_T_126; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_dirty = _schedule_WIRE_7; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_127 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_128 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_129 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_130 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_131 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_132 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_133 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_134 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_135 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_136 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_137 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_138 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_139 = _schedule_T_127 | _schedule_T_128; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_140 = _schedule_T_139 | _schedule_T_129; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_141 = _schedule_T_140 | _schedule_T_130; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_142 = _schedule_T_141 | _schedule_T_131; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_143 = _schedule_T_142 | _schedule_T_132; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_144 = _schedule_T_143 | _schedule_T_133; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_145 = _schedule_T_144 | _schedule_T_134; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_146 = _schedule_T_145 | _schedule_T_135; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_147 = _schedule_T_146 | _schedule_T_136; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_148 = _schedule_T_147 | _schedule_T_137; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_149 = _schedule_T_148 | _schedule_T_138; // @[Mux.scala:30:73]
assign _schedule_WIRE_8 = _schedule_T_149; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_way = _schedule_WIRE_8; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_150 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_151 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_152 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_153 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_154 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_155 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_156 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_157 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_158 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_159 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_160 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_161 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_162 = _schedule_T_150 | _schedule_T_151; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_163 = _schedule_T_162 | _schedule_T_152; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_164 = _schedule_T_163 | _schedule_T_153; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_165 = _schedule_T_164 | _schedule_T_154; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_166 = _schedule_T_165 | _schedule_T_155; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_167 = _schedule_T_166 | _schedule_T_156; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_168 = _schedule_T_167 | _schedule_T_157; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_169 = _schedule_T_168 | _schedule_T_158; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_170 = _schedule_T_169 | _schedule_T_159; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_171 = _schedule_T_170 | _schedule_T_160; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_172 = _schedule_T_171 | _schedule_T_161; // @[Mux.scala:30:73]
assign _schedule_WIRE_9 = _schedule_T_172; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_set = _schedule_WIRE_9; // @[Mux.scala:30:73]
wire _schedule_T_173 = _schedule_T & _mshrs_0_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_174 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_175 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_176 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_177 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_178 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_179 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_180 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_181 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_182 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_183 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_184 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_185 = _schedule_T_173 | _schedule_T_174; // @[Mux.scala:30:73]
wire _schedule_T_186 = _schedule_T_185 | _schedule_T_175; // @[Mux.scala:30:73]
wire _schedule_T_187 = _schedule_T_186 | _schedule_T_176; // @[Mux.scala:30:73]
wire _schedule_T_188 = _schedule_T_187 | _schedule_T_177; // @[Mux.scala:30:73]
wire _schedule_T_189 = _schedule_T_188 | _schedule_T_178; // @[Mux.scala:30:73]
wire _schedule_T_190 = _schedule_T_189 | _schedule_T_179; // @[Mux.scala:30:73]
wire _schedule_T_191 = _schedule_T_190 | _schedule_T_180; // @[Mux.scala:30:73]
wire _schedule_T_192 = _schedule_T_191 | _schedule_T_181; // @[Mux.scala:30:73]
wire _schedule_T_193 = _schedule_T_192 | _schedule_T_182; // @[Mux.scala:30:73]
wire _schedule_T_194 = _schedule_T_193 | _schedule_T_183; // @[Mux.scala:30:73]
wire _schedule_T_195 = _schedule_T_194 | _schedule_T_184; // @[Mux.scala:30:73]
assign _schedule_WIRE_10 = _schedule_T_195; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_valid = _schedule_WIRE_10; // @[Mux.scala:30:73]
wire _schedule_WIRE_14; // @[Mux.scala:30:73]
assign schedule_x_valid = _schedule_WIRE_11_valid; // @[Mux.scala:30:73]
wire _schedule_T_219 = _schedule_T & _mshrs_0_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_220 = _schedule_T_1 & _mshrs_1_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_221 = _schedule_T_2 & _mshrs_2_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_222 = _schedule_T_3 & _mshrs_3_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_223 = _schedule_T_4 & _mshrs_4_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_224 = _schedule_T_5 & _mshrs_5_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_225 = _schedule_T_6 & _mshrs_6_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_226 = _schedule_T_7 & _mshrs_7_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_227 = _schedule_T_8 & _mshrs_8_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_228 = _schedule_T_9 & _mshrs_9_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_229 = _schedule_T_10 & _mshrs_10_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_230 = _schedule_T_11 & _mshrs_11_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_231 = _schedule_T_219 | _schedule_T_220; // @[Mux.scala:30:73]
wire _schedule_T_232 = _schedule_T_231 | _schedule_T_221; // @[Mux.scala:30:73]
wire _schedule_T_233 = _schedule_T_232 | _schedule_T_222; // @[Mux.scala:30:73]
wire _schedule_T_234 = _schedule_T_233 | _schedule_T_223; // @[Mux.scala:30:73]
wire _schedule_T_235 = _schedule_T_234 | _schedule_T_224; // @[Mux.scala:30:73]
wire _schedule_T_236 = _schedule_T_235 | _schedule_T_225; // @[Mux.scala:30:73]
wire _schedule_T_237 = _schedule_T_236 | _schedule_T_226; // @[Mux.scala:30:73]
wire _schedule_T_238 = _schedule_T_237 | _schedule_T_227; // @[Mux.scala:30:73]
wire _schedule_T_239 = _schedule_T_238 | _schedule_T_228; // @[Mux.scala:30:73]
wire _schedule_T_240 = _schedule_T_239 | _schedule_T_229; // @[Mux.scala:30:73]
wire _schedule_T_241 = _schedule_T_240 | _schedule_T_230; // @[Mux.scala:30:73]
assign _schedule_WIRE_14 = _schedule_T_241; // @[Mux.scala:30:73]
assign _schedule_WIRE_11_valid = _schedule_WIRE_14; // @[Mux.scala:30:73]
wire _schedule_WIRE_18; // @[Mux.scala:30:73]
assign schedule_e_valid = _schedule_WIRE_15_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_16_sink; // @[Mux.scala:30:73]
assign schedule_e_bits_sink = _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_17; // @[Mux.scala:30:73]
assign _schedule_WIRE_15_bits_sink = _schedule_WIRE_16_sink; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_242 = _schedule_T ? _mshrs_0_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_243 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_244 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_245 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_246 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_247 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_248 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_249 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_250 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_251 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_252 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_253 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_254 = _schedule_T_242 | _schedule_T_243; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_255 = _schedule_T_254 | _schedule_T_244; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_256 = _schedule_T_255 | _schedule_T_245; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_257 = _schedule_T_256 | _schedule_T_246; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_258 = _schedule_T_257 | _schedule_T_247; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_259 = _schedule_T_258 | _schedule_T_248; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_260 = _schedule_T_259 | _schedule_T_249; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_261 = _schedule_T_260 | _schedule_T_250; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_262 = _schedule_T_261 | _schedule_T_251; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_263 = _schedule_T_262 | _schedule_T_252; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_264 = _schedule_T_263 | _schedule_T_253; // @[Mux.scala:30:73]
assign _schedule_WIRE_17 = _schedule_T_264; // @[Mux.scala:30:73]
assign _schedule_WIRE_16_sink = _schedule_WIRE_17; // @[Mux.scala:30:73]
wire _schedule_T_265 = _schedule_T & _mshrs_0_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_266 = _schedule_T_1 & _mshrs_1_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_267 = _schedule_T_2 & _mshrs_2_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_268 = _schedule_T_3 & _mshrs_3_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_269 = _schedule_T_4 & _mshrs_4_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_270 = _schedule_T_5 & _mshrs_5_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_271 = _schedule_T_6 & _mshrs_6_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_272 = _schedule_T_7 & _mshrs_7_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_273 = _schedule_T_8 & _mshrs_8_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_274 = _schedule_T_9 & _mshrs_9_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_275 = _schedule_T_10 & _mshrs_10_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_276 = _schedule_T_11 & _mshrs_11_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_277 = _schedule_T_265 | _schedule_T_266; // @[Mux.scala:30:73]
wire _schedule_T_278 = _schedule_T_277 | _schedule_T_267; // @[Mux.scala:30:73]
wire _schedule_T_279 = _schedule_T_278 | _schedule_T_268; // @[Mux.scala:30:73]
wire _schedule_T_280 = _schedule_T_279 | _schedule_T_269; // @[Mux.scala:30:73]
wire _schedule_T_281 = _schedule_T_280 | _schedule_T_270; // @[Mux.scala:30:73]
wire _schedule_T_282 = _schedule_T_281 | _schedule_T_271; // @[Mux.scala:30:73]
wire _schedule_T_283 = _schedule_T_282 | _schedule_T_272; // @[Mux.scala:30:73]
wire _schedule_T_284 = _schedule_T_283 | _schedule_T_273; // @[Mux.scala:30:73]
wire _schedule_T_285 = _schedule_T_284 | _schedule_T_274; // @[Mux.scala:30:73]
wire _schedule_T_286 = _schedule_T_285 | _schedule_T_275; // @[Mux.scala:30:73]
wire _schedule_T_287 = _schedule_T_286 | _schedule_T_276; // @[Mux.scala:30:73]
assign _schedule_WIRE_18 = _schedule_T_287; // @[Mux.scala:30:73]
assign _schedule_WIRE_15_valid = _schedule_WIRE_18; // @[Mux.scala:30:73]
wire _schedule_WIRE_37; // @[Mux.scala:30:73]
assign schedule_d_valid = _schedule_WIRE_19_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_0 = _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_1 = _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_2 = _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_control; // @[Mux.scala:30:73]
assign schedule_d_bits_control = _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_opcode; // @[Mux.scala:30:73]
assign schedule_d_bits_opcode = _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_param; // @[Mux.scala:30:73]
assign schedule_d_bits_param = _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_size; // @[Mux.scala:30:73]
assign schedule_d_bits_size = _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_20_source; // @[Mux.scala:30:73]
assign schedule_d_bits_source = _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_20_tag; // @[Mux.scala:30:73]
assign schedule_d_bits_tag = _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_20_offset; // @[Mux.scala:30:73]
assign schedule_d_bits_offset = _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_20_put; // @[Mux.scala:30:73]
assign schedule_d_bits_put = _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_20_set; // @[Mux.scala:30:73]
assign schedule_d_bits_set = _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_20_way; // @[Mux.scala:30:73]
assign schedule_d_bits_way = _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_bad; // @[Mux.scala:30:73]
assign schedule_d_bits_bad = _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_0; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_0 = _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_1; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_1 = _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_2; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_2 = _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_32; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_control = _schedule_WIRE_20_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_31; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_opcode = _schedule_WIRE_20_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_30; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_param = _schedule_WIRE_20_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_29; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_size = _schedule_WIRE_20_size; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_28; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_source = _schedule_WIRE_20_source; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_27; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_tag = _schedule_WIRE_20_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_26; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_offset = _schedule_WIRE_20_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_25; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_put = _schedule_WIRE_20_put; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_24; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_set = _schedule_WIRE_20_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_22; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_way = _schedule_WIRE_20_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_21; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_bad = _schedule_WIRE_20_bad; // @[Mux.scala:30:73]
wire _schedule_T_288 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_289 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_290 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_291 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_292 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_293 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_294 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_295 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_296 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_297 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_298 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_299 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_300 = _schedule_T_288 | _schedule_T_289; // @[Mux.scala:30:73]
wire _schedule_T_301 = _schedule_T_300 | _schedule_T_290; // @[Mux.scala:30:73]
wire _schedule_T_302 = _schedule_T_301 | _schedule_T_291; // @[Mux.scala:30:73]
wire _schedule_T_303 = _schedule_T_302 | _schedule_T_292; // @[Mux.scala:30:73]
wire _schedule_T_304 = _schedule_T_303 | _schedule_T_293; // @[Mux.scala:30:73]
wire _schedule_T_305 = _schedule_T_304 | _schedule_T_294; // @[Mux.scala:30:73]
wire _schedule_T_306 = _schedule_T_305 | _schedule_T_295; // @[Mux.scala:30:73]
wire _schedule_T_307 = _schedule_T_306 | _schedule_T_296; // @[Mux.scala:30:73]
wire _schedule_T_308 = _schedule_T_307 | _schedule_T_297; // @[Mux.scala:30:73]
wire _schedule_T_309 = _schedule_T_308 | _schedule_T_298; // @[Mux.scala:30:73]
wire _schedule_T_310 = _schedule_T_309 | _schedule_T_299; // @[Mux.scala:30:73]
assign _schedule_WIRE_21 = _schedule_T_310; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_bad = _schedule_WIRE_21; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_311 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_312 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_313 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_314 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_315 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_316 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_317 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_318 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_319 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_320 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_321 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_322 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_323 = _schedule_T_311 | _schedule_T_312; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_324 = _schedule_T_323 | _schedule_T_313; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_325 = _schedule_T_324 | _schedule_T_314; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_326 = _schedule_T_325 | _schedule_T_315; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_327 = _schedule_T_326 | _schedule_T_316; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_328 = _schedule_T_327 | _schedule_T_317; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_329 = _schedule_T_328 | _schedule_T_318; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_330 = _schedule_T_329 | _schedule_T_319; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_331 = _schedule_T_330 | _schedule_T_320; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_332 = _schedule_T_331 | _schedule_T_321; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_333 = _schedule_T_332 | _schedule_T_322; // @[Mux.scala:30:73]
assign _schedule_WIRE_22 = _schedule_T_333; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_way = _schedule_WIRE_22; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_357 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_358 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_359 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_360 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_361 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_362 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_363 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_364 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_365 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_366 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_367 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_368 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_369 = _schedule_T_357 | _schedule_T_358; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_370 = _schedule_T_369 | _schedule_T_359; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_371 = _schedule_T_370 | _schedule_T_360; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_372 = _schedule_T_371 | _schedule_T_361; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_373 = _schedule_T_372 | _schedule_T_362; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_374 = _schedule_T_373 | _schedule_T_363; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_375 = _schedule_T_374 | _schedule_T_364; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_376 = _schedule_T_375 | _schedule_T_365; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_377 = _schedule_T_376 | _schedule_T_366; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_378 = _schedule_T_377 | _schedule_T_367; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_379 = _schedule_T_378 | _schedule_T_368; // @[Mux.scala:30:73]
assign _schedule_WIRE_24 = _schedule_T_379; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_set = _schedule_WIRE_24; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_380 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_381 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_382 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_383 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_384 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_385 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_386 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_387 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_388 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_389 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_390 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_391 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_392 = _schedule_T_380 | _schedule_T_381; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_393 = _schedule_T_392 | _schedule_T_382; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_394 = _schedule_T_393 | _schedule_T_383; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_395 = _schedule_T_394 | _schedule_T_384; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_396 = _schedule_T_395 | _schedule_T_385; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_397 = _schedule_T_396 | _schedule_T_386; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_398 = _schedule_T_397 | _schedule_T_387; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_399 = _schedule_T_398 | _schedule_T_388; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_400 = _schedule_T_399 | _schedule_T_389; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_401 = _schedule_T_400 | _schedule_T_390; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_402 = _schedule_T_401 | _schedule_T_391; // @[Mux.scala:30:73]
assign _schedule_WIRE_25 = _schedule_T_402; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_put = _schedule_WIRE_25; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_403 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_404 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_405 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_406 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_407 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_408 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_409 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_410 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_411 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_412 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_413 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_414 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_415 = _schedule_T_403 | _schedule_T_404; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_416 = _schedule_T_415 | _schedule_T_405; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_417 = _schedule_T_416 | _schedule_T_406; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_418 = _schedule_T_417 | _schedule_T_407; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_419 = _schedule_T_418 | _schedule_T_408; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_420 = _schedule_T_419 | _schedule_T_409; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_421 = _schedule_T_420 | _schedule_T_410; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_422 = _schedule_T_421 | _schedule_T_411; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_423 = _schedule_T_422 | _schedule_T_412; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_424 = _schedule_T_423 | _schedule_T_413; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_425 = _schedule_T_424 | _schedule_T_414; // @[Mux.scala:30:73]
assign _schedule_WIRE_26 = _schedule_T_425; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_offset = _schedule_WIRE_26; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_426 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_427 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_428 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_429 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_430 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_431 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_432 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_433 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_434 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_435 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_436 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_437 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_438 = _schedule_T_426 | _schedule_T_427; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_439 = _schedule_T_438 | _schedule_T_428; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_440 = _schedule_T_439 | _schedule_T_429; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_441 = _schedule_T_440 | _schedule_T_430; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_442 = _schedule_T_441 | _schedule_T_431; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_443 = _schedule_T_442 | _schedule_T_432; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_444 = _schedule_T_443 | _schedule_T_433; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_445 = _schedule_T_444 | _schedule_T_434; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_446 = _schedule_T_445 | _schedule_T_435; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_447 = _schedule_T_446 | _schedule_T_436; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_448 = _schedule_T_447 | _schedule_T_437; // @[Mux.scala:30:73]
assign _schedule_WIRE_27 = _schedule_T_448; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_tag = _schedule_WIRE_27; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_449 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_450 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_451 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_452 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_453 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_454 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_455 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_456 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_457 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_458 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_459 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_460 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_461 = _schedule_T_449 | _schedule_T_450; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_462 = _schedule_T_461 | _schedule_T_451; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_463 = _schedule_T_462 | _schedule_T_452; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_464 = _schedule_T_463 | _schedule_T_453; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_465 = _schedule_T_464 | _schedule_T_454; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_466 = _schedule_T_465 | _schedule_T_455; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_467 = _schedule_T_466 | _schedule_T_456; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_468 = _schedule_T_467 | _schedule_T_457; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_469 = _schedule_T_468 | _schedule_T_458; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_470 = _schedule_T_469 | _schedule_T_459; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_471 = _schedule_T_470 | _schedule_T_460; // @[Mux.scala:30:73]
assign _schedule_WIRE_28 = _schedule_T_471; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_source = _schedule_WIRE_28; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_472 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_473 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_474 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_475 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_476 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_477 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_478 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_479 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_480 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_481 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_482 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_483 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_484 = _schedule_T_472 | _schedule_T_473; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_485 = _schedule_T_484 | _schedule_T_474; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_486 = _schedule_T_485 | _schedule_T_475; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_487 = _schedule_T_486 | _schedule_T_476; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_488 = _schedule_T_487 | _schedule_T_477; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_489 = _schedule_T_488 | _schedule_T_478; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_490 = _schedule_T_489 | _schedule_T_479; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_491 = _schedule_T_490 | _schedule_T_480; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_492 = _schedule_T_491 | _schedule_T_481; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_493 = _schedule_T_492 | _schedule_T_482; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_494 = _schedule_T_493 | _schedule_T_483; // @[Mux.scala:30:73]
assign _schedule_WIRE_29 = _schedule_T_494; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_size = _schedule_WIRE_29; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_495 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_496 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_497 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_498 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_499 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_500 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_501 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_502 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_503 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_504 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_505 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_506 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_507 = _schedule_T_495 | _schedule_T_496; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_508 = _schedule_T_507 | _schedule_T_497; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_509 = _schedule_T_508 | _schedule_T_498; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_510 = _schedule_T_509 | _schedule_T_499; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_511 = _schedule_T_510 | _schedule_T_500; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_512 = _schedule_T_511 | _schedule_T_501; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_513 = _schedule_T_512 | _schedule_T_502; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_514 = _schedule_T_513 | _schedule_T_503; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_515 = _schedule_T_514 | _schedule_T_504; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_516 = _schedule_T_515 | _schedule_T_505; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_517 = _schedule_T_516 | _schedule_T_506; // @[Mux.scala:30:73]
assign _schedule_WIRE_30 = _schedule_T_517; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_param = _schedule_WIRE_30; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_518 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_519 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_520 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_521 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_522 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_523 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_524 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_525 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_526 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_527 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_528 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_529 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_530 = _schedule_T_518 | _schedule_T_519; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_531 = _schedule_T_530 | _schedule_T_520; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_532 = _schedule_T_531 | _schedule_T_521; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_533 = _schedule_T_532 | _schedule_T_522; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_534 = _schedule_T_533 | _schedule_T_523; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_535 = _schedule_T_534 | _schedule_T_524; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_536 = _schedule_T_535 | _schedule_T_525; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_537 = _schedule_T_536 | _schedule_T_526; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_538 = _schedule_T_537 | _schedule_T_527; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_539 = _schedule_T_538 | _schedule_T_528; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_540 = _schedule_T_539 | _schedule_T_529; // @[Mux.scala:30:73]
assign _schedule_WIRE_31 = _schedule_T_540; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_opcode = _schedule_WIRE_31; // @[Mux.scala:30:73]
wire _schedule_T_541 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_542 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_543 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_544 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_545 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_546 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_547 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_548 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_549 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_550 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_551 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_552 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_553 = _schedule_T_541 | _schedule_T_542; // @[Mux.scala:30:73]
wire _schedule_T_554 = _schedule_T_553 | _schedule_T_543; // @[Mux.scala:30:73]
wire _schedule_T_555 = _schedule_T_554 | _schedule_T_544; // @[Mux.scala:30:73]
wire _schedule_T_556 = _schedule_T_555 | _schedule_T_545; // @[Mux.scala:30:73]
wire _schedule_T_557 = _schedule_T_556 | _schedule_T_546; // @[Mux.scala:30:73]
wire _schedule_T_558 = _schedule_T_557 | _schedule_T_547; // @[Mux.scala:30:73]
wire _schedule_T_559 = _schedule_T_558 | _schedule_T_548; // @[Mux.scala:30:73]
wire _schedule_T_560 = _schedule_T_559 | _schedule_T_549; // @[Mux.scala:30:73]
wire _schedule_T_561 = _schedule_T_560 | _schedule_T_550; // @[Mux.scala:30:73]
wire _schedule_T_562 = _schedule_T_561 | _schedule_T_551; // @[Mux.scala:30:73]
wire _schedule_T_563 = _schedule_T_562 | _schedule_T_552; // @[Mux.scala:30:73]
assign _schedule_WIRE_32 = _schedule_T_563; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_control = _schedule_WIRE_32; // @[Mux.scala:30:73]
wire _schedule_WIRE_34; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_0 = _schedule_WIRE_33_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_35; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_1 = _schedule_WIRE_33_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_36; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_2 = _schedule_WIRE_33_2; // @[Mux.scala:30:73]
wire _schedule_T_564 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_565 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_566 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_567 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_568 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_569 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_570 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_571 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_572 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_573 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_576 = _schedule_T_564 | _schedule_T_565; // @[Mux.scala:30:73]
wire _schedule_T_577 = _schedule_T_576 | _schedule_T_566; // @[Mux.scala:30:73]
wire _schedule_T_578 = _schedule_T_577 | _schedule_T_567; // @[Mux.scala:30:73]
wire _schedule_T_579 = _schedule_T_578 | _schedule_T_568; // @[Mux.scala:30:73]
wire _schedule_T_580 = _schedule_T_579 | _schedule_T_569; // @[Mux.scala:30:73]
wire _schedule_T_581 = _schedule_T_580 | _schedule_T_570; // @[Mux.scala:30:73]
wire _schedule_T_582 = _schedule_T_581 | _schedule_T_571; // @[Mux.scala:30:73]
wire _schedule_T_583 = _schedule_T_582 | _schedule_T_572; // @[Mux.scala:30:73]
wire _schedule_T_584 = _schedule_T_583 | _schedule_T_573; // @[Mux.scala:30:73]
wire _schedule_T_585 = _schedule_T_584; // @[Mux.scala:30:73]
wire _schedule_T_586 = _schedule_T_585; // @[Mux.scala:30:73]
assign _schedule_WIRE_34 = _schedule_T_586; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_0 = _schedule_WIRE_34; // @[Mux.scala:30:73]
wire _schedule_T_587 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_588 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_589 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_590 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_591 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_592 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_593 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_594 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_595 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_596 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_597 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_599 = _schedule_T_587 | _schedule_T_588; // @[Mux.scala:30:73]
wire _schedule_T_600 = _schedule_T_599 | _schedule_T_589; // @[Mux.scala:30:73]
wire _schedule_T_601 = _schedule_T_600 | _schedule_T_590; // @[Mux.scala:30:73]
wire _schedule_T_602 = _schedule_T_601 | _schedule_T_591; // @[Mux.scala:30:73]
wire _schedule_T_603 = _schedule_T_602 | _schedule_T_592; // @[Mux.scala:30:73]
wire _schedule_T_604 = _schedule_T_603 | _schedule_T_593; // @[Mux.scala:30:73]
wire _schedule_T_605 = _schedule_T_604 | _schedule_T_594; // @[Mux.scala:30:73]
wire _schedule_T_606 = _schedule_T_605 | _schedule_T_595; // @[Mux.scala:30:73]
wire _schedule_T_607 = _schedule_T_606 | _schedule_T_596; // @[Mux.scala:30:73]
wire _schedule_T_608 = _schedule_T_607 | _schedule_T_597; // @[Mux.scala:30:73]
wire _schedule_T_609 = _schedule_T_608; // @[Mux.scala:30:73]
assign _schedule_WIRE_35 = _schedule_T_609; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_1 = _schedule_WIRE_35; // @[Mux.scala:30:73]
wire _schedule_T_610 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_611 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_612 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_613 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_614 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_615 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_616 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_617 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_618 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_619 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_620 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_621 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_622 = _schedule_T_610 | _schedule_T_611; // @[Mux.scala:30:73]
wire _schedule_T_623 = _schedule_T_622 | _schedule_T_612; // @[Mux.scala:30:73]
wire _schedule_T_624 = _schedule_T_623 | _schedule_T_613; // @[Mux.scala:30:73]
wire _schedule_T_625 = _schedule_T_624 | _schedule_T_614; // @[Mux.scala:30:73]
wire _schedule_T_626 = _schedule_T_625 | _schedule_T_615; // @[Mux.scala:30:73]
wire _schedule_T_627 = _schedule_T_626 | _schedule_T_616; // @[Mux.scala:30:73]
wire _schedule_T_628 = _schedule_T_627 | _schedule_T_617; // @[Mux.scala:30:73]
wire _schedule_T_629 = _schedule_T_628 | _schedule_T_618; // @[Mux.scala:30:73]
wire _schedule_T_630 = _schedule_T_629 | _schedule_T_619; // @[Mux.scala:30:73]
wire _schedule_T_631 = _schedule_T_630 | _schedule_T_620; // @[Mux.scala:30:73]
wire _schedule_T_632 = _schedule_T_631 | _schedule_T_621; // @[Mux.scala:30:73]
assign _schedule_WIRE_36 = _schedule_T_632; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_2 = _schedule_WIRE_36; // @[Mux.scala:30:73]
wire _schedule_T_633 = _schedule_T & _mshrs_0_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_634 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_635 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_636 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_637 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_638 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_639 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_640 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_641 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_642 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_643 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_644 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_645 = _schedule_T_633 | _schedule_T_634; // @[Mux.scala:30:73]
wire _schedule_T_646 = _schedule_T_645 | _schedule_T_635; // @[Mux.scala:30:73]
wire _schedule_T_647 = _schedule_T_646 | _schedule_T_636; // @[Mux.scala:30:73]
wire _schedule_T_648 = _schedule_T_647 | _schedule_T_637; // @[Mux.scala:30:73]
wire _schedule_T_649 = _schedule_T_648 | _schedule_T_638; // @[Mux.scala:30:73]
wire _schedule_T_650 = _schedule_T_649 | _schedule_T_639; // @[Mux.scala:30:73]
wire _schedule_T_651 = _schedule_T_650 | _schedule_T_640; // @[Mux.scala:30:73]
wire _schedule_T_652 = _schedule_T_651 | _schedule_T_641; // @[Mux.scala:30:73]
wire _schedule_T_653 = _schedule_T_652 | _schedule_T_642; // @[Mux.scala:30:73]
wire _schedule_T_654 = _schedule_T_653 | _schedule_T_643; // @[Mux.scala:30:73]
wire _schedule_T_655 = _schedule_T_654 | _schedule_T_644; // @[Mux.scala:30:73]
assign _schedule_WIRE_37 = _schedule_T_655; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_valid = _schedule_WIRE_37; // @[Mux.scala:30:73]
wire _schedule_WIRE_47; // @[Mux.scala:30:73]
assign schedule_c_valid = _schedule_WIRE_38_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_39_opcode; // @[Mux.scala:30:73]
assign schedule_c_bits_opcode = _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_39_param; // @[Mux.scala:30:73]
assign schedule_c_bits_param = _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_39_tag; // @[Mux.scala:30:73]
assign schedule_c_bits_tag = _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_39_set; // @[Mux.scala:30:73]
assign schedule_c_bits_set = _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_39_way; // @[Mux.scala:30:73]
assign schedule_c_bits_way = _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_39_dirty; // @[Mux.scala:30:73]
assign schedule_c_bits_dirty = _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_46; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_opcode = _schedule_WIRE_39_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_45; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_param = _schedule_WIRE_39_param; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_43; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_tag = _schedule_WIRE_39_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_42; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_set = _schedule_WIRE_39_set; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_41; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_way = _schedule_WIRE_39_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_40; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_dirty = _schedule_WIRE_39_dirty; // @[Mux.scala:30:73]
wire _schedule_T_656 = _schedule_T & _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_657 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_658 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_659 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_660 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_661 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_662 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_663 = _schedule_T_7 & _mshrs_7_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_664 = _schedule_T_8 & _mshrs_8_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_665 = _schedule_T_9 & _mshrs_9_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_666 = _schedule_T_10 & _mshrs_10_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_667 = _schedule_T_11 & _mshrs_11_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_668 = _schedule_T_656 | _schedule_T_657; // @[Mux.scala:30:73]
wire _schedule_T_669 = _schedule_T_668 | _schedule_T_658; // @[Mux.scala:30:73]
wire _schedule_T_670 = _schedule_T_669 | _schedule_T_659; // @[Mux.scala:30:73]
wire _schedule_T_671 = _schedule_T_670 | _schedule_T_660; // @[Mux.scala:30:73]
wire _schedule_T_672 = _schedule_T_671 | _schedule_T_661; // @[Mux.scala:30:73]
wire _schedule_T_673 = _schedule_T_672 | _schedule_T_662; // @[Mux.scala:30:73]
wire _schedule_T_674 = _schedule_T_673 | _schedule_T_663; // @[Mux.scala:30:73]
wire _schedule_T_675 = _schedule_T_674 | _schedule_T_664; // @[Mux.scala:30:73]
wire _schedule_T_676 = _schedule_T_675 | _schedule_T_665; // @[Mux.scala:30:73]
wire _schedule_T_677 = _schedule_T_676 | _schedule_T_666; // @[Mux.scala:30:73]
wire _schedule_T_678 = _schedule_T_677 | _schedule_T_667; // @[Mux.scala:30:73]
assign _schedule_WIRE_40 = _schedule_T_678; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_dirty = _schedule_WIRE_40; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_679 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_680 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_681 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_682 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_683 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_684 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_685 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_686 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_687 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_688 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_689 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_690 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36]
wire [3:0] _schedule_T_691 = _schedule_T_679 | _schedule_T_680; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_692 = _schedule_T_691 | _schedule_T_681; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_693 = _schedule_T_692 | _schedule_T_682; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_694 = _schedule_T_693 | _schedule_T_683; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_695 = _schedule_T_694 | _schedule_T_684; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_696 = _schedule_T_695 | _schedule_T_685; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_697 = _schedule_T_696 | _schedule_T_686; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_698 = _schedule_T_697 | _schedule_T_687; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_699 = _schedule_T_698 | _schedule_T_688; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_700 = _schedule_T_699 | _schedule_T_689; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_701 = _schedule_T_700 | _schedule_T_690; // @[Mux.scala:30:73]
assign _schedule_WIRE_41 = _schedule_T_701; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_way = _schedule_WIRE_41; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_702 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_703 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_704 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_705 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_706 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_707 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_708 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_709 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_710 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_711 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_712 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_713 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_714 = _schedule_T_702 | _schedule_T_703; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_715 = _schedule_T_714 | _schedule_T_704; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_716 = _schedule_T_715 | _schedule_T_705; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_717 = _schedule_T_716 | _schedule_T_706; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_718 = _schedule_T_717 | _schedule_T_707; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_719 = _schedule_T_718 | _schedule_T_708; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_720 = _schedule_T_719 | _schedule_T_709; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_721 = _schedule_T_720 | _schedule_T_710; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_722 = _schedule_T_721 | _schedule_T_711; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_723 = _schedule_T_722 | _schedule_T_712; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_724 = _schedule_T_723 | _schedule_T_713; // @[Mux.scala:30:73]
assign _schedule_WIRE_42 = _schedule_T_724; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_set = _schedule_WIRE_42; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_725 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_726 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_727 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_728 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_729 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_730 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_731 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_732 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_733 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_734 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_735 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_736 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_737 = _schedule_T_725 | _schedule_T_726; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_738 = _schedule_T_737 | _schedule_T_727; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_739 = _schedule_T_738 | _schedule_T_728; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_740 = _schedule_T_739 | _schedule_T_729; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_741 = _schedule_T_740 | _schedule_T_730; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_742 = _schedule_T_741 | _schedule_T_731; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_743 = _schedule_T_742 | _schedule_T_732; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_744 = _schedule_T_743 | _schedule_T_733; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_745 = _schedule_T_744 | _schedule_T_734; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_746 = _schedule_T_745 | _schedule_T_735; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_747 = _schedule_T_746 | _schedule_T_736; // @[Mux.scala:30:73]
assign _schedule_WIRE_43 = _schedule_T_747; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_tag = _schedule_WIRE_43; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_771 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_772 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_773 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_774 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_775 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_776 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_777 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_778 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_779 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_780 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_781 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_782 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_783 = _schedule_T_771 | _schedule_T_772; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_784 = _schedule_T_783 | _schedule_T_773; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_785 = _schedule_T_784 | _schedule_T_774; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_786 = _schedule_T_785 | _schedule_T_775; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_787 = _schedule_T_786 | _schedule_T_776; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_788 = _schedule_T_787 | _schedule_T_777; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_789 = _schedule_T_788 | _schedule_T_778; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_790 = _schedule_T_789 | _schedule_T_779; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_791 = _schedule_T_790 | _schedule_T_780; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_792 = _schedule_T_791 | _schedule_T_781; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_793 = _schedule_T_792 | _schedule_T_782; // @[Mux.scala:30:73]
assign _schedule_WIRE_45 = _schedule_T_793; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_param = _schedule_WIRE_45; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_794 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_795 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_796 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_797 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_798 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_799 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_800 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_801 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_802 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_803 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_804 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_805 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_806 = _schedule_T_794 | _schedule_T_795; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_807 = _schedule_T_806 | _schedule_T_796; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_808 = _schedule_T_807 | _schedule_T_797; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_809 = _schedule_T_808 | _schedule_T_798; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_810 = _schedule_T_809 | _schedule_T_799; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_811 = _schedule_T_810 | _schedule_T_800; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_812 = _schedule_T_811 | _schedule_T_801; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_813 = _schedule_T_812 | _schedule_T_802; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_814 = _schedule_T_813 | _schedule_T_803; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_815 = _schedule_T_814 | _schedule_T_804; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_816 = _schedule_T_815 | _schedule_T_805; // @[Mux.scala:30:73]
assign _schedule_WIRE_46 = _schedule_T_816; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_opcode = _schedule_WIRE_46; // @[Mux.scala:30:73]
wire _schedule_T_817 = _schedule_T & _mshrs_0_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_818 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_819 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_820 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_821 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_822 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_823 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_824 = _schedule_T_7 & _mshrs_7_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_825 = _schedule_T_8 & _mshrs_8_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_826 = _schedule_T_9 & _mshrs_9_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_827 = _schedule_T_10 & _mshrs_10_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_828 = _schedule_T_11 & _mshrs_11_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_829 = _schedule_T_817 | _schedule_T_818; // @[Mux.scala:30:73]
wire _schedule_T_830 = _schedule_T_829 | _schedule_T_819; // @[Mux.scala:30:73]
wire _schedule_T_831 = _schedule_T_830 | _schedule_T_820; // @[Mux.scala:30:73]
wire _schedule_T_832 = _schedule_T_831 | _schedule_T_821; // @[Mux.scala:30:73]
wire _schedule_T_833 = _schedule_T_832 | _schedule_T_822; // @[Mux.scala:30:73]
wire _schedule_T_834 = _schedule_T_833 | _schedule_T_823; // @[Mux.scala:30:73]
wire _schedule_T_835 = _schedule_T_834 | _schedule_T_824; // @[Mux.scala:30:73]
wire _schedule_T_836 = _schedule_T_835 | _schedule_T_825; // @[Mux.scala:30:73]
wire _schedule_T_837 = _schedule_T_836 | _schedule_T_826; // @[Mux.scala:30:73]
wire _schedule_T_838 = _schedule_T_837 | _schedule_T_827; // @[Mux.scala:30:73]
wire _schedule_T_839 = _schedule_T_838 | _schedule_T_828; // @[Mux.scala:30:73]
assign _schedule_WIRE_47 = _schedule_T_839; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_valid = _schedule_WIRE_47; // @[Mux.scala:30:73]
wire _schedule_WIRE_54; // @[Mux.scala:30:73]
assign schedule_b_valid = _schedule_WIRE_48_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_49_param; // @[Mux.scala:30:73]
assign schedule_b_bits_param = _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_49_tag; // @[Mux.scala:30:73]
assign schedule_b_bits_tag = _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_49_set; // @[Mux.scala:30:73]
assign schedule_b_bits_set = _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_49_clients; // @[Mux.scala:30:73]
assign schedule_b_bits_clients = _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_53; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_param = _schedule_WIRE_49_param; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_52; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_tag = _schedule_WIRE_49_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_51; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_set = _schedule_WIRE_49_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_50; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_clients = _schedule_WIRE_49_clients; // @[Mux.scala:30:73]
wire _schedule_T_840 = _schedule_T & _mshrs_0_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_841 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_842 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_843 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_844 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_845 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_846 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_847 = _schedule_T_7 & _mshrs_7_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_848 = _schedule_T_8 & _mshrs_8_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_849 = _schedule_T_9 & _mshrs_9_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_850 = _schedule_T_10 & _mshrs_10_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_851 = _schedule_T_11 & _mshrs_11_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_852 = _schedule_T_840 | _schedule_T_841; // @[Mux.scala:30:73]
wire _schedule_T_853 = _schedule_T_852 | _schedule_T_842; // @[Mux.scala:30:73]
wire _schedule_T_854 = _schedule_T_853 | _schedule_T_843; // @[Mux.scala:30:73]
wire _schedule_T_855 = _schedule_T_854 | _schedule_T_844; // @[Mux.scala:30:73]
wire _schedule_T_856 = _schedule_T_855 | _schedule_T_845; // @[Mux.scala:30:73]
wire _schedule_T_857 = _schedule_T_856 | _schedule_T_846; // @[Mux.scala:30:73]
wire _schedule_T_858 = _schedule_T_857 | _schedule_T_847; // @[Mux.scala:30:73]
wire _schedule_T_859 = _schedule_T_858 | _schedule_T_848; // @[Mux.scala:30:73]
wire _schedule_T_860 = _schedule_T_859 | _schedule_T_849; // @[Mux.scala:30:73]
wire _schedule_T_861 = _schedule_T_860 | _schedule_T_850; // @[Mux.scala:30:73]
wire _schedule_T_862 = _schedule_T_861 | _schedule_T_851; // @[Mux.scala:30:73]
assign _schedule_WIRE_50 = _schedule_T_862; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_clients = _schedule_WIRE_50; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_863 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_864 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_865 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_866 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_867 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_868 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_869 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_870 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_871 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_872 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_873 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_874 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_875 = _schedule_T_863 | _schedule_T_864; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_876 = _schedule_T_875 | _schedule_T_865; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_877 = _schedule_T_876 | _schedule_T_866; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_878 = _schedule_T_877 | _schedule_T_867; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_879 = _schedule_T_878 | _schedule_T_868; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_880 = _schedule_T_879 | _schedule_T_869; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_881 = _schedule_T_880 | _schedule_T_870; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_882 = _schedule_T_881 | _schedule_T_871; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_883 = _schedule_T_882 | _schedule_T_872; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_884 = _schedule_T_883 | _schedule_T_873; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_885 = _schedule_T_884 | _schedule_T_874; // @[Mux.scala:30:73]
assign _schedule_WIRE_51 = _schedule_T_885; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_set = _schedule_WIRE_51; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_886 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_887 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_888 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_889 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_890 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_891 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_892 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_893 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_894 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_895 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_896 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_897 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_898 = _schedule_T_886 | _schedule_T_887; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_899 = _schedule_T_898 | _schedule_T_888; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_900 = _schedule_T_899 | _schedule_T_889; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_901 = _schedule_T_900 | _schedule_T_890; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_902 = _schedule_T_901 | _schedule_T_891; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_903 = _schedule_T_902 | _schedule_T_892; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_904 = _schedule_T_903 | _schedule_T_893; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_905 = _schedule_T_904 | _schedule_T_894; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_906 = _schedule_T_905 | _schedule_T_895; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_907 = _schedule_T_906 | _schedule_T_896; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_908 = _schedule_T_907 | _schedule_T_897; // @[Mux.scala:30:73]
assign _schedule_WIRE_52 = _schedule_T_908; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_tag = _schedule_WIRE_52; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_909 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_910 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_911 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_912 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_913 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_914 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_915 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_916 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_917 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_918 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_919 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_920 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_921 = _schedule_T_909 | _schedule_T_910; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_922 = _schedule_T_921 | _schedule_T_911; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_923 = _schedule_T_922 | _schedule_T_912; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_924 = _schedule_T_923 | _schedule_T_913; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_925 = _schedule_T_924 | _schedule_T_914; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_926 = _schedule_T_925 | _schedule_T_915; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_927 = _schedule_T_926 | _schedule_T_916; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_928 = _schedule_T_927 | _schedule_T_917; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_929 = _schedule_T_928 | _schedule_T_918; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_930 = _schedule_T_929 | _schedule_T_919; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_931 = _schedule_T_930 | _schedule_T_920; // @[Mux.scala:30:73]
assign _schedule_WIRE_53 = _schedule_T_931; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_param = _schedule_WIRE_53; // @[Mux.scala:30:73]
wire _schedule_T_932 = _schedule_T & _mshrs_0_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_933 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_934 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_935 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_936 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_937 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_938 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_939 = _schedule_T_7 & _mshrs_7_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_940 = _schedule_T_8 & _mshrs_8_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_941 = _schedule_T_9 & _mshrs_9_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_942 = _schedule_T_10 & _mshrs_10_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_943 = _schedule_T_11 & _mshrs_11_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_944 = _schedule_T_932 | _schedule_T_933; // @[Mux.scala:30:73]
wire _schedule_T_945 = _schedule_T_944 | _schedule_T_934; // @[Mux.scala:30:73]
wire _schedule_T_946 = _schedule_T_945 | _schedule_T_935; // @[Mux.scala:30:73]
wire _schedule_T_947 = _schedule_T_946 | _schedule_T_936; // @[Mux.scala:30:73]
wire _schedule_T_948 = _schedule_T_947 | _schedule_T_937; // @[Mux.scala:30:73]
wire _schedule_T_949 = _schedule_T_948 | _schedule_T_938; // @[Mux.scala:30:73]
wire _schedule_T_950 = _schedule_T_949 | _schedule_T_939; // @[Mux.scala:30:73]
wire _schedule_T_951 = _schedule_T_950 | _schedule_T_940; // @[Mux.scala:30:73]
wire _schedule_T_952 = _schedule_T_951 | _schedule_T_941; // @[Mux.scala:30:73]
wire _schedule_T_953 = _schedule_T_952 | _schedule_T_942; // @[Mux.scala:30:73]
wire _schedule_T_954 = _schedule_T_953 | _schedule_T_943; // @[Mux.scala:30:73]
assign _schedule_WIRE_54 = _schedule_T_954; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_valid = _schedule_WIRE_54; // @[Mux.scala:30:73]
wire _schedule_WIRE_62; // @[Mux.scala:30:73]
assign schedule_a_valid = _schedule_WIRE_55_valid; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_56_tag; // @[Mux.scala:30:73]
assign schedule_a_bits_tag = _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_56_set; // @[Mux.scala:30:73]
assign schedule_a_bits_set = _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_56_param; // @[Mux.scala:30:73]
assign schedule_a_bits_param = _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_56_block; // @[Mux.scala:30:73]
assign schedule_a_bits_block = _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73]
wire [8:0] _schedule_WIRE_61; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_tag = _schedule_WIRE_56_tag; // @[Mux.scala:30:73]
wire [10:0] _schedule_WIRE_60; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_set = _schedule_WIRE_56_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_59; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_param = _schedule_WIRE_56_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_57; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_block = _schedule_WIRE_56_block; // @[Mux.scala:30:73]
wire _schedule_T_955 = _schedule_T & _mshrs_0_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_956 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_957 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_958 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_959 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_960 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_961 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_962 = _schedule_T_7 & _mshrs_7_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_963 = _schedule_T_8 & _mshrs_8_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_964 = _schedule_T_9 & _mshrs_9_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_965 = _schedule_T_10 & _mshrs_10_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_966 = _schedule_T_11 & _mshrs_11_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_967 = _schedule_T_955 | _schedule_T_956; // @[Mux.scala:30:73]
wire _schedule_T_968 = _schedule_T_967 | _schedule_T_957; // @[Mux.scala:30:73]
wire _schedule_T_969 = _schedule_T_968 | _schedule_T_958; // @[Mux.scala:30:73]
wire _schedule_T_970 = _schedule_T_969 | _schedule_T_959; // @[Mux.scala:30:73]
wire _schedule_T_971 = _schedule_T_970 | _schedule_T_960; // @[Mux.scala:30:73]
wire _schedule_T_972 = _schedule_T_971 | _schedule_T_961; // @[Mux.scala:30:73]
wire _schedule_T_973 = _schedule_T_972 | _schedule_T_962; // @[Mux.scala:30:73]
wire _schedule_T_974 = _schedule_T_973 | _schedule_T_963; // @[Mux.scala:30:73]
wire _schedule_T_975 = _schedule_T_974 | _schedule_T_964; // @[Mux.scala:30:73]
wire _schedule_T_976 = _schedule_T_975 | _schedule_T_965; // @[Mux.scala:30:73]
wire _schedule_T_977 = _schedule_T_976 | _schedule_T_966; // @[Mux.scala:30:73]
assign _schedule_WIRE_57 = _schedule_T_977; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_block = _schedule_WIRE_57; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1001 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1002 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1003 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1004 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1005 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1006 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1007 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1008 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1009 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1010 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1011 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1012 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1013 = _schedule_T_1001 | _schedule_T_1002; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1014 = _schedule_T_1013 | _schedule_T_1003; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1015 = _schedule_T_1014 | _schedule_T_1004; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1016 = _schedule_T_1015 | _schedule_T_1005; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1017 = _schedule_T_1016 | _schedule_T_1006; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1018 = _schedule_T_1017 | _schedule_T_1007; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1019 = _schedule_T_1018 | _schedule_T_1008; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1020 = _schedule_T_1019 | _schedule_T_1009; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1021 = _schedule_T_1020 | _schedule_T_1010; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1022 = _schedule_T_1021 | _schedule_T_1011; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1023 = _schedule_T_1022 | _schedule_T_1012; // @[Mux.scala:30:73]
assign _schedule_WIRE_59 = _schedule_T_1023; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_param = _schedule_WIRE_59; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1024 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1025 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1026 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1027 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1028 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1029 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1030 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1031 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1032 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1033 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1034 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1035 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _schedule_T_1036 = _schedule_T_1024 | _schedule_T_1025; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1037 = _schedule_T_1036 | _schedule_T_1026; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1038 = _schedule_T_1037 | _schedule_T_1027; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1039 = _schedule_T_1038 | _schedule_T_1028; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1040 = _schedule_T_1039 | _schedule_T_1029; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1041 = _schedule_T_1040 | _schedule_T_1030; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1042 = _schedule_T_1041 | _schedule_T_1031; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1043 = _schedule_T_1042 | _schedule_T_1032; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1044 = _schedule_T_1043 | _schedule_T_1033; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1045 = _schedule_T_1044 | _schedule_T_1034; // @[Mux.scala:30:73]
wire [10:0] _schedule_T_1046 = _schedule_T_1045 | _schedule_T_1035; // @[Mux.scala:30:73]
assign _schedule_WIRE_60 = _schedule_T_1046; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_set = _schedule_WIRE_60; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1047 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1048 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1049 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1050 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1051 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1052 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1053 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1054 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1055 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1056 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1057 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1058 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _schedule_T_1059 = _schedule_T_1047 | _schedule_T_1048; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1060 = _schedule_T_1059 | _schedule_T_1049; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1061 = _schedule_T_1060 | _schedule_T_1050; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1062 = _schedule_T_1061 | _schedule_T_1051; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1063 = _schedule_T_1062 | _schedule_T_1052; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1064 = _schedule_T_1063 | _schedule_T_1053; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1065 = _schedule_T_1064 | _schedule_T_1054; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1066 = _schedule_T_1065 | _schedule_T_1055; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1067 = _schedule_T_1066 | _schedule_T_1056; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1068 = _schedule_T_1067 | _schedule_T_1057; // @[Mux.scala:30:73]
wire [8:0] _schedule_T_1069 = _schedule_T_1068 | _schedule_T_1058; // @[Mux.scala:30:73]
assign _schedule_WIRE_61 = _schedule_T_1069; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_tag = _schedule_WIRE_61; // @[Mux.scala:30:73]
wire _schedule_T_1070 = _schedule_T & _mshrs_0_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1071 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1072 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1073 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1074 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1075 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1076 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1077 = _schedule_T_7 & _mshrs_7_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1078 = _schedule_T_8 & _mshrs_8_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1079 = _schedule_T_9 & _mshrs_9_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1080 = _schedule_T_10 & _mshrs_10_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1081 = _schedule_T_11 & _mshrs_11_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1082 = _schedule_T_1070 | _schedule_T_1071; // @[Mux.scala:30:73]
wire _schedule_T_1083 = _schedule_T_1082 | _schedule_T_1072; // @[Mux.scala:30:73]
wire _schedule_T_1084 = _schedule_T_1083 | _schedule_T_1073; // @[Mux.scala:30:73]
wire _schedule_T_1085 = _schedule_T_1084 | _schedule_T_1074; // @[Mux.scala:30:73]
wire _schedule_T_1086 = _schedule_T_1085 | _schedule_T_1075; // @[Mux.scala:30:73]
wire _schedule_T_1087 = _schedule_T_1086 | _schedule_T_1076; // @[Mux.scala:30:73]
wire _schedule_T_1088 = _schedule_T_1087 | _schedule_T_1077; // @[Mux.scala:30:73]
wire _schedule_T_1089 = _schedule_T_1088 | _schedule_T_1078; // @[Mux.scala:30:73]
wire _schedule_T_1090 = _schedule_T_1089 | _schedule_T_1079; // @[Mux.scala:30:73]
wire _schedule_T_1091 = _schedule_T_1090 | _schedule_T_1080; // @[Mux.scala:30:73]
wire _schedule_T_1092 = _schedule_T_1091 | _schedule_T_1081; // @[Mux.scala:30:73]
assign _schedule_WIRE_62 = _schedule_T_1092; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_valid = _schedule_WIRE_62; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_12 = _scheduleTag_T ? _mshrs_0_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_13 = _scheduleTag_T_1 ? _mshrs_1_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_14 = _scheduleTag_T_2 ? _mshrs_2_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_15 = _scheduleTag_T_3 ? _mshrs_3_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_16 = _scheduleTag_T_4 ? _mshrs_4_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_17 = _scheduleTag_T_5 ? _mshrs_5_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_18 = _scheduleTag_T_6 ? _mshrs_6_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_19 = _scheduleTag_T_7 ? _mshrs_7_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_20 = _scheduleTag_T_8 ? _mshrs_8_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_21 = _scheduleTag_T_9 ? _mshrs_9_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_22 = _scheduleTag_T_10 ? _mshrs_10_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_23 = _scheduleTag_T_11 ? _mshrs_11_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36]
wire [8:0] _scheduleTag_T_24 = _scheduleTag_T_12 | _scheduleTag_T_13; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_25 = _scheduleTag_T_24 | _scheduleTag_T_14; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_26 = _scheduleTag_T_25 | _scheduleTag_T_15; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_27 = _scheduleTag_T_26 | _scheduleTag_T_16; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_28 = _scheduleTag_T_27 | _scheduleTag_T_17; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_29 = _scheduleTag_T_28 | _scheduleTag_T_18; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_30 = _scheduleTag_T_29 | _scheduleTag_T_19; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_31 = _scheduleTag_T_30 | _scheduleTag_T_20; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_32 = _scheduleTag_T_31 | _scheduleTag_T_21; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_33 = _scheduleTag_T_32 | _scheduleTag_T_22; // @[Mux.scala:30:73]
wire [8:0] _scheduleTag_T_34 = _scheduleTag_T_33 | _scheduleTag_T_23; // @[Mux.scala:30:73]
wire [8:0] scheduleTag = _scheduleTag_T_34; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_12 = _scheduleSet_T ? _mshrs_0_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_13 = _scheduleSet_T_1 ? _mshrs_1_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_14 = _scheduleSet_T_2 ? _mshrs_2_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_15 = _scheduleSet_T_3 ? _mshrs_3_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_16 = _scheduleSet_T_4 ? _mshrs_4_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_17 = _scheduleSet_T_5 ? _mshrs_5_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_18 = _scheduleSet_T_6 ? _mshrs_6_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_19 = _scheduleSet_T_7 ? _mshrs_7_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_20 = _scheduleSet_T_8 ? _mshrs_8_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_21 = _scheduleSet_T_9 ? _mshrs_9_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_22 = _scheduleSet_T_10 ? _mshrs_10_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_23 = _scheduleSet_T_11 ? _mshrs_11_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36]
wire [10:0] _scheduleSet_T_24 = _scheduleSet_T_12 | _scheduleSet_T_13; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_25 = _scheduleSet_T_24 | _scheduleSet_T_14; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_26 = _scheduleSet_T_25 | _scheduleSet_T_15; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_27 = _scheduleSet_T_26 | _scheduleSet_T_16; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_28 = _scheduleSet_T_27 | _scheduleSet_T_17; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_29 = _scheduleSet_T_28 | _scheduleSet_T_18; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_30 = _scheduleSet_T_29 | _scheduleSet_T_19; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_31 = _scheduleSet_T_30 | _scheduleSet_T_20; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_32 = _scheduleSet_T_31 | _scheduleSet_T_21; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_33 = _scheduleSet_T_32 | _scheduleSet_T_22; // @[Mux.scala:30:73]
wire [10:0] _scheduleSet_T_34 = _scheduleSet_T_33 | _scheduleSet_T_23; // @[Mux.scala:30:73]
wire [10:0] scheduleSet = _scheduleSet_T_34; // @[Mux.scala:30:73]
wire [10:0] _robin_filter_T = mshr_selectOH[11:1]; // @[package.scala:262:48]
wire [11:0] _robin_filter_T_1 = {mshr_selectOH[11], mshr_selectOH[10:0] | _robin_filter_T}; // @[Mux.scala:32:36]
wire [9:0] _robin_filter_T_2 = _robin_filter_T_1[11:2]; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_3 = {_robin_filter_T_1[11:10], _robin_filter_T_1[9:0] | _robin_filter_T_2}; // @[package.scala:262:{43,48}]
wire [7:0] _robin_filter_T_4 = _robin_filter_T_3[11:4]; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_5 = {_robin_filter_T_3[11:8], _robin_filter_T_3[7:0] | _robin_filter_T_4}; // @[package.scala:262:{43,48}]
wire [3:0] _robin_filter_T_6 = _robin_filter_T_5[11:8]; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_7 = {_robin_filter_T_5[11:4], _robin_filter_T_5[3:0] | _robin_filter_T_6}; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_8 = _robin_filter_T_7; // @[package.scala:262:43, :263:17]
wire [11:0] _robin_filter_T_9 = ~_robin_filter_T_8; // @[package.scala:263:17]
wire _schedule_c_bits_source_T = schedule_c_bits_opcode[1]; // @[Mux.scala:30:73]
assign _schedule_c_bits_source_T_1 = _schedule_c_bits_source_T ? mshr_select : 4'h0; // @[OneHot.scala:32:10]
assign schedule_c_bits_source = _schedule_c_bits_source_T_1; // @[Mux.scala:30:73]
assign _nestedwb_set_T = select_c ? _mshrs_11_io_status_bits_set : _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :153:32, :155:24]
assign nestedwb_set = _nestedwb_set_T; // @[Scheduler.scala:75:22, :155:24]
assign _nestedwb_tag_T = select_c ? _mshrs_11_io_status_bits_tag : _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46, :153:32, :156:24]
assign nestedwb_tag = _nestedwb_tag_T; // @[Scheduler.scala:75:22, :156:24]
wire _GEN = select_bc & _mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :154:32, :157:37]
wire _nestedwb_b_toN_T; // @[Scheduler.scala:157:37]
assign _nestedwb_b_toN_T = _GEN; // @[Scheduler.scala:157:37]
wire _nestedwb_b_toB_T; // @[Scheduler.scala:158:37]
assign _nestedwb_b_toB_T = _GEN; // @[Scheduler.scala:157:37, :158:37]
assign _nestedwb_b_clr_dirty_T = _GEN; // @[Scheduler.scala:157:37, :159:37]
wire _nestedwb_b_toN_T_1 = _mshrs_10_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala:71:46, :157:123]
assign _nestedwb_b_toN_T_2 = _nestedwb_b_toN_T & _nestedwb_b_toN_T_1; // @[Scheduler.scala:157:{37,75,123}]
assign nestedwb_b_toN = _nestedwb_b_toN_T_2; // @[Scheduler.scala:75:22, :157:75]
wire _nestedwb_b_toB_T_1 = _mshrs_10_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala:71:46, :158:123]
assign _nestedwb_b_toB_T_2 = _nestedwb_b_toB_T & _nestedwb_b_toB_T_1; // @[Scheduler.scala:158:{37,75,123}]
assign nestedwb_b_toB = _nestedwb_b_toB_T_2; // @[Scheduler.scala:75:22, :158:75]
assign nestedwb_b_clr_dirty = _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:75:22, :159:37]
wire _nestedwb_c_set_dirty_T = select_c & _mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :153:32, :160:37]
assign _nestedwb_c_set_dirty_T_1 = _nestedwb_c_set_dirty_T & _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46, :160:{37,75}]
assign nestedwb_c_set_dirty = _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:75:22, :160:75]
wire _request_ready_T_2; // @[Scheduler.scala:261:40]
wire _request_valid_T_2; // @[Scheduler.scala:164:39]
wire _request_bits_T_1_prio_0; // @[Scheduler.scala:165:22]
wire _view__WIRE_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_7_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_8_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_9_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_10_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_11_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _request_bits_T_1_prio_2; // @[Scheduler.scala:165:22]
wire _request_bits_T_1_control; // @[Scheduler.scala:165:22]
wire _view__WIRE_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_7_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_8_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_9_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_10_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_11_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_opcode; // @[Scheduler.scala:165:22]
wire _view__WIRE_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_7_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_8_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_9_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_10_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_11_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_param; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_7_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_8_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_9_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_10_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_11_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_size; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_7_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_8_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_9_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_10_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_11_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _request_bits_T_1_source; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_7_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_8_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_9_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_10_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_11_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _request_bits_T_1_tag; // @[Scheduler.scala:165:22]
wire [5:0] _view__WIRE_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_1_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_2_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_3_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_4_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_5_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_6_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_7_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_8_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_9_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_10_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_11_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _request_bits_T_1_offset; // @[Scheduler.scala:165:22]
wire [8:0] _view__WIRE_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_1_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_2_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_3_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_4_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_5_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_6_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_7_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_8_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_9_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_10_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [8:0] _view__WIRE_11_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _request_bits_T_1_put; // @[Scheduler.scala:165:22]
wire [5:0] _view__WIRE_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_1_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_2_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_3_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_4_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_5_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_6_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_7_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_8_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_9_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_10_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_11_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [10:0] _request_bits_T_1_set; // @[Scheduler.scala:165:22]
wire [5:0] _view__WIRE_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_1_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_2_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_3_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_4_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_5_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_6_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_7_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_8_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_9_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_10_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_11_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [10:0] request_bits_set; // @[Scheduler.scala:163:21]
wire request_ready; // @[Scheduler.scala:163:21]
wire request_valid; // @[Scheduler.scala:163:21]
wire _request_valid_T = _sinkA_io_req_valid | _sinkX_io_req_valid; // @[Scheduler.scala:54:21, :58:21, :164:62]
wire _request_valid_T_1 = _request_valid_T | _sinkC_io_req_valid; // @[Scheduler.scala:55:21, :164:{62,84}]
assign _request_valid_T_2 = _directory_io_ready & _request_valid_T_1; // @[Scheduler.scala:68:25, :164:{39,84}]
assign request_valid = _request_valid_T_2; // @[Scheduler.scala:163:21, :164:39]
wire [2:0] _request_bits_T_opcode = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [2:0] _request_bits_T_param = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [2:0] _request_bits_T_size = _sinkX_io_req_valid ? 3'h6 : _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [5:0] _request_bits_T_source = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [8:0] _request_bits_T_tag = _sinkX_io_req_valid ? _sinkX_io_req_bits_tag : _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [5:0] _request_bits_T_offset = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [5:0] _request_bits_T_put = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [10:0] _request_bits_T_set = _sinkX_io_req_valid ? _sinkX_io_req_bits_set : _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire _request_bits_T_control; // @[Scheduler.scala:166:22]
assign _request_bits_T_1_control = ~_sinkC_io_req_valid & _request_bits_T_control; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_opcode = _sinkC_io_req_valid ? _sinkC_io_req_bits_opcode : _request_bits_T_opcode; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_param = _sinkC_io_req_valid ? _sinkC_io_req_bits_param : _request_bits_T_param; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_size = _sinkC_io_req_valid ? _sinkC_io_req_bits_size : _request_bits_T_size; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_source = _sinkC_io_req_valid ? _sinkC_io_req_bits_source : _request_bits_T_source; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_tag = _sinkC_io_req_valid ? _sinkC_io_req_bits_tag : _request_bits_T_tag; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_offset = _sinkC_io_req_valid ? _sinkC_io_req_bits_offset : _request_bits_T_offset; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_put = _sinkC_io_req_valid ? _sinkC_io_req_bits_put : _request_bits_T_put; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_set = _sinkC_io_req_valid ? _sinkC_io_req_bits_set : _request_bits_T_set; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_prio_0 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22]
assign request_bits_prio_0 = _request_bits_T_1_prio_0; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_prio_2 = _request_bits_T_1_prio_2; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_control = _request_bits_T_1_control; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_opcode = _request_bits_T_1_opcode; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_param = _request_bits_T_1_param; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_size = _request_bits_T_1_size; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_source = _request_bits_T_1_source; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_tag = _request_bits_T_1_tag; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_offset = _request_bits_T_1_offset; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_put = _request_bits_T_1_put; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_set = _request_bits_T_1_set; // @[Scheduler.scala:163:21, :165:22]
wire _GEN_0 = _directory_io_ready & request_ready; // @[Scheduler.scala:68:25, :163:21, :167:44]
wire _sinkC_io_req_ready_T; // @[Scheduler.scala:167:44]
assign _sinkC_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44]
wire _sinkX_io_req_ready_T; // @[Scheduler.scala:168:44]
assign _sinkX_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :168:44]
wire _sinkA_io_req_ready_T; // @[Scheduler.scala:169:44]
assign _sinkA_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :169:44]
wire _sinkX_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :168:64]
wire _sinkX_io_req_ready_T_2 = _sinkX_io_req_ready_T & _sinkX_io_req_ready_T_1; // @[Scheduler.scala:168:{44,61,64}]
wire _sinkA_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :169:64]
wire _sinkA_io_req_ready_T_2 = _sinkA_io_req_ready_T & _sinkA_io_req_ready_T_1; // @[Scheduler.scala:169:{44,61,64}]
wire _sinkA_io_req_ready_T_3 = ~_sinkX_io_req_valid; // @[Scheduler.scala:58:21, :169:87]
wire _sinkA_io_req_ready_T_4 = _sinkA_io_req_ready_T_2 & _sinkA_io_req_ready_T_3; // @[Scheduler.scala:169:{61,84,87}]
wire _setMatches_T = _mshrs_0_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_1 = _mshrs_0_io_status_valid & _setMatches_T; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_2 = _mshrs_1_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_3 = _mshrs_1_io_status_valid & _setMatches_T_2; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_4 = _mshrs_2_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_5 = _mshrs_2_io_status_valid & _setMatches_T_4; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_6 = _mshrs_3_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_7 = _mshrs_3_io_status_valid & _setMatches_T_6; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_8 = _mshrs_4_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_9 = _mshrs_4_io_status_valid & _setMatches_T_8; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_10 = _mshrs_5_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_11 = _mshrs_5_io_status_valid & _setMatches_T_10; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_12 = _mshrs_6_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_13 = _mshrs_6_io_status_valid & _setMatches_T_12; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_14 = _mshrs_7_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_15 = _mshrs_7_io_status_valid & _setMatches_T_14; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_16 = _mshrs_8_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_17 = _mshrs_8_io_status_valid & _setMatches_T_16; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_18 = _mshrs_9_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_19 = _mshrs_9_io_status_valid & _setMatches_T_18; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_20 = _mshrs_10_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_21 = _mshrs_10_io_status_valid & _setMatches_T_20; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_22 = _mshrs_11_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_23 = _mshrs_11_io_status_valid & _setMatches_T_22; // @[Scheduler.scala:71:46, :172:{59,83}]
wire [1:0] setMatches_lo_lo_hi = {_setMatches_T_5, _setMatches_T_3}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_lo_lo = {setMatches_lo_lo_hi, _setMatches_T_1}; // @[Scheduler.scala:172:{23,59}]
wire [1:0] setMatches_lo_hi_hi = {_setMatches_T_11, _setMatches_T_9}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_lo_hi = {setMatches_lo_hi_hi, _setMatches_T_7}; // @[Scheduler.scala:172:{23,59}]
wire [5:0] setMatches_lo = {setMatches_lo_hi, setMatches_lo_lo}; // @[Scheduler.scala:172:23]
wire [1:0] setMatches_hi_lo_hi = {_setMatches_T_17, _setMatches_T_15}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_hi_lo = {setMatches_hi_lo_hi, _setMatches_T_13}; // @[Scheduler.scala:172:{23,59}]
wire [1:0] setMatches_hi_hi_hi = {_setMatches_T_23, _setMatches_T_21}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_hi_hi = {setMatches_hi_hi_hi, _setMatches_T_19}; // @[Scheduler.scala:172:{23,59}]
wire [5:0] setMatches_hi = {setMatches_hi_hi, setMatches_hi_lo}; // @[Scheduler.scala:172:23]
wire [11:0] setMatches = {setMatches_hi, setMatches_lo}; // @[Scheduler.scala:172:23]
wire _alloc_T = |setMatches; // @[Scheduler.scala:172:23, :173:27]
wire alloc = ~_alloc_T; // @[Scheduler.scala:173:{15,27}]
wire _blockB_T = setMatches[0]; // @[Mux.scala:32:36]
wire _blockC_T = setMatches[0]; // @[Mux.scala:32:36]
wire _nestB_T = setMatches[0]; // @[Mux.scala:32:36]
wire _nestC_T = setMatches[0]; // @[Mux.scala:32:36]
wire _blockB_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _blockC_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _nestB_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _nestC_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _blockB_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _blockC_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _nestB_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _nestC_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _blockB_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _blockC_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _nestB_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _nestC_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _blockB_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _blockC_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _nestB_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _nestC_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _blockB_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _blockC_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _nestB_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _nestC_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _blockB_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _blockC_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _nestB_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _nestC_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _blockB_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _blockC_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _nestB_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _nestC_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _blockB_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _blockC_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _nestB_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _nestC_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _blockB_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _blockC_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _nestB_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _nestC_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _blockB_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _blockC_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _nestB_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _nestC_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _blockB_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _blockC_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _nestB_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _nestC_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _blockB_T_12 = _blockB_T & _mshrs_0_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_13 = _blockB_T_1 & _mshrs_1_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_14 = _blockB_T_2 & _mshrs_2_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_15 = _blockB_T_3 & _mshrs_3_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_16 = _blockB_T_4 & _mshrs_4_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_17 = _blockB_T_5 & _mshrs_5_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_18 = _blockB_T_6 & _mshrs_6_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_19 = _blockB_T_7 & _mshrs_7_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_20 = _blockB_T_8 & _mshrs_8_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_21 = _blockB_T_9 & _mshrs_9_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_22 = _blockB_T_10 & _mshrs_10_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_23 = _blockB_T_11 & _mshrs_11_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_24 = _blockB_T_12 | _blockB_T_13; // @[Mux.scala:30:73]
wire _blockB_T_25 = _blockB_T_24 | _blockB_T_14; // @[Mux.scala:30:73]
wire _blockB_T_26 = _blockB_T_25 | _blockB_T_15; // @[Mux.scala:30:73]
wire _blockB_T_27 = _blockB_T_26 | _blockB_T_16; // @[Mux.scala:30:73]
wire _blockB_T_28 = _blockB_T_27 | _blockB_T_17; // @[Mux.scala:30:73]
wire _blockB_T_29 = _blockB_T_28 | _blockB_T_18; // @[Mux.scala:30:73]
wire _blockB_T_30 = _blockB_T_29 | _blockB_T_19; // @[Mux.scala:30:73]
wire _blockB_T_31 = _blockB_T_30 | _blockB_T_20; // @[Mux.scala:30:73]
wire _blockB_T_32 = _blockB_T_31 | _blockB_T_21; // @[Mux.scala:30:73]
wire _blockB_T_33 = _blockB_T_32 | _blockB_T_22; // @[Mux.scala:30:73]
wire _blockB_T_34 = _blockB_T_33 | _blockB_T_23; // @[Mux.scala:30:73]
wire _blockB_WIRE = _blockB_T_34; // @[Mux.scala:30:73]
wire _blockC_T_12 = _blockC_T & _mshrs_0_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_13 = _blockC_T_1 & _mshrs_1_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_14 = _blockC_T_2 & _mshrs_2_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_15 = _blockC_T_3 & _mshrs_3_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_16 = _blockC_T_4 & _mshrs_4_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_17 = _blockC_T_5 & _mshrs_5_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_18 = _blockC_T_6 & _mshrs_6_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_19 = _blockC_T_7 & _mshrs_7_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_20 = _blockC_T_8 & _mshrs_8_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_21 = _blockC_T_9 & _mshrs_9_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_22 = _blockC_T_10 & _mshrs_10_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_23 = _blockC_T_11 & _mshrs_11_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_24 = _blockC_T_12 | _blockC_T_13; // @[Mux.scala:30:73]
wire _blockC_T_25 = _blockC_T_24 | _blockC_T_14; // @[Mux.scala:30:73]
wire _blockC_T_26 = _blockC_T_25 | _blockC_T_15; // @[Mux.scala:30:73]
wire _blockC_T_27 = _blockC_T_26 | _blockC_T_16; // @[Mux.scala:30:73]
wire _blockC_T_28 = _blockC_T_27 | _blockC_T_17; // @[Mux.scala:30:73]
wire _blockC_T_29 = _blockC_T_28 | _blockC_T_18; // @[Mux.scala:30:73]
wire _blockC_T_30 = _blockC_T_29 | _blockC_T_19; // @[Mux.scala:30:73]
wire _blockC_T_31 = _blockC_T_30 | _blockC_T_20; // @[Mux.scala:30:73]
wire _blockC_T_32 = _blockC_T_31 | _blockC_T_21; // @[Mux.scala:30:73]
wire _blockC_T_33 = _blockC_T_32 | _blockC_T_22; // @[Mux.scala:30:73]
wire _blockC_T_34 = _blockC_T_33 | _blockC_T_23; // @[Mux.scala:30:73]
wire _blockC_WIRE = _blockC_T_34; // @[Mux.scala:30:73]
wire blockC = _blockC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73]
wire _nestB_T_12 = _nestB_T & _mshrs_0_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_13 = _nestB_T_1 & _mshrs_1_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_14 = _nestB_T_2 & _mshrs_2_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_15 = _nestB_T_3 & _mshrs_3_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_16 = _nestB_T_4 & _mshrs_4_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_17 = _nestB_T_5 & _mshrs_5_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_18 = _nestB_T_6 & _mshrs_6_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_19 = _nestB_T_7 & _mshrs_7_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_20 = _nestB_T_8 & _mshrs_8_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_21 = _nestB_T_9 & _mshrs_9_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_22 = _nestB_T_10 & _mshrs_10_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_23 = _nestB_T_11 & _mshrs_11_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_24 = _nestB_T_12 | _nestB_T_13; // @[Mux.scala:30:73]
wire _nestB_T_25 = _nestB_T_24 | _nestB_T_14; // @[Mux.scala:30:73]
wire _nestB_T_26 = _nestB_T_25 | _nestB_T_15; // @[Mux.scala:30:73]
wire _nestB_T_27 = _nestB_T_26 | _nestB_T_16; // @[Mux.scala:30:73]
wire _nestB_T_28 = _nestB_T_27 | _nestB_T_17; // @[Mux.scala:30:73]
wire _nestB_T_29 = _nestB_T_28 | _nestB_T_18; // @[Mux.scala:30:73]
wire _nestB_T_30 = _nestB_T_29 | _nestB_T_19; // @[Mux.scala:30:73]
wire _nestB_T_31 = _nestB_T_30 | _nestB_T_20; // @[Mux.scala:30:73]
wire _nestB_T_32 = _nestB_T_31 | _nestB_T_21; // @[Mux.scala:30:73]
wire _nestB_T_33 = _nestB_T_32 | _nestB_T_22; // @[Mux.scala:30:73]
wire _nestB_T_34 = _nestB_T_33 | _nestB_T_23; // @[Mux.scala:30:73]
wire _nestB_WIRE = _nestB_T_34; // @[Mux.scala:30:73]
wire _nestC_T_12 = _nestC_T & _mshrs_0_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_13 = _nestC_T_1 & _mshrs_1_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_14 = _nestC_T_2 & _mshrs_2_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_15 = _nestC_T_3 & _mshrs_3_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_16 = _nestC_T_4 & _mshrs_4_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_17 = _nestC_T_5 & _mshrs_5_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_18 = _nestC_T_6 & _mshrs_6_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_19 = _nestC_T_7 & _mshrs_7_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_20 = _nestC_T_8 & _mshrs_8_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_21 = _nestC_T_9 & _mshrs_9_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_22 = _nestC_T_10 & _mshrs_10_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_23 = _nestC_T_11 & _mshrs_11_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_24 = _nestC_T_12 | _nestC_T_13; // @[Mux.scala:30:73]
wire _nestC_T_25 = _nestC_T_24 | _nestC_T_14; // @[Mux.scala:30:73]
wire _nestC_T_26 = _nestC_T_25 | _nestC_T_15; // @[Mux.scala:30:73]
wire _nestC_T_27 = _nestC_T_26 | _nestC_T_16; // @[Mux.scala:30:73]
wire _nestC_T_28 = _nestC_T_27 | _nestC_T_17; // @[Mux.scala:30:73]
wire _nestC_T_29 = _nestC_T_28 | _nestC_T_18; // @[Mux.scala:30:73]
wire _nestC_T_30 = _nestC_T_29 | _nestC_T_19; // @[Mux.scala:30:73]
wire _nestC_T_31 = _nestC_T_30 | _nestC_T_20; // @[Mux.scala:30:73]
wire _nestC_T_32 = _nestC_T_31 | _nestC_T_21; // @[Mux.scala:30:73]
wire _nestC_T_33 = _nestC_T_32 | _nestC_T_22; // @[Mux.scala:30:73]
wire _nestC_T_34 = _nestC_T_33 | _nestC_T_23; // @[Mux.scala:30:73]
wire _nestC_WIRE = _nestC_T_34; // @[Mux.scala:30:73]
wire nestC = _nestC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73]
wire _prioFilter_T = ~request_bits_prio_0; // @[Scheduler.scala:163:21, :182:46]
wire [1:0] prioFilter_hi = {request_bits_prio_2, _prioFilter_T}; // @[Scheduler.scala:163:21, :182:{23,46}]
wire [11:0] prioFilter = {prioFilter_hi, 10'h3FF}; // @[Scheduler.scala:182:23]
wire [11:0] lowerMatches = setMatches & prioFilter; // @[Scheduler.scala:172:23, :182:23, :183:33]
wire _queue_T = |lowerMatches; // @[Scheduler.scala:183:33, :185:28]
wire _queue_T_2 = _queue_T; // @[Scheduler.scala:185:{28,32}]
wire _queue_T_3 = ~nestC; // @[Scheduler.scala:180:70, :185:45]
wire _queue_T_4 = _queue_T_2 & _queue_T_3; // @[Scheduler.scala:185:{32,42,45}]
wire _queue_T_6 = _queue_T_4; // @[Scheduler.scala:185:{42,52}]
wire _queue_T_7 = ~blockC; // @[Scheduler.scala:176:70, :185:66]
wire queue = _queue_T_6 & _queue_T_7; // @[Scheduler.scala:185:{52,63,66}]
wire _T_12 = request_valid & queue; // @[Scheduler.scala:163:21, :185:63, :195:31]
wire _bypass_T; // @[Scheduler.scala:213:30]
assign _bypass_T = _T_12; // @[Scheduler.scala:195:31, :213:30]
wire _bypass_T_1; // @[Scheduler.scala:231:32]
assign _bypass_T_1 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_2; // @[Scheduler.scala:231:32]
assign _bypass_T_2 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_3; // @[Scheduler.scala:231:32]
assign _bypass_T_3 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_4; // @[Scheduler.scala:231:32]
assign _bypass_T_4 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_5; // @[Scheduler.scala:231:32]
assign _bypass_T_5 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_6; // @[Scheduler.scala:231:32]
assign _bypass_T_6 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_7; // @[Scheduler.scala:231:32]
assign _bypass_T_7 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_8; // @[Scheduler.scala:231:32]
assign _bypass_T_8 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_9; // @[Scheduler.scala:231:32]
assign _bypass_T_9 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_10; // @[Scheduler.scala:231:32]
assign _bypass_T_10 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_11; // @[Scheduler.scala:231:32]
assign _bypass_T_11 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_12; // @[Scheduler.scala:231:32]
assign _bypass_T_12 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _requests_io_push_valid_T; // @[Scheduler.scala:270:43]
assign _requests_io_push_valid_T = _T_12; // @[Scheduler.scala:195:31, :270:43]
wire _lowerMatches1_T = lowerMatches[11]; // @[Scheduler.scala:183:33, :200:21]
wire _lowerMatches1_T_2 = lowerMatches[10]; // @[Scheduler.scala:183:33, :201:21]
wire [11:0] _lowerMatches1_T_4 = _lowerMatches1_T_2 ? 12'h400 : lowerMatches; // @[Scheduler.scala:183:33, :201:{8,21}]
wire [11:0] lowerMatches1 = _lowerMatches1_T ? 12'h800 : _lowerMatches1_T_4; // @[Scheduler.scala:200:{8,21}, :201:8]
wire [11:0] _requests_io_push_bits_index_T = lowerMatches1; // @[Scheduler.scala:200:8, :274:30]
wire [23:0] _GEN_1 = {2{mshr_selectOH}}; // @[Scheduler.scala:121:70, :206:30]
wire [23:0] selected_requests_hi; // @[Scheduler.scala:206:30]
assign selected_requests_hi = _GEN_1; // @[Scheduler.scala:206:30]
wire [23:0] pop_index_hi; // @[Scheduler.scala:241:31]
assign pop_index_hi = _GEN_1; // @[Scheduler.scala:206:30, :241:31]
wire [35:0] _selected_requests_T = {selected_requests_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :206:30]
wire [35:0] selected_requests = _selected_requests_T & _requests_io_valid; // @[Scheduler.scala:70:24, :206:{30,76}]
wire [11:0] _a_pop_T = selected_requests[11:0]; // @[Scheduler.scala:206:76, :207:32]
wire a_pop = |_a_pop_T; // @[Scheduler.scala:207:{32,79}]
wire [11:0] _b_pop_T = selected_requests[23:12]; // @[Scheduler.scala:206:76, :208:32]
wire b_pop = |_b_pop_T; // @[Scheduler.scala:208:{32,79}]
wire _bypassMatches_T_4 = b_pop; // @[Scheduler.scala:208:79, :211:76]
wire [11:0] _c_pop_T = selected_requests[35:24]; // @[Scheduler.scala:206:76, :209:32]
wire c_pop = |_c_pop_T; // @[Scheduler.scala:209:{32,79}]
wire [11:0] _bypassMatches_T = mshr_selectOH & lowerMatches1; // @[Scheduler.scala:121:70, :200:8, :210:38]
wire _bypassMatches_T_1 = |_bypassMatches_T; // @[Scheduler.scala:210:{38,55}]
wire _bypassMatches_T_2 = c_pop | request_bits_prio_2; // @[Scheduler.scala:163:21, :209:79, :211:33]
wire _bypassMatches_T_3 = ~c_pop; // @[Scheduler.scala:209:79, :211:58]
wire _bypassMatches_T_5 = ~b_pop; // @[Scheduler.scala:208:79, :211:101]
wire _bypassMatches_T_6 = ~a_pop; // @[Scheduler.scala:207:79, :211:109]
wire _bypassMatches_T_7 = _bypassMatches_T_4 ? _bypassMatches_T_5 : _bypassMatches_T_6; // @[Scheduler.scala:211:{69,76,101,109}]
wire _bypassMatches_T_8 = _bypassMatches_T_2 ? _bypassMatches_T_3 : _bypassMatches_T_7; // @[Scheduler.scala:211:{26,33,58,69}]
wire bypassMatches = _bypassMatches_T_1 & _bypassMatches_T_8; // @[Scheduler.scala:210:{55,59}, :211:26]
wire _may_pop_T = a_pop | b_pop; // @[Scheduler.scala:207:79, :208:79, :212:23]
wire may_pop = _may_pop_T | c_pop; // @[Scheduler.scala:209:79, :212:{23,32}]
wire bypass = _bypass_T & bypassMatches; // @[Scheduler.scala:210:59, :213:{30,39}]
wire _will_reload_T = may_pop | bypass; // @[Scheduler.scala:212:32, :213:39, :214:49]
wire will_reload = schedule_reload & _will_reload_T; // @[Mux.scala:30:73]
wire _GEN_2 = schedule_reload & may_pop; // @[Mux.scala:30:73]
wire _will_pop_T; // @[Scheduler.scala:215:34]
assign _will_pop_T = _GEN_2; // @[Scheduler.scala:215:34]
wire _mshr_uses_directory_assuming_no_bypass_T; // @[Scheduler.scala:247:64]
assign _mshr_uses_directory_assuming_no_bypass_T = _GEN_2; // @[Scheduler.scala:215:34, :247:64]
wire _will_pop_T_1 = ~bypass; // @[Scheduler.scala:213:39, :215:48]
wire will_pop = _will_pop_T & _will_pop_T_1; // @[Scheduler.scala:215:{34,45,48}]
wire a_pop_1 = _requests_io_valid[0]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_1 = _requests_io_valid[12]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_12 = b_pop_1; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_1 = _requests_io_valid[24]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_9 = lowerMatches1[0]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_10 = c_pop_1 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_11 = ~c_pop_1; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_13 = ~b_pop_1; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_14 = ~a_pop_1; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_15 = _bypassMatches_T_12 ? _bypassMatches_T_13 : _bypassMatches_T_14; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_16 = _bypassMatches_T_10 ? _bypassMatches_T_11 : _bypassMatches_T_15; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_1 = _bypassMatches_T_9 & _bypassMatches_T_16; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_1 = a_pop_1 | b_pop_1; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_1 = _may_pop_T_1 | c_pop_1; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_1 = _bypass_T_1 & bypassMatches_1; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_1 = may_pop_1 | bypass_1; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_1 = _mshrs_0_io_schedule_bits_reload & _will_reload_T_1; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_prio_0 = bypass_1 ? _view__WIRE_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_prio_1 = ~bypass_1 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_prio_2 = bypass_1 ? _view__WIRE_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_control = bypass_1 ? _view__WIRE_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_opcode = bypass_1 ? _view__WIRE_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_param = bypass_1 ? _view__WIRE_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_size = bypass_1 ? _view__WIRE_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_source = bypass_1 ? _view__WIRE_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_tag = bypass_1 ? _view__WIRE_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_offset = bypass_1 ? _view__WIRE_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_put = bypass_1 ? _view__WIRE_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_0_io_allocate_bits_repeat_T = mshrs_0_io_allocate_bits_tag == _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_0_io_allocate_valid_T = sel & will_reload_1; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_2 = _requests_io_valid[1]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_2 = _requests_io_valid[13]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_20 = b_pop_2; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_2 = _requests_io_valid[25]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_17 = lowerMatches1[1]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_18 = c_pop_2 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_19 = ~c_pop_2; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_21 = ~b_pop_2; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_22 = ~a_pop_2; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_23 = _bypassMatches_T_20 ? _bypassMatches_T_21 : _bypassMatches_T_22; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_24 = _bypassMatches_T_18 ? _bypassMatches_T_19 : _bypassMatches_T_23; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_2 = _bypassMatches_T_17 & _bypassMatches_T_24; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_2 = a_pop_2 | b_pop_2; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_2 = _may_pop_T_2 | c_pop_2; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_2 = _bypass_T_2 & bypassMatches_2; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_2 = may_pop_2 | bypass_2; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_2 = _mshrs_1_io_schedule_bits_reload & _will_reload_T_2; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_1_prio_0 = bypass_2 ? _view__WIRE_1_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_1_prio_1 = ~bypass_2 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_1_prio_2 = bypass_2 ? _view__WIRE_1_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_1_control = bypass_2 ? _view__WIRE_1_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_opcode = bypass_2 ? _view__WIRE_1_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_param = bypass_2 ? _view__WIRE_1_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_size = bypass_2 ? _view__WIRE_1_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_1_source = bypass_2 ? _view__WIRE_1_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_1_tag = bypass_2 ? _view__WIRE_1_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_1_offset = bypass_2 ? _view__WIRE_1_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_1_put = bypass_2 ? _view__WIRE_1_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_1_io_allocate_bits_repeat_T = mshrs_1_io_allocate_bits_tag == _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_1_io_allocate_valid_T = sel_1 & will_reload_2; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_3 = _requests_io_valid[2]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_3 = _requests_io_valid[14]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_28 = b_pop_3; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_3 = _requests_io_valid[26]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_25 = lowerMatches1[2]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_26 = c_pop_3 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_27 = ~c_pop_3; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_29 = ~b_pop_3; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_30 = ~a_pop_3; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_31 = _bypassMatches_T_28 ? _bypassMatches_T_29 : _bypassMatches_T_30; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_32 = _bypassMatches_T_26 ? _bypassMatches_T_27 : _bypassMatches_T_31; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_3 = _bypassMatches_T_25 & _bypassMatches_T_32; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_3 = a_pop_3 | b_pop_3; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_3 = _may_pop_T_3 | c_pop_3; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_3 = _bypass_T_3 & bypassMatches_3; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_3 = may_pop_3 | bypass_3; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_3 = _mshrs_2_io_schedule_bits_reload & _will_reload_T_3; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_2_prio_0 = bypass_3 ? _view__WIRE_2_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_2_prio_1 = ~bypass_3 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_2_prio_2 = bypass_3 ? _view__WIRE_2_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_2_control = bypass_3 ? _view__WIRE_2_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_opcode = bypass_3 ? _view__WIRE_2_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_param = bypass_3 ? _view__WIRE_2_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_size = bypass_3 ? _view__WIRE_2_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_2_source = bypass_3 ? _view__WIRE_2_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_2_tag = bypass_3 ? _view__WIRE_2_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_2_offset = bypass_3 ? _view__WIRE_2_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_2_put = bypass_3 ? _view__WIRE_2_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_2_io_allocate_bits_repeat_T = mshrs_2_io_allocate_bits_tag == _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_2_io_allocate_valid_T = sel_2 & will_reload_3; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_4 = _requests_io_valid[3]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_4 = _requests_io_valid[15]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_36 = b_pop_4; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_4 = _requests_io_valid[27]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_33 = lowerMatches1[3]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_34 = c_pop_4 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_35 = ~c_pop_4; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_37 = ~b_pop_4; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_38 = ~a_pop_4; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_39 = _bypassMatches_T_36 ? _bypassMatches_T_37 : _bypassMatches_T_38; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_40 = _bypassMatches_T_34 ? _bypassMatches_T_35 : _bypassMatches_T_39; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_4 = _bypassMatches_T_33 & _bypassMatches_T_40; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_4 = a_pop_4 | b_pop_4; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_4 = _may_pop_T_4 | c_pop_4; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_4 = _bypass_T_4 & bypassMatches_4; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_4 = may_pop_4 | bypass_4; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_4 = _mshrs_3_io_schedule_bits_reload & _will_reload_T_4; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_3_prio_0 = bypass_4 ? _view__WIRE_3_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_3_prio_1 = ~bypass_4 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_3_prio_2 = bypass_4 ? _view__WIRE_3_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_3_control = bypass_4 ? _view__WIRE_3_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_opcode = bypass_4 ? _view__WIRE_3_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_param = bypass_4 ? _view__WIRE_3_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_size = bypass_4 ? _view__WIRE_3_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_3_source = bypass_4 ? _view__WIRE_3_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_3_tag = bypass_4 ? _view__WIRE_3_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_3_offset = bypass_4 ? _view__WIRE_3_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_3_put = bypass_4 ? _view__WIRE_3_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_3_io_allocate_bits_repeat_T = mshrs_3_io_allocate_bits_tag == _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_3_io_allocate_valid_T = sel_3 & will_reload_4; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_5 = _requests_io_valid[4]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_5 = _requests_io_valid[16]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_44 = b_pop_5; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_5 = _requests_io_valid[28]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_41 = lowerMatches1[4]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_42 = c_pop_5 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_43 = ~c_pop_5; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_45 = ~b_pop_5; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_46 = ~a_pop_5; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_47 = _bypassMatches_T_44 ? _bypassMatches_T_45 : _bypassMatches_T_46; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_48 = _bypassMatches_T_42 ? _bypassMatches_T_43 : _bypassMatches_T_47; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_5 = _bypassMatches_T_41 & _bypassMatches_T_48; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_5 = a_pop_5 | b_pop_5; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_5 = _may_pop_T_5 | c_pop_5; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_5 = _bypass_T_5 & bypassMatches_5; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_5 = may_pop_5 | bypass_5; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_5 = _mshrs_4_io_schedule_bits_reload & _will_reload_T_5; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_4_prio_0 = bypass_5 ? _view__WIRE_4_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_4_prio_1 = ~bypass_5 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_4_prio_2 = bypass_5 ? _view__WIRE_4_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_4_control = bypass_5 ? _view__WIRE_4_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_opcode = bypass_5 ? _view__WIRE_4_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_param = bypass_5 ? _view__WIRE_4_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_size = bypass_5 ? _view__WIRE_4_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_4_source = bypass_5 ? _view__WIRE_4_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_4_tag = bypass_5 ? _view__WIRE_4_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_4_offset = bypass_5 ? _view__WIRE_4_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_4_put = bypass_5 ? _view__WIRE_4_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_4_io_allocate_bits_repeat_T = mshrs_4_io_allocate_bits_tag == _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_4_io_allocate_valid_T = sel_4 & will_reload_5; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_6 = _requests_io_valid[5]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_6 = _requests_io_valid[17]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_52 = b_pop_6; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_6 = _requests_io_valid[29]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_49 = lowerMatches1[5]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_50 = c_pop_6 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_51 = ~c_pop_6; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_53 = ~b_pop_6; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_54 = ~a_pop_6; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_55 = _bypassMatches_T_52 ? _bypassMatches_T_53 : _bypassMatches_T_54; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_56 = _bypassMatches_T_50 ? _bypassMatches_T_51 : _bypassMatches_T_55; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_6 = _bypassMatches_T_49 & _bypassMatches_T_56; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_6 = a_pop_6 | b_pop_6; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_6 = _may_pop_T_6 | c_pop_6; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_6 = _bypass_T_6 & bypassMatches_6; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_6 = may_pop_6 | bypass_6; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_6 = _mshrs_5_io_schedule_bits_reload & _will_reload_T_6; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_5_prio_0 = bypass_6 ? _view__WIRE_5_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_5_prio_1 = ~bypass_6 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_5_prio_2 = bypass_6 ? _view__WIRE_5_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_5_control = bypass_6 ? _view__WIRE_5_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_opcode = bypass_6 ? _view__WIRE_5_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_param = bypass_6 ? _view__WIRE_5_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_size = bypass_6 ? _view__WIRE_5_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_5_source = bypass_6 ? _view__WIRE_5_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_5_tag = bypass_6 ? _view__WIRE_5_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_5_offset = bypass_6 ? _view__WIRE_5_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_5_put = bypass_6 ? _view__WIRE_5_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_5_io_allocate_bits_repeat_T = mshrs_5_io_allocate_bits_tag == _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_5_io_allocate_valid_T = sel_5 & will_reload_6; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_7 = _requests_io_valid[6]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_7 = _requests_io_valid[18]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_60 = b_pop_7; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_7 = _requests_io_valid[30]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_57 = lowerMatches1[6]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_58 = c_pop_7 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_59 = ~c_pop_7; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_61 = ~b_pop_7; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_62 = ~a_pop_7; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_63 = _bypassMatches_T_60 ? _bypassMatches_T_61 : _bypassMatches_T_62; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_64 = _bypassMatches_T_58 ? _bypassMatches_T_59 : _bypassMatches_T_63; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_7 = _bypassMatches_T_57 & _bypassMatches_T_64; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_7 = a_pop_7 | b_pop_7; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_7 = _may_pop_T_7 | c_pop_7; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_7 = _bypass_T_7 & bypassMatches_7; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_7 = may_pop_7 | bypass_7; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_7 = _mshrs_6_io_schedule_bits_reload & _will_reload_T_7; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_6_prio_0 = bypass_7 ? _view__WIRE_6_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_6_prio_1 = ~bypass_7 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_6_prio_2 = bypass_7 ? _view__WIRE_6_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_6_control = bypass_7 ? _view__WIRE_6_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_opcode = bypass_7 ? _view__WIRE_6_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_param = bypass_7 ? _view__WIRE_6_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_size = bypass_7 ? _view__WIRE_6_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_6_source = bypass_7 ? _view__WIRE_6_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_6_tag = bypass_7 ? _view__WIRE_6_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_6_offset = bypass_7 ? _view__WIRE_6_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_6_put = bypass_7 ? _view__WIRE_6_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_6_io_allocate_bits_repeat_T = mshrs_6_io_allocate_bits_tag == _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_6_io_allocate_valid_T = sel_6 & will_reload_7; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_8 = _requests_io_valid[7]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_8 = _requests_io_valid[19]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_68 = b_pop_8; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_8 = _requests_io_valid[31]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_65 = lowerMatches1[7]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_66 = c_pop_8 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_67 = ~c_pop_8; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_69 = ~b_pop_8; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_70 = ~a_pop_8; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_71 = _bypassMatches_T_68 ? _bypassMatches_T_69 : _bypassMatches_T_70; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_72 = _bypassMatches_T_66 ? _bypassMatches_T_67 : _bypassMatches_T_71; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_8 = _bypassMatches_T_65 & _bypassMatches_T_72; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_8 = a_pop_8 | b_pop_8; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_8 = _may_pop_T_8 | c_pop_8; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_8 = _bypass_T_8 & bypassMatches_8; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_8 = may_pop_8 | bypass_8; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_8 = _mshrs_7_io_schedule_bits_reload & _will_reload_T_8; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_7_prio_0 = bypass_8 ? _view__WIRE_7_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_7_prio_1 = ~bypass_8 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_7_prio_2 = bypass_8 ? _view__WIRE_7_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_7_control = bypass_8 ? _view__WIRE_7_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_7_opcode = bypass_8 ? _view__WIRE_7_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_7_param = bypass_8 ? _view__WIRE_7_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_7_size = bypass_8 ? _view__WIRE_7_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_7_source = bypass_8 ? _view__WIRE_7_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_7_tag = bypass_8 ? _view__WIRE_7_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_7_offset = bypass_8 ? _view__WIRE_7_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_7_put = bypass_8 ? _view__WIRE_7_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_7_io_allocate_bits_repeat_T = mshrs_7_io_allocate_bits_tag == _mshrs_7_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_7_io_allocate_valid_T = sel_7 & will_reload_8; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_9 = _requests_io_valid[8]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_9 = _requests_io_valid[20]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_76 = b_pop_9; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_9 = _requests_io_valid[32]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_73 = lowerMatches1[8]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_74 = c_pop_9 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_75 = ~c_pop_9; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_77 = ~b_pop_9; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_78 = ~a_pop_9; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_79 = _bypassMatches_T_76 ? _bypassMatches_T_77 : _bypassMatches_T_78; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_80 = _bypassMatches_T_74 ? _bypassMatches_T_75 : _bypassMatches_T_79; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_9 = _bypassMatches_T_73 & _bypassMatches_T_80; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_9 = a_pop_9 | b_pop_9; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_9 = _may_pop_T_9 | c_pop_9; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_9 = _bypass_T_9 & bypassMatches_9; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_9 = may_pop_9 | bypass_9; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_9 = _mshrs_8_io_schedule_bits_reload & _will_reload_T_9; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_8_prio_0 = bypass_9 ? _view__WIRE_8_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_8_prio_1 = ~bypass_9 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_8_prio_2 = bypass_9 ? _view__WIRE_8_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_8_control = bypass_9 ? _view__WIRE_8_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_8_opcode = bypass_9 ? _view__WIRE_8_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_8_param = bypass_9 ? _view__WIRE_8_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_8_size = bypass_9 ? _view__WIRE_8_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_8_source = bypass_9 ? _view__WIRE_8_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_8_tag = bypass_9 ? _view__WIRE_8_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_8_offset = bypass_9 ? _view__WIRE_8_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_8_put = bypass_9 ? _view__WIRE_8_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_8_io_allocate_bits_repeat_T = mshrs_8_io_allocate_bits_tag == _mshrs_8_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_8_io_allocate_valid_T = sel_8 & will_reload_9; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_10 = _requests_io_valid[9]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_10 = _requests_io_valid[21]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_84 = b_pop_10; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_10 = _requests_io_valid[33]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_81 = lowerMatches1[9]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_82 = c_pop_10 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_83 = ~c_pop_10; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_85 = ~b_pop_10; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_86 = ~a_pop_10; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_87 = _bypassMatches_T_84 ? _bypassMatches_T_85 : _bypassMatches_T_86; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_88 = _bypassMatches_T_82 ? _bypassMatches_T_83 : _bypassMatches_T_87; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_10 = _bypassMatches_T_81 & _bypassMatches_T_88; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_10 = a_pop_10 | b_pop_10; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_10 = _may_pop_T_10 | c_pop_10; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_10 = _bypass_T_10 & bypassMatches_10; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_10 = may_pop_10 | bypass_10; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_10 = _mshrs_9_io_schedule_bits_reload & _will_reload_T_10; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_9_prio_0 = bypass_10 ? _view__WIRE_9_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_9_prio_1 = ~bypass_10 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_9_prio_2 = bypass_10 ? _view__WIRE_9_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_9_control = bypass_10 ? _view__WIRE_9_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_9_opcode = bypass_10 ? _view__WIRE_9_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_9_param = bypass_10 ? _view__WIRE_9_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_9_size = bypass_10 ? _view__WIRE_9_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_9_source = bypass_10 ? _view__WIRE_9_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_9_tag = bypass_10 ? _view__WIRE_9_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_9_offset = bypass_10 ? _view__WIRE_9_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_9_put = bypass_10 ? _view__WIRE_9_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_9_io_allocate_bits_repeat_T = mshrs_9_io_allocate_bits_tag == _mshrs_9_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_9_io_allocate_valid_T = sel_9 & will_reload_10; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_11 = _requests_io_valid[10]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_11 = _requests_io_valid[22]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_92 = b_pop_11; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_11 = _requests_io_valid[34]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_89 = lowerMatches1[10]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_90 = c_pop_11 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_91 = ~c_pop_11; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_93 = ~b_pop_11; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_94 = ~a_pop_11; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_95 = _bypassMatches_T_92 ? _bypassMatches_T_93 : _bypassMatches_T_94; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_96 = _bypassMatches_T_90 ? _bypassMatches_T_91 : _bypassMatches_T_95; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_11 = _bypassMatches_T_89 & _bypassMatches_T_96; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_11 = a_pop_11 | b_pop_11; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_11 = _may_pop_T_11 | c_pop_11; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_11 = _bypass_T_11 & bypassMatches_11; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_11 = may_pop_11 | bypass_11; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_11 = _mshrs_10_io_schedule_bits_reload & _will_reload_T_11; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_10_prio_0 = bypass_11 ? _view__WIRE_10_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_10_prio_1 = ~bypass_11 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_10_prio_2 = bypass_11 ? _view__WIRE_10_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_10_control = bypass_11 ? _view__WIRE_10_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_10_opcode = bypass_11 ? _view__WIRE_10_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_10_param = bypass_11 ? _view__WIRE_10_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_10_size = bypass_11 ? _view__WIRE_10_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_10_source = bypass_11 ? _view__WIRE_10_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_10_tag = bypass_11 ? _view__WIRE_10_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_10_offset = bypass_11 ? _view__WIRE_10_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_10_put = bypass_11 ? _view__WIRE_10_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_10_io_allocate_bits_repeat_T = mshrs_10_io_allocate_bits_tag == _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :287:131, :289:74]
wire _mshrs_10_io_allocate_valid_T = sel_10 & will_reload_11; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_12 = _requests_io_valid[11]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_12 = _requests_io_valid[23]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_100 = b_pop_12; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_12 = _requests_io_valid[35]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_97 = lowerMatches1[11]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_98 = c_pop_12 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_99 = ~c_pop_12; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_101 = ~b_pop_12; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_102 = ~a_pop_12; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_103 = _bypassMatches_T_100 ? _bypassMatches_T_101 : _bypassMatches_T_102; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_104 = _bypassMatches_T_98 ? _bypassMatches_T_99 : _bypassMatches_T_103; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_12 = _bypassMatches_T_97 & _bypassMatches_T_104; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_12 = a_pop_12 | b_pop_12; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_12 = _may_pop_T_12 | c_pop_12; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_12 = _bypass_T_12 & bypassMatches_12; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_12 = may_pop_12 | bypass_12; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_12 = _mshrs_11_io_schedule_bits_reload & _will_reload_T_12; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_11_prio_0 = bypass_12 ? _view__WIRE_11_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_11_prio_1 = ~bypass_12 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_11_prio_2 = bypass_12 ? _view__WIRE_11_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_11_control = bypass_12 ? _view__WIRE_11_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_11_opcode = bypass_12 ? _view__WIRE_11_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_11_param = bypass_12 ? _view__WIRE_11_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_11_size = bypass_12 ? _view__WIRE_11_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_11_source = bypass_12 ? _view__WIRE_11_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [8:0] _view__T_11_tag = bypass_12 ? _view__WIRE_11_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_11_offset = bypass_12 ? _view__WIRE_11_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_11_put = bypass_12 ? _view__WIRE_11_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_11_io_allocate_bits_repeat_T = mshrs_11_io_allocate_bits_tag == _mshrs_11_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :295:103, :297:73]
wire _mshrs_11_io_allocate_valid_T = sel_11 & will_reload_12; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire [35:0] _prio_requests_T = ~_requests_io_valid; // @[Scheduler.scala:70:24, :240:25]
wire [23:0] _prio_requests_T_1 = _requests_io_valid[35:12]; // @[Scheduler.scala:70:24, :240:65]
wire [35:0] _prio_requests_T_2 = {_prio_requests_T[35:24], _prio_requests_T[23:0] | _prio_requests_T_1}; // @[Scheduler.scala:240:{25,44,65}]
wire [11:0] _prio_requests_T_3 = _requests_io_valid[35:24]; // @[Scheduler.scala:70:24, :240:103]
wire [35:0] _prio_requests_T_4 = {_prio_requests_T_2[35:12], _prio_requests_T_2[11:0] | _prio_requests_T_3}; // @[Scheduler.scala:240:{44,82,103}]
wire [35:0] prio_requests = ~_prio_requests_T_4; // @[Scheduler.scala:240:{23,82}]
wire [35:0] _pop_index_T = {pop_index_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :241:31]
wire [35:0] _pop_index_T_1 = _pop_index_T & prio_requests; // @[Scheduler.scala:240:23, :241:{31,77}]
wire [3:0] pop_index_hi_1 = _pop_index_T_1[35:32]; // @[OneHot.scala:30:18]
wire [31:0] pop_index_lo = _pop_index_T_1[31:0]; // @[OneHot.scala:31:18]
wire _pop_index_T_2 = |pop_index_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [31:0] _pop_index_T_3 = {28'h0, pop_index_hi_1} | pop_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [15:0] pop_index_hi_2 = _pop_index_T_3[31:16]; // @[OneHot.scala:30:18, :32:28]
wire [15:0] pop_index_lo_1 = _pop_index_T_3[15:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_4 = |pop_index_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _pop_index_T_5 = pop_index_hi_2 | pop_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] pop_index_hi_3 = _pop_index_T_5[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] pop_index_lo_2 = _pop_index_T_5[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_6 = |pop_index_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _pop_index_T_7 = pop_index_hi_3 | pop_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] pop_index_hi_4 = _pop_index_T_7[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] pop_index_lo_3 = _pop_index_T_7[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_8 = |pop_index_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _pop_index_T_9 = pop_index_hi_4 | pop_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] pop_index_hi_5 = _pop_index_T_9[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] pop_index_lo_4 = _pop_index_T_9[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_10 = |pop_index_hi_5; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _pop_index_T_11 = pop_index_hi_5 | pop_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _pop_index_T_12 = _pop_index_T_11[1]; // @[OneHot.scala:32:28]
wire [1:0] _pop_index_T_13 = {_pop_index_T_10, _pop_index_T_12}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _pop_index_T_14 = {_pop_index_T_8, _pop_index_T_13}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _pop_index_T_15 = {_pop_index_T_6, _pop_index_T_14}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _pop_index_T_16 = {_pop_index_T_4, _pop_index_T_15}; // @[OneHot.scala:32:{10,14}]
wire [5:0] pop_index = {_pop_index_T_2, _pop_index_T_16}; // @[OneHot.scala:32:{10,14}]
wire lb_tag_mismatch = scheduleTag != _requests_io_data_tag; // @[Mux.scala:30:73]
wire mshr_uses_directory_assuming_no_bypass = _mshr_uses_directory_assuming_no_bypass_T & lb_tag_mismatch; // @[Scheduler.scala:246:37, :247:{64,75}]
wire mshr_uses_directory_for_lb = will_pop & lb_tag_mismatch; // @[Scheduler.scala:215:45, :246:37, :248:45]
wire [8:0] _mshr_uses_directory_T = bypass ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :163:21, :213:39, :249:63]
wire _mshr_uses_directory_T_1 = scheduleTag != _mshr_uses_directory_T; // @[Mux.scala:30:73]
wire mshr_uses_directory = will_reload & _mshr_uses_directory_T_1; // @[Scheduler.scala:214:37, :249:{41,56}]
wire [1:0] mshr_validOH_lo_lo_hi = {_mshrs_2_io_status_valid, _mshrs_1_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_lo_lo = {mshr_validOH_lo_lo_hi, _mshrs_0_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [1:0] mshr_validOH_lo_hi_hi = {_mshrs_5_io_status_valid, _mshrs_4_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_lo_hi = {mshr_validOH_lo_hi_hi, _mshrs_3_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [5:0] mshr_validOH_lo = {mshr_validOH_lo_hi, mshr_validOH_lo_lo}; // @[Scheduler.scala:252:25]
wire [1:0] mshr_validOH_hi_lo_hi = {_mshrs_8_io_status_valid, _mshrs_7_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_hi_lo = {mshr_validOH_hi_lo_hi, _mshrs_6_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [1:0] mshr_validOH_hi_hi_hi = {_mshrs_11_io_status_valid, _mshrs_10_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_hi_hi = {mshr_validOH_hi_hi_hi, _mshrs_9_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [5:0] mshr_validOH_hi = {mshr_validOH_hi_hi, mshr_validOH_hi_lo}; // @[Scheduler.scala:252:25]
wire [11:0] mshr_validOH = {mshr_validOH_hi, mshr_validOH_lo}; // @[Scheduler.scala:252:25]
wire [11:0] _mshr_free_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20]
wire [11:0] _mshr_free_T_1 = _mshr_free_T & prioFilter; // @[Scheduler.scala:182:23, :253:{20,34}]
wire mshr_free = |_mshr_free_T_1; // @[Scheduler.scala:253:{34,48}]
wire bypassQueue = schedule_reload & bypassMatches; // @[Mux.scala:30:73]
wire _request_alloc_cases_T = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16]
wire _request_alloc_cases_T_1 = alloc & _request_alloc_cases_T; // @[Scheduler.scala:173:15, :258:{13,16}]
wire _request_alloc_cases_T_2 = _request_alloc_cases_T_1 & mshr_free; // @[Scheduler.scala:253:48, :258:{13,56}]
wire _request_alloc_cases_T_9 = _request_alloc_cases_T_2; // @[Scheduler.scala:258:{56,70}]
wire _request_alloc_cases_T_3 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :259:16]
wire _request_alloc_cases_T_5 = ~_mshrs_10_io_status_valid; // @[Scheduler.scala:71:46, :259:59]
wire _request_alloc_cases_T_7 = ~_mshrs_11_io_status_valid; // @[Scheduler.scala:71:46, :259:87]
wire _request_alloc_cases_T_10 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :260:16]
wire _request_alloc_cases_T_11 = nestC & _request_alloc_cases_T_10; // @[Scheduler.scala:180:70, :260:{13,16}]
wire _request_alloc_cases_T_12 = ~_mshrs_11_io_status_valid; // @[Scheduler.scala:71:46, :259:87, :260:59]
wire _request_alloc_cases_T_13 = _request_alloc_cases_T_11 & _request_alloc_cases_T_12; // @[Scheduler.scala:260:{13,56,59}]
wire request_alloc_cases = _request_alloc_cases_T_9 | _request_alloc_cases_T_13; // @[Scheduler.scala:258:70, :259:112, :260:56]
wire _request_ready_T = bypassQueue | _requests_io_push_ready; // @[Scheduler.scala:70:24, :256:37, :261:66]
wire _request_ready_T_1 = queue & _request_ready_T; // @[Scheduler.scala:185:63, :261:{50,66}]
assign _request_ready_T_2 = request_alloc_cases | _request_ready_T_1; // @[Scheduler.scala:259:112, :261:{40,50}]
assign request_ready = _request_ready_T_2; // @[Scheduler.scala:163:21, :261:40]
wire alloc_uses_directory = request_valid & request_alloc_cases; // @[Scheduler.scala:163:21, :259:112, :262:44]
wire _directory_io_read_valid_T = mshr_uses_directory | alloc_uses_directory; // @[Scheduler.scala:249:41, :262:44, :265:50]
wire [10:0] _directory_io_read_bits_set_T = mshr_uses_directory_for_lb ? scheduleSet : request_bits_set; // @[Mux.scala:30:73]
wire [8:0] _directory_io_read_bits_tag_T = mshr_uses_directory_for_lb ? _requests_io_data_tag : request_bits_tag; // @[Scheduler.scala:70:24, :163:21, :248:45, :267:36]
wire _requests_io_push_valid_T_1 = ~bypassQueue; // @[Scheduler.scala:256:37, :270:55]
wire _requests_io_push_valid_T_2 = _requests_io_push_valid_T & _requests_io_push_valid_T_1; // @[Scheduler.scala:270:{43,52,55}]
wire [3:0] requests_io_push_bits_index_hi = _requests_io_push_bits_index_T[11:8]; // @[OneHot.scala:30:18]
wire [7:0] requests_io_push_bits_index_lo = _requests_io_push_bits_index_T[7:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_1 = |requests_io_push_bits_index_hi; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_2 = {4'h0, requests_io_push_bits_index_hi} | requests_io_push_bits_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_1 = _requests_io_push_bits_index_T_2[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_1 = _requests_io_push_bits_index_T_2[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_3 = |requests_io_push_bits_index_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_4 = requests_io_push_bits_index_hi_1 | requests_io_push_bits_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_2 = _requests_io_push_bits_index_T_4[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_2 = _requests_io_push_bits_index_T_4[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_5 = |requests_io_push_bits_index_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_6 = requests_io_push_bits_index_hi_2 | requests_io_push_bits_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_7 = _requests_io_push_bits_index_T_6[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_8 = {_requests_io_push_bits_index_T_5, _requests_io_push_bits_index_T_7}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_9 = {_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_8}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_10 = {_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_9}; // @[OneHot.scala:32:{10,14}]
wire [23:0] _requests_io_push_bits_index_T_11 = {lowerMatches1, 12'h0}; // @[Scheduler.scala:200:8, :275:30]
wire [7:0] requests_io_push_bits_index_hi_3 = _requests_io_push_bits_index_T_11[23:16]; // @[OneHot.scala:30:18]
wire [15:0] requests_io_push_bits_index_lo_3 = _requests_io_push_bits_index_T_11[15:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_12 = |requests_io_push_bits_index_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _requests_io_push_bits_index_T_13 = {8'h0, requests_io_push_bits_index_hi_3} | requests_io_push_bits_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] requests_io_push_bits_index_hi_4 = _requests_io_push_bits_index_T_13[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] requests_io_push_bits_index_lo_4 = _requests_io_push_bits_index_T_13[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_14 = |requests_io_push_bits_index_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_15 = requests_io_push_bits_index_hi_4 | requests_io_push_bits_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_5 = _requests_io_push_bits_index_T_15[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_5 = _requests_io_push_bits_index_T_15[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_16 = |requests_io_push_bits_index_hi_5; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_17 = requests_io_push_bits_index_hi_5 | requests_io_push_bits_index_lo_5; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_6 = _requests_io_push_bits_index_T_17[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_6 = _requests_io_push_bits_index_T_17[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_18 = |requests_io_push_bits_index_hi_6; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_19 = requests_io_push_bits_index_hi_6 | requests_io_push_bits_index_lo_6; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_20 = _requests_io_push_bits_index_T_19[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_21 = {_requests_io_push_bits_index_T_18, _requests_io_push_bits_index_T_20}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_22 = {_requests_io_push_bits_index_T_16, _requests_io_push_bits_index_T_21}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_23 = {_requests_io_push_bits_index_T_14, _requests_io_push_bits_index_T_22}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _requests_io_push_bits_index_T_24 = {_requests_io_push_bits_index_T_12, _requests_io_push_bits_index_T_23}; // @[OneHot.scala:32:{10,14}]
wire [35:0] _requests_io_push_bits_index_T_25 = {lowerMatches1, 24'h0}; // @[Scheduler.scala:200:8, :276:30]
wire [3:0] requests_io_push_bits_index_hi_7 = _requests_io_push_bits_index_T_25[35:32]; // @[OneHot.scala:30:18]
wire [31:0] requests_io_push_bits_index_lo_7 = _requests_io_push_bits_index_T_25[31:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_26 = |requests_io_push_bits_index_hi_7; // @[OneHot.scala:30:18, :32:14]
wire [31:0] _requests_io_push_bits_index_T_27 = {28'h0, requests_io_push_bits_index_hi_7} | requests_io_push_bits_index_lo_7; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [15:0] requests_io_push_bits_index_hi_8 = _requests_io_push_bits_index_T_27[31:16]; // @[OneHot.scala:30:18, :32:28]
wire [15:0] requests_io_push_bits_index_lo_8 = _requests_io_push_bits_index_T_27[15:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_28 = |requests_io_push_bits_index_hi_8; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _requests_io_push_bits_index_T_29 = requests_io_push_bits_index_hi_8 | requests_io_push_bits_index_lo_8; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] requests_io_push_bits_index_hi_9 = _requests_io_push_bits_index_T_29[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] requests_io_push_bits_index_lo_9 = _requests_io_push_bits_index_T_29[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_30 = |requests_io_push_bits_index_hi_9; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_31 = requests_io_push_bits_index_hi_9 | requests_io_push_bits_index_lo_9; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_10 = _requests_io_push_bits_index_T_31[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_10 = _requests_io_push_bits_index_T_31[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_32 = |requests_io_push_bits_index_hi_10; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_33 = requests_io_push_bits_index_hi_10 | requests_io_push_bits_index_lo_10; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_11 = _requests_io_push_bits_index_T_33[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_11 = _requests_io_push_bits_index_T_33[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_34 = |requests_io_push_bits_index_hi_11; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_35 = requests_io_push_bits_index_hi_11 | requests_io_push_bits_index_lo_11; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_36 = _requests_io_push_bits_index_T_35[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_37 = {_requests_io_push_bits_index_T_34, _requests_io_push_bits_index_T_36}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_38 = {_requests_io_push_bits_index_T_32, _requests_io_push_bits_index_T_37}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_39 = {_requests_io_push_bits_index_T_30, _requests_io_push_bits_index_T_38}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _requests_io_push_bits_index_T_40 = {_requests_io_push_bits_index_T_28, _requests_io_push_bits_index_T_39}; // @[OneHot.scala:32:{10,14}]
wire [5:0] _requests_io_push_bits_index_T_41 = {_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_40}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_42 = request_bits_prio_0 ? _requests_io_push_bits_index_T_10 : 4'h0; // @[OneHot.scala:32:10]
wire [5:0] _requests_io_push_bits_index_T_44 = request_bits_prio_2 ? _requests_io_push_bits_index_T_41 : 6'h0; // @[OneHot.scala:32:10]
wire [4:0] _requests_io_push_bits_index_T_45 = {1'h0, _requests_io_push_bits_index_T_42}; // @[Mux.scala:30:73]
wire [5:0] _requests_io_push_bits_index_T_46 = {1'h0, _requests_io_push_bits_index_T_45} | _requests_io_push_bits_index_T_44; // @[Mux.scala:30:73]
wire [5:0] _requests_io_push_bits_index_WIRE = _requests_io_push_bits_index_T_46; // @[Mux.scala:30:73]
wire [11:0] _mshr_insertOH_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:32]
wire [12:0] _mshr_insertOH_T_1 = {_mshr_insertOH_T, 1'h0}; // @[package.scala:253:48]
wire [11:0] _mshr_insertOH_T_2 = _mshr_insertOH_T_1[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_3 = _mshr_insertOH_T | _mshr_insertOH_T_2; // @[package.scala:253:{43,53}]
wire [13:0] _mshr_insertOH_T_4 = {_mshr_insertOH_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [11:0] _mshr_insertOH_T_5 = _mshr_insertOH_T_4[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_6 = _mshr_insertOH_T_3 | _mshr_insertOH_T_5; // @[package.scala:253:{43,53}]
wire [15:0] _mshr_insertOH_T_7 = {_mshr_insertOH_T_6, 4'h0}; // @[package.scala:253:{43,48}]
wire [11:0] _mshr_insertOH_T_8 = _mshr_insertOH_T_7[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_9 = _mshr_insertOH_T_6 | _mshr_insertOH_T_8; // @[package.scala:253:{43,53}]
wire [19:0] _mshr_insertOH_T_10 = {_mshr_insertOH_T_9, 8'h0}; // @[package.scala:253:{43,48}]
wire [11:0] _mshr_insertOH_T_11 = _mshr_insertOH_T_10[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_12 = _mshr_insertOH_T_9 | _mshr_insertOH_T_11; // @[package.scala:253:{43,53}]
wire [11:0] _mshr_insertOH_T_13 = _mshr_insertOH_T_12; // @[package.scala:253:43, :254:17]
wire [12:0] _mshr_insertOH_T_14 = {_mshr_insertOH_T_13, 1'h0}; // @[package.scala:254:17]
wire [12:0] _mshr_insertOH_T_15 = ~_mshr_insertOH_T_14; // @[Scheduler.scala:278:{23,47}]
wire [11:0] _mshr_insertOH_T_16 = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:55]
wire [12:0] _mshr_insertOH_T_17 = {1'h0, _mshr_insertOH_T_15[11:0] & _mshr_insertOH_T_16}; // @[Scheduler.scala:278:{23,53,55}]
wire [12:0] mshr_insertOH = {1'h0, _mshr_insertOH_T_17[11:0] & prioFilter}; // @[Scheduler.scala:182:23, :278:{53,69}]
wire _T_76 = request_valid & alloc; // @[Scheduler.scala:163:21, :173:15, :280:25]
wire _T_35 = _T_76 & mshr_insertOH[0] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_0_io_allocate_bits_tag = _T_35 ? request_bits_tag : _view__T_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_39 = _T_76 & mshr_insertOH[1] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_1_io_allocate_bits_tag = _T_39 ? request_bits_tag : _view__T_1_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_43 = _T_76 & mshr_insertOH[2] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_2_io_allocate_bits_tag = _T_43 ? request_bits_tag : _view__T_2_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_47 = _T_76 & mshr_insertOH[3] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_3_io_allocate_bits_tag = _T_47 ? request_bits_tag : _view__T_3_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_51 = _T_76 & mshr_insertOH[4] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_4_io_allocate_bits_tag = _T_51 ? request_bits_tag : _view__T_4_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_55 = _T_76 & mshr_insertOH[5] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_5_io_allocate_bits_tag = _T_55 ? request_bits_tag : _view__T_5_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_59 = _T_76 & mshr_insertOH[6] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_6_io_allocate_bits_tag = _T_59 ? request_bits_tag : _view__T_6_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_63 = _T_76 & mshr_insertOH[7] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_7_io_allocate_bits_tag = _T_63 ? request_bits_tag : _view__T_7_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_67 = _T_76 & mshr_insertOH[8] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_8_io_allocate_bits_tag = _T_67 ? request_bits_tag : _view__T_8_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_71 = _T_76 & mshr_insertOH[9] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_9_io_allocate_bits_tag = _T_71 ? request_bits_tag : _view__T_9_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_75 = _T_76 & mshr_insertOH[10] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_10_io_allocate_bits_tag = _T_75 ? request_bits_tag : _view__T_10_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70, :287:131, :289:74]
wire _T_95 = request_valid & nestC & ~_mshrs_11_io_status_valid & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:71:46, :163:21, :180:70, :193:33, :247:75, :258:16, :259:87, :295:{32,59}]
wire _GEN_3 = _T_95 | _T_76 & mshr_insertOH[11] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:193:33, :236:25, :247:75, :258:16, :278:69, :279:18, :280:{25,34,39,83}, :281:27, :295:{32,59,103}, :296:30]
assign mshrs_11_io_allocate_bits_tag = _GEN_3 ? request_bits_tag : _view__T_11_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :236:25, :280:83, :281:27, :282:70, :295:103, :296:30, :297:73] |
Generate the Verilog code corresponding to this FIRRTL code module PE_307 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_51
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_307( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_51 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SourceC :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<12>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, bs_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, flip bs_dat : { data : UInt<64>}, evict_req : { set : UInt<10>, way : UInt<3>}, flip evict_safe : UInt<1>}
inst queue of Queue12_TLBundleC_a32d64s3k3z3c
connect queue.clock, clock
connect queue.reset, reset
regreset fill : UInt<4>, clock, reset, UInt<4>(0h0)
regreset room : UInt<1>, clock, reset, UInt<1>(0h1)
node _T = and(queue.io.enq.ready, queue.io.enq.valid)
node _T_1 = and(queue.io.deq.ready, queue.io.deq.valid)
node _T_2 = neq(_T, _T_1)
when _T_2 :
node _fill_T = and(queue.io.enq.ready, queue.io.enq.valid)
node _fill_T_1 = not(UInt<4>(0h0))
node _fill_T_2 = mux(_fill_T, UInt<1>(0h1), _fill_T_1)
node _fill_T_3 = add(fill, _fill_T_2)
node _fill_T_4 = tail(_fill_T_3, 1)
connect fill, _fill_T_4
node _room_T = eq(fill, UInt<1>(0h0))
node _room_T_1 = eq(fill, UInt<1>(0h1))
node _room_T_2 = eq(fill, UInt<2>(0h2))
node _room_T_3 = or(_room_T_1, _room_T_2)
node _room_T_4 = and(queue.io.enq.ready, queue.io.enq.valid)
node _room_T_5 = eq(_room_T_4, UInt<1>(0h0))
node _room_T_6 = and(_room_T_3, _room_T_5)
node _room_T_7 = or(_room_T, _room_T_6)
connect room, _room_T_7
node _T_3 = leq(queue.io.count, UInt<1>(0h1))
node _T_4 = eq(room, _T_3)
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceC.scala:64 assert (room === queue.io.count <= 1.U)\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
regreset busy : UInt<1>, clock, reset, UInt<1>(0h0)
regreset beat : UInt<3>, clock, reset, UInt<3>(0h0)
node _last_T = not(UInt<3>(0h0))
node last = eq(beat, _last_T)
node _req_T = eq(busy, UInt<1>(0h0))
node _req_T_1 = eq(busy, UInt<1>(0h0))
node _req_T_2 = and(_req_T_1, io.req.valid)
reg req_r : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<12>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}, clock
when _req_T_2 :
connect req_r, io.req.bits
node req = mux(_req_T, io.req.bits, req_r)
node _want_data_T = and(io.req.valid, room)
node _want_data_T_1 = and(_want_data_T, io.req.bits.dirty)
node want_data = or(busy, _want_data_T_1)
node _io_req_ready_T = eq(busy, UInt<1>(0h0))
node _io_req_ready_T_1 = and(_io_req_ready_T, room)
connect io.req.ready, _io_req_ready_T_1
connect io.evict_req.set, req.set
connect io.evict_req.way, req.way
node _io_bs_adr_valid_T = orr(beat)
node _io_bs_adr_valid_T_1 = or(_io_bs_adr_valid_T, io.evict_safe)
node _io_bs_adr_valid_T_2 = and(_io_bs_adr_valid_T_1, want_data)
connect io.bs_adr.valid, _io_bs_adr_valid_T_2
connect io.bs_adr.bits.noop, UInt<1>(0h0)
connect io.bs_adr.bits.way, req.way
connect io.bs_adr.bits.set, req.set
connect io.bs_adr.bits.beat, beat
node _io_bs_adr_bits_mask_T = not(UInt<1>(0h0))
connect io.bs_adr.bits.mask, _io_bs_adr_bits_mask_T
node _T_8 = and(io.req.valid, io.req.bits.dirty)
node _T_9 = and(_T_8, room)
node _T_10 = eq(io.evict_safe, UInt<1>(0h0))
node _T_11 = and(_T_9, _T_10)
node _T_12 = eq(io.bs_adr.ready, UInt<1>(0h0))
node _T_13 = and(io.bs_adr.valid, _T_12)
node _T_14 = and(io.req.valid, room)
node _T_15 = and(_T_14, io.req.bits.dirty)
when _T_15 :
connect busy, UInt<1>(0h1)
node _T_16 = and(io.bs_adr.ready, io.bs_adr.valid)
when _T_16 :
node _beat_T = add(beat, UInt<1>(0h1))
node _beat_T_1 = tail(_beat_T, 1)
connect beat, _beat_T_1
when last :
connect busy, UInt<1>(0h0)
connect beat, UInt<1>(0h0)
node _s2_latch_T = and(io.bs_adr.ready, io.bs_adr.valid)
node _s2_latch_T_1 = and(io.req.ready, io.req.valid)
node s2_latch = mux(want_data, _s2_latch_T, _s2_latch_T_1)
reg s2_valid : UInt<1>, clock
connect s2_valid, s2_latch
reg s2_req : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<12>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}, clock
when s2_latch :
connect s2_req, req
reg s2_beat : UInt<3>, clock
when s2_latch :
connect s2_beat, beat
reg s2_last : UInt<1>, clock
when s2_latch :
connect s2_last, last
reg s3_valid : UInt<1>, clock
connect s3_valid, s2_valid
reg s3_req : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<12>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}, clock
when s2_valid :
connect s3_req, s2_req
reg s3_beat : UInt<3>, clock
when s2_valid :
connect s3_beat, s2_beat
reg s3_last : UInt<1>, clock
when s2_valid :
connect s3_last, s2_last
wire c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect c.valid, s3_valid
connect c.bits.opcode, s3_req.opcode
connect c.bits.param, s3_req.param
connect c.bits.size, UInt<3>(0h6)
connect c.bits.source, s3_req.source
node c_bits_address_base_y = or(s3_req.tag, UInt<12>(0h0))
node _c_bits_address_base_T = shr(c_bits_address_base_y, 12)
node _c_bits_address_base_T_1 = eq(_c_bits_address_base_T, UInt<1>(0h0))
node _c_bits_address_base_T_2 = asUInt(reset)
node _c_bits_address_base_T_3 = eq(_c_bits_address_base_T_2, UInt<1>(0h0))
when _c_bits_address_base_T_3 :
node _c_bits_address_base_T_4 = eq(_c_bits_address_base_T_1, UInt<1>(0h0))
when _c_bits_address_base_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : c_bits_address_base_printf
assert(clock, _c_bits_address_base_T_1, UInt<1>(0h1), "") : c_bits_address_base_assert
node _c_bits_address_base_T_5 = bits(c_bits_address_base_y, 11, 0)
node c_bits_address_base_y_1 = or(s3_req.set, UInt<10>(0h0))
node _c_bits_address_base_T_6 = shr(c_bits_address_base_y_1, 10)
node _c_bits_address_base_T_7 = eq(_c_bits_address_base_T_6, UInt<1>(0h0))
node _c_bits_address_base_T_8 = asUInt(reset)
node _c_bits_address_base_T_9 = eq(_c_bits_address_base_T_8, UInt<1>(0h0))
when _c_bits_address_base_T_9 :
node _c_bits_address_base_T_10 = eq(_c_bits_address_base_T_7, UInt<1>(0h0))
when _c_bits_address_base_T_10 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : c_bits_address_base_printf_1
assert(clock, _c_bits_address_base_T_7, UInt<1>(0h1), "") : c_bits_address_base_assert_1
node _c_bits_address_base_T_11 = bits(c_bits_address_base_y_1, 9, 0)
node c_bits_address_base_y_2 = or(UInt<1>(0h0), UInt<6>(0h0))
node _c_bits_address_base_T_12 = shr(c_bits_address_base_y_2, 6)
node _c_bits_address_base_T_13 = eq(_c_bits_address_base_T_12, UInt<1>(0h0))
node _c_bits_address_base_T_14 = asUInt(reset)
node _c_bits_address_base_T_15 = eq(_c_bits_address_base_T_14, UInt<1>(0h0))
when _c_bits_address_base_T_15 :
node _c_bits_address_base_T_16 = eq(_c_bits_address_base_T_13, UInt<1>(0h0))
when _c_bits_address_base_T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : c_bits_address_base_printf_2
assert(clock, _c_bits_address_base_T_13, UInt<1>(0h1), "") : c_bits_address_base_assert_2
node _c_bits_address_base_T_17 = bits(c_bits_address_base_y_2, 5, 0)
node c_bits_address_base_hi = cat(_c_bits_address_base_T_5, _c_bits_address_base_T_11)
node c_bits_address_base = cat(c_bits_address_base_hi, _c_bits_address_base_T_17)
node _c_bits_address_T = bits(c_bits_address_base, 0, 0)
node _c_bits_address_T_1 = bits(c_bits_address_base, 1, 1)
node _c_bits_address_T_2 = bits(c_bits_address_base, 2, 2)
node _c_bits_address_T_3 = bits(c_bits_address_base, 3, 3)
node _c_bits_address_T_4 = bits(c_bits_address_base, 4, 4)
node _c_bits_address_T_5 = bits(c_bits_address_base, 5, 5)
node _c_bits_address_T_6 = bits(c_bits_address_base, 6, 6)
node _c_bits_address_T_7 = bits(c_bits_address_base, 7, 7)
node _c_bits_address_T_8 = bits(c_bits_address_base, 8, 8)
node _c_bits_address_T_9 = bits(c_bits_address_base, 9, 9)
node _c_bits_address_T_10 = bits(c_bits_address_base, 10, 10)
node _c_bits_address_T_11 = bits(c_bits_address_base, 11, 11)
node _c_bits_address_T_12 = bits(c_bits_address_base, 12, 12)
node _c_bits_address_T_13 = bits(c_bits_address_base, 13, 13)
node _c_bits_address_T_14 = bits(c_bits_address_base, 14, 14)
node _c_bits_address_T_15 = bits(c_bits_address_base, 15, 15)
node _c_bits_address_T_16 = bits(c_bits_address_base, 16, 16)
node _c_bits_address_T_17 = bits(c_bits_address_base, 17, 17)
node _c_bits_address_T_18 = bits(c_bits_address_base, 18, 18)
node _c_bits_address_T_19 = bits(c_bits_address_base, 19, 19)
node _c_bits_address_T_20 = bits(c_bits_address_base, 20, 20)
node _c_bits_address_T_21 = bits(c_bits_address_base, 21, 21)
node _c_bits_address_T_22 = bits(c_bits_address_base, 22, 22)
node _c_bits_address_T_23 = bits(c_bits_address_base, 23, 23)
node _c_bits_address_T_24 = bits(c_bits_address_base, 24, 24)
node _c_bits_address_T_25 = bits(c_bits_address_base, 25, 25)
node _c_bits_address_T_26 = bits(c_bits_address_base, 26, 26)
node _c_bits_address_T_27 = bits(c_bits_address_base, 27, 27)
node c_bits_address_lo_lo_lo_lo = cat(_c_bits_address_T_1, _c_bits_address_T)
node c_bits_address_lo_lo_lo_hi = cat(_c_bits_address_T_3, _c_bits_address_T_2)
node c_bits_address_lo_lo_lo = cat(c_bits_address_lo_lo_lo_hi, c_bits_address_lo_lo_lo_lo)
node c_bits_address_lo_lo_hi_lo = cat(_c_bits_address_T_5, _c_bits_address_T_4)
node c_bits_address_lo_lo_hi_hi = cat(_c_bits_address_T_7, _c_bits_address_T_6)
node c_bits_address_lo_lo_hi = cat(c_bits_address_lo_lo_hi_hi, c_bits_address_lo_lo_hi_lo)
node c_bits_address_lo_lo = cat(c_bits_address_lo_lo_hi, c_bits_address_lo_lo_lo)
node c_bits_address_lo_hi_lo_lo = cat(_c_bits_address_T_9, _c_bits_address_T_8)
node c_bits_address_lo_hi_lo_hi = cat(_c_bits_address_T_11, _c_bits_address_T_10)
node c_bits_address_lo_hi_lo = cat(c_bits_address_lo_hi_lo_hi, c_bits_address_lo_hi_lo_lo)
node c_bits_address_lo_hi_hi_lo = cat(_c_bits_address_T_13, _c_bits_address_T_12)
node c_bits_address_lo_hi_hi_hi = cat(_c_bits_address_T_15, _c_bits_address_T_14)
node c_bits_address_lo_hi_hi = cat(c_bits_address_lo_hi_hi_hi, c_bits_address_lo_hi_hi_lo)
node c_bits_address_lo_hi = cat(c_bits_address_lo_hi_hi, c_bits_address_lo_hi_lo)
node c_bits_address_lo = cat(c_bits_address_lo_hi, c_bits_address_lo_lo)
node c_bits_address_hi_lo_lo_lo = cat(_c_bits_address_T_17, _c_bits_address_T_16)
node c_bits_address_hi_lo_lo_hi = cat(_c_bits_address_T_19, _c_bits_address_T_18)
node c_bits_address_hi_lo_lo = cat(c_bits_address_hi_lo_lo_hi, c_bits_address_hi_lo_lo_lo)
node c_bits_address_hi_lo_hi_lo = cat(_c_bits_address_T_21, _c_bits_address_T_20)
node c_bits_address_hi_lo_hi_hi = cat(_c_bits_address_T_23, _c_bits_address_T_22)
node c_bits_address_hi_lo_hi = cat(c_bits_address_hi_lo_hi_hi, c_bits_address_hi_lo_hi_lo)
node c_bits_address_hi_lo = cat(c_bits_address_hi_lo_hi, c_bits_address_hi_lo_lo)
node c_bits_address_hi_hi_lo_lo = cat(_c_bits_address_T_25, _c_bits_address_T_24)
node c_bits_address_hi_hi_lo_hi = cat(_c_bits_address_T_27, _c_bits_address_T_26)
node c_bits_address_hi_hi_lo = cat(c_bits_address_hi_hi_lo_hi, c_bits_address_hi_hi_lo_lo)
node c_bits_address_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0))
node c_bits_address_hi_hi_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0))
node c_bits_address_hi_hi_hi = cat(c_bits_address_hi_hi_hi_hi, c_bits_address_hi_hi_hi_lo)
node c_bits_address_hi_hi = cat(c_bits_address_hi_hi_hi, c_bits_address_hi_hi_lo)
node c_bits_address_hi = cat(c_bits_address_hi_hi, c_bits_address_hi_lo)
node _c_bits_address_T_28 = cat(c_bits_address_hi, c_bits_address_lo)
connect c.bits.address, _c_bits_address_T_28
connect c.bits.data, io.bs_dat.data
connect c.bits.corrupt, UInt<1>(0h0)
node _T_17 = eq(c.valid, UInt<1>(0h0))
node _T_18 = or(_T_17, c.ready)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceC.scala:119 assert(!c.valid || c.ready)\n") : printf_1
assert(clock, _T_18, UInt<1>(0h1), "") : assert_1
node _T_22 = eq(c.ready, UInt<1>(0h0))
connect queue.io.enq, c
connect io.c.bits, queue.io.deq.bits
connect io.c.valid, queue.io.deq.valid
connect queue.io.deq.ready, io.c.ready | module SourceC( // @[SourceC.scala:35:7]
input clock, // @[SourceC.scala:35:7]
input reset, // @[SourceC.scala:35:7]
output io_req_ready, // @[SourceC.scala:37:14]
input io_req_valid, // @[SourceC.scala:37:14]
input [2:0] io_req_bits_opcode, // @[SourceC.scala:37:14]
input [2:0] io_req_bits_param, // @[SourceC.scala:37:14]
input [2:0] io_req_bits_source, // @[SourceC.scala:37:14]
input [11:0] io_req_bits_tag, // @[SourceC.scala:37:14]
input [9:0] io_req_bits_set, // @[SourceC.scala:37:14]
input [2:0] io_req_bits_way, // @[SourceC.scala:37:14]
input io_req_bits_dirty, // @[SourceC.scala:37:14]
input io_c_ready, // @[SourceC.scala:37:14]
output io_c_valid, // @[SourceC.scala:37:14]
output [2:0] io_c_bits_opcode, // @[SourceC.scala:37:14]
output [2:0] io_c_bits_param, // @[SourceC.scala:37:14]
output [2:0] io_c_bits_size, // @[SourceC.scala:37:14]
output [2:0] io_c_bits_source, // @[SourceC.scala:37:14]
output [31:0] io_c_bits_address, // @[SourceC.scala:37:14]
output [63:0] io_c_bits_data, // @[SourceC.scala:37:14]
output io_c_bits_corrupt, // @[SourceC.scala:37:14]
input io_bs_adr_ready, // @[SourceC.scala:37:14]
output io_bs_adr_valid, // @[SourceC.scala:37:14]
output [2:0] io_bs_adr_bits_way, // @[SourceC.scala:37:14]
output [9:0] io_bs_adr_bits_set, // @[SourceC.scala:37:14]
output [2:0] io_bs_adr_bits_beat, // @[SourceC.scala:37:14]
input [63:0] io_bs_dat_data, // @[SourceC.scala:37:14]
output [9:0] io_evict_req_set, // @[SourceC.scala:37:14]
output [2:0] io_evict_req_way, // @[SourceC.scala:37:14]
input io_evict_safe // @[SourceC.scala:37:14]
);
wire _queue_io_enq_ready; // @[SourceC.scala:54:21]
wire _queue_io_deq_valid; // @[SourceC.scala:54:21]
wire [3:0] _queue_io_count; // @[SourceC.scala:54:21]
wire io_req_valid_0 = io_req_valid; // @[SourceC.scala:35:7]
wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceC.scala:35:7]
wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceC.scala:35:7]
wire [2:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceC.scala:35:7]
wire [11:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceC.scala:35:7]
wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceC.scala:35:7]
wire [2:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceC.scala:35:7]
wire io_req_bits_dirty_0 = io_req_bits_dirty; // @[SourceC.scala:35:7]
wire io_c_ready_0 = io_c_ready; // @[SourceC.scala:35:7]
wire io_bs_adr_ready_0 = io_bs_adr_ready; // @[SourceC.scala:35:7]
wire [63:0] io_bs_dat_data_0 = io_bs_dat_data; // @[SourceC.scala:35:7]
wire io_evict_safe_0 = io_evict_safe; // @[SourceC.scala:35:7]
wire _c_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12]
wire _c_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12]
wire _c_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12]
wire io_bs_adr_bits_noop = 1'h0; // @[SourceC.scala:35:7]
wire c_bits_corrupt = 1'h0; // @[SourceC.scala:108:15]
wire _c_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15]
wire _c_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12]
wire _c_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15]
wire _c_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12]
wire _c_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15]
wire _c_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12]
wire io_bs_adr_bits_mask = 1'h1; // @[SourceC.scala:35:7]
wire _io_bs_adr_bits_mask_T = 1'h1; // @[SourceC.scala:82:26]
wire _c_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24]
wire _c_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24]
wire _c_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24]
wire [3:0] c_bits_address_hi_hi_hi = 4'h0; // @[Parameters.scala:230:8]
wire [1:0] c_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8]
wire [1:0] c_bits_address_hi_hi_hi_hi = 2'h0; // @[Parameters.scala:230:8]
wire [5:0] c_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15]
wire [5:0] _c_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6]
wire [2:0] c_bits_size = 3'h6; // @[SourceC.scala:108:15]
wire [2:0] _last_T = 3'h7; // @[SourceC.scala:68:99]
wire [3:0] _fill_T_1 = 4'hF; // @[SourceC.scala:61:48]
wire _io_req_ready_T_1; // @[SourceC.scala:72:25]
wire _io_bs_adr_valid_T_2; // @[SourceC.scala:77:50]
wire [2:0] req_way; // @[SourceC.scala:69:17]
wire [9:0] req_set; // @[SourceC.scala:69:17]
wire [63:0] c_bits_data = io_bs_dat_data_0; // @[SourceC.scala:35:7, :108:15]
wire io_req_ready_0; // @[SourceC.scala:35:7]
wire [2:0] io_c_bits_opcode_0; // @[SourceC.scala:35:7]
wire [2:0] io_c_bits_param_0; // @[SourceC.scala:35:7]
wire [2:0] io_c_bits_size_0; // @[SourceC.scala:35:7]
wire [2:0] io_c_bits_source_0; // @[SourceC.scala:35:7]
wire [31:0] io_c_bits_address_0; // @[SourceC.scala:35:7]
wire [63:0] io_c_bits_data_0; // @[SourceC.scala:35:7]
wire io_c_bits_corrupt_0; // @[SourceC.scala:35:7]
wire io_c_valid_0; // @[SourceC.scala:35:7]
wire [2:0] io_bs_adr_bits_way_0; // @[SourceC.scala:35:7]
wire [9:0] io_bs_adr_bits_set_0; // @[SourceC.scala:35:7]
wire [2:0] io_bs_adr_bits_beat_0; // @[SourceC.scala:35:7]
wire io_bs_adr_valid_0; // @[SourceC.scala:35:7]
wire [9:0] io_evict_req_set_0; // @[SourceC.scala:35:7]
wire [2:0] io_evict_req_way_0; // @[SourceC.scala:35:7]
reg [3:0] fill; // @[SourceC.scala:58:21]
reg room; // @[SourceC.scala:59:21]
wire c_valid; // @[SourceC.scala:108:15]
wire _T = _queue_io_enq_ready & c_valid; // @[Decoupled.scala:51:35]
wire _fill_T; // @[Decoupled.scala:51:35]
assign _fill_T = _T; // @[Decoupled.scala:51:35]
wire _room_T_4; // @[Decoupled.scala:51:35]
assign _room_T_4 = _T; // @[Decoupled.scala:51:35]
wire [3:0] _fill_T_2 = _fill_T ? 4'h1 : 4'hF; // @[Decoupled.scala:51:35]
wire [4:0] _fill_T_3 = {1'h0, fill} + {1'h0, _fill_T_2}; // @[SourceC.scala:58:21, :61:{18,23}]
wire [3:0] _fill_T_4 = _fill_T_3[3:0]; // @[SourceC.scala:61:18]
wire _room_T = fill == 4'h0; // @[SourceC.scala:58:21, :62:18]
wire _room_T_1 = fill == 4'h1; // @[SourceC.scala:58:21, :62:36]
wire _room_T_2 = fill == 4'h2; // @[SourceC.scala:58:21, :62:52]
wire _room_T_3 = _room_T_1 | _room_T_2; // @[SourceC.scala:62:{36,44,52}]
wire _room_T_5 = ~_room_T_4; // @[Decoupled.scala:51:35]
wire _room_T_6 = _room_T_3 & _room_T_5; // @[SourceC.scala:62:{44,61,64}]
wire _room_T_7 = _room_T | _room_T_6; // @[SourceC.scala:62:{18,26,61}]
reg busy; // @[SourceC.scala:66:21]
reg [2:0] beat; // @[SourceC.scala:67:21]
assign io_bs_adr_bits_beat_0 = beat; // @[SourceC.scala:35:7, :67:21]
wire last = &beat; // @[SourceC.scala:67:21, :68:95]
wire _req_T = ~busy; // @[SourceC.scala:66:21, :69:18]
wire _req_T_1 = ~busy; // @[SourceC.scala:66:21, :69:{18,61}]
wire _req_T_2 = _req_T_1 & io_req_valid_0; // @[SourceC.scala:35:7, :69:{61,67}]
reg [2:0] req_r_opcode; // @[SourceC.scala:69:47]
reg [2:0] req_r_param; // @[SourceC.scala:69:47]
reg [2:0] req_r_source; // @[SourceC.scala:69:47]
reg [11:0] req_r_tag; // @[SourceC.scala:69:47]
reg [9:0] req_r_set; // @[SourceC.scala:69:47]
reg [2:0] req_r_way; // @[SourceC.scala:69:47]
reg req_r_dirty; // @[SourceC.scala:69:47]
wire [2:0] req_opcode = _req_T ? io_req_bits_opcode_0 : req_r_opcode; // @[SourceC.scala:35:7, :69:{17,18,47}]
wire [2:0] req_param = _req_T ? io_req_bits_param_0 : req_r_param; // @[SourceC.scala:35:7, :69:{17,18,47}]
wire [2:0] req_source = _req_T ? io_req_bits_source_0 : req_r_source; // @[SourceC.scala:35:7, :69:{17,18,47}]
wire [11:0] req_tag = _req_T ? io_req_bits_tag_0 : req_r_tag; // @[SourceC.scala:35:7, :69:{17,18,47}]
assign req_set = _req_T ? io_req_bits_set_0 : req_r_set; // @[SourceC.scala:35:7, :69:{17,18,47}]
assign req_way = _req_T ? io_req_bits_way_0 : req_r_way; // @[SourceC.scala:35:7, :69:{17,18,47}]
wire req_dirty = _req_T ? io_req_bits_dirty_0 : req_r_dirty; // @[SourceC.scala:35:7, :69:{17,18,47}]
assign io_bs_adr_bits_set_0 = req_set; // @[SourceC.scala:35:7, :69:17]
assign io_evict_req_set_0 = req_set; // @[SourceC.scala:35:7, :69:17]
assign io_bs_adr_bits_way_0 = req_way; // @[SourceC.scala:35:7, :69:17]
assign io_evict_req_way_0 = req_way; // @[SourceC.scala:35:7, :69:17]
wire _want_data_T = io_req_valid_0 & room; // @[SourceC.scala:35:7, :59:21, :70:41]
wire _want_data_T_1 = _want_data_T & io_req_bits_dirty_0; // @[SourceC.scala:35:7, :70:{41,49}]
wire want_data = busy | _want_data_T_1; // @[SourceC.scala:66:21, :70:{24,49}]
wire _io_req_ready_T = ~busy; // @[SourceC.scala:66:21, :69:18, :72:19]
assign _io_req_ready_T_1 = _io_req_ready_T & room; // @[SourceC.scala:59:21, :72:{19,25}]
assign io_req_ready_0 = _io_req_ready_T_1; // @[SourceC.scala:35:7, :72:25]
wire _io_bs_adr_valid_T = |beat; // @[SourceC.scala:67:21, :77:28]
wire _io_bs_adr_valid_T_1 = _io_bs_adr_valid_T | io_evict_safe_0; // @[SourceC.scala:35:7, :77:{28,32}]
assign _io_bs_adr_valid_T_2 = _io_bs_adr_valid_T_1 & want_data; // @[SourceC.scala:70:24, :77:{32,50}]
assign io_bs_adr_valid_0 = _io_bs_adr_valid_T_2; // @[SourceC.scala:35:7, :77:50]
wire _s2_latch_T = io_bs_adr_ready_0 & io_bs_adr_valid_0; // @[Decoupled.scala:51:35]
wire [3:0] _beat_T = {1'h0, beat} + 4'h1; // @[SourceC.scala:67:21, :89:18]
wire [2:0] _beat_T_1 = _beat_T[2:0]; // @[SourceC.scala:89:18]
wire _s2_latch_T_1 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35]
wire s2_latch = want_data ? _s2_latch_T : _s2_latch_T_1; // @[Decoupled.scala:51:35]
reg s2_valid; // @[SourceC.scala:97:25]
reg [2:0] s2_req_opcode; // @[SourceC.scala:98:25]
reg [2:0] s2_req_param; // @[SourceC.scala:98:25]
reg [2:0] s2_req_source; // @[SourceC.scala:98:25]
reg [11:0] s2_req_tag; // @[SourceC.scala:98:25]
reg [9:0] s2_req_set; // @[SourceC.scala:98:25]
reg [2:0] s2_req_way; // @[SourceC.scala:98:25]
reg s2_req_dirty; // @[SourceC.scala:98:25]
reg [2:0] s2_beat; // @[SourceC.scala:99:26]
reg s2_last; // @[SourceC.scala:100:26]
reg s3_valid; // @[SourceC.scala:103:25]
assign c_valid = s3_valid; // @[SourceC.scala:103:25, :108:15]
reg [2:0] s3_req_opcode; // @[SourceC.scala:104:25]
wire [2:0] c_bits_opcode = s3_req_opcode; // @[SourceC.scala:104:25, :108:15]
reg [2:0] s3_req_param; // @[SourceC.scala:104:25]
wire [2:0] c_bits_param = s3_req_param; // @[SourceC.scala:104:25, :108:15]
reg [2:0] s3_req_source; // @[SourceC.scala:104:25]
wire [2:0] c_bits_source = s3_req_source; // @[SourceC.scala:104:25, :108:15]
reg [11:0] s3_req_tag; // @[SourceC.scala:104:25]
wire [11:0] c_bits_address_base_y = s3_req_tag; // @[SourceC.scala:104:25]
reg [9:0] s3_req_set; // @[SourceC.scala:104:25]
wire [9:0] c_bits_address_base_y_1 = s3_req_set; // @[SourceC.scala:104:25]
reg [2:0] s3_req_way; // @[SourceC.scala:104:25]
reg s3_req_dirty; // @[SourceC.scala:104:25]
reg [2:0] s3_beat; // @[SourceC.scala:105:26]
reg s3_last; // @[SourceC.scala:106:26]
wire [31:0] _c_bits_address_T_28; // @[Parameters.scala:230:8]
wire [31:0] c_bits_address; // @[SourceC.scala:108:15]
wire c_ready; // @[SourceC.scala:108:15]
wire [11:0] _c_bits_address_base_T_5 = c_bits_address_base_y; // @[Parameters.scala:221:15, :223:6]
wire _c_bits_address_base_T_3 = ~_c_bits_address_base_T_2; // @[Parameters.scala:222:12]
wire [9:0] _c_bits_address_base_T_11 = c_bits_address_base_y_1; // @[Parameters.scala:221:15, :223:6]
wire _c_bits_address_base_T_9 = ~_c_bits_address_base_T_8; // @[Parameters.scala:222:12]
wire _c_bits_address_base_T_15 = ~_c_bits_address_base_T_14; // @[Parameters.scala:222:12]
wire [21:0] c_bits_address_base_hi = {_c_bits_address_base_T_5, _c_bits_address_base_T_11}; // @[Parameters.scala:223:6, :227:19]
wire [27:0] c_bits_address_base = {c_bits_address_base_hi, 6'h0}; // @[Parameters.scala:227:19]
wire _c_bits_address_T = c_bits_address_base[0]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_1 = c_bits_address_base[1]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_2 = c_bits_address_base[2]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_3 = c_bits_address_base[3]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_4 = c_bits_address_base[4]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_5 = c_bits_address_base[5]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_6 = c_bits_address_base[6]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_7 = c_bits_address_base[7]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_8 = c_bits_address_base[8]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_9 = c_bits_address_base[9]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_10 = c_bits_address_base[10]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_11 = c_bits_address_base[11]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_12 = c_bits_address_base[12]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_13 = c_bits_address_base[13]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_14 = c_bits_address_base[14]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_15 = c_bits_address_base[15]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_16 = c_bits_address_base[16]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_17 = c_bits_address_base[17]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_18 = c_bits_address_base[18]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_19 = c_bits_address_base[19]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_20 = c_bits_address_base[20]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_21 = c_bits_address_base[21]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_22 = c_bits_address_base[22]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_23 = c_bits_address_base[23]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_24 = c_bits_address_base[24]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_25 = c_bits_address_base[25]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_26 = c_bits_address_base[26]; // @[Parameters.scala:227:19, :229:72]
wire _c_bits_address_T_27 = c_bits_address_base[27]; // @[Parameters.scala:227:19, :229:72]
wire [1:0] c_bits_address_lo_lo_lo_lo = {_c_bits_address_T_1, _c_bits_address_T}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] c_bits_address_lo_lo_lo_hi = {_c_bits_address_T_3, _c_bits_address_T_2}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] c_bits_address_lo_lo_lo = {c_bits_address_lo_lo_lo_hi, c_bits_address_lo_lo_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] c_bits_address_lo_lo_hi_lo = {_c_bits_address_T_5, _c_bits_address_T_4}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] c_bits_address_lo_lo_hi_hi = {_c_bits_address_T_7, _c_bits_address_T_6}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] c_bits_address_lo_lo_hi = {c_bits_address_lo_lo_hi_hi, c_bits_address_lo_lo_hi_lo}; // @[Parameters.scala:230:8]
wire [7:0] c_bits_address_lo_lo = {c_bits_address_lo_lo_hi, c_bits_address_lo_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] c_bits_address_lo_hi_lo_lo = {_c_bits_address_T_9, _c_bits_address_T_8}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] c_bits_address_lo_hi_lo_hi = {_c_bits_address_T_11, _c_bits_address_T_10}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] c_bits_address_lo_hi_lo = {c_bits_address_lo_hi_lo_hi, c_bits_address_lo_hi_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] c_bits_address_lo_hi_hi_lo = {_c_bits_address_T_13, _c_bits_address_T_12}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] c_bits_address_lo_hi_hi_hi = {_c_bits_address_T_15, _c_bits_address_T_14}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] c_bits_address_lo_hi_hi = {c_bits_address_lo_hi_hi_hi, c_bits_address_lo_hi_hi_lo}; // @[Parameters.scala:230:8]
wire [7:0] c_bits_address_lo_hi = {c_bits_address_lo_hi_hi, c_bits_address_lo_hi_lo}; // @[Parameters.scala:230:8]
wire [15:0] c_bits_address_lo = {c_bits_address_lo_hi, c_bits_address_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] c_bits_address_hi_lo_lo_lo = {_c_bits_address_T_17, _c_bits_address_T_16}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] c_bits_address_hi_lo_lo_hi = {_c_bits_address_T_19, _c_bits_address_T_18}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] c_bits_address_hi_lo_lo = {c_bits_address_hi_lo_lo_hi, c_bits_address_hi_lo_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] c_bits_address_hi_lo_hi_lo = {_c_bits_address_T_21, _c_bits_address_T_20}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] c_bits_address_hi_lo_hi_hi = {_c_bits_address_T_23, _c_bits_address_T_22}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] c_bits_address_hi_lo_hi = {c_bits_address_hi_lo_hi_hi, c_bits_address_hi_lo_hi_lo}; // @[Parameters.scala:230:8]
wire [7:0] c_bits_address_hi_lo = {c_bits_address_hi_lo_hi, c_bits_address_hi_lo_lo}; // @[Parameters.scala:230:8]
wire [1:0] c_bits_address_hi_hi_lo_lo = {_c_bits_address_T_25, _c_bits_address_T_24}; // @[Parameters.scala:229:72, :230:8]
wire [1:0] c_bits_address_hi_hi_lo_hi = {_c_bits_address_T_27, _c_bits_address_T_26}; // @[Parameters.scala:229:72, :230:8]
wire [3:0] c_bits_address_hi_hi_lo = {c_bits_address_hi_hi_lo_hi, c_bits_address_hi_hi_lo_lo}; // @[Parameters.scala:230:8]
wire [7:0] c_bits_address_hi_hi = {4'h0, c_bits_address_hi_hi_lo}; // @[Parameters.scala:230:8]
wire [15:0] c_bits_address_hi = {c_bits_address_hi_hi, c_bits_address_hi_lo}; // @[Parameters.scala:230:8]
assign _c_bits_address_T_28 = {c_bits_address_hi, c_bits_address_lo}; // @[Parameters.scala:230:8]
assign c_bits_address = _c_bits_address_T_28; // @[SourceC.scala:108:15] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w2_i0_12 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<2>, q : UInt<2>, flip en : UInt<1>}
node _reg_T = asAsyncReset(reset)
regreset reg : UInt<2>, clock, _reg_T, UInt<2>(0h0)
when io.en :
connect reg, io.d
connect io.q, reg | module AsyncResetRegVec_w2_i0_12( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset, // @[AsyncResetReg.scala:56:7]
input [1:0] io_d, // @[AsyncResetReg.scala:59:14]
output [1:0] io_q // @[AsyncResetReg.scala:59:14]
);
wire [1:0] io_d_0 = io_d; // @[AsyncResetReg.scala:56:7]
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire [1:0] io_q_0; // @[AsyncResetReg.scala:56:7]
reg [1:0] reg_0; // @[AsyncResetReg.scala:61:50]
assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29]
if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29]
reg_0 <= 2'h0; // @[AsyncResetReg.scala:61:50]
else // @[AsyncResetReg.scala:56:7]
reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TageTable_9 :
input clock : Clock
input reset : Reset
output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f3_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]}
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<8>, clock, reset, UInt<8>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<8>(0hff))
when _T :
connect doing_reset, UInt<1>(0h0)
node _T_1 = shr(io.f1_req_pc, 4)
node idx_history_hist_chunks_0 = bits(io.f1_req_ghist, 7, 0)
node idx_history_hist_chunks_1 = bits(io.f1_req_ghist, 15, 8)
node idx_history = xor(idx_history_hist_chunks_0, idx_history_hist_chunks_1)
node _idx_T = xor(_T_1, idx_history)
node s1_hashed_idx = bits(_idx_T, 7, 0)
node tag_history_hist_chunks_0 = bits(io.f1_req_ghist, 7, 0)
node tag_history_hist_chunks_1 = bits(io.f1_req_ghist, 15, 8)
node tag_history = xor(tag_history_hist_chunks_0, tag_history_hist_chunks_1)
node _tag_T = shr(_T_1, 8)
node _tag_T_1 = xor(_tag_T, tag_history)
node s1_tag = bits(_tag_T_1, 7, 0)
smem hi_us : UInt<1>[4] [256]
smem lo_us : UInt<1>[4] [256]
smem table : UInt<12>[4] [256]
reg s2_tag : UInt, clock
connect s2_tag, s1_tag
wire _s2_req_rtage_WIRE : UInt<8>
invalidate _s2_req_rtage_WIRE
when io.f1_req_valid :
connect _s2_req_rtage_WIRE, s1_hashed_idx
read mport s2_req_rtage_MPORT = table[_s2_req_rtage_WIRE], clock
wire _s2_req_rtage_WIRE_1 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_2 : UInt<12>
connect _s2_req_rtage_WIRE_2, s2_req_rtage_MPORT[0]
node _s2_req_rtage_T = bits(_s2_req_rtage_WIRE_2, 2, 0)
connect _s2_req_rtage_WIRE_1.ctr, _s2_req_rtage_T
node _s2_req_rtage_T_1 = bits(_s2_req_rtage_WIRE_2, 10, 3)
connect _s2_req_rtage_WIRE_1.tag, _s2_req_rtage_T_1
node _s2_req_rtage_T_2 = bits(_s2_req_rtage_WIRE_2, 11, 11)
connect _s2_req_rtage_WIRE_1.valid, _s2_req_rtage_T_2
wire _s2_req_rtage_WIRE_3 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_4 : UInt<12>
connect _s2_req_rtage_WIRE_4, s2_req_rtage_MPORT[1]
node _s2_req_rtage_T_3 = bits(_s2_req_rtage_WIRE_4, 2, 0)
connect _s2_req_rtage_WIRE_3.ctr, _s2_req_rtage_T_3
node _s2_req_rtage_T_4 = bits(_s2_req_rtage_WIRE_4, 10, 3)
connect _s2_req_rtage_WIRE_3.tag, _s2_req_rtage_T_4
node _s2_req_rtage_T_5 = bits(_s2_req_rtage_WIRE_4, 11, 11)
connect _s2_req_rtage_WIRE_3.valid, _s2_req_rtage_T_5
wire _s2_req_rtage_WIRE_5 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_6 : UInt<12>
connect _s2_req_rtage_WIRE_6, s2_req_rtage_MPORT[2]
node _s2_req_rtage_T_6 = bits(_s2_req_rtage_WIRE_6, 2, 0)
connect _s2_req_rtage_WIRE_5.ctr, _s2_req_rtage_T_6
node _s2_req_rtage_T_7 = bits(_s2_req_rtage_WIRE_6, 10, 3)
connect _s2_req_rtage_WIRE_5.tag, _s2_req_rtage_T_7
node _s2_req_rtage_T_8 = bits(_s2_req_rtage_WIRE_6, 11, 11)
connect _s2_req_rtage_WIRE_5.valid, _s2_req_rtage_T_8
wire _s2_req_rtage_WIRE_7 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_8 : UInt<12>
connect _s2_req_rtage_WIRE_8, s2_req_rtage_MPORT[3]
node _s2_req_rtage_T_9 = bits(_s2_req_rtage_WIRE_8, 2, 0)
connect _s2_req_rtage_WIRE_7.ctr, _s2_req_rtage_T_9
node _s2_req_rtage_T_10 = bits(_s2_req_rtage_WIRE_8, 10, 3)
connect _s2_req_rtage_WIRE_7.tag, _s2_req_rtage_T_10
node _s2_req_rtage_T_11 = bits(_s2_req_rtage_WIRE_8, 11, 11)
connect _s2_req_rtage_WIRE_7.valid, _s2_req_rtage_T_11
wire s2_req_rtage : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4]
connect s2_req_rtage[0].ctr, _s2_req_rtage_WIRE_1.ctr
connect s2_req_rtage[0].tag, _s2_req_rtage_WIRE_1.tag
connect s2_req_rtage[0].valid, _s2_req_rtage_WIRE_1.valid
connect s2_req_rtage[1].ctr, _s2_req_rtage_WIRE_3.ctr
connect s2_req_rtage[1].tag, _s2_req_rtage_WIRE_3.tag
connect s2_req_rtage[1].valid, _s2_req_rtage_WIRE_3.valid
connect s2_req_rtage[2].ctr, _s2_req_rtage_WIRE_5.ctr
connect s2_req_rtage[2].tag, _s2_req_rtage_WIRE_5.tag
connect s2_req_rtage[2].valid, _s2_req_rtage_WIRE_5.valid
connect s2_req_rtage[3].ctr, _s2_req_rtage_WIRE_7.ctr
connect s2_req_rtage[3].tag, _s2_req_rtage_WIRE_7.tag
connect s2_req_rtage[3].valid, _s2_req_rtage_WIRE_7.valid
wire _s2_req_rhius_WIRE : UInt<8>
invalidate _s2_req_rhius_WIRE
when io.f1_req_valid :
connect _s2_req_rhius_WIRE, s1_hashed_idx
read mport s2_req_rhius = hi_us[_s2_req_rhius_WIRE], clock
wire _s2_req_rlous_WIRE : UInt<8>
invalidate _s2_req_rlous_WIRE
when io.f1_req_valid :
connect _s2_req_rlous_WIRE, s1_hashed_idx
read mport s2_req_rlous = lo_us[_s2_req_rlous_WIRE], clock
node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag)
node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T)
node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2)
node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag)
node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4)
node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6)
node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag)
node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8)
node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10)
node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag)
node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12)
node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14)
wire s2_req_rhits : UInt<1>[4]
connect s2_req_rhits[0], _s2_req_rhits_T_3
connect s2_req_rhits[1], _s2_req_rhits_T_7
connect s2_req_rhits[2], _s2_req_rhits_T_11
connect s2_req_rhits[3], _s2_req_rhits_T_15
reg io_f3_resp_0_valid_REG : UInt<1>, clock
connect io_f3_resp_0_valid_REG, s2_req_rhits[0]
connect io.f3_resp[0].valid, io_f3_resp_0_valid_REG
node _io_f3_resp_0_bits_u_T = cat(s2_req_rhius[0], s2_req_rlous[0])
reg io_f3_resp_0_bits_u_REG : UInt, clock
connect io_f3_resp_0_bits_u_REG, _io_f3_resp_0_bits_u_T
connect io.f3_resp[0].bits.u, io_f3_resp_0_bits_u_REG
reg io_f3_resp_0_bits_ctr_REG : UInt, clock
connect io_f3_resp_0_bits_ctr_REG, s2_req_rtage[0].ctr
connect io.f3_resp[0].bits.ctr, io_f3_resp_0_bits_ctr_REG
reg io_f3_resp_1_valid_REG : UInt<1>, clock
connect io_f3_resp_1_valid_REG, s2_req_rhits[1]
connect io.f3_resp[1].valid, io_f3_resp_1_valid_REG
node _io_f3_resp_1_bits_u_T = cat(s2_req_rhius[1], s2_req_rlous[1])
reg io_f3_resp_1_bits_u_REG : UInt, clock
connect io_f3_resp_1_bits_u_REG, _io_f3_resp_1_bits_u_T
connect io.f3_resp[1].bits.u, io_f3_resp_1_bits_u_REG
reg io_f3_resp_1_bits_ctr_REG : UInt, clock
connect io_f3_resp_1_bits_ctr_REG, s2_req_rtage[1].ctr
connect io.f3_resp[1].bits.ctr, io_f3_resp_1_bits_ctr_REG
reg io_f3_resp_2_valid_REG : UInt<1>, clock
connect io_f3_resp_2_valid_REG, s2_req_rhits[2]
connect io.f3_resp[2].valid, io_f3_resp_2_valid_REG
node _io_f3_resp_2_bits_u_T = cat(s2_req_rhius[2], s2_req_rlous[2])
reg io_f3_resp_2_bits_u_REG : UInt, clock
connect io_f3_resp_2_bits_u_REG, _io_f3_resp_2_bits_u_T
connect io.f3_resp[2].bits.u, io_f3_resp_2_bits_u_REG
reg io_f3_resp_2_bits_ctr_REG : UInt, clock
connect io_f3_resp_2_bits_ctr_REG, s2_req_rtage[2].ctr
connect io.f3_resp[2].bits.ctr, io_f3_resp_2_bits_ctr_REG
reg io_f3_resp_3_valid_REG : UInt<1>, clock
connect io_f3_resp_3_valid_REG, s2_req_rhits[3]
connect io.f3_resp[3].valid, io_f3_resp_3_valid_REG
node _io_f3_resp_3_bits_u_T = cat(s2_req_rhius[3], s2_req_rlous[3])
reg io_f3_resp_3_bits_u_REG : UInt, clock
connect io_f3_resp_3_bits_u_REG, _io_f3_resp_3_bits_u_T
connect io.f3_resp[3].bits.u, io_f3_resp_3_bits_u_REG
reg io_f3_resp_3_bits_ctr_REG : UInt, clock
connect io_f3_resp_3_bits_ctr_REG, s2_req_rtage[3].ctr
connect io.f3_resp[3].bits.ctr, io_f3_resp_3_bits_ctr_REG
regreset clear_u_ctr : UInt<20>, clock, reset, UInt<20>(0h0)
when doing_reset :
connect clear_u_ctr, UInt<1>(0h1)
else :
node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1))
node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1)
connect clear_u_ctr, _clear_u_ctr_T_1
node _doing_clear_u_T = bits(clear_u_ctr, 10, 0)
node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0))
node _doing_clear_u_hi_T = bits(clear_u_ctr, 19, 19)
node _doing_clear_u_hi_T_1 = eq(_doing_clear_u_hi_T, UInt<1>(0h1))
node doing_clear_u_hi = and(doing_clear_u, _doing_clear_u_hi_T_1)
node _doing_clear_u_lo_T = bits(clear_u_ctr, 19, 19)
node _doing_clear_u_lo_T_1 = eq(_doing_clear_u_lo_T, UInt<1>(0h0))
node doing_clear_u_lo = and(doing_clear_u, _doing_clear_u_lo_T_1)
node clear_u_idx = shr(clear_u_ctr, 11)
node _T_2 = shr(io.update_pc, 4)
node idx_history_hist_chunks_0_1 = bits(io.update_hist, 7, 0)
node idx_history_hist_chunks_1_1 = bits(io.update_hist, 15, 8)
node idx_history_1 = xor(idx_history_hist_chunks_0_1, idx_history_hist_chunks_1_1)
node _idx_T_1 = xor(_T_2, idx_history_1)
node update_idx = bits(_idx_T_1, 7, 0)
node tag_history_hist_chunks_0_1 = bits(io.update_hist, 7, 0)
node tag_history_hist_chunks_1_1 = bits(io.update_hist, 15, 8)
node tag_history_1 = xor(tag_history_hist_chunks_0_1, tag_history_hist_chunks_1_1)
node _tag_T_2 = shr(_T_2, 8)
node _tag_T_3 = xor(_tag_T_2, tag_history_1)
node update_tag = bits(_tag_T_3, 7, 0)
wire update_wdata : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4]
node _T_3 = mux(doing_reset, reset_idx, update_idx)
wire _WIRE : UInt<12>[4]
connect _WIRE[0], UInt<12>(0h0)
connect _WIRE[1], UInt<12>(0h0)
connect _WIRE[2], UInt<12>(0h0)
connect _WIRE[3], UInt<12>(0h0)
node hi = cat(update_wdata[0].valid, update_wdata[0].tag)
node _T_4 = cat(hi, update_wdata[0].ctr)
node hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag)
node _T_5 = cat(hi_1, update_wdata[1].ctr)
node hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag)
node _T_6 = cat(hi_2, update_wdata[2].ctr)
node hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag)
node _T_7 = cat(hi_3, update_wdata[3].ctr)
wire _WIRE_1 : UInt<12>[4]
connect _WIRE_1[0], _T_4
connect _WIRE_1[1], _T_5
connect _WIRE_1[2], _T_6
connect _WIRE_1[3], _T_7
node _T_8 = mux(doing_reset, _WIRE, _WIRE_1)
node _T_9 = not(UInt<4>(0h0))
node lo = cat(io.update_mask[1], io.update_mask[0])
node hi_4 = cat(io.update_mask[3], io.update_mask[2])
node _T_10 = cat(hi_4, lo)
node _T_11 = mux(doing_reset, _T_9, _T_10)
node _T_12 = bits(_T_11, 0, 0)
node _T_13 = bits(_T_11, 1, 1)
node _T_14 = bits(_T_11, 2, 2)
node _T_15 = bits(_T_11, 3, 3)
write mport MPORT = table[_T_3], clock
when _T_12 :
connect MPORT[0], _T_8[0]
when _T_13 :
connect MPORT[1], _T_8[1]
when _T_14 :
connect MPORT[2], _T_8[2]
when _T_15 :
connect MPORT[3], _T_8[3]
wire update_hi_wdata : UInt<1>[4]
node _T_16 = mux(doing_clear_u_hi, clear_u_idx, update_idx)
node _T_17 = mux(doing_reset, reset_idx, _T_16)
node _T_18 = or(doing_reset, doing_clear_u_hi)
wire _WIRE_2 : UInt<1>[4]
connect _WIRE_2[0], UInt<1>(0h0)
connect _WIRE_2[1], UInt<1>(0h0)
connect _WIRE_2[2], UInt<1>(0h0)
connect _WIRE_2[3], UInt<1>(0h0)
node _T_19 = mux(_T_18, _WIRE_2, update_hi_wdata)
node _T_20 = or(doing_reset, doing_clear_u_hi)
node _T_21 = not(UInt<4>(0h0))
node lo_1 = cat(io.update_u_mask[1], io.update_u_mask[0])
node hi_5 = cat(io.update_u_mask[3], io.update_u_mask[2])
node _T_22 = cat(hi_5, lo_1)
node _T_23 = mux(_T_20, _T_21, _T_22)
node _T_24 = bits(_T_23, 0, 0)
node _T_25 = bits(_T_23, 1, 1)
node _T_26 = bits(_T_23, 2, 2)
node _T_27 = bits(_T_23, 3, 3)
node _T_28 = bits(_T_17, 7, 0)
write mport MPORT_1 = hi_us[_T_28], clock
when _T_24 :
connect MPORT_1[0], _T_19[0]
when _T_25 :
connect MPORT_1[1], _T_19[1]
when _T_26 :
connect MPORT_1[2], _T_19[2]
when _T_27 :
connect MPORT_1[3], _T_19[3]
wire update_lo_wdata : UInt<1>[4]
node _T_29 = mux(doing_clear_u_lo, clear_u_idx, update_idx)
node _T_30 = mux(doing_reset, reset_idx, _T_29)
node _T_31 = or(doing_reset, doing_clear_u_lo)
wire _WIRE_3 : UInt<1>[4]
connect _WIRE_3[0], UInt<1>(0h0)
connect _WIRE_3[1], UInt<1>(0h0)
connect _WIRE_3[2], UInt<1>(0h0)
connect _WIRE_3[3], UInt<1>(0h0)
node _T_32 = mux(_T_31, _WIRE_3, update_lo_wdata)
node _T_33 = or(doing_reset, doing_clear_u_lo)
node _T_34 = not(UInt<4>(0h0))
node lo_2 = cat(io.update_u_mask[1], io.update_u_mask[0])
node hi_6 = cat(io.update_u_mask[3], io.update_u_mask[2])
node _T_35 = cat(hi_6, lo_2)
node _T_36 = mux(_T_33, _T_34, _T_35)
node _T_37 = bits(_T_36, 0, 0)
node _T_38 = bits(_T_36, 1, 1)
node _T_39 = bits(_T_36, 2, 2)
node _T_40 = bits(_T_36, 3, 3)
node _T_41 = bits(_T_30, 7, 0)
write mport MPORT_2 = lo_us[_T_41], clock
when _T_37 :
connect MPORT_2[0], _T_32[0]
when _T_38 :
connect MPORT_2[1], _T_32[1]
when _T_39 :
connect MPORT_2[2], _T_32[2]
when _T_40 :
connect MPORT_2[3], _T_32[3]
reg wrbypass_tags : UInt<8>[2], clock
reg wrbypass_idxs : UInt<8>[2], clock
reg wrbypass : UInt<3>[4][2], clock
regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0)
node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag)
node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1)
node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx)
node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3)
node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag)
node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6)
node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx)
node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8)
wire wrbypass_hits : UInt<1>[2]
connect wrbypass_hits[0], _wrbypass_hits_T_4
connect wrbypass_hits[1], _wrbypass_hits_T_9
node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1])
node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1))
node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1)
node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4)
node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7))
node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1)
node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8)
node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9)
node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1)
node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14)
node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7))
node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1)
node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18)
node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19)
node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20)
node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21)
connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22
connect update_wdata[0].valid, UInt<1>(0h1)
connect update_wdata[0].tag, update_tag
node _update_hi_wdata_0_T = bits(io.update_u[0], 1, 1)
connect update_hi_wdata[0], _update_hi_wdata_0_T
node _update_lo_wdata_0_T = bits(io.update_u[0], 0, 0)
connect update_lo_wdata[0], _update_lo_wdata_0_T
node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1)
node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4)
node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7))
node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1)
node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8)
node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9)
node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1)
node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14)
node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7))
node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1)
node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18)
node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19)
node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20)
node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21)
connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22
connect update_wdata[1].valid, UInt<1>(0h1)
connect update_wdata[1].tag, update_tag
node _update_hi_wdata_1_T = bits(io.update_u[1], 1, 1)
connect update_hi_wdata[1], _update_hi_wdata_1_T
node _update_lo_wdata_1_T = bits(io.update_u[1], 0, 0)
connect update_lo_wdata[1], _update_lo_wdata_1_T
node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1)
node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4)
node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7))
node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1)
node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8)
node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9)
node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1)
node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14)
node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7))
node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1)
node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18)
node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19)
node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20)
node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21)
connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22
connect update_wdata[2].valid, UInt<1>(0h1)
connect update_wdata[2].tag, update_tag
node _update_hi_wdata_2_T = bits(io.update_u[2], 1, 1)
connect update_hi_wdata[2], _update_hi_wdata_2_T
node _update_lo_wdata_2_T = bits(io.update_u[2], 0, 0)
connect update_lo_wdata[2], _update_lo_wdata_2_T
node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1)
node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4)
node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7))
node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1)
node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8)
node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9)
node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1)
node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14)
node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7))
node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1)
node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18)
node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19)
node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20)
node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21)
connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22
connect update_wdata[3].valid, UInt<1>(0h1)
connect update_wdata[3].tag, update_tag
node _update_hi_wdata_3_T = bits(io.update_u[3], 1, 1)
connect update_hi_wdata[3], _update_hi_wdata_3_T
node _update_lo_wdata_3_T = bits(io.update_u[3], 0, 0)
connect update_lo_wdata[3], _update_lo_wdata_3_T
node _T_42 = or(io.update_mask[0], io.update_mask[1])
node _T_43 = or(_T_42, io.update_mask[2])
node _T_44 = or(_T_43, io.update_mask[3])
when _T_44 :
node _T_45 = or(wrbypass_hits[0], wrbypass_hits[1])
when _T_45 :
wire _WIRE_4 : UInt<3>[4]
connect _WIRE_4[0], update_wdata[0].ctr
connect _WIRE_4[1], update_wdata[1].ctr
connect _WIRE_4[2], update_wdata[2].ctr
connect _WIRE_4[3], update_wdata[3].ctr
connect wrbypass[wrbypass_hit_idx], _WIRE_4
else :
wire _WIRE_5 : UInt<3>[4]
connect _WIRE_5[0], update_wdata[0].ctr
connect _WIRE_5[1], update_wdata[1].ctr
connect _WIRE_5[2], update_wdata[2].ctr
connect _WIRE_5[3], update_wdata[3].ctr
connect wrbypass[wrbypass_enq_idx], _WIRE_5
connect wrbypass_tags[wrbypass_enq_idx], update_tag
connect wrbypass_idxs[wrbypass_enq_idx], update_idx
node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1))
node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1)
node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0)
connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2 | module TageTable_9( // @[tage.scala:24:7]
input clock, // @[tage.scala:24:7]
input reset, // @[tage.scala:24:7]
input io_f1_req_valid, // @[tage.scala:31:14]
input [39:0] io_f1_req_pc, // @[tage.scala:31:14]
input [63:0] io_f1_req_ghist, // @[tage.scala:31:14]
output io_f3_resp_0_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_0_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_0_bits_u, // @[tage.scala:31:14]
output io_f3_resp_1_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_1_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_1_bits_u, // @[tage.scala:31:14]
output io_f3_resp_2_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_2_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_2_bits_u, // @[tage.scala:31:14]
output io_f3_resp_3_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_3_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_3_bits_u, // @[tage.scala:31:14]
input io_update_mask_0, // @[tage.scala:31:14]
input io_update_mask_1, // @[tage.scala:31:14]
input io_update_mask_2, // @[tage.scala:31:14]
input io_update_mask_3, // @[tage.scala:31:14]
input io_update_taken_0, // @[tage.scala:31:14]
input io_update_taken_1, // @[tage.scala:31:14]
input io_update_taken_2, // @[tage.scala:31:14]
input io_update_taken_3, // @[tage.scala:31:14]
input io_update_alloc_0, // @[tage.scala:31:14]
input io_update_alloc_1, // @[tage.scala:31:14]
input io_update_alloc_2, // @[tage.scala:31:14]
input io_update_alloc_3, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14]
input [39:0] io_update_pc, // @[tage.scala:31:14]
input [63:0] io_update_hist, // @[tage.scala:31:14]
input io_update_u_mask_0, // @[tage.scala:31:14]
input io_update_u_mask_1, // @[tage.scala:31:14]
input io_update_u_mask_2, // @[tage.scala:31:14]
input io_update_u_mask_3, // @[tage.scala:31:14]
input [1:0] io_update_u_0, // @[tage.scala:31:14]
input [1:0] io_update_u_1, // @[tage.scala:31:14]
input [1:0] io_update_u_2, // @[tage.scala:31:14]
input [1:0] io_update_u_3 // @[tage.scala:31:14]
);
wire lo_us_MPORT_2_data_3; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_2; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_1; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_0; // @[tage.scala:137:8]
wire hi_us_MPORT_1_data_3; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_2; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_1; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_0; // @[tage.scala:130:8]
wire [11:0] table_MPORT_data_3; // @[tage.scala:123:8]
wire [11:0] table_MPORT_data_2; // @[tage.scala:123:8]
wire [11:0] table_MPORT_data_1; // @[tage.scala:123:8]
wire [11:0] table_MPORT_data_0; // @[tage.scala:123:8]
wire _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:87]
wire [47:0] _table_R0_data; // @[tage.scala:91:27]
wire [3:0] _lo_us_R0_data; // @[tage.scala:90:27]
wire [3:0] _hi_us_R0_data; // @[tage.scala:89:27]
wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7]
wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7]
wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7]
wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7]
wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7]
wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7]
wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7]
wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7]
wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7]
wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7]
wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7]
wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7]
wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7]
wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7]
wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7]
wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7]
wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7]
wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7]
wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7]
wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7]
wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7]
wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7]
wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7]
wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7]
wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7]
wire update_wdata_0_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_1_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_2_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_3_valid = 1'h1; // @[tage.scala:119:26]
wire [2:0] io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_0_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_0_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_1_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_1_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_2_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_2_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_3_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_3_valid_0; // @[tage.scala:24:7]
reg doing_reset; // @[tage.scala:72:28]
reg [7:0] reset_idx; // @[tage.scala:73:26]
wire [8:0] _reset_idx_T = {1'h0, reset_idx} + {8'h0, doing_reset}; // @[tage.scala:72:28, :73:26, :74:26]
wire [7:0] _reset_idx_T_1 = _reset_idx_T[7:0]; // @[tage.scala:74:26]
wire [7:0] idx_history_hist_chunks_0 = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [7:0] tag_history_hist_chunks_0 = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [7:0] idx_history_hist_chunks_1 = io_f1_req_ghist_0[15:8]; // @[tage.scala:24:7, :53:11]
wire [7:0] tag_history_hist_chunks_1 = io_f1_req_ghist_0[15:8]; // @[tage.scala:24:7, :53:11]
wire [7:0] idx_history = idx_history_hist_chunks_0 ^ idx_history_hist_chunks_1; // @[tage.scala:53:11, :55:25]
wire [27:0] _tag_T = io_f1_req_pc_0[39:12]; // @[frontend.scala:162:35]
wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[11:4] ^ idx_history}; // @[frontend.scala:162:35]
wire [7:0] s1_hashed_idx = _idx_T[7:0]; // @[tage.scala:60:{29,43}]
wire [7:0] _s2_req_rtage_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :97:40]
wire [7:0] _s2_req_rhius_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :98:32]
wire [7:0] _s2_req_rlous_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :99:32]
wire [7:0] tag_history = tag_history_hist_chunks_0 ^ tag_history_hist_chunks_1; // @[tage.scala:53:11, :55:25]
wire [27:0] _tag_T_1 = {_tag_T[27:8], _tag_T[7:0] ^ tag_history}; // @[tage.scala:55:25, :62:{30,50}]
wire [7:0] s1_tag = _tag_T_1[7:0]; // @[tage.scala:62:{50,64}]
wire [11:0] _s2_req_rtage_WIRE_2 = _table_R0_data[11:0]; // @[tage.scala:91:27, :97:87]
wire [11:0] _s2_req_rtage_WIRE_4 = _table_R0_data[23:12]; // @[tage.scala:91:27, :97:87]
wire [11:0] _s2_req_rtage_WIRE_6 = _table_R0_data[35:24]; // @[tage.scala:91:27, :97:87]
wire [11:0] _s2_req_rtage_WIRE_8 = _table_R0_data[47:36]; // @[tage.scala:91:27, :97:87]
reg [7:0] s2_tag; // @[tage.scala:95:29]
wire _s2_req_rtage_T_2; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_T_1; // @[tage.scala:97:87]
wire s2_req_rtage_0_valid = _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T; // @[tage.scala:97:87]
wire [7:0] s2_req_rtage_0_tag = _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_0_ctr = _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T = _s2_req_rtage_WIRE_2[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_ctr = _s2_req_rtage_T; // @[tage.scala:97:87]
assign _s2_req_rtage_T_1 = _s2_req_rtage_WIRE_2[10:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_tag = _s2_req_rtage_T_1; // @[tage.scala:97:87]
assign _s2_req_rtage_T_2 = _s2_req_rtage_WIRE_2[11]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_valid = _s2_req_rtage_T_2; // @[tage.scala:97:87]
wire _s2_req_rtage_T_5; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_T_4; // @[tage.scala:97:87]
wire s2_req_rtage_1_valid = _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_3; // @[tage.scala:97:87]
wire [7:0] s2_req_rtage_1_tag = _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_1_ctr = _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_3 = _s2_req_rtage_WIRE_4[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_ctr = _s2_req_rtage_T_3; // @[tage.scala:97:87]
assign _s2_req_rtage_T_4 = _s2_req_rtage_WIRE_4[10:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_tag = _s2_req_rtage_T_4; // @[tage.scala:97:87]
assign _s2_req_rtage_T_5 = _s2_req_rtage_WIRE_4[11]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_valid = _s2_req_rtage_T_5; // @[tage.scala:97:87]
wire _s2_req_rtage_T_8; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_T_7; // @[tage.scala:97:87]
wire s2_req_rtage_2_valid = _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_6; // @[tage.scala:97:87]
wire [7:0] s2_req_rtage_2_tag = _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_2_ctr = _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_6 = _s2_req_rtage_WIRE_6[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_ctr = _s2_req_rtage_T_6; // @[tage.scala:97:87]
assign _s2_req_rtage_T_7 = _s2_req_rtage_WIRE_6[10:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_tag = _s2_req_rtage_T_7; // @[tage.scala:97:87]
assign _s2_req_rtage_T_8 = _s2_req_rtage_WIRE_6[11]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_valid = _s2_req_rtage_T_8; // @[tage.scala:97:87]
wire _s2_req_rtage_T_11; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_T_10; // @[tage.scala:97:87]
wire s2_req_rtage_3_valid = _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_9; // @[tage.scala:97:87]
wire [7:0] s2_req_rtage_3_tag = _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_3_ctr = _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_9 = _s2_req_rtage_WIRE_8[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_ctr = _s2_req_rtage_T_9; // @[tage.scala:97:87]
assign _s2_req_rtage_T_10 = _s2_req_rtage_WIRE_8[10:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_tag = _s2_req_rtage_T_10; // @[tage.scala:97:87]
assign _s2_req_rtage_T_11 = _s2_req_rtage_WIRE_8[11]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_valid = _s2_req_rtage_T_11; // @[tage.scala:97:87]
wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}]
reg io_f3_resp_0_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_0_valid_0 = io_f3_resp_0_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_0_bits_u_T = {_hi_us_R0_data[0], _lo_us_R0_data[0]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_0_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_0_bits_u_0 = io_f3_resp_0_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_0_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_0_bits_ctr_0 = io_f3_resp_0_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_1_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_1_valid_0 = io_f3_resp_1_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_1_bits_u_T = {_hi_us_R0_data[1], _lo_us_R0_data[1]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_1_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_1_bits_u_0 = io_f3_resp_1_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_1_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_1_bits_ctr_0 = io_f3_resp_1_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_2_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_2_valid_0 = io_f3_resp_2_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_2_bits_u_T = {_hi_us_R0_data[2], _lo_us_R0_data[2]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_2_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_2_bits_u_0 = io_f3_resp_2_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_2_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_2_bits_ctr_0 = io_f3_resp_2_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_3_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_3_valid_0 = io_f3_resp_3_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_3_bits_u_T = {_hi_us_R0_data[3], _lo_us_R0_data[3]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_3_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_3_bits_u_0 = io_f3_resp_3_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_3_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_3_bits_ctr_0 = io_f3_resp_3_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg [19:0] clear_u_ctr; // @[tage.scala:109:28]
wire [20:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 21'h1; // @[tage.scala:109:28, :110:85]
wire [19:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[19:0]; // @[tage.scala:110:85]
wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34]
wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}]
wire _doing_clear_u_hi_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:54]
wire _doing_clear_u_lo_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:54, :114:54]
wire _doing_clear_u_hi_T_1 = _doing_clear_u_hi_T; // @[tage.scala:113:{54,95}]
wire doing_clear_u_hi = doing_clear_u & _doing_clear_u_hi_T_1; // @[tage.scala:112:61, :113:{40,95}]
wire _doing_clear_u_lo_T_1 = ~_doing_clear_u_lo_T; // @[tage.scala:114:{54,95}]
wire doing_clear_u_lo = doing_clear_u & _doing_clear_u_lo_T_1; // @[tage.scala:112:61, :114:{40,95}]
wire [8:0] clear_u_idx = clear_u_ctr[19:11]; // @[tage.scala:109:28, :115:33]
wire [7:0] idx_history_hist_chunks_0_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [7:0] tag_history_hist_chunks_0_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [7:0] idx_history_hist_chunks_1_1 = io_update_hist_0[15:8]; // @[tage.scala:24:7, :53:11]
wire [7:0] tag_history_hist_chunks_1_1 = io_update_hist_0[15:8]; // @[tage.scala:24:7, :53:11]
wire [7:0] idx_history_1 = idx_history_hist_chunks_0_1 ^ idx_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25]
wire [27:0] _tag_T_2 = io_update_pc_0[39:12]; // @[frontend.scala:162:35]
wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[11:4] ^ idx_history_1}; // @[frontend.scala:162:35]
wire [7:0] update_idx = _idx_T_1[7:0]; // @[tage.scala:60:{29,43}]
wire [7:0] tag_history_1 = tag_history_hist_chunks_0_1 ^ tag_history_hist_chunks_1_1; // @[tage.scala:53:11, :55:25]
wire [27:0] _tag_T_3 = {_tag_T_2[27:8], _tag_T_2[7:0] ^ tag_history_1}; // @[tage.scala:55:25, :62:{30,50}]
wire [7:0] update_tag = _tag_T_3[7:0]; // @[tage.scala:62:{50,64}]
wire [7:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [7:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [7:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [7:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] update_wdata_0_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_1_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_2_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_3_ctr; // @[tage.scala:119:26]
wire [8:0] hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:119:26, :123:102]
wire [8:0] hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:119:26, :123:102]
wire [8:0] hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:119:26, :123:102]
wire [8:0] hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:119:26, :123:102]
assign table_MPORT_data_0 = doing_reset ? 12'h0 : {hi, update_wdata_0_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_1 = doing_reset ? 12'h0 : {hi_1, update_wdata_1_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_2 = doing_reset ? 12'h0 : {hi_2, update_wdata_2_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_3 = doing_reset ? 12'h0 : {hi_3, update_wdata_3_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
wire [1:0] lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :124:90]
wire [1:0] hi_4 = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :124:90]
wire _update_hi_wdata_0_T; // @[tage.scala:166:44]
wire _update_hi_wdata_1_T; // @[tage.scala:166:44]
wire _update_hi_wdata_2_T; // @[tage.scala:166:44]
wire _update_hi_wdata_3_T; // @[tage.scala:166:44]
wire update_hi_wdata_0; // @[tage.scala:127:29]
wire update_hi_wdata_1; // @[tage.scala:127:29]
wire update_hi_wdata_2; // @[tage.scala:127:29]
wire update_hi_wdata_3; // @[tage.scala:127:29]
wire _T_20 = doing_reset | doing_clear_u_hi; // @[tage.scala:72:28, :113:40, :130:21]
assign hi_us_MPORT_1_data_0 = ~_T_20 & update_hi_wdata_0; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_1 = ~_T_20 & update_hi_wdata_1; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_2 = ~_T_20 & update_hi_wdata_2; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_3 = ~_T_20 & update_hi_wdata_3; // @[tage.scala:127:29, :130:{8,21}]
wire [1:0] _GEN = {io_update_u_mask_1_0, io_update_u_mask_0_0}; // @[tage.scala:24:7, :131:80]
wire [1:0] lo_1; // @[tage.scala:131:80]
assign lo_1 = _GEN; // @[tage.scala:131:80]
wire [1:0] lo_2; // @[tage.scala:138:80]
assign lo_2 = _GEN; // @[tage.scala:131:80, :138:80]
wire [1:0] _GEN_0 = {io_update_u_mask_3_0, io_update_u_mask_2_0}; // @[tage.scala:24:7, :131:80]
wire [1:0] hi_5; // @[tage.scala:131:80]
assign hi_5 = _GEN_0; // @[tage.scala:131:80]
wire [1:0] hi_6; // @[tage.scala:138:80]
assign hi_6 = _GEN_0; // @[tage.scala:131:80, :138:80]
wire _update_lo_wdata_0_T; // @[tage.scala:167:44]
wire _update_lo_wdata_1_T; // @[tage.scala:167:44]
wire _update_lo_wdata_2_T; // @[tage.scala:167:44]
wire _update_lo_wdata_3_T; // @[tage.scala:167:44]
wire update_lo_wdata_0; // @[tage.scala:134:29]
wire update_lo_wdata_1; // @[tage.scala:134:29]
wire update_lo_wdata_2; // @[tage.scala:134:29]
wire update_lo_wdata_3; // @[tage.scala:134:29]
wire _T_33 = doing_reset | doing_clear_u_lo; // @[tage.scala:72:28, :114:40, :137:21]
assign lo_us_MPORT_2_data_0 = ~_T_33 & update_lo_wdata_0; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_1 = ~_T_33 & update_lo_wdata_1; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_2 = ~_T_33 & update_lo_wdata_2; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_3 = ~_T_33 & update_lo_wdata_3; // @[tage.scala:134:29, :137:{8,21}]
reg [7:0] wrbypass_tags_0; // @[tage.scala:141:29]
reg [7:0] wrbypass_tags_1; // @[tage.scala:141:29]
reg [7:0] wrbypass_idxs_0; // @[tage.scala:142:29]
reg [7:0] wrbypass_idxs_1; // @[tage.scala:142:29]
reg [2:0] wrbypass_0_0; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_1; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_2; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_3; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_0; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_1; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_2; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_3; // @[tage.scala:143:29]
reg wrbypass_enq_idx; // @[tage.scala:144:33]
wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5]
wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :141:29, :148:22]
wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:147:{5,18}, :148:22]
wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :142:29, :149:22]
wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:147:18, :148:37, :149:22]
wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:146:33, :148:37]
wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5]
wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :141:29, :148:22]
wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:147:{5,18}, :148:22]
wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :142:29, :149:22]
wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:147:18, :148:37, :149:22]
wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:146:33, :148:37]
wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:146:33, :151:48]
wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70]
wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70]
wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70]
wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70]
wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70]
wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_0_T = io_update_u_0_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_0 = _update_hi_wdata_0_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_0_T = io_update_u_0_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_0 = _update_lo_wdata_0_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_1_T = io_update_u_1_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_1 = _update_hi_wdata_1_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_1_T = io_update_u_1_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_1 = _update_lo_wdata_1_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_2_T = io_update_u_2_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_2 = _update_hi_wdata_2_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_2_T = io_update_u_2_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_2 = _update_lo_wdata_2_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_3_T = io_update_u_3_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_3 = _update_hi_wdata_3_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_3_T = io_update_u_3_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_3 = _update_lo_wdata_3_T; // @[tage.scala:134:29, :167:44]
wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14]
wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14]
wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}]
wire _T_44 = io_update_mask_0_0 | io_update_mask_1_0 | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :170:32]
wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70]
wire _GEN_14 = ~_T_44 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39]
wire _GEN_15 = ~_T_44 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39]
always @(posedge clock) begin // @[tage.scala:24:7]
if (reset) begin // @[tage.scala:24:7]
doing_reset <= 1'h1; // @[tage.scala:72:28]
reset_idx <= 8'h0; // @[tage.scala:73:26]
clear_u_ctr <= 20'h0; // @[tage.scala:109:28]
wrbypass_enq_idx <= 1'h0; // @[tage.scala:144:33]
end
else begin // @[tage.scala:24:7]
doing_reset <= reset_idx != 8'hFF & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}]
reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26]
clear_u_ctr <= doing_reset ? 20'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}]
if (~_T_44 | wrbypass_hit) begin // @[tage.scala:143:29, :144:33, :151:48, :170:{32,38}, :171:39]
end
else // @[tage.scala:144:33, :170:38, :171:39]
wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20]
end
s2_tag <= s1_tag; // @[tage.scala:62:64, :95:29]
io_f3_resp_0_valid_REG <= s2_req_rhits_0; // @[tage.scala:100:29, :104:38]
io_f3_resp_0_bits_u_REG <= _io_f3_resp_0_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_0_bits_ctr_REG <= s2_req_rtage_0_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_1_valid_REG <= s2_req_rhits_1; // @[tage.scala:100:29, :104:38]
io_f3_resp_1_bits_u_REG <= _io_f3_resp_1_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_1_bits_ctr_REG <= s2_req_rtage_1_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_2_valid_REG <= s2_req_rhits_2; // @[tage.scala:100:29, :104:38]
io_f3_resp_2_bits_u_REG <= _io_f3_resp_2_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_2_bits_ctr_REG <= s2_req_rtage_2_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_3_valid_REG <= s2_req_rhits_3; // @[tage.scala:100:29, :104:38]
io_f3_resp_3_bits_u_REG <= _io_f3_resp_3_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_3_bits_ctr_REG <= s2_req_rtage_3_ctr; // @[tage.scala:97:29, :106:38]
if (_GEN_14) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39]
end
else // @[tage.scala:141:29, :170:38, :171:39, :175:39]
wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :141:29]
if (_GEN_15) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39]
end
else // @[tage.scala:141:29, :170:38, :171:39, :175:39]
wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :141:29]
if (_GEN_14) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39]
end
else // @[tage.scala:142:29, :170:38, :171:39, :176:39]
wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :142:29]
if (_GEN_15) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39]
end
else // @[tage.scala:142:29, :170:38, :171:39, :176:39]
wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :142:29]
if (~_T_44 | _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39]
end
else begin // @[tage.scala:143:29, :170:38, :171:39]
wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29]
end
if (_T_44 & _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39]
wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29]
end
always @(posedge)
hi_us_8 hi_us ( // @[tage.scala:89:27]
.R0_addr (_s2_req_rhius_WIRE), // @[tage.scala:98:32]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_hi_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_idx[7:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :113:40, :115:33, :129:{8,36}]
.W0_clk (clock),
.W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}), // @[tage.scala:89:27, :130:8]
.W0_mask (_T_20 ? 4'hF : {hi_5, lo_1}) // @[tage.scala:130:21, :131:{8,80}]
); // @[tage.scala:89:27]
lo_us_8 lo_us ( // @[tage.scala:90:27]
.R0_addr (_s2_req_rlous_WIRE), // @[tage.scala:99:32]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_lo_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_idx[7:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :114:40, :115:33, :136:{8,36}]
.W0_clk (clock),
.W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}), // @[tage.scala:90:27, :137:8]
.W0_mask (_T_33 ? 4'hF : {hi_6, lo_2}) // @[tage.scala:137:21, :138:{8,80}]
); // @[tage.scala:90:27]
table_8 table_0 ( // @[tage.scala:91:27]
.R0_addr (_s2_req_rtage_WIRE), // @[tage.scala:97:40]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_table_R0_data),
.W0_addr (doing_reset ? reset_idx : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :122:8]
.W0_clk (clock),
.W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}), // @[tage.scala:91:27, :123:8]
.W0_mask (doing_reset ? 4'hF : {hi_4, lo}) // @[tage.scala:72:28, :124:{8,90}]
); // @[tage.scala:91:27]
assign io_f3_resp_0_valid = io_f3_resp_0_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_1_valid = io_f3_resp_1_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_2_valid = io_f3_resp_2_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_3_valid = io_f3_resp_3_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_0; // @[tage.scala:24:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_152 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_408
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_152( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_408 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_93 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_153
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_93( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_153 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue :
input clock : Clock
input reset : Reset
output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>}
cmem ram : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>} [16]
wire _valids_WIRE : UInt<1>[16]
connect _valids_WIRE[0], UInt<1>(0h0)
connect _valids_WIRE[1], UInt<1>(0h0)
connect _valids_WIRE[2], UInt<1>(0h0)
connect _valids_WIRE[3], UInt<1>(0h0)
connect _valids_WIRE[4], UInt<1>(0h0)
connect _valids_WIRE[5], UInt<1>(0h0)
connect _valids_WIRE[6], UInt<1>(0h0)
connect _valids_WIRE[7], UInt<1>(0h0)
connect _valids_WIRE[8], UInt<1>(0h0)
connect _valids_WIRE[9], UInt<1>(0h0)
connect _valids_WIRE[10], UInt<1>(0h0)
connect _valids_WIRE[11], UInt<1>(0h0)
connect _valids_WIRE[12], UInt<1>(0h0)
connect _valids_WIRE[13], UInt<1>(0h0)
connect _valids_WIRE[14], UInt<1>(0h0)
connect _valids_WIRE[15], UInt<1>(0h0)
regreset valids : UInt<1>[16], clock, reset, _valids_WIRE
reg uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[16], clock
regreset enq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0)
regreset deq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0)
regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0)
node ptr_match = eq(enq_ptr_value, deq_ptr_value)
node _io_empty_T = eq(maybe_full, UInt<1>(0h0))
node _io_empty_T_1 = and(ptr_match, _io_empty_T)
connect io.empty, _io_empty_T_1
node full = and(ptr_match, maybe_full)
node _do_enq_T = and(io.enq.ready, io.enq.valid)
wire do_enq : UInt<1>
connect do_enq, _do_enq_T
node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0))
node _do_deq_T_1 = or(io.deq.ready, _do_deq_T)
node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0))
node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2)
wire do_deq : UInt<1>
connect do_deq, _do_deq_T_3
node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask)
node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0))
node _valids_0_T_2 = eq(_valids_0_T_1, UInt<1>(0h0))
node _valids_0_T_3 = and(valids[0], _valids_0_T_2)
node _valids_0_T_4 = and(io.flush, uops[0].uses_ldq)
node _valids_0_T_5 = eq(_valids_0_T_4, UInt<1>(0h0))
node _valids_0_T_6 = and(_valids_0_T_3, _valids_0_T_5)
connect valids[0], _valids_0_T_6
when valids[0] :
node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T)
connect uops[0].br_mask, _uops_0_br_mask_T_1
node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask)
node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0))
node _valids_1_T_2 = eq(_valids_1_T_1, UInt<1>(0h0))
node _valids_1_T_3 = and(valids[1], _valids_1_T_2)
node _valids_1_T_4 = and(io.flush, uops[1].uses_ldq)
node _valids_1_T_5 = eq(_valids_1_T_4, UInt<1>(0h0))
node _valids_1_T_6 = and(_valids_1_T_3, _valids_1_T_5)
connect valids[1], _valids_1_T_6
when valids[1] :
node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T)
connect uops[1].br_mask, _uops_1_br_mask_T_1
node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask)
node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0))
node _valids_2_T_2 = eq(_valids_2_T_1, UInt<1>(0h0))
node _valids_2_T_3 = and(valids[2], _valids_2_T_2)
node _valids_2_T_4 = and(io.flush, uops[2].uses_ldq)
node _valids_2_T_5 = eq(_valids_2_T_4, UInt<1>(0h0))
node _valids_2_T_6 = and(_valids_2_T_3, _valids_2_T_5)
connect valids[2], _valids_2_T_6
when valids[2] :
node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T)
connect uops[2].br_mask, _uops_2_br_mask_T_1
node _valids_3_T = and(io.brupdate.b1.mispredict_mask, uops[3].br_mask)
node _valids_3_T_1 = neq(_valids_3_T, UInt<1>(0h0))
node _valids_3_T_2 = eq(_valids_3_T_1, UInt<1>(0h0))
node _valids_3_T_3 = and(valids[3], _valids_3_T_2)
node _valids_3_T_4 = and(io.flush, uops[3].uses_ldq)
node _valids_3_T_5 = eq(_valids_3_T_4, UInt<1>(0h0))
node _valids_3_T_6 = and(_valids_3_T_3, _valids_3_T_5)
connect valids[3], _valids_3_T_6
when valids[3] :
node _uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_3_br_mask_T_1 = and(uops[3].br_mask, _uops_3_br_mask_T)
connect uops[3].br_mask, _uops_3_br_mask_T_1
node _valids_4_T = and(io.brupdate.b1.mispredict_mask, uops[4].br_mask)
node _valids_4_T_1 = neq(_valids_4_T, UInt<1>(0h0))
node _valids_4_T_2 = eq(_valids_4_T_1, UInt<1>(0h0))
node _valids_4_T_3 = and(valids[4], _valids_4_T_2)
node _valids_4_T_4 = and(io.flush, uops[4].uses_ldq)
node _valids_4_T_5 = eq(_valids_4_T_4, UInt<1>(0h0))
node _valids_4_T_6 = and(_valids_4_T_3, _valids_4_T_5)
connect valids[4], _valids_4_T_6
when valids[4] :
node _uops_4_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_4_br_mask_T_1 = and(uops[4].br_mask, _uops_4_br_mask_T)
connect uops[4].br_mask, _uops_4_br_mask_T_1
node _valids_5_T = and(io.brupdate.b1.mispredict_mask, uops[5].br_mask)
node _valids_5_T_1 = neq(_valids_5_T, UInt<1>(0h0))
node _valids_5_T_2 = eq(_valids_5_T_1, UInt<1>(0h0))
node _valids_5_T_3 = and(valids[5], _valids_5_T_2)
node _valids_5_T_4 = and(io.flush, uops[5].uses_ldq)
node _valids_5_T_5 = eq(_valids_5_T_4, UInt<1>(0h0))
node _valids_5_T_6 = and(_valids_5_T_3, _valids_5_T_5)
connect valids[5], _valids_5_T_6
when valids[5] :
node _uops_5_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_5_br_mask_T_1 = and(uops[5].br_mask, _uops_5_br_mask_T)
connect uops[5].br_mask, _uops_5_br_mask_T_1
node _valids_6_T = and(io.brupdate.b1.mispredict_mask, uops[6].br_mask)
node _valids_6_T_1 = neq(_valids_6_T, UInt<1>(0h0))
node _valids_6_T_2 = eq(_valids_6_T_1, UInt<1>(0h0))
node _valids_6_T_3 = and(valids[6], _valids_6_T_2)
node _valids_6_T_4 = and(io.flush, uops[6].uses_ldq)
node _valids_6_T_5 = eq(_valids_6_T_4, UInt<1>(0h0))
node _valids_6_T_6 = and(_valids_6_T_3, _valids_6_T_5)
connect valids[6], _valids_6_T_6
when valids[6] :
node _uops_6_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_6_br_mask_T_1 = and(uops[6].br_mask, _uops_6_br_mask_T)
connect uops[6].br_mask, _uops_6_br_mask_T_1
node _valids_7_T = and(io.brupdate.b1.mispredict_mask, uops[7].br_mask)
node _valids_7_T_1 = neq(_valids_7_T, UInt<1>(0h0))
node _valids_7_T_2 = eq(_valids_7_T_1, UInt<1>(0h0))
node _valids_7_T_3 = and(valids[7], _valids_7_T_2)
node _valids_7_T_4 = and(io.flush, uops[7].uses_ldq)
node _valids_7_T_5 = eq(_valids_7_T_4, UInt<1>(0h0))
node _valids_7_T_6 = and(_valids_7_T_3, _valids_7_T_5)
connect valids[7], _valids_7_T_6
when valids[7] :
node _uops_7_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_7_br_mask_T_1 = and(uops[7].br_mask, _uops_7_br_mask_T)
connect uops[7].br_mask, _uops_7_br_mask_T_1
node _valids_8_T = and(io.brupdate.b1.mispredict_mask, uops[8].br_mask)
node _valids_8_T_1 = neq(_valids_8_T, UInt<1>(0h0))
node _valids_8_T_2 = eq(_valids_8_T_1, UInt<1>(0h0))
node _valids_8_T_3 = and(valids[8], _valids_8_T_2)
node _valids_8_T_4 = and(io.flush, uops[8].uses_ldq)
node _valids_8_T_5 = eq(_valids_8_T_4, UInt<1>(0h0))
node _valids_8_T_6 = and(_valids_8_T_3, _valids_8_T_5)
connect valids[8], _valids_8_T_6
when valids[8] :
node _uops_8_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_8_br_mask_T_1 = and(uops[8].br_mask, _uops_8_br_mask_T)
connect uops[8].br_mask, _uops_8_br_mask_T_1
node _valids_9_T = and(io.brupdate.b1.mispredict_mask, uops[9].br_mask)
node _valids_9_T_1 = neq(_valids_9_T, UInt<1>(0h0))
node _valids_9_T_2 = eq(_valids_9_T_1, UInt<1>(0h0))
node _valids_9_T_3 = and(valids[9], _valids_9_T_2)
node _valids_9_T_4 = and(io.flush, uops[9].uses_ldq)
node _valids_9_T_5 = eq(_valids_9_T_4, UInt<1>(0h0))
node _valids_9_T_6 = and(_valids_9_T_3, _valids_9_T_5)
connect valids[9], _valids_9_T_6
when valids[9] :
node _uops_9_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_9_br_mask_T_1 = and(uops[9].br_mask, _uops_9_br_mask_T)
connect uops[9].br_mask, _uops_9_br_mask_T_1
node _valids_10_T = and(io.brupdate.b1.mispredict_mask, uops[10].br_mask)
node _valids_10_T_1 = neq(_valids_10_T, UInt<1>(0h0))
node _valids_10_T_2 = eq(_valids_10_T_1, UInt<1>(0h0))
node _valids_10_T_3 = and(valids[10], _valids_10_T_2)
node _valids_10_T_4 = and(io.flush, uops[10].uses_ldq)
node _valids_10_T_5 = eq(_valids_10_T_4, UInt<1>(0h0))
node _valids_10_T_6 = and(_valids_10_T_3, _valids_10_T_5)
connect valids[10], _valids_10_T_6
when valids[10] :
node _uops_10_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_10_br_mask_T_1 = and(uops[10].br_mask, _uops_10_br_mask_T)
connect uops[10].br_mask, _uops_10_br_mask_T_1
node _valids_11_T = and(io.brupdate.b1.mispredict_mask, uops[11].br_mask)
node _valids_11_T_1 = neq(_valids_11_T, UInt<1>(0h0))
node _valids_11_T_2 = eq(_valids_11_T_1, UInt<1>(0h0))
node _valids_11_T_3 = and(valids[11], _valids_11_T_2)
node _valids_11_T_4 = and(io.flush, uops[11].uses_ldq)
node _valids_11_T_5 = eq(_valids_11_T_4, UInt<1>(0h0))
node _valids_11_T_6 = and(_valids_11_T_3, _valids_11_T_5)
connect valids[11], _valids_11_T_6
when valids[11] :
node _uops_11_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_11_br_mask_T_1 = and(uops[11].br_mask, _uops_11_br_mask_T)
connect uops[11].br_mask, _uops_11_br_mask_T_1
node _valids_12_T = and(io.brupdate.b1.mispredict_mask, uops[12].br_mask)
node _valids_12_T_1 = neq(_valids_12_T, UInt<1>(0h0))
node _valids_12_T_2 = eq(_valids_12_T_1, UInt<1>(0h0))
node _valids_12_T_3 = and(valids[12], _valids_12_T_2)
node _valids_12_T_4 = and(io.flush, uops[12].uses_ldq)
node _valids_12_T_5 = eq(_valids_12_T_4, UInt<1>(0h0))
node _valids_12_T_6 = and(_valids_12_T_3, _valids_12_T_5)
connect valids[12], _valids_12_T_6
when valids[12] :
node _uops_12_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_12_br_mask_T_1 = and(uops[12].br_mask, _uops_12_br_mask_T)
connect uops[12].br_mask, _uops_12_br_mask_T_1
node _valids_13_T = and(io.brupdate.b1.mispredict_mask, uops[13].br_mask)
node _valids_13_T_1 = neq(_valids_13_T, UInt<1>(0h0))
node _valids_13_T_2 = eq(_valids_13_T_1, UInt<1>(0h0))
node _valids_13_T_3 = and(valids[13], _valids_13_T_2)
node _valids_13_T_4 = and(io.flush, uops[13].uses_ldq)
node _valids_13_T_5 = eq(_valids_13_T_4, UInt<1>(0h0))
node _valids_13_T_6 = and(_valids_13_T_3, _valids_13_T_5)
connect valids[13], _valids_13_T_6
when valids[13] :
node _uops_13_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_13_br_mask_T_1 = and(uops[13].br_mask, _uops_13_br_mask_T)
connect uops[13].br_mask, _uops_13_br_mask_T_1
node _valids_14_T = and(io.brupdate.b1.mispredict_mask, uops[14].br_mask)
node _valids_14_T_1 = neq(_valids_14_T, UInt<1>(0h0))
node _valids_14_T_2 = eq(_valids_14_T_1, UInt<1>(0h0))
node _valids_14_T_3 = and(valids[14], _valids_14_T_2)
node _valids_14_T_4 = and(io.flush, uops[14].uses_ldq)
node _valids_14_T_5 = eq(_valids_14_T_4, UInt<1>(0h0))
node _valids_14_T_6 = and(_valids_14_T_3, _valids_14_T_5)
connect valids[14], _valids_14_T_6
when valids[14] :
node _uops_14_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_14_br_mask_T_1 = and(uops[14].br_mask, _uops_14_br_mask_T)
connect uops[14].br_mask, _uops_14_br_mask_T_1
node _valids_15_T = and(io.brupdate.b1.mispredict_mask, uops[15].br_mask)
node _valids_15_T_1 = neq(_valids_15_T, UInt<1>(0h0))
node _valids_15_T_2 = eq(_valids_15_T_1, UInt<1>(0h0))
node _valids_15_T_3 = and(valids[15], _valids_15_T_2)
node _valids_15_T_4 = and(io.flush, uops[15].uses_ldq)
node _valids_15_T_5 = eq(_valids_15_T_4, UInt<1>(0h0))
node _valids_15_T_6 = and(_valids_15_T_3, _valids_15_T_5)
connect valids[15], _valids_15_T_6
when valids[15] :
node _uops_15_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_15_br_mask_T_1 = and(uops[15].br_mask, _uops_15_br_mask_T)
connect uops[15].br_mask, _uops_15_br_mask_T_1
when do_enq :
infer mport MPORT = ram[enq_ptr_value], clock
connect MPORT, io.enq.bits
connect valids[enq_ptr_value], UInt<1>(0h1)
connect uops[enq_ptr_value], io.enq.bits.uop
node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T)
connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1
node wrap = eq(enq_ptr_value, UInt<4>(0hf))
node _value_T = add(enq_ptr_value, UInt<1>(0h1))
node _value_T_1 = tail(_value_T, 1)
connect enq_ptr_value, _value_T_1
when do_deq :
connect valids[deq_ptr_value], UInt<1>(0h0)
node wrap_1 = eq(deq_ptr_value, UInt<4>(0hf))
node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1))
node _value_T_3 = tail(_value_T_2, 1)
connect deq_ptr_value, _value_T_3
node _T = neq(do_enq, do_deq)
when _T :
connect maybe_full, do_enq
node _io_enq_ready_T = eq(full, UInt<1>(0h0))
connect io.enq.ready, _io_enq_ready_T
wire out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}
infer mport out_MPORT = ram[deq_ptr_value], clock
connect out, out_MPORT
connect out.uop, uops[deq_ptr_value]
node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0))
node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value])
node _io_deq_valid_T_2 = and(io.brupdate.b1.mispredict_mask, out.uop.br_mask)
node _io_deq_valid_T_3 = neq(_io_deq_valid_T_2, UInt<1>(0h0))
node _io_deq_valid_T_4 = eq(_io_deq_valid_T_3, UInt<1>(0h0))
node _io_deq_valid_T_5 = and(_io_deq_valid_T_1, _io_deq_valid_T_4)
node _io_deq_valid_T_6 = and(io.flush, out.uop.uses_ldq)
node _io_deq_valid_T_7 = eq(_io_deq_valid_T_6, UInt<1>(0h0))
node _io_deq_valid_T_8 = and(_io_deq_valid_T_5, _io_deq_valid_T_7)
connect io.deq.valid, _io_deq_valid_T_8
connect io.deq.bits, out
node _io_deq_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _io_deq_bits_uop_br_mask_T_1 = and(out.uop.br_mask, _io_deq_bits_uop_br_mask_T)
connect io.deq.bits.uop.br_mask, _io_deq_bits_uop_br_mask_T_1
node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value)
node ptr_diff = tail(_ptr_diff_T, 1)
node _io_count_T = and(maybe_full, ptr_match)
node _io_count_T_1 = cat(_io_count_T, ptr_diff)
connect io.count, _io_count_T_1 | module BranchKillableQueue( // @[util.scala:448:7]
input clock, // @[util.scala:448:7]
input reset, // @[util.scala:448:7]
output io_enq_ready, // @[util.scala:453:14]
input io_enq_valid, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_uopc, // @[util.scala:453:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:453:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:453:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:453:14]
input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_iq_type, // @[util.scala:453:14]
input [9:0] io_enq_bits_uop_fu_code, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ctrl_br_type, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_load, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_sta, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_std, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_iw_state, // @[util.scala:453:14]
input io_enq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14]
input io_enq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14]
input io_enq_bits_uop_is_br, // @[util.scala:453:14]
input io_enq_bits_uop_is_jalr, // @[util.scala:453:14]
input io_enq_bits_uop_is_jal, // @[util.scala:453:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:453:14]
input [15:0] io_enq_bits_uop_br_mask, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:453:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:453:14]
input io_enq_bits_uop_taken, // @[util.scala:453:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:453:14]
input [11:0] io_enq_bits_uop_csr_addr, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_rob_idx, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_ldq_idx, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_stq_idx, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_pdst, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_prs1, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_prs2, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_prs3, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_ppred, // @[util.scala:453:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:453:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:453:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:453:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:453:14]
input io_enq_bits_uop_exception, // @[util.scala:453:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:453:14]
input io_enq_bits_uop_bypassable, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:453:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:453:14]
input io_enq_bits_uop_is_fence, // @[util.scala:453:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:453:14]
input io_enq_bits_uop_is_amo, // @[util.scala:453:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:453:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:453:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14]
input io_enq_bits_uop_is_unique, // @[util.scala:453:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:453:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:453:14]
input io_enq_bits_uop_ldst_val, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:453:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:453:14]
input io_enq_bits_uop_fp_val, // @[util.scala:453:14]
input io_enq_bits_uop_fp_single, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:453:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:453:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:453:14]
input [39:0] io_enq_bits_addr, // @[util.scala:453:14]
input [63:0] io_enq_bits_data, // @[util.scala:453:14]
input io_enq_bits_is_hella, // @[util.scala:453:14]
input io_enq_bits_tag_match, // @[util.scala:453:14]
input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:453:14]
input [19:0] io_enq_bits_old_meta_tag, // @[util.scala:453:14]
input [7:0] io_enq_bits_way_en, // @[util.scala:453:14]
input [4:0] io_enq_bits_sdq_id, // @[util.scala:453:14]
input io_deq_ready, // @[util.scala:453:14]
output io_deq_valid, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_uopc, // @[util.scala:453:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:453:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:453:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:453:14]
output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_iq_type, // @[util.scala:453:14]
output [9:0] io_deq_bits_uop_fu_code, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ctrl_br_type, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_load, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_sta, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_std, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_iw_state, // @[util.scala:453:14]
output io_deq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14]
output io_deq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14]
output io_deq_bits_uop_is_br, // @[util.scala:453:14]
output io_deq_bits_uop_is_jalr, // @[util.scala:453:14]
output io_deq_bits_uop_is_jal, // @[util.scala:453:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:453:14]
output [15:0] io_deq_bits_uop_br_mask, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:453:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:453:14]
output io_deq_bits_uop_taken, // @[util.scala:453:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:453:14]
output [11:0] io_deq_bits_uop_csr_addr, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_rob_idx, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_ldq_idx, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_stq_idx, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_pdst, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_prs1, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_prs2, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_prs3, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_ppred, // @[util.scala:453:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:453:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:453:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:453:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:453:14]
output io_deq_bits_uop_exception, // @[util.scala:453:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:453:14]
output io_deq_bits_uop_bypassable, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:453:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:453:14]
output io_deq_bits_uop_is_fence, // @[util.scala:453:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:453:14]
output io_deq_bits_uop_is_amo, // @[util.scala:453:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:453:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:453:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14]
output io_deq_bits_uop_is_unique, // @[util.scala:453:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:453:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:453:14]
output io_deq_bits_uop_ldst_val, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:453:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:453:14]
output io_deq_bits_uop_fp_val, // @[util.scala:453:14]
output io_deq_bits_uop_fp_single, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:453:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:453:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:453:14]
output [39:0] io_deq_bits_addr, // @[util.scala:453:14]
output [63:0] io_deq_bits_data, // @[util.scala:453:14]
output io_deq_bits_is_hella, // @[util.scala:453:14]
output io_deq_bits_tag_match, // @[util.scala:453:14]
output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:453:14]
output [19:0] io_deq_bits_old_meta_tag, // @[util.scala:453:14]
output [4:0] io_deq_bits_sdq_id, // @[util.scala:453:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[util.scala:453:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[util.scala:453:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[util.scala:453:14]
input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:453:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_rvc, // @[util.scala:453:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[util.scala:453:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[util.scala:453:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[util.scala:453:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[util.scala:453:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[util.scala:453:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[util.scala:453:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[util.scala:453:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[util.scala:453:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[util.scala:453:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_br, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_jalr, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_jal, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_sfb, // @[util.scala:453:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[util.scala:453:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:453:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:453:14]
input io_brupdate_b2_uop_edge_inst, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:453:14]
input io_brupdate_b2_uop_taken, // @[util.scala:453:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:453:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[util.scala:453:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:453:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:453:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:453:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:453:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:453:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:453:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:453:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:453:14]
input io_brupdate_b2_uop_prs1_busy, // @[util.scala:453:14]
input io_brupdate_b2_uop_prs2_busy, // @[util.scala:453:14]
input io_brupdate_b2_uop_prs3_busy, // @[util.scala:453:14]
input io_brupdate_b2_uop_ppred_busy, // @[util.scala:453:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:453:14]
input io_brupdate_b2_uop_exception, // @[util.scala:453:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:453:14]
input io_brupdate_b2_uop_bypassable, // @[util.scala:453:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:453:14]
input io_brupdate_b2_uop_mem_signed, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_fence, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_fencei, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_amo, // @[util.scala:453:14]
input io_brupdate_b2_uop_uses_ldq, // @[util.scala:453:14]
input io_brupdate_b2_uop_uses_stq, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:453:14]
input io_brupdate_b2_uop_is_unique, // @[util.scala:453:14]
input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:453:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:453:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:453:14]
input io_brupdate_b2_uop_ldst_val, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:453:14]
input io_brupdate_b2_uop_frs3_en, // @[util.scala:453:14]
input io_brupdate_b2_uop_fp_val, // @[util.scala:453:14]
input io_brupdate_b2_uop_fp_single, // @[util.scala:453:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:453:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:453:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:453:14]
input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:453:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:453:14]
input io_brupdate_b2_valid, // @[util.scala:453:14]
input io_brupdate_b2_mispredict, // @[util.scala:453:14]
input io_brupdate_b2_taken, // @[util.scala:453:14]
input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:453:14]
input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:453:14]
input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:453:14]
input [20:0] io_brupdate_b2_target_offset, // @[util.scala:453:14]
input io_flush, // @[util.scala:453:14]
output io_empty // @[util.scala:453:14]
);
wire [140:0] _ram_ext_R0_data; // @[util.scala:464:20]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_uopc_0 = io_enq_bits_uop_uopc; // @[util.scala:448:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:448:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:448:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:448:7]
wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_iq_type_0 = io_enq_bits_uop_iq_type; // @[util.scala:448:7]
wire [9:0] io_enq_bits_uop_fu_code_0 = io_enq_bits_uop_fu_code; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ctrl_br_type_0 = io_enq_bits_uop_ctrl_br_type; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_ctrl_op1_sel_0 = io_enq_bits_uop_ctrl_op1_sel; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_op2_sel_0 = io_enq_bits_uop_ctrl_op2_sel; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_imm_sel_0 = io_enq_bits_uop_ctrl_imm_sel; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_ctrl_op_fcn_0 = io_enq_bits_uop_ctrl_op_fcn; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_fcn_dw_0 = io_enq_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_csr_cmd_0 = io_enq_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_load_0 = io_enq_bits_uop_ctrl_is_load; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_sta_0 = io_enq_bits_uop_ctrl_is_sta; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_std_0 = io_enq_bits_uop_ctrl_is_std; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_iw_state_0 = io_enq_bits_uop_iw_state; // @[util.scala:448:7]
wire io_enq_bits_uop_iw_p1_poisoned_0 = io_enq_bits_uop_iw_p1_poisoned; // @[util.scala:448:7]
wire io_enq_bits_uop_iw_p2_poisoned_0 = io_enq_bits_uop_iw_p2_poisoned; // @[util.scala:448:7]
wire io_enq_bits_uop_is_br_0 = io_enq_bits_uop_is_br; // @[util.scala:448:7]
wire io_enq_bits_uop_is_jalr_0 = io_enq_bits_uop_is_jalr; // @[util.scala:448:7]
wire io_enq_bits_uop_is_jal_0 = io_enq_bits_uop_is_jal; // @[util.scala:448:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:448:7]
wire [15:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:448:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:448:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:448:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:448:7]
wire [11:0] io_enq_bits_uop_csr_addr_0 = io_enq_bits_uop_csr_addr; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:448:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:448:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:448:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:448:7]
wire io_enq_bits_uop_bypassable_0 = io_enq_bits_uop_bypassable; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:448:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:448:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:448:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:448:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:448:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:448:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:448:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:448:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:448:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:448:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:448:7]
wire io_enq_bits_uop_ldst_val_0 = io_enq_bits_uop_ldst_val; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:448:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:448:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:448:7]
wire io_enq_bits_uop_fp_single_0 = io_enq_bits_uop_fp_single; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:448:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:448:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:448:7]
wire [39:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:448:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:448:7]
wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:448:7]
wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:448:7]
wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:448:7]
wire [19:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:448:7]
wire [7:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:448:7]
wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:448:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:448:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:448:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:448:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[util.scala:448:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:448:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:448:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[util.scala:448:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[util.scala:448:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[util.scala:448:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[util.scala:448:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:448:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:448:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:448:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:448:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:448:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:448:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[util.scala:448:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:448:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:448:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:448:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:448:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:448:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:448:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:448:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:448:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:448:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:448:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[util.scala:448:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:448:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:448:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:448:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:448:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:448:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:448:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:448:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:448:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:448:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[util.scala:448:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:448:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:448:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:448:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:448:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:448:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:448:7]
wire io_flush_0 = io_flush; // @[util.scala:448:7]
wire _valids_WIRE_0 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_1 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_2 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_3 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_4 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_5 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_6 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_7 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_8 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_9 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_10 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_11 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_12 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_13 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_14 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_15 = 1'h0; // @[util.scala:465:32]
wire _io_enq_ready_T; // @[util.scala:504:19]
wire _io_deq_valid_T_8; // @[util.scala:509:108]
wire [6:0] out_uop_uopc; // @[util.scala:506:17]
wire [31:0] out_uop_inst; // @[util.scala:506:17]
wire [31:0] out_uop_debug_inst; // @[util.scala:506:17]
wire out_uop_is_rvc; // @[util.scala:506:17]
wire [39:0] out_uop_debug_pc; // @[util.scala:506:17]
wire [2:0] out_uop_iq_type; // @[util.scala:506:17]
wire [9:0] out_uop_fu_code; // @[util.scala:506:17]
wire [3:0] out_uop_ctrl_br_type; // @[util.scala:506:17]
wire [1:0] out_uop_ctrl_op1_sel; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_op2_sel; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_imm_sel; // @[util.scala:506:17]
wire [4:0] out_uop_ctrl_op_fcn; // @[util.scala:506:17]
wire out_uop_ctrl_fcn_dw; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_csr_cmd; // @[util.scala:506:17]
wire out_uop_ctrl_is_load; // @[util.scala:506:17]
wire out_uop_ctrl_is_sta; // @[util.scala:506:17]
wire out_uop_ctrl_is_std; // @[util.scala:506:17]
wire [1:0] out_uop_iw_state; // @[util.scala:506:17]
wire out_uop_iw_p1_poisoned; // @[util.scala:506:17]
wire out_uop_iw_p2_poisoned; // @[util.scala:506:17]
wire out_uop_is_br; // @[util.scala:506:17]
wire out_uop_is_jalr; // @[util.scala:506:17]
wire out_uop_is_jal; // @[util.scala:506:17]
wire out_uop_is_sfb; // @[util.scala:506:17]
wire [15:0] _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25]
wire [3:0] out_uop_br_tag; // @[util.scala:506:17]
wire [4:0] out_uop_ftq_idx; // @[util.scala:506:17]
wire out_uop_edge_inst; // @[util.scala:506:17]
wire [5:0] out_uop_pc_lob; // @[util.scala:506:17]
wire out_uop_taken; // @[util.scala:506:17]
wire [19:0] out_uop_imm_packed; // @[util.scala:506:17]
wire [11:0] out_uop_csr_addr; // @[util.scala:506:17]
wire [6:0] out_uop_rob_idx; // @[util.scala:506:17]
wire [4:0] out_uop_ldq_idx; // @[util.scala:506:17]
wire [4:0] out_uop_stq_idx; // @[util.scala:506:17]
wire [1:0] out_uop_rxq_idx; // @[util.scala:506:17]
wire [6:0] out_uop_pdst; // @[util.scala:506:17]
wire [6:0] out_uop_prs1; // @[util.scala:506:17]
wire [6:0] out_uop_prs2; // @[util.scala:506:17]
wire [6:0] out_uop_prs3; // @[util.scala:506:17]
wire [4:0] out_uop_ppred; // @[util.scala:506:17]
wire out_uop_prs1_busy; // @[util.scala:506:17]
wire out_uop_prs2_busy; // @[util.scala:506:17]
wire out_uop_prs3_busy; // @[util.scala:506:17]
wire out_uop_ppred_busy; // @[util.scala:506:17]
wire [6:0] out_uop_stale_pdst; // @[util.scala:506:17]
wire out_uop_exception; // @[util.scala:506:17]
wire [63:0] out_uop_exc_cause; // @[util.scala:506:17]
wire out_uop_bypassable; // @[util.scala:506:17]
wire [4:0] out_uop_mem_cmd; // @[util.scala:506:17]
wire [1:0] out_uop_mem_size; // @[util.scala:506:17]
wire out_uop_mem_signed; // @[util.scala:506:17]
wire out_uop_is_fence; // @[util.scala:506:17]
wire out_uop_is_fencei; // @[util.scala:506:17]
wire out_uop_is_amo; // @[util.scala:506:17]
wire out_uop_uses_ldq; // @[util.scala:506:17]
wire out_uop_uses_stq; // @[util.scala:506:17]
wire out_uop_is_sys_pc2epc; // @[util.scala:506:17]
wire out_uop_is_unique; // @[util.scala:506:17]
wire out_uop_flush_on_commit; // @[util.scala:506:17]
wire out_uop_ldst_is_rs1; // @[util.scala:506:17]
wire [5:0] out_uop_ldst; // @[util.scala:506:17]
wire [5:0] out_uop_lrs1; // @[util.scala:506:17]
wire [5:0] out_uop_lrs2; // @[util.scala:506:17]
wire [5:0] out_uop_lrs3; // @[util.scala:506:17]
wire out_uop_ldst_val; // @[util.scala:506:17]
wire [1:0] out_uop_dst_rtype; // @[util.scala:506:17]
wire [1:0] out_uop_lrs1_rtype; // @[util.scala:506:17]
wire [1:0] out_uop_lrs2_rtype; // @[util.scala:506:17]
wire out_uop_frs3_en; // @[util.scala:506:17]
wire out_uop_fp_val; // @[util.scala:506:17]
wire out_uop_fp_single; // @[util.scala:506:17]
wire out_uop_xcpt_pf_if; // @[util.scala:506:17]
wire out_uop_xcpt_ae_if; // @[util.scala:506:17]
wire out_uop_xcpt_ma_if; // @[util.scala:506:17]
wire out_uop_bp_debug_if; // @[util.scala:506:17]
wire out_uop_bp_xcpt_if; // @[util.scala:506:17]
wire [1:0] out_uop_debug_fsrc; // @[util.scala:506:17]
wire [1:0] out_uop_debug_tsrc; // @[util.scala:506:17]
wire [39:0] out_addr; // @[util.scala:506:17]
wire [63:0] out_data; // @[util.scala:506:17]
wire out_is_hella; // @[util.scala:506:17]
wire out_tag_match; // @[util.scala:506:17]
wire [1:0] out_old_meta_coh_state; // @[util.scala:506:17]
wire [19:0] out_old_meta_tag; // @[util.scala:506:17]
wire [7:0] out_way_en; // @[util.scala:506:17]
wire [4:0] out_sdq_id; // @[util.scala:506:17]
wire _io_empty_T_1; // @[util.scala:473:25]
wire io_enq_ready_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_uopc_0; // @[util.scala:448:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:448:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7]
wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_iq_type_0; // @[util.scala:448:7]
wire [9:0] io_deq_bits_uop_fu_code_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_iw_state_0; // @[util.scala:448:7]
wire io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7]
wire io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_br_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_jal_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7]
wire [15:0] io_deq_bits_uop_br_mask_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:448:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7]
wire [11:0] io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:448:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bypassable_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:448:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:448:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:448:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:448:7]
wire io_deq_bits_uop_fp_single_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7]
wire [19:0] io_deq_bits_old_meta_tag_0; // @[util.scala:448:7]
wire [39:0] io_deq_bits_addr_0; // @[util.scala:448:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:448:7]
wire io_deq_bits_is_hella_0; // @[util.scala:448:7]
wire io_deq_bits_tag_match_0; // @[util.scala:448:7]
wire [7:0] io_deq_bits_way_en; // @[util.scala:448:7]
wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:448:7]
wire io_deq_valid_0; // @[util.scala:448:7]
wire io_empty_0; // @[util.scala:448:7]
wire [3:0] io_count; // @[util.scala:448:7]
assign out_addr = _ram_ext_R0_data[39:0]; // @[util.scala:464:20, :506:17]
assign out_data = _ram_ext_R0_data[103:40]; // @[util.scala:464:20, :506:17]
assign out_is_hella = _ram_ext_R0_data[104]; // @[util.scala:464:20, :506:17]
assign out_tag_match = _ram_ext_R0_data[105]; // @[util.scala:464:20, :506:17]
assign out_old_meta_coh_state = _ram_ext_R0_data[107:106]; // @[util.scala:464:20, :506:17]
assign out_old_meta_tag = _ram_ext_R0_data[127:108]; // @[util.scala:464:20, :506:17]
assign out_way_en = _ram_ext_R0_data[135:128]; // @[util.scala:464:20, :506:17]
assign out_sdq_id = _ram_ext_R0_data[140:136]; // @[util.scala:464:20, :506:17]
reg valids_0; // @[util.scala:465:24]
reg valids_1; // @[util.scala:465:24]
reg valids_2; // @[util.scala:465:24]
reg valids_3; // @[util.scala:465:24]
reg valids_4; // @[util.scala:465:24]
reg valids_5; // @[util.scala:465:24]
reg valids_6; // @[util.scala:465:24]
reg valids_7; // @[util.scala:465:24]
reg valids_8; // @[util.scala:465:24]
reg valids_9; // @[util.scala:465:24]
reg valids_10; // @[util.scala:465:24]
reg valids_11; // @[util.scala:465:24]
reg valids_12; // @[util.scala:465:24]
reg valids_13; // @[util.scala:465:24]
reg valids_14; // @[util.scala:465:24]
reg valids_15; // @[util.scala:465:24]
reg [6:0] uops_0_uopc; // @[util.scala:466:20]
reg [31:0] uops_0_inst; // @[util.scala:466:20]
reg [31:0] uops_0_debug_inst; // @[util.scala:466:20]
reg uops_0_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_0_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_0_iq_type; // @[util.scala:466:20]
reg [9:0] uops_0_fu_code; // @[util.scala:466:20]
reg [3:0] uops_0_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_0_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_0_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_0_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_0_ctrl_is_load; // @[util.scala:466:20]
reg uops_0_ctrl_is_sta; // @[util.scala:466:20]
reg uops_0_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_0_iw_state; // @[util.scala:466:20]
reg uops_0_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_0_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_0_is_br; // @[util.scala:466:20]
reg uops_0_is_jalr; // @[util.scala:466:20]
reg uops_0_is_jal; // @[util.scala:466:20]
reg uops_0_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_0_br_mask; // @[util.scala:466:20]
reg [3:0] uops_0_br_tag; // @[util.scala:466:20]
reg [4:0] uops_0_ftq_idx; // @[util.scala:466:20]
reg uops_0_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_0_pc_lob; // @[util.scala:466:20]
reg uops_0_taken; // @[util.scala:466:20]
reg [19:0] uops_0_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_0_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_0_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_0_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_0_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_0_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_0_pdst; // @[util.scala:466:20]
reg [6:0] uops_0_prs1; // @[util.scala:466:20]
reg [6:0] uops_0_prs2; // @[util.scala:466:20]
reg [6:0] uops_0_prs3; // @[util.scala:466:20]
reg [4:0] uops_0_ppred; // @[util.scala:466:20]
reg uops_0_prs1_busy; // @[util.scala:466:20]
reg uops_0_prs2_busy; // @[util.scala:466:20]
reg uops_0_prs3_busy; // @[util.scala:466:20]
reg uops_0_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_0_stale_pdst; // @[util.scala:466:20]
reg uops_0_exception; // @[util.scala:466:20]
reg [63:0] uops_0_exc_cause; // @[util.scala:466:20]
reg uops_0_bypassable; // @[util.scala:466:20]
reg [4:0] uops_0_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_0_mem_size; // @[util.scala:466:20]
reg uops_0_mem_signed; // @[util.scala:466:20]
reg uops_0_is_fence; // @[util.scala:466:20]
reg uops_0_is_fencei; // @[util.scala:466:20]
reg uops_0_is_amo; // @[util.scala:466:20]
reg uops_0_uses_ldq; // @[util.scala:466:20]
reg uops_0_uses_stq; // @[util.scala:466:20]
reg uops_0_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_0_is_unique; // @[util.scala:466:20]
reg uops_0_flush_on_commit; // @[util.scala:466:20]
reg uops_0_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_0_ldst; // @[util.scala:466:20]
reg [5:0] uops_0_lrs1; // @[util.scala:466:20]
reg [5:0] uops_0_lrs2; // @[util.scala:466:20]
reg [5:0] uops_0_lrs3; // @[util.scala:466:20]
reg uops_0_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_0_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_0_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_0_lrs2_rtype; // @[util.scala:466:20]
reg uops_0_frs3_en; // @[util.scala:466:20]
reg uops_0_fp_val; // @[util.scala:466:20]
reg uops_0_fp_single; // @[util.scala:466:20]
reg uops_0_xcpt_pf_if; // @[util.scala:466:20]
reg uops_0_xcpt_ae_if; // @[util.scala:466:20]
reg uops_0_xcpt_ma_if; // @[util.scala:466:20]
reg uops_0_bp_debug_if; // @[util.scala:466:20]
reg uops_0_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_0_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_0_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_1_uopc; // @[util.scala:466:20]
reg [31:0] uops_1_inst; // @[util.scala:466:20]
reg [31:0] uops_1_debug_inst; // @[util.scala:466:20]
reg uops_1_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_1_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_1_iq_type; // @[util.scala:466:20]
reg [9:0] uops_1_fu_code; // @[util.scala:466:20]
reg [3:0] uops_1_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_1_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_1_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_1_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_1_ctrl_is_load; // @[util.scala:466:20]
reg uops_1_ctrl_is_sta; // @[util.scala:466:20]
reg uops_1_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_1_iw_state; // @[util.scala:466:20]
reg uops_1_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_1_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_1_is_br; // @[util.scala:466:20]
reg uops_1_is_jalr; // @[util.scala:466:20]
reg uops_1_is_jal; // @[util.scala:466:20]
reg uops_1_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_1_br_mask; // @[util.scala:466:20]
reg [3:0] uops_1_br_tag; // @[util.scala:466:20]
reg [4:0] uops_1_ftq_idx; // @[util.scala:466:20]
reg uops_1_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_1_pc_lob; // @[util.scala:466:20]
reg uops_1_taken; // @[util.scala:466:20]
reg [19:0] uops_1_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_1_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_1_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_1_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_1_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_1_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_1_pdst; // @[util.scala:466:20]
reg [6:0] uops_1_prs1; // @[util.scala:466:20]
reg [6:0] uops_1_prs2; // @[util.scala:466:20]
reg [6:0] uops_1_prs3; // @[util.scala:466:20]
reg [4:0] uops_1_ppred; // @[util.scala:466:20]
reg uops_1_prs1_busy; // @[util.scala:466:20]
reg uops_1_prs2_busy; // @[util.scala:466:20]
reg uops_1_prs3_busy; // @[util.scala:466:20]
reg uops_1_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_1_stale_pdst; // @[util.scala:466:20]
reg uops_1_exception; // @[util.scala:466:20]
reg [63:0] uops_1_exc_cause; // @[util.scala:466:20]
reg uops_1_bypassable; // @[util.scala:466:20]
reg [4:0] uops_1_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_1_mem_size; // @[util.scala:466:20]
reg uops_1_mem_signed; // @[util.scala:466:20]
reg uops_1_is_fence; // @[util.scala:466:20]
reg uops_1_is_fencei; // @[util.scala:466:20]
reg uops_1_is_amo; // @[util.scala:466:20]
reg uops_1_uses_ldq; // @[util.scala:466:20]
reg uops_1_uses_stq; // @[util.scala:466:20]
reg uops_1_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_1_is_unique; // @[util.scala:466:20]
reg uops_1_flush_on_commit; // @[util.scala:466:20]
reg uops_1_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_1_ldst; // @[util.scala:466:20]
reg [5:0] uops_1_lrs1; // @[util.scala:466:20]
reg [5:0] uops_1_lrs2; // @[util.scala:466:20]
reg [5:0] uops_1_lrs3; // @[util.scala:466:20]
reg uops_1_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_1_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_1_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_1_lrs2_rtype; // @[util.scala:466:20]
reg uops_1_frs3_en; // @[util.scala:466:20]
reg uops_1_fp_val; // @[util.scala:466:20]
reg uops_1_fp_single; // @[util.scala:466:20]
reg uops_1_xcpt_pf_if; // @[util.scala:466:20]
reg uops_1_xcpt_ae_if; // @[util.scala:466:20]
reg uops_1_xcpt_ma_if; // @[util.scala:466:20]
reg uops_1_bp_debug_if; // @[util.scala:466:20]
reg uops_1_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_1_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_1_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_2_uopc; // @[util.scala:466:20]
reg [31:0] uops_2_inst; // @[util.scala:466:20]
reg [31:0] uops_2_debug_inst; // @[util.scala:466:20]
reg uops_2_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_2_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_2_iq_type; // @[util.scala:466:20]
reg [9:0] uops_2_fu_code; // @[util.scala:466:20]
reg [3:0] uops_2_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_2_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_2_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_2_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_2_ctrl_is_load; // @[util.scala:466:20]
reg uops_2_ctrl_is_sta; // @[util.scala:466:20]
reg uops_2_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_2_iw_state; // @[util.scala:466:20]
reg uops_2_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_2_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_2_is_br; // @[util.scala:466:20]
reg uops_2_is_jalr; // @[util.scala:466:20]
reg uops_2_is_jal; // @[util.scala:466:20]
reg uops_2_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_2_br_mask; // @[util.scala:466:20]
reg [3:0] uops_2_br_tag; // @[util.scala:466:20]
reg [4:0] uops_2_ftq_idx; // @[util.scala:466:20]
reg uops_2_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_2_pc_lob; // @[util.scala:466:20]
reg uops_2_taken; // @[util.scala:466:20]
reg [19:0] uops_2_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_2_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_2_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_2_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_2_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_2_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_2_pdst; // @[util.scala:466:20]
reg [6:0] uops_2_prs1; // @[util.scala:466:20]
reg [6:0] uops_2_prs2; // @[util.scala:466:20]
reg [6:0] uops_2_prs3; // @[util.scala:466:20]
reg [4:0] uops_2_ppred; // @[util.scala:466:20]
reg uops_2_prs1_busy; // @[util.scala:466:20]
reg uops_2_prs2_busy; // @[util.scala:466:20]
reg uops_2_prs3_busy; // @[util.scala:466:20]
reg uops_2_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_2_stale_pdst; // @[util.scala:466:20]
reg uops_2_exception; // @[util.scala:466:20]
reg [63:0] uops_2_exc_cause; // @[util.scala:466:20]
reg uops_2_bypassable; // @[util.scala:466:20]
reg [4:0] uops_2_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_2_mem_size; // @[util.scala:466:20]
reg uops_2_mem_signed; // @[util.scala:466:20]
reg uops_2_is_fence; // @[util.scala:466:20]
reg uops_2_is_fencei; // @[util.scala:466:20]
reg uops_2_is_amo; // @[util.scala:466:20]
reg uops_2_uses_ldq; // @[util.scala:466:20]
reg uops_2_uses_stq; // @[util.scala:466:20]
reg uops_2_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_2_is_unique; // @[util.scala:466:20]
reg uops_2_flush_on_commit; // @[util.scala:466:20]
reg uops_2_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_2_ldst; // @[util.scala:466:20]
reg [5:0] uops_2_lrs1; // @[util.scala:466:20]
reg [5:0] uops_2_lrs2; // @[util.scala:466:20]
reg [5:0] uops_2_lrs3; // @[util.scala:466:20]
reg uops_2_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_2_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_2_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_2_lrs2_rtype; // @[util.scala:466:20]
reg uops_2_frs3_en; // @[util.scala:466:20]
reg uops_2_fp_val; // @[util.scala:466:20]
reg uops_2_fp_single; // @[util.scala:466:20]
reg uops_2_xcpt_pf_if; // @[util.scala:466:20]
reg uops_2_xcpt_ae_if; // @[util.scala:466:20]
reg uops_2_xcpt_ma_if; // @[util.scala:466:20]
reg uops_2_bp_debug_if; // @[util.scala:466:20]
reg uops_2_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_2_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_2_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_3_uopc; // @[util.scala:466:20]
reg [31:0] uops_3_inst; // @[util.scala:466:20]
reg [31:0] uops_3_debug_inst; // @[util.scala:466:20]
reg uops_3_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_3_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_3_iq_type; // @[util.scala:466:20]
reg [9:0] uops_3_fu_code; // @[util.scala:466:20]
reg [3:0] uops_3_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_3_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_3_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_3_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_3_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_3_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_3_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_3_ctrl_is_load; // @[util.scala:466:20]
reg uops_3_ctrl_is_sta; // @[util.scala:466:20]
reg uops_3_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_3_iw_state; // @[util.scala:466:20]
reg uops_3_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_3_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_3_is_br; // @[util.scala:466:20]
reg uops_3_is_jalr; // @[util.scala:466:20]
reg uops_3_is_jal; // @[util.scala:466:20]
reg uops_3_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_3_br_mask; // @[util.scala:466:20]
reg [3:0] uops_3_br_tag; // @[util.scala:466:20]
reg [4:0] uops_3_ftq_idx; // @[util.scala:466:20]
reg uops_3_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_3_pc_lob; // @[util.scala:466:20]
reg uops_3_taken; // @[util.scala:466:20]
reg [19:0] uops_3_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_3_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_3_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_3_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_3_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_3_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_3_pdst; // @[util.scala:466:20]
reg [6:0] uops_3_prs1; // @[util.scala:466:20]
reg [6:0] uops_3_prs2; // @[util.scala:466:20]
reg [6:0] uops_3_prs3; // @[util.scala:466:20]
reg [4:0] uops_3_ppred; // @[util.scala:466:20]
reg uops_3_prs1_busy; // @[util.scala:466:20]
reg uops_3_prs2_busy; // @[util.scala:466:20]
reg uops_3_prs3_busy; // @[util.scala:466:20]
reg uops_3_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_3_stale_pdst; // @[util.scala:466:20]
reg uops_3_exception; // @[util.scala:466:20]
reg [63:0] uops_3_exc_cause; // @[util.scala:466:20]
reg uops_3_bypassable; // @[util.scala:466:20]
reg [4:0] uops_3_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_3_mem_size; // @[util.scala:466:20]
reg uops_3_mem_signed; // @[util.scala:466:20]
reg uops_3_is_fence; // @[util.scala:466:20]
reg uops_3_is_fencei; // @[util.scala:466:20]
reg uops_3_is_amo; // @[util.scala:466:20]
reg uops_3_uses_ldq; // @[util.scala:466:20]
reg uops_3_uses_stq; // @[util.scala:466:20]
reg uops_3_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_3_is_unique; // @[util.scala:466:20]
reg uops_3_flush_on_commit; // @[util.scala:466:20]
reg uops_3_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_3_ldst; // @[util.scala:466:20]
reg [5:0] uops_3_lrs1; // @[util.scala:466:20]
reg [5:0] uops_3_lrs2; // @[util.scala:466:20]
reg [5:0] uops_3_lrs3; // @[util.scala:466:20]
reg uops_3_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_3_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_3_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_3_lrs2_rtype; // @[util.scala:466:20]
reg uops_3_frs3_en; // @[util.scala:466:20]
reg uops_3_fp_val; // @[util.scala:466:20]
reg uops_3_fp_single; // @[util.scala:466:20]
reg uops_3_xcpt_pf_if; // @[util.scala:466:20]
reg uops_3_xcpt_ae_if; // @[util.scala:466:20]
reg uops_3_xcpt_ma_if; // @[util.scala:466:20]
reg uops_3_bp_debug_if; // @[util.scala:466:20]
reg uops_3_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_3_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_3_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_4_uopc; // @[util.scala:466:20]
reg [31:0] uops_4_inst; // @[util.scala:466:20]
reg [31:0] uops_4_debug_inst; // @[util.scala:466:20]
reg uops_4_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_4_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_4_iq_type; // @[util.scala:466:20]
reg [9:0] uops_4_fu_code; // @[util.scala:466:20]
reg [3:0] uops_4_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_4_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_4_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_4_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_4_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_4_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_4_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_4_ctrl_is_load; // @[util.scala:466:20]
reg uops_4_ctrl_is_sta; // @[util.scala:466:20]
reg uops_4_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_4_iw_state; // @[util.scala:466:20]
reg uops_4_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_4_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_4_is_br; // @[util.scala:466:20]
reg uops_4_is_jalr; // @[util.scala:466:20]
reg uops_4_is_jal; // @[util.scala:466:20]
reg uops_4_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_4_br_mask; // @[util.scala:466:20]
reg [3:0] uops_4_br_tag; // @[util.scala:466:20]
reg [4:0] uops_4_ftq_idx; // @[util.scala:466:20]
reg uops_4_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_4_pc_lob; // @[util.scala:466:20]
reg uops_4_taken; // @[util.scala:466:20]
reg [19:0] uops_4_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_4_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_4_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_4_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_4_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_4_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_4_pdst; // @[util.scala:466:20]
reg [6:0] uops_4_prs1; // @[util.scala:466:20]
reg [6:0] uops_4_prs2; // @[util.scala:466:20]
reg [6:0] uops_4_prs3; // @[util.scala:466:20]
reg [4:0] uops_4_ppred; // @[util.scala:466:20]
reg uops_4_prs1_busy; // @[util.scala:466:20]
reg uops_4_prs2_busy; // @[util.scala:466:20]
reg uops_4_prs3_busy; // @[util.scala:466:20]
reg uops_4_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_4_stale_pdst; // @[util.scala:466:20]
reg uops_4_exception; // @[util.scala:466:20]
reg [63:0] uops_4_exc_cause; // @[util.scala:466:20]
reg uops_4_bypassable; // @[util.scala:466:20]
reg [4:0] uops_4_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_4_mem_size; // @[util.scala:466:20]
reg uops_4_mem_signed; // @[util.scala:466:20]
reg uops_4_is_fence; // @[util.scala:466:20]
reg uops_4_is_fencei; // @[util.scala:466:20]
reg uops_4_is_amo; // @[util.scala:466:20]
reg uops_4_uses_ldq; // @[util.scala:466:20]
reg uops_4_uses_stq; // @[util.scala:466:20]
reg uops_4_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_4_is_unique; // @[util.scala:466:20]
reg uops_4_flush_on_commit; // @[util.scala:466:20]
reg uops_4_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_4_ldst; // @[util.scala:466:20]
reg [5:0] uops_4_lrs1; // @[util.scala:466:20]
reg [5:0] uops_4_lrs2; // @[util.scala:466:20]
reg [5:0] uops_4_lrs3; // @[util.scala:466:20]
reg uops_4_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_4_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_4_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_4_lrs2_rtype; // @[util.scala:466:20]
reg uops_4_frs3_en; // @[util.scala:466:20]
reg uops_4_fp_val; // @[util.scala:466:20]
reg uops_4_fp_single; // @[util.scala:466:20]
reg uops_4_xcpt_pf_if; // @[util.scala:466:20]
reg uops_4_xcpt_ae_if; // @[util.scala:466:20]
reg uops_4_xcpt_ma_if; // @[util.scala:466:20]
reg uops_4_bp_debug_if; // @[util.scala:466:20]
reg uops_4_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_4_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_4_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_5_uopc; // @[util.scala:466:20]
reg [31:0] uops_5_inst; // @[util.scala:466:20]
reg [31:0] uops_5_debug_inst; // @[util.scala:466:20]
reg uops_5_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_5_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_5_iq_type; // @[util.scala:466:20]
reg [9:0] uops_5_fu_code; // @[util.scala:466:20]
reg [3:0] uops_5_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_5_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_5_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_5_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_5_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_5_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_5_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_5_ctrl_is_load; // @[util.scala:466:20]
reg uops_5_ctrl_is_sta; // @[util.scala:466:20]
reg uops_5_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_5_iw_state; // @[util.scala:466:20]
reg uops_5_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_5_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_5_is_br; // @[util.scala:466:20]
reg uops_5_is_jalr; // @[util.scala:466:20]
reg uops_5_is_jal; // @[util.scala:466:20]
reg uops_5_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_5_br_mask; // @[util.scala:466:20]
reg [3:0] uops_5_br_tag; // @[util.scala:466:20]
reg [4:0] uops_5_ftq_idx; // @[util.scala:466:20]
reg uops_5_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_5_pc_lob; // @[util.scala:466:20]
reg uops_5_taken; // @[util.scala:466:20]
reg [19:0] uops_5_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_5_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_5_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_5_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_5_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_5_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_5_pdst; // @[util.scala:466:20]
reg [6:0] uops_5_prs1; // @[util.scala:466:20]
reg [6:0] uops_5_prs2; // @[util.scala:466:20]
reg [6:0] uops_5_prs3; // @[util.scala:466:20]
reg [4:0] uops_5_ppred; // @[util.scala:466:20]
reg uops_5_prs1_busy; // @[util.scala:466:20]
reg uops_5_prs2_busy; // @[util.scala:466:20]
reg uops_5_prs3_busy; // @[util.scala:466:20]
reg uops_5_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_5_stale_pdst; // @[util.scala:466:20]
reg uops_5_exception; // @[util.scala:466:20]
reg [63:0] uops_5_exc_cause; // @[util.scala:466:20]
reg uops_5_bypassable; // @[util.scala:466:20]
reg [4:0] uops_5_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_5_mem_size; // @[util.scala:466:20]
reg uops_5_mem_signed; // @[util.scala:466:20]
reg uops_5_is_fence; // @[util.scala:466:20]
reg uops_5_is_fencei; // @[util.scala:466:20]
reg uops_5_is_amo; // @[util.scala:466:20]
reg uops_5_uses_ldq; // @[util.scala:466:20]
reg uops_5_uses_stq; // @[util.scala:466:20]
reg uops_5_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_5_is_unique; // @[util.scala:466:20]
reg uops_5_flush_on_commit; // @[util.scala:466:20]
reg uops_5_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_5_ldst; // @[util.scala:466:20]
reg [5:0] uops_5_lrs1; // @[util.scala:466:20]
reg [5:0] uops_5_lrs2; // @[util.scala:466:20]
reg [5:0] uops_5_lrs3; // @[util.scala:466:20]
reg uops_5_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_5_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_5_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_5_lrs2_rtype; // @[util.scala:466:20]
reg uops_5_frs3_en; // @[util.scala:466:20]
reg uops_5_fp_val; // @[util.scala:466:20]
reg uops_5_fp_single; // @[util.scala:466:20]
reg uops_5_xcpt_pf_if; // @[util.scala:466:20]
reg uops_5_xcpt_ae_if; // @[util.scala:466:20]
reg uops_5_xcpt_ma_if; // @[util.scala:466:20]
reg uops_5_bp_debug_if; // @[util.scala:466:20]
reg uops_5_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_5_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_5_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_6_uopc; // @[util.scala:466:20]
reg [31:0] uops_6_inst; // @[util.scala:466:20]
reg [31:0] uops_6_debug_inst; // @[util.scala:466:20]
reg uops_6_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_6_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_6_iq_type; // @[util.scala:466:20]
reg [9:0] uops_6_fu_code; // @[util.scala:466:20]
reg [3:0] uops_6_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_6_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_6_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_6_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_6_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_6_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_6_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_6_ctrl_is_load; // @[util.scala:466:20]
reg uops_6_ctrl_is_sta; // @[util.scala:466:20]
reg uops_6_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_6_iw_state; // @[util.scala:466:20]
reg uops_6_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_6_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_6_is_br; // @[util.scala:466:20]
reg uops_6_is_jalr; // @[util.scala:466:20]
reg uops_6_is_jal; // @[util.scala:466:20]
reg uops_6_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_6_br_mask; // @[util.scala:466:20]
reg [3:0] uops_6_br_tag; // @[util.scala:466:20]
reg [4:0] uops_6_ftq_idx; // @[util.scala:466:20]
reg uops_6_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_6_pc_lob; // @[util.scala:466:20]
reg uops_6_taken; // @[util.scala:466:20]
reg [19:0] uops_6_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_6_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_6_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_6_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_6_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_6_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_6_pdst; // @[util.scala:466:20]
reg [6:0] uops_6_prs1; // @[util.scala:466:20]
reg [6:0] uops_6_prs2; // @[util.scala:466:20]
reg [6:0] uops_6_prs3; // @[util.scala:466:20]
reg [4:0] uops_6_ppred; // @[util.scala:466:20]
reg uops_6_prs1_busy; // @[util.scala:466:20]
reg uops_6_prs2_busy; // @[util.scala:466:20]
reg uops_6_prs3_busy; // @[util.scala:466:20]
reg uops_6_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_6_stale_pdst; // @[util.scala:466:20]
reg uops_6_exception; // @[util.scala:466:20]
reg [63:0] uops_6_exc_cause; // @[util.scala:466:20]
reg uops_6_bypassable; // @[util.scala:466:20]
reg [4:0] uops_6_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_6_mem_size; // @[util.scala:466:20]
reg uops_6_mem_signed; // @[util.scala:466:20]
reg uops_6_is_fence; // @[util.scala:466:20]
reg uops_6_is_fencei; // @[util.scala:466:20]
reg uops_6_is_amo; // @[util.scala:466:20]
reg uops_6_uses_ldq; // @[util.scala:466:20]
reg uops_6_uses_stq; // @[util.scala:466:20]
reg uops_6_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_6_is_unique; // @[util.scala:466:20]
reg uops_6_flush_on_commit; // @[util.scala:466:20]
reg uops_6_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_6_ldst; // @[util.scala:466:20]
reg [5:0] uops_6_lrs1; // @[util.scala:466:20]
reg [5:0] uops_6_lrs2; // @[util.scala:466:20]
reg [5:0] uops_6_lrs3; // @[util.scala:466:20]
reg uops_6_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_6_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_6_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_6_lrs2_rtype; // @[util.scala:466:20]
reg uops_6_frs3_en; // @[util.scala:466:20]
reg uops_6_fp_val; // @[util.scala:466:20]
reg uops_6_fp_single; // @[util.scala:466:20]
reg uops_6_xcpt_pf_if; // @[util.scala:466:20]
reg uops_6_xcpt_ae_if; // @[util.scala:466:20]
reg uops_6_xcpt_ma_if; // @[util.scala:466:20]
reg uops_6_bp_debug_if; // @[util.scala:466:20]
reg uops_6_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_6_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_6_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_7_uopc; // @[util.scala:466:20]
reg [31:0] uops_7_inst; // @[util.scala:466:20]
reg [31:0] uops_7_debug_inst; // @[util.scala:466:20]
reg uops_7_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_7_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_7_iq_type; // @[util.scala:466:20]
reg [9:0] uops_7_fu_code; // @[util.scala:466:20]
reg [3:0] uops_7_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_7_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_7_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_7_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_7_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_7_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_7_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_7_ctrl_is_load; // @[util.scala:466:20]
reg uops_7_ctrl_is_sta; // @[util.scala:466:20]
reg uops_7_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_7_iw_state; // @[util.scala:466:20]
reg uops_7_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_7_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_7_is_br; // @[util.scala:466:20]
reg uops_7_is_jalr; // @[util.scala:466:20]
reg uops_7_is_jal; // @[util.scala:466:20]
reg uops_7_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_7_br_mask; // @[util.scala:466:20]
reg [3:0] uops_7_br_tag; // @[util.scala:466:20]
reg [4:0] uops_7_ftq_idx; // @[util.scala:466:20]
reg uops_7_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_7_pc_lob; // @[util.scala:466:20]
reg uops_7_taken; // @[util.scala:466:20]
reg [19:0] uops_7_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_7_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_7_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_7_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_7_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_7_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_7_pdst; // @[util.scala:466:20]
reg [6:0] uops_7_prs1; // @[util.scala:466:20]
reg [6:0] uops_7_prs2; // @[util.scala:466:20]
reg [6:0] uops_7_prs3; // @[util.scala:466:20]
reg [4:0] uops_7_ppred; // @[util.scala:466:20]
reg uops_7_prs1_busy; // @[util.scala:466:20]
reg uops_7_prs2_busy; // @[util.scala:466:20]
reg uops_7_prs3_busy; // @[util.scala:466:20]
reg uops_7_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_7_stale_pdst; // @[util.scala:466:20]
reg uops_7_exception; // @[util.scala:466:20]
reg [63:0] uops_7_exc_cause; // @[util.scala:466:20]
reg uops_7_bypassable; // @[util.scala:466:20]
reg [4:0] uops_7_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_7_mem_size; // @[util.scala:466:20]
reg uops_7_mem_signed; // @[util.scala:466:20]
reg uops_7_is_fence; // @[util.scala:466:20]
reg uops_7_is_fencei; // @[util.scala:466:20]
reg uops_7_is_amo; // @[util.scala:466:20]
reg uops_7_uses_ldq; // @[util.scala:466:20]
reg uops_7_uses_stq; // @[util.scala:466:20]
reg uops_7_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_7_is_unique; // @[util.scala:466:20]
reg uops_7_flush_on_commit; // @[util.scala:466:20]
reg uops_7_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_7_ldst; // @[util.scala:466:20]
reg [5:0] uops_7_lrs1; // @[util.scala:466:20]
reg [5:0] uops_7_lrs2; // @[util.scala:466:20]
reg [5:0] uops_7_lrs3; // @[util.scala:466:20]
reg uops_7_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_7_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_7_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_7_lrs2_rtype; // @[util.scala:466:20]
reg uops_7_frs3_en; // @[util.scala:466:20]
reg uops_7_fp_val; // @[util.scala:466:20]
reg uops_7_fp_single; // @[util.scala:466:20]
reg uops_7_xcpt_pf_if; // @[util.scala:466:20]
reg uops_7_xcpt_ae_if; // @[util.scala:466:20]
reg uops_7_xcpt_ma_if; // @[util.scala:466:20]
reg uops_7_bp_debug_if; // @[util.scala:466:20]
reg uops_7_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_7_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_7_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_8_uopc; // @[util.scala:466:20]
reg [31:0] uops_8_inst; // @[util.scala:466:20]
reg [31:0] uops_8_debug_inst; // @[util.scala:466:20]
reg uops_8_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_8_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_8_iq_type; // @[util.scala:466:20]
reg [9:0] uops_8_fu_code; // @[util.scala:466:20]
reg [3:0] uops_8_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_8_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_8_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_8_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_8_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_8_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_8_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_8_ctrl_is_load; // @[util.scala:466:20]
reg uops_8_ctrl_is_sta; // @[util.scala:466:20]
reg uops_8_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_8_iw_state; // @[util.scala:466:20]
reg uops_8_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_8_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_8_is_br; // @[util.scala:466:20]
reg uops_8_is_jalr; // @[util.scala:466:20]
reg uops_8_is_jal; // @[util.scala:466:20]
reg uops_8_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_8_br_mask; // @[util.scala:466:20]
reg [3:0] uops_8_br_tag; // @[util.scala:466:20]
reg [4:0] uops_8_ftq_idx; // @[util.scala:466:20]
reg uops_8_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_8_pc_lob; // @[util.scala:466:20]
reg uops_8_taken; // @[util.scala:466:20]
reg [19:0] uops_8_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_8_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_8_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_8_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_8_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_8_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_8_pdst; // @[util.scala:466:20]
reg [6:0] uops_8_prs1; // @[util.scala:466:20]
reg [6:0] uops_8_prs2; // @[util.scala:466:20]
reg [6:0] uops_8_prs3; // @[util.scala:466:20]
reg [4:0] uops_8_ppred; // @[util.scala:466:20]
reg uops_8_prs1_busy; // @[util.scala:466:20]
reg uops_8_prs2_busy; // @[util.scala:466:20]
reg uops_8_prs3_busy; // @[util.scala:466:20]
reg uops_8_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_8_stale_pdst; // @[util.scala:466:20]
reg uops_8_exception; // @[util.scala:466:20]
reg [63:0] uops_8_exc_cause; // @[util.scala:466:20]
reg uops_8_bypassable; // @[util.scala:466:20]
reg [4:0] uops_8_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_8_mem_size; // @[util.scala:466:20]
reg uops_8_mem_signed; // @[util.scala:466:20]
reg uops_8_is_fence; // @[util.scala:466:20]
reg uops_8_is_fencei; // @[util.scala:466:20]
reg uops_8_is_amo; // @[util.scala:466:20]
reg uops_8_uses_ldq; // @[util.scala:466:20]
reg uops_8_uses_stq; // @[util.scala:466:20]
reg uops_8_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_8_is_unique; // @[util.scala:466:20]
reg uops_8_flush_on_commit; // @[util.scala:466:20]
reg uops_8_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_8_ldst; // @[util.scala:466:20]
reg [5:0] uops_8_lrs1; // @[util.scala:466:20]
reg [5:0] uops_8_lrs2; // @[util.scala:466:20]
reg [5:0] uops_8_lrs3; // @[util.scala:466:20]
reg uops_8_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_8_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_8_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_8_lrs2_rtype; // @[util.scala:466:20]
reg uops_8_frs3_en; // @[util.scala:466:20]
reg uops_8_fp_val; // @[util.scala:466:20]
reg uops_8_fp_single; // @[util.scala:466:20]
reg uops_8_xcpt_pf_if; // @[util.scala:466:20]
reg uops_8_xcpt_ae_if; // @[util.scala:466:20]
reg uops_8_xcpt_ma_if; // @[util.scala:466:20]
reg uops_8_bp_debug_if; // @[util.scala:466:20]
reg uops_8_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_8_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_8_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_9_uopc; // @[util.scala:466:20]
reg [31:0] uops_9_inst; // @[util.scala:466:20]
reg [31:0] uops_9_debug_inst; // @[util.scala:466:20]
reg uops_9_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_9_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_9_iq_type; // @[util.scala:466:20]
reg [9:0] uops_9_fu_code; // @[util.scala:466:20]
reg [3:0] uops_9_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_9_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_9_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_9_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_9_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_9_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_9_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_9_ctrl_is_load; // @[util.scala:466:20]
reg uops_9_ctrl_is_sta; // @[util.scala:466:20]
reg uops_9_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_9_iw_state; // @[util.scala:466:20]
reg uops_9_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_9_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_9_is_br; // @[util.scala:466:20]
reg uops_9_is_jalr; // @[util.scala:466:20]
reg uops_9_is_jal; // @[util.scala:466:20]
reg uops_9_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_9_br_mask; // @[util.scala:466:20]
reg [3:0] uops_9_br_tag; // @[util.scala:466:20]
reg [4:0] uops_9_ftq_idx; // @[util.scala:466:20]
reg uops_9_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_9_pc_lob; // @[util.scala:466:20]
reg uops_9_taken; // @[util.scala:466:20]
reg [19:0] uops_9_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_9_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_9_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_9_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_9_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_9_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_9_pdst; // @[util.scala:466:20]
reg [6:0] uops_9_prs1; // @[util.scala:466:20]
reg [6:0] uops_9_prs2; // @[util.scala:466:20]
reg [6:0] uops_9_prs3; // @[util.scala:466:20]
reg [4:0] uops_9_ppred; // @[util.scala:466:20]
reg uops_9_prs1_busy; // @[util.scala:466:20]
reg uops_9_prs2_busy; // @[util.scala:466:20]
reg uops_9_prs3_busy; // @[util.scala:466:20]
reg uops_9_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_9_stale_pdst; // @[util.scala:466:20]
reg uops_9_exception; // @[util.scala:466:20]
reg [63:0] uops_9_exc_cause; // @[util.scala:466:20]
reg uops_9_bypassable; // @[util.scala:466:20]
reg [4:0] uops_9_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_9_mem_size; // @[util.scala:466:20]
reg uops_9_mem_signed; // @[util.scala:466:20]
reg uops_9_is_fence; // @[util.scala:466:20]
reg uops_9_is_fencei; // @[util.scala:466:20]
reg uops_9_is_amo; // @[util.scala:466:20]
reg uops_9_uses_ldq; // @[util.scala:466:20]
reg uops_9_uses_stq; // @[util.scala:466:20]
reg uops_9_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_9_is_unique; // @[util.scala:466:20]
reg uops_9_flush_on_commit; // @[util.scala:466:20]
reg uops_9_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_9_ldst; // @[util.scala:466:20]
reg [5:0] uops_9_lrs1; // @[util.scala:466:20]
reg [5:0] uops_9_lrs2; // @[util.scala:466:20]
reg [5:0] uops_9_lrs3; // @[util.scala:466:20]
reg uops_9_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_9_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_9_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_9_lrs2_rtype; // @[util.scala:466:20]
reg uops_9_frs3_en; // @[util.scala:466:20]
reg uops_9_fp_val; // @[util.scala:466:20]
reg uops_9_fp_single; // @[util.scala:466:20]
reg uops_9_xcpt_pf_if; // @[util.scala:466:20]
reg uops_9_xcpt_ae_if; // @[util.scala:466:20]
reg uops_9_xcpt_ma_if; // @[util.scala:466:20]
reg uops_9_bp_debug_if; // @[util.scala:466:20]
reg uops_9_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_9_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_9_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_10_uopc; // @[util.scala:466:20]
reg [31:0] uops_10_inst; // @[util.scala:466:20]
reg [31:0] uops_10_debug_inst; // @[util.scala:466:20]
reg uops_10_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_10_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_10_iq_type; // @[util.scala:466:20]
reg [9:0] uops_10_fu_code; // @[util.scala:466:20]
reg [3:0] uops_10_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_10_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_10_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_10_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_10_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_10_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_10_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_10_ctrl_is_load; // @[util.scala:466:20]
reg uops_10_ctrl_is_sta; // @[util.scala:466:20]
reg uops_10_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_10_iw_state; // @[util.scala:466:20]
reg uops_10_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_10_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_10_is_br; // @[util.scala:466:20]
reg uops_10_is_jalr; // @[util.scala:466:20]
reg uops_10_is_jal; // @[util.scala:466:20]
reg uops_10_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_10_br_mask; // @[util.scala:466:20]
reg [3:0] uops_10_br_tag; // @[util.scala:466:20]
reg [4:0] uops_10_ftq_idx; // @[util.scala:466:20]
reg uops_10_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_10_pc_lob; // @[util.scala:466:20]
reg uops_10_taken; // @[util.scala:466:20]
reg [19:0] uops_10_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_10_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_10_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_10_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_10_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_10_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_10_pdst; // @[util.scala:466:20]
reg [6:0] uops_10_prs1; // @[util.scala:466:20]
reg [6:0] uops_10_prs2; // @[util.scala:466:20]
reg [6:0] uops_10_prs3; // @[util.scala:466:20]
reg [4:0] uops_10_ppred; // @[util.scala:466:20]
reg uops_10_prs1_busy; // @[util.scala:466:20]
reg uops_10_prs2_busy; // @[util.scala:466:20]
reg uops_10_prs3_busy; // @[util.scala:466:20]
reg uops_10_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_10_stale_pdst; // @[util.scala:466:20]
reg uops_10_exception; // @[util.scala:466:20]
reg [63:0] uops_10_exc_cause; // @[util.scala:466:20]
reg uops_10_bypassable; // @[util.scala:466:20]
reg [4:0] uops_10_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_10_mem_size; // @[util.scala:466:20]
reg uops_10_mem_signed; // @[util.scala:466:20]
reg uops_10_is_fence; // @[util.scala:466:20]
reg uops_10_is_fencei; // @[util.scala:466:20]
reg uops_10_is_amo; // @[util.scala:466:20]
reg uops_10_uses_ldq; // @[util.scala:466:20]
reg uops_10_uses_stq; // @[util.scala:466:20]
reg uops_10_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_10_is_unique; // @[util.scala:466:20]
reg uops_10_flush_on_commit; // @[util.scala:466:20]
reg uops_10_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_10_ldst; // @[util.scala:466:20]
reg [5:0] uops_10_lrs1; // @[util.scala:466:20]
reg [5:0] uops_10_lrs2; // @[util.scala:466:20]
reg [5:0] uops_10_lrs3; // @[util.scala:466:20]
reg uops_10_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_10_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_10_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_10_lrs2_rtype; // @[util.scala:466:20]
reg uops_10_frs3_en; // @[util.scala:466:20]
reg uops_10_fp_val; // @[util.scala:466:20]
reg uops_10_fp_single; // @[util.scala:466:20]
reg uops_10_xcpt_pf_if; // @[util.scala:466:20]
reg uops_10_xcpt_ae_if; // @[util.scala:466:20]
reg uops_10_xcpt_ma_if; // @[util.scala:466:20]
reg uops_10_bp_debug_if; // @[util.scala:466:20]
reg uops_10_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_10_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_10_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_11_uopc; // @[util.scala:466:20]
reg [31:0] uops_11_inst; // @[util.scala:466:20]
reg [31:0] uops_11_debug_inst; // @[util.scala:466:20]
reg uops_11_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_11_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_11_iq_type; // @[util.scala:466:20]
reg [9:0] uops_11_fu_code; // @[util.scala:466:20]
reg [3:0] uops_11_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_11_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_11_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_11_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_11_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_11_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_11_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_11_ctrl_is_load; // @[util.scala:466:20]
reg uops_11_ctrl_is_sta; // @[util.scala:466:20]
reg uops_11_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_11_iw_state; // @[util.scala:466:20]
reg uops_11_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_11_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_11_is_br; // @[util.scala:466:20]
reg uops_11_is_jalr; // @[util.scala:466:20]
reg uops_11_is_jal; // @[util.scala:466:20]
reg uops_11_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_11_br_mask; // @[util.scala:466:20]
reg [3:0] uops_11_br_tag; // @[util.scala:466:20]
reg [4:0] uops_11_ftq_idx; // @[util.scala:466:20]
reg uops_11_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_11_pc_lob; // @[util.scala:466:20]
reg uops_11_taken; // @[util.scala:466:20]
reg [19:0] uops_11_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_11_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_11_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_11_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_11_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_11_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_11_pdst; // @[util.scala:466:20]
reg [6:0] uops_11_prs1; // @[util.scala:466:20]
reg [6:0] uops_11_prs2; // @[util.scala:466:20]
reg [6:0] uops_11_prs3; // @[util.scala:466:20]
reg [4:0] uops_11_ppred; // @[util.scala:466:20]
reg uops_11_prs1_busy; // @[util.scala:466:20]
reg uops_11_prs2_busy; // @[util.scala:466:20]
reg uops_11_prs3_busy; // @[util.scala:466:20]
reg uops_11_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_11_stale_pdst; // @[util.scala:466:20]
reg uops_11_exception; // @[util.scala:466:20]
reg [63:0] uops_11_exc_cause; // @[util.scala:466:20]
reg uops_11_bypassable; // @[util.scala:466:20]
reg [4:0] uops_11_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_11_mem_size; // @[util.scala:466:20]
reg uops_11_mem_signed; // @[util.scala:466:20]
reg uops_11_is_fence; // @[util.scala:466:20]
reg uops_11_is_fencei; // @[util.scala:466:20]
reg uops_11_is_amo; // @[util.scala:466:20]
reg uops_11_uses_ldq; // @[util.scala:466:20]
reg uops_11_uses_stq; // @[util.scala:466:20]
reg uops_11_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_11_is_unique; // @[util.scala:466:20]
reg uops_11_flush_on_commit; // @[util.scala:466:20]
reg uops_11_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_11_ldst; // @[util.scala:466:20]
reg [5:0] uops_11_lrs1; // @[util.scala:466:20]
reg [5:0] uops_11_lrs2; // @[util.scala:466:20]
reg [5:0] uops_11_lrs3; // @[util.scala:466:20]
reg uops_11_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_11_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_11_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_11_lrs2_rtype; // @[util.scala:466:20]
reg uops_11_frs3_en; // @[util.scala:466:20]
reg uops_11_fp_val; // @[util.scala:466:20]
reg uops_11_fp_single; // @[util.scala:466:20]
reg uops_11_xcpt_pf_if; // @[util.scala:466:20]
reg uops_11_xcpt_ae_if; // @[util.scala:466:20]
reg uops_11_xcpt_ma_if; // @[util.scala:466:20]
reg uops_11_bp_debug_if; // @[util.scala:466:20]
reg uops_11_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_11_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_11_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_12_uopc; // @[util.scala:466:20]
reg [31:0] uops_12_inst; // @[util.scala:466:20]
reg [31:0] uops_12_debug_inst; // @[util.scala:466:20]
reg uops_12_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_12_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_12_iq_type; // @[util.scala:466:20]
reg [9:0] uops_12_fu_code; // @[util.scala:466:20]
reg [3:0] uops_12_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_12_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_12_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_12_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_12_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_12_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_12_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_12_ctrl_is_load; // @[util.scala:466:20]
reg uops_12_ctrl_is_sta; // @[util.scala:466:20]
reg uops_12_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_12_iw_state; // @[util.scala:466:20]
reg uops_12_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_12_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_12_is_br; // @[util.scala:466:20]
reg uops_12_is_jalr; // @[util.scala:466:20]
reg uops_12_is_jal; // @[util.scala:466:20]
reg uops_12_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_12_br_mask; // @[util.scala:466:20]
reg [3:0] uops_12_br_tag; // @[util.scala:466:20]
reg [4:0] uops_12_ftq_idx; // @[util.scala:466:20]
reg uops_12_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_12_pc_lob; // @[util.scala:466:20]
reg uops_12_taken; // @[util.scala:466:20]
reg [19:0] uops_12_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_12_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_12_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_12_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_12_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_12_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_12_pdst; // @[util.scala:466:20]
reg [6:0] uops_12_prs1; // @[util.scala:466:20]
reg [6:0] uops_12_prs2; // @[util.scala:466:20]
reg [6:0] uops_12_prs3; // @[util.scala:466:20]
reg [4:0] uops_12_ppred; // @[util.scala:466:20]
reg uops_12_prs1_busy; // @[util.scala:466:20]
reg uops_12_prs2_busy; // @[util.scala:466:20]
reg uops_12_prs3_busy; // @[util.scala:466:20]
reg uops_12_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_12_stale_pdst; // @[util.scala:466:20]
reg uops_12_exception; // @[util.scala:466:20]
reg [63:0] uops_12_exc_cause; // @[util.scala:466:20]
reg uops_12_bypassable; // @[util.scala:466:20]
reg [4:0] uops_12_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_12_mem_size; // @[util.scala:466:20]
reg uops_12_mem_signed; // @[util.scala:466:20]
reg uops_12_is_fence; // @[util.scala:466:20]
reg uops_12_is_fencei; // @[util.scala:466:20]
reg uops_12_is_amo; // @[util.scala:466:20]
reg uops_12_uses_ldq; // @[util.scala:466:20]
reg uops_12_uses_stq; // @[util.scala:466:20]
reg uops_12_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_12_is_unique; // @[util.scala:466:20]
reg uops_12_flush_on_commit; // @[util.scala:466:20]
reg uops_12_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_12_ldst; // @[util.scala:466:20]
reg [5:0] uops_12_lrs1; // @[util.scala:466:20]
reg [5:0] uops_12_lrs2; // @[util.scala:466:20]
reg [5:0] uops_12_lrs3; // @[util.scala:466:20]
reg uops_12_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_12_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_12_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_12_lrs2_rtype; // @[util.scala:466:20]
reg uops_12_frs3_en; // @[util.scala:466:20]
reg uops_12_fp_val; // @[util.scala:466:20]
reg uops_12_fp_single; // @[util.scala:466:20]
reg uops_12_xcpt_pf_if; // @[util.scala:466:20]
reg uops_12_xcpt_ae_if; // @[util.scala:466:20]
reg uops_12_xcpt_ma_if; // @[util.scala:466:20]
reg uops_12_bp_debug_if; // @[util.scala:466:20]
reg uops_12_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_12_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_12_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_13_uopc; // @[util.scala:466:20]
reg [31:0] uops_13_inst; // @[util.scala:466:20]
reg [31:0] uops_13_debug_inst; // @[util.scala:466:20]
reg uops_13_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_13_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_13_iq_type; // @[util.scala:466:20]
reg [9:0] uops_13_fu_code; // @[util.scala:466:20]
reg [3:0] uops_13_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_13_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_13_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_13_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_13_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_13_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_13_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_13_ctrl_is_load; // @[util.scala:466:20]
reg uops_13_ctrl_is_sta; // @[util.scala:466:20]
reg uops_13_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_13_iw_state; // @[util.scala:466:20]
reg uops_13_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_13_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_13_is_br; // @[util.scala:466:20]
reg uops_13_is_jalr; // @[util.scala:466:20]
reg uops_13_is_jal; // @[util.scala:466:20]
reg uops_13_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_13_br_mask; // @[util.scala:466:20]
reg [3:0] uops_13_br_tag; // @[util.scala:466:20]
reg [4:0] uops_13_ftq_idx; // @[util.scala:466:20]
reg uops_13_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_13_pc_lob; // @[util.scala:466:20]
reg uops_13_taken; // @[util.scala:466:20]
reg [19:0] uops_13_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_13_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_13_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_13_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_13_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_13_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_13_pdst; // @[util.scala:466:20]
reg [6:0] uops_13_prs1; // @[util.scala:466:20]
reg [6:0] uops_13_prs2; // @[util.scala:466:20]
reg [6:0] uops_13_prs3; // @[util.scala:466:20]
reg [4:0] uops_13_ppred; // @[util.scala:466:20]
reg uops_13_prs1_busy; // @[util.scala:466:20]
reg uops_13_prs2_busy; // @[util.scala:466:20]
reg uops_13_prs3_busy; // @[util.scala:466:20]
reg uops_13_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_13_stale_pdst; // @[util.scala:466:20]
reg uops_13_exception; // @[util.scala:466:20]
reg [63:0] uops_13_exc_cause; // @[util.scala:466:20]
reg uops_13_bypassable; // @[util.scala:466:20]
reg [4:0] uops_13_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_13_mem_size; // @[util.scala:466:20]
reg uops_13_mem_signed; // @[util.scala:466:20]
reg uops_13_is_fence; // @[util.scala:466:20]
reg uops_13_is_fencei; // @[util.scala:466:20]
reg uops_13_is_amo; // @[util.scala:466:20]
reg uops_13_uses_ldq; // @[util.scala:466:20]
reg uops_13_uses_stq; // @[util.scala:466:20]
reg uops_13_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_13_is_unique; // @[util.scala:466:20]
reg uops_13_flush_on_commit; // @[util.scala:466:20]
reg uops_13_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_13_ldst; // @[util.scala:466:20]
reg [5:0] uops_13_lrs1; // @[util.scala:466:20]
reg [5:0] uops_13_lrs2; // @[util.scala:466:20]
reg [5:0] uops_13_lrs3; // @[util.scala:466:20]
reg uops_13_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_13_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_13_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_13_lrs2_rtype; // @[util.scala:466:20]
reg uops_13_frs3_en; // @[util.scala:466:20]
reg uops_13_fp_val; // @[util.scala:466:20]
reg uops_13_fp_single; // @[util.scala:466:20]
reg uops_13_xcpt_pf_if; // @[util.scala:466:20]
reg uops_13_xcpt_ae_if; // @[util.scala:466:20]
reg uops_13_xcpt_ma_if; // @[util.scala:466:20]
reg uops_13_bp_debug_if; // @[util.scala:466:20]
reg uops_13_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_13_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_13_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_14_uopc; // @[util.scala:466:20]
reg [31:0] uops_14_inst; // @[util.scala:466:20]
reg [31:0] uops_14_debug_inst; // @[util.scala:466:20]
reg uops_14_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_14_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_14_iq_type; // @[util.scala:466:20]
reg [9:0] uops_14_fu_code; // @[util.scala:466:20]
reg [3:0] uops_14_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_14_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_14_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_14_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_14_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_14_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_14_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_14_ctrl_is_load; // @[util.scala:466:20]
reg uops_14_ctrl_is_sta; // @[util.scala:466:20]
reg uops_14_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_14_iw_state; // @[util.scala:466:20]
reg uops_14_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_14_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_14_is_br; // @[util.scala:466:20]
reg uops_14_is_jalr; // @[util.scala:466:20]
reg uops_14_is_jal; // @[util.scala:466:20]
reg uops_14_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_14_br_mask; // @[util.scala:466:20]
reg [3:0] uops_14_br_tag; // @[util.scala:466:20]
reg [4:0] uops_14_ftq_idx; // @[util.scala:466:20]
reg uops_14_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_14_pc_lob; // @[util.scala:466:20]
reg uops_14_taken; // @[util.scala:466:20]
reg [19:0] uops_14_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_14_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_14_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_14_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_14_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_14_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_14_pdst; // @[util.scala:466:20]
reg [6:0] uops_14_prs1; // @[util.scala:466:20]
reg [6:0] uops_14_prs2; // @[util.scala:466:20]
reg [6:0] uops_14_prs3; // @[util.scala:466:20]
reg [4:0] uops_14_ppred; // @[util.scala:466:20]
reg uops_14_prs1_busy; // @[util.scala:466:20]
reg uops_14_prs2_busy; // @[util.scala:466:20]
reg uops_14_prs3_busy; // @[util.scala:466:20]
reg uops_14_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_14_stale_pdst; // @[util.scala:466:20]
reg uops_14_exception; // @[util.scala:466:20]
reg [63:0] uops_14_exc_cause; // @[util.scala:466:20]
reg uops_14_bypassable; // @[util.scala:466:20]
reg [4:0] uops_14_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_14_mem_size; // @[util.scala:466:20]
reg uops_14_mem_signed; // @[util.scala:466:20]
reg uops_14_is_fence; // @[util.scala:466:20]
reg uops_14_is_fencei; // @[util.scala:466:20]
reg uops_14_is_amo; // @[util.scala:466:20]
reg uops_14_uses_ldq; // @[util.scala:466:20]
reg uops_14_uses_stq; // @[util.scala:466:20]
reg uops_14_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_14_is_unique; // @[util.scala:466:20]
reg uops_14_flush_on_commit; // @[util.scala:466:20]
reg uops_14_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_14_ldst; // @[util.scala:466:20]
reg [5:0] uops_14_lrs1; // @[util.scala:466:20]
reg [5:0] uops_14_lrs2; // @[util.scala:466:20]
reg [5:0] uops_14_lrs3; // @[util.scala:466:20]
reg uops_14_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_14_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_14_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_14_lrs2_rtype; // @[util.scala:466:20]
reg uops_14_frs3_en; // @[util.scala:466:20]
reg uops_14_fp_val; // @[util.scala:466:20]
reg uops_14_fp_single; // @[util.scala:466:20]
reg uops_14_xcpt_pf_if; // @[util.scala:466:20]
reg uops_14_xcpt_ae_if; // @[util.scala:466:20]
reg uops_14_xcpt_ma_if; // @[util.scala:466:20]
reg uops_14_bp_debug_if; // @[util.scala:466:20]
reg uops_14_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_14_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_14_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_15_uopc; // @[util.scala:466:20]
reg [31:0] uops_15_inst; // @[util.scala:466:20]
reg [31:0] uops_15_debug_inst; // @[util.scala:466:20]
reg uops_15_is_rvc; // @[util.scala:466:20]
reg [39:0] uops_15_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_15_iq_type; // @[util.scala:466:20]
reg [9:0] uops_15_fu_code; // @[util.scala:466:20]
reg [3:0] uops_15_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_15_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_15_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_15_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_15_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_15_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_15_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_15_ctrl_is_load; // @[util.scala:466:20]
reg uops_15_ctrl_is_sta; // @[util.scala:466:20]
reg uops_15_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_15_iw_state; // @[util.scala:466:20]
reg uops_15_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_15_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_15_is_br; // @[util.scala:466:20]
reg uops_15_is_jalr; // @[util.scala:466:20]
reg uops_15_is_jal; // @[util.scala:466:20]
reg uops_15_is_sfb; // @[util.scala:466:20]
reg [15:0] uops_15_br_mask; // @[util.scala:466:20]
reg [3:0] uops_15_br_tag; // @[util.scala:466:20]
reg [4:0] uops_15_ftq_idx; // @[util.scala:466:20]
reg uops_15_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_15_pc_lob; // @[util.scala:466:20]
reg uops_15_taken; // @[util.scala:466:20]
reg [19:0] uops_15_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_15_csr_addr; // @[util.scala:466:20]
reg [6:0] uops_15_rob_idx; // @[util.scala:466:20]
reg [4:0] uops_15_ldq_idx; // @[util.scala:466:20]
reg [4:0] uops_15_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_15_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_15_pdst; // @[util.scala:466:20]
reg [6:0] uops_15_prs1; // @[util.scala:466:20]
reg [6:0] uops_15_prs2; // @[util.scala:466:20]
reg [6:0] uops_15_prs3; // @[util.scala:466:20]
reg [4:0] uops_15_ppred; // @[util.scala:466:20]
reg uops_15_prs1_busy; // @[util.scala:466:20]
reg uops_15_prs2_busy; // @[util.scala:466:20]
reg uops_15_prs3_busy; // @[util.scala:466:20]
reg uops_15_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_15_stale_pdst; // @[util.scala:466:20]
reg uops_15_exception; // @[util.scala:466:20]
reg [63:0] uops_15_exc_cause; // @[util.scala:466:20]
reg uops_15_bypassable; // @[util.scala:466:20]
reg [4:0] uops_15_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_15_mem_size; // @[util.scala:466:20]
reg uops_15_mem_signed; // @[util.scala:466:20]
reg uops_15_is_fence; // @[util.scala:466:20]
reg uops_15_is_fencei; // @[util.scala:466:20]
reg uops_15_is_amo; // @[util.scala:466:20]
reg uops_15_uses_ldq; // @[util.scala:466:20]
reg uops_15_uses_stq; // @[util.scala:466:20]
reg uops_15_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_15_is_unique; // @[util.scala:466:20]
reg uops_15_flush_on_commit; // @[util.scala:466:20]
reg uops_15_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_15_ldst; // @[util.scala:466:20]
reg [5:0] uops_15_lrs1; // @[util.scala:466:20]
reg [5:0] uops_15_lrs2; // @[util.scala:466:20]
reg [5:0] uops_15_lrs3; // @[util.scala:466:20]
reg uops_15_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_15_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_15_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_15_lrs2_rtype; // @[util.scala:466:20]
reg uops_15_frs3_en; // @[util.scala:466:20]
reg uops_15_fp_val; // @[util.scala:466:20]
reg uops_15_fp_single; // @[util.scala:466:20]
reg uops_15_xcpt_pf_if; // @[util.scala:466:20]
reg uops_15_xcpt_ae_if; // @[util.scala:466:20]
reg uops_15_xcpt_ma_if; // @[util.scala:466:20]
reg uops_15_bp_debug_if; // @[util.scala:466:20]
reg uops_15_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_15_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_15_debug_tsrc; // @[util.scala:466:20]
reg [3:0] enq_ptr_value; // @[Counter.scala:61:40]
reg [3:0] deq_ptr_value; // @[Counter.scala:61:40]
reg maybe_full; // @[util.scala:470:27]
wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40]
wire _io_empty_T = ~maybe_full; // @[util.scala:470:27, :473:28]
assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:472:33, :473:{25,28}]
assign io_empty_0 = _io_empty_T_1; // @[util.scala:448:7, :473:25]
wire _GEN = ptr_match & maybe_full; // @[util.scala:470:27, :472:33, :474:24]
wire full; // @[util.scala:474:24]
assign full = _GEN; // @[util.scala:474:24]
wire _io_count_T; // @[util.scala:526:32]
assign _io_count_T = _GEN; // @[util.scala:474:24, :526:32]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35]
wire [15:0] _GEN_0 = {{valids_15}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:465:24, :476:42]
wire _GEN_1 = _GEN_0[deq_ptr_value]; // @[Counter.scala:61:40]
wire _do_deq_T = ~_GEN_1; // @[util.scala:476:42]
wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:448:7, :476:{39,42}]
wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:448:7, :476:69]
wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:476:{39,66,69}]
wire do_deq = _do_deq_T_3; // @[util.scala:476:{24,66}]
wire [15:0] _valids_0_T = io_brupdate_b1_mispredict_mask_0 & uops_0_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_0_T_1 = |_valids_0_T; // @[util.scala:118:{51,59}]
wire _valids_0_T_2 = ~_valids_0_T_1; // @[util.scala:118:59, :481:32]
wire _valids_0_T_3 = valids_0 & _valids_0_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_0_T_4 = io_flush_0 & uops_0_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_0_T_5 = ~_valids_0_T_4; // @[util.scala:481:{72,83}]
wire _valids_0_T_6 = _valids_0_T_3 & _valids_0_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_0_br_mask_T_1 = uops_0_br_mask & _uops_0_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_1_T = io_brupdate_b1_mispredict_mask_0 & uops_1_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_1_T_1 = |_valids_1_T; // @[util.scala:118:{51,59}]
wire _valids_1_T_2 = ~_valids_1_T_1; // @[util.scala:118:59, :481:32]
wire _valids_1_T_3 = valids_1 & _valids_1_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_1_T_4 = io_flush_0 & uops_1_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_1_T_5 = ~_valids_1_T_4; // @[util.scala:481:{72,83}]
wire _valids_1_T_6 = _valids_1_T_3 & _valids_1_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_1_br_mask_T_1 = uops_1_br_mask & _uops_1_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_2_T = io_brupdate_b1_mispredict_mask_0 & uops_2_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_2_T_1 = |_valids_2_T; // @[util.scala:118:{51,59}]
wire _valids_2_T_2 = ~_valids_2_T_1; // @[util.scala:118:59, :481:32]
wire _valids_2_T_3 = valids_2 & _valids_2_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_2_T_4 = io_flush_0 & uops_2_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_2_T_5 = ~_valids_2_T_4; // @[util.scala:481:{72,83}]
wire _valids_2_T_6 = _valids_2_T_3 & _valids_2_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_2_br_mask_T_1 = uops_2_br_mask & _uops_2_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_3_T = io_brupdate_b1_mispredict_mask_0 & uops_3_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_3_T_1 = |_valids_3_T; // @[util.scala:118:{51,59}]
wire _valids_3_T_2 = ~_valids_3_T_1; // @[util.scala:118:59, :481:32]
wire _valids_3_T_3 = valids_3 & _valids_3_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_3_T_4 = io_flush_0 & uops_3_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_3_T_5 = ~_valids_3_T_4; // @[util.scala:481:{72,83}]
wire _valids_3_T_6 = _valids_3_T_3 & _valids_3_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_3_br_mask_T_1 = uops_3_br_mask & _uops_3_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_4_T = io_brupdate_b1_mispredict_mask_0 & uops_4_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_4_T_1 = |_valids_4_T; // @[util.scala:118:{51,59}]
wire _valids_4_T_2 = ~_valids_4_T_1; // @[util.scala:118:59, :481:32]
wire _valids_4_T_3 = valids_4 & _valids_4_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_4_T_4 = io_flush_0 & uops_4_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_4_T_5 = ~_valids_4_T_4; // @[util.scala:481:{72,83}]
wire _valids_4_T_6 = _valids_4_T_3 & _valids_4_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_4_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_4_br_mask_T_1 = uops_4_br_mask & _uops_4_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_5_T = io_brupdate_b1_mispredict_mask_0 & uops_5_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_5_T_1 = |_valids_5_T; // @[util.scala:118:{51,59}]
wire _valids_5_T_2 = ~_valids_5_T_1; // @[util.scala:118:59, :481:32]
wire _valids_5_T_3 = valids_5 & _valids_5_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_5_T_4 = io_flush_0 & uops_5_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_5_T_5 = ~_valids_5_T_4; // @[util.scala:481:{72,83}]
wire _valids_5_T_6 = _valids_5_T_3 & _valids_5_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_5_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_5_br_mask_T_1 = uops_5_br_mask & _uops_5_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_6_T = io_brupdate_b1_mispredict_mask_0 & uops_6_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_6_T_1 = |_valids_6_T; // @[util.scala:118:{51,59}]
wire _valids_6_T_2 = ~_valids_6_T_1; // @[util.scala:118:59, :481:32]
wire _valids_6_T_3 = valids_6 & _valids_6_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_6_T_4 = io_flush_0 & uops_6_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_6_T_5 = ~_valids_6_T_4; // @[util.scala:481:{72,83}]
wire _valids_6_T_6 = _valids_6_T_3 & _valids_6_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_6_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_6_br_mask_T_1 = uops_6_br_mask & _uops_6_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_7_T = io_brupdate_b1_mispredict_mask_0 & uops_7_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_7_T_1 = |_valids_7_T; // @[util.scala:118:{51,59}]
wire _valids_7_T_2 = ~_valids_7_T_1; // @[util.scala:118:59, :481:32]
wire _valids_7_T_3 = valids_7 & _valids_7_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_7_T_4 = io_flush_0 & uops_7_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_7_T_5 = ~_valids_7_T_4; // @[util.scala:481:{72,83}]
wire _valids_7_T_6 = _valids_7_T_3 & _valids_7_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_7_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_7_br_mask_T_1 = uops_7_br_mask & _uops_7_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_8_T = io_brupdate_b1_mispredict_mask_0 & uops_8_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_8_T_1 = |_valids_8_T; // @[util.scala:118:{51,59}]
wire _valids_8_T_2 = ~_valids_8_T_1; // @[util.scala:118:59, :481:32]
wire _valids_8_T_3 = valids_8 & _valids_8_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_8_T_4 = io_flush_0 & uops_8_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_8_T_5 = ~_valids_8_T_4; // @[util.scala:481:{72,83}]
wire _valids_8_T_6 = _valids_8_T_3 & _valids_8_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_8_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_8_br_mask_T_1 = uops_8_br_mask & _uops_8_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_9_T = io_brupdate_b1_mispredict_mask_0 & uops_9_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_9_T_1 = |_valids_9_T; // @[util.scala:118:{51,59}]
wire _valids_9_T_2 = ~_valids_9_T_1; // @[util.scala:118:59, :481:32]
wire _valids_9_T_3 = valids_9 & _valids_9_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_9_T_4 = io_flush_0 & uops_9_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_9_T_5 = ~_valids_9_T_4; // @[util.scala:481:{72,83}]
wire _valids_9_T_6 = _valids_9_T_3 & _valids_9_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_9_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_9_br_mask_T_1 = uops_9_br_mask & _uops_9_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_10_T = io_brupdate_b1_mispredict_mask_0 & uops_10_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_10_T_1 = |_valids_10_T; // @[util.scala:118:{51,59}]
wire _valids_10_T_2 = ~_valids_10_T_1; // @[util.scala:118:59, :481:32]
wire _valids_10_T_3 = valids_10 & _valids_10_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_10_T_4 = io_flush_0 & uops_10_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_10_T_5 = ~_valids_10_T_4; // @[util.scala:481:{72,83}]
wire _valids_10_T_6 = _valids_10_T_3 & _valids_10_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_10_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_10_br_mask_T_1 = uops_10_br_mask & _uops_10_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_11_T = io_brupdate_b1_mispredict_mask_0 & uops_11_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_11_T_1 = |_valids_11_T; // @[util.scala:118:{51,59}]
wire _valids_11_T_2 = ~_valids_11_T_1; // @[util.scala:118:59, :481:32]
wire _valids_11_T_3 = valids_11 & _valids_11_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_11_T_4 = io_flush_0 & uops_11_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_11_T_5 = ~_valids_11_T_4; // @[util.scala:481:{72,83}]
wire _valids_11_T_6 = _valids_11_T_3 & _valids_11_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_11_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_11_br_mask_T_1 = uops_11_br_mask & _uops_11_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_12_T = io_brupdate_b1_mispredict_mask_0 & uops_12_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_12_T_1 = |_valids_12_T; // @[util.scala:118:{51,59}]
wire _valids_12_T_2 = ~_valids_12_T_1; // @[util.scala:118:59, :481:32]
wire _valids_12_T_3 = valids_12 & _valids_12_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_12_T_4 = io_flush_0 & uops_12_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_12_T_5 = ~_valids_12_T_4; // @[util.scala:481:{72,83}]
wire _valids_12_T_6 = _valids_12_T_3 & _valids_12_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_12_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_12_br_mask_T_1 = uops_12_br_mask & _uops_12_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_13_T = io_brupdate_b1_mispredict_mask_0 & uops_13_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_13_T_1 = |_valids_13_T; // @[util.scala:118:{51,59}]
wire _valids_13_T_2 = ~_valids_13_T_1; // @[util.scala:118:59, :481:32]
wire _valids_13_T_3 = valids_13 & _valids_13_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_13_T_4 = io_flush_0 & uops_13_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_13_T_5 = ~_valids_13_T_4; // @[util.scala:481:{72,83}]
wire _valids_13_T_6 = _valids_13_T_3 & _valids_13_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_13_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_13_br_mask_T_1 = uops_13_br_mask & _uops_13_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_14_T = io_brupdate_b1_mispredict_mask_0 & uops_14_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_14_T_1 = |_valids_14_T; // @[util.scala:118:{51,59}]
wire _valids_14_T_2 = ~_valids_14_T_1; // @[util.scala:118:59, :481:32]
wire _valids_14_T_3 = valids_14 & _valids_14_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_14_T_4 = io_flush_0 & uops_14_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_14_T_5 = ~_valids_14_T_4; // @[util.scala:481:{72,83}]
wire _valids_14_T_6 = _valids_14_T_3 & _valids_14_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_14_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_14_br_mask_T_1 = uops_14_br_mask & _uops_14_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _valids_15_T = io_brupdate_b1_mispredict_mask_0 & uops_15_br_mask; // @[util.scala:118:51, :448:7, :466:20]
wire _valids_15_T_1 = |_valids_15_T; // @[util.scala:118:{51,59}]
wire _valids_15_T_2 = ~_valids_15_T_1; // @[util.scala:118:59, :481:32]
wire _valids_15_T_3 = valids_15 & _valids_15_T_2; // @[util.scala:465:24, :481:{29,32}]
wire _valids_15_T_4 = io_flush_0 & uops_15_uses_ldq; // @[util.scala:448:7, :466:20, :481:83]
wire _valids_15_T_5 = ~_valids_15_T_4; // @[util.scala:481:{72,83}]
wire _valids_15_T_6 = _valids_15_T_3 & _valids_15_T_5; // @[util.scala:481:{29,69,72}]
wire [15:0] _uops_15_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7]
wire [15:0] _uops_15_br_mask_T_1 = uops_15_br_mask & _uops_15_br_mask_T; // @[util.scala:89:{21,23}, :466:20]
wire [15:0] _uops_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7]
wire [15:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0 & _uops_br_mask_T; // @[util.scala:85:{25,27}, :448:7]
wire wrap = &enq_ptr_value; // @[Counter.scala:61:40, :73:24]
wire [4:0] _GEN_2 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [4:0] _value_T = _GEN_2 + 5'h1; // @[Counter.scala:77:24]
wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24]
wire wrap_1 = &deq_ptr_value; // @[Counter.scala:61:40, :73:24]
wire [4:0] _GEN_3 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [4:0] _value_T_2 = _GEN_3 + 5'h1; // @[Counter.scala:77:24]
wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24]
assign _io_enq_ready_T = ~full; // @[util.scala:474:24, :504:19]
assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:448:7, :504:19]
assign io_deq_bits_uop_uopc_0 = out_uop_uopc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iq_type_0 = out_uop_iq_type; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_fu_code_0 = out_uop_fu_code; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_br_type_0 = out_uop_ctrl_br_type; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_op1_sel_0 = out_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_op2_sel_0 = out_uop_ctrl_op2_sel; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_imm_sel_0 = out_uop_ctrl_imm_sel; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_op_fcn_0 = out_uop_ctrl_op_fcn; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_fcn_dw_0 = out_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_csr_cmd_0 = out_uop_ctrl_csr_cmd; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_is_load_0 = out_uop_ctrl_is_load; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_is_sta_0 = out_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_is_std_0 = out_uop_ctrl_is_std; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iw_state_0 = out_uop_iw_state; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iw_p1_poisoned_0 = out_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iw_p2_poisoned_0 = out_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_br_0 = out_uop_is_br; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_jalr_0 = out_uop_is_jalr; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_jal_0 = out_uop_is_jal; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_csr_addr_0 = out_uop_csr_addr; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_bypassable_0 = out_uop_bypassable; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldst_val_0 = out_uop_ldst_val; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_fp_single_0 = out_uop_fp_single; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_addr_0 = out_addr; // @[util.scala:448:7, :506:17]
assign io_deq_bits_data_0 = out_data; // @[util.scala:448:7, :506:17]
assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:448:7, :506:17]
assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:448:7, :506:17]
assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:448:7, :506:17]
assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:448:7, :506:17]
assign io_deq_bits_way_en = out_way_en; // @[util.scala:448:7, :506:17]
assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:448:7, :506:17]
wire [15:0] out_uop_br_mask; // @[util.scala:506:17]
wire [15:0][6:0] _GEN_4 = {{uops_15_uopc}, {uops_14_uopc}, {uops_13_uopc}, {uops_12_uopc}, {uops_11_uopc}, {uops_10_uopc}, {uops_9_uopc}, {uops_8_uopc}, {uops_7_uopc}, {uops_6_uopc}, {uops_5_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}}; // @[util.scala:466:20, :508:19]
assign out_uop_uopc = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][31:0] _GEN_5 = {{uops_15_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][31:0] _GEN_6 = {{uops_15_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_inst = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_7 = {{uops_15_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_rvc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][39:0] _GEN_8 = {{uops_15_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_pc = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_9 = {{uops_15_iq_type}, {uops_14_iq_type}, {uops_13_iq_type}, {uops_12_iq_type}, {uops_11_iq_type}, {uops_10_iq_type}, {uops_9_iq_type}, {uops_8_iq_type}, {uops_7_iq_type}, {uops_6_iq_type}, {uops_5_iq_type}, {uops_4_iq_type}, {uops_3_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}}; // @[util.scala:466:20, :508:19]
assign out_uop_iq_type = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][9:0] _GEN_10 = {{uops_15_fu_code}, {uops_14_fu_code}, {uops_13_fu_code}, {uops_12_fu_code}, {uops_11_fu_code}, {uops_10_fu_code}, {uops_9_fu_code}, {uops_8_fu_code}, {uops_7_fu_code}, {uops_6_fu_code}, {uops_5_fu_code}, {uops_4_fu_code}, {uops_3_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}}; // @[util.scala:466:20, :508:19]
assign out_uop_fu_code = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_11 = {{uops_15_ctrl_br_type}, {uops_14_ctrl_br_type}, {uops_13_ctrl_br_type}, {uops_12_ctrl_br_type}, {uops_11_ctrl_br_type}, {uops_10_ctrl_br_type}, {uops_9_ctrl_br_type}, {uops_8_ctrl_br_type}, {uops_7_ctrl_br_type}, {uops_6_ctrl_br_type}, {uops_5_ctrl_br_type}, {uops_4_ctrl_br_type}, {uops_3_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_br_type = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_12 = {{uops_15_ctrl_op1_sel}, {uops_14_ctrl_op1_sel}, {uops_13_ctrl_op1_sel}, {uops_12_ctrl_op1_sel}, {uops_11_ctrl_op1_sel}, {uops_10_ctrl_op1_sel}, {uops_9_ctrl_op1_sel}, {uops_8_ctrl_op1_sel}, {uops_7_ctrl_op1_sel}, {uops_6_ctrl_op1_sel}, {uops_5_ctrl_op1_sel}, {uops_4_ctrl_op1_sel}, {uops_3_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op1_sel = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_13 = {{uops_15_ctrl_op2_sel}, {uops_14_ctrl_op2_sel}, {uops_13_ctrl_op2_sel}, {uops_12_ctrl_op2_sel}, {uops_11_ctrl_op2_sel}, {uops_10_ctrl_op2_sel}, {uops_9_ctrl_op2_sel}, {uops_8_ctrl_op2_sel}, {uops_7_ctrl_op2_sel}, {uops_6_ctrl_op2_sel}, {uops_5_ctrl_op2_sel}, {uops_4_ctrl_op2_sel}, {uops_3_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op2_sel = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_14 = {{uops_15_ctrl_imm_sel}, {uops_14_ctrl_imm_sel}, {uops_13_ctrl_imm_sel}, {uops_12_ctrl_imm_sel}, {uops_11_ctrl_imm_sel}, {uops_10_ctrl_imm_sel}, {uops_9_ctrl_imm_sel}, {uops_8_ctrl_imm_sel}, {uops_7_ctrl_imm_sel}, {uops_6_ctrl_imm_sel}, {uops_5_ctrl_imm_sel}, {uops_4_ctrl_imm_sel}, {uops_3_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_imm_sel = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_15 = {{uops_15_ctrl_op_fcn}, {uops_14_ctrl_op_fcn}, {uops_13_ctrl_op_fcn}, {uops_12_ctrl_op_fcn}, {uops_11_ctrl_op_fcn}, {uops_10_ctrl_op_fcn}, {uops_9_ctrl_op_fcn}, {uops_8_ctrl_op_fcn}, {uops_7_ctrl_op_fcn}, {uops_6_ctrl_op_fcn}, {uops_5_ctrl_op_fcn}, {uops_4_ctrl_op_fcn}, {uops_3_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op_fcn = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_16 = {{uops_15_ctrl_fcn_dw}, {uops_14_ctrl_fcn_dw}, {uops_13_ctrl_fcn_dw}, {uops_12_ctrl_fcn_dw}, {uops_11_ctrl_fcn_dw}, {uops_10_ctrl_fcn_dw}, {uops_9_ctrl_fcn_dw}, {uops_8_ctrl_fcn_dw}, {uops_7_ctrl_fcn_dw}, {uops_6_ctrl_fcn_dw}, {uops_5_ctrl_fcn_dw}, {uops_4_ctrl_fcn_dw}, {uops_3_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_fcn_dw = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_17 = {{uops_15_ctrl_csr_cmd}, {uops_14_ctrl_csr_cmd}, {uops_13_ctrl_csr_cmd}, {uops_12_ctrl_csr_cmd}, {uops_11_ctrl_csr_cmd}, {uops_10_ctrl_csr_cmd}, {uops_9_ctrl_csr_cmd}, {uops_8_ctrl_csr_cmd}, {uops_7_ctrl_csr_cmd}, {uops_6_ctrl_csr_cmd}, {uops_5_ctrl_csr_cmd}, {uops_4_ctrl_csr_cmd}, {uops_3_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_csr_cmd = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_18 = {{uops_15_ctrl_is_load}, {uops_14_ctrl_is_load}, {uops_13_ctrl_is_load}, {uops_12_ctrl_is_load}, {uops_11_ctrl_is_load}, {uops_10_ctrl_is_load}, {uops_9_ctrl_is_load}, {uops_8_ctrl_is_load}, {uops_7_ctrl_is_load}, {uops_6_ctrl_is_load}, {uops_5_ctrl_is_load}, {uops_4_ctrl_is_load}, {uops_3_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_load = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_19 = {{uops_15_ctrl_is_sta}, {uops_14_ctrl_is_sta}, {uops_13_ctrl_is_sta}, {uops_12_ctrl_is_sta}, {uops_11_ctrl_is_sta}, {uops_10_ctrl_is_sta}, {uops_9_ctrl_is_sta}, {uops_8_ctrl_is_sta}, {uops_7_ctrl_is_sta}, {uops_6_ctrl_is_sta}, {uops_5_ctrl_is_sta}, {uops_4_ctrl_is_sta}, {uops_3_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_sta = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_20 = {{uops_15_ctrl_is_std}, {uops_14_ctrl_is_std}, {uops_13_ctrl_is_std}, {uops_12_ctrl_is_std}, {uops_11_ctrl_is_std}, {uops_10_ctrl_is_std}, {uops_9_ctrl_is_std}, {uops_8_ctrl_is_std}, {uops_7_ctrl_is_std}, {uops_6_ctrl_is_std}, {uops_5_ctrl_is_std}, {uops_4_ctrl_is_std}, {uops_3_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_std = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_21 = {{uops_15_iw_state}, {uops_14_iw_state}, {uops_13_iw_state}, {uops_12_iw_state}, {uops_11_iw_state}, {uops_10_iw_state}, {uops_9_iw_state}, {uops_8_iw_state}, {uops_7_iw_state}, {uops_6_iw_state}, {uops_5_iw_state}, {uops_4_iw_state}, {uops_3_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_state = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_22 = {{uops_15_iw_p1_poisoned}, {uops_14_iw_p1_poisoned}, {uops_13_iw_p1_poisoned}, {uops_12_iw_p1_poisoned}, {uops_11_iw_p1_poisoned}, {uops_10_iw_p1_poisoned}, {uops_9_iw_p1_poisoned}, {uops_8_iw_p1_poisoned}, {uops_7_iw_p1_poisoned}, {uops_6_iw_p1_poisoned}, {uops_5_iw_p1_poisoned}, {uops_4_iw_p1_poisoned}, {uops_3_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_p1_poisoned = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_23 = {{uops_15_iw_p2_poisoned}, {uops_14_iw_p2_poisoned}, {uops_13_iw_p2_poisoned}, {uops_12_iw_p2_poisoned}, {uops_11_iw_p2_poisoned}, {uops_10_iw_p2_poisoned}, {uops_9_iw_p2_poisoned}, {uops_8_iw_p2_poisoned}, {uops_7_iw_p2_poisoned}, {uops_6_iw_p2_poisoned}, {uops_5_iw_p2_poisoned}, {uops_4_iw_p2_poisoned}, {uops_3_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_p2_poisoned = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_24 = {{uops_15_is_br}, {uops_14_is_br}, {uops_13_is_br}, {uops_12_is_br}, {uops_11_is_br}, {uops_10_is_br}, {uops_9_is_br}, {uops_8_is_br}, {uops_7_is_br}, {uops_6_is_br}, {uops_5_is_br}, {uops_4_is_br}, {uops_3_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_br = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_25 = {{uops_15_is_jalr}, {uops_14_is_jalr}, {uops_13_is_jalr}, {uops_12_is_jalr}, {uops_11_is_jalr}, {uops_10_is_jalr}, {uops_9_is_jalr}, {uops_8_is_jalr}, {uops_7_is_jalr}, {uops_6_is_jalr}, {uops_5_is_jalr}, {uops_4_is_jalr}, {uops_3_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_jalr = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_26 = {{uops_15_is_jal}, {uops_14_is_jal}, {uops_13_is_jal}, {uops_12_is_jal}, {uops_11_is_jal}, {uops_10_is_jal}, {uops_9_is_jal}, {uops_8_is_jal}, {uops_7_is_jal}, {uops_6_is_jal}, {uops_5_is_jal}, {uops_4_is_jal}, {uops_3_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_jal = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_27 = {{uops_15_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_sfb = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][15:0] _GEN_28 = {{uops_15_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:466:20, :508:19]
assign out_uop_br_mask = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_29 = {{uops_15_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:466:20, :508:19]
assign out_uop_br_tag = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_30 = {{uops_15_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_ftq_idx = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_31 = {{uops_15_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_edge_inst = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_32 = {{uops_15_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:466:20, :508:19]
assign out_uop_pc_lob = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_33 = {{uops_15_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:466:20, :508:19]
assign out_uop_taken = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][19:0] _GEN_34 = {{uops_15_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:466:20, :508:19]
assign out_uop_imm_packed = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][11:0] _GEN_35 = {{uops_15_csr_addr}, {uops_14_csr_addr}, {uops_13_csr_addr}, {uops_12_csr_addr}, {uops_11_csr_addr}, {uops_10_csr_addr}, {uops_9_csr_addr}, {uops_8_csr_addr}, {uops_7_csr_addr}, {uops_6_csr_addr}, {uops_5_csr_addr}, {uops_4_csr_addr}, {uops_3_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}}; // @[util.scala:466:20, :508:19]
assign out_uop_csr_addr = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_36 = {{uops_15_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_rob_idx = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_37 = {{uops_15_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldq_idx = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_38 = {{uops_15_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_stq_idx = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_39 = {{uops_15_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_rxq_idx = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_40 = {{uops_15_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:466:20, :508:19]
assign out_uop_pdst = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_41 = {{uops_15_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs1 = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_42 = {{uops_15_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs2 = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_43 = {{uops_15_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs3 = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_44 = {{uops_15_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:466:20, :508:19]
assign out_uop_ppred = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_45 = {{uops_15_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs1_busy = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_46 = {{uops_15_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs2_busy = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_47 = {{uops_15_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs3_busy = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_48 = {{uops_15_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_ppred_busy = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_49 = {{uops_15_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:466:20, :508:19]
assign out_uop_stale_pdst = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_50 = {{uops_15_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:466:20, :508:19]
assign out_uop_exception = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][63:0] _GEN_51 = {{uops_15_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:466:20, :508:19]
assign out_uop_exc_cause = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_52 = {{uops_15_bypassable}, {uops_14_bypassable}, {uops_13_bypassable}, {uops_12_bypassable}, {uops_11_bypassable}, {uops_10_bypassable}, {uops_9_bypassable}, {uops_8_bypassable}, {uops_7_bypassable}, {uops_6_bypassable}, {uops_5_bypassable}, {uops_4_bypassable}, {uops_3_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}}; // @[util.scala:466:20, :508:19]
assign out_uop_bypassable = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_53 = {{uops_15_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_cmd = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_54 = {{uops_15_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_size = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_55 = {{uops_15_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_signed = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_56 = {{uops_15_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_fence = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_57 = {{uops_15_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_fencei = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_58 = {{uops_15_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_amo = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_59 = {{uops_15_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:466:20, :508:19]
assign out_uop_uses_ldq = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_60 = {{uops_15_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:466:20, :508:19]
assign out_uop_uses_stq = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_61 = {{uops_15_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_sys_pc2epc = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_62 = {{uops_15_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_unique = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_63 = {{uops_15_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:466:20, :508:19]
assign out_uop_flush_on_commit = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_64 = {{uops_15_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst_is_rs1 = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_65 = {{uops_15_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_66 = {{uops_15_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs1 = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_67 = {{uops_15_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs2 = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_68 = {{uops_15_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs3 = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_69 = {{uops_15_ldst_val}, {uops_14_ldst_val}, {uops_13_ldst_val}, {uops_12_ldst_val}, {uops_11_ldst_val}, {uops_10_ldst_val}, {uops_9_ldst_val}, {uops_8_ldst_val}, {uops_7_ldst_val}, {uops_6_ldst_val}, {uops_5_ldst_val}, {uops_4_ldst_val}, {uops_3_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst_val = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_70 = {{uops_15_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_dst_rtype = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_71 = {{uops_15_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs1_rtype = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_72 = {{uops_15_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs2_rtype = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_73 = {{uops_15_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:466:20, :508:19]
assign out_uop_frs3_en = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_74 = {{uops_15_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:466:20, :508:19]
assign out_uop_fp_val = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_75 = {{uops_15_fp_single}, {uops_14_fp_single}, {uops_13_fp_single}, {uops_12_fp_single}, {uops_11_fp_single}, {uops_10_fp_single}, {uops_9_fp_single}, {uops_8_fp_single}, {uops_7_fp_single}, {uops_6_fp_single}, {uops_5_fp_single}, {uops_4_fp_single}, {uops_3_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}}; // @[util.scala:466:20, :508:19]
assign out_uop_fp_single = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_76 = {{uops_15_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_pf_if = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_77 = {{uops_15_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_ae_if = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_78 = {{uops_15_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_ma_if = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_79 = {{uops_15_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_bp_debug_if = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_80 = {{uops_15_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_bp_xcpt_if = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_81 = {{uops_15_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_fsrc = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_82 = {{uops_15_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_tsrc = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40]
wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:448:7, :476:69, :509:30]
wire _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_1; // @[util.scala:476:42, :509:{30,40}]
wire [15:0] _io_deq_valid_T_2 = io_brupdate_b1_mispredict_mask_0 & out_uop_br_mask; // @[util.scala:118:51, :448:7, :506:17]
wire _io_deq_valid_T_3 = |_io_deq_valid_T_2; // @[util.scala:118:{51,59}]
wire _io_deq_valid_T_4 = ~_io_deq_valid_T_3; // @[util.scala:118:59, :509:68]
wire _io_deq_valid_T_5 = _io_deq_valid_T_1 & _io_deq_valid_T_4; // @[util.scala:509:{40,65,68}]
wire _io_deq_valid_T_6 = io_flush_0 & out_uop_uses_ldq; // @[util.scala:448:7, :506:17, :509:122]
wire _io_deq_valid_T_7 = ~_io_deq_valid_T_6; // @[util.scala:509:{111,122}]
assign _io_deq_valid_T_8 = _io_deq_valid_T_5 & _io_deq_valid_T_7; // @[util.scala:509:{65,108,111}]
assign io_deq_valid_0 = _io_deq_valid_T_8; // @[util.scala:448:7, :509:108]
wire [15:0] _io_deq_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7]
assign _io_deq_bits_uop_br_mask_T_1 = out_uop_br_mask & _io_deq_bits_uop_br_mask_T; // @[util.scala:85:{25,27}, :506:17]
assign io_deq_bits_uop_br_mask_0 = _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25, :448:7]
wire [4:0] _ptr_diff_T = _GEN_2 - _GEN_3; // @[Counter.scala:77:24]
wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:524:40]
wire [4:0] _io_count_T_1 = {_io_count_T, ptr_diff}; // @[util.scala:524:40, :526:{20,32}]
assign io_count = _io_count_T_1[3:0]; // @[util.scala:448:7, :526:{14,20}]
wire _GEN_83 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40]
wire _GEN_84 = do_enq & _GEN_83; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_85 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40]
wire _GEN_86 = do_enq & _GEN_85; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_87 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40]
wire _GEN_88 = do_enq & _GEN_87; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_89 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40]
wire _GEN_90 = do_enq & _GEN_89; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_91 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40]
wire _GEN_92 = do_enq & _GEN_91; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_93 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40]
wire _GEN_94 = do_enq & _GEN_93; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_95 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40]
wire _GEN_96 = do_enq & _GEN_95; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_97 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40]
wire _GEN_98 = do_enq & _GEN_97; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_99 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40]
wire _GEN_100 = do_enq & _GEN_99; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_101 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40]
wire _GEN_102 = do_enq & _GEN_101; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_103 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40]
wire _GEN_104 = do_enq & _GEN_103; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_105 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40]
wire _GEN_106 = do_enq & _GEN_105; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_107 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40]
wire _GEN_108 = do_enq & _GEN_107; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_109 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40]
wire _GEN_110 = do_enq & _GEN_109; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_111 = enq_ptr_value == 4'hE; // @[Counter.scala:61:40]
wire _GEN_112 = do_enq & _GEN_111; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_113 = do_enq & (&enq_ptr_value); // @[Counter.scala:61:40]
always @(posedge clock) begin // @[util.scala:448:7]
if (reset) begin // @[util.scala:448:7]
valids_0 <= 1'h0; // @[util.scala:465:24]
valids_1 <= 1'h0; // @[util.scala:465:24]
valids_2 <= 1'h0; // @[util.scala:465:24]
valids_3 <= 1'h0; // @[util.scala:465:24]
valids_4 <= 1'h0; // @[util.scala:465:24]
valids_5 <= 1'h0; // @[util.scala:465:24]
valids_6 <= 1'h0; // @[util.scala:465:24]
valids_7 <= 1'h0; // @[util.scala:465:24]
valids_8 <= 1'h0; // @[util.scala:465:24]
valids_9 <= 1'h0; // @[util.scala:465:24]
valids_10 <= 1'h0; // @[util.scala:465:24]
valids_11 <= 1'h0; // @[util.scala:465:24]
valids_12 <= 1'h0; // @[util.scala:465:24]
valids_13 <= 1'h0; // @[util.scala:465:24]
valids_14 <= 1'h0; // @[util.scala:465:24]
valids_15 <= 1'h0; // @[util.scala:465:24]
enq_ptr_value <= 4'h0; // @[Counter.scala:61:40]
deq_ptr_value <= 4'h0; // @[Counter.scala:61:40]
maybe_full <= 1'h0; // @[util.scala:470:27]
end
else begin // @[util.scala:448:7]
valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_84 | _valids_0_T_6); // @[Counter.scala:61:40]
valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_86 | _valids_1_T_6); // @[Counter.scala:61:40]
valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_88 | _valids_2_T_6); // @[Counter.scala:61:40]
valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_90 | _valids_3_T_6); // @[Counter.scala:61:40]
valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_92 | _valids_4_T_6); // @[Counter.scala:61:40]
valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_94 | _valids_5_T_6); // @[Counter.scala:61:40]
valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_96 | _valids_6_T_6); // @[Counter.scala:61:40]
valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_98 | _valids_7_T_6); // @[Counter.scala:61:40]
valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_100 | _valids_8_T_6); // @[Counter.scala:61:40]
valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_102 | _valids_9_T_6); // @[Counter.scala:61:40]
valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_104 | _valids_10_T_6); // @[Counter.scala:61:40]
valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_106 | _valids_11_T_6); // @[Counter.scala:61:40]
valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_108 | _valids_12_T_6); // @[Counter.scala:61:40]
valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_110 | _valids_13_T_6); // @[Counter.scala:61:40]
valids_14 <= ~(do_deq & deq_ptr_value == 4'hE) & (_GEN_112 | _valids_14_T_6); // @[Counter.scala:61:40]
valids_15 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_113 | _valids_15_T_6); // @[Counter.scala:61:40]
if (do_enq) // @[util.scala:475:24]
enq_ptr_value <= _value_T_1; // @[Counter.scala:61:40, :77:24]
if (do_deq) // @[util.scala:476:24]
deq_ptr_value <= _value_T_3; // @[Counter.scala:61:40, :77:24]
if (~(do_enq == do_deq)) // @[util.scala:470:27, :475:24, :476:24, :500:{16,28}, :501:16]
maybe_full <= do_enq; // @[util.scala:470:27, :475:24]
end
if (_GEN_84) begin // @[util.scala:481:16, :487:17, :489:33]
uops_0_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_0_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_0_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_0_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_0_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_0_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_0_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_0_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_0_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_0_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_0_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_83) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_0) // @[util.scala:465:24]
uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_86) begin // @[util.scala:481:16, :487:17, :489:33]
uops_1_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_1_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_1_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_1_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_1_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_1_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_1_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_1_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_1_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_1_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_1_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_85) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_1) // @[util.scala:465:24]
uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_88) begin // @[util.scala:481:16, :487:17, :489:33]
uops_2_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_2_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_2_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_2_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_2_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_2_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_2_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_2_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_2_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_2_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_2_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_87) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_2) // @[util.scala:465:24]
uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_90) begin // @[util.scala:481:16, :487:17, :489:33]
uops_3_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_3_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_3_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_3_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_3_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_3_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_3_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_3_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_3_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_3_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_3_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_3_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_3_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_89) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_3) // @[util.scala:465:24]
uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_92) begin // @[util.scala:481:16, :487:17, :489:33]
uops_4_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_4_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_4_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_4_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_4_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_4_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_4_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_4_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_4_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_4_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_4_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_4_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_4_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_91) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_4) // @[util.scala:465:24]
uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_94) begin // @[util.scala:481:16, :487:17, :489:33]
uops_5_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_5_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_5_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_5_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_5_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_5_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_5_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_5_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_5_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_5_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_5_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_5_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_5_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_93) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_5) // @[util.scala:465:24]
uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_96) begin // @[util.scala:481:16, :487:17, :489:33]
uops_6_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_6_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_6_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_6_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_6_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_6_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_6_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_6_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_6_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_6_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_6_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_6_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_6_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_95) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_6) // @[util.scala:465:24]
uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_98) begin // @[util.scala:481:16, :487:17, :489:33]
uops_7_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_7_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_7_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_7_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_7_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_7_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_7_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_7_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_7_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_7_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_7_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_7_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_7_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_97) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_7) // @[util.scala:465:24]
uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_100) begin // @[util.scala:481:16, :487:17, :489:33]
uops_8_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_8_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_8_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_8_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_8_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_8_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_8_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_8_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_8_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_8_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_8_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_8_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_8_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_99) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_8) // @[util.scala:465:24]
uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_102) begin // @[util.scala:481:16, :487:17, :489:33]
uops_9_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_9_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_9_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_9_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_9_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_9_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_9_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_9_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_9_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_9_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_9_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_9_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_9_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_101) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_9) // @[util.scala:465:24]
uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_104) begin // @[util.scala:481:16, :487:17, :489:33]
uops_10_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_10_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_10_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_10_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_10_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_10_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_10_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_10_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_10_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_10_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_10_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_10_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_10_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_103) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_10) // @[util.scala:465:24]
uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_106) begin // @[util.scala:481:16, :487:17, :489:33]
uops_11_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_11_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_11_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_11_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_11_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_11_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_11_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_11_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_11_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_11_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_11_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_11_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_11_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_105) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_11) // @[util.scala:465:24]
uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_108) begin // @[util.scala:481:16, :487:17, :489:33]
uops_12_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_12_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_12_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_12_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_12_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_12_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_12_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_12_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_12_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_12_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_12_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_12_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_12_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_107) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_12) // @[util.scala:465:24]
uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_110) begin // @[util.scala:481:16, :487:17, :489:33]
uops_13_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_13_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_13_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_13_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_13_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_13_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_13_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_13_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_13_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_13_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_13_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_13_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_13_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_109) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_13) // @[util.scala:465:24]
uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_112) begin // @[util.scala:481:16, :487:17, :489:33]
uops_14_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_14_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_14_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_14_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_14_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_14_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_14_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_14_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_14_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_14_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_14_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_14_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_14_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_111) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_14) // @[util.scala:465:24]
uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_113) begin // @[util.scala:481:16, :487:17, :489:33]
uops_15_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_15_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_15_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_15_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_15_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_15_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_15_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_15_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_15_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_15_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_15_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_15_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_15_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_15_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_15_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_15_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_15_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_15_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_15_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_15_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_15_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_15_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_15_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_15_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_15_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_15_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_15_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_15_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_15_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_15_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_15_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_15_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_15_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_15_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_15_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_15_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_15_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_15_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_15_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_15_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_15_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_15_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_15_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_15_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_15_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_15_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_15_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_15_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_15_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_15_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_15_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_15_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_15_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_15_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_15_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_15_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_15_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_15_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_15_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_15_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_15_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_15_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_15_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_15_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_15_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_15_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_15_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_15_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & (&enq_ptr_value)) // @[Counter.scala:61:40]
uops_15_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_15) // @[util.scala:465:24]
uops_15_br_mask <= _uops_15_br_mask_T_1; // @[util.scala:89:21, :466:20]
always @(posedge)
ram_16x141 ram_ext ( // @[util.scala:464:20]
.R0_addr (deq_ptr_value), // @[Counter.scala:61:40]
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_ram_ext_R0_data),
.W0_addr (enq_ptr_value), // @[Counter.scala:61:40]
.W0_en (do_enq), // @[util.scala:475:24]
.W0_clk (clock),
.W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:448:7, :464:20]
); // @[util.scala:464:20]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:448:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uopc = io_deq_bits_uop_uopc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iq_type = io_deq_bits_uop_iq_type_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fu_code = io_deq_bits_uop_fu_code_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_br_type = io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op1_sel = io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op2_sel = io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_imm_sel = io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op_fcn = io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_fcn_dw = io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_csr_cmd = io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_load = io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_sta = io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_std = io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_state = io_deq_bits_uop_iw_state_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_p1_poisoned = io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_p2_poisoned = io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_br = io_deq_bits_uop_is_br_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_jalr = io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_jal = io_deq_bits_uop_is_jal_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:448:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:448:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7]
assign io_deq_bits_uop_csr_addr = io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:448:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bypassable = io_deq_bits_uop_bypassable_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:448:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst_val = io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fp_single = io_deq_bits_uop_fp_single_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7]
assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:448:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:448:7]
assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:448:7]
assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:448:7]
assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7]
assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:448:7]
assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:448:7]
assign io_empty = io_empty_0; // @[util.scala:448:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_93 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_110
connect io_out_sink_valid_1.clock, clock
connect io_out_sink_valid_1.reset, reset
connect io_out_sink_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_93( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_110 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BankBinder :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_43
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
connect nodeOut, nodeIn | module BankBinder( // @[BankBinder.scala:61:9]
input clock, // @[BankBinder.scala:61:9]
input reset, // @[BankBinder.scala:61:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[BankBinder.scala:61:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BankBinder.scala:61:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BankBinder.scala:61:9]
wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BankBinder.scala:61:9]
wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BankBinder.scala:61:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BankBinder.scala:61:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BankBinder.scala:61:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BankBinder.scala:61:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BankBinder.scala:61:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[BankBinder.scala:61:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[BankBinder.scala:61:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[BankBinder.scala:61:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[BankBinder.scala:61:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[BankBinder.scala:61:9]
wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[BankBinder.scala:61:9]
wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[BankBinder.scala:61:9]
wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[BankBinder.scala:61:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[BankBinder.scala:61:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[BankBinder.scala:61:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[BankBinder.scala:61:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[BankBinder.scala:61:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BankBinder.scala:61:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BankBinder.scala:61:9]
wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BankBinder.scala:61:9]
wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BankBinder.scala:61:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BankBinder.scala:61:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BankBinder.scala:61:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BankBinder.scala:61:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BankBinder.scala:61:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[BankBinder.scala:61:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[BankBinder.scala:61:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[BankBinder.scala:61:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[BankBinder.scala:61:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[BankBinder.scala:61:9]
wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[BankBinder.scala:61:9]
wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[BankBinder.scala:61:9]
wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[BankBinder.scala:61:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[BankBinder.scala:61:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[BankBinder.scala:61:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[BankBinder.scala:61:9]
wire auto_in_a_ready_0; // @[BankBinder.scala:61:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[BankBinder.scala:61:9]
wire [1:0] auto_in_d_bits_param_0; // @[BankBinder.scala:61:9]
wire [2:0] auto_in_d_bits_size_0; // @[BankBinder.scala:61:9]
wire [3:0] auto_in_d_bits_source_0; // @[BankBinder.scala:61:9]
wire auto_in_d_bits_sink_0; // @[BankBinder.scala:61:9]
wire auto_in_d_bits_denied_0; // @[BankBinder.scala:61:9]
wire [63:0] auto_in_d_bits_data_0; // @[BankBinder.scala:61:9]
wire auto_in_d_bits_corrupt_0; // @[BankBinder.scala:61:9]
wire auto_in_d_valid_0; // @[BankBinder.scala:61:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[BankBinder.scala:61:9]
wire [2:0] auto_out_a_bits_param_0; // @[BankBinder.scala:61:9]
wire [2:0] auto_out_a_bits_size_0; // @[BankBinder.scala:61:9]
wire [3:0] auto_out_a_bits_source_0; // @[BankBinder.scala:61:9]
wire [31:0] auto_out_a_bits_address_0; // @[BankBinder.scala:61:9]
wire [7:0] auto_out_a_bits_mask_0; // @[BankBinder.scala:61:9]
wire [63:0] auto_out_a_bits_data_0; // @[BankBinder.scala:61:9]
wire auto_out_a_bits_corrupt_0; // @[BankBinder.scala:61:9]
wire auto_out_a_valid_0; // @[BankBinder.scala:61:9]
wire auto_out_d_ready_0; // @[BankBinder.scala:61:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BankBinder.scala:61:9]
assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BankBinder.scala:61:9]
assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[BankBinder.scala:61:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[BankBinder.scala:61:9]
assign nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_denied = nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
TLMonitor_43 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_a_ready = auto_in_a_ready_0; // @[BankBinder.scala:61:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BankBinder.scala:61:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BankBinder.scala:61:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[BankBinder.scala:61:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[BankBinder.scala:61:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[BankBinder.scala:61:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_43 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_55
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_43( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_55 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget32_9 :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_67
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
wire repeat : UInt<1>
inst repeated_repeater of Repeater_TLBundleA_a32d256s2k3z4u_3
connect repeated_repeater.clock, clock
connect repeated_repeater.reset, reset
connect repeated_repeater.io.repeat, repeat
connect repeated_repeater.io.enq, anonIn.a
wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}
connect cated.bits, repeated_repeater.io.deq.bits
connect cated.valid, repeated_repeater.io.deq.valid
connect repeated_repeater.io.deq.ready, cated.ready
node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 255, 64)
node _cated_bits_data_T_1 = bits(anonIn.a.bits.data, 63, 0)
node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1)
connect cated.bits.data, _cated_bits_data_T_2
node _repeat_hasData_opdata_T = bits(cated.bits.opcode, 2, 2)
node repeat_hasData = eq(_repeat_hasData_opdata_T, UInt<1>(0h0))
node _repeat_limit_T = dshl(UInt<5>(0h1f), cated.bits.size)
node _repeat_limit_T_1 = bits(_repeat_limit_T, 4, 0)
node _repeat_limit_T_2 = not(_repeat_limit_T_1)
node repeat_limit = shr(_repeat_limit_T_2, 3)
regreset repeat_count : UInt<2>, clock, reset, UInt<2>(0h0)
node repeat_first = eq(repeat_count, UInt<1>(0h0))
node _repeat_last_T = eq(repeat_count, repeat_limit)
node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0))
node repeat_last = or(_repeat_last_T, _repeat_last_T_1)
node _repeat_T = and(anonOut.a.ready, anonOut.a.valid)
when _repeat_T :
node _repeat_count_T = add(repeat_count, UInt<1>(0h1))
node _repeat_count_T_1 = tail(_repeat_count_T, 1)
connect repeat_count, _repeat_count_T_1
when repeat_last :
connect repeat_count, UInt<1>(0h0)
node repeat_sel = bits(cated.bits.address, 4, 3)
node repeat_index = or(repeat_sel, repeat_count)
connect anonOut.a.bits, cated.bits
connect anonOut.a.valid, cated.valid
connect cated.ready, anonOut.a.ready
node _repeat_anonOut_a_bits_data_mux_T = bits(cated.bits.data, 63, 0)
node _repeat_anonOut_a_bits_data_mux_T_1 = bits(cated.bits.data, 127, 64)
node _repeat_anonOut_a_bits_data_mux_T_2 = bits(cated.bits.data, 191, 128)
node _repeat_anonOut_a_bits_data_mux_T_3 = bits(cated.bits.data, 255, 192)
wire repeat_anonOut_a_bits_data_mux : UInt<64>[4]
connect repeat_anonOut_a_bits_data_mux[0], _repeat_anonOut_a_bits_data_mux_T
connect repeat_anonOut_a_bits_data_mux[1], _repeat_anonOut_a_bits_data_mux_T_1
connect repeat_anonOut_a_bits_data_mux[2], _repeat_anonOut_a_bits_data_mux_T_2
connect repeat_anonOut_a_bits_data_mux[3], _repeat_anonOut_a_bits_data_mux_T_3
connect anonOut.a.bits.data, repeat_anonOut_a_bits_data_mux[repeat_index]
node _repeat_anonOut_a_bits_mask_mux_T = bits(cated.bits.mask, 7, 0)
node _repeat_anonOut_a_bits_mask_mux_T_1 = bits(cated.bits.mask, 15, 8)
node _repeat_anonOut_a_bits_mask_mux_T_2 = bits(cated.bits.mask, 23, 16)
node _repeat_anonOut_a_bits_mask_mux_T_3 = bits(cated.bits.mask, 31, 24)
wire repeat_anonOut_a_bits_mask_mux : UInt<8>[4]
connect repeat_anonOut_a_bits_mask_mux[0], _repeat_anonOut_a_bits_mask_mux_T
connect repeat_anonOut_a_bits_mask_mux[1], _repeat_anonOut_a_bits_mask_mux_T_1
connect repeat_anonOut_a_bits_mask_mux[2], _repeat_anonOut_a_bits_mask_mux_T_2
connect repeat_anonOut_a_bits_mask_mux[3], _repeat_anonOut_a_bits_mask_mux_T_3
connect anonOut.a.bits.mask, repeat_anonOut_a_bits_mask_mux[repeat_index]
node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0))
connect repeat, _repeat_T_1
node hasData = bits(anonOut.d.bits.opcode, 0, 0)
node _limit_T = dshl(UInt<5>(0h1f), anonOut.d.bits.size)
node _limit_T_1 = bits(_limit_T, 4, 0)
node _limit_T_2 = not(_limit_T_1)
node limit = shr(_limit_T_2, 3)
regreset count : UInt<2>, clock, reset, UInt<2>(0h0)
node first = eq(count, UInt<1>(0h0))
node _last_T = eq(count, limit)
node _last_T_1 = eq(hasData, UInt<1>(0h0))
node last = or(_last_T, _last_T_1)
node _enable_T = xor(count, UInt<1>(0h0))
node _enable_T_1 = and(_enable_T, limit)
node _enable_T_2 = orr(_enable_T_1)
node enable_0 = eq(_enable_T_2, UInt<1>(0h0))
node _enable_T_3 = xor(count, UInt<1>(0h1))
node _enable_T_4 = and(_enable_T_3, limit)
node _enable_T_5 = orr(_enable_T_4)
node enable_1 = eq(_enable_T_5, UInt<1>(0h0))
node _enable_T_6 = xor(count, UInt<2>(0h2))
node _enable_T_7 = and(_enable_T_6, limit)
node _enable_T_8 = orr(_enable_T_7)
node enable_2 = eq(_enable_T_8, UInt<1>(0h0))
node _enable_T_9 = xor(count, UInt<2>(0h3))
node _enable_T_10 = and(_enable_T_9, limit)
node _enable_T_11 = orr(_enable_T_10)
node enable_3 = eq(_enable_T_11, UInt<1>(0h0))
regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0)
node corrupt_out = or(anonOut.d.bits.corrupt, corrupt_reg)
node _T = and(anonOut.d.ready, anonOut.d.valid)
when _T :
node _count_T = add(count, UInt<1>(0h1))
node _count_T_1 = tail(_count_T, 1)
connect count, _count_T_1
connect corrupt_reg, corrupt_out
when last :
connect count, UInt<1>(0h0)
connect corrupt_reg, UInt<1>(0h0)
node _anonOut_d_ready_T = eq(last, UInt<1>(0h0))
node _anonOut_d_ready_T_1 = or(anonIn.d.ready, _anonOut_d_ready_T)
connect anonOut.d.ready, _anonOut_d_ready_T_1
node _anonIn_d_valid_T = and(anonOut.d.valid, last)
connect anonIn.d.valid, _anonIn_d_valid_T
connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt
connect anonIn.d.bits.data, anonOut.d.bits.data
connect anonIn.d.bits.denied, anonOut.d.bits.denied
connect anonIn.d.bits.sink, anonOut.d.bits.sink
connect anonIn.d.bits.source, anonOut.d.bits.source
connect anonIn.d.bits.size, anonOut.d.bits.size
connect anonIn.d.bits.param, anonOut.d.bits.param
connect anonIn.d.bits.opcode, anonOut.d.bits.opcode
regreset anonIn_d_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0)
node _anonIn_d_bits_data_masked_enable_T = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_0 = or(enable_0, _anonIn_d_bits_data_masked_enable_T)
node _anonIn_d_bits_data_masked_enable_T_1 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_1 = or(enable_1, _anonIn_d_bits_data_masked_enable_T_1)
node _anonIn_d_bits_data_masked_enable_T_2 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_2 = or(enable_2, _anonIn_d_bits_data_masked_enable_T_2)
node _anonIn_d_bits_data_masked_enable_T_3 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_3 = or(enable_3, _anonIn_d_bits_data_masked_enable_T_3)
wire anonIn_d_bits_data_odata_0 : UInt
connect anonIn_d_bits_data_odata_0, anonOut.d.bits.data
wire anonIn_d_bits_data_odata_1 : UInt
connect anonIn_d_bits_data_odata_1, anonOut.d.bits.data
wire anonIn_d_bits_data_odata_2 : UInt
connect anonIn_d_bits_data_odata_2, anonOut.d.bits.data
wire anonIn_d_bits_data_odata_3 : UInt
connect anonIn_d_bits_data_odata_3, anonOut.d.bits.data
reg anonIn_d_bits_data_rdata : UInt<64>[3], clock
node anonIn_d_bits_data_mdata_0 = mux(anonIn_d_bits_data_masked_enable_0, anonIn_d_bits_data_odata_0, anonIn_d_bits_data_rdata[0])
node anonIn_d_bits_data_mdata_1 = mux(anonIn_d_bits_data_masked_enable_1, anonIn_d_bits_data_odata_1, anonIn_d_bits_data_rdata[1])
node anonIn_d_bits_data_mdata_2 = mux(anonIn_d_bits_data_masked_enable_2, anonIn_d_bits_data_odata_2, anonIn_d_bits_data_rdata[2])
node anonIn_d_bits_data_mdata_3 = mux(anonIn_d_bits_data_masked_enable_3, anonIn_d_bits_data_odata_3, anonOut.d.bits.data)
node _anonIn_d_bits_data_T = and(anonOut.d.ready, anonOut.d.valid)
node _anonIn_d_bits_data_T_1 = eq(last, UInt<1>(0h0))
node _anonIn_d_bits_data_T_2 = and(_anonIn_d_bits_data_T, _anonIn_d_bits_data_T_1)
when _anonIn_d_bits_data_T_2 :
connect anonIn_d_bits_data_rdata_written_once, UInt<1>(0h1)
connect anonIn_d_bits_data_rdata[0], anonIn_d_bits_data_mdata_0
connect anonIn_d_bits_data_rdata[1], anonIn_d_bits_data_mdata_1
connect anonIn_d_bits_data_rdata[2], anonIn_d_bits_data_mdata_2
node anonIn_d_bits_data_lo = cat(anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0)
node anonIn_d_bits_data_hi = cat(anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2)
node _anonIn_d_bits_data_T_3 = cat(anonIn_d_bits_data_hi, anonIn_d_bits_data_lo)
connect anonIn.d.bits.data, _anonIn_d_bits_data_T_3
connect anonIn.d.bits.corrupt, corrupt_out
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<256>(0h0)
connect _WIRE.bits.mask, UInt<32>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<2>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<256>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<2>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<2>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<2>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_10.bits.sink, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLWidthWidget32_9( // @[WidthWidget.scala:27:9]
input clock, // @[WidthWidget.scala:27:9]
input reset, // @[WidthWidget.scala:27:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [255:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [255:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [255:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [255:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [1:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [255:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [255:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [1:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [255:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9]
wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [255:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
wire corrupt_out; // @[WidthWidget.scala:47:36]
assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25]
wire cated_valid; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] cated_bits_source; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] cated_bits_address; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
wire cated_bits_corrupt; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_2 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_3 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire _repeat_T_1; // @[WidthWidget.scala:148:7]
wire repeat_0; // @[WidthWidget.scala:159:26]
assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25]
wire [255:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39]
assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25]
wire [31:0] cated_bits_mask; // @[WidthWidget.scala:161:25]
wire [255:0] cated_bits_data; // @[WidthWidget.scala:161:25]
wire [191:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[255:64]; // @[Repeater.scala:36:26]
wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31]
assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31]
assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39]
wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25]
wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [19:0] _repeat_limit_T = 20'h1F << cated_bits_size; // @[package.scala:243:71]
wire [4:0] _repeat_limit_T_1 = _repeat_limit_T[4:0]; // @[package.scala:243:{71,76}]
wire [4:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}]
wire [1:0] repeat_limit = _repeat_limit_T_2[4:3]; // @[package.scala:243:46]
reg [1:0] repeat_count; // @[WidthWidget.scala:105:26]
wire repeat_first = repeat_count == 2'h0; // @[WidthWidget.scala:105:26, :106:25]
wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25]
wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38]
wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}]
wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35]
wire [2:0] _repeat_count_T = {1'h0, repeat_count} + 3'h1; // @[WidthWidget.scala:105:26, :110:24]
wire [1:0] _repeat_count_T_1 = _repeat_count_T[1:0]; // @[WidthWidget.scala:110:24]
wire [1:0] repeat_sel = cated_bits_address[4:3]; // @[WidthWidget.scala:116:39, :161:25]
wire [1:0] repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_2 = cated_bits_data[191:128]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_2 = _repeat_anonOut_a_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_3 = cated_bits_data[255:192]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_3 = _repeat_anonOut_a_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}]
wire [3:0][63:0] _GEN = {{repeat_anonOut_a_bits_data_mux_3}, {repeat_anonOut_a_bits_data_mux_2}, {repeat_anonOut_a_bits_data_mux_1}, {repeat_anonOut_a_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30]
assign anonOut_a_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_2 = cated_bits_mask[23:16]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_2 = _repeat_anonOut_a_bits_mask_mux_T_2; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_3 = cated_bits_mask[31:24]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_3 = _repeat_anonOut_a_bits_mask_mux_T_3; // @[WidthWidget.scala:128:{43,55}]
wire [3:0][7:0] _GEN_0 = {{repeat_anonOut_a_bits_mask_mux_3}, {repeat_anonOut_a_bits_mask_mux_2}, {repeat_anonOut_a_bits_mask_mux_1}, {repeat_anonOut_a_bits_mask_mux_0}}; // @[WidthWidget.scala:128:43, :140:53]
assign anonOut_a_bits_mask = _GEN_0[repeat_index]; // @[WidthWidget.scala:126:24, :140:53]
assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7]
assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26]
wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [19:0] _limit_T = 20'h1F << anonOut_d_bits_size; // @[package.scala:243:71]
wire [4:0] _limit_T_1 = _limit_T[4:0]; // @[package.scala:243:{71,76}]
wire [4:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}]
wire [1:0] limit = _limit_T_2[4:3]; // @[package.scala:243:46]
reg [1:0] count; // @[WidthWidget.scala:40:27]
wire [1:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56]
wire first = count == 2'h0; // @[WidthWidget.scala:40:27, :41:26]
wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26]
wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39]
wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}]
wire [1:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_2 = |_enable_T_1; // @[WidthWidget.scala:43:{63,72}]
wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_3 = {count[1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_5 = |_enable_T_4; // @[WidthWidget.scala:43:{63,72}]
wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_6 = count ^ 2'h2; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_8 = |_enable_T_7; // @[WidthWidget.scala:43:{63,72}]
wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_9 = ~count; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_11 = |_enable_T_10; // @[WidthWidget.scala:43:{63,72}]
wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}]
reg corrupt_reg; // @[WidthWidget.scala:45:32]
assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36]
assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36]
wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [2:0] _count_T = {1'h0, count} + 3'h1; // @[WidthWidget.scala:40:27, :50:24]
wire [1:0] _count_T_1 = _count_T[1:0]; // @[WidthWidget.scala:50:24]
wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32]
assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}]
assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29]
assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41]
wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_2 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_2 = enable_2 | _anonIn_d_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_3 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_3 = enable_3 | _anonIn_d_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}]
reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24]
reg [63:0] anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:66:24]
reg [63:0] anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:66:24]
wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_2 = anonIn_d_bits_data_masked_enable_2 ? anonIn_d_bits_data_odata_2 : anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_3 = anonIn_d_bits_data_masked_enable_3 ? anonIn_d_bits_data_odata_3 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88]
wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32]
wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35]
wire [127:0] anonIn_d_bits_data_lo = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12]
wire [127:0] anonIn_d_bits_data_hi = {anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12]
assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_hi, anonIn_d_bits_data_lo}; // @[WidthWidget.scala:73:12]
assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
always @(posedge clock) begin // @[WidthWidget.scala:27:9]
if (reset) begin // @[WidthWidget.scala:27:9]
repeat_count <= 2'h0; // @[WidthWidget.scala:105:26]
count <= 2'h0; // @[WidthWidget.scala:40:27]
corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32]
anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41]
end
else begin // @[WidthWidget.scala:27:9]
if (_repeat_T) // @[Decoupled.scala:51:35]
repeat_count <= repeat_last ? 2'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}]
if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35]
count <= last ? 2'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17]
corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23]
end
anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
end
if (_anonIn_d_bits_data_T_2) begin // @[WidthWidget.scala:69:23]
anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88]
anonIn_d_bits_data_rdata_1 <= anonIn_d_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88]
anonIn_d_bits_data_rdata_2 <= anonIn_d_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88]
end
always @(posedge)
TLMonitor_67 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Repeater_TLBundleA_a32d256s2k3z4u_3 repeated_repeater ( // @[Repeater.scala:36:26]
.clock (clock),
.reset (reset),
.io_repeat (repeat_0), // @[WidthWidget.scala:159:26]
.io_enq_ready (anonIn_a_ready),
.io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25]
.io_deq_valid (cated_valid),
.io_deq_bits_opcode (cated_bits_opcode),
.io_deq_bits_param (cated_bits_param),
.io_deq_bits_size (cated_bits_size),
.io_deq_bits_source (cated_bits_source),
.io_deq_bits_address (cated_bits_address),
.io_deq_bits_mask (cated_bits_mask),
.io_deq_bits_data (_repeated_repeater_io_deq_bits_data),
.io_deq_bits_corrupt (cated_bits_corrupt)
); // @[Repeater.scala:36:26]
assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s1k3z4c_7 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_81
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s1k3z4c_7
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s1k3z4c_7
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
inst nodeIn_b_q of Queue2_TLBundleB_a32d64s1k3z4c_7
connect nodeIn_b_q.clock, clock
connect nodeIn_b_q.reset, reset
connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid
connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt
connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data
connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask
connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address
connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source
connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size
connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param
connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode
connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready
connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits
connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid
connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready
inst nodeOut_c_q of Queue2_TLBundleC_a32d64s1k3z4c_7
connect nodeOut_c_q.clock, clock
connect nodeOut_c_q.reset, reset
connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid
connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt
connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data
connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address
connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source
connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size
connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param
connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode
connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready
connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits
connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid
connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready
inst nodeOut_e_q of Queue2_TLBundleE_a32d64s1k3z4c_7
connect nodeOut_e_q.clock, clock
connect nodeOut_e_q.reset, reset
connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid
connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink
connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready
connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits
connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid
connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready | module TLBuffer_a32d64s1k3z4c_7( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[Buffer.scala:40:9]
wire auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[Buffer.scala:40:9]
wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9]
wire nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[Buffer.scala:40:9]
wire nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_b_valid_0; // @[Buffer.scala:40:9]
wire auto_in_c_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire auto_in_e_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_b_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_c_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
TLMonitor_81 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s1k3z4c_7 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s1k3z4c_7 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d64s1k3z4c_7 nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_b_ready),
.io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_b_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_b_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17]
.io_enq_bits_mask (nodeOut_b_bits_mask), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_b_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_b_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_b_valid),
.io_deq_bits_opcode (nodeIn_b_bits_opcode),
.io_deq_bits_param (nodeIn_b_bits_param),
.io_deq_bits_size (nodeIn_b_bits_size),
.io_deq_bits_source (nodeIn_b_bits_source),
.io_deq_bits_address (nodeIn_b_bits_address),
.io_deq_bits_mask (nodeIn_b_bits_mask),
.io_deq_bits_data (nodeIn_b_bits_data),
.io_deq_bits_corrupt (nodeIn_b_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d64s1k3z4c_7 nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_c_ready),
.io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_c_valid),
.io_deq_bits_opcode (nodeOut_c_bits_opcode),
.io_deq_bits_param (nodeOut_c_bits_param),
.io_deq_bits_size (nodeOut_c_bits_size),
.io_deq_bits_source (nodeOut_c_bits_source),
.io_deq_bits_address (nodeOut_c_bits_address),
.io_deq_bits_data (nodeOut_c_bits_data),
.io_deq_bits_corrupt (nodeOut_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d64s1k3z4c_7 nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_e_ready),
.io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_e_valid),
.io_deq_bits_sink (nodeOut_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_100 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_100( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLAtomicAutomata_cbus :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_23
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
wire initval : { state : UInt<2>}
connect initval.state, UInt<1>(0h0)
wire _cam_s_WIRE : { state : UInt<2>}[1]
connect _cam_s_WIRE[0], initval
regreset cam_s : { state : UInt<2>}[1], clock, reset, _cam_s_WIRE
reg cam_a : { bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, fifoId : UInt<1>, lut : UInt<4>}[1], clock
reg cam_d : { data : UInt<64>, denied : UInt<1>, corrupt : UInt<1>}[1], clock
node cam_free_0 = eq(cam_s[0].state, UInt<1>(0h0))
node cam_amo_0 = eq(cam_s[0].state, UInt<2>(0h2))
node _cam_abusy_T = eq(cam_s[0].state, UInt<2>(0h3))
node _cam_abusy_T_1 = eq(cam_s[0].state, UInt<2>(0h2))
node cam_abusy_0 = or(_cam_abusy_T, _cam_abusy_T_1)
node cam_dmatch_0 = neq(cam_s[0].state, UInt<1>(0h0))
node _a_canLogical_T = leq(UInt<1>(0h0), nodeIn.a.bits.size)
node _a_canLogical_T_1 = leq(nodeIn.a.bits.size, UInt<2>(0h3))
node _a_canLogical_T_2 = and(_a_canLogical_T, _a_canLogical_T_1)
node _a_canLogical_T_3 = or(UInt<1>(0h0), _a_canLogical_T_2)
node _a_canLogical_T_4 = xor(nodeIn.a.bits.address, UInt<13>(0h1000))
node _a_canLogical_T_5 = cvt(_a_canLogical_T_4)
node _a_canLogical_T_6 = and(_a_canLogical_T_5, asSInt(UInt<30>(0h1a011000)))
node _a_canLogical_T_7 = asSInt(_a_canLogical_T_6)
node _a_canLogical_T_8 = eq(_a_canLogical_T_7, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_9 = xor(nodeIn.a.bits.address, UInt<29>(0h10000000))
node _a_canLogical_T_10 = cvt(_a_canLogical_T_9)
node _a_canLogical_T_11 = and(_a_canLogical_T_10, asSInt(UInt<30>(0h1a011000)))
node _a_canLogical_T_12 = asSInt(_a_canLogical_T_11)
node _a_canLogical_T_13 = eq(_a_canLogical_T_12, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_14 = or(_a_canLogical_T_8, _a_canLogical_T_13)
node _a_canLogical_T_15 = and(_a_canLogical_T_3, _a_canLogical_T_14)
node _a_canLogical_T_16 = or(UInt<1>(0h0), UInt<1>(0h0))
node _a_canLogical_T_17 = xor(nodeIn.a.bits.address, UInt<1>(0h0))
node _a_canLogical_T_18 = cvt(_a_canLogical_T_17)
node _a_canLogical_T_19 = and(_a_canLogical_T_18, asSInt(UInt<30>(0h1a001000)))
node _a_canLogical_T_20 = asSInt(_a_canLogical_T_19)
node _a_canLogical_T_21 = eq(_a_canLogical_T_20, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_22 = xor(nodeIn.a.bits.address, UInt<17>(0h10000))
node _a_canLogical_T_23 = cvt(_a_canLogical_T_22)
node _a_canLogical_T_24 = and(_a_canLogical_T_23, asSInt(UInt<30>(0h1a010000)))
node _a_canLogical_T_25 = asSInt(_a_canLogical_T_24)
node _a_canLogical_T_26 = eq(_a_canLogical_T_25, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_27 = xor(nodeIn.a.bits.address, UInt<26>(0h2000000))
node _a_canLogical_T_28 = cvt(_a_canLogical_T_27)
node _a_canLogical_T_29 = and(_a_canLogical_T_28, asSInt(UInt<30>(0h1a010000)))
node _a_canLogical_T_30 = asSInt(_a_canLogical_T_29)
node _a_canLogical_T_31 = eq(_a_canLogical_T_30, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_32 = xor(nodeIn.a.bits.address, UInt<26>(0h2010000))
node _a_canLogical_T_33 = cvt(_a_canLogical_T_32)
node _a_canLogical_T_34 = and(_a_canLogical_T_33, asSInt(UInt<30>(0h1a011000)))
node _a_canLogical_T_35 = asSInt(_a_canLogical_T_34)
node _a_canLogical_T_36 = eq(_a_canLogical_T_35, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_37 = xor(nodeIn.a.bits.address, UInt<28>(0h8000000))
node _a_canLogical_T_38 = cvt(_a_canLogical_T_37)
node _a_canLogical_T_39 = and(_a_canLogical_T_38, asSInt(UInt<30>(0h18000000)))
node _a_canLogical_T_40 = asSInt(_a_canLogical_T_39)
node _a_canLogical_T_41 = eq(_a_canLogical_T_40, asSInt(UInt<1>(0h0)))
node _a_canLogical_T_42 = or(_a_canLogical_T_21, _a_canLogical_T_26)
node _a_canLogical_T_43 = or(_a_canLogical_T_42, _a_canLogical_T_31)
node _a_canLogical_T_44 = or(_a_canLogical_T_43, _a_canLogical_T_36)
node _a_canLogical_T_45 = or(_a_canLogical_T_44, _a_canLogical_T_41)
node _a_canLogical_T_46 = and(_a_canLogical_T_16, _a_canLogical_T_45)
node _a_canLogical_T_47 = or(UInt<1>(0h0), _a_canLogical_T_15)
node _a_canLogical_T_48 = or(_a_canLogical_T_47, _a_canLogical_T_46)
node a_canLogical = and(UInt<1>(0h1), _a_canLogical_T_48)
node _a_canArithmetic_T = leq(UInt<1>(0h0), nodeIn.a.bits.size)
node _a_canArithmetic_T_1 = leq(nodeIn.a.bits.size, UInt<2>(0h3))
node _a_canArithmetic_T_2 = and(_a_canArithmetic_T, _a_canArithmetic_T_1)
node _a_canArithmetic_T_3 = or(UInt<1>(0h0), _a_canArithmetic_T_2)
node _a_canArithmetic_T_4 = xor(nodeIn.a.bits.address, UInt<13>(0h1000))
node _a_canArithmetic_T_5 = cvt(_a_canArithmetic_T_4)
node _a_canArithmetic_T_6 = and(_a_canArithmetic_T_5, asSInt(UInt<30>(0h1a011000)))
node _a_canArithmetic_T_7 = asSInt(_a_canArithmetic_T_6)
node _a_canArithmetic_T_8 = eq(_a_canArithmetic_T_7, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_9 = xor(nodeIn.a.bits.address, UInt<29>(0h10000000))
node _a_canArithmetic_T_10 = cvt(_a_canArithmetic_T_9)
node _a_canArithmetic_T_11 = and(_a_canArithmetic_T_10, asSInt(UInt<30>(0h1a011000)))
node _a_canArithmetic_T_12 = asSInt(_a_canArithmetic_T_11)
node _a_canArithmetic_T_13 = eq(_a_canArithmetic_T_12, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_14 = or(_a_canArithmetic_T_8, _a_canArithmetic_T_13)
node _a_canArithmetic_T_15 = and(_a_canArithmetic_T_3, _a_canArithmetic_T_14)
node _a_canArithmetic_T_16 = or(UInt<1>(0h0), UInt<1>(0h0))
node _a_canArithmetic_T_17 = xor(nodeIn.a.bits.address, UInt<1>(0h0))
node _a_canArithmetic_T_18 = cvt(_a_canArithmetic_T_17)
node _a_canArithmetic_T_19 = and(_a_canArithmetic_T_18, asSInt(UInt<30>(0h1a001000)))
node _a_canArithmetic_T_20 = asSInt(_a_canArithmetic_T_19)
node _a_canArithmetic_T_21 = eq(_a_canArithmetic_T_20, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_22 = xor(nodeIn.a.bits.address, UInt<17>(0h10000))
node _a_canArithmetic_T_23 = cvt(_a_canArithmetic_T_22)
node _a_canArithmetic_T_24 = and(_a_canArithmetic_T_23, asSInt(UInt<30>(0h1a010000)))
node _a_canArithmetic_T_25 = asSInt(_a_canArithmetic_T_24)
node _a_canArithmetic_T_26 = eq(_a_canArithmetic_T_25, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_27 = xor(nodeIn.a.bits.address, UInt<26>(0h2000000))
node _a_canArithmetic_T_28 = cvt(_a_canArithmetic_T_27)
node _a_canArithmetic_T_29 = and(_a_canArithmetic_T_28, asSInt(UInt<30>(0h1a010000)))
node _a_canArithmetic_T_30 = asSInt(_a_canArithmetic_T_29)
node _a_canArithmetic_T_31 = eq(_a_canArithmetic_T_30, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_32 = xor(nodeIn.a.bits.address, UInt<26>(0h2010000))
node _a_canArithmetic_T_33 = cvt(_a_canArithmetic_T_32)
node _a_canArithmetic_T_34 = and(_a_canArithmetic_T_33, asSInt(UInt<30>(0h1a011000)))
node _a_canArithmetic_T_35 = asSInt(_a_canArithmetic_T_34)
node _a_canArithmetic_T_36 = eq(_a_canArithmetic_T_35, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_37 = xor(nodeIn.a.bits.address, UInt<28>(0h8000000))
node _a_canArithmetic_T_38 = cvt(_a_canArithmetic_T_37)
node _a_canArithmetic_T_39 = and(_a_canArithmetic_T_38, asSInt(UInt<30>(0h18000000)))
node _a_canArithmetic_T_40 = asSInt(_a_canArithmetic_T_39)
node _a_canArithmetic_T_41 = eq(_a_canArithmetic_T_40, asSInt(UInt<1>(0h0)))
node _a_canArithmetic_T_42 = or(_a_canArithmetic_T_21, _a_canArithmetic_T_26)
node _a_canArithmetic_T_43 = or(_a_canArithmetic_T_42, _a_canArithmetic_T_31)
node _a_canArithmetic_T_44 = or(_a_canArithmetic_T_43, _a_canArithmetic_T_36)
node _a_canArithmetic_T_45 = or(_a_canArithmetic_T_44, _a_canArithmetic_T_41)
node _a_canArithmetic_T_46 = and(_a_canArithmetic_T_16, _a_canArithmetic_T_45)
node _a_canArithmetic_T_47 = or(UInt<1>(0h0), _a_canArithmetic_T_15)
node _a_canArithmetic_T_48 = or(_a_canArithmetic_T_47, _a_canArithmetic_T_46)
node a_canArithmetic = and(UInt<1>(0h1), _a_canArithmetic_T_48)
node a_isLogical = eq(nodeIn.a.bits.opcode, UInt<2>(0h3))
node a_isArithmetic = eq(nodeIn.a.bits.opcode, UInt<2>(0h2))
node _a_isSupported_T = mux(a_isArithmetic, a_canArithmetic, UInt<1>(0h1))
node a_isSupported = mux(a_isLogical, a_canLogical, _a_isSupported_T)
node _a_cam_por_put_T = or(UInt<1>(0h0), cam_amo_0)
node _a_cam_sel_put_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node a_cam_sel_put_0 = and(cam_amo_0, _a_cam_sel_put_T)
node _a_fifoId_T = xor(nodeIn.a.bits.address, UInt<1>(0h0))
node _a_fifoId_T_1 = cvt(_a_fifoId_T)
node _a_fifoId_T_2 = and(_a_fifoId_T_1, asSInt(UInt<1>(0h0)))
node _a_fifoId_T_3 = asSInt(_a_fifoId_T_2)
node _a_fifoId_T_4 = eq(_a_fifoId_T_3, asSInt(UInt<1>(0h0)))
node _a_cam_busy_T = eq(cam_a[0].fifoId, UInt<1>(0h0))
node a_cam_busy = and(cam_abusy_0, _a_cam_busy_T)
node _a_cam_por_free_T = or(UInt<1>(0h0), cam_free_0)
node _a_cam_sel_free_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node a_cam_sel_free_0 = and(cam_free_0, _a_cam_sel_free_T)
node _indexes_T = bits(cam_a[0].bits.data, 0, 0)
node _indexes_T_1 = bits(cam_d[0].data, 0, 0)
node indexes_0 = cat(_indexes_T, _indexes_T_1)
node _indexes_T_2 = bits(cam_a[0].bits.data, 1, 1)
node _indexes_T_3 = bits(cam_d[0].data, 1, 1)
node indexes_1 = cat(_indexes_T_2, _indexes_T_3)
node _indexes_T_4 = bits(cam_a[0].bits.data, 2, 2)
node _indexes_T_5 = bits(cam_d[0].data, 2, 2)
node indexes_2 = cat(_indexes_T_4, _indexes_T_5)
node _indexes_T_6 = bits(cam_a[0].bits.data, 3, 3)
node _indexes_T_7 = bits(cam_d[0].data, 3, 3)
node indexes_3 = cat(_indexes_T_6, _indexes_T_7)
node _indexes_T_8 = bits(cam_a[0].bits.data, 4, 4)
node _indexes_T_9 = bits(cam_d[0].data, 4, 4)
node indexes_4 = cat(_indexes_T_8, _indexes_T_9)
node _indexes_T_10 = bits(cam_a[0].bits.data, 5, 5)
node _indexes_T_11 = bits(cam_d[0].data, 5, 5)
node indexes_5 = cat(_indexes_T_10, _indexes_T_11)
node _indexes_T_12 = bits(cam_a[0].bits.data, 6, 6)
node _indexes_T_13 = bits(cam_d[0].data, 6, 6)
node indexes_6 = cat(_indexes_T_12, _indexes_T_13)
node _indexes_T_14 = bits(cam_a[0].bits.data, 7, 7)
node _indexes_T_15 = bits(cam_d[0].data, 7, 7)
node indexes_7 = cat(_indexes_T_14, _indexes_T_15)
node _indexes_T_16 = bits(cam_a[0].bits.data, 8, 8)
node _indexes_T_17 = bits(cam_d[0].data, 8, 8)
node indexes_8 = cat(_indexes_T_16, _indexes_T_17)
node _indexes_T_18 = bits(cam_a[0].bits.data, 9, 9)
node _indexes_T_19 = bits(cam_d[0].data, 9, 9)
node indexes_9 = cat(_indexes_T_18, _indexes_T_19)
node _indexes_T_20 = bits(cam_a[0].bits.data, 10, 10)
node _indexes_T_21 = bits(cam_d[0].data, 10, 10)
node indexes_10 = cat(_indexes_T_20, _indexes_T_21)
node _indexes_T_22 = bits(cam_a[0].bits.data, 11, 11)
node _indexes_T_23 = bits(cam_d[0].data, 11, 11)
node indexes_11 = cat(_indexes_T_22, _indexes_T_23)
node _indexes_T_24 = bits(cam_a[0].bits.data, 12, 12)
node _indexes_T_25 = bits(cam_d[0].data, 12, 12)
node indexes_12 = cat(_indexes_T_24, _indexes_T_25)
node _indexes_T_26 = bits(cam_a[0].bits.data, 13, 13)
node _indexes_T_27 = bits(cam_d[0].data, 13, 13)
node indexes_13 = cat(_indexes_T_26, _indexes_T_27)
node _indexes_T_28 = bits(cam_a[0].bits.data, 14, 14)
node _indexes_T_29 = bits(cam_d[0].data, 14, 14)
node indexes_14 = cat(_indexes_T_28, _indexes_T_29)
node _indexes_T_30 = bits(cam_a[0].bits.data, 15, 15)
node _indexes_T_31 = bits(cam_d[0].data, 15, 15)
node indexes_15 = cat(_indexes_T_30, _indexes_T_31)
node _indexes_T_32 = bits(cam_a[0].bits.data, 16, 16)
node _indexes_T_33 = bits(cam_d[0].data, 16, 16)
node indexes_16 = cat(_indexes_T_32, _indexes_T_33)
node _indexes_T_34 = bits(cam_a[0].bits.data, 17, 17)
node _indexes_T_35 = bits(cam_d[0].data, 17, 17)
node indexes_17 = cat(_indexes_T_34, _indexes_T_35)
node _indexes_T_36 = bits(cam_a[0].bits.data, 18, 18)
node _indexes_T_37 = bits(cam_d[0].data, 18, 18)
node indexes_18 = cat(_indexes_T_36, _indexes_T_37)
node _indexes_T_38 = bits(cam_a[0].bits.data, 19, 19)
node _indexes_T_39 = bits(cam_d[0].data, 19, 19)
node indexes_19 = cat(_indexes_T_38, _indexes_T_39)
node _indexes_T_40 = bits(cam_a[0].bits.data, 20, 20)
node _indexes_T_41 = bits(cam_d[0].data, 20, 20)
node indexes_20 = cat(_indexes_T_40, _indexes_T_41)
node _indexes_T_42 = bits(cam_a[0].bits.data, 21, 21)
node _indexes_T_43 = bits(cam_d[0].data, 21, 21)
node indexes_21 = cat(_indexes_T_42, _indexes_T_43)
node _indexes_T_44 = bits(cam_a[0].bits.data, 22, 22)
node _indexes_T_45 = bits(cam_d[0].data, 22, 22)
node indexes_22 = cat(_indexes_T_44, _indexes_T_45)
node _indexes_T_46 = bits(cam_a[0].bits.data, 23, 23)
node _indexes_T_47 = bits(cam_d[0].data, 23, 23)
node indexes_23 = cat(_indexes_T_46, _indexes_T_47)
node _indexes_T_48 = bits(cam_a[0].bits.data, 24, 24)
node _indexes_T_49 = bits(cam_d[0].data, 24, 24)
node indexes_24 = cat(_indexes_T_48, _indexes_T_49)
node _indexes_T_50 = bits(cam_a[0].bits.data, 25, 25)
node _indexes_T_51 = bits(cam_d[0].data, 25, 25)
node indexes_25 = cat(_indexes_T_50, _indexes_T_51)
node _indexes_T_52 = bits(cam_a[0].bits.data, 26, 26)
node _indexes_T_53 = bits(cam_d[0].data, 26, 26)
node indexes_26 = cat(_indexes_T_52, _indexes_T_53)
node _indexes_T_54 = bits(cam_a[0].bits.data, 27, 27)
node _indexes_T_55 = bits(cam_d[0].data, 27, 27)
node indexes_27 = cat(_indexes_T_54, _indexes_T_55)
node _indexes_T_56 = bits(cam_a[0].bits.data, 28, 28)
node _indexes_T_57 = bits(cam_d[0].data, 28, 28)
node indexes_28 = cat(_indexes_T_56, _indexes_T_57)
node _indexes_T_58 = bits(cam_a[0].bits.data, 29, 29)
node _indexes_T_59 = bits(cam_d[0].data, 29, 29)
node indexes_29 = cat(_indexes_T_58, _indexes_T_59)
node _indexes_T_60 = bits(cam_a[0].bits.data, 30, 30)
node _indexes_T_61 = bits(cam_d[0].data, 30, 30)
node indexes_30 = cat(_indexes_T_60, _indexes_T_61)
node _indexes_T_62 = bits(cam_a[0].bits.data, 31, 31)
node _indexes_T_63 = bits(cam_d[0].data, 31, 31)
node indexes_31 = cat(_indexes_T_62, _indexes_T_63)
node _indexes_T_64 = bits(cam_a[0].bits.data, 32, 32)
node _indexes_T_65 = bits(cam_d[0].data, 32, 32)
node indexes_32 = cat(_indexes_T_64, _indexes_T_65)
node _indexes_T_66 = bits(cam_a[0].bits.data, 33, 33)
node _indexes_T_67 = bits(cam_d[0].data, 33, 33)
node indexes_33 = cat(_indexes_T_66, _indexes_T_67)
node _indexes_T_68 = bits(cam_a[0].bits.data, 34, 34)
node _indexes_T_69 = bits(cam_d[0].data, 34, 34)
node indexes_34 = cat(_indexes_T_68, _indexes_T_69)
node _indexes_T_70 = bits(cam_a[0].bits.data, 35, 35)
node _indexes_T_71 = bits(cam_d[0].data, 35, 35)
node indexes_35 = cat(_indexes_T_70, _indexes_T_71)
node _indexes_T_72 = bits(cam_a[0].bits.data, 36, 36)
node _indexes_T_73 = bits(cam_d[0].data, 36, 36)
node indexes_36 = cat(_indexes_T_72, _indexes_T_73)
node _indexes_T_74 = bits(cam_a[0].bits.data, 37, 37)
node _indexes_T_75 = bits(cam_d[0].data, 37, 37)
node indexes_37 = cat(_indexes_T_74, _indexes_T_75)
node _indexes_T_76 = bits(cam_a[0].bits.data, 38, 38)
node _indexes_T_77 = bits(cam_d[0].data, 38, 38)
node indexes_38 = cat(_indexes_T_76, _indexes_T_77)
node _indexes_T_78 = bits(cam_a[0].bits.data, 39, 39)
node _indexes_T_79 = bits(cam_d[0].data, 39, 39)
node indexes_39 = cat(_indexes_T_78, _indexes_T_79)
node _indexes_T_80 = bits(cam_a[0].bits.data, 40, 40)
node _indexes_T_81 = bits(cam_d[0].data, 40, 40)
node indexes_40 = cat(_indexes_T_80, _indexes_T_81)
node _indexes_T_82 = bits(cam_a[0].bits.data, 41, 41)
node _indexes_T_83 = bits(cam_d[0].data, 41, 41)
node indexes_41 = cat(_indexes_T_82, _indexes_T_83)
node _indexes_T_84 = bits(cam_a[0].bits.data, 42, 42)
node _indexes_T_85 = bits(cam_d[0].data, 42, 42)
node indexes_42 = cat(_indexes_T_84, _indexes_T_85)
node _indexes_T_86 = bits(cam_a[0].bits.data, 43, 43)
node _indexes_T_87 = bits(cam_d[0].data, 43, 43)
node indexes_43 = cat(_indexes_T_86, _indexes_T_87)
node _indexes_T_88 = bits(cam_a[0].bits.data, 44, 44)
node _indexes_T_89 = bits(cam_d[0].data, 44, 44)
node indexes_44 = cat(_indexes_T_88, _indexes_T_89)
node _indexes_T_90 = bits(cam_a[0].bits.data, 45, 45)
node _indexes_T_91 = bits(cam_d[0].data, 45, 45)
node indexes_45 = cat(_indexes_T_90, _indexes_T_91)
node _indexes_T_92 = bits(cam_a[0].bits.data, 46, 46)
node _indexes_T_93 = bits(cam_d[0].data, 46, 46)
node indexes_46 = cat(_indexes_T_92, _indexes_T_93)
node _indexes_T_94 = bits(cam_a[0].bits.data, 47, 47)
node _indexes_T_95 = bits(cam_d[0].data, 47, 47)
node indexes_47 = cat(_indexes_T_94, _indexes_T_95)
node _indexes_T_96 = bits(cam_a[0].bits.data, 48, 48)
node _indexes_T_97 = bits(cam_d[0].data, 48, 48)
node indexes_48 = cat(_indexes_T_96, _indexes_T_97)
node _indexes_T_98 = bits(cam_a[0].bits.data, 49, 49)
node _indexes_T_99 = bits(cam_d[0].data, 49, 49)
node indexes_49 = cat(_indexes_T_98, _indexes_T_99)
node _indexes_T_100 = bits(cam_a[0].bits.data, 50, 50)
node _indexes_T_101 = bits(cam_d[0].data, 50, 50)
node indexes_50 = cat(_indexes_T_100, _indexes_T_101)
node _indexes_T_102 = bits(cam_a[0].bits.data, 51, 51)
node _indexes_T_103 = bits(cam_d[0].data, 51, 51)
node indexes_51 = cat(_indexes_T_102, _indexes_T_103)
node _indexes_T_104 = bits(cam_a[0].bits.data, 52, 52)
node _indexes_T_105 = bits(cam_d[0].data, 52, 52)
node indexes_52 = cat(_indexes_T_104, _indexes_T_105)
node _indexes_T_106 = bits(cam_a[0].bits.data, 53, 53)
node _indexes_T_107 = bits(cam_d[0].data, 53, 53)
node indexes_53 = cat(_indexes_T_106, _indexes_T_107)
node _indexes_T_108 = bits(cam_a[0].bits.data, 54, 54)
node _indexes_T_109 = bits(cam_d[0].data, 54, 54)
node indexes_54 = cat(_indexes_T_108, _indexes_T_109)
node _indexes_T_110 = bits(cam_a[0].bits.data, 55, 55)
node _indexes_T_111 = bits(cam_d[0].data, 55, 55)
node indexes_55 = cat(_indexes_T_110, _indexes_T_111)
node _indexes_T_112 = bits(cam_a[0].bits.data, 56, 56)
node _indexes_T_113 = bits(cam_d[0].data, 56, 56)
node indexes_56 = cat(_indexes_T_112, _indexes_T_113)
node _indexes_T_114 = bits(cam_a[0].bits.data, 57, 57)
node _indexes_T_115 = bits(cam_d[0].data, 57, 57)
node indexes_57 = cat(_indexes_T_114, _indexes_T_115)
node _indexes_T_116 = bits(cam_a[0].bits.data, 58, 58)
node _indexes_T_117 = bits(cam_d[0].data, 58, 58)
node indexes_58 = cat(_indexes_T_116, _indexes_T_117)
node _indexes_T_118 = bits(cam_a[0].bits.data, 59, 59)
node _indexes_T_119 = bits(cam_d[0].data, 59, 59)
node indexes_59 = cat(_indexes_T_118, _indexes_T_119)
node _indexes_T_120 = bits(cam_a[0].bits.data, 60, 60)
node _indexes_T_121 = bits(cam_d[0].data, 60, 60)
node indexes_60 = cat(_indexes_T_120, _indexes_T_121)
node _indexes_T_122 = bits(cam_a[0].bits.data, 61, 61)
node _indexes_T_123 = bits(cam_d[0].data, 61, 61)
node indexes_61 = cat(_indexes_T_122, _indexes_T_123)
node _indexes_T_124 = bits(cam_a[0].bits.data, 62, 62)
node _indexes_T_125 = bits(cam_d[0].data, 62, 62)
node indexes_62 = cat(_indexes_T_124, _indexes_T_125)
node _indexes_T_126 = bits(cam_a[0].bits.data, 63, 63)
node _indexes_T_127 = bits(cam_d[0].data, 63, 63)
node indexes_63 = cat(_indexes_T_126, _indexes_T_127)
node _logic_out_T = dshr(cam_a[0].lut, indexes_0)
node _logic_out_T_1 = bits(_logic_out_T, 0, 0)
node _logic_out_T_2 = dshr(cam_a[0].lut, indexes_1)
node _logic_out_T_3 = bits(_logic_out_T_2, 0, 0)
node _logic_out_T_4 = dshr(cam_a[0].lut, indexes_2)
node _logic_out_T_5 = bits(_logic_out_T_4, 0, 0)
node _logic_out_T_6 = dshr(cam_a[0].lut, indexes_3)
node _logic_out_T_7 = bits(_logic_out_T_6, 0, 0)
node _logic_out_T_8 = dshr(cam_a[0].lut, indexes_4)
node _logic_out_T_9 = bits(_logic_out_T_8, 0, 0)
node _logic_out_T_10 = dshr(cam_a[0].lut, indexes_5)
node _logic_out_T_11 = bits(_logic_out_T_10, 0, 0)
node _logic_out_T_12 = dshr(cam_a[0].lut, indexes_6)
node _logic_out_T_13 = bits(_logic_out_T_12, 0, 0)
node _logic_out_T_14 = dshr(cam_a[0].lut, indexes_7)
node _logic_out_T_15 = bits(_logic_out_T_14, 0, 0)
node _logic_out_T_16 = dshr(cam_a[0].lut, indexes_8)
node _logic_out_T_17 = bits(_logic_out_T_16, 0, 0)
node _logic_out_T_18 = dshr(cam_a[0].lut, indexes_9)
node _logic_out_T_19 = bits(_logic_out_T_18, 0, 0)
node _logic_out_T_20 = dshr(cam_a[0].lut, indexes_10)
node _logic_out_T_21 = bits(_logic_out_T_20, 0, 0)
node _logic_out_T_22 = dshr(cam_a[0].lut, indexes_11)
node _logic_out_T_23 = bits(_logic_out_T_22, 0, 0)
node _logic_out_T_24 = dshr(cam_a[0].lut, indexes_12)
node _logic_out_T_25 = bits(_logic_out_T_24, 0, 0)
node _logic_out_T_26 = dshr(cam_a[0].lut, indexes_13)
node _logic_out_T_27 = bits(_logic_out_T_26, 0, 0)
node _logic_out_T_28 = dshr(cam_a[0].lut, indexes_14)
node _logic_out_T_29 = bits(_logic_out_T_28, 0, 0)
node _logic_out_T_30 = dshr(cam_a[0].lut, indexes_15)
node _logic_out_T_31 = bits(_logic_out_T_30, 0, 0)
node _logic_out_T_32 = dshr(cam_a[0].lut, indexes_16)
node _logic_out_T_33 = bits(_logic_out_T_32, 0, 0)
node _logic_out_T_34 = dshr(cam_a[0].lut, indexes_17)
node _logic_out_T_35 = bits(_logic_out_T_34, 0, 0)
node _logic_out_T_36 = dshr(cam_a[0].lut, indexes_18)
node _logic_out_T_37 = bits(_logic_out_T_36, 0, 0)
node _logic_out_T_38 = dshr(cam_a[0].lut, indexes_19)
node _logic_out_T_39 = bits(_logic_out_T_38, 0, 0)
node _logic_out_T_40 = dshr(cam_a[0].lut, indexes_20)
node _logic_out_T_41 = bits(_logic_out_T_40, 0, 0)
node _logic_out_T_42 = dshr(cam_a[0].lut, indexes_21)
node _logic_out_T_43 = bits(_logic_out_T_42, 0, 0)
node _logic_out_T_44 = dshr(cam_a[0].lut, indexes_22)
node _logic_out_T_45 = bits(_logic_out_T_44, 0, 0)
node _logic_out_T_46 = dshr(cam_a[0].lut, indexes_23)
node _logic_out_T_47 = bits(_logic_out_T_46, 0, 0)
node _logic_out_T_48 = dshr(cam_a[0].lut, indexes_24)
node _logic_out_T_49 = bits(_logic_out_T_48, 0, 0)
node _logic_out_T_50 = dshr(cam_a[0].lut, indexes_25)
node _logic_out_T_51 = bits(_logic_out_T_50, 0, 0)
node _logic_out_T_52 = dshr(cam_a[0].lut, indexes_26)
node _logic_out_T_53 = bits(_logic_out_T_52, 0, 0)
node _logic_out_T_54 = dshr(cam_a[0].lut, indexes_27)
node _logic_out_T_55 = bits(_logic_out_T_54, 0, 0)
node _logic_out_T_56 = dshr(cam_a[0].lut, indexes_28)
node _logic_out_T_57 = bits(_logic_out_T_56, 0, 0)
node _logic_out_T_58 = dshr(cam_a[0].lut, indexes_29)
node _logic_out_T_59 = bits(_logic_out_T_58, 0, 0)
node _logic_out_T_60 = dshr(cam_a[0].lut, indexes_30)
node _logic_out_T_61 = bits(_logic_out_T_60, 0, 0)
node _logic_out_T_62 = dshr(cam_a[0].lut, indexes_31)
node _logic_out_T_63 = bits(_logic_out_T_62, 0, 0)
node _logic_out_T_64 = dshr(cam_a[0].lut, indexes_32)
node _logic_out_T_65 = bits(_logic_out_T_64, 0, 0)
node _logic_out_T_66 = dshr(cam_a[0].lut, indexes_33)
node _logic_out_T_67 = bits(_logic_out_T_66, 0, 0)
node _logic_out_T_68 = dshr(cam_a[0].lut, indexes_34)
node _logic_out_T_69 = bits(_logic_out_T_68, 0, 0)
node _logic_out_T_70 = dshr(cam_a[0].lut, indexes_35)
node _logic_out_T_71 = bits(_logic_out_T_70, 0, 0)
node _logic_out_T_72 = dshr(cam_a[0].lut, indexes_36)
node _logic_out_T_73 = bits(_logic_out_T_72, 0, 0)
node _logic_out_T_74 = dshr(cam_a[0].lut, indexes_37)
node _logic_out_T_75 = bits(_logic_out_T_74, 0, 0)
node _logic_out_T_76 = dshr(cam_a[0].lut, indexes_38)
node _logic_out_T_77 = bits(_logic_out_T_76, 0, 0)
node _logic_out_T_78 = dshr(cam_a[0].lut, indexes_39)
node _logic_out_T_79 = bits(_logic_out_T_78, 0, 0)
node _logic_out_T_80 = dshr(cam_a[0].lut, indexes_40)
node _logic_out_T_81 = bits(_logic_out_T_80, 0, 0)
node _logic_out_T_82 = dshr(cam_a[0].lut, indexes_41)
node _logic_out_T_83 = bits(_logic_out_T_82, 0, 0)
node _logic_out_T_84 = dshr(cam_a[0].lut, indexes_42)
node _logic_out_T_85 = bits(_logic_out_T_84, 0, 0)
node _logic_out_T_86 = dshr(cam_a[0].lut, indexes_43)
node _logic_out_T_87 = bits(_logic_out_T_86, 0, 0)
node _logic_out_T_88 = dshr(cam_a[0].lut, indexes_44)
node _logic_out_T_89 = bits(_logic_out_T_88, 0, 0)
node _logic_out_T_90 = dshr(cam_a[0].lut, indexes_45)
node _logic_out_T_91 = bits(_logic_out_T_90, 0, 0)
node _logic_out_T_92 = dshr(cam_a[0].lut, indexes_46)
node _logic_out_T_93 = bits(_logic_out_T_92, 0, 0)
node _logic_out_T_94 = dshr(cam_a[0].lut, indexes_47)
node _logic_out_T_95 = bits(_logic_out_T_94, 0, 0)
node _logic_out_T_96 = dshr(cam_a[0].lut, indexes_48)
node _logic_out_T_97 = bits(_logic_out_T_96, 0, 0)
node _logic_out_T_98 = dshr(cam_a[0].lut, indexes_49)
node _logic_out_T_99 = bits(_logic_out_T_98, 0, 0)
node _logic_out_T_100 = dshr(cam_a[0].lut, indexes_50)
node _logic_out_T_101 = bits(_logic_out_T_100, 0, 0)
node _logic_out_T_102 = dshr(cam_a[0].lut, indexes_51)
node _logic_out_T_103 = bits(_logic_out_T_102, 0, 0)
node _logic_out_T_104 = dshr(cam_a[0].lut, indexes_52)
node _logic_out_T_105 = bits(_logic_out_T_104, 0, 0)
node _logic_out_T_106 = dshr(cam_a[0].lut, indexes_53)
node _logic_out_T_107 = bits(_logic_out_T_106, 0, 0)
node _logic_out_T_108 = dshr(cam_a[0].lut, indexes_54)
node _logic_out_T_109 = bits(_logic_out_T_108, 0, 0)
node _logic_out_T_110 = dshr(cam_a[0].lut, indexes_55)
node _logic_out_T_111 = bits(_logic_out_T_110, 0, 0)
node _logic_out_T_112 = dshr(cam_a[0].lut, indexes_56)
node _logic_out_T_113 = bits(_logic_out_T_112, 0, 0)
node _logic_out_T_114 = dshr(cam_a[0].lut, indexes_57)
node _logic_out_T_115 = bits(_logic_out_T_114, 0, 0)
node _logic_out_T_116 = dshr(cam_a[0].lut, indexes_58)
node _logic_out_T_117 = bits(_logic_out_T_116, 0, 0)
node _logic_out_T_118 = dshr(cam_a[0].lut, indexes_59)
node _logic_out_T_119 = bits(_logic_out_T_118, 0, 0)
node _logic_out_T_120 = dshr(cam_a[0].lut, indexes_60)
node _logic_out_T_121 = bits(_logic_out_T_120, 0, 0)
node _logic_out_T_122 = dshr(cam_a[0].lut, indexes_61)
node _logic_out_T_123 = bits(_logic_out_T_122, 0, 0)
node _logic_out_T_124 = dshr(cam_a[0].lut, indexes_62)
node _logic_out_T_125 = bits(_logic_out_T_124, 0, 0)
node _logic_out_T_126 = dshr(cam_a[0].lut, indexes_63)
node _logic_out_T_127 = bits(_logic_out_T_126, 0, 0)
node logic_out_lo_lo_lo_lo_lo = cat(_logic_out_T_3, _logic_out_T_1)
node logic_out_lo_lo_lo_lo_hi = cat(_logic_out_T_7, _logic_out_T_5)
node logic_out_lo_lo_lo_lo = cat(logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo)
node logic_out_lo_lo_lo_hi_lo = cat(_logic_out_T_11, _logic_out_T_9)
node logic_out_lo_lo_lo_hi_hi = cat(_logic_out_T_15, _logic_out_T_13)
node logic_out_lo_lo_lo_hi = cat(logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo)
node logic_out_lo_lo_lo = cat(logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo)
node logic_out_lo_lo_hi_lo_lo = cat(_logic_out_T_19, _logic_out_T_17)
node logic_out_lo_lo_hi_lo_hi = cat(_logic_out_T_23, _logic_out_T_21)
node logic_out_lo_lo_hi_lo = cat(logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo)
node logic_out_lo_lo_hi_hi_lo = cat(_logic_out_T_27, _logic_out_T_25)
node logic_out_lo_lo_hi_hi_hi = cat(_logic_out_T_31, _logic_out_T_29)
node logic_out_lo_lo_hi_hi = cat(logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo)
node logic_out_lo_lo_hi = cat(logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo)
node logic_out_lo_lo = cat(logic_out_lo_lo_hi, logic_out_lo_lo_lo)
node logic_out_lo_hi_lo_lo_lo = cat(_logic_out_T_35, _logic_out_T_33)
node logic_out_lo_hi_lo_lo_hi = cat(_logic_out_T_39, _logic_out_T_37)
node logic_out_lo_hi_lo_lo = cat(logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo)
node logic_out_lo_hi_lo_hi_lo = cat(_logic_out_T_43, _logic_out_T_41)
node logic_out_lo_hi_lo_hi_hi = cat(_logic_out_T_47, _logic_out_T_45)
node logic_out_lo_hi_lo_hi = cat(logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo)
node logic_out_lo_hi_lo = cat(logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo)
node logic_out_lo_hi_hi_lo_lo = cat(_logic_out_T_51, _logic_out_T_49)
node logic_out_lo_hi_hi_lo_hi = cat(_logic_out_T_55, _logic_out_T_53)
node logic_out_lo_hi_hi_lo = cat(logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo)
node logic_out_lo_hi_hi_hi_lo = cat(_logic_out_T_59, _logic_out_T_57)
node logic_out_lo_hi_hi_hi_hi = cat(_logic_out_T_63, _logic_out_T_61)
node logic_out_lo_hi_hi_hi = cat(logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo)
node logic_out_lo_hi_hi = cat(logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo)
node logic_out_lo_hi = cat(logic_out_lo_hi_hi, logic_out_lo_hi_lo)
node logic_out_lo = cat(logic_out_lo_hi, logic_out_lo_lo)
node logic_out_hi_lo_lo_lo_lo = cat(_logic_out_T_67, _logic_out_T_65)
node logic_out_hi_lo_lo_lo_hi = cat(_logic_out_T_71, _logic_out_T_69)
node logic_out_hi_lo_lo_lo = cat(logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo)
node logic_out_hi_lo_lo_hi_lo = cat(_logic_out_T_75, _logic_out_T_73)
node logic_out_hi_lo_lo_hi_hi = cat(_logic_out_T_79, _logic_out_T_77)
node logic_out_hi_lo_lo_hi = cat(logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo)
node logic_out_hi_lo_lo = cat(logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo)
node logic_out_hi_lo_hi_lo_lo = cat(_logic_out_T_83, _logic_out_T_81)
node logic_out_hi_lo_hi_lo_hi = cat(_logic_out_T_87, _logic_out_T_85)
node logic_out_hi_lo_hi_lo = cat(logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo)
node logic_out_hi_lo_hi_hi_lo = cat(_logic_out_T_91, _logic_out_T_89)
node logic_out_hi_lo_hi_hi_hi = cat(_logic_out_T_95, _logic_out_T_93)
node logic_out_hi_lo_hi_hi = cat(logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo)
node logic_out_hi_lo_hi = cat(logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo)
node logic_out_hi_lo = cat(logic_out_hi_lo_hi, logic_out_hi_lo_lo)
node logic_out_hi_hi_lo_lo_lo = cat(_logic_out_T_99, _logic_out_T_97)
node logic_out_hi_hi_lo_lo_hi = cat(_logic_out_T_103, _logic_out_T_101)
node logic_out_hi_hi_lo_lo = cat(logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo)
node logic_out_hi_hi_lo_hi_lo = cat(_logic_out_T_107, _logic_out_T_105)
node logic_out_hi_hi_lo_hi_hi = cat(_logic_out_T_111, _logic_out_T_109)
node logic_out_hi_hi_lo_hi = cat(logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo)
node logic_out_hi_hi_lo = cat(logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo)
node logic_out_hi_hi_hi_lo_lo = cat(_logic_out_T_115, _logic_out_T_113)
node logic_out_hi_hi_hi_lo_hi = cat(_logic_out_T_119, _logic_out_T_117)
node logic_out_hi_hi_hi_lo = cat(logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo)
node logic_out_hi_hi_hi_hi_lo = cat(_logic_out_T_123, _logic_out_T_121)
node logic_out_hi_hi_hi_hi_hi = cat(_logic_out_T_127, _logic_out_T_125)
node logic_out_hi_hi_hi_hi = cat(logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo)
node logic_out_hi_hi_hi = cat(logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo)
node logic_out_hi_hi = cat(logic_out_hi_hi_hi, logic_out_hi_hi_lo)
node logic_out_hi = cat(logic_out_hi_hi, logic_out_hi_lo)
node logic_out = cat(logic_out_hi, logic_out_lo)
node unsigned = bits(cam_a[0].bits.param, 1, 1)
node take_max = bits(cam_a[0].bits.param, 0, 0)
node adder = bits(cam_a[0].bits.param, 2, 2)
node _signSel_T = not(cam_a[0].bits.mask)
node _signSel_T_1 = shr(cam_a[0].bits.mask, 1)
node _signSel_T_2 = or(_signSel_T, _signSel_T_1)
node signSel = not(_signSel_T_2)
node _signbits_a_T = bits(cam_a[0].bits.data, 7, 7)
node _signbits_a_T_1 = bits(cam_a[0].bits.data, 15, 15)
node _signbits_a_T_2 = bits(cam_a[0].bits.data, 23, 23)
node _signbits_a_T_3 = bits(cam_a[0].bits.data, 31, 31)
node _signbits_a_T_4 = bits(cam_a[0].bits.data, 39, 39)
node _signbits_a_T_5 = bits(cam_a[0].bits.data, 47, 47)
node _signbits_a_T_6 = bits(cam_a[0].bits.data, 55, 55)
node _signbits_a_T_7 = bits(cam_a[0].bits.data, 63, 63)
node signbits_a_lo_lo = cat(_signbits_a_T_1, _signbits_a_T)
node signbits_a_lo_hi = cat(_signbits_a_T_3, _signbits_a_T_2)
node signbits_a_lo = cat(signbits_a_lo_hi, signbits_a_lo_lo)
node signbits_a_hi_lo = cat(_signbits_a_T_5, _signbits_a_T_4)
node signbits_a_hi_hi = cat(_signbits_a_T_7, _signbits_a_T_6)
node signbits_a_hi = cat(signbits_a_hi_hi, signbits_a_hi_lo)
node signbits_a = cat(signbits_a_hi, signbits_a_lo)
node _signbits_d_T = bits(cam_d[0].data, 7, 7)
node _signbits_d_T_1 = bits(cam_d[0].data, 15, 15)
node _signbits_d_T_2 = bits(cam_d[0].data, 23, 23)
node _signbits_d_T_3 = bits(cam_d[0].data, 31, 31)
node _signbits_d_T_4 = bits(cam_d[0].data, 39, 39)
node _signbits_d_T_5 = bits(cam_d[0].data, 47, 47)
node _signbits_d_T_6 = bits(cam_d[0].data, 55, 55)
node _signbits_d_T_7 = bits(cam_d[0].data, 63, 63)
node signbits_d_lo_lo = cat(_signbits_d_T_1, _signbits_d_T)
node signbits_d_lo_hi = cat(_signbits_d_T_3, _signbits_d_T_2)
node signbits_d_lo = cat(signbits_d_lo_hi, signbits_d_lo_lo)
node signbits_d_hi_lo = cat(_signbits_d_T_5, _signbits_d_T_4)
node signbits_d_hi_hi = cat(_signbits_d_T_7, _signbits_d_T_6)
node signbits_d_hi = cat(signbits_d_hi_hi, signbits_d_hi_lo)
node signbits_d = cat(signbits_d_hi, signbits_d_lo)
node _signbit_a_T = and(signbits_a, signSel)
node _signbit_a_T_1 = shl(_signbit_a_T, 1)
node signbit_a = bits(_signbit_a_T_1, 7, 0)
node _signbit_d_T = and(signbits_d, signSel)
node _signbit_d_T_1 = shl(_signbit_d_T, 1)
node signbit_d = bits(_signbit_d_T_1, 7, 0)
node _signext_a_T = shl(signbit_a, 1)
node _signext_a_T_1 = bits(_signext_a_T, 7, 0)
node _signext_a_T_2 = or(signbit_a, _signext_a_T_1)
node _signext_a_T_3 = shl(_signext_a_T_2, 2)
node _signext_a_T_4 = bits(_signext_a_T_3, 7, 0)
node _signext_a_T_5 = or(_signext_a_T_2, _signext_a_T_4)
node _signext_a_T_6 = shl(_signext_a_T_5, 4)
node _signext_a_T_7 = bits(_signext_a_T_6, 7, 0)
node _signext_a_T_8 = or(_signext_a_T_5, _signext_a_T_7)
node _signext_a_T_9 = bits(_signext_a_T_8, 7, 0)
node _signext_a_T_10 = bits(_signext_a_T_9, 0, 0)
node _signext_a_T_11 = bits(_signext_a_T_9, 1, 1)
node _signext_a_T_12 = bits(_signext_a_T_9, 2, 2)
node _signext_a_T_13 = bits(_signext_a_T_9, 3, 3)
node _signext_a_T_14 = bits(_signext_a_T_9, 4, 4)
node _signext_a_T_15 = bits(_signext_a_T_9, 5, 5)
node _signext_a_T_16 = bits(_signext_a_T_9, 6, 6)
node _signext_a_T_17 = bits(_signext_a_T_9, 7, 7)
node _signext_a_T_18 = mux(_signext_a_T_10, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_19 = mux(_signext_a_T_11, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_20 = mux(_signext_a_T_12, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_21 = mux(_signext_a_T_13, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_22 = mux(_signext_a_T_14, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_23 = mux(_signext_a_T_15, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_24 = mux(_signext_a_T_16, UInt<8>(0hff), UInt<8>(0h0))
node _signext_a_T_25 = mux(_signext_a_T_17, UInt<8>(0hff), UInt<8>(0h0))
node signext_a_lo_lo = cat(_signext_a_T_19, _signext_a_T_18)
node signext_a_lo_hi = cat(_signext_a_T_21, _signext_a_T_20)
node signext_a_lo = cat(signext_a_lo_hi, signext_a_lo_lo)
node signext_a_hi_lo = cat(_signext_a_T_23, _signext_a_T_22)
node signext_a_hi_hi = cat(_signext_a_T_25, _signext_a_T_24)
node signext_a_hi = cat(signext_a_hi_hi, signext_a_hi_lo)
node signext_a = cat(signext_a_hi, signext_a_lo)
node _signext_d_T = shl(signbit_d, 1)
node _signext_d_T_1 = bits(_signext_d_T, 7, 0)
node _signext_d_T_2 = or(signbit_d, _signext_d_T_1)
node _signext_d_T_3 = shl(_signext_d_T_2, 2)
node _signext_d_T_4 = bits(_signext_d_T_3, 7, 0)
node _signext_d_T_5 = or(_signext_d_T_2, _signext_d_T_4)
node _signext_d_T_6 = shl(_signext_d_T_5, 4)
node _signext_d_T_7 = bits(_signext_d_T_6, 7, 0)
node _signext_d_T_8 = or(_signext_d_T_5, _signext_d_T_7)
node _signext_d_T_9 = bits(_signext_d_T_8, 7, 0)
node _signext_d_T_10 = bits(_signext_d_T_9, 0, 0)
node _signext_d_T_11 = bits(_signext_d_T_9, 1, 1)
node _signext_d_T_12 = bits(_signext_d_T_9, 2, 2)
node _signext_d_T_13 = bits(_signext_d_T_9, 3, 3)
node _signext_d_T_14 = bits(_signext_d_T_9, 4, 4)
node _signext_d_T_15 = bits(_signext_d_T_9, 5, 5)
node _signext_d_T_16 = bits(_signext_d_T_9, 6, 6)
node _signext_d_T_17 = bits(_signext_d_T_9, 7, 7)
node _signext_d_T_18 = mux(_signext_d_T_10, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_19 = mux(_signext_d_T_11, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_20 = mux(_signext_d_T_12, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_21 = mux(_signext_d_T_13, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_22 = mux(_signext_d_T_14, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_23 = mux(_signext_d_T_15, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_24 = mux(_signext_d_T_16, UInt<8>(0hff), UInt<8>(0h0))
node _signext_d_T_25 = mux(_signext_d_T_17, UInt<8>(0hff), UInt<8>(0h0))
node signext_d_lo_lo = cat(_signext_d_T_19, _signext_d_T_18)
node signext_d_lo_hi = cat(_signext_d_T_21, _signext_d_T_20)
node signext_d_lo = cat(signext_d_lo_hi, signext_d_lo_lo)
node signext_d_hi_lo = cat(_signext_d_T_23, _signext_d_T_22)
node signext_d_hi_hi = cat(_signext_d_T_25, _signext_d_T_24)
node signext_d_hi = cat(signext_d_hi_hi, signext_d_hi_lo)
node signext_d = cat(signext_d_hi, signext_d_lo)
node _wide_mask_T = bits(cam_a[0].bits.mask, 0, 0)
node _wide_mask_T_1 = bits(cam_a[0].bits.mask, 1, 1)
node _wide_mask_T_2 = bits(cam_a[0].bits.mask, 2, 2)
node _wide_mask_T_3 = bits(cam_a[0].bits.mask, 3, 3)
node _wide_mask_T_4 = bits(cam_a[0].bits.mask, 4, 4)
node _wide_mask_T_5 = bits(cam_a[0].bits.mask, 5, 5)
node _wide_mask_T_6 = bits(cam_a[0].bits.mask, 6, 6)
node _wide_mask_T_7 = bits(cam_a[0].bits.mask, 7, 7)
node _wide_mask_T_8 = mux(_wide_mask_T, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_9 = mux(_wide_mask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_10 = mux(_wide_mask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_11 = mux(_wide_mask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_12 = mux(_wide_mask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_13 = mux(_wide_mask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_14 = mux(_wide_mask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _wide_mask_T_15 = mux(_wide_mask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node wide_mask_lo_lo = cat(_wide_mask_T_9, _wide_mask_T_8)
node wide_mask_lo_hi = cat(_wide_mask_T_11, _wide_mask_T_10)
node wide_mask_lo = cat(wide_mask_lo_hi, wide_mask_lo_lo)
node wide_mask_hi_lo = cat(_wide_mask_T_13, _wide_mask_T_12)
node wide_mask_hi_hi = cat(_wide_mask_T_15, _wide_mask_T_14)
node wide_mask_hi = cat(wide_mask_hi_hi, wide_mask_hi_lo)
node wide_mask = cat(wide_mask_hi, wide_mask_lo)
node _a_a_ext_T = and(cam_a[0].bits.data, wide_mask)
node a_a_ext = or(_a_a_ext_T, signext_a)
node _a_d_ext_T = and(cam_d[0].data, wide_mask)
node a_d_ext = or(_a_d_ext_T, signext_d)
node _a_d_inv_T = not(a_d_ext)
node a_d_inv = mux(adder, a_d_ext, _a_d_inv_T)
node _adder_out_T = add(a_a_ext, a_d_inv)
node adder_out = tail(_adder_out_T, 1)
node _a_bigger_uneq_T = bits(a_a_ext, 63, 63)
node a_bigger_uneq = eq(unsigned, _a_bigger_uneq_T)
node _a_bigger_T = bits(a_a_ext, 63, 63)
node _a_bigger_T_1 = bits(a_d_ext, 63, 63)
node _a_bigger_T_2 = eq(_a_bigger_T, _a_bigger_T_1)
node _a_bigger_T_3 = bits(adder_out, 63, 63)
node _a_bigger_T_4 = eq(_a_bigger_T_3, UInt<1>(0h0))
node a_bigger = mux(_a_bigger_T_2, _a_bigger_T_4, a_bigger_uneq)
node pick_a = eq(take_max, a_bigger)
node _arith_out_T = mux(pick_a, cam_a[0].bits.data, cam_d[0].data)
node arith_out = mux(adder, adder_out, _arith_out_T)
node _amo_data_T = bits(cam_a[0].bits.opcode, 0, 0)
node amo_data = mux(_amo_data_T, logic_out, arith_out)
wire source_i : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
node _a_allow_T = eq(a_cam_busy, UInt<1>(0h0))
node _a_allow_T_1 = or(a_isSupported, cam_free_0)
node a_allow = and(_a_allow_T, _a_allow_T_1)
node _nodeIn_a_ready_T = and(source_i.ready, a_allow)
connect nodeIn.a.ready, _nodeIn_a_ready_T
node _source_i_valid_T = and(nodeIn.a.valid, a_allow)
connect source_i.valid, _source_i_valid_T
connect source_i.bits, nodeIn.a.bits
node _T = eq(a_isSupported, UInt<1>(0h0))
when _T :
connect source_i.bits.opcode, UInt<3>(0h4)
connect source_i.bits.param, UInt<1>(0h0)
wire source_c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect source_c.valid, cam_amo_0
node _source_c_bits_T = or(cam_a[0].bits.corrupt, cam_d[0].corrupt)
node _source_c_bits_legal_T = leq(UInt<1>(0h0), cam_a[0].bits.size)
node _source_c_bits_legal_T_1 = leq(cam_a[0].bits.size, UInt<4>(0hc))
node _source_c_bits_legal_T_2 = and(_source_c_bits_legal_T, _source_c_bits_legal_T_1)
node _source_c_bits_legal_T_3 = or(UInt<1>(0h0), _source_c_bits_legal_T_2)
node _source_c_bits_legal_T_4 = xor(cam_a[0].bits.address, UInt<14>(0h3000))
node _source_c_bits_legal_T_5 = cvt(_source_c_bits_legal_T_4)
node _source_c_bits_legal_T_6 = and(_source_c_bits_legal_T_5, asSInt(UInt<30>(0h1a113000)))
node _source_c_bits_legal_T_7 = asSInt(_source_c_bits_legal_T_6)
node _source_c_bits_legal_T_8 = eq(_source_c_bits_legal_T_7, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_9 = and(_source_c_bits_legal_T_3, _source_c_bits_legal_T_8)
node _source_c_bits_legal_T_10 = leq(UInt<1>(0h0), cam_a[0].bits.size)
node _source_c_bits_legal_T_11 = leq(cam_a[0].bits.size, UInt<3>(0h6))
node _source_c_bits_legal_T_12 = and(_source_c_bits_legal_T_10, _source_c_bits_legal_T_11)
node _source_c_bits_legal_T_13 = or(UInt<1>(0h0), _source_c_bits_legal_T_12)
node _source_c_bits_legal_T_14 = xor(cam_a[0].bits.address, UInt<1>(0h0))
node _source_c_bits_legal_T_15 = cvt(_source_c_bits_legal_T_14)
node _source_c_bits_legal_T_16 = and(_source_c_bits_legal_T_15, asSInt(UInt<30>(0h1a112000)))
node _source_c_bits_legal_T_17 = asSInt(_source_c_bits_legal_T_16)
node _source_c_bits_legal_T_18 = eq(_source_c_bits_legal_T_17, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_19 = xor(cam_a[0].bits.address, UInt<21>(0h100000))
node _source_c_bits_legal_T_20 = cvt(_source_c_bits_legal_T_19)
node _source_c_bits_legal_T_21 = and(_source_c_bits_legal_T_20, asSInt(UInt<30>(0h1a103000)))
node _source_c_bits_legal_T_22 = asSInt(_source_c_bits_legal_T_21)
node _source_c_bits_legal_T_23 = eq(_source_c_bits_legal_T_22, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_24 = xor(cam_a[0].bits.address, UInt<26>(0h2000000))
node _source_c_bits_legal_T_25 = cvt(_source_c_bits_legal_T_24)
node _source_c_bits_legal_T_26 = and(_source_c_bits_legal_T_25, asSInt(UInt<30>(0h1a110000)))
node _source_c_bits_legal_T_27 = asSInt(_source_c_bits_legal_T_26)
node _source_c_bits_legal_T_28 = eq(_source_c_bits_legal_T_27, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_29 = xor(cam_a[0].bits.address, UInt<26>(0h2010000))
node _source_c_bits_legal_T_30 = cvt(_source_c_bits_legal_T_29)
node _source_c_bits_legal_T_31 = and(_source_c_bits_legal_T_30, asSInt(UInt<30>(0h1a113000)))
node _source_c_bits_legal_T_32 = asSInt(_source_c_bits_legal_T_31)
node _source_c_bits_legal_T_33 = eq(_source_c_bits_legal_T_32, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_34 = xor(cam_a[0].bits.address, UInt<28>(0h8000000))
node _source_c_bits_legal_T_35 = cvt(_source_c_bits_legal_T_34)
node _source_c_bits_legal_T_36 = and(_source_c_bits_legal_T_35, asSInt(UInt<30>(0h18000000)))
node _source_c_bits_legal_T_37 = asSInt(_source_c_bits_legal_T_36)
node _source_c_bits_legal_T_38 = eq(_source_c_bits_legal_T_37, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_39 = xor(cam_a[0].bits.address, UInt<29>(0h10000000))
node _source_c_bits_legal_T_40 = cvt(_source_c_bits_legal_T_39)
node _source_c_bits_legal_T_41 = and(_source_c_bits_legal_T_40, asSInt(UInt<30>(0h1a113000)))
node _source_c_bits_legal_T_42 = asSInt(_source_c_bits_legal_T_41)
node _source_c_bits_legal_T_43 = eq(_source_c_bits_legal_T_42, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_44 = or(_source_c_bits_legal_T_18, _source_c_bits_legal_T_23)
node _source_c_bits_legal_T_45 = or(_source_c_bits_legal_T_44, _source_c_bits_legal_T_28)
node _source_c_bits_legal_T_46 = or(_source_c_bits_legal_T_45, _source_c_bits_legal_T_33)
node _source_c_bits_legal_T_47 = or(_source_c_bits_legal_T_46, _source_c_bits_legal_T_38)
node _source_c_bits_legal_T_48 = or(_source_c_bits_legal_T_47, _source_c_bits_legal_T_43)
node _source_c_bits_legal_T_49 = and(_source_c_bits_legal_T_13, _source_c_bits_legal_T_48)
node _source_c_bits_legal_T_50 = or(UInt<1>(0h0), UInt<1>(0h0))
node _source_c_bits_legal_T_51 = xor(cam_a[0].bits.address, UInt<17>(0h10000))
node _source_c_bits_legal_T_52 = cvt(_source_c_bits_legal_T_51)
node _source_c_bits_legal_T_53 = and(_source_c_bits_legal_T_52, asSInt(UInt<30>(0h1a110000)))
node _source_c_bits_legal_T_54 = asSInt(_source_c_bits_legal_T_53)
node _source_c_bits_legal_T_55 = eq(_source_c_bits_legal_T_54, asSInt(UInt<1>(0h0)))
node _source_c_bits_legal_T_56 = and(_source_c_bits_legal_T_50, _source_c_bits_legal_T_55)
node _source_c_bits_legal_T_57 = or(UInt<1>(0h0), _source_c_bits_legal_T_9)
node _source_c_bits_legal_T_58 = or(_source_c_bits_legal_T_57, _source_c_bits_legal_T_49)
node source_c_bits_legal = or(_source_c_bits_legal_T_58, _source_c_bits_legal_T_56)
wire source_c_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect source_c_bits_a.opcode, UInt<1>(0h0)
connect source_c_bits_a.param, UInt<1>(0h0)
connect source_c_bits_a.size, cam_a[0].bits.size
connect source_c_bits_a.source, cam_a[0].bits.source
connect source_c_bits_a.address, cam_a[0].bits.address
node _source_c_bits_a_mask_sizeOH_T = or(cam_a[0].bits.size, UInt<3>(0h0))
node source_c_bits_a_mask_sizeOH_shiftAmount = bits(_source_c_bits_a_mask_sizeOH_T, 1, 0)
node _source_c_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), source_c_bits_a_mask_sizeOH_shiftAmount)
node _source_c_bits_a_mask_sizeOH_T_2 = bits(_source_c_bits_a_mask_sizeOH_T_1, 2, 0)
node source_c_bits_a_mask_sizeOH = or(_source_c_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node source_c_bits_a_mask_sub_sub_sub_0_1 = geq(cam_a[0].bits.size, UInt<2>(0h3))
node source_c_bits_a_mask_sub_sub_size = bits(source_c_bits_a_mask_sizeOH, 2, 2)
node source_c_bits_a_mask_sub_sub_bit = bits(cam_a[0].bits.address, 2, 2)
node source_c_bits_a_mask_sub_sub_nbit = eq(source_c_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node source_c_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_nbit)
node _source_c_bits_a_mask_sub_sub_acc_T = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_0_2)
node source_c_bits_a_mask_sub_sub_0_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T)
node source_c_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), source_c_bits_a_mask_sub_sub_bit)
node _source_c_bits_a_mask_sub_sub_acc_T_1 = and(source_c_bits_a_mask_sub_sub_size, source_c_bits_a_mask_sub_sub_1_2)
node source_c_bits_a_mask_sub_sub_1_1 = or(source_c_bits_a_mask_sub_sub_sub_0_1, _source_c_bits_a_mask_sub_sub_acc_T_1)
node source_c_bits_a_mask_sub_size = bits(source_c_bits_a_mask_sizeOH, 1, 1)
node source_c_bits_a_mask_sub_bit = bits(cam_a[0].bits.address, 1, 1)
node source_c_bits_a_mask_sub_nbit = eq(source_c_bits_a_mask_sub_bit, UInt<1>(0h0))
node source_c_bits_a_mask_sub_0_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_nbit)
node _source_c_bits_a_mask_sub_acc_T = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_0_2)
node source_c_bits_a_mask_sub_0_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T)
node source_c_bits_a_mask_sub_1_2 = and(source_c_bits_a_mask_sub_sub_0_2, source_c_bits_a_mask_sub_bit)
node _source_c_bits_a_mask_sub_acc_T_1 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_1_2)
node source_c_bits_a_mask_sub_1_1 = or(source_c_bits_a_mask_sub_sub_0_1, _source_c_bits_a_mask_sub_acc_T_1)
node source_c_bits_a_mask_sub_2_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_nbit)
node _source_c_bits_a_mask_sub_acc_T_2 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_2_2)
node source_c_bits_a_mask_sub_2_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_2)
node source_c_bits_a_mask_sub_3_2 = and(source_c_bits_a_mask_sub_sub_1_2, source_c_bits_a_mask_sub_bit)
node _source_c_bits_a_mask_sub_acc_T_3 = and(source_c_bits_a_mask_sub_size, source_c_bits_a_mask_sub_3_2)
node source_c_bits_a_mask_sub_3_1 = or(source_c_bits_a_mask_sub_sub_1_1, _source_c_bits_a_mask_sub_acc_T_3)
node source_c_bits_a_mask_size = bits(source_c_bits_a_mask_sizeOH, 0, 0)
node source_c_bits_a_mask_bit = bits(cam_a[0].bits.address, 0, 0)
node source_c_bits_a_mask_nbit = eq(source_c_bits_a_mask_bit, UInt<1>(0h0))
node source_c_bits_a_mask_eq = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_nbit)
node _source_c_bits_a_mask_acc_T = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq)
node source_c_bits_a_mask_acc = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T)
node source_c_bits_a_mask_eq_1 = and(source_c_bits_a_mask_sub_0_2, source_c_bits_a_mask_bit)
node _source_c_bits_a_mask_acc_T_1 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_1)
node source_c_bits_a_mask_acc_1 = or(source_c_bits_a_mask_sub_0_1, _source_c_bits_a_mask_acc_T_1)
node source_c_bits_a_mask_eq_2 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_nbit)
node _source_c_bits_a_mask_acc_T_2 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_2)
node source_c_bits_a_mask_acc_2 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_2)
node source_c_bits_a_mask_eq_3 = and(source_c_bits_a_mask_sub_1_2, source_c_bits_a_mask_bit)
node _source_c_bits_a_mask_acc_T_3 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_3)
node source_c_bits_a_mask_acc_3 = or(source_c_bits_a_mask_sub_1_1, _source_c_bits_a_mask_acc_T_3)
node source_c_bits_a_mask_eq_4 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_nbit)
node _source_c_bits_a_mask_acc_T_4 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_4)
node source_c_bits_a_mask_acc_4 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_4)
node source_c_bits_a_mask_eq_5 = and(source_c_bits_a_mask_sub_2_2, source_c_bits_a_mask_bit)
node _source_c_bits_a_mask_acc_T_5 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_5)
node source_c_bits_a_mask_acc_5 = or(source_c_bits_a_mask_sub_2_1, _source_c_bits_a_mask_acc_T_5)
node source_c_bits_a_mask_eq_6 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_nbit)
node _source_c_bits_a_mask_acc_T_6 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_6)
node source_c_bits_a_mask_acc_6 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_6)
node source_c_bits_a_mask_eq_7 = and(source_c_bits_a_mask_sub_3_2, source_c_bits_a_mask_bit)
node _source_c_bits_a_mask_acc_T_7 = and(source_c_bits_a_mask_size, source_c_bits_a_mask_eq_7)
node source_c_bits_a_mask_acc_7 = or(source_c_bits_a_mask_sub_3_1, _source_c_bits_a_mask_acc_T_7)
node source_c_bits_a_mask_lo_lo = cat(source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc)
node source_c_bits_a_mask_lo_hi = cat(source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2)
node source_c_bits_a_mask_lo = cat(source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo)
node source_c_bits_a_mask_hi_lo = cat(source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4)
node source_c_bits_a_mask_hi_hi = cat(source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6)
node source_c_bits_a_mask_hi = cat(source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo)
node _source_c_bits_a_mask_T = cat(source_c_bits_a_mask_hi, source_c_bits_a_mask_lo)
connect source_c_bits_a.mask, _source_c_bits_a_mask_T
connect source_c_bits_a.data, amo_data
connect source_c_bits_a.corrupt, _source_c_bits_T
connect source_c.bits, source_c_bits_a
node _decode_T = dshl(UInt<12>(0hfff), nodeIn.a.bits.size)
node _decode_T_1 = bits(_decode_T, 11, 0)
node _decode_T_2 = not(_decode_T_1)
node decode = shr(_decode_T_2, 3)
node _opdata_T = bits(nodeIn.a.bits.opcode, 2, 2)
node opdata = eq(_opdata_T, UInt<1>(0h0))
node _T_1 = mux(opdata, decode, UInt<1>(0h0))
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, nodeOut.a.ready)
node _readys_T = cat(source_i.valid, source_c.valid)
node _readys_T_1 = shl(_readys_T, 1)
node _readys_T_2 = bits(_readys_T_1, 1, 0)
node _readys_T_3 = or(_readys_T, _readys_T_2)
node _readys_T_4 = bits(_readys_T_3, 1, 0)
node _readys_T_5 = shl(_readys_T_4, 1)
node _readys_T_6 = bits(_readys_T_5, 1, 0)
node _readys_T_7 = not(_readys_T_6)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], source_c.valid)
node _winner_T_1 = and(readys[1], source_i.valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_3 = eq(winner[0], UInt<1>(0h0))
node _T_4 = or(_T_2, _T_3)
node _T_5 = eq(prefixOR_1, UInt<1>(0h0))
node _T_6 = eq(winner[1], UInt<1>(0h0))
node _T_7 = or(_T_5, _T_6)
node _T_8 = and(_T_4, _T_7)
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
node _T_11 = eq(_T_8, UInt<1>(0h0))
when _T_11 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_8, UInt<1>(0h1), "") : assert
node _T_12 = or(source_c.valid, source_i.valid)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = or(winner[0], winner[1])
node _T_15 = or(_T_13, _T_14)
node _T_16 = asUInt(reset)
node _T_17 = eq(_T_16, UInt<1>(0h0))
when _T_17 :
node _T_18 = eq(_T_15, UInt<1>(0h0))
when _T_18 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_15, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], UInt<1>(0h0), UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], _T_1, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(nodeOut.a.ready, nodeOut.a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _source_c_ready_T = and(nodeOut.a.ready, allowed[0])
connect source_c.ready, _source_c_ready_T
node _source_i_ready_T = and(nodeOut.a.ready, allowed[1])
connect source_i.ready, _source_i_ready_T
node _nodeOut_a_valid_T = or(source_c.valid, source_i.valid)
node _nodeOut_a_valid_T_1 = mux(state[0], source_c.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_2 = mux(state[1], source_i.valid, UInt<1>(0h0))
node _nodeOut_a_valid_T_3 = or(_nodeOut_a_valid_T_1, _nodeOut_a_valid_T_2)
wire _nodeOut_a_valid_WIRE : UInt<1>
connect _nodeOut_a_valid_WIRE, _nodeOut_a_valid_T_3
node _nodeOut_a_valid_T_4 = mux(idle, _nodeOut_a_valid_T, _nodeOut_a_valid_WIRE)
connect nodeOut.a.valid, _nodeOut_a_valid_T_4
wire _nodeOut_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _nodeOut_a_bits_T = mux(muxState[0], source_c.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_1 = mux(muxState[1], source_i.bits.corrupt, UInt<1>(0h0))
node _nodeOut_a_bits_T_2 = or(_nodeOut_a_bits_T, _nodeOut_a_bits_T_1)
wire _nodeOut_a_bits_WIRE_1 : UInt<1>
connect _nodeOut_a_bits_WIRE_1, _nodeOut_a_bits_T_2
connect _nodeOut_a_bits_WIRE.corrupt, _nodeOut_a_bits_WIRE_1
node _nodeOut_a_bits_T_3 = mux(muxState[0], source_c.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_4 = mux(muxState[1], source_i.bits.data, UInt<1>(0h0))
node _nodeOut_a_bits_T_5 = or(_nodeOut_a_bits_T_3, _nodeOut_a_bits_T_4)
wire _nodeOut_a_bits_WIRE_2 : UInt<64>
connect _nodeOut_a_bits_WIRE_2, _nodeOut_a_bits_T_5
connect _nodeOut_a_bits_WIRE.data, _nodeOut_a_bits_WIRE_2
node _nodeOut_a_bits_T_6 = mux(muxState[0], source_c.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_7 = mux(muxState[1], source_i.bits.mask, UInt<1>(0h0))
node _nodeOut_a_bits_T_8 = or(_nodeOut_a_bits_T_6, _nodeOut_a_bits_T_7)
wire _nodeOut_a_bits_WIRE_3 : UInt<8>
connect _nodeOut_a_bits_WIRE_3, _nodeOut_a_bits_T_8
connect _nodeOut_a_bits_WIRE.mask, _nodeOut_a_bits_WIRE_3
wire _nodeOut_a_bits_WIRE_4 : { }
connect _nodeOut_a_bits_WIRE.echo, _nodeOut_a_bits_WIRE_4
wire _nodeOut_a_bits_WIRE_5 : { }
connect _nodeOut_a_bits_WIRE.user, _nodeOut_a_bits_WIRE_5
node _nodeOut_a_bits_T_9 = mux(muxState[0], source_c.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_10 = mux(muxState[1], source_i.bits.address, UInt<1>(0h0))
node _nodeOut_a_bits_T_11 = or(_nodeOut_a_bits_T_9, _nodeOut_a_bits_T_10)
wire _nodeOut_a_bits_WIRE_6 : UInt<29>
connect _nodeOut_a_bits_WIRE_6, _nodeOut_a_bits_T_11
connect _nodeOut_a_bits_WIRE.address, _nodeOut_a_bits_WIRE_6
node _nodeOut_a_bits_T_12 = mux(muxState[0], source_c.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_13 = mux(muxState[1], source_i.bits.source, UInt<1>(0h0))
node _nodeOut_a_bits_T_14 = or(_nodeOut_a_bits_T_12, _nodeOut_a_bits_T_13)
wire _nodeOut_a_bits_WIRE_7 : UInt<8>
connect _nodeOut_a_bits_WIRE_7, _nodeOut_a_bits_T_14
connect _nodeOut_a_bits_WIRE.source, _nodeOut_a_bits_WIRE_7
node _nodeOut_a_bits_T_15 = mux(muxState[0], source_c.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_16 = mux(muxState[1], source_i.bits.size, UInt<1>(0h0))
node _nodeOut_a_bits_T_17 = or(_nodeOut_a_bits_T_15, _nodeOut_a_bits_T_16)
wire _nodeOut_a_bits_WIRE_8 : UInt<4>
connect _nodeOut_a_bits_WIRE_8, _nodeOut_a_bits_T_17
connect _nodeOut_a_bits_WIRE.size, _nodeOut_a_bits_WIRE_8
node _nodeOut_a_bits_T_18 = mux(muxState[0], source_c.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_19 = mux(muxState[1], source_i.bits.param, UInt<1>(0h0))
node _nodeOut_a_bits_T_20 = or(_nodeOut_a_bits_T_18, _nodeOut_a_bits_T_19)
wire _nodeOut_a_bits_WIRE_9 : UInt<3>
connect _nodeOut_a_bits_WIRE_9, _nodeOut_a_bits_T_20
connect _nodeOut_a_bits_WIRE.param, _nodeOut_a_bits_WIRE_9
node _nodeOut_a_bits_T_21 = mux(muxState[0], source_c.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_22 = mux(muxState[1], source_i.bits.opcode, UInt<1>(0h0))
node _nodeOut_a_bits_T_23 = or(_nodeOut_a_bits_T_21, _nodeOut_a_bits_T_22)
wire _nodeOut_a_bits_WIRE_10 : UInt<3>
connect _nodeOut_a_bits_WIRE_10, _nodeOut_a_bits_T_23
connect _nodeOut_a_bits_WIRE.opcode, _nodeOut_a_bits_WIRE_10
connect nodeOut.a.bits.corrupt, _nodeOut_a_bits_WIRE.corrupt
connect nodeOut.a.bits.data, _nodeOut_a_bits_WIRE.data
connect nodeOut.a.bits.mask, _nodeOut_a_bits_WIRE.mask
connect nodeOut.a.bits.address, _nodeOut_a_bits_WIRE.address
connect nodeOut.a.bits.source, _nodeOut_a_bits_WIRE.source
connect nodeOut.a.bits.size, _nodeOut_a_bits_WIRE.size
connect nodeOut.a.bits.param, _nodeOut_a_bits_WIRE.param
connect nodeOut.a.bits.opcode, _nodeOut_a_bits_WIRE.opcode
node _T_19 = and(source_i.ready, source_i.valid)
node _T_20 = eq(a_isSupported, UInt<1>(0h0))
node _T_21 = and(_T_19, _T_20)
when _T_21 :
when a_cam_sel_free_0 :
connect cam_a[0].fifoId, UInt<1>(0h0)
connect cam_a[0].bits, nodeIn.a.bits
node _cam_a_0_lut_T = bits(nodeIn.a.bits.param, 1, 0)
node _cam_a_0_lut_T_1 = eq(UInt<3>(0h1), _cam_a_0_lut_T)
node _cam_a_0_lut_T_2 = mux(_cam_a_0_lut_T_1, UInt<4>(0he), UInt<4>(0h8))
node _cam_a_0_lut_T_3 = eq(UInt<3>(0h0), _cam_a_0_lut_T)
node _cam_a_0_lut_T_4 = mux(_cam_a_0_lut_T_3, UInt<3>(0h6), _cam_a_0_lut_T_2)
node _cam_a_0_lut_T_5 = eq(UInt<3>(0h3), _cam_a_0_lut_T)
node _cam_a_0_lut_T_6 = mux(_cam_a_0_lut_T_5, UInt<4>(0hc), _cam_a_0_lut_T_4)
connect cam_a[0].lut, _cam_a_0_lut_T_6
when a_cam_sel_free_0 :
connect cam_s[0].state, UInt<2>(0h3)
node _T_22 = and(source_c.ready, source_c.valid)
when _T_22 :
when a_cam_sel_put_0 :
connect cam_s[0].state, UInt<1>(0h1)
node _d_first_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
node d_cam_sel_raw_0 = eq(cam_a[0].bits.source, nodeIn.d.bits.source)
node d_cam_sel_match_0 = and(d_cam_sel_raw_0, cam_dmatch_0)
node d_cam_sel_0 = mux(UInt<1>(0h0), a_cam_sel_free_0, d_cam_sel_match_0)
node d_cam_sel_any = or(UInt<1>(0h0), d_cam_sel_match_0)
node d_ackd = eq(nodeOut.d.bits.opcode, UInt<1>(0h1))
node d_ack = eq(nodeOut.d.bits.opcode, UInt<1>(0h0))
node _T_23 = and(nodeOut.d.ready, nodeOut.d.valid)
node _T_24 = and(_T_23, d_first)
when _T_24 :
node _T_25 = and(d_cam_sel_0, d_ackd)
when _T_25 :
connect cam_d[0].data, nodeOut.d.bits.data
connect cam_d[0].denied, nodeOut.d.bits.denied
connect cam_d[0].corrupt, nodeOut.d.bits.corrupt
when d_cam_sel_0 :
node _cam_s_0_state_T = mux(d_ackd, UInt<2>(0h2), UInt<1>(0h0))
connect cam_s[0].state, _cam_s_0_state_T
node _d_drop_T = and(d_first, d_ackd)
node d_drop = and(_d_drop_T, d_cam_sel_any)
node _d_replace_T = and(d_first, d_ack)
node d_replace = and(_d_replace_T, d_cam_sel_match_0)
node _nodeIn_d_valid_T = eq(d_drop, UInt<1>(0h0))
node _nodeIn_d_valid_T_1 = and(nodeOut.d.valid, _nodeIn_d_valid_T)
connect nodeIn.d.valid, _nodeIn_d_valid_T_1
node _nodeOut_d_ready_T = or(nodeIn.d.ready, d_drop)
connect nodeOut.d.ready, _nodeOut_d_ready_T
connect nodeIn.d.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn.d.bits.data, nodeOut.d.bits.data
connect nodeIn.d.bits.denied, nodeOut.d.bits.denied
connect nodeIn.d.bits.sink, nodeOut.d.bits.sink
connect nodeIn.d.bits.source, nodeOut.d.bits.source
connect nodeIn.d.bits.size, nodeOut.d.bits.size
connect nodeIn.d.bits.param, nodeOut.d.bits.param
connect nodeIn.d.bits.opcode, nodeOut.d.bits.opcode
when d_replace :
connect nodeIn.d.bits.opcode, UInt<1>(0h1)
connect nodeIn.d.bits.data, cam_d[0].data
node _nodeIn_d_bits_corrupt_T = or(cam_d[0].corrupt, nodeOut.d.bits.denied)
connect nodeIn.d.bits.corrupt, _nodeIn_d_bits_corrupt_T
node _nodeIn_d_bits_denied_T = or(cam_d[0].denied, nodeOut.d.bits.denied)
connect nodeIn.d.bits.denied, _nodeIn_d_bits_denied_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<29>(0h0)
connect _WIRE.bits.source, UInt<8>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<29>(0h0)
connect _WIRE_2.bits.source, UInt<8>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<29>(0h0)
connect _WIRE_8.bits.source, UInt<8>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0)
extmodule plusarg_reader_48 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_49 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLAtomicAutomata_cbus( // @[AtomicAutomata.scala:36:9]
input clock, // @[AtomicAutomata.scala:36:9]
input reset, // @[AtomicAutomata.scala:36:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[AtomicAutomata.scala:36:9]
wire [7:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[AtomicAutomata.scala:36:9]
wire [28:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AtomicAutomata.scala:36:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AtomicAutomata.scala:36:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[AtomicAutomata.scala:36:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[AtomicAutomata.scala:36:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[AtomicAutomata.scala:36:9]
wire [7:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire _a_canLogical_T = 1'h1; // @[Parameters.scala:92:28]
wire _a_canArithmetic_T = 1'h1; // @[Parameters.scala:92:28]
wire _a_cam_sel_put_T = 1'h1; // @[AtomicAutomata.scala:103:83]
wire _a_fifoId_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _a_cam_busy_T = 1'h1; // @[AtomicAutomata.scala:111:60]
wire _a_cam_sel_free_T = 1'h1; // @[AtomicAutomata.scala:116:85]
wire _source_c_bits_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _source_c_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _a_canLogical_T_16 = 1'h0; // @[Parameters.scala:684:29]
wire _a_canLogical_T_46 = 1'h0; // @[Parameters.scala:684:54]
wire _a_canArithmetic_T_16 = 1'h0; // @[Parameters.scala:684:29]
wire _a_canArithmetic_T_46 = 1'h0; // @[Parameters.scala:684:54]
wire _source_c_bits_legal_T_50 = 1'h0; // @[Parameters.scala:684:29]
wire _source_c_bits_legal_T_56 = 1'h0; // @[Parameters.scala:684:54]
wire maskedBeats_0 = 1'h0; // @[Arbiter.scala:82:69]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire [2:0] source_c_bits_opcode = 3'h0; // @[AtomicAutomata.scala:165:28]
wire [2:0] source_c_bits_param = 3'h0; // @[AtomicAutomata.scala:165:28]
wire [2:0] source_c_bits_a_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] source_c_bits_a_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] _nodeOut_a_bits_T_18 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _nodeOut_a_bits_T_21 = 3'h0; // @[Mux.scala:30:73]
wire [29:0] _a_fifoId_T_2 = 30'h0; // @[Parameters.scala:137:46]
wire [29:0] _a_fifoId_T_3 = 30'h0; // @[Parameters.scala:137:46]
wire [1:0] initval_state = 2'h0; // @[AtomicAutomata.scala:80:27]
wire [1:0] _cam_s_WIRE_0_state = 2'h0; // @[AtomicAutomata.scala:82:50]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [7:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire [28:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AtomicAutomata.scala:36:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[AtomicAutomata.scala:36:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [7:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_a_ready_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [1:0] auto_in_d_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_in_d_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [7:0] auto_in_d_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_bits_sink_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_bits_denied_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_in_d_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire auto_in_d_valid_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[AtomicAutomata.scala:36:9]
wire [2:0] auto_out_a_bits_param_0; // @[AtomicAutomata.scala:36:9]
wire [3:0] auto_out_a_bits_size_0; // @[AtomicAutomata.scala:36:9]
wire [7:0] auto_out_a_bits_source_0; // @[AtomicAutomata.scala:36:9]
wire [28:0] auto_out_a_bits_address_0; // @[AtomicAutomata.scala:36:9]
wire [7:0] auto_out_a_bits_mask_0; // @[AtomicAutomata.scala:36:9]
wire [63:0] auto_out_a_bits_data_0; // @[AtomicAutomata.scala:36:9]
wire auto_out_a_bits_corrupt_0; // @[AtomicAutomata.scala:36:9]
wire auto_out_a_valid_0; // @[AtomicAutomata.scala:36:9]
wire auto_out_d_ready_0; // @[AtomicAutomata.scala:36:9]
wire _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AtomicAutomata.scala:36:9]
wire [3:0] source_i_bits_size = nodeIn_a_bits_size; // @[AtomicAutomata.scala:154:28]
wire [7:0] source_i_bits_source = nodeIn_a_bits_source; // @[AtomicAutomata.scala:154:28]
wire [28:0] _a_canLogical_T_17 = nodeIn_a_bits_address; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_17 = nodeIn_a_bits_address; // @[Parameters.scala:137:31]
wire [28:0] _a_fifoId_T = nodeIn_a_bits_address; // @[Parameters.scala:137:31]
wire [28:0] source_i_bits_address = nodeIn_a_bits_address; // @[AtomicAutomata.scala:154:28]
wire [7:0] source_i_bits_mask = nodeIn_a_bits_mask; // @[AtomicAutomata.scala:154:28]
wire [63:0] source_i_bits_data = nodeIn_a_bits_data; // @[AtomicAutomata.scala:154:28]
wire source_i_bits_corrupt = nodeIn_a_bits_corrupt; // @[AtomicAutomata.scala:154:28]
wire _nodeIn_d_valid_T_1; // @[AtomicAutomata.scala:241:35]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AtomicAutomata.scala:36:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire _nodeOut_a_valid_T_4; // @[Arbiter.scala:96:24]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[AtomicAutomata.scala:36:9]
wire [2:0] _nodeOut_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[AtomicAutomata.scala:36:9]
wire [2:0] _nodeOut_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[AtomicAutomata.scala:36:9]
wire [3:0] _nodeOut_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[AtomicAutomata.scala:36:9]
wire [7:0] _nodeOut_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[AtomicAutomata.scala:36:9]
wire [28:0] _nodeOut_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[AtomicAutomata.scala:36:9]
wire [7:0] _nodeOut_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[AtomicAutomata.scala:36:9]
wire [63:0] _nodeOut_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[AtomicAutomata.scala:36:9]
wire _nodeOut_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[AtomicAutomata.scala:36:9]
wire _nodeOut_d_ready_T; // @[AtomicAutomata.scala:242:35]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[AtomicAutomata.scala:36:9]
assign nodeIn_d_bits_param = nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_sink = nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala:82:28]
reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala:83:24]
reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala:83:24]
reg [3:0] cam_a_0_bits_size; // @[AtomicAutomata.scala:83:24]
wire [3:0] source_c_bits_a_size = cam_a_0_bits_size; // @[Edges.scala:480:17]
wire [3:0] _source_c_bits_a_mask_sizeOH_T = cam_a_0_bits_size; // @[Misc.scala:202:34]
reg [7:0] cam_a_0_bits_source; // @[AtomicAutomata.scala:83:24]
wire [7:0] source_c_bits_a_source = cam_a_0_bits_source; // @[Edges.scala:480:17]
reg [28:0] cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24]
wire [28:0] _source_c_bits_legal_T_14 = cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24]
wire [28:0] source_c_bits_a_address = cam_a_0_bits_address; // @[Edges.scala:480:17]
reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24]
reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala:83:24]
reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24]
reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala:83:24]
reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala:84:24]
reg cam_d_0_denied; // @[AtomicAutomata.scala:84:24]
reg cam_d_0_corrupt; // @[AtomicAutomata.scala:84:24]
wire cam_free_0 = ~(|cam_s_0_state); // @[AtomicAutomata.scala:82:28, :86:44]
wire _a_cam_por_free_T = cam_free_0; // @[AtomicAutomata.scala:86:44, :115:58]
wire a_cam_sel_free_0 = cam_free_0; // @[AtomicAutomata.scala:86:44, :116:82]
wire _GEN = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala:82:28, :87:44]
wire cam_amo_0; // @[AtomicAutomata.scala:87:44]
assign cam_amo_0 = _GEN; // @[AtomicAutomata.scala:87:44]
wire _cam_abusy_T_1; // @[AtomicAutomata.scala:88:68]
assign _cam_abusy_T_1 = _GEN; // @[AtomicAutomata.scala:87:44, :88:68]
wire _a_cam_por_put_T = cam_amo_0; // @[AtomicAutomata.scala:87:44, :102:56]
wire a_cam_sel_put_0 = cam_amo_0; // @[AtomicAutomata.scala:87:44, :103:80]
wire source_c_valid = cam_amo_0; // @[AtomicAutomata.scala:87:44, :165:28]
wire _cam_abusy_T = &cam_s_0_state; // @[AtomicAutomata.scala:82:28, :88:49]
wire cam_abusy_0 = _cam_abusy_T | _cam_abusy_T_1; // @[AtomicAutomata.scala:88:{49,57,68}]
wire a_cam_busy = cam_abusy_0; // @[AtomicAutomata.scala:88:57, :111:96]
wire cam_dmatch_0 = |cam_s_0_state; // @[AtomicAutomata.scala:82:28, :86:44, :89:49]
wire _GEN_0 = nodeIn_a_bits_size < 4'h4; // @[Parameters.scala:92:38]
wire _a_canLogical_T_1; // @[Parameters.scala:92:38]
assign _a_canLogical_T_1 = _GEN_0; // @[Parameters.scala:92:38]
wire _a_canArithmetic_T_1; // @[Parameters.scala:92:38]
assign _a_canArithmetic_T_1 = _GEN_0; // @[Parameters.scala:92:38]
wire _a_canLogical_T_2 = _a_canLogical_T_1; // @[Parameters.scala:92:{33,38}]
wire _a_canLogical_T_3 = _a_canLogical_T_2; // @[Parameters.scala:684:29]
wire [28:0] _GEN_1 = {nodeIn_a_bits_address[28:13], nodeIn_a_bits_address[12:0] ^ 13'h1000}; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_4; // @[Parameters.scala:137:31]
assign _a_canLogical_T_4 = _GEN_1; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_4; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_4 = _GEN_1; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_5 = {1'h0, _a_canLogical_T_4}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_6 = _a_canLogical_T_5 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_7 = _a_canLogical_T_6; // @[Parameters.scala:137:46]
wire _a_canLogical_T_8 = _a_canLogical_T_7 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _GEN_2 = nodeIn_a_bits_address ^ 29'h10000000; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_9; // @[Parameters.scala:137:31]
assign _a_canLogical_T_9 = _GEN_2; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_9; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_9 = _GEN_2; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_10 = {1'h0, _a_canLogical_T_9}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_11 = _a_canLogical_T_10 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_12 = _a_canLogical_T_11; // @[Parameters.scala:137:46]
wire _a_canLogical_T_13 = _a_canLogical_T_12 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canLogical_T_14 = _a_canLogical_T_8 | _a_canLogical_T_13; // @[Parameters.scala:685:42]
wire _a_canLogical_T_15 = _a_canLogical_T_3 & _a_canLogical_T_14; // @[Parameters.scala:684:{29,54}, :685:42]
wire _a_canLogical_T_47 = _a_canLogical_T_15; // @[Parameters.scala:684:54, :686:26]
wire [29:0] _a_canLogical_T_18 = {1'h0, _a_canLogical_T_17}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_19 = _a_canLogical_T_18 & 30'h1A001000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_20 = _a_canLogical_T_19; // @[Parameters.scala:137:46]
wire _a_canLogical_T_21 = _a_canLogical_T_20 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _GEN_3 = {nodeIn_a_bits_address[28:17], nodeIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_22; // @[Parameters.scala:137:31]
assign _a_canLogical_T_22 = _GEN_3; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_22; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_22 = _GEN_3; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_23 = {1'h0, _a_canLogical_T_22}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_24 = _a_canLogical_T_23 & 30'h1A010000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_25 = _a_canLogical_T_24; // @[Parameters.scala:137:46]
wire _a_canLogical_T_26 = _a_canLogical_T_25 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _GEN_4 = {nodeIn_a_bits_address[28:26], nodeIn_a_bits_address[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_27; // @[Parameters.scala:137:31]
assign _a_canLogical_T_27 = _GEN_4; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_27; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_27 = _GEN_4; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_28 = {1'h0, _a_canLogical_T_27}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_29 = _a_canLogical_T_28 & 30'h1A010000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_30 = _a_canLogical_T_29; // @[Parameters.scala:137:46]
wire _a_canLogical_T_31 = _a_canLogical_T_30 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _GEN_5 = {nodeIn_a_bits_address[28:26], nodeIn_a_bits_address[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_32; // @[Parameters.scala:137:31]
assign _a_canLogical_T_32 = _GEN_5; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_32; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_32 = _GEN_5; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_33 = {1'h0, _a_canLogical_T_32}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_34 = _a_canLogical_T_33 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_35 = _a_canLogical_T_34; // @[Parameters.scala:137:46]
wire _a_canLogical_T_36 = _a_canLogical_T_35 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _GEN_6 = {nodeIn_a_bits_address[28], nodeIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [28:0] _a_canLogical_T_37; // @[Parameters.scala:137:31]
assign _a_canLogical_T_37 = _GEN_6; // @[Parameters.scala:137:31]
wire [28:0] _a_canArithmetic_T_37; // @[Parameters.scala:137:31]
assign _a_canArithmetic_T_37 = _GEN_6; // @[Parameters.scala:137:31]
wire [29:0] _a_canLogical_T_38 = {1'h0, _a_canLogical_T_37}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canLogical_T_39 = _a_canLogical_T_38 & 30'h18000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canLogical_T_40 = _a_canLogical_T_39; // @[Parameters.scala:137:46]
wire _a_canLogical_T_41 = _a_canLogical_T_40 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canLogical_T_42 = _a_canLogical_T_21 | _a_canLogical_T_26; // @[Parameters.scala:685:42]
wire _a_canLogical_T_43 = _a_canLogical_T_42 | _a_canLogical_T_31; // @[Parameters.scala:685:42]
wire _a_canLogical_T_44 = _a_canLogical_T_43 | _a_canLogical_T_36; // @[Parameters.scala:685:42]
wire _a_canLogical_T_45 = _a_canLogical_T_44 | _a_canLogical_T_41; // @[Parameters.scala:685:42]
wire _a_canLogical_T_48 = _a_canLogical_T_47; // @[Parameters.scala:686:26]
wire a_canLogical = _a_canLogical_T_48; // @[Parameters.scala:686:26]
wire _a_canArithmetic_T_2 = _a_canArithmetic_T_1; // @[Parameters.scala:92:{33,38}]
wire _a_canArithmetic_T_3 = _a_canArithmetic_T_2; // @[Parameters.scala:684:29]
wire [29:0] _a_canArithmetic_T_5 = {1'h0, _a_canArithmetic_T_4}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_6 = _a_canArithmetic_T_5 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_7 = _a_canArithmetic_T_6; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_8 = _a_canArithmetic_T_7 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [29:0] _a_canArithmetic_T_10 = {1'h0, _a_canArithmetic_T_9}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_11 = _a_canArithmetic_T_10 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_12 = _a_canArithmetic_T_11; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_13 = _a_canArithmetic_T_12 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canArithmetic_T_14 = _a_canArithmetic_T_8 | _a_canArithmetic_T_13; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_15 = _a_canArithmetic_T_3 & _a_canArithmetic_T_14; // @[Parameters.scala:684:{29,54}, :685:42]
wire _a_canArithmetic_T_47 = _a_canArithmetic_T_15; // @[Parameters.scala:684:54, :686:26]
wire [29:0] _a_canArithmetic_T_18 = {1'h0, _a_canArithmetic_T_17}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_19 = _a_canArithmetic_T_18 & 30'h1A001000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_20 = _a_canArithmetic_T_19; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_21 = _a_canArithmetic_T_20 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [29:0] _a_canArithmetic_T_23 = {1'h0, _a_canArithmetic_T_22}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_24 = _a_canArithmetic_T_23 & 30'h1A010000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_25 = _a_canArithmetic_T_24; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_26 = _a_canArithmetic_T_25 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [29:0] _a_canArithmetic_T_28 = {1'h0, _a_canArithmetic_T_27}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_29 = _a_canArithmetic_T_28 & 30'h1A010000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_30 = _a_canArithmetic_T_29; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_31 = _a_canArithmetic_T_30 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [29:0] _a_canArithmetic_T_33 = {1'h0, _a_canArithmetic_T_32}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_34 = _a_canArithmetic_T_33 & 30'h1A011000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_35 = _a_canArithmetic_T_34; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_36 = _a_canArithmetic_T_35 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [29:0] _a_canArithmetic_T_38 = {1'h0, _a_canArithmetic_T_37}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _a_canArithmetic_T_39 = _a_canArithmetic_T_38 & 30'h18000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _a_canArithmetic_T_40 = _a_canArithmetic_T_39; // @[Parameters.scala:137:46]
wire _a_canArithmetic_T_41 = _a_canArithmetic_T_40 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _a_canArithmetic_T_42 = _a_canArithmetic_T_21 | _a_canArithmetic_T_26; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_43 = _a_canArithmetic_T_42 | _a_canArithmetic_T_31; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_44 = _a_canArithmetic_T_43 | _a_canArithmetic_T_36; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_45 = _a_canArithmetic_T_44 | _a_canArithmetic_T_41; // @[Parameters.scala:685:42]
wire _a_canArithmetic_T_48 = _a_canArithmetic_T_47; // @[Parameters.scala:686:26]
wire a_canArithmetic = _a_canArithmetic_T_48; // @[Parameters.scala:686:26]
wire a_isLogical = nodeIn_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala:96:47]
wire a_isArithmetic = nodeIn_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala:97:47]
wire _a_isSupported_T = ~a_isArithmetic | a_canArithmetic; // @[AtomicAutomata.scala:95:45, :97:47, :98:63]
wire a_isSupported = a_isLogical ? a_canLogical : _a_isSupported_T; // @[AtomicAutomata.scala:94:45, :96:47, :98:{32,63}]
wire [29:0] _a_fifoId_T_1 = {1'h0, _a_fifoId_T}; // @[Parameters.scala:137:{31,41}]
wire _indexes_T = cam_a_0_bits_data[0]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_1 = cam_d_0_data[0]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_0 = {_indexes_T, _indexes_T_1}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_2 = cam_a_0_bits_data[1]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_3 = cam_d_0_data[1]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_1 = {_indexes_T_2, _indexes_T_3}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_4 = cam_a_0_bits_data[2]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_5 = cam_d_0_data[2]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_2 = {_indexes_T_4, _indexes_T_5}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_6 = cam_a_0_bits_data[3]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_7 = cam_d_0_data[3]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_3 = {_indexes_T_6, _indexes_T_7}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_8 = cam_a_0_bits_data[4]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_9 = cam_d_0_data[4]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_4 = {_indexes_T_8, _indexes_T_9}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_10 = cam_a_0_bits_data[5]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_11 = cam_d_0_data[5]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_5 = {_indexes_T_10, _indexes_T_11}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_12 = cam_a_0_bits_data[6]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_13 = cam_d_0_data[6]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_6 = {_indexes_T_12, _indexes_T_13}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_14 = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T = cam_a_0_bits_data[7]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_15 = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T = cam_d_0_data[7]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_7 = {_indexes_T_14, _indexes_T_15}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_16 = cam_a_0_bits_data[8]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_17 = cam_d_0_data[8]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_8 = {_indexes_T_16, _indexes_T_17}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_18 = cam_a_0_bits_data[9]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_19 = cam_d_0_data[9]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_9 = {_indexes_T_18, _indexes_T_19}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_20 = cam_a_0_bits_data[10]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_21 = cam_d_0_data[10]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_10 = {_indexes_T_20, _indexes_T_21}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_22 = cam_a_0_bits_data[11]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_23 = cam_d_0_data[11]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_11 = {_indexes_T_22, _indexes_T_23}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_24 = cam_a_0_bits_data[12]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_25 = cam_d_0_data[12]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_12 = {_indexes_T_24, _indexes_T_25}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_26 = cam_a_0_bits_data[13]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_27 = cam_d_0_data[13]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_13 = {_indexes_T_26, _indexes_T_27}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_28 = cam_a_0_bits_data[14]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_29 = cam_d_0_data[14]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_14 = {_indexes_T_28, _indexes_T_29}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_30 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_1 = cam_a_0_bits_data[15]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_31 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_1 = cam_d_0_data[15]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_15 = {_indexes_T_30, _indexes_T_31}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_32 = cam_a_0_bits_data[16]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_33 = cam_d_0_data[16]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_16 = {_indexes_T_32, _indexes_T_33}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_34 = cam_a_0_bits_data[17]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_35 = cam_d_0_data[17]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_17 = {_indexes_T_34, _indexes_T_35}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_36 = cam_a_0_bits_data[18]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_37 = cam_d_0_data[18]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_18 = {_indexes_T_36, _indexes_T_37}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_38 = cam_a_0_bits_data[19]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_39 = cam_d_0_data[19]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_19 = {_indexes_T_38, _indexes_T_39}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_40 = cam_a_0_bits_data[20]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_41 = cam_d_0_data[20]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_20 = {_indexes_T_40, _indexes_T_41}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_42 = cam_a_0_bits_data[21]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_43 = cam_d_0_data[21]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_21 = {_indexes_T_42, _indexes_T_43}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_44 = cam_a_0_bits_data[22]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_45 = cam_d_0_data[22]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_22 = {_indexes_T_44, _indexes_T_45}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_46 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_2 = cam_a_0_bits_data[23]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_47 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_2 = cam_d_0_data[23]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_23 = {_indexes_T_46, _indexes_T_47}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_48 = cam_a_0_bits_data[24]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_49 = cam_d_0_data[24]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_24 = {_indexes_T_48, _indexes_T_49}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_50 = cam_a_0_bits_data[25]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_51 = cam_d_0_data[25]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_25 = {_indexes_T_50, _indexes_T_51}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_52 = cam_a_0_bits_data[26]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_53 = cam_d_0_data[26]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_26 = {_indexes_T_52, _indexes_T_53}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_54 = cam_a_0_bits_data[27]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_55 = cam_d_0_data[27]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_27 = {_indexes_T_54, _indexes_T_55}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_56 = cam_a_0_bits_data[28]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_57 = cam_d_0_data[28]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_28 = {_indexes_T_56, _indexes_T_57}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_58 = cam_a_0_bits_data[29]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_59 = cam_d_0_data[29]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_29 = {_indexes_T_58, _indexes_T_59}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_60 = cam_a_0_bits_data[30]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_61 = cam_d_0_data[30]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_30 = {_indexes_T_60, _indexes_T_61}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_62 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_3 = cam_a_0_bits_data[31]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_63 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_3 = cam_d_0_data[31]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_31 = {_indexes_T_62, _indexes_T_63}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_64 = cam_a_0_bits_data[32]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_65 = cam_d_0_data[32]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_32 = {_indexes_T_64, _indexes_T_65}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_66 = cam_a_0_bits_data[33]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_67 = cam_d_0_data[33]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_33 = {_indexes_T_66, _indexes_T_67}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_68 = cam_a_0_bits_data[34]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_69 = cam_d_0_data[34]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_34 = {_indexes_T_68, _indexes_T_69}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_70 = cam_a_0_bits_data[35]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_71 = cam_d_0_data[35]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_35 = {_indexes_T_70, _indexes_T_71}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_72 = cam_a_0_bits_data[36]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_73 = cam_d_0_data[36]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_36 = {_indexes_T_72, _indexes_T_73}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_74 = cam_a_0_bits_data[37]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_75 = cam_d_0_data[37]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_37 = {_indexes_T_74, _indexes_T_75}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_76 = cam_a_0_bits_data[38]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_77 = cam_d_0_data[38]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_38 = {_indexes_T_76, _indexes_T_77}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_78 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_4 = cam_a_0_bits_data[39]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_79 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_4 = cam_d_0_data[39]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_39 = {_indexes_T_78, _indexes_T_79}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_80 = cam_a_0_bits_data[40]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_81 = cam_d_0_data[40]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_40 = {_indexes_T_80, _indexes_T_81}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_82 = cam_a_0_bits_data[41]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_83 = cam_d_0_data[41]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_41 = {_indexes_T_82, _indexes_T_83}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_84 = cam_a_0_bits_data[42]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_85 = cam_d_0_data[42]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_42 = {_indexes_T_84, _indexes_T_85}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_86 = cam_a_0_bits_data[43]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_87 = cam_d_0_data[43]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_43 = {_indexes_T_86, _indexes_T_87}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_88 = cam_a_0_bits_data[44]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_89 = cam_d_0_data[44]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_44 = {_indexes_T_88, _indexes_T_89}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_90 = cam_a_0_bits_data[45]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_91 = cam_d_0_data[45]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_45 = {_indexes_T_90, _indexes_T_91}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_92 = cam_a_0_bits_data[46]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_93 = cam_d_0_data[46]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_46 = {_indexes_T_92, _indexes_T_93}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_94 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_5 = cam_a_0_bits_data[47]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_95 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_5 = cam_d_0_data[47]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_47 = {_indexes_T_94, _indexes_T_95}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_96 = cam_a_0_bits_data[48]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_97 = cam_d_0_data[48]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_48 = {_indexes_T_96, _indexes_T_97}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_98 = cam_a_0_bits_data[49]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_99 = cam_d_0_data[49]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_49 = {_indexes_T_98, _indexes_T_99}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_100 = cam_a_0_bits_data[50]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_101 = cam_d_0_data[50]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_50 = {_indexes_T_100, _indexes_T_101}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_102 = cam_a_0_bits_data[51]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_103 = cam_d_0_data[51]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_51 = {_indexes_T_102, _indexes_T_103}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_104 = cam_a_0_bits_data[52]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_105 = cam_d_0_data[52]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_52 = {_indexes_T_104, _indexes_T_105}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_106 = cam_a_0_bits_data[53]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_107 = cam_d_0_data[53]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_53 = {_indexes_T_106, _indexes_T_107}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_108 = cam_a_0_bits_data[54]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_109 = cam_d_0_data[54]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_54 = {_indexes_T_108, _indexes_T_109}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_110 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_6 = cam_a_0_bits_data[55]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_111 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_6 = cam_d_0_data[55]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_55 = {_indexes_T_110, _indexes_T_111}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_112 = cam_a_0_bits_data[56]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_113 = cam_d_0_data[56]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_56 = {_indexes_T_112, _indexes_T_113}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_114 = cam_a_0_bits_data[57]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_115 = cam_d_0_data[57]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_57 = {_indexes_T_114, _indexes_T_115}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_116 = cam_a_0_bits_data[58]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_117 = cam_d_0_data[58]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_58 = {_indexes_T_116, _indexes_T_117}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_118 = cam_a_0_bits_data[59]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_119 = cam_d_0_data[59]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_59 = {_indexes_T_118, _indexes_T_119}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_120 = cam_a_0_bits_data[60]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_121 = cam_d_0_data[60]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_60 = {_indexes_T_120, _indexes_T_121}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_122 = cam_a_0_bits_data[61]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_123 = cam_d_0_data[61]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_61 = {_indexes_T_122, _indexes_T_123}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_124 = cam_a_0_bits_data[62]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _indexes_T_125 = cam_d_0_data[62]; // @[AtomicAutomata.scala:84:24, :119:73]
wire [1:0] indexes_62 = {_indexes_T_124, _indexes_T_125}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire _indexes_T_126 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63]
wire _signbits_a_T_7 = cam_a_0_bits_data[63]; // @[AtomicAutomata.scala:83:24, :119:63, :128:64]
wire _indexes_T_127 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73]
wire _signbits_d_T_7 = cam_d_0_data[63]; // @[AtomicAutomata.scala:84:24, :119:73, :129:64]
wire [1:0] indexes_63 = {_indexes_T_126, _indexes_T_127}; // @[AtomicAutomata.scala:119:{59,63,73}]
wire [3:0] _logic_out_T = cam_a_0_lut >> indexes_0; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_1 = _logic_out_T[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_2 = cam_a_0_lut >> indexes_1; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_3 = _logic_out_T_2[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_4 = cam_a_0_lut >> indexes_2; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_5 = _logic_out_T_4[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_6 = cam_a_0_lut >> indexes_3; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_7 = _logic_out_T_6[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_8 = cam_a_0_lut >> indexes_4; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_9 = _logic_out_T_8[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_10 = cam_a_0_lut >> indexes_5; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_11 = _logic_out_T_10[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_12 = cam_a_0_lut >> indexes_6; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_13 = _logic_out_T_12[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_14 = cam_a_0_lut >> indexes_7; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_15 = _logic_out_T_14[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_16 = cam_a_0_lut >> indexes_8; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_17 = _logic_out_T_16[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_18 = cam_a_0_lut >> indexes_9; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_19 = _logic_out_T_18[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_20 = cam_a_0_lut >> indexes_10; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_21 = _logic_out_T_20[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_22 = cam_a_0_lut >> indexes_11; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_23 = _logic_out_T_22[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_24 = cam_a_0_lut >> indexes_12; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_25 = _logic_out_T_24[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_26 = cam_a_0_lut >> indexes_13; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_27 = _logic_out_T_26[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_28 = cam_a_0_lut >> indexes_14; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_29 = _logic_out_T_28[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_30 = cam_a_0_lut >> indexes_15; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_31 = _logic_out_T_30[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_32 = cam_a_0_lut >> indexes_16; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_33 = _logic_out_T_32[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_34 = cam_a_0_lut >> indexes_17; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_35 = _logic_out_T_34[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_36 = cam_a_0_lut >> indexes_18; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_37 = _logic_out_T_36[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_38 = cam_a_0_lut >> indexes_19; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_39 = _logic_out_T_38[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_40 = cam_a_0_lut >> indexes_20; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_41 = _logic_out_T_40[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_42 = cam_a_0_lut >> indexes_21; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_43 = _logic_out_T_42[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_44 = cam_a_0_lut >> indexes_22; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_45 = _logic_out_T_44[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_46 = cam_a_0_lut >> indexes_23; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_47 = _logic_out_T_46[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_48 = cam_a_0_lut >> indexes_24; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_49 = _logic_out_T_48[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_50 = cam_a_0_lut >> indexes_25; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_51 = _logic_out_T_50[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_52 = cam_a_0_lut >> indexes_26; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_53 = _logic_out_T_52[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_54 = cam_a_0_lut >> indexes_27; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_55 = _logic_out_T_54[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_56 = cam_a_0_lut >> indexes_28; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_57 = _logic_out_T_56[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_58 = cam_a_0_lut >> indexes_29; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_59 = _logic_out_T_58[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_60 = cam_a_0_lut >> indexes_30; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_61 = _logic_out_T_60[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_62 = cam_a_0_lut >> indexes_31; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_63 = _logic_out_T_62[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_64 = cam_a_0_lut >> indexes_32; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_65 = _logic_out_T_64[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_66 = cam_a_0_lut >> indexes_33; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_67 = _logic_out_T_66[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_68 = cam_a_0_lut >> indexes_34; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_69 = _logic_out_T_68[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_70 = cam_a_0_lut >> indexes_35; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_71 = _logic_out_T_70[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_72 = cam_a_0_lut >> indexes_36; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_73 = _logic_out_T_72[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_74 = cam_a_0_lut >> indexes_37; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_75 = _logic_out_T_74[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_76 = cam_a_0_lut >> indexes_38; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_77 = _logic_out_T_76[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_78 = cam_a_0_lut >> indexes_39; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_79 = _logic_out_T_78[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_80 = cam_a_0_lut >> indexes_40; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_81 = _logic_out_T_80[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_82 = cam_a_0_lut >> indexes_41; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_83 = _logic_out_T_82[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_84 = cam_a_0_lut >> indexes_42; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_85 = _logic_out_T_84[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_86 = cam_a_0_lut >> indexes_43; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_87 = _logic_out_T_86[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_88 = cam_a_0_lut >> indexes_44; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_89 = _logic_out_T_88[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_90 = cam_a_0_lut >> indexes_45; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_91 = _logic_out_T_90[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_92 = cam_a_0_lut >> indexes_46; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_93 = _logic_out_T_92[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_94 = cam_a_0_lut >> indexes_47; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_95 = _logic_out_T_94[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_96 = cam_a_0_lut >> indexes_48; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_97 = _logic_out_T_96[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_98 = cam_a_0_lut >> indexes_49; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_99 = _logic_out_T_98[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_100 = cam_a_0_lut >> indexes_50; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_101 = _logic_out_T_100[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_102 = cam_a_0_lut >> indexes_51; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_103 = _logic_out_T_102[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_104 = cam_a_0_lut >> indexes_52; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_105 = _logic_out_T_104[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_106 = cam_a_0_lut >> indexes_53; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_107 = _logic_out_T_106[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_108 = cam_a_0_lut >> indexes_54; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_109 = _logic_out_T_108[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_110 = cam_a_0_lut >> indexes_55; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_111 = _logic_out_T_110[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_112 = cam_a_0_lut >> indexes_56; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_113 = _logic_out_T_112[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_114 = cam_a_0_lut >> indexes_57; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_115 = _logic_out_T_114[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_116 = cam_a_0_lut >> indexes_58; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_117 = _logic_out_T_116[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_118 = cam_a_0_lut >> indexes_59; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_119 = _logic_out_T_118[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_120 = cam_a_0_lut >> indexes_60; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_121 = _logic_out_T_120[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_122 = cam_a_0_lut >> indexes_61; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_123 = _logic_out_T_122[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_124 = cam_a_0_lut >> indexes_62; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_125 = _logic_out_T_124[0]; // @[AtomicAutomata.scala:120:57]
wire [3:0] _logic_out_T_126 = cam_a_0_lut >> indexes_63; // @[AtomicAutomata.scala:83:24, :119:59, :120:57]
wire _logic_out_T_127 = _logic_out_T_126[0]; // @[AtomicAutomata.scala:120:57]
wire [1:0] logic_out_lo_lo_lo_lo_lo = {_logic_out_T_3, _logic_out_T_1}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_lo_lo_hi = {_logic_out_T_7, _logic_out_T_5}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_lo_lo = {logic_out_lo_lo_lo_lo_hi, logic_out_lo_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_lo_lo_hi_lo = {_logic_out_T_11, _logic_out_T_9}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_lo_hi_hi = {_logic_out_T_15, _logic_out_T_13}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_lo_hi = {logic_out_lo_lo_lo_hi_hi, logic_out_lo_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_lo_lo = {logic_out_lo_lo_lo_hi, logic_out_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_lo_hi_lo_lo = {_logic_out_T_19, _logic_out_T_17}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_hi_lo_hi = {_logic_out_T_23, _logic_out_T_21}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_hi_lo = {logic_out_lo_lo_hi_lo_hi, logic_out_lo_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_lo_hi_hi_lo = {_logic_out_T_27, _logic_out_T_25}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_lo_hi_hi_hi = {_logic_out_T_31, _logic_out_T_29}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_lo_hi_hi = {logic_out_lo_lo_hi_hi_hi, logic_out_lo_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_lo_hi = {logic_out_lo_lo_hi_hi, logic_out_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_lo_lo = {logic_out_lo_lo_hi, logic_out_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_lo_lo_lo = {_logic_out_T_35, _logic_out_T_33}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_lo_lo_hi = {_logic_out_T_39, _logic_out_T_37}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_lo_lo = {logic_out_lo_hi_lo_lo_hi, logic_out_lo_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_lo_hi_lo = {_logic_out_T_43, _logic_out_T_41}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_lo_hi_hi = {_logic_out_T_47, _logic_out_T_45}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_lo_hi = {logic_out_lo_hi_lo_hi_hi, logic_out_lo_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_hi_lo = {logic_out_lo_hi_lo_hi, logic_out_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_hi_lo_lo = {_logic_out_T_51, _logic_out_T_49}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_hi_lo_hi = {_logic_out_T_55, _logic_out_T_53}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_hi_lo = {logic_out_lo_hi_hi_lo_hi, logic_out_lo_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_lo_hi_hi_hi_lo = {_logic_out_T_59, _logic_out_T_57}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_lo_hi_hi_hi_hi = {_logic_out_T_63, _logic_out_T_61}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_lo_hi_hi_hi = {logic_out_lo_hi_hi_hi_hi, logic_out_lo_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_lo_hi_hi = {logic_out_lo_hi_hi_hi, logic_out_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_lo_hi = {logic_out_lo_hi_hi, logic_out_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [31:0] logic_out_lo = {logic_out_lo_hi, logic_out_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_lo_lo_lo = {_logic_out_T_67, _logic_out_T_65}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_lo_lo_hi = {_logic_out_T_71, _logic_out_T_69}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_lo_lo = {logic_out_hi_lo_lo_lo_hi, logic_out_hi_lo_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_lo_hi_lo = {_logic_out_T_75, _logic_out_T_73}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_lo_hi_hi = {_logic_out_T_79, _logic_out_T_77}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_lo_hi = {logic_out_hi_lo_lo_hi_hi, logic_out_hi_lo_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_lo_lo = {logic_out_hi_lo_lo_hi, logic_out_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_hi_lo_lo = {_logic_out_T_83, _logic_out_T_81}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_hi_lo_hi = {_logic_out_T_87, _logic_out_T_85}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_hi_lo = {logic_out_hi_lo_hi_lo_hi, logic_out_hi_lo_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_lo_hi_hi_lo = {_logic_out_T_91, _logic_out_T_89}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_lo_hi_hi_hi = {_logic_out_T_95, _logic_out_T_93}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_lo_hi_hi = {logic_out_hi_lo_hi_hi_hi, logic_out_hi_lo_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_lo_hi = {logic_out_hi_lo_hi_hi, logic_out_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_hi_lo = {logic_out_hi_lo_hi, logic_out_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_lo_lo_lo = {_logic_out_T_99, _logic_out_T_97}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_lo_lo_hi = {_logic_out_T_103, _logic_out_T_101}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_lo_lo = {logic_out_hi_hi_lo_lo_hi, logic_out_hi_hi_lo_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_lo_hi_lo = {_logic_out_T_107, _logic_out_T_105}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_lo_hi_hi = {_logic_out_T_111, _logic_out_T_109}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_lo_hi = {logic_out_hi_hi_lo_hi_hi, logic_out_hi_hi_lo_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_hi_lo = {logic_out_hi_hi_lo_hi, logic_out_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_hi_lo_lo = {_logic_out_T_115, _logic_out_T_113}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_hi_lo_hi = {_logic_out_T_119, _logic_out_T_117}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_hi_lo = {logic_out_hi_hi_hi_lo_hi, logic_out_hi_hi_hi_lo_lo}; // @[AtomicAutomata.scala:120:28]
wire [1:0] logic_out_hi_hi_hi_hi_lo = {_logic_out_T_123, _logic_out_T_121}; // @[AtomicAutomata.scala:120:{28,57}]
wire [1:0] logic_out_hi_hi_hi_hi_hi = {_logic_out_T_127, _logic_out_T_125}; // @[AtomicAutomata.scala:120:{28,57}]
wire [3:0] logic_out_hi_hi_hi_hi = {logic_out_hi_hi_hi_hi_hi, logic_out_hi_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [7:0] logic_out_hi_hi_hi = {logic_out_hi_hi_hi_hi, logic_out_hi_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [15:0] logic_out_hi_hi = {logic_out_hi_hi_hi, logic_out_hi_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [31:0] logic_out_hi = {logic_out_hi_hi, logic_out_hi_lo}; // @[AtomicAutomata.scala:120:28]
wire [63:0] logic_out = {logic_out_hi, logic_out_lo}; // @[AtomicAutomata.scala:120:28]
wire unsigned_0 = cam_a_0_bits_param[1]; // @[AtomicAutomata.scala:83:24, :123:42]
wire take_max = cam_a_0_bits_param[0]; // @[AtomicAutomata.scala:83:24, :124:42]
wire adder = cam_a_0_bits_param[2]; // @[AtomicAutomata.scala:83:24, :125:39]
wire [7:0] _signSel_T = ~cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24, :127:25]
wire [6:0] _signSel_T_1 = cam_a_0_bits_mask[7:1]; // @[AtomicAutomata.scala:83:24, :127:39]
wire [7:0] _signSel_T_2 = {_signSel_T[7], _signSel_T[6:0] | _signSel_T_1}; // @[AtomicAutomata.scala:127:{25,31,39}]
wire [7:0] signSel = ~_signSel_T_2; // @[AtomicAutomata.scala:127:{23,31}]
wire [1:0] signbits_a_lo_lo = {_signbits_a_T_1, _signbits_a_T}; // @[AtomicAutomata.scala:128:{29,64}]
wire [1:0] signbits_a_lo_hi = {_signbits_a_T_3, _signbits_a_T_2}; // @[AtomicAutomata.scala:128:{29,64}]
wire [3:0] signbits_a_lo = {signbits_a_lo_hi, signbits_a_lo_lo}; // @[AtomicAutomata.scala:128:29]
wire [1:0] signbits_a_hi_lo = {_signbits_a_T_5, _signbits_a_T_4}; // @[AtomicAutomata.scala:128:{29,64}]
wire [1:0] signbits_a_hi_hi = {_signbits_a_T_7, _signbits_a_T_6}; // @[AtomicAutomata.scala:128:{29,64}]
wire [3:0] signbits_a_hi = {signbits_a_hi_hi, signbits_a_hi_lo}; // @[AtomicAutomata.scala:128:29]
wire [7:0] signbits_a = {signbits_a_hi, signbits_a_lo}; // @[AtomicAutomata.scala:128:29]
wire [1:0] signbits_d_lo_lo = {_signbits_d_T_1, _signbits_d_T}; // @[AtomicAutomata.scala:129:{29,64}]
wire [1:0] signbits_d_lo_hi = {_signbits_d_T_3, _signbits_d_T_2}; // @[AtomicAutomata.scala:129:{29,64}]
wire [3:0] signbits_d_lo = {signbits_d_lo_hi, signbits_d_lo_lo}; // @[AtomicAutomata.scala:129:29]
wire [1:0] signbits_d_hi_lo = {_signbits_d_T_5, _signbits_d_T_4}; // @[AtomicAutomata.scala:129:{29,64}]
wire [1:0] signbits_d_hi_hi = {_signbits_d_T_7, _signbits_d_T_6}; // @[AtomicAutomata.scala:129:{29,64}]
wire [3:0] signbits_d_hi = {signbits_d_hi_hi, signbits_d_hi_lo}; // @[AtomicAutomata.scala:129:29]
wire [7:0] signbits_d = {signbits_d_hi, signbits_d_lo}; // @[AtomicAutomata.scala:129:29]
wire [7:0] _signbit_a_T = signbits_a & signSel; // @[AtomicAutomata.scala:127:23, :128:29, :131:38]
wire [8:0] _signbit_a_T_1 = {_signbit_a_T, 1'h0}; // @[AtomicAutomata.scala:131:{38,49}]
wire [7:0] signbit_a = _signbit_a_T_1[7:0]; // @[AtomicAutomata.scala:131:{49,54}]
wire [7:0] _signbit_d_T = signbits_d & signSel; // @[AtomicAutomata.scala:127:23, :129:29, :132:38]
wire [8:0] _signbit_d_T_1 = {_signbit_d_T, 1'h0}; // @[AtomicAutomata.scala:132:{38,49}]
wire [7:0] signbit_d = _signbit_d_T_1[7:0]; // @[AtomicAutomata.scala:132:{49,54}]
wire [8:0] _signext_a_T = {signbit_a, 1'h0}; // @[package.scala:253:48]
wire [7:0] _signext_a_T_1 = _signext_a_T[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_a_T_2 = signbit_a | _signext_a_T_1; // @[package.scala:253:{43,53}]
wire [9:0] _signext_a_T_3 = {_signext_a_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_a_T_4 = _signext_a_T_3[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_a_T_5 = _signext_a_T_2 | _signext_a_T_4; // @[package.scala:253:{43,53}]
wire [11:0] _signext_a_T_6 = {_signext_a_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_a_T_7 = _signext_a_T_6[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_a_T_8 = _signext_a_T_5 | _signext_a_T_7; // @[package.scala:253:{43,53}]
wire [7:0] _signext_a_T_9 = _signext_a_T_8; // @[package.scala:253:43, :254:17]
wire _signext_a_T_10 = _signext_a_T_9[0]; // @[package.scala:254:17]
wire _signext_a_T_11 = _signext_a_T_9[1]; // @[package.scala:254:17]
wire _signext_a_T_12 = _signext_a_T_9[2]; // @[package.scala:254:17]
wire _signext_a_T_13 = _signext_a_T_9[3]; // @[package.scala:254:17]
wire _signext_a_T_14 = _signext_a_T_9[4]; // @[package.scala:254:17]
wire _signext_a_T_15 = _signext_a_T_9[5]; // @[package.scala:254:17]
wire _signext_a_T_16 = _signext_a_T_9[6]; // @[package.scala:254:17]
wire _signext_a_T_17 = _signext_a_T_9[7]; // @[package.scala:254:17]
wire [7:0] _signext_a_T_18 = {8{_signext_a_T_10}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_19 = {8{_signext_a_T_11}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_20 = {8{_signext_a_T_12}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_21 = {8{_signext_a_T_13}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_22 = {8{_signext_a_T_14}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_23 = {8{_signext_a_T_15}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_24 = {8{_signext_a_T_16}}; // @[AtomicAutomata.scala:133:40]
wire [7:0] _signext_a_T_25 = {8{_signext_a_T_17}}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_lo_lo = {_signext_a_T_19, _signext_a_T_18}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_lo_hi = {_signext_a_T_21, _signext_a_T_20}; // @[AtomicAutomata.scala:133:40]
wire [31:0] signext_a_lo = {signext_a_lo_hi, signext_a_lo_lo}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_hi_lo = {_signext_a_T_23, _signext_a_T_22}; // @[AtomicAutomata.scala:133:40]
wire [15:0] signext_a_hi_hi = {_signext_a_T_25, _signext_a_T_24}; // @[AtomicAutomata.scala:133:40]
wire [31:0] signext_a_hi = {signext_a_hi_hi, signext_a_hi_lo}; // @[AtomicAutomata.scala:133:40]
wire [63:0] signext_a = {signext_a_hi, signext_a_lo}; // @[AtomicAutomata.scala:133:40]
wire [8:0] _signext_d_T = {signbit_d, 1'h0}; // @[package.scala:253:48]
wire [7:0] _signext_d_T_1 = _signext_d_T[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_d_T_2 = signbit_d | _signext_d_T_1; // @[package.scala:253:{43,53}]
wire [9:0] _signext_d_T_3 = {_signext_d_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_d_T_4 = _signext_d_T_3[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_d_T_5 = _signext_d_T_2 | _signext_d_T_4; // @[package.scala:253:{43,53}]
wire [11:0] _signext_d_T_6 = {_signext_d_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [7:0] _signext_d_T_7 = _signext_d_T_6[7:0]; // @[package.scala:253:{48,53}]
wire [7:0] _signext_d_T_8 = _signext_d_T_5 | _signext_d_T_7; // @[package.scala:253:{43,53}]
wire [7:0] _signext_d_T_9 = _signext_d_T_8; // @[package.scala:253:43, :254:17]
wire _signext_d_T_10 = _signext_d_T_9[0]; // @[package.scala:254:17]
wire _signext_d_T_11 = _signext_d_T_9[1]; // @[package.scala:254:17]
wire _signext_d_T_12 = _signext_d_T_9[2]; // @[package.scala:254:17]
wire _signext_d_T_13 = _signext_d_T_9[3]; // @[package.scala:254:17]
wire _signext_d_T_14 = _signext_d_T_9[4]; // @[package.scala:254:17]
wire _signext_d_T_15 = _signext_d_T_9[5]; // @[package.scala:254:17]
wire _signext_d_T_16 = _signext_d_T_9[6]; // @[package.scala:254:17]
wire _signext_d_T_17 = _signext_d_T_9[7]; // @[package.scala:254:17]
wire [7:0] _signext_d_T_18 = {8{_signext_d_T_10}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_19 = {8{_signext_d_T_11}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_20 = {8{_signext_d_T_12}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_21 = {8{_signext_d_T_13}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_22 = {8{_signext_d_T_14}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_23 = {8{_signext_d_T_15}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_24 = {8{_signext_d_T_16}}; // @[AtomicAutomata.scala:134:40]
wire [7:0] _signext_d_T_25 = {8{_signext_d_T_17}}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_lo_lo = {_signext_d_T_19, _signext_d_T_18}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_lo_hi = {_signext_d_T_21, _signext_d_T_20}; // @[AtomicAutomata.scala:134:40]
wire [31:0] signext_d_lo = {signext_d_lo_hi, signext_d_lo_lo}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_hi_lo = {_signext_d_T_23, _signext_d_T_22}; // @[AtomicAutomata.scala:134:40]
wire [15:0] signext_d_hi_hi = {_signext_d_T_25, _signext_d_T_24}; // @[AtomicAutomata.scala:134:40]
wire [31:0] signext_d_hi = {signext_d_hi_hi, signext_d_hi_lo}; // @[AtomicAutomata.scala:134:40]
wire [63:0] signext_d = {signext_d_hi, signext_d_lo}; // @[AtomicAutomata.scala:134:40]
wire _wide_mask_T = cam_a_0_bits_mask[0]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_1 = cam_a_0_bits_mask[1]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_2 = cam_a_0_bits_mask[2]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_3 = cam_a_0_bits_mask[3]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_4 = cam_a_0_bits_mask[4]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_5 = cam_a_0_bits_mask[5]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_6 = cam_a_0_bits_mask[6]; // @[AtomicAutomata.scala:83:24, :136:40]
wire _wide_mask_T_7 = cam_a_0_bits_mask[7]; // @[AtomicAutomata.scala:83:24, :136:40]
wire [7:0] _wide_mask_T_8 = {8{_wide_mask_T}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_9 = {8{_wide_mask_T_1}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_10 = {8{_wide_mask_T_2}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_11 = {8{_wide_mask_T_3}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_12 = {8{_wide_mask_T_4}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_13 = {8{_wide_mask_T_5}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_14 = {8{_wide_mask_T_6}}; // @[AtomicAutomata.scala:136:40]
wire [7:0] _wide_mask_T_15 = {8{_wide_mask_T_7}}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_lo_lo = {_wide_mask_T_9, _wide_mask_T_8}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_lo_hi = {_wide_mask_T_11, _wide_mask_T_10}; // @[AtomicAutomata.scala:136:40]
wire [31:0] wide_mask_lo = {wide_mask_lo_hi, wide_mask_lo_lo}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_hi_lo = {_wide_mask_T_13, _wide_mask_T_12}; // @[AtomicAutomata.scala:136:40]
wire [15:0] wide_mask_hi_hi = {_wide_mask_T_15, _wide_mask_T_14}; // @[AtomicAutomata.scala:136:40]
wire [31:0] wide_mask_hi = {wide_mask_hi_hi, wide_mask_hi_lo}; // @[AtomicAutomata.scala:136:40]
wire [63:0] wide_mask = {wide_mask_hi, wide_mask_lo}; // @[AtomicAutomata.scala:136:40]
wire [63:0] _a_a_ext_T = cam_a_0_bits_data & wide_mask; // @[AtomicAutomata.scala:83:24, :136:40, :137:28]
wire [63:0] a_a_ext = _a_a_ext_T | signext_a; // @[AtomicAutomata.scala:133:40, :137:{28,41}]
wire [63:0] _a_d_ext_T = cam_d_0_data & wide_mask; // @[AtomicAutomata.scala:84:24, :136:40, :138:28]
wire [63:0] a_d_ext = _a_d_ext_T | signext_d; // @[AtomicAutomata.scala:134:40, :138:{28,41}]
wire [63:0] _a_d_inv_T = ~a_d_ext; // @[AtomicAutomata.scala:138:41, :139:43]
wire [63:0] a_d_inv = adder ? a_d_ext : _a_d_inv_T; // @[AtomicAutomata.scala:125:39, :138:41, :139:{26,43}]
wire [64:0] _adder_out_T = {1'h0, a_a_ext} + {1'h0, a_d_inv}; // @[AtomicAutomata.scala:137:41, :139:26, :140:33]
wire [63:0] adder_out = _adder_out_T[63:0]; // @[AtomicAutomata.scala:140:33]
wire _a_bigger_uneq_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49]
wire _a_bigger_T = a_a_ext[63]; // @[AtomicAutomata.scala:137:41, :142:49, :143:35]
wire a_bigger_uneq = unsigned_0 == _a_bigger_uneq_T; // @[AtomicAutomata.scala:123:42, :142:{38,49}]
wire _a_bigger_T_1 = a_d_ext[63]; // @[AtomicAutomata.scala:138:41, :143:50]
wire _a_bigger_T_2 = _a_bigger_T == _a_bigger_T_1; // @[AtomicAutomata.scala:143:{35,39,50}]
wire _a_bigger_T_3 = adder_out[63]; // @[AtomicAutomata.scala:140:33, :143:65]
wire _a_bigger_T_4 = ~_a_bigger_T_3; // @[AtomicAutomata.scala:143:{55,65}]
wire a_bigger = _a_bigger_T_2 ? _a_bigger_T_4 : a_bigger_uneq; // @[AtomicAutomata.scala:142:38, :143:{27,39,55}]
wire pick_a = take_max == a_bigger; // @[AtomicAutomata.scala:124:42, :143:27, :144:31]
wire [63:0] _arith_out_T = pick_a ? cam_a_0_bits_data : cam_d_0_data; // @[AtomicAutomata.scala:83:24, :84:24, :144:31, :145:50]
wire [63:0] arith_out = adder ? adder_out : _arith_out_T; // @[AtomicAutomata.scala:125:39, :140:33, :145:{28,50}]
wire _amo_data_T = cam_a_0_bits_opcode[0]; // @[AtomicAutomata.scala:83:24, :151:34]
wire [63:0] amo_data = _amo_data_T ? logic_out : arith_out; // @[AtomicAutomata.scala:120:28, :145:28, :151:{14,34}]
wire [63:0] source_c_bits_a_data = amo_data; // @[Edges.scala:480:17]
wire _source_i_ready_T; // @[Arbiter.scala:94:31]
wire _source_i_valid_T; // @[AtomicAutomata.scala:157:38]
wire [2:0] source_i_bits_opcode; // @[AtomicAutomata.scala:154:28]
wire [2:0] source_i_bits_param; // @[AtomicAutomata.scala:154:28]
wire source_i_ready; // @[AtomicAutomata.scala:154:28]
wire source_i_valid; // @[AtomicAutomata.scala:154:28]
wire _a_allow_T = ~a_cam_busy; // @[AtomicAutomata.scala:111:96, :155:23]
wire _a_allow_T_1 = a_isSupported | cam_free_0; // @[AtomicAutomata.scala:86:44, :98:32, :155:53]
wire a_allow = _a_allow_T & _a_allow_T_1; // @[AtomicAutomata.scala:155:{23,35,53}]
assign _nodeIn_a_ready_T = source_i_ready & a_allow; // @[AtomicAutomata.scala:154:28, :155:35, :156:38]
assign nodeIn_a_ready = _nodeIn_a_ready_T; // @[AtomicAutomata.scala:156:38]
assign _source_i_valid_T = nodeIn_a_valid & a_allow; // @[AtomicAutomata.scala:155:35, :157:38]
assign source_i_valid = _source_i_valid_T; // @[AtomicAutomata.scala:154:28, :157:38]
assign source_i_bits_opcode = a_isSupported ? nodeIn_a_bits_opcode : 3'h4; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :160:32]
assign source_i_bits_param = a_isSupported ? nodeIn_a_bits_param : 3'h0; // @[AtomicAutomata.scala:98:32, :154:28, :158:24, :159:31, :161:32]
wire _source_c_ready_T; // @[Arbiter.scala:94:31]
wire [7:0] source_c_bits_a_mask; // @[Edges.scala:480:17]
wire source_c_bits_a_corrupt; // @[Edges.scala:480:17]
wire [3:0] source_c_bits_size; // @[AtomicAutomata.scala:165:28]
wire [7:0] source_c_bits_source; // @[AtomicAutomata.scala:165:28]
wire [28:0] source_c_bits_address; // @[AtomicAutomata.scala:165:28]
wire [7:0] source_c_bits_mask; // @[AtomicAutomata.scala:165:28]
wire [63:0] source_c_bits_data; // @[AtomicAutomata.scala:165:28]
wire source_c_bits_corrupt; // @[AtomicAutomata.scala:165:28]
wire source_c_ready; // @[AtomicAutomata.scala:165:28]
wire _source_c_bits_T = cam_a_0_bits_corrupt | cam_d_0_corrupt; // @[AtomicAutomata.scala:83:24, :84:24, :172:45]
assign source_c_bits_a_corrupt = _source_c_bits_T; // @[Edges.scala:480:17]
wire _source_c_bits_legal_T_1 = cam_a_0_bits_size < 4'hD; // @[AtomicAutomata.scala:83:24]
wire _source_c_bits_legal_T_2 = _source_c_bits_legal_T_1; // @[Parameters.scala:92:{33,38}]
wire _source_c_bits_legal_T_3 = _source_c_bits_legal_T_2; // @[Parameters.scala:684:29]
wire [28:0] _source_c_bits_legal_T_4 = {cam_a_0_bits_address[28:14], cam_a_0_bits_address[13:0] ^ 14'h3000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_5 = {1'h0, _source_c_bits_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_6 = _source_c_bits_legal_T_5 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_7 = _source_c_bits_legal_T_6; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_8 = _source_c_bits_legal_T_7 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _source_c_bits_legal_T_9 = _source_c_bits_legal_T_3 & _source_c_bits_legal_T_8; // @[Parameters.scala:684:{29,54}]
wire _source_c_bits_legal_T_57 = _source_c_bits_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire _source_c_bits_legal_T_11 = cam_a_0_bits_size < 4'h7; // @[AtomicAutomata.scala:83:24]
wire _source_c_bits_legal_T_12 = _source_c_bits_legal_T_11; // @[Parameters.scala:92:{33,38}]
wire _source_c_bits_legal_T_13 = _source_c_bits_legal_T_12; // @[Parameters.scala:684:29]
wire [29:0] _source_c_bits_legal_T_15 = {1'h0, _source_c_bits_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_16 = _source_c_bits_legal_T_15 & 30'h1A112000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_17 = _source_c_bits_legal_T_16; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_18 = _source_c_bits_legal_T_17 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _source_c_bits_legal_T_19 = {cam_a_0_bits_address[28:21], cam_a_0_bits_address[20:0] ^ 21'h100000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_20 = {1'h0, _source_c_bits_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_21 = _source_c_bits_legal_T_20 & 30'h1A103000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_22 = _source_c_bits_legal_T_21; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_23 = _source_c_bits_legal_T_22 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _source_c_bits_legal_T_24 = {cam_a_0_bits_address[28:26], cam_a_0_bits_address[25:0] ^ 26'h2000000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_25 = {1'h0, _source_c_bits_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_26 = _source_c_bits_legal_T_25 & 30'h1A110000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_27 = _source_c_bits_legal_T_26; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_28 = _source_c_bits_legal_T_27 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _source_c_bits_legal_T_29 = {cam_a_0_bits_address[28:26], cam_a_0_bits_address[25:0] ^ 26'h2010000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_30 = {1'h0, _source_c_bits_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_31 = _source_c_bits_legal_T_30 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_32 = _source_c_bits_legal_T_31; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_33 = _source_c_bits_legal_T_32 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _source_c_bits_legal_T_34 = {cam_a_0_bits_address[28], cam_a_0_bits_address[27:0] ^ 28'h8000000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_35 = {1'h0, _source_c_bits_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_36 = _source_c_bits_legal_T_35 & 30'h18000000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_37 = _source_c_bits_legal_T_36; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_38 = _source_c_bits_legal_T_37 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire [28:0] _source_c_bits_legal_T_39 = cam_a_0_bits_address ^ 29'h10000000; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_40 = {1'h0, _source_c_bits_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_41 = _source_c_bits_legal_T_40 & 30'h1A113000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_42 = _source_c_bits_legal_T_41; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_43 = _source_c_bits_legal_T_42 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _source_c_bits_legal_T_44 = _source_c_bits_legal_T_18 | _source_c_bits_legal_T_23; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_45 = _source_c_bits_legal_T_44 | _source_c_bits_legal_T_28; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_46 = _source_c_bits_legal_T_45 | _source_c_bits_legal_T_33; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_47 = _source_c_bits_legal_T_46 | _source_c_bits_legal_T_38; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_48 = _source_c_bits_legal_T_47 | _source_c_bits_legal_T_43; // @[Parameters.scala:685:42]
wire _source_c_bits_legal_T_49 = _source_c_bits_legal_T_13 & _source_c_bits_legal_T_48; // @[Parameters.scala:684:{29,54}, :685:42]
wire [28:0] _source_c_bits_legal_T_51 = {cam_a_0_bits_address[28:17], cam_a_0_bits_address[16:0] ^ 17'h10000}; // @[AtomicAutomata.scala:83:24]
wire [29:0] _source_c_bits_legal_T_52 = {1'h0, _source_c_bits_legal_T_51}; // @[Parameters.scala:137:{31,41}]
wire [29:0] _source_c_bits_legal_T_53 = _source_c_bits_legal_T_52 & 30'h1A110000; // @[Parameters.scala:137:{41,46}]
wire [29:0] _source_c_bits_legal_T_54 = _source_c_bits_legal_T_53; // @[Parameters.scala:137:46]
wire _source_c_bits_legal_T_55 = _source_c_bits_legal_T_54 == 30'h0; // @[Parameters.scala:137:{46,59}]
wire _source_c_bits_legal_T_58 = _source_c_bits_legal_T_57 | _source_c_bits_legal_T_49; // @[Parameters.scala:684:54, :686:26]
wire source_c_bits_legal = _source_c_bits_legal_T_58; // @[Parameters.scala:686:26]
assign source_c_bits_size = source_c_bits_a_size; // @[Edges.scala:480:17]
assign source_c_bits_source = source_c_bits_a_source; // @[Edges.scala:480:17]
assign source_c_bits_address = source_c_bits_a_address; // @[Edges.scala:480:17]
wire [7:0] _source_c_bits_a_mask_T; // @[Misc.scala:222:10]
assign source_c_bits_mask = source_c_bits_a_mask; // @[Edges.scala:480:17]
assign source_c_bits_data = source_c_bits_a_data; // @[Edges.scala:480:17]
assign source_c_bits_corrupt = source_c_bits_a_corrupt; // @[Edges.scala:480:17]
wire [1:0] source_c_bits_a_mask_sizeOH_shiftAmount = _source_c_bits_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _source_c_bits_a_mask_sizeOH_T_1 = 4'h1 << source_c_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _source_c_bits_a_mask_sizeOH_T_2 = _source_c_bits_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] source_c_bits_a_mask_sizeOH = {_source_c_bits_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire source_c_bits_a_mask_sub_sub_sub_0_1 = cam_a_0_bits_size > 4'h2; // @[Misc.scala:206:21]
wire source_c_bits_a_mask_sub_sub_size = source_c_bits_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire source_c_bits_a_mask_sub_sub_bit = cam_a_0_bits_address[2]; // @[Misc.scala:210:26]
wire source_c_bits_a_mask_sub_sub_1_2 = source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire source_c_bits_a_mask_sub_sub_nbit = ~source_c_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire source_c_bits_a_mask_sub_sub_0_2 = source_c_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_sub_sub_acc_T = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _source_c_bits_a_mask_sub_sub_acc_T_1 = source_c_bits_a_mask_sub_sub_size & source_c_bits_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 | _source_c_bits_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire source_c_bits_a_mask_sub_size = source_c_bits_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire source_c_bits_a_mask_sub_bit = cam_a_0_bits_address[1]; // @[Misc.scala:210:26]
wire source_c_bits_a_mask_sub_nbit = ~source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire source_c_bits_a_mask_sub_0_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_sub_acc_T = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_sub_1_2 = source_c_bits_a_mask_sub_sub_0_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_sub_acc_T_1 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 | _source_c_bits_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_sub_2_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_sub_acc_T_2 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_sub_3_2 = source_c_bits_a_mask_sub_sub_1_2 & source_c_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_sub_acc_T_3 = source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 | _source_c_bits_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_size = source_c_bits_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire source_c_bits_a_mask_bit = cam_a_0_bits_address[0]; // @[Misc.scala:210:26]
wire source_c_bits_a_mask_nbit = ~source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire source_c_bits_a_mask_eq = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T = source_c_bits_a_mask_size & source_c_bits_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_1 = source_c_bits_a_mask_sub_0_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_1 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_1 = source_c_bits_a_mask_sub_0_1 | _source_c_bits_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_2 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T_2 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_2 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_3 = source_c_bits_a_mask_sub_1_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_3 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_3 = source_c_bits_a_mask_sub_1_1 | _source_c_bits_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_4 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T_4 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_4 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_5 = source_c_bits_a_mask_sub_2_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_5 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_5 = source_c_bits_a_mask_sub_2_1 | _source_c_bits_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_6 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _source_c_bits_a_mask_acc_T_6 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_6 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire source_c_bits_a_mask_eq_7 = source_c_bits_a_mask_sub_3_2 & source_c_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _source_c_bits_a_mask_acc_T_7 = source_c_bits_a_mask_size & source_c_bits_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire source_c_bits_a_mask_acc_7 = source_c_bits_a_mask_sub_3_1 | _source_c_bits_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] source_c_bits_a_mask_lo_lo = {source_c_bits_a_mask_acc_1, source_c_bits_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] source_c_bits_a_mask_lo_hi = {source_c_bits_a_mask_acc_3, source_c_bits_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] source_c_bits_a_mask_lo = {source_c_bits_a_mask_lo_hi, source_c_bits_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] source_c_bits_a_mask_hi_lo = {source_c_bits_a_mask_acc_5, source_c_bits_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] source_c_bits_a_mask_hi_hi = {source_c_bits_a_mask_acc_7, source_c_bits_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] source_c_bits_a_mask_hi = {source_c_bits_a_mask_hi_hi, source_c_bits_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _source_c_bits_a_mask_T = {source_c_bits_a_mask_hi, source_c_bits_a_mask_lo}; // @[Misc.scala:222:10]
assign source_c_bits_a_mask = _source_c_bits_a_mask_T; // @[Misc.scala:222:10]
wire [26:0] _decode_T = 27'hFFF << nodeIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] _decode_T_1 = _decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _decode_T_2 = ~_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] decode = _decode_T_2[11:3]; // @[package.scala:243:46]
wire _opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire opdata = ~_opdata_T; // @[Edges.scala:92:{28,37}]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & nodeOut_a_ready; // @[Arbiter.scala:61:28, :62:24]
wire [1:0] _readys_T = {source_i_valid, source_c_valid}; // @[AtomicAutomata.scala:154:28, :165:28]
wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_T_2 = _readys_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_T_3 = _readys_T | _readys_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_T_4 = _readys_T_3; // @[package.scala:253:43, :254:17]
wire [2:0] _readys_T_5 = {_readys_T_4, 1'h0}; // @[package.scala:254:17]
wire [1:0] _readys_T_6 = _readys_T_5[1:0]; // @[Arbiter.scala:16:{78,83}]
wire [1:0] _readys_T_7 = ~_readys_T_6; // @[Arbiter.scala:16:{61,83}]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:16:61, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:16:61, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & source_c_valid; // @[AtomicAutomata.scala:165:28]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & source_i_valid; // @[AtomicAutomata.scala:154:28]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _nodeOut_a_valid_T = source_c_valid | source_i_valid; // @[AtomicAutomata.scala:154:28, :165:28] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_81 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_98
connect io_out_source_valid_1.clock, clock
connect io_out_source_valid_1.reset, reset
connect io_out_source_valid_1.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_1.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_81( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_98 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_33 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 4, 0)
node _source_ok_T = shr(io.in.a.bits.source, 5)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<5>(0h13))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits = bits(_uncommonBits_T, 4, 0)
node _T_4 = shr(io.in.a.bits.source, 5)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<5>(0h13))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 4, 0)
node _T_24 = shr(io.in.a.bits.source, 5)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<5>(0h13))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 4, 0)
node _T_86 = shr(io.in.a.bits.source, 5)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<5>(0h13))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 4, 0)
node _T_152 = shr(io.in.a.bits.source, 5)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<5>(0h13))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0)
node _T_199 = shr(io.in.a.bits.source, 5)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<5>(0h13))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0)
node _T_240 = shr(io.in.a.bits.source, 5)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<5>(0h13))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<17>(0h10000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_283 = shr(io.in.a.bits.source, 5)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<5>(0h13))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<17>(0h10000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_321 = shr(io.in.a.bits.source, 5)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<5>(0h13))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_359 = shr(io.in.a.bits.source, 5)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<5>(0h13))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<17>(0h10000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 4, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 5)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<5>(0h13))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_opcodes : UInt<80>, clock, reset, UInt<80>(0h0)
regreset inflight_sizes : UInt<80>, clock, reset, UInt<80>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<20>
connect a_set, UInt<20>(0h0)
wire a_set_wo_ready : UInt<20>
connect a_set_wo_ready, UInt<20>(0h0)
wire a_opcodes_set : UInt<80>
connect a_opcodes_set, UInt<80>(0h0)
wire a_sizes_set : UInt<80>
connect a_sizes_set, UInt<80>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<20>
connect d_clr, UInt<20>(0h0)
wire d_clr_wo_ready : UInt<20>
connect d_clr_wo_ready, UInt<20>(0h0)
wire d_opcodes_clr : UInt<80>
connect d_opcodes_clr, UInt<80>(0h0)
wire d_sizes_clr : UInt<80>
connect d_sizes_clr, UInt<80>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_66
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<20>, clock, reset, UInt<20>(0h0)
regreset inflight_opcodes_1 : UInt<80>, clock, reset, UInt<80>(0h0)
regreset inflight_sizes_1 : UInt<80>, clock, reset, UInt<80>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<5>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<20>
connect c_set, UInt<20>(0h0)
wire c_set_wo_ready : UInt<20>
connect c_set_wo_ready, UInt<20>(0h0)
wire c_opcodes_set : UInt<80>
connect c_opcodes_set, UInt<80>(0h0)
wire c_sizes_set : UInt<80>
connect c_sizes_set, UInt<80>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<20>
connect d_clr_1, UInt<20>(0h0)
wire d_clr_wo_ready_1 : UInt<20>
connect d_clr_wo_ready_1, UInt<20>(0h0)
wire d_opcodes_clr_1 : UInt<80>
connect d_opcodes_clr_1, UInt<80>(0h0)
wire d_sizes_clr_1 : UInt<80>
connect d_sizes_clr_1, UInt<80>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<5>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<5>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<5>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<5>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_67
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/MemoryBus.scala:52:50)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_33( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34]
wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34]
wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34]
wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [19:0] inflight; // @[Monitor.scala:614:27]
reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [79:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [19:0] a_set; // @[Monitor.scala:626:34]
wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [79:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [19:0] d_clr; // @[Monitor.scala:664:34]
wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [19:0] inflight_1; // @[Monitor.scala:726:35]
wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [19:0] d_clr_1; // @[Monitor.scala:774:34]
wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_124 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_141
connect io_out_sink_valid_0.clock, clock
connect io_out_sink_valid_0.reset, reset
connect io_out_sink_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_124( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_141 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Switch_8 :
input clock : Clock
input reset : Reset
output io : { in : { flip `3` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], flip `2` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], flip `1` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], flip `0` : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1]}, out : { `3` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], `2` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], `1` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], `0` : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1]}, sel : { `3` : { flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `2` : { flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `1` : { flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1], `0` : { flip `3` : UInt<1>[1], flip `2` : UInt<1>[1], flip `1` : UInt<1>[1], flip `0` : UInt<1>[1]}[1]}}
wire in_flat : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[4]
connect in_flat[0], io.in.`0`[0]
connect in_flat[1], io.in.`1`[0]
connect in_flat[2], io.in.`2`[0]
connect in_flat[3], io.in.`3`[0]
node sel_flat_lo = cat(io.sel.`0`[0].`1`[0], io.sel.`0`[0].`0`[0])
node sel_flat_hi = cat(io.sel.`0`[0].`3`[0], io.sel.`0`[0].`2`[0])
node sel_flat = cat(sel_flat_hi, sel_flat_lo)
node _T = bits(sel_flat, 0, 0)
node _T_1 = bits(sel_flat, 1, 1)
node _T_2 = bits(sel_flat, 2, 2)
node _T_3 = bits(sel_flat, 3, 3)
node _T_4 = add(_T, _T_1)
node _T_5 = bits(_T_4, 1, 0)
node _T_6 = add(_T_2, _T_3)
node _T_7 = bits(_T_6, 1, 0)
node _T_8 = add(_T_5, _T_7)
node _T_9 = bits(_T_8, 2, 0)
node _T_10 = leq(_T_9, UInt<1>(0h1))
node _T_11 = asUInt(reset)
node _T_12 = eq(_T_11, UInt<1>(0h0))
when _T_12 :
node _T_13 = eq(_T_10, UInt<1>(0h0))
when _T_13 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf
assert(clock, _T_10, UInt<1>(0h1), "") : assert
node _io_out_0_0_valid_T = bits(sel_flat, 0, 0)
node _io_out_0_0_valid_T_1 = bits(sel_flat, 1, 1)
node _io_out_0_0_valid_T_2 = bits(sel_flat, 2, 2)
node _io_out_0_0_valid_T_3 = bits(sel_flat, 3, 3)
node _io_out_0_0_valid_T_4 = mux(_io_out_0_0_valid_T, in_flat[0].valid, UInt<1>(0h0))
node _io_out_0_0_valid_T_5 = mux(_io_out_0_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0))
node _io_out_0_0_valid_T_6 = mux(_io_out_0_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0))
node _io_out_0_0_valid_T_7 = mux(_io_out_0_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0))
node _io_out_0_0_valid_T_8 = or(_io_out_0_0_valid_T_4, _io_out_0_0_valid_T_5)
node _io_out_0_0_valid_T_9 = or(_io_out_0_0_valid_T_8, _io_out_0_0_valid_T_6)
node _io_out_0_0_valid_T_10 = or(_io_out_0_0_valid_T_9, _io_out_0_0_valid_T_7)
wire _io_out_0_0_valid_WIRE : UInt<1>
connect _io_out_0_0_valid_WIRE, _io_out_0_0_valid_T_10
node _io_out_0_0_valid_T_11 = neq(sel_flat, UInt<1>(0h0))
node _io_out_0_0_valid_T_12 = and(_io_out_0_0_valid_WIRE, _io_out_0_0_valid_T_11)
connect io.out.`0`[0].valid, _io_out_0_0_valid_T_12
node _io_out_0_0_bits_T = bits(sel_flat, 0, 0)
node _io_out_0_0_bits_T_1 = bits(sel_flat, 1, 1)
node _io_out_0_0_bits_T_2 = bits(sel_flat, 2, 2)
node _io_out_0_0_bits_T_3 = bits(sel_flat, 3, 3)
wire _io_out_0_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}
node _io_out_0_0_bits_T_4 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_5 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_6 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_7 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_8 = or(_io_out_0_0_bits_T_4, _io_out_0_0_bits_T_5)
node _io_out_0_0_bits_T_9 = or(_io_out_0_0_bits_T_8, _io_out_0_0_bits_T_6)
node _io_out_0_0_bits_T_10 = or(_io_out_0_0_bits_T_9, _io_out_0_0_bits_T_7)
wire _io_out_0_0_bits_WIRE_1 : UInt<3>
connect _io_out_0_0_bits_WIRE_1, _io_out_0_0_bits_T_10
connect _io_out_0_0_bits_WIRE.virt_channel_id, _io_out_0_0_bits_WIRE_1
wire _io_out_0_0_bits_WIRE_2 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_out_0_0_bits_T_11 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_12 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_13 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_14 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_15 = or(_io_out_0_0_bits_T_11, _io_out_0_0_bits_T_12)
node _io_out_0_0_bits_T_16 = or(_io_out_0_0_bits_T_15, _io_out_0_0_bits_T_13)
node _io_out_0_0_bits_T_17 = or(_io_out_0_0_bits_T_16, _io_out_0_0_bits_T_14)
wire _io_out_0_0_bits_WIRE_3 : UInt<2>
connect _io_out_0_0_bits_WIRE_3, _io_out_0_0_bits_T_17
connect _io_out_0_0_bits_WIRE_2.egress_node_id, _io_out_0_0_bits_WIRE_3
node _io_out_0_0_bits_T_18 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_19 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_20 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_21 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_22 = or(_io_out_0_0_bits_T_18, _io_out_0_0_bits_T_19)
node _io_out_0_0_bits_T_23 = or(_io_out_0_0_bits_T_22, _io_out_0_0_bits_T_20)
node _io_out_0_0_bits_T_24 = or(_io_out_0_0_bits_T_23, _io_out_0_0_bits_T_21)
wire _io_out_0_0_bits_WIRE_4 : UInt<4>
connect _io_out_0_0_bits_WIRE_4, _io_out_0_0_bits_T_24
connect _io_out_0_0_bits_WIRE_2.egress_node, _io_out_0_0_bits_WIRE_4
node _io_out_0_0_bits_T_25 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_26 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_27 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_28 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_29 = or(_io_out_0_0_bits_T_25, _io_out_0_0_bits_T_26)
node _io_out_0_0_bits_T_30 = or(_io_out_0_0_bits_T_29, _io_out_0_0_bits_T_27)
node _io_out_0_0_bits_T_31 = or(_io_out_0_0_bits_T_30, _io_out_0_0_bits_T_28)
wire _io_out_0_0_bits_WIRE_5 : UInt<2>
connect _io_out_0_0_bits_WIRE_5, _io_out_0_0_bits_T_31
connect _io_out_0_0_bits_WIRE_2.ingress_node_id, _io_out_0_0_bits_WIRE_5
node _io_out_0_0_bits_T_32 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_33 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_34 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_35 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_0_0_bits_T_36 = or(_io_out_0_0_bits_T_32, _io_out_0_0_bits_T_33)
node _io_out_0_0_bits_T_37 = or(_io_out_0_0_bits_T_36, _io_out_0_0_bits_T_34)
node _io_out_0_0_bits_T_38 = or(_io_out_0_0_bits_T_37, _io_out_0_0_bits_T_35)
wire _io_out_0_0_bits_WIRE_6 : UInt<4>
connect _io_out_0_0_bits_WIRE_6, _io_out_0_0_bits_T_38
connect _io_out_0_0_bits_WIRE_2.ingress_node, _io_out_0_0_bits_WIRE_6
node _io_out_0_0_bits_T_39 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_40 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_41 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_42 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_0_0_bits_T_43 = or(_io_out_0_0_bits_T_39, _io_out_0_0_bits_T_40)
node _io_out_0_0_bits_T_44 = or(_io_out_0_0_bits_T_43, _io_out_0_0_bits_T_41)
node _io_out_0_0_bits_T_45 = or(_io_out_0_0_bits_T_44, _io_out_0_0_bits_T_42)
wire _io_out_0_0_bits_WIRE_7 : UInt<2>
connect _io_out_0_0_bits_WIRE_7, _io_out_0_0_bits_T_45
connect _io_out_0_0_bits_WIRE_2.vnet_id, _io_out_0_0_bits_WIRE_7
connect _io_out_0_0_bits_WIRE.flow, _io_out_0_0_bits_WIRE_2
node _io_out_0_0_bits_T_46 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0))
node _io_out_0_0_bits_T_47 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0))
node _io_out_0_0_bits_T_48 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0))
node _io_out_0_0_bits_T_49 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0))
node _io_out_0_0_bits_T_50 = or(_io_out_0_0_bits_T_46, _io_out_0_0_bits_T_47)
node _io_out_0_0_bits_T_51 = or(_io_out_0_0_bits_T_50, _io_out_0_0_bits_T_48)
node _io_out_0_0_bits_T_52 = or(_io_out_0_0_bits_T_51, _io_out_0_0_bits_T_49)
wire _io_out_0_0_bits_WIRE_8 : UInt<73>
connect _io_out_0_0_bits_WIRE_8, _io_out_0_0_bits_T_52
connect _io_out_0_0_bits_WIRE.payload, _io_out_0_0_bits_WIRE_8
node _io_out_0_0_bits_T_53 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0))
node _io_out_0_0_bits_T_54 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0))
node _io_out_0_0_bits_T_55 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0))
node _io_out_0_0_bits_T_56 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0))
node _io_out_0_0_bits_T_57 = or(_io_out_0_0_bits_T_53, _io_out_0_0_bits_T_54)
node _io_out_0_0_bits_T_58 = or(_io_out_0_0_bits_T_57, _io_out_0_0_bits_T_55)
node _io_out_0_0_bits_T_59 = or(_io_out_0_0_bits_T_58, _io_out_0_0_bits_T_56)
wire _io_out_0_0_bits_WIRE_9 : UInt<1>
connect _io_out_0_0_bits_WIRE_9, _io_out_0_0_bits_T_59
connect _io_out_0_0_bits_WIRE.tail, _io_out_0_0_bits_WIRE_9
node _io_out_0_0_bits_T_60 = mux(_io_out_0_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0))
node _io_out_0_0_bits_T_61 = mux(_io_out_0_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0))
node _io_out_0_0_bits_T_62 = mux(_io_out_0_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0))
node _io_out_0_0_bits_T_63 = mux(_io_out_0_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0))
node _io_out_0_0_bits_T_64 = or(_io_out_0_0_bits_T_60, _io_out_0_0_bits_T_61)
node _io_out_0_0_bits_T_65 = or(_io_out_0_0_bits_T_64, _io_out_0_0_bits_T_62)
node _io_out_0_0_bits_T_66 = or(_io_out_0_0_bits_T_65, _io_out_0_0_bits_T_63)
wire _io_out_0_0_bits_WIRE_10 : UInt<1>
connect _io_out_0_0_bits_WIRE_10, _io_out_0_0_bits_T_66
connect _io_out_0_0_bits_WIRE.head, _io_out_0_0_bits_WIRE_10
connect io.out.`0`[0].bits, _io_out_0_0_bits_WIRE
node _io_out_0_0_bits_virt_channel_id_T = bits(sel_flat, 0, 0)
node _io_out_0_0_bits_virt_channel_id_T_1 = bits(sel_flat, 1, 1)
node _io_out_0_0_bits_virt_channel_id_T_2 = bits(sel_flat, 2, 2)
node _io_out_0_0_bits_virt_channel_id_T_3 = bits(sel_flat, 3, 3)
node _io_out_0_0_bits_virt_channel_id_T_4 = mux(_io_out_0_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_0_0_bits_virt_channel_id_T_5 = mux(_io_out_0_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_0_0_bits_virt_channel_id_T_6 = mux(_io_out_0_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_0_0_bits_virt_channel_id_T_7 = mux(_io_out_0_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_0_0_bits_virt_channel_id_T_8 = or(_io_out_0_0_bits_virt_channel_id_T_4, _io_out_0_0_bits_virt_channel_id_T_5)
node _io_out_0_0_bits_virt_channel_id_T_9 = or(_io_out_0_0_bits_virt_channel_id_T_8, _io_out_0_0_bits_virt_channel_id_T_6)
node _io_out_0_0_bits_virt_channel_id_T_10 = or(_io_out_0_0_bits_virt_channel_id_T_9, _io_out_0_0_bits_virt_channel_id_T_7)
wire _io_out_0_0_bits_virt_channel_id_WIRE : UInt<3>
connect _io_out_0_0_bits_virt_channel_id_WIRE, _io_out_0_0_bits_virt_channel_id_T_10
connect io.out.`0`[0].bits.virt_channel_id, _io_out_0_0_bits_virt_channel_id_WIRE
node sel_flat_lo_1 = cat(io.sel.`1`[0].`1`[0], io.sel.`1`[0].`0`[0])
node sel_flat_hi_1 = cat(io.sel.`1`[0].`3`[0], io.sel.`1`[0].`2`[0])
node sel_flat_1 = cat(sel_flat_hi_1, sel_flat_lo_1)
node _T_14 = bits(sel_flat_1, 0, 0)
node _T_15 = bits(sel_flat_1, 1, 1)
node _T_16 = bits(sel_flat_1, 2, 2)
node _T_17 = bits(sel_flat_1, 3, 3)
node _T_18 = add(_T_14, _T_15)
node _T_19 = bits(_T_18, 1, 0)
node _T_20 = add(_T_16, _T_17)
node _T_21 = bits(_T_20, 1, 0)
node _T_22 = add(_T_19, _T_21)
node _T_23 = bits(_T_22, 2, 0)
node _T_24 = leq(_T_23, UInt<1>(0h1))
node _T_25 = asUInt(reset)
node _T_26 = eq(_T_25, UInt<1>(0h0))
when _T_26 :
node _T_27 = eq(_T_24, UInt<1>(0h0))
when _T_27 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_1
assert(clock, _T_24, UInt<1>(0h1), "") : assert_1
node _io_out_1_0_valid_T = bits(sel_flat_1, 0, 0)
node _io_out_1_0_valid_T_1 = bits(sel_flat_1, 1, 1)
node _io_out_1_0_valid_T_2 = bits(sel_flat_1, 2, 2)
node _io_out_1_0_valid_T_3 = bits(sel_flat_1, 3, 3)
node _io_out_1_0_valid_T_4 = mux(_io_out_1_0_valid_T, in_flat[0].valid, UInt<1>(0h0))
node _io_out_1_0_valid_T_5 = mux(_io_out_1_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0))
node _io_out_1_0_valid_T_6 = mux(_io_out_1_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0))
node _io_out_1_0_valid_T_7 = mux(_io_out_1_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0))
node _io_out_1_0_valid_T_8 = or(_io_out_1_0_valid_T_4, _io_out_1_0_valid_T_5)
node _io_out_1_0_valid_T_9 = or(_io_out_1_0_valid_T_8, _io_out_1_0_valid_T_6)
node _io_out_1_0_valid_T_10 = or(_io_out_1_0_valid_T_9, _io_out_1_0_valid_T_7)
wire _io_out_1_0_valid_WIRE : UInt<1>
connect _io_out_1_0_valid_WIRE, _io_out_1_0_valid_T_10
node _io_out_1_0_valid_T_11 = neq(sel_flat_1, UInt<1>(0h0))
node _io_out_1_0_valid_T_12 = and(_io_out_1_0_valid_WIRE, _io_out_1_0_valid_T_11)
connect io.out.`1`[0].valid, _io_out_1_0_valid_T_12
node _io_out_1_0_bits_T = bits(sel_flat_1, 0, 0)
node _io_out_1_0_bits_T_1 = bits(sel_flat_1, 1, 1)
node _io_out_1_0_bits_T_2 = bits(sel_flat_1, 2, 2)
node _io_out_1_0_bits_T_3 = bits(sel_flat_1, 3, 3)
wire _io_out_1_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}
node _io_out_1_0_bits_T_4 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_5 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_6 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_7 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_8 = or(_io_out_1_0_bits_T_4, _io_out_1_0_bits_T_5)
node _io_out_1_0_bits_T_9 = or(_io_out_1_0_bits_T_8, _io_out_1_0_bits_T_6)
node _io_out_1_0_bits_T_10 = or(_io_out_1_0_bits_T_9, _io_out_1_0_bits_T_7)
wire _io_out_1_0_bits_WIRE_1 : UInt<3>
connect _io_out_1_0_bits_WIRE_1, _io_out_1_0_bits_T_10
connect _io_out_1_0_bits_WIRE.virt_channel_id, _io_out_1_0_bits_WIRE_1
wire _io_out_1_0_bits_WIRE_2 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_out_1_0_bits_T_11 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_12 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_13 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_14 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_15 = or(_io_out_1_0_bits_T_11, _io_out_1_0_bits_T_12)
node _io_out_1_0_bits_T_16 = or(_io_out_1_0_bits_T_15, _io_out_1_0_bits_T_13)
node _io_out_1_0_bits_T_17 = or(_io_out_1_0_bits_T_16, _io_out_1_0_bits_T_14)
wire _io_out_1_0_bits_WIRE_3 : UInt<2>
connect _io_out_1_0_bits_WIRE_3, _io_out_1_0_bits_T_17
connect _io_out_1_0_bits_WIRE_2.egress_node_id, _io_out_1_0_bits_WIRE_3
node _io_out_1_0_bits_T_18 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_19 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_20 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_21 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_22 = or(_io_out_1_0_bits_T_18, _io_out_1_0_bits_T_19)
node _io_out_1_0_bits_T_23 = or(_io_out_1_0_bits_T_22, _io_out_1_0_bits_T_20)
node _io_out_1_0_bits_T_24 = or(_io_out_1_0_bits_T_23, _io_out_1_0_bits_T_21)
wire _io_out_1_0_bits_WIRE_4 : UInt<4>
connect _io_out_1_0_bits_WIRE_4, _io_out_1_0_bits_T_24
connect _io_out_1_0_bits_WIRE_2.egress_node, _io_out_1_0_bits_WIRE_4
node _io_out_1_0_bits_T_25 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_26 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_27 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_28 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_29 = or(_io_out_1_0_bits_T_25, _io_out_1_0_bits_T_26)
node _io_out_1_0_bits_T_30 = or(_io_out_1_0_bits_T_29, _io_out_1_0_bits_T_27)
node _io_out_1_0_bits_T_31 = or(_io_out_1_0_bits_T_30, _io_out_1_0_bits_T_28)
wire _io_out_1_0_bits_WIRE_5 : UInt<2>
connect _io_out_1_0_bits_WIRE_5, _io_out_1_0_bits_T_31
connect _io_out_1_0_bits_WIRE_2.ingress_node_id, _io_out_1_0_bits_WIRE_5
node _io_out_1_0_bits_T_32 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_33 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_34 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_35 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_1_0_bits_T_36 = or(_io_out_1_0_bits_T_32, _io_out_1_0_bits_T_33)
node _io_out_1_0_bits_T_37 = or(_io_out_1_0_bits_T_36, _io_out_1_0_bits_T_34)
node _io_out_1_0_bits_T_38 = or(_io_out_1_0_bits_T_37, _io_out_1_0_bits_T_35)
wire _io_out_1_0_bits_WIRE_6 : UInt<4>
connect _io_out_1_0_bits_WIRE_6, _io_out_1_0_bits_T_38
connect _io_out_1_0_bits_WIRE_2.ingress_node, _io_out_1_0_bits_WIRE_6
node _io_out_1_0_bits_T_39 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_40 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_41 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_42 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_1_0_bits_T_43 = or(_io_out_1_0_bits_T_39, _io_out_1_0_bits_T_40)
node _io_out_1_0_bits_T_44 = or(_io_out_1_0_bits_T_43, _io_out_1_0_bits_T_41)
node _io_out_1_0_bits_T_45 = or(_io_out_1_0_bits_T_44, _io_out_1_0_bits_T_42)
wire _io_out_1_0_bits_WIRE_7 : UInt<2>
connect _io_out_1_0_bits_WIRE_7, _io_out_1_0_bits_T_45
connect _io_out_1_0_bits_WIRE_2.vnet_id, _io_out_1_0_bits_WIRE_7
connect _io_out_1_0_bits_WIRE.flow, _io_out_1_0_bits_WIRE_2
node _io_out_1_0_bits_T_46 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0))
node _io_out_1_0_bits_T_47 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0))
node _io_out_1_0_bits_T_48 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0))
node _io_out_1_0_bits_T_49 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0))
node _io_out_1_0_bits_T_50 = or(_io_out_1_0_bits_T_46, _io_out_1_0_bits_T_47)
node _io_out_1_0_bits_T_51 = or(_io_out_1_0_bits_T_50, _io_out_1_0_bits_T_48)
node _io_out_1_0_bits_T_52 = or(_io_out_1_0_bits_T_51, _io_out_1_0_bits_T_49)
wire _io_out_1_0_bits_WIRE_8 : UInt<73>
connect _io_out_1_0_bits_WIRE_8, _io_out_1_0_bits_T_52
connect _io_out_1_0_bits_WIRE.payload, _io_out_1_0_bits_WIRE_8
node _io_out_1_0_bits_T_53 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0))
node _io_out_1_0_bits_T_54 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0))
node _io_out_1_0_bits_T_55 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0))
node _io_out_1_0_bits_T_56 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0))
node _io_out_1_0_bits_T_57 = or(_io_out_1_0_bits_T_53, _io_out_1_0_bits_T_54)
node _io_out_1_0_bits_T_58 = or(_io_out_1_0_bits_T_57, _io_out_1_0_bits_T_55)
node _io_out_1_0_bits_T_59 = or(_io_out_1_0_bits_T_58, _io_out_1_0_bits_T_56)
wire _io_out_1_0_bits_WIRE_9 : UInt<1>
connect _io_out_1_0_bits_WIRE_9, _io_out_1_0_bits_T_59
connect _io_out_1_0_bits_WIRE.tail, _io_out_1_0_bits_WIRE_9
node _io_out_1_0_bits_T_60 = mux(_io_out_1_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0))
node _io_out_1_0_bits_T_61 = mux(_io_out_1_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0))
node _io_out_1_0_bits_T_62 = mux(_io_out_1_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0))
node _io_out_1_0_bits_T_63 = mux(_io_out_1_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0))
node _io_out_1_0_bits_T_64 = or(_io_out_1_0_bits_T_60, _io_out_1_0_bits_T_61)
node _io_out_1_0_bits_T_65 = or(_io_out_1_0_bits_T_64, _io_out_1_0_bits_T_62)
node _io_out_1_0_bits_T_66 = or(_io_out_1_0_bits_T_65, _io_out_1_0_bits_T_63)
wire _io_out_1_0_bits_WIRE_10 : UInt<1>
connect _io_out_1_0_bits_WIRE_10, _io_out_1_0_bits_T_66
connect _io_out_1_0_bits_WIRE.head, _io_out_1_0_bits_WIRE_10
connect io.out.`1`[0].bits, _io_out_1_0_bits_WIRE
node _io_out_1_0_bits_virt_channel_id_T = bits(sel_flat_1, 0, 0)
node _io_out_1_0_bits_virt_channel_id_T_1 = bits(sel_flat_1, 1, 1)
node _io_out_1_0_bits_virt_channel_id_T_2 = bits(sel_flat_1, 2, 2)
node _io_out_1_0_bits_virt_channel_id_T_3 = bits(sel_flat_1, 3, 3)
node _io_out_1_0_bits_virt_channel_id_T_4 = mux(_io_out_1_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_1_0_bits_virt_channel_id_T_5 = mux(_io_out_1_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_1_0_bits_virt_channel_id_T_6 = mux(_io_out_1_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_1_0_bits_virt_channel_id_T_7 = mux(_io_out_1_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_1_0_bits_virt_channel_id_T_8 = or(_io_out_1_0_bits_virt_channel_id_T_4, _io_out_1_0_bits_virt_channel_id_T_5)
node _io_out_1_0_bits_virt_channel_id_T_9 = or(_io_out_1_0_bits_virt_channel_id_T_8, _io_out_1_0_bits_virt_channel_id_T_6)
node _io_out_1_0_bits_virt_channel_id_T_10 = or(_io_out_1_0_bits_virt_channel_id_T_9, _io_out_1_0_bits_virt_channel_id_T_7)
wire _io_out_1_0_bits_virt_channel_id_WIRE : UInt<3>
connect _io_out_1_0_bits_virt_channel_id_WIRE, _io_out_1_0_bits_virt_channel_id_T_10
connect io.out.`1`[0].bits.virt_channel_id, _io_out_1_0_bits_virt_channel_id_WIRE
node sel_flat_lo_2 = cat(io.sel.`2`[0].`1`[0], io.sel.`2`[0].`0`[0])
node sel_flat_hi_2 = cat(io.sel.`2`[0].`3`[0], io.sel.`2`[0].`2`[0])
node sel_flat_2 = cat(sel_flat_hi_2, sel_flat_lo_2)
node _T_28 = bits(sel_flat_2, 0, 0)
node _T_29 = bits(sel_flat_2, 1, 1)
node _T_30 = bits(sel_flat_2, 2, 2)
node _T_31 = bits(sel_flat_2, 3, 3)
node _T_32 = add(_T_28, _T_29)
node _T_33 = bits(_T_32, 1, 0)
node _T_34 = add(_T_30, _T_31)
node _T_35 = bits(_T_34, 1, 0)
node _T_36 = add(_T_33, _T_35)
node _T_37 = bits(_T_36, 2, 0)
node _T_38 = leq(_T_37, UInt<1>(0h1))
node _T_39 = asUInt(reset)
node _T_40 = eq(_T_39, UInt<1>(0h0))
when _T_40 :
node _T_41 = eq(_T_38, UInt<1>(0h0))
when _T_41 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_2
assert(clock, _T_38, UInt<1>(0h1), "") : assert_2
node _io_out_2_0_valid_T = bits(sel_flat_2, 0, 0)
node _io_out_2_0_valid_T_1 = bits(sel_flat_2, 1, 1)
node _io_out_2_0_valid_T_2 = bits(sel_flat_2, 2, 2)
node _io_out_2_0_valid_T_3 = bits(sel_flat_2, 3, 3)
node _io_out_2_0_valid_T_4 = mux(_io_out_2_0_valid_T, in_flat[0].valid, UInt<1>(0h0))
node _io_out_2_0_valid_T_5 = mux(_io_out_2_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0))
node _io_out_2_0_valid_T_6 = mux(_io_out_2_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0))
node _io_out_2_0_valid_T_7 = mux(_io_out_2_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0))
node _io_out_2_0_valid_T_8 = or(_io_out_2_0_valid_T_4, _io_out_2_0_valid_T_5)
node _io_out_2_0_valid_T_9 = or(_io_out_2_0_valid_T_8, _io_out_2_0_valid_T_6)
node _io_out_2_0_valid_T_10 = or(_io_out_2_0_valid_T_9, _io_out_2_0_valid_T_7)
wire _io_out_2_0_valid_WIRE : UInt<1>
connect _io_out_2_0_valid_WIRE, _io_out_2_0_valid_T_10
node _io_out_2_0_valid_T_11 = neq(sel_flat_2, UInt<1>(0h0))
node _io_out_2_0_valid_T_12 = and(_io_out_2_0_valid_WIRE, _io_out_2_0_valid_T_11)
connect io.out.`2`[0].valid, _io_out_2_0_valid_T_12
node _io_out_2_0_bits_T = bits(sel_flat_2, 0, 0)
node _io_out_2_0_bits_T_1 = bits(sel_flat_2, 1, 1)
node _io_out_2_0_bits_T_2 = bits(sel_flat_2, 2, 2)
node _io_out_2_0_bits_T_3 = bits(sel_flat_2, 3, 3)
wire _io_out_2_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}
node _io_out_2_0_bits_T_4 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_5 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_6 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_7 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_8 = or(_io_out_2_0_bits_T_4, _io_out_2_0_bits_T_5)
node _io_out_2_0_bits_T_9 = or(_io_out_2_0_bits_T_8, _io_out_2_0_bits_T_6)
node _io_out_2_0_bits_T_10 = or(_io_out_2_0_bits_T_9, _io_out_2_0_bits_T_7)
wire _io_out_2_0_bits_WIRE_1 : UInt<3>
connect _io_out_2_0_bits_WIRE_1, _io_out_2_0_bits_T_10
connect _io_out_2_0_bits_WIRE.virt_channel_id, _io_out_2_0_bits_WIRE_1
wire _io_out_2_0_bits_WIRE_2 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_out_2_0_bits_T_11 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_12 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_13 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_14 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_15 = or(_io_out_2_0_bits_T_11, _io_out_2_0_bits_T_12)
node _io_out_2_0_bits_T_16 = or(_io_out_2_0_bits_T_15, _io_out_2_0_bits_T_13)
node _io_out_2_0_bits_T_17 = or(_io_out_2_0_bits_T_16, _io_out_2_0_bits_T_14)
wire _io_out_2_0_bits_WIRE_3 : UInt<2>
connect _io_out_2_0_bits_WIRE_3, _io_out_2_0_bits_T_17
connect _io_out_2_0_bits_WIRE_2.egress_node_id, _io_out_2_0_bits_WIRE_3
node _io_out_2_0_bits_T_18 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_19 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_20 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_21 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_22 = or(_io_out_2_0_bits_T_18, _io_out_2_0_bits_T_19)
node _io_out_2_0_bits_T_23 = or(_io_out_2_0_bits_T_22, _io_out_2_0_bits_T_20)
node _io_out_2_0_bits_T_24 = or(_io_out_2_0_bits_T_23, _io_out_2_0_bits_T_21)
wire _io_out_2_0_bits_WIRE_4 : UInt<4>
connect _io_out_2_0_bits_WIRE_4, _io_out_2_0_bits_T_24
connect _io_out_2_0_bits_WIRE_2.egress_node, _io_out_2_0_bits_WIRE_4
node _io_out_2_0_bits_T_25 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_26 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_27 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_28 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_29 = or(_io_out_2_0_bits_T_25, _io_out_2_0_bits_T_26)
node _io_out_2_0_bits_T_30 = or(_io_out_2_0_bits_T_29, _io_out_2_0_bits_T_27)
node _io_out_2_0_bits_T_31 = or(_io_out_2_0_bits_T_30, _io_out_2_0_bits_T_28)
wire _io_out_2_0_bits_WIRE_5 : UInt<2>
connect _io_out_2_0_bits_WIRE_5, _io_out_2_0_bits_T_31
connect _io_out_2_0_bits_WIRE_2.ingress_node_id, _io_out_2_0_bits_WIRE_5
node _io_out_2_0_bits_T_32 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_33 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_34 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_35 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_2_0_bits_T_36 = or(_io_out_2_0_bits_T_32, _io_out_2_0_bits_T_33)
node _io_out_2_0_bits_T_37 = or(_io_out_2_0_bits_T_36, _io_out_2_0_bits_T_34)
node _io_out_2_0_bits_T_38 = or(_io_out_2_0_bits_T_37, _io_out_2_0_bits_T_35)
wire _io_out_2_0_bits_WIRE_6 : UInt<4>
connect _io_out_2_0_bits_WIRE_6, _io_out_2_0_bits_T_38
connect _io_out_2_0_bits_WIRE_2.ingress_node, _io_out_2_0_bits_WIRE_6
node _io_out_2_0_bits_T_39 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_40 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_41 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_42 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_2_0_bits_T_43 = or(_io_out_2_0_bits_T_39, _io_out_2_0_bits_T_40)
node _io_out_2_0_bits_T_44 = or(_io_out_2_0_bits_T_43, _io_out_2_0_bits_T_41)
node _io_out_2_0_bits_T_45 = or(_io_out_2_0_bits_T_44, _io_out_2_0_bits_T_42)
wire _io_out_2_0_bits_WIRE_7 : UInt<2>
connect _io_out_2_0_bits_WIRE_7, _io_out_2_0_bits_T_45
connect _io_out_2_0_bits_WIRE_2.vnet_id, _io_out_2_0_bits_WIRE_7
connect _io_out_2_0_bits_WIRE.flow, _io_out_2_0_bits_WIRE_2
node _io_out_2_0_bits_T_46 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0))
node _io_out_2_0_bits_T_47 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0))
node _io_out_2_0_bits_T_48 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0))
node _io_out_2_0_bits_T_49 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0))
node _io_out_2_0_bits_T_50 = or(_io_out_2_0_bits_T_46, _io_out_2_0_bits_T_47)
node _io_out_2_0_bits_T_51 = or(_io_out_2_0_bits_T_50, _io_out_2_0_bits_T_48)
node _io_out_2_0_bits_T_52 = or(_io_out_2_0_bits_T_51, _io_out_2_0_bits_T_49)
wire _io_out_2_0_bits_WIRE_8 : UInt<73>
connect _io_out_2_0_bits_WIRE_8, _io_out_2_0_bits_T_52
connect _io_out_2_0_bits_WIRE.payload, _io_out_2_0_bits_WIRE_8
node _io_out_2_0_bits_T_53 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0))
node _io_out_2_0_bits_T_54 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0))
node _io_out_2_0_bits_T_55 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0))
node _io_out_2_0_bits_T_56 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0))
node _io_out_2_0_bits_T_57 = or(_io_out_2_0_bits_T_53, _io_out_2_0_bits_T_54)
node _io_out_2_0_bits_T_58 = or(_io_out_2_0_bits_T_57, _io_out_2_0_bits_T_55)
node _io_out_2_0_bits_T_59 = or(_io_out_2_0_bits_T_58, _io_out_2_0_bits_T_56)
wire _io_out_2_0_bits_WIRE_9 : UInt<1>
connect _io_out_2_0_bits_WIRE_9, _io_out_2_0_bits_T_59
connect _io_out_2_0_bits_WIRE.tail, _io_out_2_0_bits_WIRE_9
node _io_out_2_0_bits_T_60 = mux(_io_out_2_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0))
node _io_out_2_0_bits_T_61 = mux(_io_out_2_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0))
node _io_out_2_0_bits_T_62 = mux(_io_out_2_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0))
node _io_out_2_0_bits_T_63 = mux(_io_out_2_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0))
node _io_out_2_0_bits_T_64 = or(_io_out_2_0_bits_T_60, _io_out_2_0_bits_T_61)
node _io_out_2_0_bits_T_65 = or(_io_out_2_0_bits_T_64, _io_out_2_0_bits_T_62)
node _io_out_2_0_bits_T_66 = or(_io_out_2_0_bits_T_65, _io_out_2_0_bits_T_63)
wire _io_out_2_0_bits_WIRE_10 : UInt<1>
connect _io_out_2_0_bits_WIRE_10, _io_out_2_0_bits_T_66
connect _io_out_2_0_bits_WIRE.head, _io_out_2_0_bits_WIRE_10
connect io.out.`2`[0].bits, _io_out_2_0_bits_WIRE
node _io_out_2_0_bits_virt_channel_id_T = bits(sel_flat_2, 0, 0)
node _io_out_2_0_bits_virt_channel_id_T_1 = bits(sel_flat_2, 1, 1)
node _io_out_2_0_bits_virt_channel_id_T_2 = bits(sel_flat_2, 2, 2)
node _io_out_2_0_bits_virt_channel_id_T_3 = bits(sel_flat_2, 3, 3)
node _io_out_2_0_bits_virt_channel_id_T_4 = mux(_io_out_2_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_2_0_bits_virt_channel_id_T_5 = mux(_io_out_2_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_2_0_bits_virt_channel_id_T_6 = mux(_io_out_2_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_2_0_bits_virt_channel_id_T_7 = mux(_io_out_2_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_2_0_bits_virt_channel_id_T_8 = or(_io_out_2_0_bits_virt_channel_id_T_4, _io_out_2_0_bits_virt_channel_id_T_5)
node _io_out_2_0_bits_virt_channel_id_T_9 = or(_io_out_2_0_bits_virt_channel_id_T_8, _io_out_2_0_bits_virt_channel_id_T_6)
node _io_out_2_0_bits_virt_channel_id_T_10 = or(_io_out_2_0_bits_virt_channel_id_T_9, _io_out_2_0_bits_virt_channel_id_T_7)
wire _io_out_2_0_bits_virt_channel_id_WIRE : UInt<3>
connect _io_out_2_0_bits_virt_channel_id_WIRE, _io_out_2_0_bits_virt_channel_id_T_10
connect io.out.`2`[0].bits.virt_channel_id, _io_out_2_0_bits_virt_channel_id_WIRE
node sel_flat_lo_3 = cat(io.sel.`3`[0].`1`[0], io.sel.`3`[0].`0`[0])
node sel_flat_hi_3 = cat(io.sel.`3`[0].`3`[0], io.sel.`3`[0].`2`[0])
node sel_flat_3 = cat(sel_flat_hi_3, sel_flat_lo_3)
node _T_42 = bits(sel_flat_3, 0, 0)
node _T_43 = bits(sel_flat_3, 1, 1)
node _T_44 = bits(sel_flat_3, 2, 2)
node _T_45 = bits(sel_flat_3, 3, 3)
node _T_46 = add(_T_42, _T_43)
node _T_47 = bits(_T_46, 1, 0)
node _T_48 = add(_T_44, _T_45)
node _T_49 = bits(_T_48, 1, 0)
node _T_50 = add(_T_47, _T_49)
node _T_51 = bits(_T_50, 2, 0)
node _T_52 = leq(_T_51, UInt<1>(0h1))
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Switch.scala:47 assert(PopCount(sel_flat) <= 1.U)\n") : printf_3
assert(clock, _T_52, UInt<1>(0h1), "") : assert_3
node _io_out_3_0_valid_T = bits(sel_flat_3, 0, 0)
node _io_out_3_0_valid_T_1 = bits(sel_flat_3, 1, 1)
node _io_out_3_0_valid_T_2 = bits(sel_flat_3, 2, 2)
node _io_out_3_0_valid_T_3 = bits(sel_flat_3, 3, 3)
node _io_out_3_0_valid_T_4 = mux(_io_out_3_0_valid_T, in_flat[0].valid, UInt<1>(0h0))
node _io_out_3_0_valid_T_5 = mux(_io_out_3_0_valid_T_1, in_flat[1].valid, UInt<1>(0h0))
node _io_out_3_0_valid_T_6 = mux(_io_out_3_0_valid_T_2, in_flat[2].valid, UInt<1>(0h0))
node _io_out_3_0_valid_T_7 = mux(_io_out_3_0_valid_T_3, in_flat[3].valid, UInt<1>(0h0))
node _io_out_3_0_valid_T_8 = or(_io_out_3_0_valid_T_4, _io_out_3_0_valid_T_5)
node _io_out_3_0_valid_T_9 = or(_io_out_3_0_valid_T_8, _io_out_3_0_valid_T_6)
node _io_out_3_0_valid_T_10 = or(_io_out_3_0_valid_T_9, _io_out_3_0_valid_T_7)
wire _io_out_3_0_valid_WIRE : UInt<1>
connect _io_out_3_0_valid_WIRE, _io_out_3_0_valid_T_10
node _io_out_3_0_valid_T_11 = neq(sel_flat_3, UInt<1>(0h0))
node _io_out_3_0_valid_T_12 = and(_io_out_3_0_valid_WIRE, _io_out_3_0_valid_T_11)
connect io.out.`3`[0].valid, _io_out_3_0_valid_T_12
node _io_out_3_0_bits_T = bits(sel_flat_3, 0, 0)
node _io_out_3_0_bits_T_1 = bits(sel_flat_3, 1, 1)
node _io_out_3_0_bits_T_2 = bits(sel_flat_3, 2, 2)
node _io_out_3_0_bits_T_3 = bits(sel_flat_3, 3, 3)
wire _io_out_3_0_bits_WIRE : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}
node _io_out_3_0_bits_T_4 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_5 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_6 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_7 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.virt_channel_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_8 = or(_io_out_3_0_bits_T_4, _io_out_3_0_bits_T_5)
node _io_out_3_0_bits_T_9 = or(_io_out_3_0_bits_T_8, _io_out_3_0_bits_T_6)
node _io_out_3_0_bits_T_10 = or(_io_out_3_0_bits_T_9, _io_out_3_0_bits_T_7)
wire _io_out_3_0_bits_WIRE_1 : UInt<3>
connect _io_out_3_0_bits_WIRE_1, _io_out_3_0_bits_T_10
connect _io_out_3_0_bits_WIRE.virt_channel_id, _io_out_3_0_bits_WIRE_1
wire _io_out_3_0_bits_WIRE_2 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_out_3_0_bits_T_11 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_12 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_13 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_14 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_15 = or(_io_out_3_0_bits_T_11, _io_out_3_0_bits_T_12)
node _io_out_3_0_bits_T_16 = or(_io_out_3_0_bits_T_15, _io_out_3_0_bits_T_13)
node _io_out_3_0_bits_T_17 = or(_io_out_3_0_bits_T_16, _io_out_3_0_bits_T_14)
wire _io_out_3_0_bits_WIRE_3 : UInt<2>
connect _io_out_3_0_bits_WIRE_3, _io_out_3_0_bits_T_17
connect _io_out_3_0_bits_WIRE_2.egress_node_id, _io_out_3_0_bits_WIRE_3
node _io_out_3_0_bits_T_18 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_19 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_20 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_21 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.egress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_22 = or(_io_out_3_0_bits_T_18, _io_out_3_0_bits_T_19)
node _io_out_3_0_bits_T_23 = or(_io_out_3_0_bits_T_22, _io_out_3_0_bits_T_20)
node _io_out_3_0_bits_T_24 = or(_io_out_3_0_bits_T_23, _io_out_3_0_bits_T_21)
wire _io_out_3_0_bits_WIRE_4 : UInt<4>
connect _io_out_3_0_bits_WIRE_4, _io_out_3_0_bits_T_24
connect _io_out_3_0_bits_WIRE_2.egress_node, _io_out_3_0_bits_WIRE_4
node _io_out_3_0_bits_T_25 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_26 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_27 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_28 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_29 = or(_io_out_3_0_bits_T_25, _io_out_3_0_bits_T_26)
node _io_out_3_0_bits_T_30 = or(_io_out_3_0_bits_T_29, _io_out_3_0_bits_T_27)
node _io_out_3_0_bits_T_31 = or(_io_out_3_0_bits_T_30, _io_out_3_0_bits_T_28)
wire _io_out_3_0_bits_WIRE_5 : UInt<2>
connect _io_out_3_0_bits_WIRE_5, _io_out_3_0_bits_T_31
connect _io_out_3_0_bits_WIRE_2.ingress_node_id, _io_out_3_0_bits_WIRE_5
node _io_out_3_0_bits_T_32 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_33 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_34 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_35 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.ingress_node, UInt<1>(0h0))
node _io_out_3_0_bits_T_36 = or(_io_out_3_0_bits_T_32, _io_out_3_0_bits_T_33)
node _io_out_3_0_bits_T_37 = or(_io_out_3_0_bits_T_36, _io_out_3_0_bits_T_34)
node _io_out_3_0_bits_T_38 = or(_io_out_3_0_bits_T_37, _io_out_3_0_bits_T_35)
wire _io_out_3_0_bits_WIRE_6 : UInt<4>
connect _io_out_3_0_bits_WIRE_6, _io_out_3_0_bits_T_38
connect _io_out_3_0_bits_WIRE_2.ingress_node, _io_out_3_0_bits_WIRE_6
node _io_out_3_0_bits_T_39 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_40 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_41 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_42 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.flow.vnet_id, UInt<1>(0h0))
node _io_out_3_0_bits_T_43 = or(_io_out_3_0_bits_T_39, _io_out_3_0_bits_T_40)
node _io_out_3_0_bits_T_44 = or(_io_out_3_0_bits_T_43, _io_out_3_0_bits_T_41)
node _io_out_3_0_bits_T_45 = or(_io_out_3_0_bits_T_44, _io_out_3_0_bits_T_42)
wire _io_out_3_0_bits_WIRE_7 : UInt<2>
connect _io_out_3_0_bits_WIRE_7, _io_out_3_0_bits_T_45
connect _io_out_3_0_bits_WIRE_2.vnet_id, _io_out_3_0_bits_WIRE_7
connect _io_out_3_0_bits_WIRE.flow, _io_out_3_0_bits_WIRE_2
node _io_out_3_0_bits_T_46 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.payload, UInt<1>(0h0))
node _io_out_3_0_bits_T_47 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.payload, UInt<1>(0h0))
node _io_out_3_0_bits_T_48 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.payload, UInt<1>(0h0))
node _io_out_3_0_bits_T_49 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.payload, UInt<1>(0h0))
node _io_out_3_0_bits_T_50 = or(_io_out_3_0_bits_T_46, _io_out_3_0_bits_T_47)
node _io_out_3_0_bits_T_51 = or(_io_out_3_0_bits_T_50, _io_out_3_0_bits_T_48)
node _io_out_3_0_bits_T_52 = or(_io_out_3_0_bits_T_51, _io_out_3_0_bits_T_49)
wire _io_out_3_0_bits_WIRE_8 : UInt<73>
connect _io_out_3_0_bits_WIRE_8, _io_out_3_0_bits_T_52
connect _io_out_3_0_bits_WIRE.payload, _io_out_3_0_bits_WIRE_8
node _io_out_3_0_bits_T_53 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.tail, UInt<1>(0h0))
node _io_out_3_0_bits_T_54 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.tail, UInt<1>(0h0))
node _io_out_3_0_bits_T_55 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.tail, UInt<1>(0h0))
node _io_out_3_0_bits_T_56 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.tail, UInt<1>(0h0))
node _io_out_3_0_bits_T_57 = or(_io_out_3_0_bits_T_53, _io_out_3_0_bits_T_54)
node _io_out_3_0_bits_T_58 = or(_io_out_3_0_bits_T_57, _io_out_3_0_bits_T_55)
node _io_out_3_0_bits_T_59 = or(_io_out_3_0_bits_T_58, _io_out_3_0_bits_T_56)
wire _io_out_3_0_bits_WIRE_9 : UInt<1>
connect _io_out_3_0_bits_WIRE_9, _io_out_3_0_bits_T_59
connect _io_out_3_0_bits_WIRE.tail, _io_out_3_0_bits_WIRE_9
node _io_out_3_0_bits_T_60 = mux(_io_out_3_0_bits_T, in_flat[0].bits.flit.head, UInt<1>(0h0))
node _io_out_3_0_bits_T_61 = mux(_io_out_3_0_bits_T_1, in_flat[1].bits.flit.head, UInt<1>(0h0))
node _io_out_3_0_bits_T_62 = mux(_io_out_3_0_bits_T_2, in_flat[2].bits.flit.head, UInt<1>(0h0))
node _io_out_3_0_bits_T_63 = mux(_io_out_3_0_bits_T_3, in_flat[3].bits.flit.head, UInt<1>(0h0))
node _io_out_3_0_bits_T_64 = or(_io_out_3_0_bits_T_60, _io_out_3_0_bits_T_61)
node _io_out_3_0_bits_T_65 = or(_io_out_3_0_bits_T_64, _io_out_3_0_bits_T_62)
node _io_out_3_0_bits_T_66 = or(_io_out_3_0_bits_T_65, _io_out_3_0_bits_T_63)
wire _io_out_3_0_bits_WIRE_10 : UInt<1>
connect _io_out_3_0_bits_WIRE_10, _io_out_3_0_bits_T_66
connect _io_out_3_0_bits_WIRE.head, _io_out_3_0_bits_WIRE_10
connect io.out.`3`[0].bits, _io_out_3_0_bits_WIRE
node _io_out_3_0_bits_virt_channel_id_T = bits(sel_flat_3, 0, 0)
node _io_out_3_0_bits_virt_channel_id_T_1 = bits(sel_flat_3, 1, 1)
node _io_out_3_0_bits_virt_channel_id_T_2 = bits(sel_flat_3, 2, 2)
node _io_out_3_0_bits_virt_channel_id_T_3 = bits(sel_flat_3, 3, 3)
node _io_out_3_0_bits_virt_channel_id_T_4 = mux(_io_out_3_0_bits_virt_channel_id_T, in_flat[0].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_3_0_bits_virt_channel_id_T_5 = mux(_io_out_3_0_bits_virt_channel_id_T_1, in_flat[1].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_3_0_bits_virt_channel_id_T_6 = mux(_io_out_3_0_bits_virt_channel_id_T_2, in_flat[2].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_3_0_bits_virt_channel_id_T_7 = mux(_io_out_3_0_bits_virt_channel_id_T_3, in_flat[3].bits.out_virt_channel, UInt<1>(0h0))
node _io_out_3_0_bits_virt_channel_id_T_8 = or(_io_out_3_0_bits_virt_channel_id_T_4, _io_out_3_0_bits_virt_channel_id_T_5)
node _io_out_3_0_bits_virt_channel_id_T_9 = or(_io_out_3_0_bits_virt_channel_id_T_8, _io_out_3_0_bits_virt_channel_id_T_6)
node _io_out_3_0_bits_virt_channel_id_T_10 = or(_io_out_3_0_bits_virt_channel_id_T_9, _io_out_3_0_bits_virt_channel_id_T_7)
wire _io_out_3_0_bits_virt_channel_id_WIRE : UInt<3>
connect _io_out_3_0_bits_virt_channel_id_WIRE, _io_out_3_0_bits_virt_channel_id_T_10
connect io.out.`3`[0].bits.virt_channel_id, _io_out_3_0_bits_virt_channel_id_WIRE | module Switch_8( // @[Switch.scala:16:7]
input clock, // @[Switch.scala:16:7]
input reset, // @[Switch.scala:16:7]
input io_in_3_0_valid, // @[Switch.scala:27:14]
input io_in_3_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_3_0_bits_flit_tail, // @[Switch.scala:27:14]
input [72:0] io_in_3_0_bits_flit_payload, // @[Switch.scala:27:14]
input [1:0] io_in_3_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [3:0] io_in_3_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input [1:0] io_in_3_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_3_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input [1:0] io_in_3_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
input [2:0] io_in_3_0_bits_out_virt_channel, // @[Switch.scala:27:14]
input io_in_1_0_valid, // @[Switch.scala:27:14]
input io_in_1_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_1_0_bits_flit_tail, // @[Switch.scala:27:14]
input [72:0] io_in_1_0_bits_flit_payload, // @[Switch.scala:27:14]
input [1:0] io_in_1_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [3:0] io_in_1_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input [1:0] io_in_1_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_1_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input [1:0] io_in_1_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
input [2:0] io_in_1_0_bits_out_virt_channel, // @[Switch.scala:27:14]
input io_in_0_0_valid, // @[Switch.scala:27:14]
input io_in_0_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_0_0_bits_flit_tail, // @[Switch.scala:27:14]
input [72:0] io_in_0_0_bits_flit_payload, // @[Switch.scala:27:14]
input [1:0] io_in_0_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [3:0] io_in_0_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input [1:0] io_in_0_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_0_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input [1:0] io_in_0_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
input [2:0] io_in_0_0_bits_out_virt_channel, // @[Switch.scala:27:14]
output io_out_3_0_valid, // @[Switch.scala:27:14]
output io_out_3_0_bits_head, // @[Switch.scala:27:14]
output io_out_3_0_bits_tail, // @[Switch.scala:27:14]
output [72:0] io_out_3_0_bits_payload, // @[Switch.scala:27:14]
output io_out_2_0_valid, // @[Switch.scala:27:14]
output io_out_2_0_bits_head, // @[Switch.scala:27:14]
output io_out_2_0_bits_tail, // @[Switch.scala:27:14]
output [72:0] io_out_2_0_bits_payload, // @[Switch.scala:27:14]
output [3:0] io_out_2_0_bits_flow_ingress_node, // @[Switch.scala:27:14]
output [1:0] io_out_2_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14]
output io_out_1_0_valid, // @[Switch.scala:27:14]
output io_out_1_0_bits_head, // @[Switch.scala:27:14]
output io_out_1_0_bits_tail, // @[Switch.scala:27:14]
output [72:0] io_out_1_0_bits_payload, // @[Switch.scala:27:14]
output [3:0] io_out_1_0_bits_flow_ingress_node, // @[Switch.scala:27:14]
output [1:0] io_out_1_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14]
output io_out_0_0_valid, // @[Switch.scala:27:14]
output io_out_0_0_bits_head, // @[Switch.scala:27:14]
output io_out_0_0_bits_tail, // @[Switch.scala:27:14]
output [72:0] io_out_0_0_bits_payload, // @[Switch.scala:27:14]
output [1:0] io_out_0_0_bits_flow_vnet_id, // @[Switch.scala:27:14]
output [3:0] io_out_0_0_bits_flow_ingress_node, // @[Switch.scala:27:14]
output [1:0] io_out_0_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14]
output [3:0] io_out_0_0_bits_flow_egress_node, // @[Switch.scala:27:14]
output [1:0] io_out_0_0_bits_flow_egress_node_id, // @[Switch.scala:27:14]
output [2:0] io_out_0_0_bits_virt_channel_id, // @[Switch.scala:27:14]
input io_sel_3_0_3_0, // @[Switch.scala:27:14]
input io_sel_3_0_1_0, // @[Switch.scala:27:14]
input io_sel_3_0_0_0, // @[Switch.scala:27:14]
input io_sel_2_0_3_0, // @[Switch.scala:27:14]
input io_sel_2_0_1_0, // @[Switch.scala:27:14]
input io_sel_2_0_0_0, // @[Switch.scala:27:14]
input io_sel_1_0_3_0, // @[Switch.scala:27:14]
input io_sel_1_0_1_0, // @[Switch.scala:27:14]
input io_sel_1_0_0_0, // @[Switch.scala:27:14]
input io_sel_0_0_3_0, // @[Switch.scala:27:14]
input io_sel_0_0_1_0, // @[Switch.scala:27:14]
input io_sel_0_0_0_0 // @[Switch.scala:27:14]
); |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_144 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_144( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module FPToFP_3 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}, flip lt : UInt<1>}
regreset in_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect in_pipe_v, io.in.valid
reg in_pipe_b : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock
when io.in.valid :
connect in_pipe_b, io.in.bits
wire in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}
connect in.valid, in_pipe_v
connect in.bits, in_pipe_b
node _signNum_T = bits(in.bits.rm, 1, 1)
node _signNum_T_1 = xor(in.bits.in1, in.bits.in2)
node _signNum_T_2 = bits(in.bits.rm, 0, 0)
node _signNum_T_3 = not(in.bits.in2)
node _signNum_T_4 = mux(_signNum_T_2, _signNum_T_3, in.bits.in2)
node signNum = mux(_signNum_T, _signNum_T_1, _signNum_T_4)
node _fsgnj_T = bits(signNum, 64, 64)
node _fsgnj_T_1 = bits(in.bits.in1, 63, 0)
node fsgnj = cat(_fsgnj_T, _fsgnj_T_1)
wire fsgnjMux : { data : UInt<65>, exc : UInt<5>}
connect fsgnjMux.exc, UInt<1>(0h0)
connect fsgnjMux.data, fsgnj
when in.bits.wflags :
node _isnan1_T = bits(in.bits.in1, 63, 61)
node isnan1 = andr(_isnan1_T)
node _isnan2_T = bits(in.bits.in2, 63, 61)
node isnan2 = andr(_isnan2_T)
node _isInvalid_T = bits(in.bits.in1, 63, 61)
node _isInvalid_T_1 = andr(_isInvalid_T)
node _isInvalid_T_2 = bits(in.bits.in1, 51, 51)
node _isInvalid_T_3 = eq(_isInvalid_T_2, UInt<1>(0h0))
node _isInvalid_T_4 = and(_isInvalid_T_1, _isInvalid_T_3)
node _isInvalid_T_5 = bits(in.bits.in2, 63, 61)
node _isInvalid_T_6 = andr(_isInvalid_T_5)
node _isInvalid_T_7 = bits(in.bits.in2, 51, 51)
node _isInvalid_T_8 = eq(_isInvalid_T_7, UInt<1>(0h0))
node _isInvalid_T_9 = and(_isInvalid_T_6, _isInvalid_T_8)
node isInvalid = or(_isInvalid_T_4, _isInvalid_T_9)
node isNaNOut = and(isnan1, isnan2)
node _isLHS_T = bits(in.bits.rm, 0, 0)
node _isLHS_T_1 = neq(_isLHS_T, io.lt)
node _isLHS_T_2 = eq(isnan1, UInt<1>(0h0))
node _isLHS_T_3 = and(_isLHS_T_1, _isLHS_T_2)
node isLHS = or(isnan2, _isLHS_T_3)
node _fsgnjMux_exc_T = shl(isInvalid, 4)
connect fsgnjMux.exc, _fsgnjMux_exc_T
node _fsgnjMux_data_T = mux(isLHS, in.bits.in1, in.bits.in2)
node _fsgnjMux_data_T_1 = mux(isNaNOut, UInt<65>(0he008000000000000), _fsgnjMux_data_T)
connect fsgnjMux.data, _fsgnjMux_data_T_1
wire mux : { data : UInt<65>, exc : UInt<5>}
connect mux, fsgnjMux
node _T = eq(in.bits.typeTagOut, UInt<1>(0h0))
when _T :
node _mux_data_T = shr(fsgnjMux.data, 17)
node mux_data_sign = bits(fsgnjMux.data, 64, 64)
node mux_data_fractIn = bits(fsgnjMux.data, 51, 0)
node mux_data_expIn = bits(fsgnjMux.data, 63, 52)
node _mux_data_fractOut_T = shl(mux_data_fractIn, 11)
node mux_data_fractOut = shr(_mux_data_fractOut_T, 53)
node mux_data_expOut_expCode = bits(mux_data_expIn, 11, 9)
node _mux_data_expOut_commonCase_T = add(mux_data_expIn, UInt<6>(0h20))
node _mux_data_expOut_commonCase_T_1 = tail(_mux_data_expOut_commonCase_T, 1)
node _mux_data_expOut_commonCase_T_2 = sub(_mux_data_expOut_commonCase_T_1, UInt<12>(0h800))
node mux_data_expOut_commonCase = tail(_mux_data_expOut_commonCase_T_2, 1)
node _mux_data_expOut_T = eq(mux_data_expOut_expCode, UInt<1>(0h0))
node _mux_data_expOut_T_1 = geq(mux_data_expOut_expCode, UInt<3>(0h6))
node _mux_data_expOut_T_2 = or(_mux_data_expOut_T, _mux_data_expOut_T_1)
node _mux_data_expOut_T_3 = bits(mux_data_expOut_commonCase, 2, 0)
node _mux_data_expOut_T_4 = cat(mux_data_expOut_expCode, _mux_data_expOut_T_3)
node _mux_data_expOut_T_5 = bits(mux_data_expOut_commonCase, 5, 0)
node mux_data_expOut = mux(_mux_data_expOut_T_2, _mux_data_expOut_T_4, _mux_data_expOut_T_5)
node mux_data_hi = cat(mux_data_sign, mux_data_expOut)
node _mux_data_T_1 = cat(mux_data_hi, mux_data_fractOut)
node _mux_data_T_2 = cat(_mux_data_T, _mux_data_T_1)
connect mux.data, _mux_data_T_2
node _T_1 = eq(in.bits.typeTagOut, UInt<1>(0h1))
when _T_1 :
node _mux_data_T_3 = shr(fsgnjMux.data, 33)
node mux_data_sign_1 = bits(fsgnjMux.data, 64, 64)
node mux_data_fractIn_1 = bits(fsgnjMux.data, 51, 0)
node mux_data_expIn_1 = bits(fsgnjMux.data, 63, 52)
node _mux_data_fractOut_T_1 = shl(mux_data_fractIn_1, 24)
node mux_data_fractOut_1 = shr(_mux_data_fractOut_T_1, 53)
node mux_data_expOut_expCode_1 = bits(mux_data_expIn_1, 11, 9)
node _mux_data_expOut_commonCase_T_3 = add(mux_data_expIn_1, UInt<9>(0h100))
node _mux_data_expOut_commonCase_T_4 = tail(_mux_data_expOut_commonCase_T_3, 1)
node _mux_data_expOut_commonCase_T_5 = sub(_mux_data_expOut_commonCase_T_4, UInt<12>(0h800))
node mux_data_expOut_commonCase_1 = tail(_mux_data_expOut_commonCase_T_5, 1)
node _mux_data_expOut_T_6 = eq(mux_data_expOut_expCode_1, UInt<1>(0h0))
node _mux_data_expOut_T_7 = geq(mux_data_expOut_expCode_1, UInt<3>(0h6))
node _mux_data_expOut_T_8 = or(_mux_data_expOut_T_6, _mux_data_expOut_T_7)
node _mux_data_expOut_T_9 = bits(mux_data_expOut_commonCase_1, 5, 0)
node _mux_data_expOut_T_10 = cat(mux_data_expOut_expCode_1, _mux_data_expOut_T_9)
node _mux_data_expOut_T_11 = bits(mux_data_expOut_commonCase_1, 8, 0)
node mux_data_expOut_1 = mux(_mux_data_expOut_T_8, _mux_data_expOut_T_10, _mux_data_expOut_T_11)
node mux_data_hi_1 = cat(mux_data_sign_1, mux_data_expOut_1)
node _mux_data_T_4 = cat(mux_data_hi_1, mux_data_fractOut_1)
node _mux_data_T_5 = cat(_mux_data_T_3, _mux_data_T_4)
connect mux.data, _mux_data_T_5
node _T_2 = eq(in.bits.ren2, UInt<1>(0h0))
node _T_3 = and(in.bits.wflags, _T_2)
when _T_3 :
node _widened_T = bits(in.bits.in1, 63, 61)
node _widened_T_1 = andr(_widened_T)
node widened = mux(_widened_T_1, UInt<65>(0he008000000000000), in.bits.in1)
connect fsgnjMux.data, widened
node _fsgnjMux_exc_T_1 = bits(in.bits.in1, 63, 61)
node _fsgnjMux_exc_T_2 = andr(_fsgnjMux_exc_T_1)
node _fsgnjMux_exc_T_3 = bits(in.bits.in1, 51, 51)
node _fsgnjMux_exc_T_4 = eq(_fsgnjMux_exc_T_3, UInt<1>(0h0))
node _fsgnjMux_exc_T_5 = and(_fsgnjMux_exc_T_2, _fsgnjMux_exc_T_4)
node _fsgnjMux_exc_T_6 = shl(_fsgnjMux_exc_T_5, 4)
connect fsgnjMux.exc, _fsgnjMux_exc_T_6
node _T_4 = eq(in.bits.typeTagOut, UInt<1>(0h0))
node _T_5 = lt(in.bits.typeTagOut, in.bits.typeTagIn)
node _T_6 = or(UInt<1>(0h1), _T_5)
node _T_7 = and(_T_4, _T_6)
when _T_7 :
inst narrower of RecFNToRecFN_6
connect narrower.io.in, in.bits.in1
connect narrower.io.roundingMode, in.bits.rm
connect narrower.io.detectTininess, UInt<1>(0h1)
node _mux_data_T_6 = shr(fsgnjMux.data, 17)
node _mux_data_T_7 = cat(_mux_data_T_6, narrower.io.out)
connect mux.data, _mux_data_T_7
connect mux.exc, narrower.io.exceptionFlags
node _T_8 = eq(in.bits.typeTagOut, UInt<1>(0h1))
node _T_9 = lt(in.bits.typeTagOut, in.bits.typeTagIn)
node _T_10 = or(UInt<1>(0h0), _T_9)
node _T_11 = and(_T_8, _T_10)
when _T_11 :
inst narrower_1 of RecFNToRecFN_7
connect narrower_1.io.in, in.bits.in1
connect narrower_1.io.roundingMode, in.bits.rm
connect narrower_1.io.detectTininess, UInt<1>(0h1)
node _narrowed_maskedNaN_T = not(UInt<33>(0h10800000))
node narrowed_maskedNaN = and(narrower_1.io.out, _narrowed_maskedNaN_T)
node _narrowed_T = bits(narrower_1.io.out, 31, 29)
node _narrowed_T_1 = andr(_narrowed_T)
node narrowed = mux(_narrowed_T_1, narrowed_maskedNaN, narrower_1.io.out)
node _mux_data_T_8 = shr(fsgnjMux.data, 33)
node _mux_data_T_9 = cat(_mux_data_T_8, narrowed)
connect mux.data, _mux_data_T_9
connect mux.exc, narrower_1.io.exceptionFlags
regreset io_out_pipe_v : UInt<1>, clock, reset, UInt<1>(0h0)
connect io_out_pipe_v, in.valid
reg io_out_pipe_b : { data : UInt<65>, exc : UInt<5>}, clock
when in.valid :
connect io_out_pipe_b, mux
wire io_out_pipe_out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}
connect io_out_pipe_out.valid, io_out_pipe_v
connect io_out_pipe_out.bits, io_out_pipe_b
connect io.out, io_out_pipe_out | module FPToFP_3( // @[FPU.scala:573:7]
input clock, // @[FPU.scala:573:7]
input reset, // @[FPU.scala:573:7]
input io_in_valid, // @[FPU.scala:574:14]
input io_in_bits_ldst, // @[FPU.scala:574:14]
input io_in_bits_wen, // @[FPU.scala:574:14]
input io_in_bits_ren1, // @[FPU.scala:574:14]
input io_in_bits_ren2, // @[FPU.scala:574:14]
input io_in_bits_ren3, // @[FPU.scala:574:14]
input io_in_bits_swap12, // @[FPU.scala:574:14]
input io_in_bits_swap23, // @[FPU.scala:574:14]
input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:574:14]
input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:574:14]
input io_in_bits_fromint, // @[FPU.scala:574:14]
input io_in_bits_toint, // @[FPU.scala:574:14]
input io_in_bits_fastpipe, // @[FPU.scala:574:14]
input io_in_bits_fma, // @[FPU.scala:574:14]
input io_in_bits_div, // @[FPU.scala:574:14]
input io_in_bits_sqrt, // @[FPU.scala:574:14]
input io_in_bits_wflags, // @[FPU.scala:574:14]
input io_in_bits_vec, // @[FPU.scala:574:14]
input [2:0] io_in_bits_rm, // @[FPU.scala:574:14]
input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:574:14]
input [1:0] io_in_bits_typ, // @[FPU.scala:574:14]
input [1:0] io_in_bits_fmt, // @[FPU.scala:574:14]
input [64:0] io_in_bits_in1, // @[FPU.scala:574:14]
input [64:0] io_in_bits_in2, // @[FPU.scala:574:14]
input [64:0] io_in_bits_in3, // @[FPU.scala:574:14]
output [64:0] io_out_bits_data, // @[FPU.scala:574:14]
output [4:0] io_out_bits_exc, // @[FPU.scala:574:14]
input io_lt // @[FPU.scala:574:14]
);
wire [32:0] _narrower_1_io_out; // @[FPU.scala:619:30]
wire [4:0] _narrower_1_io_exceptionFlags; // @[FPU.scala:619:30]
wire [16:0] _narrower_io_out; // @[FPU.scala:619:30]
wire [4:0] _narrower_io_exceptionFlags; // @[FPU.scala:619:30]
wire io_in_valid_0 = io_in_valid; // @[FPU.scala:573:7]
wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:573:7]
wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:573:7]
wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:573:7]
wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:573:7]
wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:573:7]
wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:573:7]
wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:573:7]
wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:573:7]
wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:573:7]
wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:573:7]
wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:573:7]
wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:573:7]
wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:573:7]
wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:573:7]
wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:573:7]
wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:573:7]
wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:573:7]
wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:573:7]
wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:573:7]
wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:573:7]
wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:573:7]
wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:573:7]
wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:573:7]
wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:573:7]
wire io_lt_0 = io_lt; // @[FPU.scala:573:7]
wire [32:0] _narrowed_maskedNaN_T = 33'h1EF7FFFFF; // @[FPU.scala:413:27]
wire io_out_pipe_out_valid; // @[Valid.scala:135:21]
wire [64:0] io_out_pipe_out_bits_data; // @[Valid.scala:135:21]
wire [4:0] io_out_pipe_out_bits_exc; // @[Valid.scala:135:21]
wire [64:0] io_out_bits_data_0; // @[FPU.scala:573:7]
wire [4:0] io_out_bits_exc_0; // @[FPU.scala:573:7]
wire io_out_valid; // @[FPU.scala:573:7]
reg in_pipe_v; // @[Valid.scala:141:24]
wire in_valid = in_pipe_v; // @[Valid.scala:135:21, :141:24]
reg in_pipe_b_ldst; // @[Valid.scala:142:26]
wire in_bits_ldst = in_pipe_b_ldst; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_wen; // @[Valid.scala:142:26]
wire in_bits_wen = in_pipe_b_wen; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_ren1; // @[Valid.scala:142:26]
wire in_bits_ren1 = in_pipe_b_ren1; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_ren2; // @[Valid.scala:142:26]
wire in_bits_ren2 = in_pipe_b_ren2; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_ren3; // @[Valid.scala:142:26]
wire in_bits_ren3 = in_pipe_b_ren3; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_swap12; // @[Valid.scala:142:26]
wire in_bits_swap12 = in_pipe_b_swap12; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_swap23; // @[Valid.scala:142:26]
wire in_bits_swap23 = in_pipe_b_swap23; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_typeTagIn; // @[Valid.scala:142:26]
wire [1:0] in_bits_typeTagIn = in_pipe_b_typeTagIn; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_typeTagOut; // @[Valid.scala:142:26]
wire [1:0] in_bits_typeTagOut = in_pipe_b_typeTagOut; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_fromint; // @[Valid.scala:142:26]
wire in_bits_fromint = in_pipe_b_fromint; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_toint; // @[Valid.scala:142:26]
wire in_bits_toint = in_pipe_b_toint; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_fastpipe; // @[Valid.scala:142:26]
wire in_bits_fastpipe = in_pipe_b_fastpipe; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_fma; // @[Valid.scala:142:26]
wire in_bits_fma = in_pipe_b_fma; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_div; // @[Valid.scala:142:26]
wire in_bits_div = in_pipe_b_div; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_sqrt; // @[Valid.scala:142:26]
wire in_bits_sqrt = in_pipe_b_sqrt; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_wflags; // @[Valid.scala:142:26]
wire in_bits_wflags = in_pipe_b_wflags; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_vec; // @[Valid.scala:142:26]
wire in_bits_vec = in_pipe_b_vec; // @[Valid.scala:135:21, :142:26]
reg [2:0] in_pipe_b_rm; // @[Valid.scala:142:26]
wire [2:0] in_bits_rm = in_pipe_b_rm; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_fmaCmd; // @[Valid.scala:142:26]
wire [1:0] in_bits_fmaCmd = in_pipe_b_fmaCmd; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_typ; // @[Valid.scala:142:26]
wire [1:0] in_bits_typ = in_pipe_b_typ; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_fmt; // @[Valid.scala:142:26]
wire [1:0] in_bits_fmt = in_pipe_b_fmt; // @[Valid.scala:135:21, :142:26]
reg [64:0] in_pipe_b_in1; // @[Valid.scala:142:26]
wire [64:0] in_bits_in1 = in_pipe_b_in1; // @[Valid.scala:135:21, :142:26]
reg [64:0] in_pipe_b_in2; // @[Valid.scala:142:26]
wire [64:0] in_bits_in2 = in_pipe_b_in2; // @[Valid.scala:135:21, :142:26]
reg [64:0] in_pipe_b_in3; // @[Valid.scala:142:26]
wire [64:0] in_bits_in3 = in_pipe_b_in3; // @[Valid.scala:135:21, :142:26]
wire _signNum_T = in_bits_rm[1]; // @[Valid.scala:135:21]
wire [64:0] _signNum_T_1 = in_bits_in1 ^ in_bits_in2; // @[Valid.scala:135:21]
wire _signNum_T_2 = in_bits_rm[0]; // @[Valid.scala:135:21]
wire _isLHS_T = in_bits_rm[0]; // @[Valid.scala:135:21]
wire [64:0] _signNum_T_3 = ~in_bits_in2; // @[Valid.scala:135:21]
wire [64:0] _signNum_T_4 = _signNum_T_2 ? _signNum_T_3 : in_bits_in2; // @[Valid.scala:135:21]
wire [64:0] signNum = _signNum_T ? _signNum_T_1 : _signNum_T_4; // @[FPU.scala:582:{20,31,48,66}]
wire _fsgnj_T = signNum[64]; // @[FPU.scala:582:20, :583:26]
wire [63:0] _fsgnj_T_1 = in_bits_in1[63:0]; // @[Valid.scala:135:21]
wire [64:0] fsgnj = {_fsgnj_T, _fsgnj_T_1}; // @[FPU.scala:583:{18,26,45}]
wire [64:0] fsgnjMux_data; // @[FPU.scala:585:22]
wire [4:0] fsgnjMux_exc; // @[FPU.scala:585:22]
wire [2:0] _isnan1_T = in_bits_in1[63:61]; // @[Valid.scala:135:21]
wire [2:0] _isInvalid_T = in_bits_in1[63:61]; // @[Valid.scala:135:21]
wire [2:0] _widened_T = in_bits_in1[63:61]; // @[Valid.scala:135:21]
wire [2:0] _fsgnjMux_exc_T_1 = in_bits_in1[63:61]; // @[Valid.scala:135:21]
wire isnan1 = &_isnan1_T; // @[FPU.scala:249:{25,56}]
wire [2:0] _isnan2_T = in_bits_in2[63:61]; // @[Valid.scala:135:21]
wire [2:0] _isInvalid_T_5 = in_bits_in2[63:61]; // @[Valid.scala:135:21]
wire isnan2 = &_isnan2_T; // @[FPU.scala:249:{25,56}]
wire _isInvalid_T_1 = &_isInvalid_T; // @[FPU.scala:249:{25,56}]
wire _isInvalid_T_2 = in_bits_in1[51]; // @[Valid.scala:135:21]
wire _fsgnjMux_exc_T_3 = in_bits_in1[51]; // @[Valid.scala:135:21]
wire _isInvalid_T_3 = ~_isInvalid_T_2; // @[FPU.scala:250:{37,39}]
wire _isInvalid_T_4 = _isInvalid_T_1 & _isInvalid_T_3; // @[FPU.scala:249:56, :250:{34,37}]
wire _isInvalid_T_6 = &_isInvalid_T_5; // @[FPU.scala:249:{25,56}]
wire _isInvalid_T_7 = in_bits_in2[51]; // @[Valid.scala:135:21]
wire _isInvalid_T_8 = ~_isInvalid_T_7; // @[FPU.scala:250:{37,39}]
wire _isInvalid_T_9 = _isInvalid_T_6 & _isInvalid_T_8; // @[FPU.scala:249:56, :250:{34,37}]
wire isInvalid = _isInvalid_T_4 | _isInvalid_T_9; // @[FPU.scala:250:34, :592:49]
wire isNaNOut = isnan1 & isnan2; // @[FPU.scala:249:56, :593:27]
wire _isLHS_T_1 = _isLHS_T != io_lt_0; // @[FPU.scala:573:7, :594:{37,41}]
wire _isLHS_T_2 = ~isnan1; // @[FPU.scala:249:56, :594:54]
wire _isLHS_T_3 = _isLHS_T_1 & _isLHS_T_2; // @[FPU.scala:594:{41,51,54}]
wire isLHS = isnan2 | _isLHS_T_3; // @[FPU.scala:249:56, :594:{24,51}]
wire [4:0] _fsgnjMux_exc_T = {isInvalid, 4'h0}; // @[FPU.scala:592:49, :595:31]
wire [64:0] _fsgnjMux_data_T = isLHS ? in_bits_in1 : in_bits_in2; // @[Valid.scala:135:21]
wire [64:0] _fsgnjMux_data_T_1 = isNaNOut ? 65'hE008000000000000 : _fsgnjMux_data_T; // @[FPU.scala:593:27, :596:{25,53}]
wire [64:0] mux_data; // @[FPU.scala:601:24]
wire [4:0] mux_exc; // @[FPU.scala:601:24]
wire _T_7 = in_bits_typeTagOut == 2'h0; // @[Valid.scala:135:21]
wire [47:0] _mux_data_T = fsgnjMux_data[64:17]; // @[FPU.scala:585:22, :604:37]
wire [47:0] _mux_data_T_6 = fsgnjMux_data[64:17]; // @[FPU.scala:585:22, :604:37, :624:39]
wire mux_data_sign = fsgnjMux_data[64]; // @[FPU.scala:274:17, :585:22]
wire mux_data_sign_1 = fsgnjMux_data[64]; // @[FPU.scala:274:17, :585:22]
wire [51:0] mux_data_fractIn = fsgnjMux_data[51:0]; // @[FPU.scala:275:20, :585:22]
wire [51:0] mux_data_fractIn_1 = fsgnjMux_data[51:0]; // @[FPU.scala:275:20, :585:22]
wire [11:0] mux_data_expIn = fsgnjMux_data[63:52]; // @[FPU.scala:276:18, :585:22]
wire [11:0] mux_data_expIn_1 = fsgnjMux_data[63:52]; // @[FPU.scala:276:18, :585:22]
wire [62:0] _mux_data_fractOut_T = {mux_data_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28]
wire [9:0] mux_data_fractOut = _mux_data_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] mux_data_expOut_expCode = mux_data_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _mux_data_expOut_commonCase_T = {1'h0, mux_data_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31]
wire [11:0] _mux_data_expOut_commonCase_T_1 = _mux_data_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _mux_data_expOut_commonCase_T_2 = {1'h0, _mux_data_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] mux_data_expOut_commonCase = _mux_data_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _mux_data_expOut_T = mux_data_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _mux_data_expOut_T_1 = mux_data_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _mux_data_expOut_T_2 = _mux_data_expOut_T | _mux_data_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [2:0] _mux_data_expOut_T_3 = mux_data_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69]
wire [5:0] _mux_data_expOut_T_4 = {mux_data_expOut_expCode, _mux_data_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [5:0] _mux_data_expOut_T_5 = mux_data_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97]
wire [5:0] mux_data_expOut = _mux_data_expOut_T_2 ? _mux_data_expOut_T_4 : _mux_data_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [6:0] mux_data_hi = {mux_data_sign, mux_data_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [16:0] _mux_data_T_1 = {mux_data_hi, mux_data_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [64:0] _mux_data_T_2 = {_mux_data_T, _mux_data_T_1}; // @[FPU.scala:283:8, :604:{22,37}]
wire _T_8 = in_bits_typeTagOut == 2'h1; // @[Valid.scala:135:21]
wire [31:0] _mux_data_T_3 = fsgnjMux_data[64:33]; // @[FPU.scala:585:22, :604:37]
wire [31:0] _mux_data_T_8 = fsgnjMux_data[64:33]; // @[FPU.scala:585:22, :604:37, :624:39]
wire [75:0] _mux_data_fractOut_T_1 = {mux_data_fractIn_1, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] mux_data_fractOut_1 = _mux_data_fractOut_T_1[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] mux_data_expOut_expCode_1 = mux_data_expIn_1[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _mux_data_expOut_commonCase_T_3 = {1'h0, mux_data_expIn_1} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _mux_data_expOut_commonCase_T_4 = _mux_data_expOut_commonCase_T_3[11:0]; // @[FPU.scala:280:31]
wire [12:0] _mux_data_expOut_commonCase_T_5 = {1'h0, _mux_data_expOut_commonCase_T_4} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] mux_data_expOut_commonCase_1 = _mux_data_expOut_commonCase_T_5[11:0]; // @[FPU.scala:280:50]
wire _mux_data_expOut_T_6 = mux_data_expOut_expCode_1 == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _mux_data_expOut_T_7 = mux_data_expOut_expCode_1 > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _mux_data_expOut_T_8 = _mux_data_expOut_T_6 | _mux_data_expOut_T_7; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _mux_data_expOut_T_9 = mux_data_expOut_commonCase_1[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _mux_data_expOut_T_10 = {mux_data_expOut_expCode_1, _mux_data_expOut_T_9}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _mux_data_expOut_T_11 = mux_data_expOut_commonCase_1[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] mux_data_expOut_1 = _mux_data_expOut_T_8 ? _mux_data_expOut_T_10 : _mux_data_expOut_T_11; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] mux_data_hi_1 = {mux_data_sign_1, mux_data_expOut_1}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] _mux_data_T_4 = {mux_data_hi_1, mux_data_fractOut_1}; // @[FPU.scala:277:38, :283:8]
wire [64:0] _mux_data_T_5 = {_mux_data_T_3, _mux_data_T_4}; // @[FPU.scala:283:8, :604:{22,37}]
wire _T_3 = in_bits_wflags & ~in_bits_ren2; // @[Valid.scala:135:21]
wire _widened_T_1 = &_widened_T; // @[FPU.scala:249:{25,56}]
wire [64:0] widened = _widened_T_1 ? 65'hE008000000000000 : in_bits_in1; // @[Valid.scala:135:21]
assign fsgnjMux_data = _T_3 ? widened : in_bits_wflags ? _fsgnjMux_data_T_1 : fsgnj; // @[Valid.scala:135:21]
wire _fsgnjMux_exc_T_2 = &_fsgnjMux_exc_T_1; // @[FPU.scala:249:{25,56}]
wire _fsgnjMux_exc_T_4 = ~_fsgnjMux_exc_T_3; // @[FPU.scala:250:{37,39}]
wire _fsgnjMux_exc_T_5 = _fsgnjMux_exc_T_2 & _fsgnjMux_exc_T_4; // @[FPU.scala:249:56, :250:{34,37}]
wire [4:0] _fsgnjMux_exc_T_6 = {_fsgnjMux_exc_T_5, 4'h0}; // @[FPU.scala:250:34, :595:31, :613:51]
assign fsgnjMux_exc = _T_3 ? _fsgnjMux_exc_T_6 : in_bits_wflags ? _fsgnjMux_exc_T : 5'h0; // @[Valid.scala:135:21]
wire [64:0] _mux_data_T_7 = {_mux_data_T_6, _narrower_io_out}; // @[FPU.scala:619:30, :624:{24,39}]
wire _T_11 = _T_8 & in_bits_typeTagOut < in_bits_typeTagIn; // @[Valid.scala:135:21]
wire [32:0] narrowed_maskedNaN = _narrower_1_io_out & 33'h1EF7FFFFF; // @[FPU.scala:413:25, :619:30]
wire [2:0] _narrowed_T = _narrower_1_io_out[31:29]; // @[FPU.scala:249:25, :619:30]
wire _narrowed_T_1 = &_narrowed_T; // @[FPU.scala:249:{25,56}]
wire [32:0] narrowed = _narrowed_T_1 ? narrowed_maskedNaN : _narrower_1_io_out; // @[FPU.scala:249:56, :413:25, :414:10, :619:30]
wire [64:0] _mux_data_T_9 = {_mux_data_T_8, narrowed}; // @[FPU.scala:414:10, :624:{24,39}]
assign mux_data = _T_3 ? (_T_11 ? _mux_data_T_9 : _T_7 ? _mux_data_T_7 : _T_8 ? _mux_data_T_5 : fsgnjMux_data) : _T_8 ? _mux_data_T_5 : _T_7 ? _mux_data_T_2 : fsgnjMux_data; // @[FPU.scala:585:22, :601:24, :603:{18,36}, :604:{16,22}, :608:{24,42}, :618:{76,126}, :624:{18,24}]
assign mux_exc = _T_3 ? (_T_11 ? _narrower_1_io_exceptionFlags : _T_7 ? _narrower_io_exceptionFlags : fsgnjMux_exc) : fsgnjMux_exc; // @[FPU.scala:585:22, :601:24, :603:18, :608:{24,42}, :618:{76,126}, :619:30, :625:17]
reg io_out_pipe_v; // @[Valid.scala:141:24]
assign io_out_pipe_out_valid = io_out_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26]
assign io_out_pipe_out_bits_data = io_out_pipe_b_data; // @[Valid.scala:135:21, :142:26]
reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26]
assign io_out_pipe_out_bits_exc = io_out_pipe_b_exc; // @[Valid.scala:135:21, :142:26]
assign io_out_valid = io_out_pipe_out_valid; // @[Valid.scala:135:21]
assign io_out_bits_data_0 = io_out_pipe_out_bits_data; // @[Valid.scala:135:21]
assign io_out_bits_exc_0 = io_out_pipe_out_bits_exc; // @[Valid.scala:135:21]
always @(posedge clock) begin // @[FPU.scala:573:7]
if (reset) begin // @[FPU.scala:573:7]
in_pipe_v <= 1'h0; // @[Valid.scala:141:24]
io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24]
end
else begin // @[FPU.scala:573:7]
in_pipe_v <= io_in_valid_0; // @[Valid.scala:141:24]
io_out_pipe_v <= in_valid; // @[Valid.scala:135:21, :141:24]
end
if (io_in_valid_0) begin // @[FPU.scala:573:7]
in_pipe_b_ldst <= io_in_bits_ldst_0; // @[Valid.scala:142:26]
in_pipe_b_wen <= io_in_bits_wen_0; // @[Valid.scala:142:26]
in_pipe_b_ren1 <= io_in_bits_ren1_0; // @[Valid.scala:142:26]
in_pipe_b_ren2 <= io_in_bits_ren2_0; // @[Valid.scala:142:26]
in_pipe_b_ren3 <= io_in_bits_ren3_0; // @[Valid.scala:142:26]
in_pipe_b_swap12 <= io_in_bits_swap12_0; // @[Valid.scala:142:26]
in_pipe_b_swap23 <= io_in_bits_swap23_0; // @[Valid.scala:142:26]
in_pipe_b_typeTagIn <= io_in_bits_typeTagIn_0; // @[Valid.scala:142:26]
in_pipe_b_typeTagOut <= io_in_bits_typeTagOut_0; // @[Valid.scala:142:26]
in_pipe_b_fromint <= io_in_bits_fromint_0; // @[Valid.scala:142:26]
in_pipe_b_toint <= io_in_bits_toint_0; // @[Valid.scala:142:26]
in_pipe_b_fastpipe <= io_in_bits_fastpipe_0; // @[Valid.scala:142:26]
in_pipe_b_fma <= io_in_bits_fma_0; // @[Valid.scala:142:26]
in_pipe_b_div <= io_in_bits_div_0; // @[Valid.scala:142:26]
in_pipe_b_sqrt <= io_in_bits_sqrt_0; // @[Valid.scala:142:26]
in_pipe_b_wflags <= io_in_bits_wflags_0; // @[Valid.scala:142:26]
in_pipe_b_vec <= io_in_bits_vec_0; // @[Valid.scala:142:26]
in_pipe_b_rm <= io_in_bits_rm_0; // @[Valid.scala:142:26]
in_pipe_b_fmaCmd <= io_in_bits_fmaCmd_0; // @[Valid.scala:142:26]
in_pipe_b_typ <= io_in_bits_typ_0; // @[Valid.scala:142:26]
in_pipe_b_fmt <= io_in_bits_fmt_0; // @[Valid.scala:142:26]
in_pipe_b_in1 <= io_in_bits_in1_0; // @[Valid.scala:142:26]
in_pipe_b_in2 <= io_in_bits_in2_0; // @[Valid.scala:142:26]
in_pipe_b_in3 <= io_in_bits_in3_0; // @[Valid.scala:142:26]
end
if (in_valid) begin // @[Valid.scala:135:21]
io_out_pipe_b_data <= mux_data; // @[Valid.scala:142:26]
io_out_pipe_b_exc <= mux_exc; // @[Valid.scala:142:26]
end
always @(posedge)
RecFNToRecFN_6 narrower ( // @[FPU.scala:619:30]
.io_in (in_bits_in1), // @[Valid.scala:135:21]
.io_roundingMode (in_bits_rm), // @[Valid.scala:135:21]
.io_out (_narrower_io_out),
.io_exceptionFlags (_narrower_io_exceptionFlags)
); // @[FPU.scala:619:30]
RecFNToRecFN_7 narrower_1 ( // @[FPU.scala:619:30]
.io_in (in_bits_in1), // @[Valid.scala:135:21]
.io_roundingMode (in_bits_rm), // @[Valid.scala:135:21]
.io_out (_narrower_1_io_out),
.io_exceptionFlags (_narrower_1_io_exceptionFlags)
); // @[FPU.scala:619:30]
assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:573:7]
assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:573:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_66 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}}
inst input_buffer of InputBuffer_66
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
connect input_buffer.io.deq[4].ready, UInt<1>(0h0)
connect input_buffer.io.deq[5].ready, UInt<1>(0h0)
connect input_buffer.io.deq[6].ready, UInt<1>(0h0)
connect input_buffer.io.deq[7].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter8_RouteComputerReq_66
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h1e))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1))
connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T
connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id
connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node
connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id
connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node
connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id
connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0)
node _T_9 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_9 :
connect states[0].g, UInt<3>(0h2)
node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1))
connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T
connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id
connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node
connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id
connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node
connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id
connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1)
node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_10 :
connect states[1].g, UInt<3>(0h2)
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_11 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_11 :
connect states[2].g, UInt<3>(0h2)
node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1))
connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T
connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id
connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node
connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id
connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node
connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id
connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3)
node _T_12 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid)
when _T_12 :
connect states[3].g, UInt<3>(0h2)
node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1))
connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T
connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id
connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node
connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id
connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node
connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id
connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4)
node _T_13 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid)
when _T_13 :
connect states[4].g, UInt<3>(0h2)
node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1))
connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T
connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id
connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node
connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id
connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node
connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id
connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5)
node _T_14 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid)
when _T_14 :
connect states[5].g, UInt<3>(0h2)
node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1))
connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T
connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id
connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node
connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id
connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node
connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id
connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6)
node _T_15 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid)
when _T_15 :
connect states[6].g, UInt<3>(0h2)
node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1))
connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T
connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id
connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node
connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id
connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node
connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id
connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7)
node _T_16 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid)
when _T_16 :
connect states[7].g, UInt<3>(0h2)
node _T_17 = and(io.router_req.ready, io.router_req.valid)
when _T_17 :
node _T_18 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_18, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_22 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_22 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_23 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_23 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_24 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_24 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_25 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_25 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_26 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id)
when _T_26 :
connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_27 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id)
when _T_27 :
connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_28 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id)
when _T_28 :
connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_29 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id)
when _T_29 :
connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3`
regreset mask : UInt<8>, clock, reset, UInt<8>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8]
wire vcalloc_vals : UInt<1>[8]
node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo)
node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo)
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1)
node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1)
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8)
node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9)
node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10)
node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11)
node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12)
node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13)
node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14)
node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15)
node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0))
node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21)
node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22)
node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23)
node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24)
node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25)
node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26)
node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27)
node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28)
node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29)
node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30)
node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31)
node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32)
node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33)
node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35)
node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_30 = and(io.router_req.ready, io.router_req.valid)
when _T_30 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_31 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_32 = or(_T_31, vcalloc_vals[2])
node _T_33 = or(_T_32, vcalloc_vals[3])
node _T_34 = or(_T_33, vcalloc_vals[4])
node _T_35 = or(_T_34, vcalloc_vals[5])
node _T_36 = or(_T_35, vcalloc_vals[6])
node _T_37 = or(_T_36, vcalloc_vals[7])
when _T_37 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = not(UInt<5>(0h0))
node _mask_T_8 = not(UInt<6>(0h0))
node _mask_T_9 = not(UInt<7>(0h0))
node _mask_T_10 = not(UInt<8>(0h0))
node _mask_T_11 = bits(vcalloc_sel, 0, 0)
node _mask_T_12 = bits(vcalloc_sel, 1, 1)
node _mask_T_13 = bits(vcalloc_sel, 2, 2)
node _mask_T_14 = bits(vcalloc_sel, 3, 3)
node _mask_T_15 = bits(vcalloc_sel, 4, 4)
node _mask_T_16 = bits(vcalloc_sel, 5, 5)
node _mask_T_17 = bits(vcalloc_sel, 6, 6)
node _mask_T_18 = bits(vcalloc_sel, 7, 7)
node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0))
node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0))
node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0))
node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0))
node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0))
node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0))
node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0))
node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0))
node _mask_T_27 = or(_mask_T_19, _mask_T_20)
node _mask_T_28 = or(_mask_T_27, _mask_T_21)
node _mask_T_29 = or(_mask_T_28, _mask_T_22)
node _mask_T_30 = or(_mask_T_29, _mask_T_23)
node _mask_T_31 = or(_mask_T_30, _mask_T_24)
node _mask_T_32 = or(_mask_T_31, _mask_T_25)
node _mask_T_33 = or(_mask_T_32, _mask_T_26)
wire _mask_WIRE : UInt<8>
connect _mask_WIRE, _mask_T_33
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4])
node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5])
node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6])
node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4)
node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5)
node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6)
node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8]
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10)
node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11)
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12)
node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13)
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25)
node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26)
node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27)
node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28)
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40)
node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41)
node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42)
node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43)
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55)
node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56)
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70)
node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71)
node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72)
node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73)
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82
connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84)
node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85)
node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86)
node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87)
node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88)
node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89)
node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97
connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99)
node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100)
node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101)
node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102)
node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103)
node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104)
node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112
connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114)
node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115)
node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116)
node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117)
node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118)
node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119)
node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127
connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8]
node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129)
node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130)
node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131)
node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132)
node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133)
node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134)
node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142
connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144)
node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145)
node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146)
node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147)
node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148)
node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149)
node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157
connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13
node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159)
node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160)
node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161)
node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162)
node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163)
node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164)
node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172
connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14
node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174)
node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175)
node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176)
node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177)
node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178)
node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179)
node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187
connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15
node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189)
node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190)
node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191)
node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192)
node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193)
node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194)
node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202
connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16
node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204)
node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205)
node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206)
node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207)
node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208)
node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209)
node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217
connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219)
node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220)
node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221)
node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222)
node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223)
node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224)
node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232
connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234)
node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235)
node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236)
node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237)
node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238)
node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239)
node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247
connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11
wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8]
node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249)
node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250)
node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251)
node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252)
node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253)
node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254)
node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262
connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264)
node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265)
node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266)
node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267)
node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268)
node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269)
node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277
connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22
node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279)
node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280)
node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281)
node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282)
node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283)
node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284)
node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285)
wire _io_vcalloc_req_bits_WIRE_23 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292
connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23
node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294)
node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295)
node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296)
node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297)
node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298)
node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299)
node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300)
wire _io_vcalloc_req_bits_WIRE_24 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307
connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24
node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309)
node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310)
node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311)
node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312)
node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313)
node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314)
node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315)
wire _io_vcalloc_req_bits_WIRE_25 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322
connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25
node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324)
node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325)
node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326)
node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327)
node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328)
node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329)
node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330)
wire _io_vcalloc_req_bits_WIRE_26 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337
connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26
node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339)
node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340)
node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341)
node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342)
node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343)
node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344)
node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345)
wire _io_vcalloc_req_bits_WIRE_27 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352
connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27
node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354)
node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355)
node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356)
node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357)
node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358)
node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359)
node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360)
wire _io_vcalloc_req_bits_WIRE_28 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367
connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20
wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8]
node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369)
node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370)
node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371)
node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372)
node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373)
node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374)
node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375)
wire _io_vcalloc_req_bits_WIRE_30 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382
connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30
node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384)
node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385)
node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386)
node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387)
node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388)
node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389)
node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390)
wire _io_vcalloc_req_bits_WIRE_31 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397
connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31
node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399)
node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400)
node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401)
node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402)
node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403)
node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404)
node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405)
wire _io_vcalloc_req_bits_WIRE_32 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412
connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32
node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414)
node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415)
node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416)
node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417)
node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418)
node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419)
node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420)
wire _io_vcalloc_req_bits_WIRE_33 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427
connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33
node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429)
node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430)
node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431)
node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432)
node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433)
node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434)
node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435)
wire _io_vcalloc_req_bits_WIRE_34 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442
connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34
node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444)
node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445)
node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446)
node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447)
node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448)
node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449)
node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450)
wire _io_vcalloc_req_bits_WIRE_35 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457
connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35
node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459)
node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460)
node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461)
node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462)
node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463)
node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464)
node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465)
wire _io_vcalloc_req_bits_WIRE_36 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472
connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36
node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474)
node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475)
node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476)
node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477)
node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478)
node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479)
node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480)
wire _io_vcalloc_req_bits_WIRE_37 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487
connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37
connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489)
node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490)
node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491)
node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492)
node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493)
node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494)
node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495)
wire _io_vcalloc_req_bits_WIRE_38 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_502
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_38
wire _io_vcalloc_req_bits_WIRE_39 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504)
node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505)
node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506)
node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507)
node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508)
node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509)
node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510)
wire _io_vcalloc_req_bits_WIRE_40 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517
connect _io_vcalloc_req_bits_WIRE_39.egress_node_id, _io_vcalloc_req_bits_WIRE_40
node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519)
node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520)
node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521)
node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522)
node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523)
node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524)
node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525)
wire _io_vcalloc_req_bits_WIRE_41 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532
connect _io_vcalloc_req_bits_WIRE_39.egress_node, _io_vcalloc_req_bits_WIRE_41
node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534)
node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535)
node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536)
node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537)
node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538)
node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539)
node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540)
wire _io_vcalloc_req_bits_WIRE_42 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547
connect _io_vcalloc_req_bits_WIRE_39.ingress_node_id, _io_vcalloc_req_bits_WIRE_42
node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549)
node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550)
node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551)
node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552)
node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553)
node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554)
node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555)
wire _io_vcalloc_req_bits_WIRE_43 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562
connect _io_vcalloc_req_bits_WIRE_39.ingress_node, _io_vcalloc_req_bits_WIRE_43
node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564)
node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565)
node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566)
node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567)
node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568)
node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569)
node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570)
wire _io_vcalloc_req_bits_WIRE_44 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577
connect _io_vcalloc_req_bits_WIRE_39.vnet_id, _io_vcalloc_req_bits_WIRE_44
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_39
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2))
node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1)
connect vcalloc_vals[0], _vcalloc_vals_0_T_2
connect vcalloc_reqs[0].in_vc, UInt<1>(0h0)
connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2`
connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3`
connect vcalloc_reqs[0].flow, states[0].flow
node _T_38 = bits(vcalloc_sel, 0, 0)
node _T_39 = and(vcalloc_vals[0], _T_38)
node _T_40 = and(_T_39, io.vcalloc_req.ready)
when _T_40 :
connect states[0].g, UInt<3>(0h3)
node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2))
node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1)
connect vcalloc_vals[1], _vcalloc_vals_1_T_2
connect vcalloc_reqs[1].in_vc, UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1`
connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2`
connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3`
connect vcalloc_reqs[1].flow, states[1].flow
node _T_41 = bits(vcalloc_sel, 1, 1)
node _T_42 = and(vcalloc_vals[1], _T_41)
node _T_43 = and(_T_42, io.vcalloc_req.ready)
when _T_43 :
connect states[1].g, UInt<3>(0h3)
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2`
connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_44 = bits(vcalloc_sel, 2, 2)
node _T_45 = and(vcalloc_vals[2], _T_44)
node _T_46 = and(_T_45, io.vcalloc_req.ready)
when _T_46 :
connect states[2].g, UInt<3>(0h3)
node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2))
node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1)
connect vcalloc_vals[3], _vcalloc_vals_3_T_2
connect vcalloc_reqs[3].in_vc, UInt<2>(0h3)
connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0`
connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1`
connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2`
connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3`
connect vcalloc_reqs[3].flow, states[3].flow
node _T_47 = bits(vcalloc_sel, 3, 3)
node _T_48 = and(vcalloc_vals[3], _T_47)
node _T_49 = and(_T_48, io.vcalloc_req.ready)
when _T_49 :
connect states[3].g, UInt<3>(0h3)
node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2))
node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1)
connect vcalloc_vals[4], _vcalloc_vals_4_T_2
connect vcalloc_reqs[4].in_vc, UInt<3>(0h4)
connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0`
connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1`
connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2`
connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3`
connect vcalloc_reqs[4].flow, states[4].flow
node _T_50 = bits(vcalloc_sel, 4, 4)
node _T_51 = and(vcalloc_vals[4], _T_50)
node _T_52 = and(_T_51, io.vcalloc_req.ready)
when _T_52 :
connect states[4].g, UInt<3>(0h3)
node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2))
node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1)
connect vcalloc_vals[5], _vcalloc_vals_5_T_2
connect vcalloc_reqs[5].in_vc, UInt<3>(0h5)
connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0`
connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1`
connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2`
connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3`
connect vcalloc_reqs[5].flow, states[5].flow
node _T_53 = bits(vcalloc_sel, 5, 5)
node _T_54 = and(vcalloc_vals[5], _T_53)
node _T_55 = and(_T_54, io.vcalloc_req.ready)
when _T_55 :
connect states[5].g, UInt<3>(0h3)
node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2))
node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1)
connect vcalloc_vals[6], _vcalloc_vals_6_T_2
connect vcalloc_reqs[6].in_vc, UInt<3>(0h6)
connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0`
connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1`
connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2`
connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3`
connect vcalloc_reqs[6].flow, states[6].flow
node _T_56 = bits(vcalloc_sel, 6, 6)
node _T_57 = and(vcalloc_vals[6], _T_56)
node _T_58 = and(_T_57, io.vcalloc_req.ready)
when _T_58 :
connect states[6].g, UInt<3>(0h3)
node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2))
node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1)
connect vcalloc_vals[7], _vcalloc_vals_7_T_2
connect vcalloc_reqs[7].in_vc, UInt<3>(0h7)
connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0`
connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1`
connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2`
connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3`
connect vcalloc_reqs[7].flow, states[7].flow
node _T_59 = bits(vcalloc_sel, 7, 7)
node _T_60 = and(vcalloc_vals[7], _T_59)
node _T_61 = and(_T_60, io.vcalloc_req.ready)
when _T_61 :
connect states[7].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0)
node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5])
node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0)
node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7])
node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0)
node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9)
node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0)
node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11)
node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0)
node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready)
node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_15
node _T_62 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_62 :
node _T_63 = bits(vcalloc_sel, 0, 0)
when _T_63 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[0].g, UInt<3>(0h3)
node _T_64 = eq(states[0].g, UInt<3>(0h2))
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_64, UInt<1>(0h1), "") : assert_3
node _T_68 = bits(vcalloc_sel, 1, 1)
when _T_68 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[1].g, UInt<3>(0h3)
node _T_69 = eq(states[1].g, UInt<3>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_69, UInt<1>(0h1), "") : assert_4
node _T_73 = bits(vcalloc_sel, 2, 2)
when _T_73 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[2].g, UInt<3>(0h3)
node _T_74 = eq(states[2].g, UInt<3>(0h2))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_74, UInt<1>(0h1), "") : assert_5
node _T_78 = bits(vcalloc_sel, 3, 3)
when _T_78 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[3].g, UInt<3>(0h3)
node _T_79 = eq(states[3].g, UInt<3>(0h2))
node _T_80 = asUInt(reset)
node _T_81 = eq(_T_80, UInt<1>(0h0))
when _T_81 :
node _T_82 = eq(_T_79, UInt<1>(0h0))
when _T_82 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_79, UInt<1>(0h1), "") : assert_6
node _T_83 = bits(vcalloc_sel, 4, 4)
when _T_83 :
connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[4].g, UInt<3>(0h3)
node _T_84 = eq(states[4].g, UInt<3>(0h2))
node _T_85 = asUInt(reset)
node _T_86 = eq(_T_85, UInt<1>(0h0))
when _T_86 :
node _T_87 = eq(_T_84, UInt<1>(0h0))
when _T_87 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7
assert(clock, _T_84, UInt<1>(0h1), "") : assert_7
node _T_88 = bits(vcalloc_sel, 5, 5)
when _T_88 :
connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[5].g, UInt<3>(0h3)
node _T_89 = eq(states[5].g, UInt<3>(0h2))
node _T_90 = asUInt(reset)
node _T_91 = eq(_T_90, UInt<1>(0h0))
when _T_91 :
node _T_92 = eq(_T_89, UInt<1>(0h0))
when _T_92 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8
assert(clock, _T_89, UInt<1>(0h1), "") : assert_8
node _T_93 = bits(vcalloc_sel, 6, 6)
when _T_93 :
connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[6].g, UInt<3>(0h3)
node _T_94 = eq(states[6].g, UInt<3>(0h2))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9
assert(clock, _T_94, UInt<1>(0h1), "") : assert_9
node _T_98 = bits(vcalloc_sel, 7, 7)
when _T_98 :
connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[7].g, UInt<3>(0h3)
node _T_99 = eq(states[7].g, UInt<3>(0h2))
node _T_100 = asUInt(reset)
node _T_101 = eq(_T_100, UInt<1>(0h0))
when _T_101 :
node _T_102 = eq(_T_99, UInt<1>(0h0))
when _T_102 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10
assert(clock, _T_99, UInt<1>(0h1), "") : assert_10
inst salloc_arb of SwitchArbiter_165
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
node credit_available_lo_lo = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0])
node credit_available_lo_hi = cat(states[0].vc_sel.`0`[3], states[0].vc_sel.`0`[2])
node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo)
node credit_available_hi_lo = cat(states[0].vc_sel.`0`[5], states[0].vc_sel.`0`[4])
node credit_available_hi_hi = cat(states[0].vc_sel.`0`[7], states[0].vc_sel.`0`[6])
node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo)
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node credit_available_lo_lo_1 = cat(states[0].vc_sel.`1`[1], states[0].vc_sel.`1`[0])
node credit_available_lo_hi_1 = cat(states[0].vc_sel.`1`[3], states[0].vc_sel.`1`[2])
node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1)
node credit_available_hi_lo_1 = cat(states[0].vc_sel.`1`[5], states[0].vc_sel.`1`[4])
node credit_available_hi_hi_1 = cat(states[0].vc_sel.`1`[7], states[0].vc_sel.`1`[6])
node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1)
node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1)
node credit_available_lo_lo_2 = cat(states[0].vc_sel.`2`[1], states[0].vc_sel.`2`[0])
node credit_available_lo_hi_2 = cat(states[0].vc_sel.`2`[3], states[0].vc_sel.`2`[2])
node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2)
node credit_available_hi_lo_2 = cat(states[0].vc_sel.`2`[5], states[0].vc_sel.`2`[4])
node credit_available_hi_hi_2 = cat(states[0].vc_sel.`2`[7], states[0].vc_sel.`2`[6])
node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2)
node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2)
node credit_available_lo_lo_3 = cat(states[0].vc_sel.`3`[1], states[0].vc_sel.`3`[0])
node credit_available_lo_hi_3 = cat(states[0].vc_sel.`3`[3], states[0].vc_sel.`3`[2])
node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3)
node credit_available_hi_lo_3 = cat(states[0].vc_sel.`3`[5], states[0].vc_sel.`3`[4])
node credit_available_hi_hi_3 = cat(states[0].vc_sel.`3`[7], states[0].vc_sel.`3`[6])
node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3)
node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3)
node credit_available_lo_4 = cat(_credit_available_T_1, _credit_available_T)
node credit_available_hi_4 = cat(_credit_available_T_3, _credit_available_T_2)
node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4)
node credit_available_lo_lo_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_4 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_5 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4)
node credit_available_hi_lo_4 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_4 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4)
node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5)
node credit_available_lo_lo_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_5 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5)
node credit_available_hi_lo_5 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_5 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5)
node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6)
node credit_available_lo_lo_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_6 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6)
node credit_available_hi_lo_6 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_6 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_7 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6)
node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7)
node credit_available_lo_lo_7 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_7 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7)
node credit_available_hi_lo_7 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_7 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_8 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7)
node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8)
node credit_available_lo_9 = cat(_credit_available_T_6, _credit_available_T_5)
node credit_available_hi_9 = cat(_credit_available_T_8, _credit_available_T_7)
node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9)
node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9)
node credit_available = neq(_credit_available_T_10, UInt<1>(0h0))
node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3))
node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available)
node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid)
connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2
connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[6], states[0].vc_sel.`0`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[7], states[0].vc_sel.`0`[7]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[3], states[0].vc_sel.`1`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[4], states[0].vc_sel.`1`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[5], states[0].vc_sel.`1`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[6], states[0].vc_sel.`1`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[7], states[0].vc_sel.`1`[7]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[3], states[0].vc_sel.`2`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[4], states[0].vc_sel.`2`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[5], states[0].vc_sel.`2`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[6], states[0].vc_sel.`2`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[7], states[0].vc_sel.`2`[7]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[1], states[0].vc_sel.`3`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[2], states[0].vc_sel.`3`[2]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[3], states[0].vc_sel.`3`[3]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[4], states[0].vc_sel.`3`[4]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[5], states[0].vc_sel.`3`[5]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[6], states[0].vc_sel.`3`[6]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[7], states[0].vc_sel.`3`[7]
connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail
node _T_103 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid)
node _T_104 = and(_T_103, input_buffer.io.deq[0].bits.tail)
when _T_104 :
connect states[0].g, UInt<3>(0h0)
connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready
node credit_available_lo_lo_8 = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0])
node credit_available_lo_hi_8 = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2])
node credit_available_lo_10 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8)
node credit_available_hi_lo_8 = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4])
node credit_available_hi_hi_8 = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6])
node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8)
node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_10)
node credit_available_lo_lo_9 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0])
node credit_available_lo_hi_9 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2])
node credit_available_lo_11 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9)
node credit_available_hi_lo_9 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4])
node credit_available_hi_hi_9 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6])
node credit_available_hi_11 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9)
node _credit_available_T_12 = cat(credit_available_hi_11, credit_available_lo_11)
node credit_available_lo_lo_10 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0])
node credit_available_lo_hi_10 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2])
node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10)
node credit_available_hi_lo_10 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4])
node credit_available_hi_hi_10 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6])
node credit_available_hi_12 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10)
node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12)
node credit_available_lo_lo_11 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0])
node credit_available_lo_hi_11 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2])
node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11)
node credit_available_hi_lo_11 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4])
node credit_available_hi_hi_11 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6])
node credit_available_hi_13 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11)
node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13)
node credit_available_lo_14 = cat(_credit_available_T_12, _credit_available_T_11)
node credit_available_hi_14 = cat(_credit_available_T_14, _credit_available_T_13)
node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14)
node credit_available_lo_lo_12 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_12 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_15 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12)
node credit_available_hi_lo_12 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_12 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_15 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12)
node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15)
node credit_available_lo_lo_13 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_13 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_16 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13)
node credit_available_hi_lo_13 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_13 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_16 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13)
node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16)
node credit_available_lo_lo_14 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_14 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_17 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14)
node credit_available_hi_lo_14 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_14 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_17 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14)
node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17)
node credit_available_lo_lo_15 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_15 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15)
node credit_available_hi_lo_15 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_15 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_18 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15)
node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18)
node credit_available_lo_19 = cat(_credit_available_T_17, _credit_available_T_16)
node credit_available_hi_19 = cat(_credit_available_T_19, _credit_available_T_18)
node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19)
node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20)
node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0))
node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3))
node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1)
node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid)
connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2
connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7]
connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail
node _T_105 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid)
node _T_106 = and(_T_105, input_buffer.io.deq[1].bits.tail)
when _T_106 :
connect states[1].g, UInt<3>(0h0)
connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready
node credit_available_lo_lo_16 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0])
node credit_available_lo_hi_16 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2])
node credit_available_lo_20 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16)
node credit_available_hi_lo_16 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4])
node credit_available_hi_hi_16 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6])
node credit_available_hi_20 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16)
node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_20)
node credit_available_lo_lo_17 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0])
node credit_available_lo_hi_17 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2])
node credit_available_lo_21 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17)
node credit_available_hi_lo_17 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4])
node credit_available_hi_hi_17 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6])
node credit_available_hi_21 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17)
node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_21)
node credit_available_lo_lo_18 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0])
node credit_available_lo_hi_18 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2])
node credit_available_lo_22 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18)
node credit_available_hi_lo_18 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4])
node credit_available_hi_hi_18 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6])
node credit_available_hi_22 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18)
node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_22)
node credit_available_lo_lo_19 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0])
node credit_available_lo_hi_19 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2])
node credit_available_lo_23 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19)
node credit_available_hi_lo_19 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4])
node credit_available_hi_hi_19 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6])
node credit_available_hi_23 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19)
node _credit_available_T_25 = cat(credit_available_hi_23, credit_available_lo_23)
node credit_available_lo_24 = cat(_credit_available_T_23, _credit_available_T_22)
node credit_available_hi_24 = cat(_credit_available_T_25, _credit_available_T_24)
node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24)
node credit_available_lo_lo_20 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_20 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_25 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20)
node credit_available_hi_lo_20 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_20 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_25 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20)
node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25)
node credit_available_lo_lo_21 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_21 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_26 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21)
node credit_available_hi_lo_21 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_21 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_26 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21)
node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26)
node credit_available_lo_lo_22 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_22 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_27 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22)
node credit_available_hi_lo_22 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_22 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_27 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22)
node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27)
node credit_available_lo_lo_23 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_23 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_28 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23)
node credit_available_hi_lo_23 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_23 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_28 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23)
node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28)
node credit_available_lo_29 = cat(_credit_available_T_28, _credit_available_T_27)
node credit_available_hi_29 = cat(_credit_available_T_30, _credit_available_T_29)
node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29)
node _credit_available_T_32 = and(_credit_available_T_26, _credit_available_T_31)
node credit_available_2 = neq(_credit_available_T_32, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_107 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_108 = and(_T_107, input_buffer.io.deq[2].bits.tail)
when _T_108 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node credit_available_lo_lo_24 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0])
node credit_available_lo_hi_24 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2])
node credit_available_lo_30 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24)
node credit_available_hi_lo_24 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4])
node credit_available_hi_hi_24 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6])
node credit_available_hi_30 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24)
node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_30)
node credit_available_lo_lo_25 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0])
node credit_available_lo_hi_25 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2])
node credit_available_lo_31 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25)
node credit_available_hi_lo_25 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4])
node credit_available_hi_hi_25 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6])
node credit_available_hi_31 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25)
node _credit_available_T_34 = cat(credit_available_hi_31, credit_available_lo_31)
node credit_available_lo_lo_26 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0])
node credit_available_lo_hi_26 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2])
node credit_available_lo_32 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26)
node credit_available_hi_lo_26 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4])
node credit_available_hi_hi_26 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6])
node credit_available_hi_32 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26)
node _credit_available_T_35 = cat(credit_available_hi_32, credit_available_lo_32)
node credit_available_lo_lo_27 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0])
node credit_available_lo_hi_27 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2])
node credit_available_lo_33 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27)
node credit_available_hi_lo_27 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4])
node credit_available_hi_hi_27 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6])
node credit_available_hi_33 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27)
node _credit_available_T_36 = cat(credit_available_hi_33, credit_available_lo_33)
node credit_available_lo_34 = cat(_credit_available_T_34, _credit_available_T_33)
node credit_available_hi_34 = cat(_credit_available_T_36, _credit_available_T_35)
node _credit_available_T_37 = cat(credit_available_hi_34, credit_available_lo_34)
node credit_available_lo_lo_28 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_28 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_35 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28)
node credit_available_hi_lo_28 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_28 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_35 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28)
node _credit_available_T_38 = cat(credit_available_hi_35, credit_available_lo_35)
node credit_available_lo_lo_29 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_29 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_36 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29)
node credit_available_hi_lo_29 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_29 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_36 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29)
node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36)
node credit_available_lo_lo_30 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_30 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_37 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30)
node credit_available_hi_lo_30 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_30 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_37 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30)
node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37)
node credit_available_lo_lo_31 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_31 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_38 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31)
node credit_available_hi_lo_31 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_31 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_38 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31)
node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38)
node credit_available_lo_39 = cat(_credit_available_T_39, _credit_available_T_38)
node credit_available_hi_39 = cat(_credit_available_T_41, _credit_available_T_40)
node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39)
node _credit_available_T_43 = and(_credit_available_T_37, _credit_available_T_42)
node credit_available_3 = neq(_credit_available_T_43, UInt<1>(0h0))
node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3))
node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_3)
node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid)
connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2
connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7]
connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail
node _T_109 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid)
node _T_110 = and(_T_109, input_buffer.io.deq[3].bits.tail)
when _T_110 :
connect states[3].g, UInt<3>(0h0)
connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready
node credit_available_lo_lo_32 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0])
node credit_available_lo_hi_32 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2])
node credit_available_lo_40 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32)
node credit_available_hi_lo_32 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4])
node credit_available_hi_hi_32 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6])
node credit_available_hi_40 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32)
node _credit_available_T_44 = cat(credit_available_hi_40, credit_available_lo_40)
node credit_available_lo_lo_33 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0])
node credit_available_lo_hi_33 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2])
node credit_available_lo_41 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33)
node credit_available_hi_lo_33 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4])
node credit_available_hi_hi_33 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6])
node credit_available_hi_41 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33)
node _credit_available_T_45 = cat(credit_available_hi_41, credit_available_lo_41)
node credit_available_lo_lo_34 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0])
node credit_available_lo_hi_34 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2])
node credit_available_lo_42 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34)
node credit_available_hi_lo_34 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4])
node credit_available_hi_hi_34 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6])
node credit_available_hi_42 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34)
node _credit_available_T_46 = cat(credit_available_hi_42, credit_available_lo_42)
node credit_available_lo_lo_35 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0])
node credit_available_lo_hi_35 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2])
node credit_available_lo_43 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35)
node credit_available_hi_lo_35 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4])
node credit_available_hi_hi_35 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6])
node credit_available_hi_43 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35)
node _credit_available_T_47 = cat(credit_available_hi_43, credit_available_lo_43)
node credit_available_lo_44 = cat(_credit_available_T_45, _credit_available_T_44)
node credit_available_hi_44 = cat(_credit_available_T_47, _credit_available_T_46)
node _credit_available_T_48 = cat(credit_available_hi_44, credit_available_lo_44)
node credit_available_lo_lo_36 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_36 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_45 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36)
node credit_available_hi_lo_36 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_36 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_45 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36)
node _credit_available_T_49 = cat(credit_available_hi_45, credit_available_lo_45)
node credit_available_lo_lo_37 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_37 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_46 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37)
node credit_available_hi_lo_37 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_37 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_46 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37)
node _credit_available_T_50 = cat(credit_available_hi_46, credit_available_lo_46)
node credit_available_lo_lo_38 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_38 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_47 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38)
node credit_available_hi_lo_38 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_38 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_47 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38)
node _credit_available_T_51 = cat(credit_available_hi_47, credit_available_lo_47)
node credit_available_lo_lo_39 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_39 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_48 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39)
node credit_available_hi_lo_39 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_39 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_48 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39)
node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48)
node credit_available_lo_49 = cat(_credit_available_T_50, _credit_available_T_49)
node credit_available_hi_49 = cat(_credit_available_T_52, _credit_available_T_51)
node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49)
node _credit_available_T_54 = and(_credit_available_T_48, _credit_available_T_53)
node credit_available_4 = neq(_credit_available_T_54, UInt<1>(0h0))
node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3))
node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_4)
node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid)
connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2
connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7]
connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail
node _T_111 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid)
node _T_112 = and(_T_111, input_buffer.io.deq[4].bits.tail)
when _T_112 :
connect states[4].g, UInt<3>(0h0)
connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready
node credit_available_lo_lo_40 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0])
node credit_available_lo_hi_40 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2])
node credit_available_lo_50 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40)
node credit_available_hi_lo_40 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4])
node credit_available_hi_hi_40 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6])
node credit_available_hi_50 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40)
node _credit_available_T_55 = cat(credit_available_hi_50, credit_available_lo_50)
node credit_available_lo_lo_41 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0])
node credit_available_lo_hi_41 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2])
node credit_available_lo_51 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41)
node credit_available_hi_lo_41 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4])
node credit_available_hi_hi_41 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6])
node credit_available_hi_51 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41)
node _credit_available_T_56 = cat(credit_available_hi_51, credit_available_lo_51)
node credit_available_lo_lo_42 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0])
node credit_available_lo_hi_42 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2])
node credit_available_lo_52 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42)
node credit_available_hi_lo_42 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4])
node credit_available_hi_hi_42 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6])
node credit_available_hi_52 = cat(credit_available_hi_hi_42, credit_available_hi_lo_42)
node _credit_available_T_57 = cat(credit_available_hi_52, credit_available_lo_52)
node credit_available_lo_lo_43 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0])
node credit_available_lo_hi_43 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2])
node credit_available_lo_53 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43)
node credit_available_hi_lo_43 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4])
node credit_available_hi_hi_43 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6])
node credit_available_hi_53 = cat(credit_available_hi_hi_43, credit_available_hi_lo_43)
node _credit_available_T_58 = cat(credit_available_hi_53, credit_available_lo_53)
node credit_available_lo_54 = cat(_credit_available_T_56, _credit_available_T_55)
node credit_available_hi_54 = cat(_credit_available_T_58, _credit_available_T_57)
node _credit_available_T_59 = cat(credit_available_hi_54, credit_available_lo_54)
node credit_available_lo_lo_44 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_44 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_55 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44)
node credit_available_hi_lo_44 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_44 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_55 = cat(credit_available_hi_hi_44, credit_available_hi_lo_44)
node _credit_available_T_60 = cat(credit_available_hi_55, credit_available_lo_55)
node credit_available_lo_lo_45 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_45 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_56 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45)
node credit_available_hi_lo_45 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_45 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_56 = cat(credit_available_hi_hi_45, credit_available_hi_lo_45)
node _credit_available_T_61 = cat(credit_available_hi_56, credit_available_lo_56)
node credit_available_lo_lo_46 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_46 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_57 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46)
node credit_available_hi_lo_46 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_46 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_57 = cat(credit_available_hi_hi_46, credit_available_hi_lo_46)
node _credit_available_T_62 = cat(credit_available_hi_57, credit_available_lo_57)
node credit_available_lo_lo_47 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_47 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_58 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47)
node credit_available_hi_lo_47 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_47 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_58 = cat(credit_available_hi_hi_47, credit_available_hi_lo_47)
node _credit_available_T_63 = cat(credit_available_hi_58, credit_available_lo_58)
node credit_available_lo_59 = cat(_credit_available_T_61, _credit_available_T_60)
node credit_available_hi_59 = cat(_credit_available_T_63, _credit_available_T_62)
node _credit_available_T_64 = cat(credit_available_hi_59, credit_available_lo_59)
node _credit_available_T_65 = and(_credit_available_T_59, _credit_available_T_64)
node credit_available_5 = neq(_credit_available_T_65, UInt<1>(0h0))
node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3))
node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_5)
node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid)
connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2
connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7]
connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail
node _T_113 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid)
node _T_114 = and(_T_113, input_buffer.io.deq[5].bits.tail)
when _T_114 :
connect states[5].g, UInt<3>(0h0)
connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready
node credit_available_lo_lo_48 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0])
node credit_available_lo_hi_48 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2])
node credit_available_lo_60 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48)
node credit_available_hi_lo_48 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4])
node credit_available_hi_hi_48 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6])
node credit_available_hi_60 = cat(credit_available_hi_hi_48, credit_available_hi_lo_48)
node _credit_available_T_66 = cat(credit_available_hi_60, credit_available_lo_60)
node credit_available_lo_lo_49 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0])
node credit_available_lo_hi_49 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2])
node credit_available_lo_61 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49)
node credit_available_hi_lo_49 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4])
node credit_available_hi_hi_49 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6])
node credit_available_hi_61 = cat(credit_available_hi_hi_49, credit_available_hi_lo_49)
node _credit_available_T_67 = cat(credit_available_hi_61, credit_available_lo_61)
node credit_available_lo_lo_50 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0])
node credit_available_lo_hi_50 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2])
node credit_available_lo_62 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50)
node credit_available_hi_lo_50 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4])
node credit_available_hi_hi_50 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6])
node credit_available_hi_62 = cat(credit_available_hi_hi_50, credit_available_hi_lo_50)
node _credit_available_T_68 = cat(credit_available_hi_62, credit_available_lo_62)
node credit_available_lo_lo_51 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0])
node credit_available_lo_hi_51 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2])
node credit_available_lo_63 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51)
node credit_available_hi_lo_51 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4])
node credit_available_hi_hi_51 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6])
node credit_available_hi_63 = cat(credit_available_hi_hi_51, credit_available_hi_lo_51)
node _credit_available_T_69 = cat(credit_available_hi_63, credit_available_lo_63)
node credit_available_lo_64 = cat(_credit_available_T_67, _credit_available_T_66)
node credit_available_hi_64 = cat(_credit_available_T_69, _credit_available_T_68)
node _credit_available_T_70 = cat(credit_available_hi_64, credit_available_lo_64)
node credit_available_lo_lo_52 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_52 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_65 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52)
node credit_available_hi_lo_52 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_52 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_65 = cat(credit_available_hi_hi_52, credit_available_hi_lo_52)
node _credit_available_T_71 = cat(credit_available_hi_65, credit_available_lo_65)
node credit_available_lo_lo_53 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_53 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_66 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53)
node credit_available_hi_lo_53 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_53 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_66 = cat(credit_available_hi_hi_53, credit_available_hi_lo_53)
node _credit_available_T_72 = cat(credit_available_hi_66, credit_available_lo_66)
node credit_available_lo_lo_54 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_54 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_67 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54)
node credit_available_hi_lo_54 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_54 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_67 = cat(credit_available_hi_hi_54, credit_available_hi_lo_54)
node _credit_available_T_73 = cat(credit_available_hi_67, credit_available_lo_67)
node credit_available_lo_lo_55 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_55 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_68 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55)
node credit_available_hi_lo_55 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_55 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_68 = cat(credit_available_hi_hi_55, credit_available_hi_lo_55)
node _credit_available_T_74 = cat(credit_available_hi_68, credit_available_lo_68)
node credit_available_lo_69 = cat(_credit_available_T_72, _credit_available_T_71)
node credit_available_hi_69 = cat(_credit_available_T_74, _credit_available_T_73)
node _credit_available_T_75 = cat(credit_available_hi_69, credit_available_lo_69)
node _credit_available_T_76 = and(_credit_available_T_70, _credit_available_T_75)
node credit_available_6 = neq(_credit_available_T_76, UInt<1>(0h0))
node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3))
node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_6)
node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid)
connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2
connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7]
connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail
node _T_115 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid)
node _T_116 = and(_T_115, input_buffer.io.deq[6].bits.tail)
when _T_116 :
connect states[6].g, UInt<3>(0h0)
connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready
node credit_available_lo_lo_56 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0])
node credit_available_lo_hi_56 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2])
node credit_available_lo_70 = cat(credit_available_lo_hi_56, credit_available_lo_lo_56)
node credit_available_hi_lo_56 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4])
node credit_available_hi_hi_56 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6])
node credit_available_hi_70 = cat(credit_available_hi_hi_56, credit_available_hi_lo_56)
node _credit_available_T_77 = cat(credit_available_hi_70, credit_available_lo_70)
node credit_available_lo_lo_57 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0])
node credit_available_lo_hi_57 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2])
node credit_available_lo_71 = cat(credit_available_lo_hi_57, credit_available_lo_lo_57)
node credit_available_hi_lo_57 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4])
node credit_available_hi_hi_57 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6])
node credit_available_hi_71 = cat(credit_available_hi_hi_57, credit_available_hi_lo_57)
node _credit_available_T_78 = cat(credit_available_hi_71, credit_available_lo_71)
node credit_available_lo_lo_58 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0])
node credit_available_lo_hi_58 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2])
node credit_available_lo_72 = cat(credit_available_lo_hi_58, credit_available_lo_lo_58)
node credit_available_hi_lo_58 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4])
node credit_available_hi_hi_58 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6])
node credit_available_hi_72 = cat(credit_available_hi_hi_58, credit_available_hi_lo_58)
node _credit_available_T_79 = cat(credit_available_hi_72, credit_available_lo_72)
node credit_available_lo_lo_59 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0])
node credit_available_lo_hi_59 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2])
node credit_available_lo_73 = cat(credit_available_lo_hi_59, credit_available_lo_lo_59)
node credit_available_hi_lo_59 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4])
node credit_available_hi_hi_59 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6])
node credit_available_hi_73 = cat(credit_available_hi_hi_59, credit_available_hi_lo_59)
node _credit_available_T_80 = cat(credit_available_hi_73, credit_available_lo_73)
node credit_available_lo_74 = cat(_credit_available_T_78, _credit_available_T_77)
node credit_available_hi_74 = cat(_credit_available_T_80, _credit_available_T_79)
node _credit_available_T_81 = cat(credit_available_hi_74, credit_available_lo_74)
node credit_available_lo_lo_60 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_60 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_75 = cat(credit_available_lo_hi_60, credit_available_lo_lo_60)
node credit_available_hi_lo_60 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_60 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_75 = cat(credit_available_hi_hi_60, credit_available_hi_lo_60)
node _credit_available_T_82 = cat(credit_available_hi_75, credit_available_lo_75)
node credit_available_lo_lo_61 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node credit_available_lo_hi_61 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2])
node credit_available_lo_76 = cat(credit_available_lo_hi_61, credit_available_lo_lo_61)
node credit_available_hi_lo_61 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4])
node credit_available_hi_hi_61 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6])
node credit_available_hi_76 = cat(credit_available_hi_hi_61, credit_available_hi_lo_61)
node _credit_available_T_83 = cat(credit_available_hi_76, credit_available_lo_76)
node credit_available_lo_lo_62 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node credit_available_lo_hi_62 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2])
node credit_available_lo_77 = cat(credit_available_lo_hi_62, credit_available_lo_lo_62)
node credit_available_hi_lo_62 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4])
node credit_available_hi_hi_62 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6])
node credit_available_hi_77 = cat(credit_available_hi_hi_62, credit_available_hi_lo_62)
node _credit_available_T_84 = cat(credit_available_hi_77, credit_available_lo_77)
node credit_available_lo_lo_63 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_hi_63 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2])
node credit_available_lo_78 = cat(credit_available_lo_hi_63, credit_available_lo_lo_63)
node credit_available_hi_lo_63 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4])
node credit_available_hi_hi_63 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6])
node credit_available_hi_78 = cat(credit_available_hi_hi_63, credit_available_hi_lo_63)
node _credit_available_T_85 = cat(credit_available_hi_78, credit_available_lo_78)
node credit_available_lo_79 = cat(_credit_available_T_83, _credit_available_T_82)
node credit_available_hi_79 = cat(_credit_available_T_85, _credit_available_T_84)
node _credit_available_T_86 = cat(credit_available_hi_79, credit_available_lo_79)
node _credit_available_T_87 = and(_credit_available_T_81, _credit_available_T_86)
node credit_available_7 = neq(_credit_available_T_87, UInt<1>(0h0))
node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3))
node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_7)
node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid)
connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2
connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7]
connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail
node _T_117 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid)
node _T_118 = and(_T_117, input_buffer.io.deq[7].bits.tail)
when _T_118 :
connect states[7].g, UInt<3>(0h0)
connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8)
node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10)
node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12)
node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14)
node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0)
node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0)
node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19)
node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0)
node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11)
node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0)
node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15)
node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0)
node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25)
node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0)
node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27)
node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_29
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10)
node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11)
node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12)
node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13)
node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14)
node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15)
node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23
node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_25
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2)
node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0)
node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1)
node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1)
node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1)
node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4)
node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}
wire _vc_sel_WIRE : UInt<1>[8]
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10)
node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11)
node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12)
node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13)
node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_22
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25)
node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26)
node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27)
node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28)
node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_37
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40)
node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41)
node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42)
node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43)
node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44)
node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_52
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54)
node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55)
node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56)
node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57)
node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58)
node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59)
node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_67
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69)
node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70)
node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71)
node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72)
node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73)
node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74)
node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_82
connect _vc_sel_WIRE[4], _vc_sel_WIRE_5
node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84)
node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85)
node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86)
node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87)
node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88)
node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89)
node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_97
connect _vc_sel_WIRE[5], _vc_sel_WIRE_6
node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99)
node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100)
node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101)
node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102)
node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103)
node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104)
node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_112
connect _vc_sel_WIRE[6], _vc_sel_WIRE_7
node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114)
node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115)
node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116)
node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117)
node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118)
node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119)
node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_127
connect _vc_sel_WIRE[7], _vc_sel_WIRE_8
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_9 : UInt<1>[8]
node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129)
node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130)
node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131)
node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132)
node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133)
node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134)
node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_142
connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10
node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144)
node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145)
node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146)
node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147)
node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148)
node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149)
node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_157
connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11
node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159)
node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160)
node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161)
node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162)
node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163)
node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164)
node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165)
wire _vc_sel_WIRE_12 : UInt<1>
connect _vc_sel_WIRE_12, _vc_sel_T_172
connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12
node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0))
node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174)
node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175)
node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176)
node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177)
node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178)
node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179)
node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_187
connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13
node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0))
node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189)
node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190)
node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191)
node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192)
node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193)
node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194)
node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195)
wire _vc_sel_WIRE_14 : UInt<1>
connect _vc_sel_WIRE_14, _vc_sel_T_202
connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14
node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0))
node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204)
node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205)
node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206)
node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207)
node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208)
node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209)
node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210)
wire _vc_sel_WIRE_15 : UInt<1>
connect _vc_sel_WIRE_15, _vc_sel_T_217
connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15
node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0))
node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219)
node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220)
node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221)
node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222)
node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223)
node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224)
node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225)
wire _vc_sel_WIRE_16 : UInt<1>
connect _vc_sel_WIRE_16, _vc_sel_T_232
connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16
node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0))
node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234)
node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235)
node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236)
node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237)
node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238)
node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239)
node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240)
wire _vc_sel_WIRE_17 : UInt<1>
connect _vc_sel_WIRE_17, _vc_sel_T_247
connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17
connect vc_sel.`1`, _vc_sel_WIRE_9
wire _vc_sel_WIRE_18 : UInt<1>[8]
node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249)
node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250)
node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251)
node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252)
node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253)
node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254)
node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255)
wire _vc_sel_WIRE_19 : UInt<1>
connect _vc_sel_WIRE_19, _vc_sel_T_262
connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19
node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264)
node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265)
node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266)
node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267)
node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268)
node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269)
node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270)
wire _vc_sel_WIRE_20 : UInt<1>
connect _vc_sel_WIRE_20, _vc_sel_T_277
connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20
node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279)
node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280)
node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281)
node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282)
node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283)
node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284)
node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285)
wire _vc_sel_WIRE_21 : UInt<1>
connect _vc_sel_WIRE_21, _vc_sel_T_292
connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21
node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0))
node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294)
node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295)
node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296)
node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297)
node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298)
node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299)
node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300)
wire _vc_sel_WIRE_22 : UInt<1>
connect _vc_sel_WIRE_22, _vc_sel_T_307
connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22
node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0))
node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309)
node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310)
node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311)
node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312)
node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313)
node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314)
node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315)
wire _vc_sel_WIRE_23 : UInt<1>
connect _vc_sel_WIRE_23, _vc_sel_T_322
connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23
node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0))
node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324)
node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325)
node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326)
node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327)
node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328)
node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329)
node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330)
wire _vc_sel_WIRE_24 : UInt<1>
connect _vc_sel_WIRE_24, _vc_sel_T_337
connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24
node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0))
node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339)
node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340)
node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341)
node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342)
node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343)
node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344)
node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345)
wire _vc_sel_WIRE_25 : UInt<1>
connect _vc_sel_WIRE_25, _vc_sel_T_352
connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25
node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0))
node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354)
node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355)
node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356)
node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357)
node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358)
node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359)
node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360)
wire _vc_sel_WIRE_26 : UInt<1>
connect _vc_sel_WIRE_26, _vc_sel_T_367
connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26
connect vc_sel.`2`, _vc_sel_WIRE_18
wire _vc_sel_WIRE_27 : UInt<1>[8]
node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369)
node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370)
node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371)
node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372)
node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373)
node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374)
node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375)
wire _vc_sel_WIRE_28 : UInt<1>
connect _vc_sel_WIRE_28, _vc_sel_T_382
connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28
node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384)
node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385)
node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386)
node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387)
node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388)
node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389)
node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390)
wire _vc_sel_WIRE_29 : UInt<1>
connect _vc_sel_WIRE_29, _vc_sel_T_397
connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29
node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0))
node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399)
node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400)
node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401)
node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402)
node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403)
node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404)
node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405)
wire _vc_sel_WIRE_30 : UInt<1>
connect _vc_sel_WIRE_30, _vc_sel_T_412
connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30
node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0))
node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414)
node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415)
node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416)
node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417)
node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418)
node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419)
node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420)
wire _vc_sel_WIRE_31 : UInt<1>
connect _vc_sel_WIRE_31, _vc_sel_T_427
connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31
node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0))
node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429)
node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430)
node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431)
node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432)
node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433)
node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434)
node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435)
wire _vc_sel_WIRE_32 : UInt<1>
connect _vc_sel_WIRE_32, _vc_sel_T_442
connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32
node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0))
node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444)
node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445)
node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446)
node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447)
node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448)
node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449)
node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450)
wire _vc_sel_WIRE_33 : UInt<1>
connect _vc_sel_WIRE_33, _vc_sel_T_457
connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33
node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0))
node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459)
node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460)
node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461)
node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462)
node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463)
node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464)
node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465)
wire _vc_sel_WIRE_34 : UInt<1>
connect _vc_sel_WIRE_34, _vc_sel_T_472
connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34
node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0))
node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474)
node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475)
node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476)
node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477)
node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478)
node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479)
node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480)
wire _vc_sel_WIRE_35 : UInt<1>
connect _vc_sel_WIRE_35, _vc_sel_T_487
connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35
connect vc_sel.`3`, _vc_sel_WIRE_27
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3])
node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4])
node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5])
node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6])
node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7])
node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2])
node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3])
node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4])
node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5])
node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6])
node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7])
node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2])
node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3])
node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4])
node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5])
node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6])
node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7])
node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1])
node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2])
node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3])
node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4])
node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5])
node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6])
node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7])
node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2])
node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo)
node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4])
node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6])
node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo)
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4)
node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0)
node _virt_channel_T_3 = orr(virt_channel_hi_2)
node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2)
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5)
node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6)
node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0])
node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2])
node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1)
node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4])
node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6])
node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1)
node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3)
node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4)
node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0)
node _virt_channel_T_9 = orr(virt_channel_hi_4)
node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4)
node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2)
node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0)
node _virt_channel_T_11 = orr(virt_channel_hi_5)
node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5)
node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1)
node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13)
node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14)
node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0])
node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2])
node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2)
node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4])
node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6])
node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2)
node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6)
node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4)
node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0)
node _virt_channel_T_17 = orr(virt_channel_hi_7)
node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7)
node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2)
node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0)
node _virt_channel_T_19 = orr(virt_channel_hi_8)
node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8)
node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1)
node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21)
node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22)
node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0])
node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2])
node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3)
node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4])
node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6])
node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3)
node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9)
node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4)
node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0)
node _virt_channel_T_25 = orr(virt_channel_hi_10)
node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10)
node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2)
node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0)
node _virt_channel_T_27 = orr(virt_channel_hi_11)
node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11)
node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1)
node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29)
node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30)
node _virt_channel_T_32 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_33 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0))
node _virt_channel_T_34 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0))
node _virt_channel_T_35 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0))
node _virt_channel_T_36 = or(_virt_channel_T_32, _virt_channel_T_33)
node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_34)
node _virt_channel_T_38 = or(_virt_channel_T_37, _virt_channel_T_35)
wire virt_channel : UInt<3>
connect virt_channel, _virt_channel_T_38
node _T_119 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_119 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9)
node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10)
node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11)
node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12)
node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13)
node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14)
node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15)
wire _salloc_outs_0_flit_payload_WIRE : UInt<73>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9)
node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10)
node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11)
node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12)
node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13)
node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14)
node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9)
node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10)
node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11)
node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12)
node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13)
node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14)
node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10)
node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11)
node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12)
node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13)
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25)
node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26)
node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27)
node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28)
node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29)
node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39)
node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40)
node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41)
node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42)
node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43)
node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44)
node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54)
node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55)
node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56)
node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57)
node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58)
node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59)
node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69)
node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70)
node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71)
node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72)
node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73)
node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74)
node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
connect states[0].vc_sel.`0`[0], UInt<1>(0h0)
connect states[0].vc_sel.`0`[1], UInt<1>(0h0)
connect states[0].vc_sel.`0`[2], UInt<1>(0h0)
connect states[0].vc_sel.`0`[3], UInt<1>(0h0)
connect states[0].vc_sel.`0`[4], UInt<1>(0h0)
connect states[0].vc_sel.`0`[5], UInt<1>(0h0)
connect states[0].vc_sel.`0`[6], UInt<1>(0h0)
connect states[0].vc_sel.`0`[7], UInt<1>(0h0)
connect states[0].vc_sel.`3`[0], UInt<1>(0h0)
connect states[0].vc_sel.`3`[1], UInt<1>(0h0)
connect states[0].vc_sel.`3`[2], UInt<1>(0h0)
connect states[0].vc_sel.`3`[3], UInt<1>(0h0)
connect states[0].vc_sel.`3`[4], UInt<1>(0h0)
connect states[0].vc_sel.`3`[5], UInt<1>(0h0)
connect states[0].vc_sel.`3`[6], UInt<1>(0h0)
connect states[0].vc_sel.`3`[7], UInt<1>(0h0)
connect states[1].vc_sel.`0`[0], UInt<1>(0h0)
connect states[1].vc_sel.`0`[1], UInt<1>(0h0)
connect states[1].vc_sel.`0`[2], UInt<1>(0h0)
connect states[1].vc_sel.`0`[3], UInt<1>(0h0)
connect states[1].vc_sel.`0`[4], UInt<1>(0h0)
connect states[1].vc_sel.`0`[5], UInt<1>(0h0)
connect states[1].vc_sel.`0`[6], UInt<1>(0h0)
connect states[1].vc_sel.`0`[7], UInt<1>(0h0)
connect states[1].vc_sel.`3`[0], UInt<1>(0h0)
connect states[1].vc_sel.`3`[1], UInt<1>(0h0)
connect states[1].vc_sel.`3`[2], UInt<1>(0h0)
connect states[1].vc_sel.`3`[3], UInt<1>(0h0)
connect states[1].vc_sel.`3`[4], UInt<1>(0h0)
connect states[1].vc_sel.`3`[5], UInt<1>(0h0)
connect states[1].vc_sel.`3`[6], UInt<1>(0h0)
connect states[1].vc_sel.`3`[7], UInt<1>(0h0)
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`0`[1], UInt<1>(0h0)
connect states[2].vc_sel.`0`[2], UInt<1>(0h0)
connect states[2].vc_sel.`0`[3], UInt<1>(0h0)
connect states[2].vc_sel.`0`[4], UInt<1>(0h0)
connect states[2].vc_sel.`0`[5], UInt<1>(0h0)
connect states[2].vc_sel.`0`[6], UInt<1>(0h0)
connect states[2].vc_sel.`0`[7], UInt<1>(0h0)
connect states[2].vc_sel.`3`[0], UInt<1>(0h0)
connect states[2].vc_sel.`3`[1], UInt<1>(0h0)
connect states[2].vc_sel.`3`[2], UInt<1>(0h0)
connect states[2].vc_sel.`3`[3], UInt<1>(0h0)
connect states[2].vc_sel.`3`[4], UInt<1>(0h0)
connect states[2].vc_sel.`3`[5], UInt<1>(0h0)
connect states[2].vc_sel.`3`[6], UInt<1>(0h0)
connect states[2].vc_sel.`3`[7], UInt<1>(0h0)
connect states[3].vc_sel.`0`[0], UInt<1>(0h0)
connect states[3].vc_sel.`0`[1], UInt<1>(0h0)
connect states[3].vc_sel.`0`[2], UInt<1>(0h0)
connect states[3].vc_sel.`0`[3], UInt<1>(0h0)
connect states[3].vc_sel.`0`[4], UInt<1>(0h0)
connect states[3].vc_sel.`0`[5], UInt<1>(0h0)
connect states[3].vc_sel.`0`[6], UInt<1>(0h0)
connect states[3].vc_sel.`0`[7], UInt<1>(0h0)
connect states[3].vc_sel.`3`[0], UInt<1>(0h0)
connect states[3].vc_sel.`3`[1], UInt<1>(0h0)
connect states[3].vc_sel.`3`[2], UInt<1>(0h0)
connect states[3].vc_sel.`3`[3], UInt<1>(0h0)
connect states[3].vc_sel.`3`[4], UInt<1>(0h0)
connect states[3].vc_sel.`3`[5], UInt<1>(0h0)
connect states[3].vc_sel.`3`[6], UInt<1>(0h0)
connect states[3].vc_sel.`3`[7], UInt<1>(0h0)
connect states[4].vc_sel.`0`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[1], UInt<1>(0h0)
connect states[4].vc_sel.`0`[2], UInt<1>(0h0)
connect states[4].vc_sel.`0`[3], UInt<1>(0h0)
connect states[4].vc_sel.`0`[4], UInt<1>(0h0)
connect states[4].vc_sel.`0`[5], UInt<1>(0h0)
connect states[4].vc_sel.`0`[6], UInt<1>(0h0)
connect states[4].vc_sel.`0`[7], UInt<1>(0h0)
connect states[4].vc_sel.`3`[0], UInt<1>(0h0)
connect states[4].vc_sel.`3`[1], UInt<1>(0h0)
connect states[4].vc_sel.`3`[2], UInt<1>(0h0)
connect states[4].vc_sel.`3`[3], UInt<1>(0h0)
connect states[5].vc_sel.`0`[0], UInt<1>(0h0)
connect states[5].vc_sel.`0`[1], UInt<1>(0h0)
connect states[5].vc_sel.`0`[2], UInt<1>(0h0)
connect states[5].vc_sel.`0`[3], UInt<1>(0h0)
connect states[5].vc_sel.`0`[4], UInt<1>(0h0)
connect states[5].vc_sel.`0`[5], UInt<1>(0h0)
connect states[5].vc_sel.`0`[6], UInt<1>(0h0)
connect states[5].vc_sel.`0`[7], UInt<1>(0h0)
connect states[5].vc_sel.`3`[0], UInt<1>(0h0)
connect states[5].vc_sel.`3`[1], UInt<1>(0h0)
connect states[5].vc_sel.`3`[2], UInt<1>(0h0)
connect states[5].vc_sel.`3`[3], UInt<1>(0h0)
connect states[6].vc_sel.`0`[0], UInt<1>(0h0)
connect states[6].vc_sel.`0`[1], UInt<1>(0h0)
connect states[6].vc_sel.`0`[2], UInt<1>(0h0)
connect states[6].vc_sel.`0`[3], UInt<1>(0h0)
connect states[6].vc_sel.`0`[4], UInt<1>(0h0)
connect states[6].vc_sel.`0`[5], UInt<1>(0h0)
connect states[6].vc_sel.`0`[6], UInt<1>(0h0)
connect states[6].vc_sel.`0`[7], UInt<1>(0h0)
connect states[6].vc_sel.`3`[0], UInt<1>(0h0)
connect states[6].vc_sel.`3`[1], UInt<1>(0h0)
connect states[6].vc_sel.`3`[2], UInt<1>(0h0)
connect states[6].vc_sel.`3`[3], UInt<1>(0h0)
connect states[7].vc_sel.`0`[0], UInt<1>(0h0)
connect states[7].vc_sel.`0`[1], UInt<1>(0h0)
connect states[7].vc_sel.`0`[2], UInt<1>(0h0)
connect states[7].vc_sel.`0`[3], UInt<1>(0h0)
connect states[7].vc_sel.`0`[4], UInt<1>(0h0)
connect states[7].vc_sel.`0`[5], UInt<1>(0h0)
connect states[7].vc_sel.`0`[6], UInt<1>(0h0)
connect states[7].vc_sel.`0`[7], UInt<1>(0h0)
connect states[7].vc_sel.`3`[0], UInt<1>(0h0)
connect states[7].vc_sel.`3`[1], UInt<1>(0h0)
connect states[7].vc_sel.`3`[2], UInt<1>(0h0)
connect states[7].vc_sel.`3`[3], UInt<1>(0h0)
node _T_120 = asUInt(reset)
when _T_120 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0)
connect states[4].g, UInt<3>(0h0)
connect states[5].g, UInt<3>(0h0)
connect states[6].g, UInt<3>(0h0)
connect states[7].g, UInt<3>(0h0) | module InputUnit_66( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [7:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire vcalloc_vals_0; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [7:0] mask; // @[InputUnit.scala:250:21]
wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_0 ? 16'h100 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59]
assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_7 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_8 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_88 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_99
connect io_out_source_valid_0.clock, clock
connect io_out_source_valid_0.reset, reset
connect io_out_source_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_88( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_99 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_285 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_29
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_285( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_29 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFM_small_e11_s53 :
input clock : Clock
input reset : Reset
output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>}
inst divSqrtRecFNToRaw of DivSqrtRecFMToRaw_small_e11_s53
connect divSqrtRecFNToRaw.clock, clock
connect divSqrtRecFNToRaw.reset, reset
connect io.inReady, divSqrtRecFNToRaw.io.inReady
connect divSqrtRecFNToRaw.io.inValid, io.inValid
connect divSqrtRecFNToRaw.io.sqrtOp, io.sqrtOp
connect divSqrtRecFNToRaw.io.a, io.a
connect divSqrtRecFNToRaw.io.b, io.b
connect divSqrtRecFNToRaw.io.roundingMode, io.roundingMode
connect io.outValid_div, divSqrtRecFNToRaw.io.rawOutValid_div
connect io.outValid_sqrt, divSqrtRecFNToRaw.io.rawOutValid_sqrt
inst roundRawFNToRecFN of RoundRawFNToRecFN_e11_s53_1
connect roundRawFNToRecFN.io.invalidExc, divSqrtRecFNToRaw.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, divSqrtRecFNToRaw.io.infiniteExc
connect roundRawFNToRecFN.io.in.sig, divSqrtRecFNToRaw.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, divSqrtRecFNToRaw.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, divSqrtRecFNToRaw.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, divSqrtRecFNToRaw.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, divSqrtRecFNToRaw.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, divSqrtRecFNToRaw.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, divSqrtRecFNToRaw.io.roundingModeOut
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module DivSqrtRecFM_small_e11_s53( // @[DivSqrtRecFN_small.scala:468:5]
input clock, // @[DivSqrtRecFN_small.scala:468:5]
input reset, // @[DivSqrtRecFN_small.scala:468:5]
output io_inReady, // @[DivSqrtRecFN_small.scala:472:16]
input io_inValid, // @[DivSqrtRecFN_small.scala:472:16]
input io_sqrtOp, // @[DivSqrtRecFN_small.scala:472:16]
input [64:0] io_a, // @[DivSqrtRecFN_small.scala:472:16]
input [64:0] io_b, // @[DivSqrtRecFN_small.scala:472:16]
input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:472:16]
output io_outValid_div, // @[DivSqrtRecFN_small.scala:472:16]
output io_outValid_sqrt, // @[DivSqrtRecFN_small.scala:472:16]
output [64:0] io_out, // @[DivSqrtRecFN_small.scala:472:16]
output [4:0] io_exceptionFlags // @[DivSqrtRecFN_small.scala:472:16]
);
wire [2:0] _divSqrtRecFNToRaw_io_roundingModeOut; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_invalidExc; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_infiniteExc; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_rawOut_isNaN; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_rawOut_isInf; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_rawOut_isZero; // @[DivSqrtRecFN_small.scala:493:15]
wire _divSqrtRecFNToRaw_io_rawOut_sign; // @[DivSqrtRecFN_small.scala:493:15]
wire [12:0] _divSqrtRecFNToRaw_io_rawOut_sExp; // @[DivSqrtRecFN_small.scala:493:15]
wire [55:0] _divSqrtRecFNToRaw_io_rawOut_sig; // @[DivSqrtRecFN_small.scala:493:15]
wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:468:5]
wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:468:5]
wire [64:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:468:5]
wire [64:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:468:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:468:5]
wire io_detectTininess = 1'h1; // @[DivSqrtRecFN_small.scala:468:5, :472:16, :508:15]
wire io_inReady_0; // @[DivSqrtRecFN_small.scala:468:5]
wire io_outValid_div_0; // @[DivSqrtRecFN_small.scala:468:5]
wire io_outValid_sqrt_0; // @[DivSqrtRecFN_small.scala:468:5]
wire [64:0] io_out_0; // @[DivSqrtRecFN_small.scala:468:5]
wire [4:0] io_exceptionFlags_0; // @[DivSqrtRecFN_small.scala:468:5]
DivSqrtRecFMToRaw_small_e11_s53 divSqrtRecFNToRaw ( // @[DivSqrtRecFN_small.scala:493:15]
.clock (clock),
.reset (reset),
.io_inReady (io_inReady_0),
.io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:468:5]
.io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:468:5]
.io_a (io_a_0), // @[DivSqrtRecFN_small.scala:468:5]
.io_b (io_b_0), // @[DivSqrtRecFN_small.scala:468:5]
.io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:468:5]
.io_rawOutValid_div (io_outValid_div_0),
.io_rawOutValid_sqrt (io_outValid_sqrt_0),
.io_roundingModeOut (_divSqrtRecFNToRaw_io_roundingModeOut),
.io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc),
.io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc),
.io_rawOut_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN),
.io_rawOut_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf),
.io_rawOut_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero),
.io_rawOut_sign (_divSqrtRecFNToRaw_io_rawOut_sign),
.io_rawOut_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp),
.io_rawOut_sig (_divSqrtRecFNToRaw_io_rawOut_sig)
); // @[DivSqrtRecFN_small.scala:493:15]
RoundRawFNToRecFN_e11_s53_1 roundRawFNToRecFN ( // @[DivSqrtRecFN_small.scala:508:15]
.io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc), // @[DivSqrtRecFN_small.scala:493:15]
.io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_sign (_divSqrtRecFNToRaw_io_rawOut_sign), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp), // @[DivSqrtRecFN_small.scala:493:15]
.io_in_sig (_divSqrtRecFNToRaw_io_rawOut_sig), // @[DivSqrtRecFN_small.scala:493:15]
.io_roundingMode (_divSqrtRecFNToRaw_io_roundingModeOut), // @[DivSqrtRecFN_small.scala:493:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[DivSqrtRecFN_small.scala:508:15]
assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:468:5]
assign io_outValid_div = io_outValid_div_0; // @[DivSqrtRecFN_small.scala:468:5]
assign io_outValid_sqrt = io_outValid_sqrt_0; // @[DivSqrtRecFN_small.scala:468:5]
assign io_out = io_out_0; // @[DivSqrtRecFN_small.scala:468:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[DivSqrtRecFN_small.scala:468:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_249 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_249( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module PMAChecker_5 :
input clock : Clock
input reset : Reset
output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}}
node _legal_address_T = xor(io.paddr, UInt<1>(0h0))
node _legal_address_T_1 = cvt(_legal_address_T)
node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000)))
node _legal_address_T_3 = asSInt(_legal_address_T_2)
node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0)))
node _legal_address_T_5 = xor(io.paddr, UInt<13>(0h1000))
node _legal_address_T_6 = cvt(_legal_address_T_5)
node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000)))
node _legal_address_T_8 = asSInt(_legal_address_T_7)
node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0)))
node _legal_address_T_10 = xor(io.paddr, UInt<14>(0h3000))
node _legal_address_T_11 = cvt(_legal_address_T_10)
node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000)))
node _legal_address_T_13 = asSInt(_legal_address_T_12)
node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0)))
node _legal_address_T_15 = xor(io.paddr, UInt<17>(0h10000))
node _legal_address_T_16 = cvt(_legal_address_T_15)
node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000)))
node _legal_address_T_18 = asSInt(_legal_address_T_17)
node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0)))
node _legal_address_T_20 = xor(io.paddr, UInt<18>(0h20000))
node _legal_address_T_21 = cvt(_legal_address_T_20)
node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000)))
node _legal_address_T_23 = asSInt(_legal_address_T_22)
node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0)))
node _legal_address_T_25 = xor(io.paddr, UInt<18>(0h21000))
node _legal_address_T_26 = cvt(_legal_address_T_25)
node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000)))
node _legal_address_T_28 = asSInt(_legal_address_T_27)
node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0)))
node _legal_address_T_30 = xor(io.paddr, UInt<18>(0h22000))
node _legal_address_T_31 = cvt(_legal_address_T_30)
node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<13>(0h1000)))
node _legal_address_T_33 = asSInt(_legal_address_T_32)
node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0)))
node _legal_address_T_35 = xor(io.paddr, UInt<18>(0h23000))
node _legal_address_T_36 = cvt(_legal_address_T_35)
node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000)))
node _legal_address_T_38 = asSInt(_legal_address_T_37)
node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0)))
node _legal_address_T_40 = xor(io.paddr, UInt<18>(0h24000))
node _legal_address_T_41 = cvt(_legal_address_T_40)
node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<13>(0h1000)))
node _legal_address_T_43 = asSInt(_legal_address_T_42)
node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0)))
node _legal_address_T_45 = xor(io.paddr, UInt<21>(0h100000))
node _legal_address_T_46 = cvt(_legal_address_T_45)
node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<13>(0h1000)))
node _legal_address_T_48 = asSInt(_legal_address_T_47)
node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0)))
node _legal_address_T_50 = xor(io.paddr, UInt<21>(0h110000))
node _legal_address_T_51 = cvt(_legal_address_T_50)
node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000)))
node _legal_address_T_53 = asSInt(_legal_address_T_52)
node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0)))
node _legal_address_T_55 = xor(io.paddr, UInt<26>(0h2000000))
node _legal_address_T_56 = cvt(_legal_address_T_55)
node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<17>(0h10000)))
node _legal_address_T_58 = asSInt(_legal_address_T_57)
node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0)))
node _legal_address_T_60 = xor(io.paddr, UInt<26>(0h2010000))
node _legal_address_T_61 = cvt(_legal_address_T_60)
node _legal_address_T_62 = and(_legal_address_T_61, asSInt(UInt<13>(0h1000)))
node _legal_address_T_63 = asSInt(_legal_address_T_62)
node _legal_address_T_64 = eq(_legal_address_T_63, asSInt(UInt<1>(0h0)))
node _legal_address_T_65 = xor(io.paddr, UInt<28>(0h8000000))
node _legal_address_T_66 = cvt(_legal_address_T_65)
node _legal_address_T_67 = and(_legal_address_T_66, asSInt(UInt<17>(0h10000)))
node _legal_address_T_68 = asSInt(_legal_address_T_67)
node _legal_address_T_69 = eq(_legal_address_T_68, asSInt(UInt<1>(0h0)))
node _legal_address_T_70 = xor(io.paddr, UInt<28>(0hc000000))
node _legal_address_T_71 = cvt(_legal_address_T_70)
node _legal_address_T_72 = and(_legal_address_T_71, asSInt(UInt<27>(0h4000000)))
node _legal_address_T_73 = asSInt(_legal_address_T_72)
node _legal_address_T_74 = eq(_legal_address_T_73, asSInt(UInt<1>(0h0)))
node _legal_address_T_75 = xor(io.paddr, UInt<29>(0h10020000))
node _legal_address_T_76 = cvt(_legal_address_T_75)
node _legal_address_T_77 = and(_legal_address_T_76, asSInt(UInt<13>(0h1000)))
node _legal_address_T_78 = asSInt(_legal_address_T_77)
node _legal_address_T_79 = eq(_legal_address_T_78, asSInt(UInt<1>(0h0)))
node _legal_address_T_80 = xor(io.paddr, UInt<32>(0h80000000))
node _legal_address_T_81 = cvt(_legal_address_T_80)
node _legal_address_T_82 = and(_legal_address_T_81, asSInt(UInt<29>(0h10000000)))
node _legal_address_T_83 = asSInt(_legal_address_T_82)
node _legal_address_T_84 = eq(_legal_address_T_83, asSInt(UInt<1>(0h0)))
wire _legal_address_WIRE : UInt<1>[17]
connect _legal_address_WIRE[0], _legal_address_T_4
connect _legal_address_WIRE[1], _legal_address_T_9
connect _legal_address_WIRE[2], _legal_address_T_14
connect _legal_address_WIRE[3], _legal_address_T_19
connect _legal_address_WIRE[4], _legal_address_T_24
connect _legal_address_WIRE[5], _legal_address_T_29
connect _legal_address_WIRE[6], _legal_address_T_34
connect _legal_address_WIRE[7], _legal_address_T_39
connect _legal_address_WIRE[8], _legal_address_T_44
connect _legal_address_WIRE[9], _legal_address_T_49
connect _legal_address_WIRE[10], _legal_address_T_54
connect _legal_address_WIRE[11], _legal_address_T_59
connect _legal_address_WIRE[12], _legal_address_T_64
connect _legal_address_WIRE[13], _legal_address_T_69
connect _legal_address_WIRE[14], _legal_address_T_74
connect _legal_address_WIRE[15], _legal_address_T_79
connect _legal_address_WIRE[16], _legal_address_T_84
node _legal_address_T_85 = or(_legal_address_WIRE[0], _legal_address_WIRE[1])
node _legal_address_T_86 = or(_legal_address_T_85, _legal_address_WIRE[2])
node _legal_address_T_87 = or(_legal_address_T_86, _legal_address_WIRE[3])
node _legal_address_T_88 = or(_legal_address_T_87, _legal_address_WIRE[4])
node _legal_address_T_89 = or(_legal_address_T_88, _legal_address_WIRE[5])
node _legal_address_T_90 = or(_legal_address_T_89, _legal_address_WIRE[6])
node _legal_address_T_91 = or(_legal_address_T_90, _legal_address_WIRE[7])
node _legal_address_T_92 = or(_legal_address_T_91, _legal_address_WIRE[8])
node _legal_address_T_93 = or(_legal_address_T_92, _legal_address_WIRE[9])
node _legal_address_T_94 = or(_legal_address_T_93, _legal_address_WIRE[10])
node _legal_address_T_95 = or(_legal_address_T_94, _legal_address_WIRE[11])
node _legal_address_T_96 = or(_legal_address_T_95, _legal_address_WIRE[12])
node _legal_address_T_97 = or(_legal_address_T_96, _legal_address_WIRE[13])
node _legal_address_T_98 = or(_legal_address_T_97, _legal_address_WIRE[14])
node _legal_address_T_99 = or(_legal_address_T_98, _legal_address_WIRE[15])
node legal_address = or(_legal_address_T_99, _legal_address_WIRE[16])
node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T)
node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<33>(0h8c020000)))
node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2)
node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_5 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_cacheable_T_6 = cvt(_io_resp_cacheable_T_5)
node _io_resp_cacheable_T_7 = and(_io_resp_cacheable_T_6, asSInt(UInt<33>(0h8c031000)))
node _io_resp_cacheable_T_8 = asSInt(_io_resp_cacheable_T_7)
node _io_resp_cacheable_T_9 = eq(_io_resp_cacheable_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_10 = xor(io.paddr, UInt<18>(0h20000))
node _io_resp_cacheable_T_11 = cvt(_io_resp_cacheable_T_10)
node _io_resp_cacheable_T_12 = and(_io_resp_cacheable_T_11, asSInt(UInt<33>(0h8c030000)))
node _io_resp_cacheable_T_13 = asSInt(_io_resp_cacheable_T_12)
node _io_resp_cacheable_T_14 = eq(_io_resp_cacheable_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_15 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_cacheable_T_16 = cvt(_io_resp_cacheable_T_15)
node _io_resp_cacheable_T_17 = and(_io_resp_cacheable_T_16, asSInt(UInt<33>(0h8c000000)))
node _io_resp_cacheable_T_18 = asSInt(_io_resp_cacheable_T_17)
node _io_resp_cacheable_T_19 = eq(_io_resp_cacheable_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_20 = or(_io_resp_cacheable_T_4, _io_resp_cacheable_T_9)
node _io_resp_cacheable_T_21 = or(_io_resp_cacheable_T_20, _io_resp_cacheable_T_14)
node _io_resp_cacheable_T_22 = or(_io_resp_cacheable_T_21, _io_resp_cacheable_T_19)
node _io_resp_cacheable_T_23 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_cacheable_T_24 = cvt(_io_resp_cacheable_T_23)
node _io_resp_cacheable_T_25 = and(_io_resp_cacheable_T_24, asSInt(UInt<33>(0h8c030000)))
node _io_resp_cacheable_T_26 = asSInt(_io_resp_cacheable_T_25)
node _io_resp_cacheable_T_27 = eq(_io_resp_cacheable_T_26, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_28 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_cacheable_T_29 = cvt(_io_resp_cacheable_T_28)
node _io_resp_cacheable_T_30 = and(_io_resp_cacheable_T_29, asSInt(UInt<33>(0h80000000)))
node _io_resp_cacheable_T_31 = asSInt(_io_resp_cacheable_T_30)
node _io_resp_cacheable_T_32 = eq(_io_resp_cacheable_T_31, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_33 = or(_io_resp_cacheable_T_27, _io_resp_cacheable_T_32)
node _io_resp_cacheable_T_34 = mux(_io_resp_cacheable_T_22, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_cacheable_T_35 = mux(_io_resp_cacheable_T_33, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_cacheable_T_36 = or(_io_resp_cacheable_T_34, _io_resp_cacheable_T_35)
wire _io_resp_cacheable_WIRE : UInt<1>
connect _io_resp_cacheable_WIRE, _io_resp_cacheable_T_36
node _io_resp_cacheable_T_37 = and(legal_address, _io_resp_cacheable_WIRE)
connect io.resp.cacheable, _io_resp_cacheable_T_37
node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_r_T_1 = cvt(_io_resp_r_T)
node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0)))
node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2)
node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1))
connect io.resp.r, _io_resp_r_T_5
node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_w_T_1 = cvt(_io_resp_w_T)
node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0hfffd8000)))
node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2)
node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_w_T_6 = cvt(_io_resp_w_T_5)
node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0hfffe9000)))
node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7)
node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_10 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_w_T_11 = cvt(_io_resp_w_T_10)
node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0hffff0000)))
node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12)
node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_15 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_w_T_16 = cvt(_io_resp_w_T_15)
node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0hffff9000)))
node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17)
node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_w_T_21 = cvt(_io_resp_w_T_20)
node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0hffff0000)))
node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22)
node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_25 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_w_T_26 = cvt(_io_resp_w_T_25)
node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0hfc000000)))
node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27)
node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_30 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_w_T_31 = cvt(_io_resp_w_T_30)
node _io_resp_w_T_32 = and(_io_resp_w_T_31, asSInt(UInt<33>(0hffff9000)))
node _io_resp_w_T_33 = asSInt(_io_resp_w_T_32)
node _io_resp_w_T_34 = eq(_io_resp_w_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_35 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_w_T_36 = cvt(_io_resp_w_T_35)
node _io_resp_w_T_37 = and(_io_resp_w_T_36, asSInt(UInt<33>(0hf0000000)))
node _io_resp_w_T_38 = asSInt(_io_resp_w_T_37)
node _io_resp_w_T_39 = eq(_io_resp_w_T_38, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_40 = or(_io_resp_w_T_4, _io_resp_w_T_9)
node _io_resp_w_T_41 = or(_io_resp_w_T_40, _io_resp_w_T_14)
node _io_resp_w_T_42 = or(_io_resp_w_T_41, _io_resp_w_T_19)
node _io_resp_w_T_43 = or(_io_resp_w_T_42, _io_resp_w_T_24)
node _io_resp_w_T_44 = or(_io_resp_w_T_43, _io_resp_w_T_29)
node _io_resp_w_T_45 = or(_io_resp_w_T_44, _io_resp_w_T_34)
node _io_resp_w_T_46 = or(_io_resp_w_T_45, _io_resp_w_T_39)
node _io_resp_w_T_47 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_w_T_48 = cvt(_io_resp_w_T_47)
node _io_resp_w_T_49 = and(_io_resp_w_T_48, asSInt(UInt<33>(0hffff0000)))
node _io_resp_w_T_50 = asSInt(_io_resp_w_T_49)
node _io_resp_w_T_51 = eq(_io_resp_w_T_50, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_52 = mux(_io_resp_w_T_46, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_w_T_53 = mux(_io_resp_w_T_51, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_w_T_54 = or(_io_resp_w_T_52, _io_resp_w_T_53)
wire _io_resp_w_WIRE : UInt<1>
connect _io_resp_w_WIRE, _io_resp_w_T_54
node _io_resp_w_T_55 = and(legal_address, _io_resp_w_WIRE)
connect io.resp.w, _io_resp_w_T_55
node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_pp_T_1 = cvt(_io_resp_pp_T)
node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0hfffd8000)))
node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2)
node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5)
node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0hfffe9000)))
node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7)
node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_10 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10)
node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0hffff0000)))
node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12)
node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_15 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15)
node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0hffff9000)))
node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17)
node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20)
node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0hffff0000)))
node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22)
node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_25 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25)
node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0hfc000000)))
node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27)
node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_30 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_pp_T_31 = cvt(_io_resp_pp_T_30)
node _io_resp_pp_T_32 = and(_io_resp_pp_T_31, asSInt(UInt<33>(0hffff9000)))
node _io_resp_pp_T_33 = asSInt(_io_resp_pp_T_32)
node _io_resp_pp_T_34 = eq(_io_resp_pp_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_35 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_pp_T_36 = cvt(_io_resp_pp_T_35)
node _io_resp_pp_T_37 = and(_io_resp_pp_T_36, asSInt(UInt<33>(0hf0000000)))
node _io_resp_pp_T_38 = asSInt(_io_resp_pp_T_37)
node _io_resp_pp_T_39 = eq(_io_resp_pp_T_38, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_40 = or(_io_resp_pp_T_4, _io_resp_pp_T_9)
node _io_resp_pp_T_41 = or(_io_resp_pp_T_40, _io_resp_pp_T_14)
node _io_resp_pp_T_42 = or(_io_resp_pp_T_41, _io_resp_pp_T_19)
node _io_resp_pp_T_43 = or(_io_resp_pp_T_42, _io_resp_pp_T_24)
node _io_resp_pp_T_44 = or(_io_resp_pp_T_43, _io_resp_pp_T_29)
node _io_resp_pp_T_45 = or(_io_resp_pp_T_44, _io_resp_pp_T_34)
node _io_resp_pp_T_46 = or(_io_resp_pp_T_45, _io_resp_pp_T_39)
node _io_resp_pp_T_47 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_pp_T_48 = cvt(_io_resp_pp_T_47)
node _io_resp_pp_T_49 = and(_io_resp_pp_T_48, asSInt(UInt<33>(0hffff0000)))
node _io_resp_pp_T_50 = asSInt(_io_resp_pp_T_49)
node _io_resp_pp_T_51 = eq(_io_resp_pp_T_50, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_52 = mux(_io_resp_pp_T_46, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_pp_T_53 = mux(_io_resp_pp_T_51, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_pp_T_54 = or(_io_resp_pp_T_52, _io_resp_pp_T_53)
wire _io_resp_pp_WIRE : UInt<1>
connect _io_resp_pp_WIRE, _io_resp_pp_T_54
node _io_resp_pp_T_55 = and(legal_address, _io_resp_pp_WIRE)
connect io.resp.pp, _io_resp_pp_T_55
node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_al_T_1 = cvt(_io_resp_al_T)
node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0hfffd8000)))
node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2)
node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_al_T_6 = cvt(_io_resp_al_T_5)
node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0hfffe9000)))
node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7)
node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_10 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_al_T_11 = cvt(_io_resp_al_T_10)
node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0hffff0000)))
node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12)
node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_15 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_al_T_16 = cvt(_io_resp_al_T_15)
node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0hffff9000)))
node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17)
node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_al_T_21 = cvt(_io_resp_al_T_20)
node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0hffff0000)))
node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22)
node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_25 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_al_T_26 = cvt(_io_resp_al_T_25)
node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0hfc000000)))
node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27)
node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_30 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_al_T_31 = cvt(_io_resp_al_T_30)
node _io_resp_al_T_32 = and(_io_resp_al_T_31, asSInt(UInt<33>(0hffff9000)))
node _io_resp_al_T_33 = asSInt(_io_resp_al_T_32)
node _io_resp_al_T_34 = eq(_io_resp_al_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_35 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_al_T_36 = cvt(_io_resp_al_T_35)
node _io_resp_al_T_37 = and(_io_resp_al_T_36, asSInt(UInt<33>(0hf0000000)))
node _io_resp_al_T_38 = asSInt(_io_resp_al_T_37)
node _io_resp_al_T_39 = eq(_io_resp_al_T_38, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_40 = or(_io_resp_al_T_4, _io_resp_al_T_9)
node _io_resp_al_T_41 = or(_io_resp_al_T_40, _io_resp_al_T_14)
node _io_resp_al_T_42 = or(_io_resp_al_T_41, _io_resp_al_T_19)
node _io_resp_al_T_43 = or(_io_resp_al_T_42, _io_resp_al_T_24)
node _io_resp_al_T_44 = or(_io_resp_al_T_43, _io_resp_al_T_29)
node _io_resp_al_T_45 = or(_io_resp_al_T_44, _io_resp_al_T_34)
node _io_resp_al_T_46 = or(_io_resp_al_T_45, _io_resp_al_T_39)
node _io_resp_al_T_47 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_al_T_48 = cvt(_io_resp_al_T_47)
node _io_resp_al_T_49 = and(_io_resp_al_T_48, asSInt(UInt<33>(0hffff0000)))
node _io_resp_al_T_50 = asSInt(_io_resp_al_T_49)
node _io_resp_al_T_51 = eq(_io_resp_al_T_50, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_52 = mux(_io_resp_al_T_46, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_al_T_53 = mux(_io_resp_al_T_51, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_al_T_54 = or(_io_resp_al_T_52, _io_resp_al_T_53)
wire _io_resp_al_WIRE : UInt<1>
connect _io_resp_al_WIRE, _io_resp_al_T_54
node _io_resp_al_T_55 = and(legal_address, _io_resp_al_WIRE)
connect io.resp.al, _io_resp_al_T_55
node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_aa_T_1 = cvt(_io_resp_aa_T)
node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0hfffd8000)))
node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2)
node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5)
node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0hfffe9000)))
node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7)
node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_10 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10)
node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0hffff0000)))
node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12)
node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_15 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15)
node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0hffff9000)))
node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17)
node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20)
node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0hffff0000)))
node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22)
node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_25 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25)
node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0hfc000000)))
node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27)
node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_30 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_aa_T_31 = cvt(_io_resp_aa_T_30)
node _io_resp_aa_T_32 = and(_io_resp_aa_T_31, asSInt(UInt<33>(0hffff9000)))
node _io_resp_aa_T_33 = asSInt(_io_resp_aa_T_32)
node _io_resp_aa_T_34 = eq(_io_resp_aa_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_35 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_aa_T_36 = cvt(_io_resp_aa_T_35)
node _io_resp_aa_T_37 = and(_io_resp_aa_T_36, asSInt(UInt<33>(0hf0000000)))
node _io_resp_aa_T_38 = asSInt(_io_resp_aa_T_37)
node _io_resp_aa_T_39 = eq(_io_resp_aa_T_38, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_40 = or(_io_resp_aa_T_4, _io_resp_aa_T_9)
node _io_resp_aa_T_41 = or(_io_resp_aa_T_40, _io_resp_aa_T_14)
node _io_resp_aa_T_42 = or(_io_resp_aa_T_41, _io_resp_aa_T_19)
node _io_resp_aa_T_43 = or(_io_resp_aa_T_42, _io_resp_aa_T_24)
node _io_resp_aa_T_44 = or(_io_resp_aa_T_43, _io_resp_aa_T_29)
node _io_resp_aa_T_45 = or(_io_resp_aa_T_44, _io_resp_aa_T_34)
node _io_resp_aa_T_46 = or(_io_resp_aa_T_45, _io_resp_aa_T_39)
node _io_resp_aa_T_47 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_aa_T_48 = cvt(_io_resp_aa_T_47)
node _io_resp_aa_T_49 = and(_io_resp_aa_T_48, asSInt(UInt<33>(0hffff0000)))
node _io_resp_aa_T_50 = asSInt(_io_resp_aa_T_49)
node _io_resp_aa_T_51 = eq(_io_resp_aa_T_50, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_52 = mux(_io_resp_aa_T_46, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_aa_T_53 = mux(_io_resp_aa_T_51, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_aa_T_54 = or(_io_resp_aa_T_52, _io_resp_aa_T_53)
wire _io_resp_aa_WIRE : UInt<1>
connect _io_resp_aa_WIRE, _io_resp_aa_T_54
node _io_resp_aa_T_55 = and(legal_address, _io_resp_aa_WIRE)
connect io.resp.aa, _io_resp_aa_T_55
node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_x_T_1 = cvt(_io_resp_x_T)
node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2)
node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_5 = xor(io.paddr, UInt<14>(0h3000))
node _io_resp_x_T_6 = cvt(_io_resp_x_T_5)
node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7)
node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_10 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_x_T_11 = cvt(_io_resp_x_T_10)
node _io_resp_x_T_12 = and(_io_resp_x_T_11, asSInt(UInt<33>(0hffff0000)))
node _io_resp_x_T_13 = asSInt(_io_resp_x_T_12)
node _io_resp_x_T_14 = eq(_io_resp_x_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_x_T_16 = cvt(_io_resp_x_T_15)
node _io_resp_x_T_17 = and(_io_resp_x_T_16, asSInt(UInt<33>(0hffff0000)))
node _io_resp_x_T_18 = asSInt(_io_resp_x_T_17)
node _io_resp_x_T_19 = eq(_io_resp_x_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_20 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_x_T_21 = cvt(_io_resp_x_T_20)
node _io_resp_x_T_22 = and(_io_resp_x_T_21, asSInt(UInt<33>(0hf0000000)))
node _io_resp_x_T_23 = asSInt(_io_resp_x_T_22)
node _io_resp_x_T_24 = eq(_io_resp_x_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_25 = or(_io_resp_x_T_4, _io_resp_x_T_9)
node _io_resp_x_T_26 = or(_io_resp_x_T_25, _io_resp_x_T_14)
node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_19)
node _io_resp_x_T_28 = or(_io_resp_x_T_27, _io_resp_x_T_24)
node _io_resp_x_T_29 = xor(io.paddr, UInt<13>(0h1000))
node _io_resp_x_T_30 = cvt(_io_resp_x_T_29)
node _io_resp_x_T_31 = and(_io_resp_x_T_30, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_32 = asSInt(_io_resp_x_T_31)
node _io_resp_x_T_33 = eq(_io_resp_x_T_32, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_34 = xor(io.paddr, UInt<18>(0h20000))
node _io_resp_x_T_35 = cvt(_io_resp_x_T_34)
node _io_resp_x_T_36 = and(_io_resp_x_T_35, asSInt(UInt<33>(0hffffc000)))
node _io_resp_x_T_37 = asSInt(_io_resp_x_T_36)
node _io_resp_x_T_38 = eq(_io_resp_x_T_37, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_39 = xor(io.paddr, UInt<18>(0h24000))
node _io_resp_x_T_40 = cvt(_io_resp_x_T_39)
node _io_resp_x_T_41 = and(_io_resp_x_T_40, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_42 = asSInt(_io_resp_x_T_41)
node _io_resp_x_T_43 = eq(_io_resp_x_T_42, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_44 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_x_T_45 = cvt(_io_resp_x_T_44)
node _io_resp_x_T_46 = and(_io_resp_x_T_45, asSInt(UInt<33>(0hfffef000)))
node _io_resp_x_T_47 = asSInt(_io_resp_x_T_46)
node _io_resp_x_T_48 = eq(_io_resp_x_T_47, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_49 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_x_T_50 = cvt(_io_resp_x_T_49)
node _io_resp_x_T_51 = and(_io_resp_x_T_50, asSInt(UInt<33>(0hffff0000)))
node _io_resp_x_T_52 = asSInt(_io_resp_x_T_51)
node _io_resp_x_T_53 = eq(_io_resp_x_T_52, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_54 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_x_T_55 = cvt(_io_resp_x_T_54)
node _io_resp_x_T_56 = and(_io_resp_x_T_55, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_57 = asSInt(_io_resp_x_T_56)
node _io_resp_x_T_58 = eq(_io_resp_x_T_57, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_59 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_x_T_60 = cvt(_io_resp_x_T_59)
node _io_resp_x_T_61 = and(_io_resp_x_T_60, asSInt(UInt<33>(0hfc000000)))
node _io_resp_x_T_62 = asSInt(_io_resp_x_T_61)
node _io_resp_x_T_63 = eq(_io_resp_x_T_62, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_64 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_x_T_65 = cvt(_io_resp_x_T_64)
node _io_resp_x_T_66 = and(_io_resp_x_T_65, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_67 = asSInt(_io_resp_x_T_66)
node _io_resp_x_T_68 = eq(_io_resp_x_T_67, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_69 = or(_io_resp_x_T_33, _io_resp_x_T_38)
node _io_resp_x_T_70 = or(_io_resp_x_T_69, _io_resp_x_T_43)
node _io_resp_x_T_71 = or(_io_resp_x_T_70, _io_resp_x_T_48)
node _io_resp_x_T_72 = or(_io_resp_x_T_71, _io_resp_x_T_53)
node _io_resp_x_T_73 = or(_io_resp_x_T_72, _io_resp_x_T_58)
node _io_resp_x_T_74 = or(_io_resp_x_T_73, _io_resp_x_T_63)
node _io_resp_x_T_75 = or(_io_resp_x_T_74, _io_resp_x_T_68)
node _io_resp_x_T_76 = mux(_io_resp_x_T_28, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_x_T_77 = mux(_io_resp_x_T_75, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_x_T_78 = or(_io_resp_x_T_76, _io_resp_x_T_77)
wire _io_resp_x_WIRE : UInt<1>
connect _io_resp_x_WIRE, _io_resp_x_T_78
node _io_resp_x_T_79 = and(legal_address, _io_resp_x_WIRE)
connect io.resp.x, _io_resp_x_T_79
node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_eff_T_1 = cvt(_io_resp_eff_T)
node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0hffffa000)))
node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2)
node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_5 = xor(io.paddr, UInt<18>(0h20000))
node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5)
node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0hffff8000)))
node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7)
node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_10 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10)
node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0hfffeb000)))
node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12)
node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_15 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15)
node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0hffff0000)))
node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17)
node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_20 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20)
node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0hffffb000)))
node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22)
node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_25 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25)
node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0hfc000000)))
node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27)
node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_30 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_eff_T_31 = cvt(_io_resp_eff_T_30)
node _io_resp_eff_T_32 = and(_io_resp_eff_T_31, asSInt(UInt<33>(0hffffb000)))
node _io_resp_eff_T_33 = asSInt(_io_resp_eff_T_32)
node _io_resp_eff_T_34 = eq(_io_resp_eff_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_35 = or(_io_resp_eff_T_4, _io_resp_eff_T_9)
node _io_resp_eff_T_36 = or(_io_resp_eff_T_35, _io_resp_eff_T_14)
node _io_resp_eff_T_37 = or(_io_resp_eff_T_36, _io_resp_eff_T_19)
node _io_resp_eff_T_38 = or(_io_resp_eff_T_37, _io_resp_eff_T_24)
node _io_resp_eff_T_39 = or(_io_resp_eff_T_38, _io_resp_eff_T_29)
node _io_resp_eff_T_40 = or(_io_resp_eff_T_39, _io_resp_eff_T_34)
node _io_resp_eff_T_41 = xor(io.paddr, UInt<14>(0h3000))
node _io_resp_eff_T_42 = cvt(_io_resp_eff_T_41)
node _io_resp_eff_T_43 = and(_io_resp_eff_T_42, asSInt(UInt<33>(0hffffb000)))
node _io_resp_eff_T_44 = asSInt(_io_resp_eff_T_43)
node _io_resp_eff_T_45 = eq(_io_resp_eff_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_46 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_eff_T_47 = cvt(_io_resp_eff_T_46)
node _io_resp_eff_T_48 = and(_io_resp_eff_T_47, asSInt(UInt<33>(0hffff0000)))
node _io_resp_eff_T_49 = asSInt(_io_resp_eff_T_48)
node _io_resp_eff_T_50 = eq(_io_resp_eff_T_49, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_51 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_eff_T_52 = cvt(_io_resp_eff_T_51)
node _io_resp_eff_T_53 = and(_io_resp_eff_T_52, asSInt(UInt<33>(0hffff0000)))
node _io_resp_eff_T_54 = asSInt(_io_resp_eff_T_53)
node _io_resp_eff_T_55 = eq(_io_resp_eff_T_54, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_56 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_eff_T_57 = cvt(_io_resp_eff_T_56)
node _io_resp_eff_T_58 = and(_io_resp_eff_T_57, asSInt(UInt<33>(0hf0000000)))
node _io_resp_eff_T_59 = asSInt(_io_resp_eff_T_58)
node _io_resp_eff_T_60 = eq(_io_resp_eff_T_59, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_61 = or(_io_resp_eff_T_45, _io_resp_eff_T_50)
node _io_resp_eff_T_62 = or(_io_resp_eff_T_61, _io_resp_eff_T_55)
node _io_resp_eff_T_63 = or(_io_resp_eff_T_62, _io_resp_eff_T_60)
node _io_resp_eff_T_64 = mux(_io_resp_eff_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_eff_T_65 = mux(_io_resp_eff_T_63, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_eff_T_66 = or(_io_resp_eff_T_64, _io_resp_eff_T_65)
wire _io_resp_eff_WIRE : UInt<1>
connect _io_resp_eff_WIRE, _io_resp_eff_T_66
node _io_resp_eff_T_67 = and(legal_address, _io_resp_eff_WIRE)
connect io.resp.eff, _io_resp_eff_T_67 | module PMAChecker_5( // @[PMA.scala:18:7]
input clock, // @[PMA.scala:18:7]
input reset, // @[PMA.scala:18:7]
input [39:0] io_paddr, // @[PMA.scala:19:14]
output io_resp_cacheable, // @[PMA.scala:19:14]
output io_resp_r, // @[PMA.scala:19:14]
output io_resp_w, // @[PMA.scala:19:14]
output io_resp_pp, // @[PMA.scala:19:14]
output io_resp_al, // @[PMA.scala:19:14]
output io_resp_aa, // @[PMA.scala:19:14]
output io_resp_x, // @[PMA.scala:19:14]
output io_resp_eff // @[PMA.scala:19:14]
);
wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7]
wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46]
wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46]
wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _io_resp_cacheable_T_34 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_w_T_53 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_pp_T_53 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_al_T_53 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_aa_T_53 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_x_T_77 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_eff_T_65 = 1'h0; // @[Mux.scala:30:73]
wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_cacheable_T_37; // @[PMA.scala:39:19]
wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_r_T_5; // @[PMA.scala:39:19]
wire _io_resp_w_T_55; // @[PMA.scala:39:19]
wire _io_resp_pp_T_55; // @[PMA.scala:39:19]
wire _io_resp_al_T_55; // @[PMA.scala:39:19]
wire _io_resp_aa_T_55; // @[PMA.scala:39:19]
wire _io_resp_x_T_79; // @[PMA.scala:39:19]
wire _io_resp_eff_T_67; // @[PMA.scala:39:19]
wire io_resp_cacheable_0; // @[PMA.scala:18:7]
wire io_resp_r_0; // @[PMA.scala:18:7]
wire io_resp_w_0; // @[PMA.scala:18:7]
wire io_resp_pp_0; // @[PMA.scala:18:7]
wire io_resp_al_0; // @[PMA.scala:18:7]
wire io_resp_aa_0; // @[PMA.scala:18:7]
wire io_resp_x_0; // @[PMA.scala:18:7]
wire io_resp_eff_0; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46]
wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40]
wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31]
assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31]
assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46]
wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40]
wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31]
assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31]
assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_41; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_41 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46]
wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40]
wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31]
assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_47; // @[Parameters.scala:137:31]
assign _io_resp_w_T_47 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_47; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_47 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_47; // @[Parameters.scala:137:31]
assign _io_resp_al_T_47 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_47; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_47 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31]
assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_46; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_46 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46]
wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40]
wire [39:0] _GEN_2 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h20000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31]
assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_10 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31]
assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46]
wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_25 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h21000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46]
wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_30 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h22000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46]
wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_35 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h23000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46]
wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40]
wire [39:0] _GEN_3 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h24000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31]
assign _legal_address_T_40 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31]
assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46]
wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40]
wire [39:0] _GEN_4 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31]
assign _legal_address_T_45 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31]
assign _io_resp_w_T_5 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_5 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31]
assign _io_resp_al_T_5 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_5 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31]
assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46]
wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_50 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46]
wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40]
wire [39:0] _GEN_5 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31]
assign _legal_address_T_55 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31]
assign _io_resp_w_T_10 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_10 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31]
assign _io_resp_al_T_10 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_10 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31]
assign _io_resp_x_T_49 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46]
wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40]
wire [39:0] _GEN_6 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_60; // @[Parameters.scala:137:31]
assign _legal_address_T_60 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31]
assign _io_resp_w_T_15 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_15 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31]
assign _io_resp_al_T_15 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_15 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31]
assign _io_resp_x_T_54 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_61 = {1'h0, _legal_address_T_60}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_62 = _legal_address_T_61 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_63 = _legal_address_T_62; // @[Parameters.scala:137:46]
wire _legal_address_T_64 = _legal_address_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_12 = _legal_address_T_64; // @[Parameters.scala:612:40]
wire [39:0] _GEN_7 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_65; // @[Parameters.scala:137:31]
assign _legal_address_T_65 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_23; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_23 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31]
assign _io_resp_w_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31]
assign _io_resp_al_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31]
assign _io_resp_x_T_15 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_51; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_51 = _GEN_7; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_66 = {1'h0, _legal_address_T_65}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_67 = _legal_address_T_66 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_68 = _legal_address_T_67; // @[Parameters.scala:137:46]
wire _legal_address_T_69 = _legal_address_T_68 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_13 = _legal_address_T_69; // @[Parameters.scala:612:40]
wire [39:0] _GEN_8 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_70; // @[Parameters.scala:137:31]
assign _legal_address_T_70 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_15; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_15 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31]
assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31]
assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_59; // @[Parameters.scala:137:31]
assign _io_resp_x_T_59 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_71 = {1'h0, _legal_address_T_70}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_72 = _legal_address_T_71 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_73 = _legal_address_T_72; // @[Parameters.scala:137:46]
wire _legal_address_T_74 = _legal_address_T_73 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_14 = _legal_address_T_74; // @[Parameters.scala:612:40]
wire [39:0] _GEN_9 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_75; // @[Parameters.scala:137:31]
assign _legal_address_T_75 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31]
assign _io_resp_w_T_30 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_30 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31]
assign _io_resp_al_T_30 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_30 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_64; // @[Parameters.scala:137:31]
assign _io_resp_x_T_64 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_30; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_30 = _GEN_9; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_76 = {1'h0, _legal_address_T_75}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_77 = _legal_address_T_76 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_78 = _legal_address_T_77; // @[Parameters.scala:137:46]
wire _legal_address_T_79 = _legal_address_T_78 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_15 = _legal_address_T_79; // @[Parameters.scala:612:40]
wire [39:0] _GEN_10 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_80; // @[Parameters.scala:137:31]
assign _legal_address_T_80 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_28; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_28 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_35; // @[Parameters.scala:137:31]
assign _io_resp_w_T_35 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_35; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_35 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_35; // @[Parameters.scala:137:31]
assign _io_resp_al_T_35 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_35; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_35 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31]
assign _io_resp_x_T_20 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_56; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_56 = _GEN_10; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_81 = {1'h0, _legal_address_T_80}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_82 = _legal_address_T_81 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_83 = _legal_address_T_82; // @[Parameters.scala:137:46]
wire _legal_address_T_84 = _legal_address_T_83 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_16 = _legal_address_T_84; // @[Parameters.scala:612:40]
wire _legal_address_T_85 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40]
wire _legal_address_T_86 = _legal_address_T_85 | _legal_address_WIRE_2; // @[Parameters.scala:612:40]
wire _legal_address_T_87 = _legal_address_T_86 | _legal_address_WIRE_3; // @[Parameters.scala:612:40]
wire _legal_address_T_88 = _legal_address_T_87 | _legal_address_WIRE_4; // @[Parameters.scala:612:40]
wire _legal_address_T_89 = _legal_address_T_88 | _legal_address_WIRE_5; // @[Parameters.scala:612:40]
wire _legal_address_T_90 = _legal_address_T_89 | _legal_address_WIRE_6; // @[Parameters.scala:612:40]
wire _legal_address_T_91 = _legal_address_T_90 | _legal_address_WIRE_7; // @[Parameters.scala:612:40]
wire _legal_address_T_92 = _legal_address_T_91 | _legal_address_WIRE_8; // @[Parameters.scala:612:40]
wire _legal_address_T_93 = _legal_address_T_92 | _legal_address_WIRE_9; // @[Parameters.scala:612:40]
wire _legal_address_T_94 = _legal_address_T_93 | _legal_address_WIRE_10; // @[Parameters.scala:612:40]
wire _legal_address_T_95 = _legal_address_T_94 | _legal_address_WIRE_11; // @[Parameters.scala:612:40]
wire _legal_address_T_96 = _legal_address_T_95 | _legal_address_WIRE_12; // @[Parameters.scala:612:40]
wire _legal_address_T_97 = _legal_address_T_96 | _legal_address_WIRE_13; // @[Parameters.scala:612:40]
wire _legal_address_T_98 = _legal_address_T_97 | _legal_address_WIRE_14; // @[Parameters.scala:612:40]
wire _legal_address_T_99 = _legal_address_T_98 | _legal_address_WIRE_15; // @[Parameters.scala:612:40]
wire legal_address = _legal_address_T_99 | _legal_address_WIRE_16; // @[Parameters.scala:612:40]
assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19]
wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C020000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C031000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C030000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_16 = {1'h0, _io_resp_cacheable_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_17 = _io_resp_cacheable_T_16 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_18 = _io_resp_cacheable_T_17; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_20 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_22 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_19; // @[Parameters.scala:629:89]
wire [40:0] _io_resp_cacheable_T_24 = {1'h0, _io_resp_cacheable_T_23}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24 & 41'h8C030000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_26 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_29 = {1'h0, _io_resp_cacheable_T_28}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_31 = _io_resp_cacheable_T_30; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_32 = _io_resp_cacheable_T_31 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_33 = _io_resp_cacheable_T_27 | _io_resp_cacheable_T_32; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_35 = _io_resp_cacheable_T_33; // @[Mux.scala:30:73]
wire _io_resp_cacheable_T_36 = _io_resp_cacheable_T_35; // @[Mux.scala:30:73]
wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_36; // @[Mux.scala:30:73]
assign _io_resp_cacheable_T_37 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_37; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}]
assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46]
wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46]
wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46]
wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46]
wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46]
wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46]
wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46]
wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_36 = {1'h0, _io_resp_w_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_37 = _io_resp_w_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_38 = _io_resp_w_T_37; // @[Parameters.scala:137:46]
wire _io_resp_w_T_39 = _io_resp_w_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_40 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89]
wire _io_resp_w_T_41 = _io_resp_w_T_40 | _io_resp_w_T_14; // @[Parameters.scala:629:89]
wire _io_resp_w_T_42 = _io_resp_w_T_41 | _io_resp_w_T_19; // @[Parameters.scala:629:89]
wire _io_resp_w_T_43 = _io_resp_w_T_42 | _io_resp_w_T_24; // @[Parameters.scala:629:89]
wire _io_resp_w_T_44 = _io_resp_w_T_43 | _io_resp_w_T_29; // @[Parameters.scala:629:89]
wire _io_resp_w_T_45 = _io_resp_w_T_44 | _io_resp_w_T_34; // @[Parameters.scala:629:89]
wire _io_resp_w_T_46 = _io_resp_w_T_45 | _io_resp_w_T_39; // @[Parameters.scala:629:89]
wire _io_resp_w_T_52 = _io_resp_w_T_46; // @[Mux.scala:30:73]
wire [40:0] _io_resp_w_T_48 = {1'h0, _io_resp_w_T_47}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_49 = _io_resp_w_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_50 = _io_resp_w_T_49; // @[Parameters.scala:137:46]
wire _io_resp_w_T_51 = _io_resp_w_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_54 = _io_resp_w_T_52; // @[Mux.scala:30:73]
wire _io_resp_w_WIRE = _io_resp_w_T_54; // @[Mux.scala:30:73]
assign _io_resp_w_T_55 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73]
assign io_resp_w_0 = _io_resp_w_T_55; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_36 = {1'h0, _io_resp_pp_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_37 = _io_resp_pp_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_38 = _io_resp_pp_T_37; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_39 = _io_resp_pp_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_40 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_41 = _io_resp_pp_T_40 | _io_resp_pp_T_14; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_42 = _io_resp_pp_T_41 | _io_resp_pp_T_19; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_43 = _io_resp_pp_T_42 | _io_resp_pp_T_24; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_44 = _io_resp_pp_T_43 | _io_resp_pp_T_29; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_45 = _io_resp_pp_T_44 | _io_resp_pp_T_34; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_46 = _io_resp_pp_T_45 | _io_resp_pp_T_39; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_52 = _io_resp_pp_T_46; // @[Mux.scala:30:73]
wire [40:0] _io_resp_pp_T_48 = {1'h0, _io_resp_pp_T_47}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_49 = _io_resp_pp_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_50 = _io_resp_pp_T_49; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_51 = _io_resp_pp_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_54 = _io_resp_pp_T_52; // @[Mux.scala:30:73]
wire _io_resp_pp_WIRE = _io_resp_pp_T_54; // @[Mux.scala:30:73]
assign _io_resp_pp_T_55 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73]
assign io_resp_pp_0 = _io_resp_pp_T_55; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46]
wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46]
wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46]
wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46]
wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46]
wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46]
wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46]
wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_36 = {1'h0, _io_resp_al_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_37 = _io_resp_al_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_38 = _io_resp_al_T_37; // @[Parameters.scala:137:46]
wire _io_resp_al_T_39 = _io_resp_al_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_40 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89]
wire _io_resp_al_T_41 = _io_resp_al_T_40 | _io_resp_al_T_14; // @[Parameters.scala:629:89]
wire _io_resp_al_T_42 = _io_resp_al_T_41 | _io_resp_al_T_19; // @[Parameters.scala:629:89]
wire _io_resp_al_T_43 = _io_resp_al_T_42 | _io_resp_al_T_24; // @[Parameters.scala:629:89]
wire _io_resp_al_T_44 = _io_resp_al_T_43 | _io_resp_al_T_29; // @[Parameters.scala:629:89]
wire _io_resp_al_T_45 = _io_resp_al_T_44 | _io_resp_al_T_34; // @[Parameters.scala:629:89]
wire _io_resp_al_T_46 = _io_resp_al_T_45 | _io_resp_al_T_39; // @[Parameters.scala:629:89]
wire _io_resp_al_T_52 = _io_resp_al_T_46; // @[Mux.scala:30:73]
wire [40:0] _io_resp_al_T_48 = {1'h0, _io_resp_al_T_47}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_49 = _io_resp_al_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_50 = _io_resp_al_T_49; // @[Parameters.scala:137:46]
wire _io_resp_al_T_51 = _io_resp_al_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_54 = _io_resp_al_T_52; // @[Mux.scala:30:73]
wire _io_resp_al_WIRE = _io_resp_al_T_54; // @[Mux.scala:30:73]
assign _io_resp_al_T_55 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73]
assign io_resp_al_0 = _io_resp_al_T_55; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_36 = {1'h0, _io_resp_aa_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_37 = _io_resp_aa_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_38 = _io_resp_aa_T_37; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_39 = _io_resp_aa_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_40 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_41 = _io_resp_aa_T_40 | _io_resp_aa_T_14; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_42 = _io_resp_aa_T_41 | _io_resp_aa_T_19; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_43 = _io_resp_aa_T_42 | _io_resp_aa_T_24; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_44 = _io_resp_aa_T_43 | _io_resp_aa_T_29; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_45 = _io_resp_aa_T_44 | _io_resp_aa_T_34; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_46 = _io_resp_aa_T_45 | _io_resp_aa_T_39; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_52 = _io_resp_aa_T_46; // @[Mux.scala:30:73]
wire [40:0] _io_resp_aa_T_48 = {1'h0, _io_resp_aa_T_47}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_49 = _io_resp_aa_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_50 = _io_resp_aa_T_49; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_51 = _io_resp_aa_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_54 = _io_resp_aa_T_52; // @[Mux.scala:30:73]
wire _io_resp_aa_WIRE = _io_resp_aa_T_54; // @[Mux.scala:30:73]
assign _io_resp_aa_T_55 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73]
assign io_resp_aa_0 = _io_resp_aa_T_55; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46]
wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46]
wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46]
wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46]
wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46]
wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89]
wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89]
wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89]
wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89]
wire _io_resp_x_T_76 = _io_resp_x_T_28; // @[Mux.scala:30:73]
wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46]
wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'hFFFFC000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46]
wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46]
wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'hFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46]
wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46]
wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46]
wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_60 = {1'h0, _io_resp_x_T_59}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_61 = _io_resp_x_T_60 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_62 = _io_resp_x_T_61; // @[Parameters.scala:137:46]
wire _io_resp_x_T_63 = _io_resp_x_T_62 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_65 = {1'h0, _io_resp_x_T_64}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_66 = _io_resp_x_T_65 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_67 = _io_resp_x_T_66; // @[Parameters.scala:137:46]
wire _io_resp_x_T_68 = _io_resp_x_T_67 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_69 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89]
wire _io_resp_x_T_70 = _io_resp_x_T_69 | _io_resp_x_T_43; // @[Parameters.scala:629:89]
wire _io_resp_x_T_71 = _io_resp_x_T_70 | _io_resp_x_T_48; // @[Parameters.scala:629:89]
wire _io_resp_x_T_72 = _io_resp_x_T_71 | _io_resp_x_T_53; // @[Parameters.scala:629:89]
wire _io_resp_x_T_73 = _io_resp_x_T_72 | _io_resp_x_T_58; // @[Parameters.scala:629:89]
wire _io_resp_x_T_74 = _io_resp_x_T_73 | _io_resp_x_T_63; // @[Parameters.scala:629:89]
wire _io_resp_x_T_75 = _io_resp_x_T_74 | _io_resp_x_T_68; // @[Parameters.scala:629:89]
wire _io_resp_x_T_78 = _io_resp_x_T_76; // @[Mux.scala:30:73]
wire _io_resp_x_WIRE = _io_resp_x_T_78; // @[Mux.scala:30:73]
assign _io_resp_x_T_79 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73]
assign io_resp_x_0 = _io_resp_x_T_79; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'hFFFFA000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'hFFFF8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'hFFFEB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_31 = {1'h0, _io_resp_eff_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_32 = _io_resp_eff_T_31 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_33 = _io_resp_eff_T_32; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_34 = _io_resp_eff_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_35 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_36 = _io_resp_eff_T_35 | _io_resp_eff_T_14; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_37 = _io_resp_eff_T_36 | _io_resp_eff_T_19; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_38 = _io_resp_eff_T_37 | _io_resp_eff_T_24; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_39 = _io_resp_eff_T_38 | _io_resp_eff_T_29; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_40 = _io_resp_eff_T_39 | _io_resp_eff_T_34; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_64 = _io_resp_eff_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_eff_T_42 = {1'h0, _io_resp_eff_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_44 = _io_resp_eff_T_43; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_45 = _io_resp_eff_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_47 = {1'h0, _io_resp_eff_T_46}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_49 = _io_resp_eff_T_48; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_50 = _io_resp_eff_T_49 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_52 = {1'h0, _io_resp_eff_T_51}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_54 = _io_resp_eff_T_53; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_55 = _io_resp_eff_T_54 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_57 = {1'h0, _io_resp_eff_T_56}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_58 = _io_resp_eff_T_57 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_59 = _io_resp_eff_T_58; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_60 = _io_resp_eff_T_59 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_61 = _io_resp_eff_T_45 | _io_resp_eff_T_50; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_62 = _io_resp_eff_T_61 | _io_resp_eff_T_55; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_63 = _io_resp_eff_T_62 | _io_resp_eff_T_60; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_66 = _io_resp_eff_T_64; // @[Mux.scala:30:73]
wire _io_resp_eff_WIRE = _io_resp_eff_T_66; // @[Mux.scala:30:73]
assign _io_resp_eff_T_67 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73]
assign io_resp_eff_0 = _io_resp_eff_T_67; // @[PMA.scala:18:7, :39:19]
assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7]
assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7]
assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7]
assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7]
assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7]
assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7]
assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7]
assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_8 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<6>(0h30))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<4>(0h8))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<4>(0h9))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<4>(0ha))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<4>(0hb))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 3)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<2>(0h2))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 3)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<1>(0h1))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_5, UInt<3>(0h7))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 2, 0)
node _source_ok_T_37 = shr(io.in.a.bits.source, 3)
node _source_ok_T_38 = eq(_source_ok_T_37, UInt<1>(0h0))
node _source_ok_T_39 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39)
node _source_ok_T_41 = leq(source_ok_uncommonBits_6, UInt<3>(0h7))
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_36
connect _source_ok_WIRE[7], _source_ok_T_42
connect _source_ok_WIRE[8], _source_ok_T_43
node _source_ok_T_44 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[2])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[3])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[4])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[5])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[6])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_50, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<4>(0h8))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<4>(0h9))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<4>(0ha))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<4>(0hb))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_64 = shr(io.in.a.bits.source, 3)
node _T_65 = eq(_T_64, UInt<2>(0h2))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<3>(0h7))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0)
node _T_77 = shr(io.in.a.bits.source, 3)
node _T_78 = eq(_T_77, UInt<1>(0h1))
node _T_79 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_80 = and(_T_78, _T_79)
node _T_81 = leq(uncommonBits_5, UInt<3>(0h7))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(_T_82, UInt<1>(0h0))
node _T_84 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_85 = cvt(_T_84)
node _T_86 = and(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = asSInt(_T_86)
node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0)))
node _T_89 = or(_T_83, _T_88)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0)
node _T_90 = shr(io.in.a.bits.source, 3)
node _T_91 = eq(_T_90, UInt<1>(0h0))
node _T_92 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_93 = and(_T_91, _T_92)
node _T_94 = leq(uncommonBits_6, UInt<3>(0h7))
node _T_95 = and(_T_93, _T_94)
node _T_96 = eq(_T_95, UInt<1>(0h0))
node _T_97 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_98 = cvt(_T_97)
node _T_99 = and(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = asSInt(_T_99)
node _T_101 = eq(_T_100, asSInt(UInt<1>(0h0)))
node _T_102 = or(_T_96, _T_101)
node _T_103 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_106 = cvt(_T_105)
node _T_107 = and(_T_106, asSInt(UInt<1>(0h0)))
node _T_108 = asSInt(_T_107)
node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0)))
node _T_110 = or(_T_104, _T_109)
node _T_111 = and(_T_11, _T_24)
node _T_112 = and(_T_111, _T_37)
node _T_113 = and(_T_112, _T_50)
node _T_114 = and(_T_113, _T_63)
node _T_115 = and(_T_114, _T_76)
node _T_116 = and(_T_115, _T_89)
node _T_117 = and(_T_116, _T_102)
node _T_118 = and(_T_117, _T_110)
node _T_119 = asUInt(reset)
node _T_120 = eq(_T_119, UInt<1>(0h0))
when _T_120 :
node _T_121 = eq(_T_118, UInt<1>(0h0))
when _T_121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_118, UInt<1>(0h1), "") : assert_1
node _T_122 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_122 :
node _T_123 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_124 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_125 = and(_T_123, _T_124)
node _T_126 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_127 = shr(io.in.a.bits.source, 2)
node _T_128 = eq(_T_127, UInt<4>(0h8))
node _T_129 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_130 = and(_T_128, _T_129)
node _T_131 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_132 = and(_T_130, _T_131)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_133 = shr(io.in.a.bits.source, 2)
node _T_134 = eq(_T_133, UInt<4>(0h9))
node _T_135 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_136 = and(_T_134, _T_135)
node _T_137 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_138 = and(_T_136, _T_137)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_139 = shr(io.in.a.bits.source, 2)
node _T_140 = eq(_T_139, UInt<4>(0ha))
node _T_141 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_142 = and(_T_140, _T_141)
node _T_143 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_144 = and(_T_142, _T_143)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_145 = shr(io.in.a.bits.source, 2)
node _T_146 = eq(_T_145, UInt<4>(0hb))
node _T_147 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_148 = and(_T_146, _T_147)
node _T_149 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_150 = and(_T_148, _T_149)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0)
node _T_151 = shr(io.in.a.bits.source, 3)
node _T_152 = eq(_T_151, UInt<2>(0h2))
node _T_153 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_154 = and(_T_152, _T_153)
node _T_155 = leq(uncommonBits_11, UInt<3>(0h7))
node _T_156 = and(_T_154, _T_155)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0)
node _T_157 = shr(io.in.a.bits.source, 3)
node _T_158 = eq(_T_157, UInt<1>(0h1))
node _T_159 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_160 = and(_T_158, _T_159)
node _T_161 = leq(uncommonBits_12, UInt<3>(0h7))
node _T_162 = and(_T_160, _T_161)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0)
node _T_163 = shr(io.in.a.bits.source, 3)
node _T_164 = eq(_T_163, UInt<1>(0h0))
node _T_165 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_166 = and(_T_164, _T_165)
node _T_167 = leq(uncommonBits_13, UInt<3>(0h7))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_170 = or(_T_126, _T_132)
node _T_171 = or(_T_170, _T_138)
node _T_172 = or(_T_171, _T_144)
node _T_173 = or(_T_172, _T_150)
node _T_174 = or(_T_173, _T_156)
node _T_175 = or(_T_174, _T_162)
node _T_176 = or(_T_175, _T_168)
node _T_177 = or(_T_176, _T_169)
node _T_178 = and(_T_125, _T_177)
node _T_179 = or(UInt<1>(0h0), _T_178)
node _T_180 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_181 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_182 = cvt(_T_181)
node _T_183 = and(_T_182, asSInt(UInt<13>(0h1000)))
node _T_184 = asSInt(_T_183)
node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0)))
node _T_186 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<13>(0h1000)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = or(_T_185, _T_190)
node _T_192 = and(_T_180, _T_191)
node _T_193 = or(UInt<1>(0h0), _T_192)
node _T_194 = and(_T_179, _T_193)
node _T_195 = asUInt(reset)
node _T_196 = eq(_T_195, UInt<1>(0h0))
when _T_196 :
node _T_197 = eq(_T_194, UInt<1>(0h0))
when _T_197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_194, UInt<1>(0h1), "") : assert_2
node _T_198 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_199 = shr(io.in.a.bits.source, 2)
node _T_200 = eq(_T_199, UInt<4>(0h8))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_204 = and(_T_202, _T_203)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_205 = shr(io.in.a.bits.source, 2)
node _T_206 = eq(_T_205, UInt<4>(0h9))
node _T_207 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_208 = and(_T_206, _T_207)
node _T_209 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_210 = and(_T_208, _T_209)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_211 = shr(io.in.a.bits.source, 2)
node _T_212 = eq(_T_211, UInt<4>(0ha))
node _T_213 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_214 = and(_T_212, _T_213)
node _T_215 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_216 = and(_T_214, _T_215)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_217 = shr(io.in.a.bits.source, 2)
node _T_218 = eq(_T_217, UInt<4>(0hb))
node _T_219 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_220 = and(_T_218, _T_219)
node _T_221 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_222 = and(_T_220, _T_221)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 2, 0)
node _T_223 = shr(io.in.a.bits.source, 3)
node _T_224 = eq(_T_223, UInt<2>(0h2))
node _T_225 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_226 = and(_T_224, _T_225)
node _T_227 = leq(uncommonBits_18, UInt<3>(0h7))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0)
node _T_229 = shr(io.in.a.bits.source, 3)
node _T_230 = eq(_T_229, UInt<1>(0h1))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_19, UInt<3>(0h7))
node _T_234 = and(_T_232, _T_233)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 2, 0)
node _T_235 = shr(io.in.a.bits.source, 3)
node _T_236 = eq(_T_235, UInt<1>(0h0))
node _T_237 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_238 = and(_T_236, _T_237)
node _T_239 = leq(uncommonBits_20, UInt<3>(0h7))
node _T_240 = and(_T_238, _T_239)
node _T_241 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_198
connect _WIRE[1], _T_204
connect _WIRE[2], _T_210
connect _WIRE[3], _T_216
connect _WIRE[4], _T_222
connect _WIRE[5], _T_228
connect _WIRE[6], _T_234
connect _WIRE[7], _T_240
connect _WIRE[8], _T_241
node _T_242 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_243 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_244 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_245 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_246 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_247 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_248 = mux(_WIRE[5], _T_242, UInt<1>(0h0))
node _T_249 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_250 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_251 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_252 = or(_T_243, _T_244)
node _T_253 = or(_T_252, _T_245)
node _T_254 = or(_T_253, _T_246)
node _T_255 = or(_T_254, _T_247)
node _T_256 = or(_T_255, _T_248)
node _T_257 = or(_T_256, _T_249)
node _T_258 = or(_T_257, _T_250)
node _T_259 = or(_T_258, _T_251)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_259
node _T_260 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_261 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_262 = and(_T_260, _T_261)
node _T_263 = or(UInt<1>(0h0), _T_262)
node _T_264 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<13>(0h1000)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<13>(0h1000)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = or(_T_268, _T_273)
node _T_275 = and(_T_263, _T_274)
node _T_276 = or(UInt<1>(0h0), _T_275)
node _T_277 = and(_WIRE_1, _T_276)
node _T_278 = asUInt(reset)
node _T_279 = eq(_T_278, UInt<1>(0h0))
when _T_279 :
node _T_280 = eq(_T_277, UInt<1>(0h0))
when _T_280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_277, UInt<1>(0h1), "") : assert_3
node _T_281 = asUInt(reset)
node _T_282 = eq(_T_281, UInt<1>(0h0))
when _T_282 :
node _T_283 = eq(source_ok, UInt<1>(0h0))
when _T_283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_284 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_284, UInt<1>(0h1), "") : assert_5
node _T_288 = asUInt(reset)
node _T_289 = eq(_T_288, UInt<1>(0h0))
when _T_289 :
node _T_290 = eq(is_aligned, UInt<1>(0h0))
when _T_290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_291 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_292 = asUInt(reset)
node _T_293 = eq(_T_292, UInt<1>(0h0))
when _T_293 :
node _T_294 = eq(_T_291, UInt<1>(0h0))
when _T_294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_291, UInt<1>(0h1), "") : assert_7
node _T_295 = not(io.in.a.bits.mask)
node _T_296 = eq(_T_295, UInt<1>(0h0))
node _T_297 = asUInt(reset)
node _T_298 = eq(_T_297, UInt<1>(0h0))
when _T_298 :
node _T_299 = eq(_T_296, UInt<1>(0h0))
when _T_299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_296, UInt<1>(0h1), "") : assert_8
node _T_300 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_301 = asUInt(reset)
node _T_302 = eq(_T_301, UInt<1>(0h0))
when _T_302 :
node _T_303 = eq(_T_300, UInt<1>(0h0))
when _T_303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_300, UInt<1>(0h1), "") : assert_9
node _T_304 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_304 :
node _T_305 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_306 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_309 = shr(io.in.a.bits.source, 2)
node _T_310 = eq(_T_309, UInt<4>(0h8))
node _T_311 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_312 = and(_T_310, _T_311)
node _T_313 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_314 = and(_T_312, _T_313)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_315 = shr(io.in.a.bits.source, 2)
node _T_316 = eq(_T_315, UInt<4>(0h9))
node _T_317 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_318 = and(_T_316, _T_317)
node _T_319 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_321 = shr(io.in.a.bits.source, 2)
node _T_322 = eq(_T_321, UInt<4>(0ha))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_326 = and(_T_324, _T_325)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_327 = shr(io.in.a.bits.source, 2)
node _T_328 = eq(_T_327, UInt<4>(0hb))
node _T_329 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_330 = and(_T_328, _T_329)
node _T_331 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_332 = and(_T_330, _T_331)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 2, 0)
node _T_333 = shr(io.in.a.bits.source, 3)
node _T_334 = eq(_T_333, UInt<2>(0h2))
node _T_335 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_336 = and(_T_334, _T_335)
node _T_337 = leq(uncommonBits_25, UInt<3>(0h7))
node _T_338 = and(_T_336, _T_337)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 2, 0)
node _T_339 = shr(io.in.a.bits.source, 3)
node _T_340 = eq(_T_339, UInt<1>(0h1))
node _T_341 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_342 = and(_T_340, _T_341)
node _T_343 = leq(uncommonBits_26, UInt<3>(0h7))
node _T_344 = and(_T_342, _T_343)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 2, 0)
node _T_345 = shr(io.in.a.bits.source, 3)
node _T_346 = eq(_T_345, UInt<1>(0h0))
node _T_347 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_348 = and(_T_346, _T_347)
node _T_349 = leq(uncommonBits_27, UInt<3>(0h7))
node _T_350 = and(_T_348, _T_349)
node _T_351 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_352 = or(_T_308, _T_314)
node _T_353 = or(_T_352, _T_320)
node _T_354 = or(_T_353, _T_326)
node _T_355 = or(_T_354, _T_332)
node _T_356 = or(_T_355, _T_338)
node _T_357 = or(_T_356, _T_344)
node _T_358 = or(_T_357, _T_350)
node _T_359 = or(_T_358, _T_351)
node _T_360 = and(_T_307, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_363 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_364 = cvt(_T_363)
node _T_365 = and(_T_364, asSInt(UInt<13>(0h1000)))
node _T_366 = asSInt(_T_365)
node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0)))
node _T_368 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = or(_T_367, _T_372)
node _T_374 = and(_T_362, _T_373)
node _T_375 = or(UInt<1>(0h0), _T_374)
node _T_376 = and(_T_361, _T_375)
node _T_377 = asUInt(reset)
node _T_378 = eq(_T_377, UInt<1>(0h0))
when _T_378 :
node _T_379 = eq(_T_376, UInt<1>(0h0))
when _T_379 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_376, UInt<1>(0h1), "") : assert_10
node _T_380 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_381 = shr(io.in.a.bits.source, 2)
node _T_382 = eq(_T_381, UInt<4>(0h8))
node _T_383 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_384 = and(_T_382, _T_383)
node _T_385 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_387 = shr(io.in.a.bits.source, 2)
node _T_388 = eq(_T_387, UInt<4>(0h9))
node _T_389 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_390 = and(_T_388, _T_389)
node _T_391 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_392 = and(_T_390, _T_391)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_393 = shr(io.in.a.bits.source, 2)
node _T_394 = eq(_T_393, UInt<4>(0ha))
node _T_395 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_396 = and(_T_394, _T_395)
node _T_397 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_398 = and(_T_396, _T_397)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_399 = shr(io.in.a.bits.source, 2)
node _T_400 = eq(_T_399, UInt<4>(0hb))
node _T_401 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_402 = and(_T_400, _T_401)
node _T_403 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_404 = and(_T_402, _T_403)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 2, 0)
node _T_405 = shr(io.in.a.bits.source, 3)
node _T_406 = eq(_T_405, UInt<2>(0h2))
node _T_407 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_408 = and(_T_406, _T_407)
node _T_409 = leq(uncommonBits_32, UInt<3>(0h7))
node _T_410 = and(_T_408, _T_409)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 2, 0)
node _T_411 = shr(io.in.a.bits.source, 3)
node _T_412 = eq(_T_411, UInt<1>(0h1))
node _T_413 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_414 = and(_T_412, _T_413)
node _T_415 = leq(uncommonBits_33, UInt<3>(0h7))
node _T_416 = and(_T_414, _T_415)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0)
node _T_417 = shr(io.in.a.bits.source, 3)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_420 = and(_T_418, _T_419)
node _T_421 = leq(uncommonBits_34, UInt<3>(0h7))
node _T_422 = and(_T_420, _T_421)
node _T_423 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_380
connect _WIRE_2[1], _T_386
connect _WIRE_2[2], _T_392
connect _WIRE_2[3], _T_398
connect _WIRE_2[4], _T_404
connect _WIRE_2[5], _T_410
connect _WIRE_2[6], _T_416
connect _WIRE_2[7], _T_422
connect _WIRE_2[8], _T_423
node _T_424 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_425 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_426 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_427 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_428 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_429 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_430 = mux(_WIRE_2[5], _T_424, UInt<1>(0h0))
node _T_431 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_432 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_433 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_434 = or(_T_425, _T_426)
node _T_435 = or(_T_434, _T_427)
node _T_436 = or(_T_435, _T_428)
node _T_437 = or(_T_436, _T_429)
node _T_438 = or(_T_437, _T_430)
node _T_439 = or(_T_438, _T_431)
node _T_440 = or(_T_439, _T_432)
node _T_441 = or(_T_440, _T_433)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_441
node _T_442 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_443 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_444 = and(_T_442, _T_443)
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_447 = cvt(_T_446)
node _T_448 = and(_T_447, asSInt(UInt<13>(0h1000)))
node _T_449 = asSInt(_T_448)
node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0)))
node _T_451 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_452 = cvt(_T_451)
node _T_453 = and(_T_452, asSInt(UInt<13>(0h1000)))
node _T_454 = asSInt(_T_453)
node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0)))
node _T_456 = or(_T_450, _T_455)
node _T_457 = and(_T_445, _T_456)
node _T_458 = or(UInt<1>(0h0), _T_457)
node _T_459 = and(_WIRE_3, _T_458)
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_459, UInt<1>(0h1), "") : assert_11
node _T_463 = asUInt(reset)
node _T_464 = eq(_T_463, UInt<1>(0h0))
when _T_464 :
node _T_465 = eq(source_ok, UInt<1>(0h0))
when _T_465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_466 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_467 = asUInt(reset)
node _T_468 = eq(_T_467, UInt<1>(0h0))
when _T_468 :
node _T_469 = eq(_T_466, UInt<1>(0h0))
when _T_469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_466, UInt<1>(0h1), "") : assert_13
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(is_aligned, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_473 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_473, UInt<1>(0h1), "") : assert_15
node _T_477 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_477, UInt<1>(0h1), "") : assert_16
node _T_481 = not(io.in.a.bits.mask)
node _T_482 = eq(_T_481, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_482, UInt<1>(0h1), "") : assert_17
node _T_486 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_486, UInt<1>(0h1), "") : assert_18
node _T_490 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_490 :
node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_492 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_493 = and(_T_491, _T_492)
node _T_494 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_495 = shr(io.in.a.bits.source, 2)
node _T_496 = eq(_T_495, UInt<4>(0h8))
node _T_497 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_498 = and(_T_496, _T_497)
node _T_499 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_500 = and(_T_498, _T_499)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_501 = shr(io.in.a.bits.source, 2)
node _T_502 = eq(_T_501, UInt<4>(0h9))
node _T_503 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_504 = and(_T_502, _T_503)
node _T_505 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_506 = and(_T_504, _T_505)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_507 = shr(io.in.a.bits.source, 2)
node _T_508 = eq(_T_507, UInt<4>(0ha))
node _T_509 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_510 = and(_T_508, _T_509)
node _T_511 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_512 = and(_T_510, _T_511)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_513 = shr(io.in.a.bits.source, 2)
node _T_514 = eq(_T_513, UInt<4>(0hb))
node _T_515 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_516 = and(_T_514, _T_515)
node _T_517 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_518 = and(_T_516, _T_517)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0)
node _T_519 = shr(io.in.a.bits.source, 3)
node _T_520 = eq(_T_519, UInt<2>(0h2))
node _T_521 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_522 = and(_T_520, _T_521)
node _T_523 = leq(uncommonBits_39, UInt<3>(0h7))
node _T_524 = and(_T_522, _T_523)
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0)
node _T_525 = shr(io.in.a.bits.source, 3)
node _T_526 = eq(_T_525, UInt<1>(0h1))
node _T_527 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_528 = and(_T_526, _T_527)
node _T_529 = leq(uncommonBits_40, UInt<3>(0h7))
node _T_530 = and(_T_528, _T_529)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0)
node _T_531 = shr(io.in.a.bits.source, 3)
node _T_532 = eq(_T_531, UInt<1>(0h0))
node _T_533 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_534 = and(_T_532, _T_533)
node _T_535 = leq(uncommonBits_41, UInt<3>(0h7))
node _T_536 = and(_T_534, _T_535)
node _T_537 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_538 = or(_T_494, _T_500)
node _T_539 = or(_T_538, _T_506)
node _T_540 = or(_T_539, _T_512)
node _T_541 = or(_T_540, _T_518)
node _T_542 = or(_T_541, _T_524)
node _T_543 = or(_T_542, _T_530)
node _T_544 = or(_T_543, _T_536)
node _T_545 = or(_T_544, _T_537)
node _T_546 = and(_T_493, _T_545)
node _T_547 = or(UInt<1>(0h0), _T_546)
node _T_548 = asUInt(reset)
node _T_549 = eq(_T_548, UInt<1>(0h0))
when _T_549 :
node _T_550 = eq(_T_547, UInt<1>(0h0))
when _T_550 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_547, UInt<1>(0h1), "") : assert_19
node _T_551 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_552 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_553 = and(_T_551, _T_552)
node _T_554 = or(UInt<1>(0h0), _T_553)
node _T_555 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_556 = cvt(_T_555)
node _T_557 = and(_T_556, asSInt(UInt<13>(0h1000)))
node _T_558 = asSInt(_T_557)
node _T_559 = eq(_T_558, asSInt(UInt<1>(0h0)))
node _T_560 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_561 = cvt(_T_560)
node _T_562 = and(_T_561, asSInt(UInt<13>(0h1000)))
node _T_563 = asSInt(_T_562)
node _T_564 = eq(_T_563, asSInt(UInt<1>(0h0)))
node _T_565 = or(_T_559, _T_564)
node _T_566 = and(_T_554, _T_565)
node _T_567 = or(UInt<1>(0h0), _T_566)
node _T_568 = asUInt(reset)
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(_T_567, UInt<1>(0h0))
when _T_570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_567, UInt<1>(0h1), "") : assert_20
node _T_571 = asUInt(reset)
node _T_572 = eq(_T_571, UInt<1>(0h0))
when _T_572 :
node _T_573 = eq(source_ok, UInt<1>(0h0))
when _T_573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(is_aligned, UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_577 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_577, UInt<1>(0h1), "") : assert_23
node _T_581 = eq(io.in.a.bits.mask, mask)
node _T_582 = asUInt(reset)
node _T_583 = eq(_T_582, UInt<1>(0h0))
when _T_583 :
node _T_584 = eq(_T_581, UInt<1>(0h0))
when _T_584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_581, UInt<1>(0h1), "") : assert_24
node _T_585 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_586 = asUInt(reset)
node _T_587 = eq(_T_586, UInt<1>(0h0))
when _T_587 :
node _T_588 = eq(_T_585, UInt<1>(0h0))
when _T_588 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_585, UInt<1>(0h1), "") : assert_25
node _T_589 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_589 :
node _T_590 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_591 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_592 = and(_T_590, _T_591)
node _T_593 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_594 = shr(io.in.a.bits.source, 2)
node _T_595 = eq(_T_594, UInt<4>(0h8))
node _T_596 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_597 = and(_T_595, _T_596)
node _T_598 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_599 = and(_T_597, _T_598)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_600 = shr(io.in.a.bits.source, 2)
node _T_601 = eq(_T_600, UInt<4>(0h9))
node _T_602 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_603 = and(_T_601, _T_602)
node _T_604 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_605 = and(_T_603, _T_604)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_606 = shr(io.in.a.bits.source, 2)
node _T_607 = eq(_T_606, UInt<4>(0ha))
node _T_608 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_609 = and(_T_607, _T_608)
node _T_610 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_611 = and(_T_609, _T_610)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_612 = shr(io.in.a.bits.source, 2)
node _T_613 = eq(_T_612, UInt<4>(0hb))
node _T_614 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_615 = and(_T_613, _T_614)
node _T_616 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_617 = and(_T_615, _T_616)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0)
node _T_618 = shr(io.in.a.bits.source, 3)
node _T_619 = eq(_T_618, UInt<2>(0h2))
node _T_620 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_621 = and(_T_619, _T_620)
node _T_622 = leq(uncommonBits_46, UInt<3>(0h7))
node _T_623 = and(_T_621, _T_622)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0)
node _T_624 = shr(io.in.a.bits.source, 3)
node _T_625 = eq(_T_624, UInt<1>(0h1))
node _T_626 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_627 = and(_T_625, _T_626)
node _T_628 = leq(uncommonBits_47, UInt<3>(0h7))
node _T_629 = and(_T_627, _T_628)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 2, 0)
node _T_630 = shr(io.in.a.bits.source, 3)
node _T_631 = eq(_T_630, UInt<1>(0h0))
node _T_632 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_633 = and(_T_631, _T_632)
node _T_634 = leq(uncommonBits_48, UInt<3>(0h7))
node _T_635 = and(_T_633, _T_634)
node _T_636 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_637 = or(_T_593, _T_599)
node _T_638 = or(_T_637, _T_605)
node _T_639 = or(_T_638, _T_611)
node _T_640 = or(_T_639, _T_617)
node _T_641 = or(_T_640, _T_623)
node _T_642 = or(_T_641, _T_629)
node _T_643 = or(_T_642, _T_635)
node _T_644 = or(_T_643, _T_636)
node _T_645 = and(_T_592, _T_644)
node _T_646 = or(UInt<1>(0h0), _T_645)
node _T_647 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_648 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_649 = and(_T_647, _T_648)
node _T_650 = or(UInt<1>(0h0), _T_649)
node _T_651 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_652 = cvt(_T_651)
node _T_653 = and(_T_652, asSInt(UInt<13>(0h1000)))
node _T_654 = asSInt(_T_653)
node _T_655 = eq(_T_654, asSInt(UInt<1>(0h0)))
node _T_656 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_657 = cvt(_T_656)
node _T_658 = and(_T_657, asSInt(UInt<13>(0h1000)))
node _T_659 = asSInt(_T_658)
node _T_660 = eq(_T_659, asSInt(UInt<1>(0h0)))
node _T_661 = or(_T_655, _T_660)
node _T_662 = and(_T_650, _T_661)
node _T_663 = or(UInt<1>(0h0), _T_662)
node _T_664 = and(_T_646, _T_663)
node _T_665 = asUInt(reset)
node _T_666 = eq(_T_665, UInt<1>(0h0))
when _T_666 :
node _T_667 = eq(_T_664, UInt<1>(0h0))
when _T_667 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_664, UInt<1>(0h1), "") : assert_26
node _T_668 = asUInt(reset)
node _T_669 = eq(_T_668, UInt<1>(0h0))
when _T_669 :
node _T_670 = eq(source_ok, UInt<1>(0h0))
when _T_670 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_671 = asUInt(reset)
node _T_672 = eq(_T_671, UInt<1>(0h0))
when _T_672 :
node _T_673 = eq(is_aligned, UInt<1>(0h0))
when _T_673 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_674 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_675 = asUInt(reset)
node _T_676 = eq(_T_675, UInt<1>(0h0))
when _T_676 :
node _T_677 = eq(_T_674, UInt<1>(0h0))
when _T_677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_674, UInt<1>(0h1), "") : assert_29
node _T_678 = eq(io.in.a.bits.mask, mask)
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_678, UInt<1>(0h1), "") : assert_30
node _T_682 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_682 :
node _T_683 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_684 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_685 = and(_T_683, _T_684)
node _T_686 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_687 = shr(io.in.a.bits.source, 2)
node _T_688 = eq(_T_687, UInt<4>(0h8))
node _T_689 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_690 = and(_T_688, _T_689)
node _T_691 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_692 = and(_T_690, _T_691)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_693 = shr(io.in.a.bits.source, 2)
node _T_694 = eq(_T_693, UInt<4>(0h9))
node _T_695 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_696 = and(_T_694, _T_695)
node _T_697 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_698 = and(_T_696, _T_697)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_699 = shr(io.in.a.bits.source, 2)
node _T_700 = eq(_T_699, UInt<4>(0ha))
node _T_701 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_702 = and(_T_700, _T_701)
node _T_703 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_704 = and(_T_702, _T_703)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_705 = shr(io.in.a.bits.source, 2)
node _T_706 = eq(_T_705, UInt<4>(0hb))
node _T_707 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_708 = and(_T_706, _T_707)
node _T_709 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_710 = and(_T_708, _T_709)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0)
node _T_711 = shr(io.in.a.bits.source, 3)
node _T_712 = eq(_T_711, UInt<2>(0h2))
node _T_713 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_714 = and(_T_712, _T_713)
node _T_715 = leq(uncommonBits_53, UInt<3>(0h7))
node _T_716 = and(_T_714, _T_715)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0)
node _T_717 = shr(io.in.a.bits.source, 3)
node _T_718 = eq(_T_717, UInt<1>(0h1))
node _T_719 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_720 = and(_T_718, _T_719)
node _T_721 = leq(uncommonBits_54, UInt<3>(0h7))
node _T_722 = and(_T_720, _T_721)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 2, 0)
node _T_723 = shr(io.in.a.bits.source, 3)
node _T_724 = eq(_T_723, UInt<1>(0h0))
node _T_725 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_726 = and(_T_724, _T_725)
node _T_727 = leq(uncommonBits_55, UInt<3>(0h7))
node _T_728 = and(_T_726, _T_727)
node _T_729 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_730 = or(_T_686, _T_692)
node _T_731 = or(_T_730, _T_698)
node _T_732 = or(_T_731, _T_704)
node _T_733 = or(_T_732, _T_710)
node _T_734 = or(_T_733, _T_716)
node _T_735 = or(_T_734, _T_722)
node _T_736 = or(_T_735, _T_728)
node _T_737 = or(_T_736, _T_729)
node _T_738 = and(_T_685, _T_737)
node _T_739 = or(UInt<1>(0h0), _T_738)
node _T_740 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_741 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_742 = and(_T_740, _T_741)
node _T_743 = or(UInt<1>(0h0), _T_742)
node _T_744 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_745 = cvt(_T_744)
node _T_746 = and(_T_745, asSInt(UInt<13>(0h1000)))
node _T_747 = asSInt(_T_746)
node _T_748 = eq(_T_747, asSInt(UInt<1>(0h0)))
node _T_749 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_750 = cvt(_T_749)
node _T_751 = and(_T_750, asSInt(UInt<13>(0h1000)))
node _T_752 = asSInt(_T_751)
node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0)))
node _T_754 = or(_T_748, _T_753)
node _T_755 = and(_T_743, _T_754)
node _T_756 = or(UInt<1>(0h0), _T_755)
node _T_757 = and(_T_739, _T_756)
node _T_758 = asUInt(reset)
node _T_759 = eq(_T_758, UInt<1>(0h0))
when _T_759 :
node _T_760 = eq(_T_757, UInt<1>(0h0))
when _T_760 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_757, UInt<1>(0h1), "") : assert_31
node _T_761 = asUInt(reset)
node _T_762 = eq(_T_761, UInt<1>(0h0))
when _T_762 :
node _T_763 = eq(source_ok, UInt<1>(0h0))
when _T_763 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(is_aligned, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_767 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_767, UInt<1>(0h1), "") : assert_34
node _T_771 = not(mask)
node _T_772 = and(io.in.a.bits.mask, _T_771)
node _T_773 = eq(_T_772, UInt<1>(0h0))
node _T_774 = asUInt(reset)
node _T_775 = eq(_T_774, UInt<1>(0h0))
when _T_775 :
node _T_776 = eq(_T_773, UInt<1>(0h0))
when _T_776 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_773, UInt<1>(0h1), "") : assert_35
node _T_777 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_777 :
node _T_778 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_779 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_780 = and(_T_778, _T_779)
node _T_781 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_782 = shr(io.in.a.bits.source, 2)
node _T_783 = eq(_T_782, UInt<4>(0h8))
node _T_784 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_785 = and(_T_783, _T_784)
node _T_786 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_787 = and(_T_785, _T_786)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_788 = shr(io.in.a.bits.source, 2)
node _T_789 = eq(_T_788, UInt<4>(0h9))
node _T_790 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_791 = and(_T_789, _T_790)
node _T_792 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_793 = and(_T_791, _T_792)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 1, 0)
node _T_794 = shr(io.in.a.bits.source, 2)
node _T_795 = eq(_T_794, UInt<4>(0ha))
node _T_796 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_797 = and(_T_795, _T_796)
node _T_798 = leq(uncommonBits_58, UInt<2>(0h3))
node _T_799 = and(_T_797, _T_798)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 1, 0)
node _T_800 = shr(io.in.a.bits.source, 2)
node _T_801 = eq(_T_800, UInt<4>(0hb))
node _T_802 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_803 = and(_T_801, _T_802)
node _T_804 = leq(uncommonBits_59, UInt<2>(0h3))
node _T_805 = and(_T_803, _T_804)
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 2, 0)
node _T_806 = shr(io.in.a.bits.source, 3)
node _T_807 = eq(_T_806, UInt<2>(0h2))
node _T_808 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_809 = and(_T_807, _T_808)
node _T_810 = leq(uncommonBits_60, UInt<3>(0h7))
node _T_811 = and(_T_809, _T_810)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 2, 0)
node _T_812 = shr(io.in.a.bits.source, 3)
node _T_813 = eq(_T_812, UInt<1>(0h1))
node _T_814 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_815 = and(_T_813, _T_814)
node _T_816 = leq(uncommonBits_61, UInt<3>(0h7))
node _T_817 = and(_T_815, _T_816)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 2, 0)
node _T_818 = shr(io.in.a.bits.source, 3)
node _T_819 = eq(_T_818, UInt<1>(0h0))
node _T_820 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_821 = and(_T_819, _T_820)
node _T_822 = leq(uncommonBits_62, UInt<3>(0h7))
node _T_823 = and(_T_821, _T_822)
node _T_824 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_825 = or(_T_781, _T_787)
node _T_826 = or(_T_825, _T_793)
node _T_827 = or(_T_826, _T_799)
node _T_828 = or(_T_827, _T_805)
node _T_829 = or(_T_828, _T_811)
node _T_830 = or(_T_829, _T_817)
node _T_831 = or(_T_830, _T_823)
node _T_832 = or(_T_831, _T_824)
node _T_833 = and(_T_780, _T_832)
node _T_834 = or(UInt<1>(0h0), _T_833)
node _T_835 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_836 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_837 = and(_T_835, _T_836)
node _T_838 = or(UInt<1>(0h0), _T_837)
node _T_839 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_840 = cvt(_T_839)
node _T_841 = and(_T_840, asSInt(UInt<13>(0h1000)))
node _T_842 = asSInt(_T_841)
node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0)))
node _T_844 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_845 = cvt(_T_844)
node _T_846 = and(_T_845, asSInt(UInt<13>(0h1000)))
node _T_847 = asSInt(_T_846)
node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0)))
node _T_849 = or(_T_843, _T_848)
node _T_850 = and(_T_838, _T_849)
node _T_851 = or(UInt<1>(0h0), _T_850)
node _T_852 = and(_T_834, _T_851)
node _T_853 = asUInt(reset)
node _T_854 = eq(_T_853, UInt<1>(0h0))
when _T_854 :
node _T_855 = eq(_T_852, UInt<1>(0h0))
when _T_855 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_852, UInt<1>(0h1), "") : assert_36
node _T_856 = asUInt(reset)
node _T_857 = eq(_T_856, UInt<1>(0h0))
when _T_857 :
node _T_858 = eq(source_ok, UInt<1>(0h0))
when _T_858 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_859 = asUInt(reset)
node _T_860 = eq(_T_859, UInt<1>(0h0))
when _T_860 :
node _T_861 = eq(is_aligned, UInt<1>(0h0))
when _T_861 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_862 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_863 = asUInt(reset)
node _T_864 = eq(_T_863, UInt<1>(0h0))
when _T_864 :
node _T_865 = eq(_T_862, UInt<1>(0h0))
when _T_865 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_862, UInt<1>(0h1), "") : assert_39
node _T_866 = eq(io.in.a.bits.mask, mask)
node _T_867 = asUInt(reset)
node _T_868 = eq(_T_867, UInt<1>(0h0))
when _T_868 :
node _T_869 = eq(_T_866, UInt<1>(0h0))
when _T_869 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_866, UInt<1>(0h1), "") : assert_40
node _T_870 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_870 :
node _T_871 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_872 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_873 = and(_T_871, _T_872)
node _T_874 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_875 = shr(io.in.a.bits.source, 2)
node _T_876 = eq(_T_875, UInt<4>(0h8))
node _T_877 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_878 = and(_T_876, _T_877)
node _T_879 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_880 = and(_T_878, _T_879)
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 1, 0)
node _T_881 = shr(io.in.a.bits.source, 2)
node _T_882 = eq(_T_881, UInt<4>(0h9))
node _T_883 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_884 = and(_T_882, _T_883)
node _T_885 = leq(uncommonBits_64, UInt<2>(0h3))
node _T_886 = and(_T_884, _T_885)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 1, 0)
node _T_887 = shr(io.in.a.bits.source, 2)
node _T_888 = eq(_T_887, UInt<4>(0ha))
node _T_889 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_890 = and(_T_888, _T_889)
node _T_891 = leq(uncommonBits_65, UInt<2>(0h3))
node _T_892 = and(_T_890, _T_891)
node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 1, 0)
node _T_893 = shr(io.in.a.bits.source, 2)
node _T_894 = eq(_T_893, UInt<4>(0hb))
node _T_895 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_896 = and(_T_894, _T_895)
node _T_897 = leq(uncommonBits_66, UInt<2>(0h3))
node _T_898 = and(_T_896, _T_897)
node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 2, 0)
node _T_899 = shr(io.in.a.bits.source, 3)
node _T_900 = eq(_T_899, UInt<2>(0h2))
node _T_901 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_902 = and(_T_900, _T_901)
node _T_903 = leq(uncommonBits_67, UInt<3>(0h7))
node _T_904 = and(_T_902, _T_903)
node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 2, 0)
node _T_905 = shr(io.in.a.bits.source, 3)
node _T_906 = eq(_T_905, UInt<1>(0h1))
node _T_907 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_908 = and(_T_906, _T_907)
node _T_909 = leq(uncommonBits_68, UInt<3>(0h7))
node _T_910 = and(_T_908, _T_909)
node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 2, 0)
node _T_911 = shr(io.in.a.bits.source, 3)
node _T_912 = eq(_T_911, UInt<1>(0h0))
node _T_913 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_914 = and(_T_912, _T_913)
node _T_915 = leq(uncommonBits_69, UInt<3>(0h7))
node _T_916 = and(_T_914, _T_915)
node _T_917 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_918 = or(_T_874, _T_880)
node _T_919 = or(_T_918, _T_886)
node _T_920 = or(_T_919, _T_892)
node _T_921 = or(_T_920, _T_898)
node _T_922 = or(_T_921, _T_904)
node _T_923 = or(_T_922, _T_910)
node _T_924 = or(_T_923, _T_916)
node _T_925 = or(_T_924, _T_917)
node _T_926 = and(_T_873, _T_925)
node _T_927 = or(UInt<1>(0h0), _T_926)
node _T_928 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_929 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_930 = and(_T_928, _T_929)
node _T_931 = or(UInt<1>(0h0), _T_930)
node _T_932 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_933 = cvt(_T_932)
node _T_934 = and(_T_933, asSInt(UInt<13>(0h1000)))
node _T_935 = asSInt(_T_934)
node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0)))
node _T_937 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_938 = cvt(_T_937)
node _T_939 = and(_T_938, asSInt(UInt<13>(0h1000)))
node _T_940 = asSInt(_T_939)
node _T_941 = eq(_T_940, asSInt(UInt<1>(0h0)))
node _T_942 = or(_T_936, _T_941)
node _T_943 = and(_T_931, _T_942)
node _T_944 = or(UInt<1>(0h0), _T_943)
node _T_945 = and(_T_927, _T_944)
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(_T_945, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_945, UInt<1>(0h1), "") : assert_41
node _T_949 = asUInt(reset)
node _T_950 = eq(_T_949, UInt<1>(0h0))
when _T_950 :
node _T_951 = eq(source_ok, UInt<1>(0h0))
when _T_951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_952 = asUInt(reset)
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(is_aligned, UInt<1>(0h0))
when _T_954 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_955 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_956 = asUInt(reset)
node _T_957 = eq(_T_956, UInt<1>(0h0))
when _T_957 :
node _T_958 = eq(_T_955, UInt<1>(0h0))
when _T_958 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_955, UInt<1>(0h1), "") : assert_44
node _T_959 = eq(io.in.a.bits.mask, mask)
node _T_960 = asUInt(reset)
node _T_961 = eq(_T_960, UInt<1>(0h0))
when _T_961 :
node _T_962 = eq(_T_959, UInt<1>(0h0))
when _T_962 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_959, UInt<1>(0h1), "") : assert_45
node _T_963 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_963 :
node _T_964 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_965 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_966 = and(_T_964, _T_965)
node _T_967 = eq(io.in.a.bits.source, UInt<6>(0h30))
node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 1, 0)
node _T_968 = shr(io.in.a.bits.source, 2)
node _T_969 = eq(_T_968, UInt<4>(0h8))
node _T_970 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_971 = and(_T_969, _T_970)
node _T_972 = leq(uncommonBits_70, UInt<2>(0h3))
node _T_973 = and(_T_971, _T_972)
node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 1, 0)
node _T_974 = shr(io.in.a.bits.source, 2)
node _T_975 = eq(_T_974, UInt<4>(0h9))
node _T_976 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_977 = and(_T_975, _T_976)
node _T_978 = leq(uncommonBits_71, UInt<2>(0h3))
node _T_979 = and(_T_977, _T_978)
node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0)
node _T_980 = shr(io.in.a.bits.source, 2)
node _T_981 = eq(_T_980, UInt<4>(0ha))
node _T_982 = leq(UInt<1>(0h0), uncommonBits_72)
node _T_983 = and(_T_981, _T_982)
node _T_984 = leq(uncommonBits_72, UInt<2>(0h3))
node _T_985 = and(_T_983, _T_984)
node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0)
node _T_986 = shr(io.in.a.bits.source, 2)
node _T_987 = eq(_T_986, UInt<4>(0hb))
node _T_988 = leq(UInt<1>(0h0), uncommonBits_73)
node _T_989 = and(_T_987, _T_988)
node _T_990 = leq(uncommonBits_73, UInt<2>(0h3))
node _T_991 = and(_T_989, _T_990)
node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_74 = bits(_uncommonBits_T_74, 2, 0)
node _T_992 = shr(io.in.a.bits.source, 3)
node _T_993 = eq(_T_992, UInt<2>(0h2))
node _T_994 = leq(UInt<1>(0h0), uncommonBits_74)
node _T_995 = and(_T_993, _T_994)
node _T_996 = leq(uncommonBits_74, UInt<3>(0h7))
node _T_997 = and(_T_995, _T_996)
node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_75 = bits(_uncommonBits_T_75, 2, 0)
node _T_998 = shr(io.in.a.bits.source, 3)
node _T_999 = eq(_T_998, UInt<1>(0h1))
node _T_1000 = leq(UInt<1>(0h0), uncommonBits_75)
node _T_1001 = and(_T_999, _T_1000)
node _T_1002 = leq(uncommonBits_75, UInt<3>(0h7))
node _T_1003 = and(_T_1001, _T_1002)
node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_76 = bits(_uncommonBits_T_76, 2, 0)
node _T_1004 = shr(io.in.a.bits.source, 3)
node _T_1005 = eq(_T_1004, UInt<1>(0h0))
node _T_1006 = leq(UInt<1>(0h0), uncommonBits_76)
node _T_1007 = and(_T_1005, _T_1006)
node _T_1008 = leq(uncommonBits_76, UInt<3>(0h7))
node _T_1009 = and(_T_1007, _T_1008)
node _T_1010 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1011 = or(_T_967, _T_973)
node _T_1012 = or(_T_1011, _T_979)
node _T_1013 = or(_T_1012, _T_985)
node _T_1014 = or(_T_1013, _T_991)
node _T_1015 = or(_T_1014, _T_997)
node _T_1016 = or(_T_1015, _T_1003)
node _T_1017 = or(_T_1016, _T_1009)
node _T_1018 = or(_T_1017, _T_1010)
node _T_1019 = and(_T_966, _T_1018)
node _T_1020 = or(UInt<1>(0h0), _T_1019)
node _T_1021 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1022 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1023 = cvt(_T_1022)
node _T_1024 = and(_T_1023, asSInt(UInt<13>(0h1000)))
node _T_1025 = asSInt(_T_1024)
node _T_1026 = eq(_T_1025, asSInt(UInt<1>(0h0)))
node _T_1027 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1028 = cvt(_T_1027)
node _T_1029 = and(_T_1028, asSInt(UInt<13>(0h1000)))
node _T_1030 = asSInt(_T_1029)
node _T_1031 = eq(_T_1030, asSInt(UInt<1>(0h0)))
node _T_1032 = or(_T_1026, _T_1031)
node _T_1033 = and(_T_1021, _T_1032)
node _T_1034 = or(UInt<1>(0h0), _T_1033)
node _T_1035 = and(_T_1020, _T_1034)
node _T_1036 = asUInt(reset)
node _T_1037 = eq(_T_1036, UInt<1>(0h0))
when _T_1037 :
node _T_1038 = eq(_T_1035, UInt<1>(0h0))
when _T_1038 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1035, UInt<1>(0h1), "") : assert_46
node _T_1039 = asUInt(reset)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
when _T_1040 :
node _T_1041 = eq(source_ok, UInt<1>(0h0))
when _T_1041 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(is_aligned, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1045 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_T_1045, UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1045, UInt<1>(0h1), "") : assert_49
node _T_1049 = eq(io.in.a.bits.mask, mask)
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_50
node _T_1053 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(_T_1053, UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1053, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1057 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_52
node _source_ok_T_51 = eq(io.in.d.bits.source, UInt<6>(0h30))
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_52 = shr(io.in.d.bits.source, 2)
node _source_ok_T_53 = eq(_source_ok_T_52, UInt<4>(0h8))
node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54)
node _source_ok_T_56 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_58 = shr(io.in.d.bits.source, 2)
node _source_ok_T_59 = eq(_source_ok_T_58, UInt<4>(0h9))
node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60)
node _source_ok_T_62 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_64 = shr(io.in.d.bits.source, 2)
node _source_ok_T_65 = eq(_source_ok_T_64, UInt<4>(0ha))
node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66)
node _source_ok_T_68 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68)
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 1, 0)
node _source_ok_T_70 = shr(io.in.d.bits.source, 2)
node _source_ok_T_71 = eq(_source_ok_T_70, UInt<4>(0hb))
node _source_ok_T_72 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72)
node _source_ok_T_74 = leq(source_ok_uncommonBits_10, UInt<2>(0h3))
node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74)
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0)
node _source_ok_T_76 = shr(io.in.d.bits.source, 3)
node _source_ok_T_77 = eq(_source_ok_T_76, UInt<2>(0h2))
node _source_ok_T_78 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_79 = and(_source_ok_T_77, _source_ok_T_78)
node _source_ok_T_80 = leq(source_ok_uncommonBits_11, UInt<3>(0h7))
node _source_ok_T_81 = and(_source_ok_T_79, _source_ok_T_80)
node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 2, 0)
node _source_ok_T_82 = shr(io.in.d.bits.source, 3)
node _source_ok_T_83 = eq(_source_ok_T_82, UInt<1>(0h1))
node _source_ok_T_84 = leq(UInt<1>(0h0), source_ok_uncommonBits_12)
node _source_ok_T_85 = and(_source_ok_T_83, _source_ok_T_84)
node _source_ok_T_86 = leq(source_ok_uncommonBits_12, UInt<3>(0h7))
node _source_ok_T_87 = and(_source_ok_T_85, _source_ok_T_86)
node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 2, 0)
node _source_ok_T_88 = shr(io.in.d.bits.source, 3)
node _source_ok_T_89 = eq(_source_ok_T_88, UInt<1>(0h0))
node _source_ok_T_90 = leq(UInt<1>(0h0), source_ok_uncommonBits_13)
node _source_ok_T_91 = and(_source_ok_T_89, _source_ok_T_90)
node _source_ok_T_92 = leq(source_ok_uncommonBits_13, UInt<3>(0h7))
node _source_ok_T_93 = and(_source_ok_T_91, _source_ok_T_92)
node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_51
connect _source_ok_WIRE_1[1], _source_ok_T_57
connect _source_ok_WIRE_1[2], _source_ok_T_63
connect _source_ok_WIRE_1[3], _source_ok_T_69
connect _source_ok_WIRE_1[4], _source_ok_T_75
connect _source_ok_WIRE_1[5], _source_ok_T_81
connect _source_ok_WIRE_1[6], _source_ok_T_87
connect _source_ok_WIRE_1[7], _source_ok_T_93
connect _source_ok_WIRE_1[8], _source_ok_T_94
node _source_ok_T_95 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[2])
node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[3])
node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[4])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[5])
node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[6])
node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_101, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1061 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1061 :
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(source_ok_1, UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1065 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1066 = asUInt(reset)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
when _T_1067 :
node _T_1068 = eq(_T_1065, UInt<1>(0h0))
when _T_1068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1065, UInt<1>(0h1), "") : assert_54
node _T_1069 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1070 = asUInt(reset)
node _T_1071 = eq(_T_1070, UInt<1>(0h0))
when _T_1071 :
node _T_1072 = eq(_T_1069, UInt<1>(0h0))
when _T_1072 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1069, UInt<1>(0h1), "") : assert_55
node _T_1073 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1074 = asUInt(reset)
node _T_1075 = eq(_T_1074, UInt<1>(0h0))
when _T_1075 :
node _T_1076 = eq(_T_1073, UInt<1>(0h0))
when _T_1076 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1073, UInt<1>(0h1), "") : assert_56
node _T_1077 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1078 = asUInt(reset)
node _T_1079 = eq(_T_1078, UInt<1>(0h0))
when _T_1079 :
node _T_1080 = eq(_T_1077, UInt<1>(0h0))
when _T_1080 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1077, UInt<1>(0h1), "") : assert_57
node _T_1081 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1081 :
node _T_1082 = asUInt(reset)
node _T_1083 = eq(_T_1082, UInt<1>(0h0))
when _T_1083 :
node _T_1084 = eq(source_ok_1, UInt<1>(0h0))
when _T_1084 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(sink_ok, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1088 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(_T_1088, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1088, UInt<1>(0h1), "") : assert_60
node _T_1092 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_61
node _T_1096 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_62
node _T_1100 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_63
node _T_1104 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1105 = or(UInt<1>(0h0), _T_1104)
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(_T_1105, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1105, UInt<1>(0h1), "") : assert_64
node _T_1109 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1109 :
node _T_1110 = asUInt(reset)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
when _T_1111 :
node _T_1112 = eq(source_ok_1, UInt<1>(0h0))
when _T_1112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(sink_ok, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1116 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1117 = asUInt(reset)
node _T_1118 = eq(_T_1117, UInt<1>(0h0))
when _T_1118 :
node _T_1119 = eq(_T_1116, UInt<1>(0h0))
when _T_1119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1116, UInt<1>(0h1), "") : assert_67
node _T_1120 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_68
node _T_1124 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_69
node _T_1128 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1129 = or(_T_1128, io.in.d.bits.corrupt)
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_70
node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1134 = or(UInt<1>(0h0), _T_1133)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_71
node _T_1138 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(source_ok_1, UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1142 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(_T_1142, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1142, UInt<1>(0h1), "") : assert_73
node _T_1146 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1147 = asUInt(reset)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
when _T_1148 :
node _T_1149 = eq(_T_1146, UInt<1>(0h0))
when _T_1149 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1146, UInt<1>(0h1), "") : assert_74
node _T_1150 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1151 = or(UInt<1>(0h0), _T_1150)
node _T_1152 = asUInt(reset)
node _T_1153 = eq(_T_1152, UInt<1>(0h0))
when _T_1153 :
node _T_1154 = eq(_T_1151, UInt<1>(0h0))
when _T_1154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1151, UInt<1>(0h1), "") : assert_75
node _T_1155 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1155 :
node _T_1156 = asUInt(reset)
node _T_1157 = eq(_T_1156, UInt<1>(0h0))
when _T_1157 :
node _T_1158 = eq(source_ok_1, UInt<1>(0h0))
when _T_1158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1159 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1160 = asUInt(reset)
node _T_1161 = eq(_T_1160, UInt<1>(0h0))
when _T_1161 :
node _T_1162 = eq(_T_1159, UInt<1>(0h0))
when _T_1162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1159, UInt<1>(0h1), "") : assert_77
node _T_1163 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1164 = or(_T_1163, io.in.d.bits.corrupt)
node _T_1165 = asUInt(reset)
node _T_1166 = eq(_T_1165, UInt<1>(0h0))
when _T_1166 :
node _T_1167 = eq(_T_1164, UInt<1>(0h0))
when _T_1167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1164, UInt<1>(0h1), "") : assert_78
node _T_1168 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1169 = or(UInt<1>(0h0), _T_1168)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_79
node _T_1173 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1173 :
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(source_ok_1, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1177 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1178 = asUInt(reset)
node _T_1179 = eq(_T_1178, UInt<1>(0h0))
when _T_1179 :
node _T_1180 = eq(_T_1177, UInt<1>(0h0))
when _T_1180 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1177, UInt<1>(0h1), "") : assert_81
node _T_1181 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1182 = asUInt(reset)
node _T_1183 = eq(_T_1182, UInt<1>(0h0))
when _T_1183 :
node _T_1184 = eq(_T_1181, UInt<1>(0h0))
when _T_1184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1181, UInt<1>(0h1), "") : assert_82
node _T_1185 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1186 = or(UInt<1>(0h0), _T_1185)
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1190 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1194 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1195 = asUInt(reset)
node _T_1196 = eq(_T_1195, UInt<1>(0h0))
when _T_1196 :
node _T_1197 = eq(_T_1194, UInt<1>(0h0))
when _T_1197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1194, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1198 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1199 = asUInt(reset)
node _T_1200 = eq(_T_1199, UInt<1>(0h0))
when _T_1200 :
node _T_1201 = eq(_T_1198, UInt<1>(0h0))
when _T_1201 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1198, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1202 = eq(a_first, UInt<1>(0h0))
node _T_1203 = and(io.in.a.valid, _T_1202)
when _T_1203 :
node _T_1204 = eq(io.in.a.bits.opcode, opcode)
node _T_1205 = asUInt(reset)
node _T_1206 = eq(_T_1205, UInt<1>(0h0))
when _T_1206 :
node _T_1207 = eq(_T_1204, UInt<1>(0h0))
when _T_1207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1204, UInt<1>(0h1), "") : assert_87
node _T_1208 = eq(io.in.a.bits.param, param)
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(_T_1208, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1208, UInt<1>(0h1), "") : assert_88
node _T_1212 = eq(io.in.a.bits.size, size)
node _T_1213 = asUInt(reset)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
when _T_1214 :
node _T_1215 = eq(_T_1212, UInt<1>(0h0))
when _T_1215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1212, UInt<1>(0h1), "") : assert_89
node _T_1216 = eq(io.in.a.bits.source, source)
node _T_1217 = asUInt(reset)
node _T_1218 = eq(_T_1217, UInt<1>(0h0))
when _T_1218 :
node _T_1219 = eq(_T_1216, UInt<1>(0h0))
when _T_1219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1216, UInt<1>(0h1), "") : assert_90
node _T_1220 = eq(io.in.a.bits.address, address)
node _T_1221 = asUInt(reset)
node _T_1222 = eq(_T_1221, UInt<1>(0h0))
when _T_1222 :
node _T_1223 = eq(_T_1220, UInt<1>(0h0))
when _T_1223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1220, UInt<1>(0h1), "") : assert_91
node _T_1224 = and(io.in.a.ready, io.in.a.valid)
node _T_1225 = and(_T_1224, a_first)
when _T_1225 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1226 = eq(d_first, UInt<1>(0h0))
node _T_1227 = and(io.in.d.valid, _T_1226)
when _T_1227 :
node _T_1228 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1229 = asUInt(reset)
node _T_1230 = eq(_T_1229, UInt<1>(0h0))
when _T_1230 :
node _T_1231 = eq(_T_1228, UInt<1>(0h0))
when _T_1231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1228, UInt<1>(0h1), "") : assert_92
node _T_1232 = eq(io.in.d.bits.param, param_1)
node _T_1233 = asUInt(reset)
node _T_1234 = eq(_T_1233, UInt<1>(0h0))
when _T_1234 :
node _T_1235 = eq(_T_1232, UInt<1>(0h0))
when _T_1235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1232, UInt<1>(0h1), "") : assert_93
node _T_1236 = eq(io.in.d.bits.size, size_1)
node _T_1237 = asUInt(reset)
node _T_1238 = eq(_T_1237, UInt<1>(0h0))
when _T_1238 :
node _T_1239 = eq(_T_1236, UInt<1>(0h0))
when _T_1239 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1236, UInt<1>(0h1), "") : assert_94
node _T_1240 = eq(io.in.d.bits.source, source_1)
node _T_1241 = asUInt(reset)
node _T_1242 = eq(_T_1241, UInt<1>(0h0))
when _T_1242 :
node _T_1243 = eq(_T_1240, UInt<1>(0h0))
when _T_1243 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1240, UInt<1>(0h1), "") : assert_95
node _T_1244 = eq(io.in.d.bits.sink, sink)
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(_T_1244, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1244, UInt<1>(0h1), "") : assert_96
node _T_1248 = eq(io.in.d.bits.denied, denied)
node _T_1249 = asUInt(reset)
node _T_1250 = eq(_T_1249, UInt<1>(0h0))
when _T_1250 :
node _T_1251 = eq(_T_1248, UInt<1>(0h0))
when _T_1251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1248, UInt<1>(0h1), "") : assert_97
node _T_1252 = and(io.in.d.ready, io.in.d.valid)
node _T_1253 = and(_T_1252, d_first)
when _T_1253 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1254 = and(io.in.a.valid, a_first_1)
node _T_1255 = and(_T_1254, UInt<1>(0h1))
when _T_1255 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1256 = and(io.in.a.ready, io.in.a.valid)
node _T_1257 = and(_T_1256, a_first_1)
node _T_1258 = and(_T_1257, UInt<1>(0h1))
when _T_1258 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1259 = dshr(inflight, io.in.a.bits.source)
node _T_1260 = bits(_T_1259, 0, 0)
node _T_1261 = eq(_T_1260, UInt<1>(0h0))
node _T_1262 = asUInt(reset)
node _T_1263 = eq(_T_1262, UInt<1>(0h0))
when _T_1263 :
node _T_1264 = eq(_T_1261, UInt<1>(0h0))
when _T_1264 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1261, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1265 = and(io.in.d.valid, d_first_1)
node _T_1266 = and(_T_1265, UInt<1>(0h1))
node _T_1267 = eq(d_release_ack, UInt<1>(0h0))
node _T_1268 = and(_T_1266, _T_1267)
when _T_1268 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1269 = and(io.in.d.ready, io.in.d.valid)
node _T_1270 = and(_T_1269, d_first_1)
node _T_1271 = and(_T_1270, UInt<1>(0h1))
node _T_1272 = eq(d_release_ack, UInt<1>(0h0))
node _T_1273 = and(_T_1271, _T_1272)
when _T_1273 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1274 = and(io.in.d.valid, d_first_1)
node _T_1275 = and(_T_1274, UInt<1>(0h1))
node _T_1276 = eq(d_release_ack, UInt<1>(0h0))
node _T_1277 = and(_T_1275, _T_1276)
when _T_1277 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1278 = dshr(inflight, io.in.d.bits.source)
node _T_1279 = bits(_T_1278, 0, 0)
node _T_1280 = or(_T_1279, same_cycle_resp)
node _T_1281 = asUInt(reset)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
when _T_1282 :
node _T_1283 = eq(_T_1280, UInt<1>(0h0))
when _T_1283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1280, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1284 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1285 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1286 = or(_T_1284, _T_1285)
node _T_1287 = asUInt(reset)
node _T_1288 = eq(_T_1287, UInt<1>(0h0))
when _T_1288 :
node _T_1289 = eq(_T_1286, UInt<1>(0h0))
when _T_1289 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1286, UInt<1>(0h1), "") : assert_100
node _T_1290 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1291 = asUInt(reset)
node _T_1292 = eq(_T_1291, UInt<1>(0h0))
when _T_1292 :
node _T_1293 = eq(_T_1290, UInt<1>(0h0))
when _T_1293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1290, UInt<1>(0h1), "") : assert_101
else :
node _T_1294 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1295 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1296 = or(_T_1294, _T_1295)
node _T_1297 = asUInt(reset)
node _T_1298 = eq(_T_1297, UInt<1>(0h0))
when _T_1298 :
node _T_1299 = eq(_T_1296, UInt<1>(0h0))
when _T_1299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1296, UInt<1>(0h1), "") : assert_102
node _T_1300 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1301 = asUInt(reset)
node _T_1302 = eq(_T_1301, UInt<1>(0h0))
when _T_1302 :
node _T_1303 = eq(_T_1300, UInt<1>(0h0))
when _T_1303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1300, UInt<1>(0h1), "") : assert_103
node _T_1304 = and(io.in.d.valid, d_first_1)
node _T_1305 = and(_T_1304, a_first_1)
node _T_1306 = and(_T_1305, io.in.a.valid)
node _T_1307 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1308 = and(_T_1306, _T_1307)
node _T_1309 = eq(d_release_ack, UInt<1>(0h0))
node _T_1310 = and(_T_1308, _T_1309)
when _T_1310 :
node _T_1311 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1312 = or(_T_1311, io.in.a.ready)
node _T_1313 = asUInt(reset)
node _T_1314 = eq(_T_1313, UInt<1>(0h0))
when _T_1314 :
node _T_1315 = eq(_T_1312, UInt<1>(0h0))
when _T_1315 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1312, UInt<1>(0h1), "") : assert_104
node _T_1316 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1317 = orr(a_set_wo_ready)
node _T_1318 = eq(_T_1317, UInt<1>(0h0))
node _T_1319 = or(_T_1316, _T_1318)
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(_T_1319, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1319, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_16
node _T_1323 = orr(inflight)
node _T_1324 = eq(_T_1323, UInt<1>(0h0))
node _T_1325 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1326 = or(_T_1324, _T_1325)
node _T_1327 = lt(watchdog, plusarg_reader.out)
node _T_1328 = or(_T_1326, _T_1327)
node _T_1329 = asUInt(reset)
node _T_1330 = eq(_T_1329, UInt<1>(0h0))
when _T_1330 :
node _T_1331 = eq(_T_1328, UInt<1>(0h0))
when _T_1331 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1328, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1332 = and(io.in.a.ready, io.in.a.valid)
node _T_1333 = and(io.in.d.ready, io.in.d.valid)
node _T_1334 = or(_T_1332, _T_1333)
when _T_1334 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1335 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1336 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1337 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1338 = and(_T_1336, _T_1337)
node _T_1339 = and(_T_1335, _T_1338)
when _T_1339 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1340 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1341 = and(_T_1340, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1342 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1343 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1344 = and(_T_1342, _T_1343)
node _T_1345 = and(_T_1341, _T_1344)
when _T_1345 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1346 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1347 = bits(_T_1346, 0, 0)
node _T_1348 = eq(_T_1347, UInt<1>(0h0))
node _T_1349 = asUInt(reset)
node _T_1350 = eq(_T_1349, UInt<1>(0h0))
when _T_1350 :
node _T_1351 = eq(_T_1348, UInt<1>(0h0))
when _T_1351 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1348, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1352 = and(io.in.d.valid, d_first_2)
node _T_1353 = and(_T_1352, UInt<1>(0h1))
node _T_1354 = and(_T_1353, d_release_ack_1)
when _T_1354 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1355 = and(io.in.d.ready, io.in.d.valid)
node _T_1356 = and(_T_1355, d_first_2)
node _T_1357 = and(_T_1356, UInt<1>(0h1))
node _T_1358 = and(_T_1357, d_release_ack_1)
when _T_1358 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1359 = and(io.in.d.valid, d_first_2)
node _T_1360 = and(_T_1359, UInt<1>(0h1))
node _T_1361 = and(_T_1360, d_release_ack_1)
when _T_1361 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1362 = dshr(inflight_1, io.in.d.bits.source)
node _T_1363 = bits(_T_1362, 0, 0)
node _T_1364 = or(_T_1363, same_cycle_resp_1)
node _T_1365 = asUInt(reset)
node _T_1366 = eq(_T_1365, UInt<1>(0h0))
when _T_1366 :
node _T_1367 = eq(_T_1364, UInt<1>(0h0))
when _T_1367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1364, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1368 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(_T_1368, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1368, UInt<1>(0h1), "") : assert_109
else :
node _T_1372 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1373 = asUInt(reset)
node _T_1374 = eq(_T_1373, UInt<1>(0h0))
when _T_1374 :
node _T_1375 = eq(_T_1372, UInt<1>(0h0))
when _T_1375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1372, UInt<1>(0h1), "") : assert_110
node _T_1376 = and(io.in.d.valid, d_first_2)
node _T_1377 = and(_T_1376, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1378 = and(_T_1377, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1379 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1380 = and(_T_1378, _T_1379)
node _T_1381 = and(_T_1380, d_release_ack_1)
node _T_1382 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1383 = and(_T_1381, _T_1382)
when _T_1383 :
node _T_1384 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1385 = or(_T_1384, _WIRE_27.ready)
node _T_1386 = asUInt(reset)
node _T_1387 = eq(_T_1386, UInt<1>(0h0))
when _T_1387 :
node _T_1388 = eq(_T_1385, UInt<1>(0h0))
when _T_1388 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1385, UInt<1>(0h1), "") : assert_111
node _T_1389 = orr(c_set_wo_ready)
when _T_1389 :
node _T_1390 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1391 = asUInt(reset)
node _T_1392 = eq(_T_1391, UInt<1>(0h0))
when _T_1392 :
node _T_1393 = eq(_T_1390, UInt<1>(0h0))
when _T_1393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1390, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_17
node _T_1394 = orr(inflight_1)
node _T_1395 = eq(_T_1394, UInt<1>(0h0))
node _T_1396 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1397 = or(_T_1395, _T_1396)
node _T_1398 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1399 = or(_T_1397, _T_1398)
node _T_1400 = asUInt(reset)
node _T_1401 = eq(_T_1400, UInt<1>(0h0))
when _T_1401 :
node _T_1402 = eq(_T_1399, UInt<1>(0h0))
when _T_1402 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1399, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1403 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1404 = and(io.in.d.ready, io.in.d.valid)
node _T_1405 = or(_T_1403, _T_1404)
when _T_1405 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_8( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_86 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_92 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_37 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_38 = _source_ok_T_37 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire _source_ok_T_44 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_50 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_51 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_51; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_52 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_58 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_64 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_70 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_53 = _source_ok_T_52 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_57; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_59 = _source_ok_T_58 == 5'h9; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_63; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_65 = _source_ok_T_64 == 5'hA; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_69; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_71 = _source_ok_T_70 == 5'hB; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_75; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_76 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_82 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_88 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_77 = _source_ok_T_76 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_81; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_83 = _source_ok_T_82 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_87 = _source_ok_T_85; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_89 = _source_ok_T_88 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_93 = _source_ok_T_91; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_7 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_94; // @[Parameters.scala:1138:31]
wire _source_ok_T_95 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_101 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1332 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1332; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1332; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1405 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1405; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1405; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1405; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1258 = _T_1332 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1258 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1258 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1258 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1258 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1258 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1304 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1304 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1273 = _T_1405 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1273 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1273 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1273 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1376 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1376 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1358 = _T_1405 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1358 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1358 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1358 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_6 :
output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags)
node _sigSum_T = bits(io.mulAddResult, 48, 48)
node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1))
node _sigSum_T_2 = tail(_sigSum_T_1, 1)
node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC)
node _sigSum_T_4 = bits(io.mulAddResult, 47, 0)
node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4)
node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC)
node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags)
node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T)
node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1)
node CDom_sExp = asSInt(_CDom_sExp_T_2)
node _CDom_absSigSum_T = bits(sigSum, 74, 25)
node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T)
node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24)
node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2)
node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26)
node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4)
node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5)
node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1)
node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T)
node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1)
node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1)
node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3)
node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4)
node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist)
node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21)
node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0)
node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3)
wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0)
node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T)
connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1
node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4)
node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T)
connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1
node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8)
node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T)
connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1
node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12)
node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T)
connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1
node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16)
node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T)
connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1
node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20)
node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T)
connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1
node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24)
node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T)
connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1
node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1])
node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0])
node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3])
node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5])
node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo)
node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo)
node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2)
node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3)
node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4)
node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1)
node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0)
node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0)
node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0)
node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1)
node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9)
node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2)
node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0)
node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1)
node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13)
node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14)
node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4)
node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0)
node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1)
node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18)
node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19)
node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20)
node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21)
node _CDom_sig_T = shr(CDom_mainSig, 3)
node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0)
node _CDom_sig_T_2 = orr(_CDom_sig_T_1)
node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra)
node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra)
node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4)
node notCDom_signSigSum = bits(sigSum, 51, 51)
node _notCDom_absSigSum_T = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T)
node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags)
node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1)
node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4)
wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26]
node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0)
node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T)
connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2)
node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T)
connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4)
node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T)
connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6)
node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T)
connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8)
node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T)
connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10)
node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T)
connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12)
node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T)
connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14)
node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T)
connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16)
node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T)
connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18)
node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T)
connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20)
node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T)
connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22)
node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T)
connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24)
node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T)
connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26)
node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T)
connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28)
node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T)
connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30)
node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T)
connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32)
node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T)
connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34)
node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T)
connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36)
node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T)
connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38)
node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T)
connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40)
node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T)
connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42)
node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T)
connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44)
node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T)
connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46)
node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T)
connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48)
node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T)
connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50)
node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T)
connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1
node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1])
node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0])
node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4])
node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3])
node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo)
node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7])
node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6])
node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9])
node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11])
node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo)
node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo)
node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo)
node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14])
node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13])
node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17])
node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16])
node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo)
node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20])
node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19])
node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22])
node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24])
node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo)
node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo)
node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0)
node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1)
node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2)
node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3)
node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4)
node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5)
node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6)
node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7)
node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8)
node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9)
node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10)
node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11)
node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12)
node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13)
node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14)
node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15)
node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16)
node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17)
node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18)
node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19)
node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20)
node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21)
node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22)
node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23)
node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24)
node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25)
node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19))
node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26)
node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27)
node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28)
node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29)
node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30)
node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31)
node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32)
node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33)
node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34)
node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35)
node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36)
node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37)
node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38)
node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39)
node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40)
node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41)
node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42)
node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43)
node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44)
node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45)
node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46)
node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47)
node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48)
node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49)
node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1)
node _notCDom_sExp_T = cvt(notCDom_nearNormDist)
node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T)
node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1)
node notCDom_sExp = asSInt(_notCDom_sExp_T_2)
node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist)
node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23)
node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0)
node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0)
wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0)
node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T)
connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1
node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2)
node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T)
connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1
node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4)
node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T)
connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1
node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6)
node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T)
connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1
node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8)
node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T)
connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1
node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10)
node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T)
connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1
node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12)
node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T)
connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1
node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1])
node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0])
node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3])
node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5])
node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo)
node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo)
node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1)
node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3)
node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4)
node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1)
node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0)
node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0)
node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0)
node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1)
node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9)
node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2)
node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0)
node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1)
node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13)
node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14)
node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4)
node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0)
node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1)
node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18)
node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19)
node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20)
node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21)
node _notCDom_sig_T = shr(notCDom_mainSig, 3)
node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0)
node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1)
node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra)
node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3)
node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25)
node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0))
node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum)
node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T)
node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC)
node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB)
node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC)
node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB)
node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T)
node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB)
node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2)
node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0))
node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC)
node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags)
node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8)
connect io.invalidExc, _io_invalidExc_T_9
node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.isInf, notNaN_isInfOut
node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0))
node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation)
node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1)
connect io.rawOut.isZero, _io_rawOut_isZero_T_2
node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd)
node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC)
node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1)
node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0))
node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3)
node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd)
node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC)
node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6)
node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min)
node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC)
node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9)
node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10)
node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0))
node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0))
node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13)
node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign)
node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15)
node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16)
connect io.rawOut.sign, _io_rawOut_sign_T_17
node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
connect io.rawOut.sExp, _io_rawOut_sExp_T
node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
connect io.rawOut.sig, _io_rawOut_sig_T | module MulAddRecFNToRaw_postMul_e8_s24_6( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16]
wire io_fromPreMul_isZeroC = 1'h1; // @[MulAddRecFN.scala:169:7]
wire _io_rawOut_isZero_T = 1'h1; // @[MulAddRecFN.scala:283:14]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire io_fromPreMul_isNaNC = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant = 1'h0; // @[MulAddRecFN.scala:169:7]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire _io_invalidExc_T_7 = 1'h0; // @[MulAddRecFN.scala:275:61]
wire _io_invalidExc_T_8 = 1'h0; // @[MulAddRecFN.scala:276:35]
wire _io_rawOut_sign_T_1 = 1'h0; // @[MulAddRecFN.scala:286:31]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
assign _io_rawOut_sExp_T = notCDom_sExp; // @[MulAddRecFN.scala:241:46, :293:26]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
assign _io_rawOut_sig_T = notCDom_sig; // @[MulAddRecFN.scala:251:12, :294:25]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _io_rawOut_isZero_T_1 = notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:42]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
wire _io_rawOut_sign_T_15 = notCDom_sign; // @[MulAddRecFN.scala:257:12, :292:17]
wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49]
assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49]
wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36]
assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36]
assign notNaN_isInfOut = notNaN_isInfProd; // @[MulAddRecFN.scala:264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire notNaN_addZeros = _notNaN_addZeros_T; // @[MulAddRecFN.scala:267:{32,58}]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31]
wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3; // @[MulAddRecFN.scala:272:57, :273:57]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T; // @[MulAddRecFN.scala:285:{27,54}]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_25 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_234
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_235
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_236
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_237
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_25( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_234 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_235 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_236 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_237 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_384 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_128
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_384( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_128 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ErrorDeviceWrapper :
input clock : Clock
input reset : Reset
output auto : { flip buffer_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<10>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
inst error of TLError
connect error.clock, clock
connect error.reset, reset
inst buffer of TLBuffer_a14d64s10k1z4u
connect buffer.clock, clock
connect buffer.reset, reset
connect error.auto.in, buffer.auto.out
connect buffer.auto.in, auto.buffer_in
extmodule plusarg_reader_78 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_79 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module ErrorDeviceWrapper( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
output auto_buffer_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_buffer_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_buffer_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_buffer_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_buffer_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_buffer_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_buffer_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_buffer_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28]
wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28]
wire [3:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28]
wire [9:0] _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28]
wire [13:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28]
wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28]
wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28]
wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28]
wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28]
wire _error_auto_in_a_ready; // @[CanHaveBuiltInDevices.scala:40:29]
wire _error_auto_in_d_valid; // @[CanHaveBuiltInDevices.scala:40:29]
wire [2:0] _error_auto_in_d_bits_opcode; // @[CanHaveBuiltInDevices.scala:40:29]
wire [3:0] _error_auto_in_d_bits_size; // @[CanHaveBuiltInDevices.scala:40:29]
wire [9:0] _error_auto_in_d_bits_source; // @[CanHaveBuiltInDevices.scala:40:29]
wire _error_auto_in_d_bits_corrupt; // @[CanHaveBuiltInDevices.scala:40:29]
wire auto_buffer_in_a_valid_0 = auto_buffer_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_a_bits_opcode_0 = auto_buffer_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_a_bits_param_0 = auto_buffer_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_buffer_in_a_bits_size_0 = auto_buffer_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [9:0] auto_buffer_in_a_bits_source_0 = auto_buffer_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [13:0] auto_buffer_in_a_bits_address_0 = auto_buffer_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_buffer_in_a_bits_mask_0 = auto_buffer_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_buffer_in_a_bits_data_0 = auto_buffer_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_a_bits_corrupt_0 = auto_buffer_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_ready_0 = auto_buffer_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_buffer_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_buffer_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [9:0] auto_buffer_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_buffer_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
TLError error ( // @[CanHaveBuiltInDevices.scala:40:29]
.clock (clock),
.reset (reset),
.auto_in_a_ready (_error_auto_in_a_ready),
.auto_in_a_valid (_buffer_auto_out_a_valid), // @[Buffer.scala:75:28]
.auto_in_a_bits_opcode (_buffer_auto_out_a_bits_opcode), // @[Buffer.scala:75:28]
.auto_in_a_bits_param (_buffer_auto_out_a_bits_param), // @[Buffer.scala:75:28]
.auto_in_a_bits_size (_buffer_auto_out_a_bits_size), // @[Buffer.scala:75:28]
.auto_in_a_bits_source (_buffer_auto_out_a_bits_source), // @[Buffer.scala:75:28]
.auto_in_a_bits_address (_buffer_auto_out_a_bits_address), // @[Buffer.scala:75:28]
.auto_in_a_bits_mask (_buffer_auto_out_a_bits_mask), // @[Buffer.scala:75:28]
.auto_in_a_bits_data (_buffer_auto_out_a_bits_data), // @[Buffer.scala:75:28]
.auto_in_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), // @[Buffer.scala:75:28]
.auto_in_d_ready (_buffer_auto_out_d_ready), // @[Buffer.scala:75:28]
.auto_in_d_valid (_error_auto_in_d_valid),
.auto_in_d_bits_opcode (_error_auto_in_d_bits_opcode),
.auto_in_d_bits_size (_error_auto_in_d_bits_size),
.auto_in_d_bits_source (_error_auto_in_d_bits_source),
.auto_in_d_bits_corrupt (_error_auto_in_d_bits_corrupt)
); // @[CanHaveBuiltInDevices.scala:40:29]
TLBuffer_a14d64s10k1z4u buffer ( // @[Buffer.scala:75:28]
.clock (clock),
.reset (reset),
.auto_in_a_ready (auto_buffer_in_a_ready_0),
.auto_in_a_valid (auto_buffer_in_a_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_opcode (auto_buffer_in_a_bits_opcode_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_param (auto_buffer_in_a_bits_param_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_size (auto_buffer_in_a_bits_size_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_source (auto_buffer_in_a_bits_source_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_address (auto_buffer_in_a_bits_address_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_mask (auto_buffer_in_a_bits_mask_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_data (auto_buffer_in_a_bits_data_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_corrupt (auto_buffer_in_a_bits_corrupt_0), // @[LazyModuleImp.scala:138:7]
.auto_in_d_ready (auto_buffer_in_d_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_in_d_valid (auto_buffer_in_d_valid_0),
.auto_in_d_bits_opcode (auto_buffer_in_d_bits_opcode_0),
.auto_in_d_bits_param (auto_buffer_in_d_bits_param_0),
.auto_in_d_bits_size (auto_buffer_in_d_bits_size_0),
.auto_in_d_bits_source (auto_buffer_in_d_bits_source_0),
.auto_in_d_bits_sink (auto_buffer_in_d_bits_sink_0),
.auto_in_d_bits_denied (auto_buffer_in_d_bits_denied_0),
.auto_in_d_bits_data (auto_buffer_in_d_bits_data_0),
.auto_in_d_bits_corrupt (auto_buffer_in_d_bits_corrupt_0),
.auto_out_a_ready (_error_auto_in_a_ready), // @[CanHaveBuiltInDevices.scala:40:29]
.auto_out_a_valid (_buffer_auto_out_a_valid),
.auto_out_a_bits_opcode (_buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_buffer_auto_out_a_bits_param),
.auto_out_a_bits_size (_buffer_auto_out_a_bits_size),
.auto_out_a_bits_source (_buffer_auto_out_a_bits_source),
.auto_out_a_bits_address (_buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask (_buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data (_buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready (_buffer_auto_out_d_ready),
.auto_out_d_valid (_error_auto_in_d_valid), // @[CanHaveBuiltInDevices.scala:40:29]
.auto_out_d_bits_opcode (_error_auto_in_d_bits_opcode), // @[CanHaveBuiltInDevices.scala:40:29]
.auto_out_d_bits_size (_error_auto_in_d_bits_size), // @[CanHaveBuiltInDevices.scala:40:29]
.auto_out_d_bits_source (_error_auto_in_d_bits_source), // @[CanHaveBuiltInDevices.scala:40:29]
.auto_out_d_bits_corrupt (_error_auto_in_d_bits_corrupt) // @[CanHaveBuiltInDevices.scala:40:29]
); // @[Buffer.scala:75:28]
assign auto_buffer_in_a_ready = auto_buffer_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_valid = auto_buffer_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_opcode = auto_buffer_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_param = auto_buffer_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_size = auto_buffer_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_source = auto_buffer_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_sink = auto_buffer_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_denied = auto_buffer_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_data = auto_buffer_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_corrupt = auto_buffer_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_382 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_382( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module TileResetSetter :
input clock : Clock
input reset : Reset
output auto : { flip clock_in : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, flip tl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire tlNodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlNodeIn.d.bits.corrupt
invalidate tlNodeIn.d.bits.data
invalidate tlNodeIn.d.bits.denied
invalidate tlNodeIn.d.bits.sink
invalidate tlNodeIn.d.bits.source
invalidate tlNodeIn.d.bits.size
invalidate tlNodeIn.d.bits.param
invalidate tlNodeIn.d.bits.opcode
invalidate tlNodeIn.d.valid
invalidate tlNodeIn.d.ready
invalidate tlNodeIn.a.bits.corrupt
invalidate tlNodeIn.a.bits.data
invalidate tlNodeIn.a.bits.mask
invalidate tlNodeIn.a.bits.address
invalidate tlNodeIn.a.bits.source
invalidate tlNodeIn.a.bits.size
invalidate tlNodeIn.a.bits.param
invalidate tlNodeIn.a.bits.opcode
invalidate tlNodeIn.a.valid
invalidate tlNodeIn.a.ready
inst monitor of TLMonitor_65
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, tlNodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, tlNodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, tlNodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, tlNodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, tlNodeIn.d.bits.source
connect monitor.io.in.d.bits.size, tlNodeIn.d.bits.size
connect monitor.io.in.d.bits.param, tlNodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, tlNodeIn.d.bits.opcode
connect monitor.io.in.d.valid, tlNodeIn.d.valid
connect monitor.io.in.d.ready, tlNodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, tlNodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, tlNodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, tlNodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, tlNodeIn.a.bits.address
connect monitor.io.in.a.bits.source, tlNodeIn.a.bits.source
connect monitor.io.in.a.bits.size, tlNodeIn.a.bits.size
connect monitor.io.in.a.bits.param, tlNodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, tlNodeIn.a.bits.opcode
connect monitor.io.in.a.valid, tlNodeIn.a.valid
connect monitor.io.in.a.ready, tlNodeIn.a.ready
wire clockNodeOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}
invalidate clockNodeOut.member.allClocks_uncore.reset
invalidate clockNodeOut.member.allClocks_uncore.clock
wire clockNodeIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}
invalidate clockNodeIn.member.allClocks_uncore.reset
invalidate clockNodeIn.member.allClocks_uncore.clock
connect clockNodeOut, clockNodeIn
connect tlNodeIn, auto.tl_in
connect auto.clock_out, clockNodeOut
connect clockNodeIn, auto.clock_in
wire tile_async_resets : Reset[1]
node _tile_async_resets_0_T = asAsyncReset(UInt<1>(0h1))
connect tile_async_resets[0], _tile_async_resets_0_T
inst r_tile_resets_0 of AsyncResetRegVec_w1_i0_6
connect r_tile_resets_0.clock, clock
connect r_tile_resets_0.reset, tile_async_resets[0]
wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
node _in_bits_read_T = eq(tlNodeIn.a.bits.opcode, UInt<3>(0h4))
connect in.bits.read, _in_bits_read_T
node _in_bits_index_T = shr(tlNodeIn.a.bits.address, 3)
connect in.bits.index, _in_bits_index_T
connect in.bits.data, tlNodeIn.a.bits.data
connect in.bits.mask, tlNodeIn.a.bits.mask
connect in.bits.extra.tlrr_extra.source, tlNodeIn.a.bits.source
connect in.bits.extra.tlrr_extra.size, tlNodeIn.a.bits.size
wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}}
connect out_front.bits, in.bits
node out_maskMatch = not(UInt<9>(0h0))
node out_findex = and(out_front.bits.index, out_maskMatch)
node out_bindex = and(out_front.bits.index, out_maskMatch)
node _out_T = eq(out_findex, UInt<9>(0h0))
node _out_T_1 = eq(out_bindex, UInt<9>(0h0))
wire out_rivalid : UInt<1>[1]
wire out_wivalid : UInt<1>[1]
wire out_roready : UInt<1>[1]
wire out_woready : UInt<1>[1]
node _out_frontMask_T = bits(out_front.bits.mask, 0, 0)
node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8)
node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10)
node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo)
node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12)
node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14)
node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo)
node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo)
node _out_backMask_T = bits(out_front.bits.mask, 0, 0)
node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1)
node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2)
node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3)
node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4)
node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5)
node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6)
node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7)
node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8)
node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10)
node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo)
node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12)
node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14)
node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo)
node out_backMask = cat(out_backMask_hi, out_backMask_lo)
node _out_rimask_T = bits(out_frontMask, 0, 0)
node out_rimask = orr(_out_rimask_T)
node _out_wimask_T = bits(out_frontMask, 0, 0)
node out_wimask = andr(_out_wimask_T)
node _out_romask_T = bits(out_backMask, 0, 0)
node out_romask = orr(_out_romask_T)
node _out_womask_T = bits(out_backMask, 0, 0)
node out_womask = andr(_out_womask_T)
node out_f_rivalid = and(out_rivalid[0], out_rimask)
node out_f_roready = and(out_roready[0], out_romask)
node out_f_wivalid = and(out_wivalid[0], out_wimask)
node out_f_woready = and(out_woready[0], out_womask)
node _out_T_2 = bits(out_front.bits.data, 0, 0)
connect r_tile_resets_0.io.en, out_f_woready
connect r_tile_resets_0.io.d, _out_T_2
node _out_T_3 = eq(out_rimask, UInt<1>(0h0))
node _out_T_4 = eq(out_wimask, UInt<1>(0h0))
node _out_T_5 = eq(out_romask, UInt<1>(0h0))
node _out_T_6 = eq(out_womask, UInt<1>(0h0))
node _out_T_7 = or(r_tile_resets_0.io.q, UInt<1>(0h0))
node _out_T_8 = bits(_out_T_7, 0, 0)
node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
node out_frontSel_0 = bits(_out_frontSel_T, 0, 0)
node out_frontSel_1 = bits(_out_frontSel_T, 1, 1)
node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0))
node out_backSel_0 = bits(_out_backSel_T, 0, 0)
node out_backSel_1 = bits(_out_backSel_T, 1, 1)
node _out_rifireMux_T = and(in.valid, out_front.ready)
node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read)
wire out_rifireMux_out : UInt<1>
node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0)
node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T)
connect out_rifireMux_out, UInt<1>(0h1)
connect out_rivalid[0], _out_rifireMux_T_3
node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0))
node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4)
node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_rifireMux_WIRE : UInt<1>[1]
connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5
node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0])
node _out_wifireMux_T = and(in.valid, out_front.ready)
node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1)
wire out_wifireMux_out : UInt<1>
node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0)
node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T)
connect out_wifireMux_out, UInt<1>(0h1)
connect out_wivalid[0], _out_wifireMux_T_4
node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0))
node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5)
node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_wifireMux_WIRE : UInt<1>[1]
connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6
node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0])
node _out_rofireMux_T = and(out_front.valid, out.ready)
node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read)
wire out_rofireMux_out : UInt<1>
node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0)
node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1)
connect out_rofireMux_out, UInt<1>(0h1)
connect out_roready[0], _out_rofireMux_T_3
node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0))
node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4)
node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_rofireMux_WIRE : UInt<1>[1]
connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5
node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0])
node _out_wofireMux_T = and(out_front.valid, out.ready)
node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0))
node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1)
wire out_wofireMux_out : UInt<1>
node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0)
node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1)
connect out_wofireMux_out, UInt<1>(0h1)
connect out_woready[0], _out_wofireMux_T_4
node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0))
node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5)
node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_wofireMux_WIRE : UInt<1>[1]
connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6
node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0])
node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux)
node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux)
node _out_in_ready_T = and(out_front.ready, out_iready)
connect in.ready, _out_in_ready_T
node _out_front_valid_T = and(in.valid, out_iready)
connect out_front.valid, _out_front_valid_T
node _out_front_ready_T = and(out.ready, out_oready)
connect out_front.ready, _out_front_ready_T
node _out_out_valid_T = and(out_front.valid, out_oready)
connect out.valid, _out_out_valid_T
connect out.bits.read, out_front.bits.read
node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_out_bits_data_WIRE : UInt<1>[1]
connect _out_out_bits_data_WIRE[0], _out_T_1
node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0])
node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1))
wire _out_out_bits_data_WIRE_1 : UInt<1>[1]
connect _out_out_bits_data_WIRE_1[0], _out_T_8
node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0])
node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0))
connect out.bits.data, _out_out_bits_data_T_4
connect out.bits.extra, out_front.bits.extra
connect in.valid, tlNodeIn.a.valid
connect tlNodeIn.a.ready, in.ready
connect tlNodeIn.d.valid, out.valid
connect out.ready, tlNodeIn.d.ready
wire tlNodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect tlNodeIn_d_bits_d.opcode, UInt<1>(0h0)
connect tlNodeIn_d_bits_d.param, UInt<1>(0h0)
connect tlNodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size
connect tlNodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source
connect tlNodeIn_d_bits_d.sink, UInt<1>(0h0)
connect tlNodeIn_d_bits_d.denied, UInt<1>(0h0)
invalidate tlNodeIn_d_bits_d.data
connect tlNodeIn_d_bits_d.corrupt, UInt<1>(0h0)
connect tlNodeIn.d.bits.corrupt, tlNodeIn_d_bits_d.corrupt
connect tlNodeIn.d.bits.data, tlNodeIn_d_bits_d.data
connect tlNodeIn.d.bits.denied, tlNodeIn_d_bits_d.denied
connect tlNodeIn.d.bits.sink, tlNodeIn_d_bits_d.sink
connect tlNodeIn.d.bits.source, tlNodeIn_d_bits_d.source
connect tlNodeIn.d.bits.size, tlNodeIn_d_bits_d.size
connect tlNodeIn.d.bits.param, tlNodeIn_d_bits_d.param
connect tlNodeIn.d.bits.opcode, tlNodeIn_d_bits_d.opcode
connect tlNodeIn.d.bits.data, out.bits.data
node _tlNodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0))
connect tlNodeIn.d.bits.opcode, _tlNodeIn_d_bits_opcode_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<21>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<21>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
connect clockNodeOut.member.allClocks_uncore.clock, clockNodeIn.member.allClocks_uncore.clock
connect clockNodeOut.member.allClocks_uncore.reset, clockNodeIn.member.allClocks_uncore.reset
extmodule plusarg_reader_135 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_136 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TileResetSetter( // @[TileResetSetter.scala:26:25]
input clock, // @[TileResetSetter.scala:26:25]
input reset, // @[TileResetSetter.scala:26:25]
input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25]
);
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire auto_clock_in_member_allClocks_uncore_clock_0 = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25]
wire auto_clock_in_member_allClocks_uncore_reset_0 = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25]
wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[TileResetSetter.scala:26:25]
wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[TileResetSetter.scala:26:25]
wire [1:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25]
wire [10:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25]
wire [20:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[TileResetSetter.scala:26:25]
wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[TileResetSetter.scala:26:25]
wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25]
wire [1:0] _out_frontSel_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _out_backSel_T = 2'h1; // @[OneHot.scala:58:35]
wire [8:0] out_maskMatch = 9'h1FF; // @[RegisterRouter.scala:87:24]
wire tile_async_resets_0 = 1'h1; // @[TileResetSetter.scala:29:33]
wire _tile_async_resets_0_T = 1'h1; // @[TileResetSetter.scala:31:38]
wire out_frontSel_0 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_backSel_0 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24]
wire [2:0] tlNodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [1:0] auto_tl_in_d_bits_param = 2'h0; // @[TileResetSetter.scala:26:25]
wire [1:0] tlNodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire auto_tl_in_d_bits_sink = 1'h0; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_d_bits_denied = 1'h0; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_d_bits_corrupt = 1'h0; // @[TileResetSetter.scala:26:25]
wire tlNodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _out_T_7 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_8 = 1'h0; // @[RegisterRouter.scala:87:24]
wire out_frontSel_1 = 1'h0; // @[RegisterRouter.scala:87:24]
wire out_backSel_1 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_6 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_7 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_WIRE_1_0 = 1'h0; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_T_3 = 1'h0; // @[MuxLiteral.scala:49:10]
wire _out_out_bits_data_T_4 = 1'h0; // @[RegisterRouter.scala:87:24]
wire tlNodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire tlNodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire tlNodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [63:0] auto_tl_in_d_bits_data = 64'h0; // @[TileResetSetter.scala:26:25]
wire [63:0] tlNodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] out_bits_data = 64'h0; // @[RegisterRouter.scala:87:24]
wire [63:0] tlNodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire clockNodeIn_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock_0; // @[MixedNode.scala:551:17]
wire clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17]
wire clockNodeIn_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset_0; // @[MixedNode.scala:551:17]
wire clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17]
wire tlNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire tlNodeIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17]
wire [2:0] tlNodeIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17]
wire [2:0] tlNodeIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17]
wire [10:0] tlNodeIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17]
wire [20:0] tlNodeIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17]
wire [7:0] tlNodeIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17]
wire [63:0] tlNodeIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17]
wire tlNodeIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17]
wire tlNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25]
wire auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25]
wire [2:0] auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25]
wire [1:0] auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25]
wire [10:0] auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25]
wire auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign auto_tl_in_a_ready_0 = tlNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire in_valid = tlNodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = tlNodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [10:0] in_bits_extra_tlrr_extra_source = tlNodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = tlNodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = tlNodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = tlNodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign auto_tl_in_d_valid_0 = tlNodeIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_tl_in_d_bits_opcode_0 = tlNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign auto_tl_in_d_bits_size_0 = tlNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [10:0] tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign auto_tl_in_d_bits_source_0 = tlNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_clock_out_member_allClocks_uncore_clock_0 = clockNodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17]
assign auto_clock_out_member_allClocks_uncore_reset_0 = clockNodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17]
assign clockNodeOut_member_allClocks_uncore_clock = clockNodeIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNodeOut_member_allClocks_uncore_reset = clockNodeIn_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17, :551:17]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = tlNodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [17:0] _in_bits_index_T = tlNodeIn_a_bits_address[20:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire _tlNodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign tlNodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign tlNodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24]
assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex = out_front_bits_index; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex = out_front_bits_index; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire _out_T = out_findex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24]
wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24]
wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
wire _out_T_2 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24]
wire _out_T_3 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_4 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_5 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_6 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire _GEN = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_T_1 = _out_out_bits_data_WIRE_0; // @[MuxLiteral.scala:49:{10,48}]
assign tlNodeIn_d_bits_size = tlNodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign tlNodeIn_d_bits_source = tlNodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign tlNodeIn_d_bits_opcode = {2'h0, _tlNodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
TLMonitor_65 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (tlNodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (tlNodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (tlNodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (tlNodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (tlNodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (tlNodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (tlNodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (tlNodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (tlNodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (tlNodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (tlNodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (tlNodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (tlNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (tlNodeIn_d_bits_source) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
AsyncResetRegVec_w1_i0_6 r_tile_resets_0 ( // @[TileResetSetter.scala:33:15]
.clock (clock),
.io_d (_out_T_2), // @[RegisterRouter.scala:87:24]
.io_en (out_f_woready) // @[RegisterRouter.scala:87:24]
); // @[TileResetSetter.scala:33:15]
assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_out_member_allClocks_uncore_clock_0; // @[TileResetSetter.scala:26:25]
assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_out_member_allClocks_uncore_reset_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[TileResetSetter.scala:26:25]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_12 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T = shr(io.in.a.bits.source, 2)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_6 = shr(io.in.a.bits.source, 2)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_12 = shr(io.in.a.bits.source, 2)
node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2))
node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14)
node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_18 = shr(io.in.a.bits.source, 2)
node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3))
node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20)
node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22)
wire _source_ok_WIRE : UInt<1>[4]
connect _source_ok_WIRE[0], _source_ok_T_5
connect _source_ok_WIRE[1], _source_ok_T_11
connect _source_ok_WIRE[2], _source_ok_T_17
connect _source_ok_WIRE[3], _source_ok_T_23
node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2])
node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_4 = shr(io.in.a.bits.source, 2)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<2>(0h3))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_17 = shr(io.in.a.bits.source, 2)
node _T_18 = eq(_T_17, UInt<1>(0h1))
node _T_19 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_20 = and(_T_18, _T_19)
node _T_21 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_25 = cvt(_T_24)
node _T_26 = and(_T_25, asSInt(UInt<1>(0h0)))
node _T_27 = asSInt(_T_26)
node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0)))
node _T_29 = or(_T_23, _T_28)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_30 = shr(io.in.a.bits.source, 2)
node _T_31 = eq(_T_30, UInt<2>(0h2))
node _T_32 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_33 = and(_T_31, _T_32)
node _T_34 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_35 = and(_T_33, _T_34)
node _T_36 = eq(_T_35, UInt<1>(0h0))
node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_38 = cvt(_T_37)
node _T_39 = and(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = asSInt(_T_39)
node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0)))
node _T_42 = or(_T_36, _T_41)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_43 = shr(io.in.a.bits.source, 2)
node _T_44 = eq(_T_43, UInt<2>(0h3))
node _T_45 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_46 = and(_T_44, _T_45)
node _T_47 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_48 = and(_T_46, _T_47)
node _T_49 = eq(_T_48, UInt<1>(0h0))
node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_51 = cvt(_T_50)
node _T_52 = and(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = asSInt(_T_52)
node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0)))
node _T_55 = or(_T_49, _T_54)
node _T_56 = and(_T_16, _T_29)
node _T_57 = and(_T_56, _T_42)
node _T_58 = and(_T_57, _T_55)
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_T_58, UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_58, UInt<1>(0h1), "") : assert_1
node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_62 :
node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_65 = and(_T_63, _T_64)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_66 = shr(io.in.a.bits.source, 2)
node _T_67 = eq(_T_66, UInt<1>(0h0))
node _T_68 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_69 = and(_T_67, _T_68)
node _T_70 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_71 = and(_T_69, _T_70)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_72 = shr(io.in.a.bits.source, 2)
node _T_73 = eq(_T_72, UInt<1>(0h1))
node _T_74 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_75 = and(_T_73, _T_74)
node _T_76 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_77 = and(_T_75, _T_76)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_78 = shr(io.in.a.bits.source, 2)
node _T_79 = eq(_T_78, UInt<2>(0h2))
node _T_80 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_81 = and(_T_79, _T_80)
node _T_82 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_83 = and(_T_81, _T_82)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_84 = shr(io.in.a.bits.source, 2)
node _T_85 = eq(_T_84, UInt<2>(0h3))
node _T_86 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_87 = and(_T_85, _T_86)
node _T_88 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_89 = and(_T_87, _T_88)
node _T_90 = or(_T_71, _T_77)
node _T_91 = or(_T_90, _T_83)
node _T_92 = or(_T_91, _T_89)
node _T_93 = and(_T_65, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_96 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_97 = cvt(_T_96)
node _T_98 = and(_T_97, asSInt(UInt<14>(0h2000)))
node _T_99 = asSInt(_T_98)
node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_102 = cvt(_T_101)
node _T_103 = and(_T_102, asSInt(UInt<13>(0h1000)))
node _T_104 = asSInt(_T_103)
node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0)))
node _T_106 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<17>(0h10000)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_112 = cvt(_T_111)
node _T_113 = and(_T_112, asSInt(UInt<18>(0h2f000)))
node _T_114 = asSInt(_T_113)
node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0)))
node _T_116 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_117 = cvt(_T_116)
node _T_118 = and(_T_117, asSInt(UInt<17>(0h10000)))
node _T_119 = asSInt(_T_118)
node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0)))
node _T_121 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_122 = cvt(_T_121)
node _T_123 = and(_T_122, asSInt(UInt<13>(0h1000)))
node _T_124 = asSInt(_T_123)
node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_127 = cvt(_T_126)
node _T_128 = and(_T_127, asSInt(UInt<27>(0h4000000)))
node _T_129 = asSInt(_T_128)
node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0)))
node _T_131 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_132 = cvt(_T_131)
node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000)))
node _T_134 = asSInt(_T_133)
node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0)))
node _T_136 = or(_T_100, _T_105)
node _T_137 = or(_T_136, _T_110)
node _T_138 = or(_T_137, _T_115)
node _T_139 = or(_T_138, _T_120)
node _T_140 = or(_T_139, _T_125)
node _T_141 = or(_T_140, _T_130)
node _T_142 = or(_T_141, _T_135)
node _T_143 = and(_T_95, _T_142)
node _T_144 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_145 = or(UInt<1>(0h0), _T_144)
node _T_146 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_152 = cvt(_T_151)
node _T_153 = and(_T_152, asSInt(UInt<29>(0h10000000)))
node _T_154 = asSInt(_T_153)
node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0)))
node _T_156 = or(_T_150, _T_155)
node _T_157 = and(_T_145, _T_156)
node _T_158 = or(UInt<1>(0h0), _T_143)
node _T_159 = or(_T_158, _T_157)
node _T_160 = and(_T_94, _T_159)
node _T_161 = asUInt(reset)
node _T_162 = eq(_T_161, UInt<1>(0h0))
when _T_162 :
node _T_163 = eq(_T_160, UInt<1>(0h0))
when _T_163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_160, UInt<1>(0h1), "") : assert_2
node _T_164 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_165 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_166 = and(_T_164, _T_165)
node _T_167 = or(UInt<1>(0h0), _T_166)
node _T_168 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_169 = cvt(_T_168)
node _T_170 = and(_T_169, asSInt(UInt<14>(0h2000)))
node _T_171 = asSInt(_T_170)
node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_174 = cvt(_T_173)
node _T_175 = and(_T_174, asSInt(UInt<13>(0h1000)))
node _T_176 = asSInt(_T_175)
node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0)))
node _T_178 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_179 = cvt(_T_178)
node _T_180 = and(_T_179, asSInt(UInt<17>(0h10000)))
node _T_181 = asSInt(_T_180)
node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0)))
node _T_183 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_184 = cvt(_T_183)
node _T_185 = and(_T_184, asSInt(UInt<18>(0h2f000)))
node _T_186 = asSInt(_T_185)
node _T_187 = eq(_T_186, asSInt(UInt<1>(0h0)))
node _T_188 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_189 = cvt(_T_188)
node _T_190 = and(_T_189, asSInt(UInt<17>(0h10000)))
node _T_191 = asSInt(_T_190)
node _T_192 = eq(_T_191, asSInt(UInt<1>(0h0)))
node _T_193 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<13>(0h1000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_199 = cvt(_T_198)
node _T_200 = and(_T_199, asSInt(UInt<17>(0h10000)))
node _T_201 = asSInt(_T_200)
node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0)))
node _T_203 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_204 = cvt(_T_203)
node _T_205 = and(_T_204, asSInt(UInt<27>(0h4000000)))
node _T_206 = asSInt(_T_205)
node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0)))
node _T_208 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_209 = cvt(_T_208)
node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000)))
node _T_211 = asSInt(_T_210)
node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_214 = cvt(_T_213)
node _T_215 = and(_T_214, asSInt(UInt<29>(0h10000000)))
node _T_216 = asSInt(_T_215)
node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0)))
node _T_218 = or(_T_172, _T_177)
node _T_219 = or(_T_218, _T_182)
node _T_220 = or(_T_219, _T_187)
node _T_221 = or(_T_220, _T_192)
node _T_222 = or(_T_221, _T_197)
node _T_223 = or(_T_222, _T_202)
node _T_224 = or(_T_223, _T_207)
node _T_225 = or(_T_224, _T_212)
node _T_226 = or(_T_225, _T_217)
node _T_227 = and(_T_167, _T_226)
node _T_228 = or(UInt<1>(0h0), _T_227)
node _T_229 = and(UInt<1>(0h0), _T_228)
node _T_230 = asUInt(reset)
node _T_231 = eq(_T_230, UInt<1>(0h0))
when _T_231 :
node _T_232 = eq(_T_229, UInt<1>(0h0))
when _T_232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_229, UInt<1>(0h1), "") : assert_3
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(source_ok, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_236 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_237 = asUInt(reset)
node _T_238 = eq(_T_237, UInt<1>(0h0))
when _T_238 :
node _T_239 = eq(_T_236, UInt<1>(0h0))
when _T_239 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_236, UInt<1>(0h1), "") : assert_5
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(is_aligned, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_243 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_243, UInt<1>(0h1), "") : assert_7
node _T_247 = not(io.in.a.bits.mask)
node _T_248 = eq(_T_247, UInt<1>(0h0))
node _T_249 = asUInt(reset)
node _T_250 = eq(_T_249, UInt<1>(0h0))
when _T_250 :
node _T_251 = eq(_T_248, UInt<1>(0h0))
when _T_251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_248, UInt<1>(0h1), "") : assert_8
node _T_252 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_253 = asUInt(reset)
node _T_254 = eq(_T_253, UInt<1>(0h0))
when _T_254 :
node _T_255 = eq(_T_252, UInt<1>(0h0))
when _T_255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_252, UInt<1>(0h1), "") : assert_9
node _T_256 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_256 :
node _T_257 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_258 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_259 = and(_T_257, _T_258)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_260 = shr(io.in.a.bits.source, 2)
node _T_261 = eq(_T_260, UInt<1>(0h0))
node _T_262 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_263 = and(_T_261, _T_262)
node _T_264 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_265 = and(_T_263, _T_264)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_266 = shr(io.in.a.bits.source, 2)
node _T_267 = eq(_T_266, UInt<1>(0h1))
node _T_268 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_269 = and(_T_267, _T_268)
node _T_270 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_271 = and(_T_269, _T_270)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_272 = shr(io.in.a.bits.source, 2)
node _T_273 = eq(_T_272, UInt<2>(0h2))
node _T_274 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_275 = and(_T_273, _T_274)
node _T_276 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_277 = and(_T_275, _T_276)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_278 = shr(io.in.a.bits.source, 2)
node _T_279 = eq(_T_278, UInt<2>(0h3))
node _T_280 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_281 = and(_T_279, _T_280)
node _T_282 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_283 = and(_T_281, _T_282)
node _T_284 = or(_T_265, _T_271)
node _T_285 = or(_T_284, _T_277)
node _T_286 = or(_T_285, _T_283)
node _T_287 = and(_T_259, _T_286)
node _T_288 = or(UInt<1>(0h0), _T_287)
node _T_289 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_291 = cvt(_T_290)
node _T_292 = and(_T_291, asSInt(UInt<14>(0h2000)))
node _T_293 = asSInt(_T_292)
node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0)))
node _T_295 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_296 = cvt(_T_295)
node _T_297 = and(_T_296, asSInt(UInt<13>(0h1000)))
node _T_298 = asSInt(_T_297)
node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0)))
node _T_300 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_301 = cvt(_T_300)
node _T_302 = and(_T_301, asSInt(UInt<17>(0h10000)))
node _T_303 = asSInt(_T_302)
node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0)))
node _T_305 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_306 = cvt(_T_305)
node _T_307 = and(_T_306, asSInt(UInt<18>(0h2f000)))
node _T_308 = asSInt(_T_307)
node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0)))
node _T_310 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_311 = cvt(_T_310)
node _T_312 = and(_T_311, asSInt(UInt<17>(0h10000)))
node _T_313 = asSInt(_T_312)
node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0)))
node _T_315 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_316 = cvt(_T_315)
node _T_317 = and(_T_316, asSInt(UInt<13>(0h1000)))
node _T_318 = asSInt(_T_317)
node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0)))
node _T_320 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_321 = cvt(_T_320)
node _T_322 = and(_T_321, asSInt(UInt<27>(0h4000000)))
node _T_323 = asSInt(_T_322)
node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0)))
node _T_325 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_326 = cvt(_T_325)
node _T_327 = and(_T_326, asSInt(UInt<13>(0h1000)))
node _T_328 = asSInt(_T_327)
node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0)))
node _T_330 = or(_T_294, _T_299)
node _T_331 = or(_T_330, _T_304)
node _T_332 = or(_T_331, _T_309)
node _T_333 = or(_T_332, _T_314)
node _T_334 = or(_T_333, _T_319)
node _T_335 = or(_T_334, _T_324)
node _T_336 = or(_T_335, _T_329)
node _T_337 = and(_T_289, _T_336)
node _T_338 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_339 = or(UInt<1>(0h0), _T_338)
node _T_340 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_341 = cvt(_T_340)
node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000)))
node _T_343 = asSInt(_T_342)
node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0)))
node _T_345 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_346 = cvt(_T_345)
node _T_347 = and(_T_346, asSInt(UInt<29>(0h10000000)))
node _T_348 = asSInt(_T_347)
node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0)))
node _T_350 = or(_T_344, _T_349)
node _T_351 = and(_T_339, _T_350)
node _T_352 = or(UInt<1>(0h0), _T_337)
node _T_353 = or(_T_352, _T_351)
node _T_354 = and(_T_288, _T_353)
node _T_355 = asUInt(reset)
node _T_356 = eq(_T_355, UInt<1>(0h0))
when _T_356 :
node _T_357 = eq(_T_354, UInt<1>(0h0))
when _T_357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_354, UInt<1>(0h1), "") : assert_10
node _T_358 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_359 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_360 = and(_T_358, _T_359)
node _T_361 = or(UInt<1>(0h0), _T_360)
node _T_362 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_363 = cvt(_T_362)
node _T_364 = and(_T_363, asSInt(UInt<14>(0h2000)))
node _T_365 = asSInt(_T_364)
node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0)))
node _T_367 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_368 = cvt(_T_367)
node _T_369 = and(_T_368, asSInt(UInt<13>(0h1000)))
node _T_370 = asSInt(_T_369)
node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0)))
node _T_372 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_373 = cvt(_T_372)
node _T_374 = and(_T_373, asSInt(UInt<17>(0h10000)))
node _T_375 = asSInt(_T_374)
node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0)))
node _T_377 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_378 = cvt(_T_377)
node _T_379 = and(_T_378, asSInt(UInt<18>(0h2f000)))
node _T_380 = asSInt(_T_379)
node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0)))
node _T_382 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_383 = cvt(_T_382)
node _T_384 = and(_T_383, asSInt(UInt<17>(0h10000)))
node _T_385 = asSInt(_T_384)
node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0)))
node _T_387 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_388 = cvt(_T_387)
node _T_389 = and(_T_388, asSInt(UInt<13>(0h1000)))
node _T_390 = asSInt(_T_389)
node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0)))
node _T_392 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_393 = cvt(_T_392)
node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000)))
node _T_395 = asSInt(_T_394)
node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0)))
node _T_397 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_398 = cvt(_T_397)
node _T_399 = and(_T_398, asSInt(UInt<27>(0h4000000)))
node _T_400 = asSInt(_T_399)
node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0)))
node _T_402 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_403 = cvt(_T_402)
node _T_404 = and(_T_403, asSInt(UInt<13>(0h1000)))
node _T_405 = asSInt(_T_404)
node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0)))
node _T_407 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_408 = cvt(_T_407)
node _T_409 = and(_T_408, asSInt(UInt<29>(0h10000000)))
node _T_410 = asSInt(_T_409)
node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0)))
node _T_412 = or(_T_366, _T_371)
node _T_413 = or(_T_412, _T_376)
node _T_414 = or(_T_413, _T_381)
node _T_415 = or(_T_414, _T_386)
node _T_416 = or(_T_415, _T_391)
node _T_417 = or(_T_416, _T_396)
node _T_418 = or(_T_417, _T_401)
node _T_419 = or(_T_418, _T_406)
node _T_420 = or(_T_419, _T_411)
node _T_421 = and(_T_361, _T_420)
node _T_422 = or(UInt<1>(0h0), _T_421)
node _T_423 = and(UInt<1>(0h0), _T_422)
node _T_424 = asUInt(reset)
node _T_425 = eq(_T_424, UInt<1>(0h0))
when _T_425 :
node _T_426 = eq(_T_423, UInt<1>(0h0))
when _T_426 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_423, UInt<1>(0h1), "") : assert_11
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(source_ok, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_430 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_431 = asUInt(reset)
node _T_432 = eq(_T_431, UInt<1>(0h0))
when _T_432 :
node _T_433 = eq(_T_430, UInt<1>(0h0))
when _T_433 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_430, UInt<1>(0h1), "") : assert_13
node _T_434 = asUInt(reset)
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(is_aligned, UInt<1>(0h0))
when _T_436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_437 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_T_437, UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_437, UInt<1>(0h1), "") : assert_15
node _T_441 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(_T_441, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_441, UInt<1>(0h1), "") : assert_16
node _T_445 = not(io.in.a.bits.mask)
node _T_446 = eq(_T_445, UInt<1>(0h0))
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_T_446, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_446, UInt<1>(0h1), "") : assert_17
node _T_450 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(_T_450, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_450, UInt<1>(0h1), "") : assert_18
node _T_454 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_454 :
node _T_455 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_456 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_457 = and(_T_455, _T_456)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_458 = shr(io.in.a.bits.source, 2)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_461 = and(_T_459, _T_460)
node _T_462 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_463 = and(_T_461, _T_462)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_464 = shr(io.in.a.bits.source, 2)
node _T_465 = eq(_T_464, UInt<1>(0h1))
node _T_466 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_467 = and(_T_465, _T_466)
node _T_468 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_469 = and(_T_467, _T_468)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_470 = shr(io.in.a.bits.source, 2)
node _T_471 = eq(_T_470, UInt<2>(0h2))
node _T_472 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_473 = and(_T_471, _T_472)
node _T_474 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_475 = and(_T_473, _T_474)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_476 = shr(io.in.a.bits.source, 2)
node _T_477 = eq(_T_476, UInt<2>(0h3))
node _T_478 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_479 = and(_T_477, _T_478)
node _T_480 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_481 = and(_T_479, _T_480)
node _T_482 = or(_T_463, _T_469)
node _T_483 = or(_T_482, _T_475)
node _T_484 = or(_T_483, _T_481)
node _T_485 = and(_T_457, _T_484)
node _T_486 = or(UInt<1>(0h0), _T_485)
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_486, UInt<1>(0h1), "") : assert_19
node _T_490 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_491 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_492 = and(_T_490, _T_491)
node _T_493 = or(UInt<1>(0h0), _T_492)
node _T_494 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_495 = cvt(_T_494)
node _T_496 = and(_T_495, asSInt(UInt<13>(0h1000)))
node _T_497 = asSInt(_T_496)
node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0)))
node _T_499 = and(_T_493, _T_498)
node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_501 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_502 = and(_T_500, _T_501)
node _T_503 = or(UInt<1>(0h0), _T_502)
node _T_504 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_505 = cvt(_T_504)
node _T_506 = and(_T_505, asSInt(UInt<14>(0h2000)))
node _T_507 = asSInt(_T_506)
node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0)))
node _T_509 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_510 = cvt(_T_509)
node _T_511 = and(_T_510, asSInt(UInt<17>(0h10000)))
node _T_512 = asSInt(_T_511)
node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0)))
node _T_514 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_515 = cvt(_T_514)
node _T_516 = and(_T_515, asSInt(UInt<18>(0h2f000)))
node _T_517 = asSInt(_T_516)
node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0)))
node _T_519 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_520 = cvt(_T_519)
node _T_521 = and(_T_520, asSInt(UInt<17>(0h10000)))
node _T_522 = asSInt(_T_521)
node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0)))
node _T_524 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_525 = cvt(_T_524)
node _T_526 = and(_T_525, asSInt(UInt<13>(0h1000)))
node _T_527 = asSInt(_T_526)
node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0)))
node _T_529 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_530 = cvt(_T_529)
node _T_531 = and(_T_530, asSInt(UInt<17>(0h10000)))
node _T_532 = asSInt(_T_531)
node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0)))
node _T_534 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_535 = cvt(_T_534)
node _T_536 = and(_T_535, asSInt(UInt<27>(0h4000000)))
node _T_537 = asSInt(_T_536)
node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0)))
node _T_539 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_540 = cvt(_T_539)
node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000)))
node _T_542 = asSInt(_T_541)
node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0)))
node _T_544 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_545 = cvt(_T_544)
node _T_546 = and(_T_545, asSInt(UInt<29>(0h10000000)))
node _T_547 = asSInt(_T_546)
node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0)))
node _T_549 = or(_T_508, _T_513)
node _T_550 = or(_T_549, _T_518)
node _T_551 = or(_T_550, _T_523)
node _T_552 = or(_T_551, _T_528)
node _T_553 = or(_T_552, _T_533)
node _T_554 = or(_T_553, _T_538)
node _T_555 = or(_T_554, _T_543)
node _T_556 = or(_T_555, _T_548)
node _T_557 = and(_T_503, _T_556)
node _T_558 = or(UInt<1>(0h0), _T_499)
node _T_559 = or(_T_558, _T_557)
node _T_560 = asUInt(reset)
node _T_561 = eq(_T_560, UInt<1>(0h0))
when _T_561 :
node _T_562 = eq(_T_559, UInt<1>(0h0))
when _T_562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_559, UInt<1>(0h1), "") : assert_20
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(source_ok, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_566 = asUInt(reset)
node _T_567 = eq(_T_566, UInt<1>(0h0))
when _T_567 :
node _T_568 = eq(is_aligned, UInt<1>(0h0))
when _T_568 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_569 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_569, UInt<1>(0h1), "") : assert_23
node _T_573 = eq(io.in.a.bits.mask, mask)
node _T_574 = asUInt(reset)
node _T_575 = eq(_T_574, UInt<1>(0h0))
when _T_575 :
node _T_576 = eq(_T_573, UInt<1>(0h0))
when _T_576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_573, UInt<1>(0h1), "") : assert_24
node _T_577 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_578 = asUInt(reset)
node _T_579 = eq(_T_578, UInt<1>(0h0))
when _T_579 :
node _T_580 = eq(_T_577, UInt<1>(0h0))
when _T_580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_577, UInt<1>(0h1), "") : assert_25
node _T_581 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_581 :
node _T_582 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_583 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_584 = and(_T_582, _T_583)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_585 = shr(io.in.a.bits.source, 2)
node _T_586 = eq(_T_585, UInt<1>(0h0))
node _T_587 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_588 = and(_T_586, _T_587)
node _T_589 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_590 = and(_T_588, _T_589)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_591 = shr(io.in.a.bits.source, 2)
node _T_592 = eq(_T_591, UInt<1>(0h1))
node _T_593 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_594 = and(_T_592, _T_593)
node _T_595 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_596 = and(_T_594, _T_595)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_597 = shr(io.in.a.bits.source, 2)
node _T_598 = eq(_T_597, UInt<2>(0h2))
node _T_599 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_600 = and(_T_598, _T_599)
node _T_601 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_602 = and(_T_600, _T_601)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_603 = shr(io.in.a.bits.source, 2)
node _T_604 = eq(_T_603, UInt<2>(0h3))
node _T_605 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_606 = and(_T_604, _T_605)
node _T_607 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_608 = and(_T_606, _T_607)
node _T_609 = or(_T_590, _T_596)
node _T_610 = or(_T_609, _T_602)
node _T_611 = or(_T_610, _T_608)
node _T_612 = and(_T_584, _T_611)
node _T_613 = or(UInt<1>(0h0), _T_612)
node _T_614 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_615 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_616 = and(_T_614, _T_615)
node _T_617 = or(UInt<1>(0h0), _T_616)
node _T_618 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_619 = cvt(_T_618)
node _T_620 = and(_T_619, asSInt(UInt<13>(0h1000)))
node _T_621 = asSInt(_T_620)
node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0)))
node _T_623 = and(_T_617, _T_622)
node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_626 = and(_T_624, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_629 = cvt(_T_628)
node _T_630 = and(_T_629, asSInt(UInt<14>(0h2000)))
node _T_631 = asSInt(_T_630)
node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0)))
node _T_633 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_634 = cvt(_T_633)
node _T_635 = and(_T_634, asSInt(UInt<18>(0h2f000)))
node _T_636 = asSInt(_T_635)
node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0)))
node _T_638 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_639 = cvt(_T_638)
node _T_640 = and(_T_639, asSInt(UInt<17>(0h10000)))
node _T_641 = asSInt(_T_640)
node _T_642 = eq(_T_641, asSInt(UInt<1>(0h0)))
node _T_643 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_644 = cvt(_T_643)
node _T_645 = and(_T_644, asSInt(UInt<13>(0h1000)))
node _T_646 = asSInt(_T_645)
node _T_647 = eq(_T_646, asSInt(UInt<1>(0h0)))
node _T_648 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_649 = cvt(_T_648)
node _T_650 = and(_T_649, asSInt(UInt<17>(0h10000)))
node _T_651 = asSInt(_T_650)
node _T_652 = eq(_T_651, asSInt(UInt<1>(0h0)))
node _T_653 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_654 = cvt(_T_653)
node _T_655 = and(_T_654, asSInt(UInt<27>(0h4000000)))
node _T_656 = asSInt(_T_655)
node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0)))
node _T_658 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_659 = cvt(_T_658)
node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000)))
node _T_661 = asSInt(_T_660)
node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0)))
node _T_663 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_664 = cvt(_T_663)
node _T_665 = and(_T_664, asSInt(UInt<29>(0h10000000)))
node _T_666 = asSInt(_T_665)
node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0)))
node _T_668 = or(_T_632, _T_637)
node _T_669 = or(_T_668, _T_642)
node _T_670 = or(_T_669, _T_647)
node _T_671 = or(_T_670, _T_652)
node _T_672 = or(_T_671, _T_657)
node _T_673 = or(_T_672, _T_662)
node _T_674 = or(_T_673, _T_667)
node _T_675 = and(_T_627, _T_674)
node _T_676 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_677 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_678 = cvt(_T_677)
node _T_679 = and(_T_678, asSInt(UInt<17>(0h10000)))
node _T_680 = asSInt(_T_679)
node _T_681 = eq(_T_680, asSInt(UInt<1>(0h0)))
node _T_682 = and(_T_676, _T_681)
node _T_683 = or(UInt<1>(0h0), _T_623)
node _T_684 = or(_T_683, _T_675)
node _T_685 = or(_T_684, _T_682)
node _T_686 = and(_T_613, _T_685)
node _T_687 = asUInt(reset)
node _T_688 = eq(_T_687, UInt<1>(0h0))
when _T_688 :
node _T_689 = eq(_T_686, UInt<1>(0h0))
when _T_689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_686, UInt<1>(0h1), "") : assert_26
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(source_ok, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_693 = asUInt(reset)
node _T_694 = eq(_T_693, UInt<1>(0h0))
when _T_694 :
node _T_695 = eq(is_aligned, UInt<1>(0h0))
when _T_695 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_696 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_697 = asUInt(reset)
node _T_698 = eq(_T_697, UInt<1>(0h0))
when _T_698 :
node _T_699 = eq(_T_696, UInt<1>(0h0))
when _T_699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_696, UInt<1>(0h1), "") : assert_29
node _T_700 = eq(io.in.a.bits.mask, mask)
node _T_701 = asUInt(reset)
node _T_702 = eq(_T_701, UInt<1>(0h0))
when _T_702 :
node _T_703 = eq(_T_700, UInt<1>(0h0))
when _T_703 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_700, UInt<1>(0h1), "") : assert_30
node _T_704 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_704 :
node _T_705 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_706 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_707 = and(_T_705, _T_706)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_708 = shr(io.in.a.bits.source, 2)
node _T_709 = eq(_T_708, UInt<1>(0h0))
node _T_710 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_711 = and(_T_709, _T_710)
node _T_712 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_713 = and(_T_711, _T_712)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_714 = shr(io.in.a.bits.source, 2)
node _T_715 = eq(_T_714, UInt<1>(0h1))
node _T_716 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_717 = and(_T_715, _T_716)
node _T_718 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_719 = and(_T_717, _T_718)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_720 = shr(io.in.a.bits.source, 2)
node _T_721 = eq(_T_720, UInt<2>(0h2))
node _T_722 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_723 = and(_T_721, _T_722)
node _T_724 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_725 = and(_T_723, _T_724)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_726 = shr(io.in.a.bits.source, 2)
node _T_727 = eq(_T_726, UInt<2>(0h3))
node _T_728 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_729 = and(_T_727, _T_728)
node _T_730 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_731 = and(_T_729, _T_730)
node _T_732 = or(_T_713, _T_719)
node _T_733 = or(_T_732, _T_725)
node _T_734 = or(_T_733, _T_731)
node _T_735 = and(_T_707, _T_734)
node _T_736 = or(UInt<1>(0h0), _T_735)
node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_738 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_739 = and(_T_737, _T_738)
node _T_740 = or(UInt<1>(0h0), _T_739)
node _T_741 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_742 = cvt(_T_741)
node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000)))
node _T_744 = asSInt(_T_743)
node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0)))
node _T_746 = and(_T_740, _T_745)
node _T_747 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_748 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_749 = and(_T_747, _T_748)
node _T_750 = or(UInt<1>(0h0), _T_749)
node _T_751 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_752 = cvt(_T_751)
node _T_753 = and(_T_752, asSInt(UInt<14>(0h2000)))
node _T_754 = asSInt(_T_753)
node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0)))
node _T_756 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_757 = cvt(_T_756)
node _T_758 = and(_T_757, asSInt(UInt<18>(0h2f000)))
node _T_759 = asSInt(_T_758)
node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0)))
node _T_761 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_762 = cvt(_T_761)
node _T_763 = and(_T_762, asSInt(UInt<17>(0h10000)))
node _T_764 = asSInt(_T_763)
node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0)))
node _T_766 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_767 = cvt(_T_766)
node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000)))
node _T_769 = asSInt(_T_768)
node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0)))
node _T_771 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_772 = cvt(_T_771)
node _T_773 = and(_T_772, asSInt(UInt<17>(0h10000)))
node _T_774 = asSInt(_T_773)
node _T_775 = eq(_T_774, asSInt(UInt<1>(0h0)))
node _T_776 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_777 = cvt(_T_776)
node _T_778 = and(_T_777, asSInt(UInt<27>(0h4000000)))
node _T_779 = asSInt(_T_778)
node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0)))
node _T_781 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_782 = cvt(_T_781)
node _T_783 = and(_T_782, asSInt(UInt<13>(0h1000)))
node _T_784 = asSInt(_T_783)
node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0)))
node _T_786 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_787 = cvt(_T_786)
node _T_788 = and(_T_787, asSInt(UInt<29>(0h10000000)))
node _T_789 = asSInt(_T_788)
node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0)))
node _T_791 = or(_T_755, _T_760)
node _T_792 = or(_T_791, _T_765)
node _T_793 = or(_T_792, _T_770)
node _T_794 = or(_T_793, _T_775)
node _T_795 = or(_T_794, _T_780)
node _T_796 = or(_T_795, _T_785)
node _T_797 = or(_T_796, _T_790)
node _T_798 = and(_T_750, _T_797)
node _T_799 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_800 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_801 = cvt(_T_800)
node _T_802 = and(_T_801, asSInt(UInt<17>(0h10000)))
node _T_803 = asSInt(_T_802)
node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0)))
node _T_805 = and(_T_799, _T_804)
node _T_806 = or(UInt<1>(0h0), _T_746)
node _T_807 = or(_T_806, _T_798)
node _T_808 = or(_T_807, _T_805)
node _T_809 = and(_T_736, _T_808)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_809, UInt<1>(0h1), "") : assert_31
node _T_813 = asUInt(reset)
node _T_814 = eq(_T_813, UInt<1>(0h0))
when _T_814 :
node _T_815 = eq(source_ok, UInt<1>(0h0))
when _T_815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_816 = asUInt(reset)
node _T_817 = eq(_T_816, UInt<1>(0h0))
when _T_817 :
node _T_818 = eq(is_aligned, UInt<1>(0h0))
when _T_818 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_819 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_820 = asUInt(reset)
node _T_821 = eq(_T_820, UInt<1>(0h0))
when _T_821 :
node _T_822 = eq(_T_819, UInt<1>(0h0))
when _T_822 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_819, UInt<1>(0h1), "") : assert_34
node _T_823 = not(mask)
node _T_824 = and(io.in.a.bits.mask, _T_823)
node _T_825 = eq(_T_824, UInt<1>(0h0))
node _T_826 = asUInt(reset)
node _T_827 = eq(_T_826, UInt<1>(0h0))
when _T_827 :
node _T_828 = eq(_T_825, UInt<1>(0h0))
when _T_828 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_825, UInt<1>(0h1), "") : assert_35
node _T_829 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_829 :
node _T_830 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_831 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_832 = and(_T_830, _T_831)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_833 = shr(io.in.a.bits.source, 2)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_836 = and(_T_834, _T_835)
node _T_837 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_838 = and(_T_836, _T_837)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_839 = shr(io.in.a.bits.source, 2)
node _T_840 = eq(_T_839, UInt<1>(0h1))
node _T_841 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_842 = and(_T_840, _T_841)
node _T_843 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_844 = and(_T_842, _T_843)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_845 = shr(io.in.a.bits.source, 2)
node _T_846 = eq(_T_845, UInt<2>(0h2))
node _T_847 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_848 = and(_T_846, _T_847)
node _T_849 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_850 = and(_T_848, _T_849)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_851 = shr(io.in.a.bits.source, 2)
node _T_852 = eq(_T_851, UInt<2>(0h3))
node _T_853 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_854 = and(_T_852, _T_853)
node _T_855 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_856 = and(_T_854, _T_855)
node _T_857 = or(_T_838, _T_844)
node _T_858 = or(_T_857, _T_850)
node _T_859 = or(_T_858, _T_856)
node _T_860 = and(_T_832, _T_859)
node _T_861 = or(UInt<1>(0h0), _T_860)
node _T_862 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_863 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_864 = and(_T_862, _T_863)
node _T_865 = or(UInt<1>(0h0), _T_864)
node _T_866 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_867 = cvt(_T_866)
node _T_868 = and(_T_867, asSInt(UInt<14>(0h2000)))
node _T_869 = asSInt(_T_868)
node _T_870 = eq(_T_869, asSInt(UInt<1>(0h0)))
node _T_871 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_872 = cvt(_T_871)
node _T_873 = and(_T_872, asSInt(UInt<13>(0h1000)))
node _T_874 = asSInt(_T_873)
node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0)))
node _T_876 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_877 = cvt(_T_876)
node _T_878 = and(_T_877, asSInt(UInt<18>(0h2f000)))
node _T_879 = asSInt(_T_878)
node _T_880 = eq(_T_879, asSInt(UInt<1>(0h0)))
node _T_881 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_882 = cvt(_T_881)
node _T_883 = and(_T_882, asSInt(UInt<17>(0h10000)))
node _T_884 = asSInt(_T_883)
node _T_885 = eq(_T_884, asSInt(UInt<1>(0h0)))
node _T_886 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_887 = cvt(_T_886)
node _T_888 = and(_T_887, asSInt(UInt<13>(0h1000)))
node _T_889 = asSInt(_T_888)
node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0)))
node _T_891 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_892 = cvt(_T_891)
node _T_893 = and(_T_892, asSInt(UInt<27>(0h4000000)))
node _T_894 = asSInt(_T_893)
node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0)))
node _T_896 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_897 = cvt(_T_896)
node _T_898 = and(_T_897, asSInt(UInt<13>(0h1000)))
node _T_899 = asSInt(_T_898)
node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0)))
node _T_901 = or(_T_870, _T_875)
node _T_902 = or(_T_901, _T_880)
node _T_903 = or(_T_902, _T_885)
node _T_904 = or(_T_903, _T_890)
node _T_905 = or(_T_904, _T_895)
node _T_906 = or(_T_905, _T_900)
node _T_907 = and(_T_865, _T_906)
node _T_908 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_909 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_910 = cvt(_T_909)
node _T_911 = and(_T_910, asSInt(UInt<17>(0h10000)))
node _T_912 = asSInt(_T_911)
node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0)))
node _T_914 = and(_T_908, _T_913)
node _T_915 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_916 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_917 = and(_T_915, _T_916)
node _T_918 = or(UInt<1>(0h0), _T_917)
node _T_919 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_920 = cvt(_T_919)
node _T_921 = and(_T_920, asSInt(UInt<17>(0h10000)))
node _T_922 = asSInt(_T_921)
node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0)))
node _T_924 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_925 = cvt(_T_924)
node _T_926 = and(_T_925, asSInt(UInt<29>(0h10000000)))
node _T_927 = asSInt(_T_926)
node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0)))
node _T_929 = or(_T_923, _T_928)
node _T_930 = and(_T_918, _T_929)
node _T_931 = or(UInt<1>(0h0), _T_907)
node _T_932 = or(_T_931, _T_914)
node _T_933 = or(_T_932, _T_930)
node _T_934 = and(_T_861, _T_933)
node _T_935 = asUInt(reset)
node _T_936 = eq(_T_935, UInt<1>(0h0))
when _T_936 :
node _T_937 = eq(_T_934, UInt<1>(0h0))
when _T_937 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_934, UInt<1>(0h1), "") : assert_36
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(source_ok, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_941 = asUInt(reset)
node _T_942 = eq(_T_941, UInt<1>(0h0))
when _T_942 :
node _T_943 = eq(is_aligned, UInt<1>(0h0))
when _T_943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_944 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_945 = asUInt(reset)
node _T_946 = eq(_T_945, UInt<1>(0h0))
when _T_946 :
node _T_947 = eq(_T_944, UInt<1>(0h0))
when _T_947 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_944, UInt<1>(0h1), "") : assert_39
node _T_948 = eq(io.in.a.bits.mask, mask)
node _T_949 = asUInt(reset)
node _T_950 = eq(_T_949, UInt<1>(0h0))
when _T_950 :
node _T_951 = eq(_T_948, UInt<1>(0h0))
when _T_951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_948, UInt<1>(0h1), "") : assert_40
node _T_952 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_952 :
node _T_953 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_954 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_955 = and(_T_953, _T_954)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_956 = shr(io.in.a.bits.source, 2)
node _T_957 = eq(_T_956, UInt<1>(0h0))
node _T_958 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_959 = and(_T_957, _T_958)
node _T_960 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_961 = and(_T_959, _T_960)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_962 = shr(io.in.a.bits.source, 2)
node _T_963 = eq(_T_962, UInt<1>(0h1))
node _T_964 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_965 = and(_T_963, _T_964)
node _T_966 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_967 = and(_T_965, _T_966)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_968 = shr(io.in.a.bits.source, 2)
node _T_969 = eq(_T_968, UInt<2>(0h2))
node _T_970 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_971 = and(_T_969, _T_970)
node _T_972 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_973 = and(_T_971, _T_972)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_974 = shr(io.in.a.bits.source, 2)
node _T_975 = eq(_T_974, UInt<2>(0h3))
node _T_976 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_977 = and(_T_975, _T_976)
node _T_978 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_979 = and(_T_977, _T_978)
node _T_980 = or(_T_961, _T_967)
node _T_981 = or(_T_980, _T_973)
node _T_982 = or(_T_981, _T_979)
node _T_983 = and(_T_955, _T_982)
node _T_984 = or(UInt<1>(0h0), _T_983)
node _T_985 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_986 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_987 = and(_T_985, _T_986)
node _T_988 = or(UInt<1>(0h0), _T_987)
node _T_989 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_990 = cvt(_T_989)
node _T_991 = and(_T_990, asSInt(UInt<14>(0h2000)))
node _T_992 = asSInt(_T_991)
node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0)))
node _T_994 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_995 = cvt(_T_994)
node _T_996 = and(_T_995, asSInt(UInt<13>(0h1000)))
node _T_997 = asSInt(_T_996)
node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0)))
node _T_999 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1000 = cvt(_T_999)
node _T_1001 = and(_T_1000, asSInt(UInt<18>(0h2f000)))
node _T_1002 = asSInt(_T_1001)
node _T_1003 = eq(_T_1002, asSInt(UInt<1>(0h0)))
node _T_1004 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1005 = cvt(_T_1004)
node _T_1006 = and(_T_1005, asSInt(UInt<17>(0h10000)))
node _T_1007 = asSInt(_T_1006)
node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0)))
node _T_1009 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1010 = cvt(_T_1009)
node _T_1011 = and(_T_1010, asSInt(UInt<13>(0h1000)))
node _T_1012 = asSInt(_T_1011)
node _T_1013 = eq(_T_1012, asSInt(UInt<1>(0h0)))
node _T_1014 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1015 = cvt(_T_1014)
node _T_1016 = and(_T_1015, asSInt(UInt<27>(0h4000000)))
node _T_1017 = asSInt(_T_1016)
node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0)))
node _T_1019 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1020 = cvt(_T_1019)
node _T_1021 = and(_T_1020, asSInt(UInt<13>(0h1000)))
node _T_1022 = asSInt(_T_1021)
node _T_1023 = eq(_T_1022, asSInt(UInt<1>(0h0)))
node _T_1024 = or(_T_993, _T_998)
node _T_1025 = or(_T_1024, _T_1003)
node _T_1026 = or(_T_1025, _T_1008)
node _T_1027 = or(_T_1026, _T_1013)
node _T_1028 = or(_T_1027, _T_1018)
node _T_1029 = or(_T_1028, _T_1023)
node _T_1030 = and(_T_988, _T_1029)
node _T_1031 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1032 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1033 = cvt(_T_1032)
node _T_1034 = and(_T_1033, asSInt(UInt<17>(0h10000)))
node _T_1035 = asSInt(_T_1034)
node _T_1036 = eq(_T_1035, asSInt(UInt<1>(0h0)))
node _T_1037 = and(_T_1031, _T_1036)
node _T_1038 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1039 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_1040 = and(_T_1038, _T_1039)
node _T_1041 = or(UInt<1>(0h0), _T_1040)
node _T_1042 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1043 = cvt(_T_1042)
node _T_1044 = and(_T_1043, asSInt(UInt<17>(0h10000)))
node _T_1045 = asSInt(_T_1044)
node _T_1046 = eq(_T_1045, asSInt(UInt<1>(0h0)))
node _T_1047 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1048 = cvt(_T_1047)
node _T_1049 = and(_T_1048, asSInt(UInt<29>(0h10000000)))
node _T_1050 = asSInt(_T_1049)
node _T_1051 = eq(_T_1050, asSInt(UInt<1>(0h0)))
node _T_1052 = or(_T_1046, _T_1051)
node _T_1053 = and(_T_1041, _T_1052)
node _T_1054 = or(UInt<1>(0h0), _T_1030)
node _T_1055 = or(_T_1054, _T_1037)
node _T_1056 = or(_T_1055, _T_1053)
node _T_1057 = and(_T_984, _T_1056)
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_41
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(source_ok, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1064 = asUInt(reset)
node _T_1065 = eq(_T_1064, UInt<1>(0h0))
when _T_1065 :
node _T_1066 = eq(is_aligned, UInt<1>(0h0))
when _T_1066 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1067 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1068 = asUInt(reset)
node _T_1069 = eq(_T_1068, UInt<1>(0h0))
when _T_1069 :
node _T_1070 = eq(_T_1067, UInt<1>(0h0))
when _T_1070 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1067, UInt<1>(0h1), "") : assert_44
node _T_1071 = eq(io.in.a.bits.mask, mask)
node _T_1072 = asUInt(reset)
node _T_1073 = eq(_T_1072, UInt<1>(0h0))
when _T_1073 :
node _T_1074 = eq(_T_1071, UInt<1>(0h0))
when _T_1074 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1071, UInt<1>(0h1), "") : assert_45
node _T_1075 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1075 :
node _T_1076 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1077 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1078 = and(_T_1076, _T_1077)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1079 = shr(io.in.a.bits.source, 2)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
node _T_1081 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1082 = and(_T_1080, _T_1081)
node _T_1083 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1084 = and(_T_1082, _T_1083)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1085 = shr(io.in.a.bits.source, 2)
node _T_1086 = eq(_T_1085, UInt<1>(0h1))
node _T_1087 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1088 = and(_T_1086, _T_1087)
node _T_1089 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1090 = and(_T_1088, _T_1089)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1091 = shr(io.in.a.bits.source, 2)
node _T_1092 = eq(_T_1091, UInt<2>(0h2))
node _T_1093 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1094 = and(_T_1092, _T_1093)
node _T_1095 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1096 = and(_T_1094, _T_1095)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1097 = shr(io.in.a.bits.source, 2)
node _T_1098 = eq(_T_1097, UInt<2>(0h3))
node _T_1099 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1100 = and(_T_1098, _T_1099)
node _T_1101 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1102 = and(_T_1100, _T_1101)
node _T_1103 = or(_T_1084, _T_1090)
node _T_1104 = or(_T_1103, _T_1096)
node _T_1105 = or(_T_1104, _T_1102)
node _T_1106 = and(_T_1078, _T_1105)
node _T_1107 = or(UInt<1>(0h0), _T_1106)
node _T_1108 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1109 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1110 = and(_T_1108, _T_1109)
node _T_1111 = or(UInt<1>(0h0), _T_1110)
node _T_1112 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1113 = cvt(_T_1112)
node _T_1114 = and(_T_1113, asSInt(UInt<13>(0h1000)))
node _T_1115 = asSInt(_T_1114)
node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0)))
node _T_1117 = and(_T_1111, _T_1116)
node _T_1118 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1119 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1120 = cvt(_T_1119)
node _T_1121 = and(_T_1120, asSInt(UInt<14>(0h2000)))
node _T_1122 = asSInt(_T_1121)
node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0)))
node _T_1124 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1125 = cvt(_T_1124)
node _T_1126 = and(_T_1125, asSInt(UInt<17>(0h10000)))
node _T_1127 = asSInt(_T_1126)
node _T_1128 = eq(_T_1127, asSInt(UInt<1>(0h0)))
node _T_1129 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1130 = cvt(_T_1129)
node _T_1131 = and(_T_1130, asSInt(UInt<18>(0h2f000)))
node _T_1132 = asSInt(_T_1131)
node _T_1133 = eq(_T_1132, asSInt(UInt<1>(0h0)))
node _T_1134 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1135 = cvt(_T_1134)
node _T_1136 = and(_T_1135, asSInt(UInt<17>(0h10000)))
node _T_1137 = asSInt(_T_1136)
node _T_1138 = eq(_T_1137, asSInt(UInt<1>(0h0)))
node _T_1139 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1140 = cvt(_T_1139)
node _T_1141 = and(_T_1140, asSInt(UInt<13>(0h1000)))
node _T_1142 = asSInt(_T_1141)
node _T_1143 = eq(_T_1142, asSInt(UInt<1>(0h0)))
node _T_1144 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1145 = cvt(_T_1144)
node _T_1146 = and(_T_1145, asSInt(UInt<27>(0h4000000)))
node _T_1147 = asSInt(_T_1146)
node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0)))
node _T_1149 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1150 = cvt(_T_1149)
node _T_1151 = and(_T_1150, asSInt(UInt<13>(0h1000)))
node _T_1152 = asSInt(_T_1151)
node _T_1153 = eq(_T_1152, asSInt(UInt<1>(0h0)))
node _T_1154 = or(_T_1123, _T_1128)
node _T_1155 = or(_T_1154, _T_1133)
node _T_1156 = or(_T_1155, _T_1138)
node _T_1157 = or(_T_1156, _T_1143)
node _T_1158 = or(_T_1157, _T_1148)
node _T_1159 = or(_T_1158, _T_1153)
node _T_1160 = and(_T_1118, _T_1159)
node _T_1161 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1162 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1163 = and(_T_1161, _T_1162)
node _T_1164 = or(UInt<1>(0h0), _T_1163)
node _T_1165 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1166 = cvt(_T_1165)
node _T_1167 = and(_T_1166, asSInt(UInt<17>(0h10000)))
node _T_1168 = asSInt(_T_1167)
node _T_1169 = eq(_T_1168, asSInt(UInt<1>(0h0)))
node _T_1170 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1171 = cvt(_T_1170)
node _T_1172 = and(_T_1171, asSInt(UInt<29>(0h10000000)))
node _T_1173 = asSInt(_T_1172)
node _T_1174 = eq(_T_1173, asSInt(UInt<1>(0h0)))
node _T_1175 = or(_T_1169, _T_1174)
node _T_1176 = and(_T_1164, _T_1175)
node _T_1177 = or(UInt<1>(0h0), _T_1117)
node _T_1178 = or(_T_1177, _T_1160)
node _T_1179 = or(_T_1178, _T_1176)
node _T_1180 = and(_T_1107, _T_1179)
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(_T_1180, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1180, UInt<1>(0h1), "") : assert_46
node _T_1184 = asUInt(reset)
node _T_1185 = eq(_T_1184, UInt<1>(0h0))
when _T_1185 :
node _T_1186 = eq(source_ok, UInt<1>(0h0))
when _T_1186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(is_aligned, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1190 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_49
node _T_1194 = eq(io.in.a.bits.mask, mask)
node _T_1195 = asUInt(reset)
node _T_1196 = eq(_T_1195, UInt<1>(0h0))
when _T_1196 :
node _T_1197 = eq(_T_1194, UInt<1>(0h0))
when _T_1197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1194, UInt<1>(0h1), "") : assert_50
node _T_1198 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1199 = asUInt(reset)
node _T_1200 = eq(_T_1199, UInt<1>(0h0))
when _T_1200 :
node _T_1201 = eq(_T_1198, UInt<1>(0h0))
when _T_1201 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1198, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1202 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_26 = shr(io.in.d.bits.source, 2)
node _source_ok_T_27 = eq(_source_ok_T_26, UInt<1>(0h0))
node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28)
node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_32 = shr(io.in.d.bits.source, 2)
node _source_ok_T_33 = eq(_source_ok_T_32, UInt<1>(0h1))
node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34)
node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_38 = shr(io.in.d.bits.source, 2)
node _source_ok_T_39 = eq(_source_ok_T_38, UInt<2>(0h2))
node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40)
node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_44 = shr(io.in.d.bits.source, 2)
node _source_ok_T_45 = eq(_source_ok_T_44, UInt<2>(0h3))
node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46)
node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48)
wire _source_ok_WIRE_1 : UInt<1>[4]
connect _source_ok_WIRE_1[0], _source_ok_T_31
connect _source_ok_WIRE_1[1], _source_ok_T_37
connect _source_ok_WIRE_1[2], _source_ok_T_43
connect _source_ok_WIRE_1[3], _source_ok_T_49
node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2])
node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_1206 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1206 :
node _T_1207 = asUInt(reset)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
when _T_1208 :
node _T_1209 = eq(source_ok_1, UInt<1>(0h0))
when _T_1209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1210 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1211 = asUInt(reset)
node _T_1212 = eq(_T_1211, UInt<1>(0h0))
when _T_1212 :
node _T_1213 = eq(_T_1210, UInt<1>(0h0))
when _T_1213 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1210, UInt<1>(0h1), "") : assert_54
node _T_1214 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1215 = asUInt(reset)
node _T_1216 = eq(_T_1215, UInt<1>(0h0))
when _T_1216 :
node _T_1217 = eq(_T_1214, UInt<1>(0h0))
when _T_1217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1214, UInt<1>(0h1), "") : assert_55
node _T_1218 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1219 = asUInt(reset)
node _T_1220 = eq(_T_1219, UInt<1>(0h0))
when _T_1220 :
node _T_1221 = eq(_T_1218, UInt<1>(0h0))
when _T_1221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1218, UInt<1>(0h1), "") : assert_56
node _T_1222 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1223 = asUInt(reset)
node _T_1224 = eq(_T_1223, UInt<1>(0h0))
when _T_1224 :
node _T_1225 = eq(_T_1222, UInt<1>(0h0))
when _T_1225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1222, UInt<1>(0h1), "") : assert_57
node _T_1226 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1226 :
node _T_1227 = asUInt(reset)
node _T_1228 = eq(_T_1227, UInt<1>(0h0))
when _T_1228 :
node _T_1229 = eq(source_ok_1, UInt<1>(0h0))
when _T_1229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1230 = asUInt(reset)
node _T_1231 = eq(_T_1230, UInt<1>(0h0))
when _T_1231 :
node _T_1232 = eq(sink_ok, UInt<1>(0h0))
when _T_1232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1233 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1234 = asUInt(reset)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
when _T_1235 :
node _T_1236 = eq(_T_1233, UInt<1>(0h0))
when _T_1236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1233, UInt<1>(0h1), "") : assert_60
node _T_1237 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_61
node _T_1241 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_62
node _T_1245 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1246 = asUInt(reset)
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
when _T_1247 :
node _T_1248 = eq(_T_1245, UInt<1>(0h0))
when _T_1248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1245, UInt<1>(0h1), "") : assert_63
node _T_1249 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1250 = or(UInt<1>(0h1), _T_1249)
node _T_1251 = asUInt(reset)
node _T_1252 = eq(_T_1251, UInt<1>(0h0))
when _T_1252 :
node _T_1253 = eq(_T_1250, UInt<1>(0h0))
when _T_1253 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1250, UInt<1>(0h1), "") : assert_64
node _T_1254 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1254 :
node _T_1255 = asUInt(reset)
node _T_1256 = eq(_T_1255, UInt<1>(0h0))
when _T_1256 :
node _T_1257 = eq(source_ok_1, UInt<1>(0h0))
when _T_1257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1258 = asUInt(reset)
node _T_1259 = eq(_T_1258, UInt<1>(0h0))
when _T_1259 :
node _T_1260 = eq(sink_ok, UInt<1>(0h0))
when _T_1260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1261 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1262 = asUInt(reset)
node _T_1263 = eq(_T_1262, UInt<1>(0h0))
when _T_1263 :
node _T_1264 = eq(_T_1261, UInt<1>(0h0))
when _T_1264 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1261, UInt<1>(0h1), "") : assert_67
node _T_1265 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1266 = asUInt(reset)
node _T_1267 = eq(_T_1266, UInt<1>(0h0))
when _T_1267 :
node _T_1268 = eq(_T_1265, UInt<1>(0h0))
when _T_1268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1265, UInt<1>(0h1), "") : assert_68
node _T_1269 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(_T_1269, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1269, UInt<1>(0h1), "") : assert_69
node _T_1273 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1274 = or(_T_1273, io.in.d.bits.corrupt)
node _T_1275 = asUInt(reset)
node _T_1276 = eq(_T_1275, UInt<1>(0h0))
when _T_1276 :
node _T_1277 = eq(_T_1274, UInt<1>(0h0))
when _T_1277 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1274, UInt<1>(0h1), "") : assert_70
node _T_1278 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1279 = or(UInt<1>(0h1), _T_1278)
node _T_1280 = asUInt(reset)
node _T_1281 = eq(_T_1280, UInt<1>(0h0))
when _T_1281 :
node _T_1282 = eq(_T_1279, UInt<1>(0h0))
when _T_1282 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1279, UInt<1>(0h1), "") : assert_71
node _T_1283 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1283 :
node _T_1284 = asUInt(reset)
node _T_1285 = eq(_T_1284, UInt<1>(0h0))
when _T_1285 :
node _T_1286 = eq(source_ok_1, UInt<1>(0h0))
when _T_1286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1287 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1288 = asUInt(reset)
node _T_1289 = eq(_T_1288, UInt<1>(0h0))
when _T_1289 :
node _T_1290 = eq(_T_1287, UInt<1>(0h0))
when _T_1290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1287, UInt<1>(0h1), "") : assert_73
node _T_1291 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1292 = asUInt(reset)
node _T_1293 = eq(_T_1292, UInt<1>(0h0))
when _T_1293 :
node _T_1294 = eq(_T_1291, UInt<1>(0h0))
when _T_1294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1291, UInt<1>(0h1), "") : assert_74
node _T_1295 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1296 = or(UInt<1>(0h1), _T_1295)
node _T_1297 = asUInt(reset)
node _T_1298 = eq(_T_1297, UInt<1>(0h0))
when _T_1298 :
node _T_1299 = eq(_T_1296, UInt<1>(0h0))
when _T_1299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1296, UInt<1>(0h1), "") : assert_75
node _T_1300 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1300 :
node _T_1301 = asUInt(reset)
node _T_1302 = eq(_T_1301, UInt<1>(0h0))
when _T_1302 :
node _T_1303 = eq(source_ok_1, UInt<1>(0h0))
when _T_1303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1304 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1305 = asUInt(reset)
node _T_1306 = eq(_T_1305, UInt<1>(0h0))
when _T_1306 :
node _T_1307 = eq(_T_1304, UInt<1>(0h0))
when _T_1307 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1304, UInt<1>(0h1), "") : assert_77
node _T_1308 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1309 = or(_T_1308, io.in.d.bits.corrupt)
node _T_1310 = asUInt(reset)
node _T_1311 = eq(_T_1310, UInt<1>(0h0))
when _T_1311 :
node _T_1312 = eq(_T_1309, UInt<1>(0h0))
when _T_1312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1309, UInt<1>(0h1), "") : assert_78
node _T_1313 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1314 = or(UInt<1>(0h1), _T_1313)
node _T_1315 = asUInt(reset)
node _T_1316 = eq(_T_1315, UInt<1>(0h0))
when _T_1316 :
node _T_1317 = eq(_T_1314, UInt<1>(0h0))
when _T_1317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1314, UInt<1>(0h1), "") : assert_79
node _T_1318 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1318 :
node _T_1319 = asUInt(reset)
node _T_1320 = eq(_T_1319, UInt<1>(0h0))
when _T_1320 :
node _T_1321 = eq(source_ok_1, UInt<1>(0h0))
when _T_1321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1322 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1323 = asUInt(reset)
node _T_1324 = eq(_T_1323, UInt<1>(0h0))
when _T_1324 :
node _T_1325 = eq(_T_1322, UInt<1>(0h0))
when _T_1325 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1322, UInt<1>(0h1), "") : assert_81
node _T_1326 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1327 = asUInt(reset)
node _T_1328 = eq(_T_1327, UInt<1>(0h0))
when _T_1328 :
node _T_1329 = eq(_T_1326, UInt<1>(0h0))
when _T_1329 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1326, UInt<1>(0h1), "") : assert_82
node _T_1330 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1331 = or(UInt<1>(0h1), _T_1330)
node _T_1332 = asUInt(reset)
node _T_1333 = eq(_T_1332, UInt<1>(0h0))
when _T_1333 :
node _T_1334 = eq(_T_1331, UInt<1>(0h0))
when _T_1334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1331, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1335 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1336 = asUInt(reset)
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(_T_1335, UInt<1>(0h0))
when _T_1338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1335, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1339 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1340 = asUInt(reset)
node _T_1341 = eq(_T_1340, UInt<1>(0h0))
when _T_1341 :
node _T_1342 = eq(_T_1339, UInt<1>(0h0))
when _T_1342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1339, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1343 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1344 = asUInt(reset)
node _T_1345 = eq(_T_1344, UInt<1>(0h0))
when _T_1345 :
node _T_1346 = eq(_T_1343, UInt<1>(0h0))
when _T_1346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1343, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1347 = eq(a_first, UInt<1>(0h0))
node _T_1348 = and(io.in.a.valid, _T_1347)
when _T_1348 :
node _T_1349 = eq(io.in.a.bits.opcode, opcode)
node _T_1350 = asUInt(reset)
node _T_1351 = eq(_T_1350, UInt<1>(0h0))
when _T_1351 :
node _T_1352 = eq(_T_1349, UInt<1>(0h0))
when _T_1352 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1349, UInt<1>(0h1), "") : assert_87
node _T_1353 = eq(io.in.a.bits.param, param)
node _T_1354 = asUInt(reset)
node _T_1355 = eq(_T_1354, UInt<1>(0h0))
when _T_1355 :
node _T_1356 = eq(_T_1353, UInt<1>(0h0))
when _T_1356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1353, UInt<1>(0h1), "") : assert_88
node _T_1357 = eq(io.in.a.bits.size, size)
node _T_1358 = asUInt(reset)
node _T_1359 = eq(_T_1358, UInt<1>(0h0))
when _T_1359 :
node _T_1360 = eq(_T_1357, UInt<1>(0h0))
when _T_1360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1357, UInt<1>(0h1), "") : assert_89
node _T_1361 = eq(io.in.a.bits.source, source)
node _T_1362 = asUInt(reset)
node _T_1363 = eq(_T_1362, UInt<1>(0h0))
when _T_1363 :
node _T_1364 = eq(_T_1361, UInt<1>(0h0))
when _T_1364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1361, UInt<1>(0h1), "") : assert_90
node _T_1365 = eq(io.in.a.bits.address, address)
node _T_1366 = asUInt(reset)
node _T_1367 = eq(_T_1366, UInt<1>(0h0))
when _T_1367 :
node _T_1368 = eq(_T_1365, UInt<1>(0h0))
when _T_1368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1365, UInt<1>(0h1), "") : assert_91
node _T_1369 = and(io.in.a.ready, io.in.a.valid)
node _T_1370 = and(_T_1369, a_first)
when _T_1370 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1371 = eq(d_first, UInt<1>(0h0))
node _T_1372 = and(io.in.d.valid, _T_1371)
when _T_1372 :
node _T_1373 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1374 = asUInt(reset)
node _T_1375 = eq(_T_1374, UInt<1>(0h0))
when _T_1375 :
node _T_1376 = eq(_T_1373, UInt<1>(0h0))
when _T_1376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1373, UInt<1>(0h1), "") : assert_92
node _T_1377 = eq(io.in.d.bits.param, param_1)
node _T_1378 = asUInt(reset)
node _T_1379 = eq(_T_1378, UInt<1>(0h0))
when _T_1379 :
node _T_1380 = eq(_T_1377, UInt<1>(0h0))
when _T_1380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1377, UInt<1>(0h1), "") : assert_93
node _T_1381 = eq(io.in.d.bits.size, size_1)
node _T_1382 = asUInt(reset)
node _T_1383 = eq(_T_1382, UInt<1>(0h0))
when _T_1383 :
node _T_1384 = eq(_T_1381, UInt<1>(0h0))
when _T_1384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1381, UInt<1>(0h1), "") : assert_94
node _T_1385 = eq(io.in.d.bits.source, source_1)
node _T_1386 = asUInt(reset)
node _T_1387 = eq(_T_1386, UInt<1>(0h0))
when _T_1387 :
node _T_1388 = eq(_T_1385, UInt<1>(0h0))
when _T_1388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1385, UInt<1>(0h1), "") : assert_95
node _T_1389 = eq(io.in.d.bits.sink, sink)
node _T_1390 = asUInt(reset)
node _T_1391 = eq(_T_1390, UInt<1>(0h0))
when _T_1391 :
node _T_1392 = eq(_T_1389, UInt<1>(0h0))
when _T_1392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1389, UInt<1>(0h1), "") : assert_96
node _T_1393 = eq(io.in.d.bits.denied, denied)
node _T_1394 = asUInt(reset)
node _T_1395 = eq(_T_1394, UInt<1>(0h0))
when _T_1395 :
node _T_1396 = eq(_T_1393, UInt<1>(0h0))
when _T_1396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1393, UInt<1>(0h1), "") : assert_97
node _T_1397 = and(io.in.d.ready, io.in.d.valid)
node _T_1398 = and(_T_1397, d_first)
when _T_1398 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<16>
connect a_set, UInt<16>(0h0)
wire a_set_wo_ready : UInt<16>
connect a_set_wo_ready, UInt<16>(0h0)
wire a_opcodes_set : UInt<64>
connect a_opcodes_set, UInt<64>(0h0)
wire a_sizes_set : UInt<128>
connect a_sizes_set, UInt<128>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1399 = and(io.in.a.valid, a_first_1)
node _T_1400 = and(_T_1399, UInt<1>(0h1))
when _T_1400 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1401 = and(io.in.a.ready, io.in.a.valid)
node _T_1402 = and(_T_1401, a_first_1)
node _T_1403 = and(_T_1402, UInt<1>(0h1))
when _T_1403 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1404 = dshr(inflight, io.in.a.bits.source)
node _T_1405 = bits(_T_1404, 0, 0)
node _T_1406 = eq(_T_1405, UInt<1>(0h0))
node _T_1407 = asUInt(reset)
node _T_1408 = eq(_T_1407, UInt<1>(0h0))
when _T_1408 :
node _T_1409 = eq(_T_1406, UInt<1>(0h0))
when _T_1409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1406, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<16>
connect d_clr, UInt<16>(0h0)
wire d_clr_wo_ready : UInt<16>
connect d_clr_wo_ready, UInt<16>(0h0)
wire d_opcodes_clr : UInt<64>
connect d_opcodes_clr, UInt<64>(0h0)
wire d_sizes_clr : UInt<128>
connect d_sizes_clr, UInt<128>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1410 = and(io.in.d.valid, d_first_1)
node _T_1411 = and(_T_1410, UInt<1>(0h1))
node _T_1412 = eq(d_release_ack, UInt<1>(0h0))
node _T_1413 = and(_T_1411, _T_1412)
when _T_1413 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1414 = and(io.in.d.ready, io.in.d.valid)
node _T_1415 = and(_T_1414, d_first_1)
node _T_1416 = and(_T_1415, UInt<1>(0h1))
node _T_1417 = eq(d_release_ack, UInt<1>(0h0))
node _T_1418 = and(_T_1416, _T_1417)
when _T_1418 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1419 = and(io.in.d.valid, d_first_1)
node _T_1420 = and(_T_1419, UInt<1>(0h1))
node _T_1421 = eq(d_release_ack, UInt<1>(0h0))
node _T_1422 = and(_T_1420, _T_1421)
when _T_1422 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1423 = dshr(inflight, io.in.d.bits.source)
node _T_1424 = bits(_T_1423, 0, 0)
node _T_1425 = or(_T_1424, same_cycle_resp)
node _T_1426 = asUInt(reset)
node _T_1427 = eq(_T_1426, UInt<1>(0h0))
when _T_1427 :
node _T_1428 = eq(_T_1425, UInt<1>(0h0))
when _T_1428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1425, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1429 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1430 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1431 = or(_T_1429, _T_1430)
node _T_1432 = asUInt(reset)
node _T_1433 = eq(_T_1432, UInt<1>(0h0))
when _T_1433 :
node _T_1434 = eq(_T_1431, UInt<1>(0h0))
when _T_1434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1431, UInt<1>(0h1), "") : assert_100
node _T_1435 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1436 = asUInt(reset)
node _T_1437 = eq(_T_1436, UInt<1>(0h0))
when _T_1437 :
node _T_1438 = eq(_T_1435, UInt<1>(0h0))
when _T_1438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1435, UInt<1>(0h1), "") : assert_101
else :
node _T_1439 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1440 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1441 = or(_T_1439, _T_1440)
node _T_1442 = asUInt(reset)
node _T_1443 = eq(_T_1442, UInt<1>(0h0))
when _T_1443 :
node _T_1444 = eq(_T_1441, UInt<1>(0h0))
when _T_1444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1441, UInt<1>(0h1), "") : assert_102
node _T_1445 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1446 = asUInt(reset)
node _T_1447 = eq(_T_1446, UInt<1>(0h0))
when _T_1447 :
node _T_1448 = eq(_T_1445, UInt<1>(0h0))
when _T_1448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1445, UInt<1>(0h1), "") : assert_103
node _T_1449 = and(io.in.d.valid, d_first_1)
node _T_1450 = and(_T_1449, a_first_1)
node _T_1451 = and(_T_1450, io.in.a.valid)
node _T_1452 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1453 = and(_T_1451, _T_1452)
node _T_1454 = eq(d_release_ack, UInt<1>(0h0))
node _T_1455 = and(_T_1453, _T_1454)
when _T_1455 :
node _T_1456 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1457 = or(_T_1456, io.in.a.ready)
node _T_1458 = asUInt(reset)
node _T_1459 = eq(_T_1458, UInt<1>(0h0))
when _T_1459 :
node _T_1460 = eq(_T_1457, UInt<1>(0h0))
when _T_1460 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1457, UInt<1>(0h1), "") : assert_104
node _T_1461 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1462 = orr(a_set_wo_ready)
node _T_1463 = eq(_T_1462, UInt<1>(0h0))
node _T_1464 = or(_T_1461, _T_1463)
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(_T_1464, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1464, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_24
node _T_1468 = orr(inflight)
node _T_1469 = eq(_T_1468, UInt<1>(0h0))
node _T_1470 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1471 = or(_T_1469, _T_1470)
node _T_1472 = lt(watchdog, plusarg_reader.out)
node _T_1473 = or(_T_1471, _T_1472)
node _T_1474 = asUInt(reset)
node _T_1475 = eq(_T_1474, UInt<1>(0h0))
when _T_1475 :
node _T_1476 = eq(_T_1473, UInt<1>(0h0))
when _T_1476 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1473, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1477 = and(io.in.a.ready, io.in.a.valid)
node _T_1478 = and(io.in.d.ready, io.in.d.valid)
node _T_1479 = or(_T_1477, _T_1478)
when _T_1479 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0)
regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<4>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<16>
connect c_set, UInt<16>(0h0)
wire c_set_wo_ready : UInt<16>
connect c_set_wo_ready, UInt<16>(0h0)
wire c_opcodes_set : UInt<64>
connect c_opcodes_set, UInt<64>(0h0)
wire c_sizes_set : UInt<128>
connect c_sizes_set, UInt<128>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1480 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1481 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1482 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1483 = and(_T_1481, _T_1482)
node _T_1484 = and(_T_1480, _T_1483)
when _T_1484 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1485 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1486 = and(_T_1485, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<4>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1487 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1488 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1489 = and(_T_1487, _T_1488)
node _T_1490 = and(_T_1486, _T_1489)
when _T_1490 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1491 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1492 = bits(_T_1491, 0, 0)
node _T_1493 = eq(_T_1492, UInt<1>(0h0))
node _T_1494 = asUInt(reset)
node _T_1495 = eq(_T_1494, UInt<1>(0h0))
when _T_1495 :
node _T_1496 = eq(_T_1493, UInt<1>(0h0))
when _T_1496 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1493, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<16>
connect d_clr_1, UInt<16>(0h0)
wire d_clr_wo_ready_1 : UInt<16>
connect d_clr_wo_ready_1, UInt<16>(0h0)
wire d_opcodes_clr_1 : UInt<64>
connect d_opcodes_clr_1, UInt<64>(0h0)
wire d_sizes_clr_1 : UInt<128>
connect d_sizes_clr_1, UInt<128>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1497 = and(io.in.d.valid, d_first_2)
node _T_1498 = and(_T_1497, UInt<1>(0h1))
node _T_1499 = and(_T_1498, d_release_ack_1)
when _T_1499 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1500 = and(io.in.d.ready, io.in.d.valid)
node _T_1501 = and(_T_1500, d_first_2)
node _T_1502 = and(_T_1501, UInt<1>(0h1))
node _T_1503 = and(_T_1502, d_release_ack_1)
when _T_1503 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1504 = and(io.in.d.valid, d_first_2)
node _T_1505 = and(_T_1504, UInt<1>(0h1))
node _T_1506 = and(_T_1505, d_release_ack_1)
when _T_1506 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1507 = dshr(inflight_1, io.in.d.bits.source)
node _T_1508 = bits(_T_1507, 0, 0)
node _T_1509 = or(_T_1508, same_cycle_resp_1)
node _T_1510 = asUInt(reset)
node _T_1511 = eq(_T_1510, UInt<1>(0h0))
when _T_1511 :
node _T_1512 = eq(_T_1509, UInt<1>(0h0))
when _T_1512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1509, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<4>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1513 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1514 = asUInt(reset)
node _T_1515 = eq(_T_1514, UInt<1>(0h0))
when _T_1515 :
node _T_1516 = eq(_T_1513, UInt<1>(0h0))
when _T_1516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1513, UInt<1>(0h1), "") : assert_109
else :
node _T_1517 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1518 = asUInt(reset)
node _T_1519 = eq(_T_1518, UInt<1>(0h0))
when _T_1519 :
node _T_1520 = eq(_T_1517, UInt<1>(0h0))
when _T_1520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1517, UInt<1>(0h1), "") : assert_110
node _T_1521 = and(io.in.d.valid, d_first_2)
node _T_1522 = and(_T_1521, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<4>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1523 = and(_T_1522, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<4>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1524 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1525 = and(_T_1523, _T_1524)
node _T_1526 = and(_T_1525, d_release_ack_1)
node _T_1527 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1528 = and(_T_1526, _T_1527)
when _T_1528 :
node _T_1529 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<4>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1530 = or(_T_1529, _WIRE_23.ready)
node _T_1531 = asUInt(reset)
node _T_1532 = eq(_T_1531, UInt<1>(0h0))
when _T_1532 :
node _T_1533 = eq(_T_1530, UInt<1>(0h0))
when _T_1533 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1530, UInt<1>(0h1), "") : assert_111
node _T_1534 = orr(c_set_wo_ready)
when _T_1534 :
node _T_1535 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1536 = asUInt(reset)
node _T_1537 = eq(_T_1536, UInt<1>(0h0))
when _T_1537 :
node _T_1538 = eq(_T_1535, UInt<1>(0h0))
when _T_1538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1535, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_25
node _T_1539 = orr(inflight_1)
node _T_1540 = eq(_T_1539, UInt<1>(0h0))
node _T_1541 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1542 = or(_T_1540, _T_1541)
node _T_1543 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1544 = or(_T_1542, _T_1543)
node _T_1545 = asUInt(reset)
node _T_1546 = eq(_T_1545, UInt<1>(0h0))
when _T_1546 :
node _T_1547 = eq(_T_1544, UInt<1>(0h0))
when _T_1547 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1544, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<4>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1548 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1549 = and(io.in.d.ready, io.in.d.valid)
node _T_1550 = or(_T_1548, _T_1549)
when _T_1550 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_12( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34]
wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34]
wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_7 = _source_ok_T_6 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_13 = _source_ok_T_12 == 2'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_19 = &_source_ok_T_18; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire _source_ok_T_24 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_25 = _source_ok_T_24 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_25 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_27 = _source_ok_T_26 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_0 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_33 = _source_ok_T_32 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_39 = _source_ok_T_38 == 2'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_45 = &_source_ok_T_44; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_49; // @[Parameters.scala:1138:31]
wire _source_ok_T_50 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_51 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1477 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1477; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1477; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1550 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1550; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1550; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1550; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [15:0] inflight; // @[Monitor.scala:614:27]
reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [127:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [15:0] a_set; // @[Monitor.scala:626:34]
wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [127:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1403 = _T_1477 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1403 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1403 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1403 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1403 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1403 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [15:0] d_clr; // @[Monitor.scala:664:34]
wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1449 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1449 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1418 = _T_1550 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1418 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1418 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1418 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [15:0] inflight_1; // @[Monitor.scala:726:35]
wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [15:0] d_clr_1; // @[Monitor.scala:774:34]
wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1521 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1521 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire _T_1503 = _T_1550 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1503 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1503 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1503 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_172 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_187
connect io_out_sink_valid_0.clock, clock
connect io_out_sink_valid_0.reset, reset
connect io_out_sink_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_172( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_187 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_1 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
node _source_ok_T_1 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _source_ok_T_2 = eq(io.in.a.bits.source, UInt<2>(0h2))
wire _source_ok_WIRE : UInt<1>[3]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_1
connect _source_ok_WIRE[2], _source_ok_T_2
node _source_ok_T_3 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node source_ok = or(_source_ok_T_3, _source_ok_WIRE[2])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_15 = cvt(_T_14)
node _T_16 = and(_T_15, asSInt(UInt<1>(0h0)))
node _T_17 = asSInt(_T_16)
node _T_18 = eq(_T_17, asSInt(UInt<1>(0h0)))
node _T_19 = or(_T_13, _T_18)
node _T_20 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_21 = eq(_T_20, UInt<1>(0h0))
node _T_22 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_23 = cvt(_T_22)
node _T_24 = and(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = asSInt(_T_24)
node _T_26 = eq(_T_25, asSInt(UInt<1>(0h0)))
node _T_27 = or(_T_21, _T_26)
node _T_28 = and(_T_11, _T_19)
node _T_29 = and(_T_28, _T_27)
node _T_30 = asUInt(reset)
node _T_31 = eq(_T_30, UInt<1>(0h0))
when _T_31 :
node _T_32 = eq(_T_29, UInt<1>(0h0))
when _T_32 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_29, UInt<1>(0h1), "") : assert_1
node _T_33 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_33 :
node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_38 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_39 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_40 = or(_T_37, _T_38)
node _T_41 = or(_T_40, _T_39)
node _T_42 = and(_T_36, _T_41)
node _T_43 = or(UInt<1>(0h0), _T_42)
node _T_44 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<14>(0h2000)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_51 = cvt(_T_50)
node _T_52 = and(_T_51, asSInt(UInt<11>(0h400)))
node _T_53 = asSInt(_T_52)
node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0)))
node _T_55 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_56 = cvt(_T_55)
node _T_57 = and(_T_56, asSInt(UInt<9>(0h100)))
node _T_58 = asSInt(_T_57)
node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0)))
node _T_60 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_61 = cvt(_T_60)
node _T_62 = and(_T_61, asSInt(UInt<13>(0h1000)))
node _T_63 = asSInt(_T_62)
node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0)))
node _T_65 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<18>(0h2f000)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<17>(0h10000)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<27>(0h4000000)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<13>(0h1000)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_49, _T_54)
node _T_96 = or(_T_95, _T_59)
node _T_97 = or(_T_96, _T_64)
node _T_98 = or(_T_97, _T_69)
node _T_99 = or(_T_98, _T_74)
node _T_100 = or(_T_99, _T_79)
node _T_101 = or(_T_100, _T_84)
node _T_102 = or(_T_101, _T_89)
node _T_103 = or(_T_102, _T_94)
node _T_104 = and(_T_44, _T_103)
node _T_105 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_106 = or(UInt<1>(0h0), _T_105)
node _T_107 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<17>(0h10000)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<29>(0h10000000)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = or(_T_111, _T_116)
node _T_118 = and(_T_106, _T_117)
node _T_119 = or(UInt<1>(0h0), _T_104)
node _T_120 = or(_T_119, _T_118)
node _T_121 = and(_T_43, _T_120)
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_121, UInt<1>(0h1), "") : assert_2
node _T_125 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_126 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_127 = eq(io.in.a.bits.source, UInt<2>(0h2))
wire _WIRE : UInt<1>[3]
connect _WIRE[0], _T_125
connect _WIRE[1], _T_126
connect _WIRE[2], _T_127
node _T_128 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_129 = mux(_WIRE[0], _T_128, UInt<1>(0h0))
node _T_130 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_131 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_132 = or(_T_129, _T_130)
node _T_133 = or(_T_132, _T_131)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_133
node _T_134 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_135 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_136 = and(_T_134, _T_135)
node _T_137 = or(UInt<1>(0h0), _T_136)
node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_139 = cvt(_T_138)
node _T_140 = and(_T_139, asSInt(UInt<14>(0h2000)))
node _T_141 = asSInt(_T_140)
node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0)))
node _T_143 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_144 = cvt(_T_143)
node _T_145 = and(_T_144, asSInt(UInt<11>(0h400)))
node _T_146 = asSInt(_T_145)
node _T_147 = eq(_T_146, asSInt(UInt<1>(0h0)))
node _T_148 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_149 = cvt(_T_148)
node _T_150 = and(_T_149, asSInt(UInt<9>(0h100)))
node _T_151 = asSInt(_T_150)
node _T_152 = eq(_T_151, asSInt(UInt<1>(0h0)))
node _T_153 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_154 = cvt(_T_153)
node _T_155 = and(_T_154, asSInt(UInt<13>(0h1000)))
node _T_156 = asSInt(_T_155)
node _T_157 = eq(_T_156, asSInt(UInt<1>(0h0)))
node _T_158 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_159 = cvt(_T_158)
node _T_160 = and(_T_159, asSInt(UInt<17>(0h10000)))
node _T_161 = asSInt(_T_160)
node _T_162 = eq(_T_161, asSInt(UInt<1>(0h0)))
node _T_163 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_164 = cvt(_T_163)
node _T_165 = and(_T_164, asSInt(UInt<18>(0h2f000)))
node _T_166 = asSInt(_T_165)
node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0)))
node _T_168 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_169 = cvt(_T_168)
node _T_170 = and(_T_169, asSInt(UInt<17>(0h10000)))
node _T_171 = asSInt(_T_170)
node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_174 = cvt(_T_173)
node _T_175 = and(_T_174, asSInt(UInt<13>(0h1000)))
node _T_176 = asSInt(_T_175)
node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0)))
node _T_178 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_179 = cvt(_T_178)
node _T_180 = and(_T_179, asSInt(UInt<17>(0h10000)))
node _T_181 = asSInt(_T_180)
node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0)))
node _T_183 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_184 = cvt(_T_183)
node _T_185 = and(_T_184, asSInt(UInt<27>(0h4000000)))
node _T_186 = asSInt(_T_185)
node _T_187 = eq(_T_186, asSInt(UInt<1>(0h0)))
node _T_188 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_189 = cvt(_T_188)
node _T_190 = and(_T_189, asSInt(UInt<13>(0h1000)))
node _T_191 = asSInt(_T_190)
node _T_192 = eq(_T_191, asSInt(UInt<1>(0h0)))
node _T_193 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_194 = cvt(_T_193)
node _T_195 = and(_T_194, asSInt(UInt<29>(0h10000000)))
node _T_196 = asSInt(_T_195)
node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0)))
node _T_198 = or(_T_142, _T_147)
node _T_199 = or(_T_198, _T_152)
node _T_200 = or(_T_199, _T_157)
node _T_201 = or(_T_200, _T_162)
node _T_202 = or(_T_201, _T_167)
node _T_203 = or(_T_202, _T_172)
node _T_204 = or(_T_203, _T_177)
node _T_205 = or(_T_204, _T_182)
node _T_206 = or(_T_205, _T_187)
node _T_207 = or(_T_206, _T_192)
node _T_208 = or(_T_207, _T_197)
node _T_209 = and(_T_137, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = and(_WIRE_1, _T_210)
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_211, UInt<1>(0h1), "") : assert_3
node _T_215 = asUInt(reset)
node _T_216 = eq(_T_215, UInt<1>(0h0))
when _T_216 :
node _T_217 = eq(source_ok, UInt<1>(0h0))
when _T_217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_218 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_218, UInt<1>(0h1), "") : assert_5
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(is_aligned, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_225 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_225, UInt<1>(0h1), "") : assert_7
node _T_229 = not(io.in.a.bits.mask)
node _T_230 = eq(_T_229, UInt<1>(0h0))
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(_T_230, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_230, UInt<1>(0h1), "") : assert_8
node _T_234 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_234, UInt<1>(0h1), "") : assert_9
node _T_238 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_238 :
node _T_239 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_240 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_241 = and(_T_239, _T_240)
node _T_242 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_243 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_244 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_245 = or(_T_242, _T_243)
node _T_246 = or(_T_245, _T_244)
node _T_247 = and(_T_241, _T_246)
node _T_248 = or(UInt<1>(0h0), _T_247)
node _T_249 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_251 = cvt(_T_250)
node _T_252 = and(_T_251, asSInt(UInt<14>(0h2000)))
node _T_253 = asSInt(_T_252)
node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0)))
node _T_255 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_256 = cvt(_T_255)
node _T_257 = and(_T_256, asSInt(UInt<11>(0h400)))
node _T_258 = asSInt(_T_257)
node _T_259 = eq(_T_258, asSInt(UInt<1>(0h0)))
node _T_260 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_261 = cvt(_T_260)
node _T_262 = and(_T_261, asSInt(UInt<9>(0h100)))
node _T_263 = asSInt(_T_262)
node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0)))
node _T_265 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_266 = cvt(_T_265)
node _T_267 = and(_T_266, asSInt(UInt<13>(0h1000)))
node _T_268 = asSInt(_T_267)
node _T_269 = eq(_T_268, asSInt(UInt<1>(0h0)))
node _T_270 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_271 = cvt(_T_270)
node _T_272 = and(_T_271, asSInt(UInt<17>(0h10000)))
node _T_273 = asSInt(_T_272)
node _T_274 = eq(_T_273, asSInt(UInt<1>(0h0)))
node _T_275 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_276 = cvt(_T_275)
node _T_277 = and(_T_276, asSInt(UInt<18>(0h2f000)))
node _T_278 = asSInt(_T_277)
node _T_279 = eq(_T_278, asSInt(UInt<1>(0h0)))
node _T_280 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_281 = cvt(_T_280)
node _T_282 = and(_T_281, asSInt(UInt<17>(0h10000)))
node _T_283 = asSInt(_T_282)
node _T_284 = eq(_T_283, asSInt(UInt<1>(0h0)))
node _T_285 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_286 = cvt(_T_285)
node _T_287 = and(_T_286, asSInt(UInt<13>(0h1000)))
node _T_288 = asSInt(_T_287)
node _T_289 = eq(_T_288, asSInt(UInt<1>(0h0)))
node _T_290 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_291 = cvt(_T_290)
node _T_292 = and(_T_291, asSInt(UInt<27>(0h4000000)))
node _T_293 = asSInt(_T_292)
node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0)))
node _T_295 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_296 = cvt(_T_295)
node _T_297 = and(_T_296, asSInt(UInt<13>(0h1000)))
node _T_298 = asSInt(_T_297)
node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0)))
node _T_300 = or(_T_254, _T_259)
node _T_301 = or(_T_300, _T_264)
node _T_302 = or(_T_301, _T_269)
node _T_303 = or(_T_302, _T_274)
node _T_304 = or(_T_303, _T_279)
node _T_305 = or(_T_304, _T_284)
node _T_306 = or(_T_305, _T_289)
node _T_307 = or(_T_306, _T_294)
node _T_308 = or(_T_307, _T_299)
node _T_309 = and(_T_249, _T_308)
node _T_310 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_311 = or(UInt<1>(0h0), _T_310)
node _T_312 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_313 = cvt(_T_312)
node _T_314 = and(_T_313, asSInt(UInt<17>(0h10000)))
node _T_315 = asSInt(_T_314)
node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0)))
node _T_317 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_318 = cvt(_T_317)
node _T_319 = and(_T_318, asSInt(UInt<29>(0h10000000)))
node _T_320 = asSInt(_T_319)
node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0)))
node _T_322 = or(_T_316, _T_321)
node _T_323 = and(_T_311, _T_322)
node _T_324 = or(UInt<1>(0h0), _T_309)
node _T_325 = or(_T_324, _T_323)
node _T_326 = and(_T_248, _T_325)
node _T_327 = asUInt(reset)
node _T_328 = eq(_T_327, UInt<1>(0h0))
when _T_328 :
node _T_329 = eq(_T_326, UInt<1>(0h0))
when _T_329 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_326, UInt<1>(0h1), "") : assert_10
node _T_330 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_331 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_332 = eq(io.in.a.bits.source, UInt<2>(0h2))
wire _WIRE_2 : UInt<1>[3]
connect _WIRE_2[0], _T_330
connect _WIRE_2[1], _T_331
connect _WIRE_2[2], _T_332
node _T_333 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_334 = mux(_WIRE_2[0], _T_333, UInt<1>(0h0))
node _T_335 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_336 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_337 = or(_T_334, _T_335)
node _T_338 = or(_T_337, _T_336)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_338
node _T_339 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_340 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_341 = and(_T_339, _T_340)
node _T_342 = or(UInt<1>(0h0), _T_341)
node _T_343 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_344 = cvt(_T_343)
node _T_345 = and(_T_344, asSInt(UInt<14>(0h2000)))
node _T_346 = asSInt(_T_345)
node _T_347 = eq(_T_346, asSInt(UInt<1>(0h0)))
node _T_348 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_349 = cvt(_T_348)
node _T_350 = and(_T_349, asSInt(UInt<11>(0h400)))
node _T_351 = asSInt(_T_350)
node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0)))
node _T_353 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_354 = cvt(_T_353)
node _T_355 = and(_T_354, asSInt(UInt<9>(0h100)))
node _T_356 = asSInt(_T_355)
node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0)))
node _T_358 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_359 = cvt(_T_358)
node _T_360 = and(_T_359, asSInt(UInt<13>(0h1000)))
node _T_361 = asSInt(_T_360)
node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0)))
node _T_363 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_364 = cvt(_T_363)
node _T_365 = and(_T_364, asSInt(UInt<17>(0h10000)))
node _T_366 = asSInt(_T_365)
node _T_367 = eq(_T_366, asSInt(UInt<1>(0h0)))
node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<18>(0h2f000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_374 = cvt(_T_373)
node _T_375 = and(_T_374, asSInt(UInt<17>(0h10000)))
node _T_376 = asSInt(_T_375)
node _T_377 = eq(_T_376, asSInt(UInt<1>(0h0)))
node _T_378 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<13>(0h1000)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_384 = cvt(_T_383)
node _T_385 = and(_T_384, asSInt(UInt<17>(0h10000)))
node _T_386 = asSInt(_T_385)
node _T_387 = eq(_T_386, asSInt(UInt<1>(0h0)))
node _T_388 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_389 = cvt(_T_388)
node _T_390 = and(_T_389, asSInt(UInt<27>(0h4000000)))
node _T_391 = asSInt(_T_390)
node _T_392 = eq(_T_391, asSInt(UInt<1>(0h0)))
node _T_393 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_394 = cvt(_T_393)
node _T_395 = and(_T_394, asSInt(UInt<13>(0h1000)))
node _T_396 = asSInt(_T_395)
node _T_397 = eq(_T_396, asSInt(UInt<1>(0h0)))
node _T_398 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_399 = cvt(_T_398)
node _T_400 = and(_T_399, asSInt(UInt<29>(0h10000000)))
node _T_401 = asSInt(_T_400)
node _T_402 = eq(_T_401, asSInt(UInt<1>(0h0)))
node _T_403 = or(_T_347, _T_352)
node _T_404 = or(_T_403, _T_357)
node _T_405 = or(_T_404, _T_362)
node _T_406 = or(_T_405, _T_367)
node _T_407 = or(_T_406, _T_372)
node _T_408 = or(_T_407, _T_377)
node _T_409 = or(_T_408, _T_382)
node _T_410 = or(_T_409, _T_387)
node _T_411 = or(_T_410, _T_392)
node _T_412 = or(_T_411, _T_397)
node _T_413 = or(_T_412, _T_402)
node _T_414 = and(_T_342, _T_413)
node _T_415 = or(UInt<1>(0h0), _T_414)
node _T_416 = and(_WIRE_3, _T_415)
node _T_417 = asUInt(reset)
node _T_418 = eq(_T_417, UInt<1>(0h0))
when _T_418 :
node _T_419 = eq(_T_416, UInt<1>(0h0))
when _T_419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_416, UInt<1>(0h1), "") : assert_11
node _T_420 = asUInt(reset)
node _T_421 = eq(_T_420, UInt<1>(0h0))
when _T_421 :
node _T_422 = eq(source_ok, UInt<1>(0h0))
when _T_422 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_423 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_424 = asUInt(reset)
node _T_425 = eq(_T_424, UInt<1>(0h0))
when _T_425 :
node _T_426 = eq(_T_423, UInt<1>(0h0))
when _T_426 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_423, UInt<1>(0h1), "") : assert_13
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(is_aligned, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_430 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_431 = asUInt(reset)
node _T_432 = eq(_T_431, UInt<1>(0h0))
when _T_432 :
node _T_433 = eq(_T_430, UInt<1>(0h0))
when _T_433 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_430, UInt<1>(0h1), "") : assert_15
node _T_434 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_435 = asUInt(reset)
node _T_436 = eq(_T_435, UInt<1>(0h0))
when _T_436 :
node _T_437 = eq(_T_434, UInt<1>(0h0))
when _T_437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_434, UInt<1>(0h1), "") : assert_16
node _T_438 = not(io.in.a.bits.mask)
node _T_439 = eq(_T_438, UInt<1>(0h0))
node _T_440 = asUInt(reset)
node _T_441 = eq(_T_440, UInt<1>(0h0))
when _T_441 :
node _T_442 = eq(_T_439, UInt<1>(0h0))
when _T_442 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_439, UInt<1>(0h1), "") : assert_17
node _T_443 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_444 = asUInt(reset)
node _T_445 = eq(_T_444, UInt<1>(0h0))
when _T_445 :
node _T_446 = eq(_T_443, UInt<1>(0h0))
when _T_446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_443, UInt<1>(0h1), "") : assert_18
node _T_447 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_447 :
node _T_448 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_449 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_450 = and(_T_448, _T_449)
node _T_451 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_452 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_453 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_454 = or(_T_451, _T_452)
node _T_455 = or(_T_454, _T_453)
node _T_456 = and(_T_450, _T_455)
node _T_457 = or(UInt<1>(0h0), _T_456)
node _T_458 = asUInt(reset)
node _T_459 = eq(_T_458, UInt<1>(0h0))
when _T_459 :
node _T_460 = eq(_T_457, UInt<1>(0h0))
when _T_460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_457, UInt<1>(0h1), "") : assert_19
node _T_461 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_462 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_463 = and(_T_461, _T_462)
node _T_464 = or(UInt<1>(0h0), _T_463)
node _T_465 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_466 = cvt(_T_465)
node _T_467 = and(_T_466, asSInt(UInt<13>(0h1000)))
node _T_468 = asSInt(_T_467)
node _T_469 = eq(_T_468, asSInt(UInt<1>(0h0)))
node _T_470 = and(_T_464, _T_469)
node _T_471 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_472 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_473 = and(_T_471, _T_472)
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_476 = cvt(_T_475)
node _T_477 = and(_T_476, asSInt(UInt<14>(0h2000)))
node _T_478 = asSInt(_T_477)
node _T_479 = eq(_T_478, asSInt(UInt<1>(0h0)))
node _T_480 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_481 = cvt(_T_480)
node _T_482 = and(_T_481, asSInt(UInt<11>(0h400)))
node _T_483 = asSInt(_T_482)
node _T_484 = eq(_T_483, asSInt(UInt<1>(0h0)))
node _T_485 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_486 = cvt(_T_485)
node _T_487 = and(_T_486, asSInt(UInt<9>(0h100)))
node _T_488 = asSInt(_T_487)
node _T_489 = eq(_T_488, asSInt(UInt<1>(0h0)))
node _T_490 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_491 = cvt(_T_490)
node _T_492 = and(_T_491, asSInt(UInt<17>(0h10000)))
node _T_493 = asSInt(_T_492)
node _T_494 = eq(_T_493, asSInt(UInt<1>(0h0)))
node _T_495 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_496 = cvt(_T_495)
node _T_497 = and(_T_496, asSInt(UInt<18>(0h2f000)))
node _T_498 = asSInt(_T_497)
node _T_499 = eq(_T_498, asSInt(UInt<1>(0h0)))
node _T_500 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_501 = cvt(_T_500)
node _T_502 = and(_T_501, asSInt(UInt<17>(0h10000)))
node _T_503 = asSInt(_T_502)
node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0)))
node _T_505 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_506 = cvt(_T_505)
node _T_507 = and(_T_506, asSInt(UInt<13>(0h1000)))
node _T_508 = asSInt(_T_507)
node _T_509 = eq(_T_508, asSInt(UInt<1>(0h0)))
node _T_510 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_511 = cvt(_T_510)
node _T_512 = and(_T_511, asSInt(UInt<17>(0h10000)))
node _T_513 = asSInt(_T_512)
node _T_514 = eq(_T_513, asSInt(UInt<1>(0h0)))
node _T_515 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_516 = cvt(_T_515)
node _T_517 = and(_T_516, asSInt(UInt<27>(0h4000000)))
node _T_518 = asSInt(_T_517)
node _T_519 = eq(_T_518, asSInt(UInt<1>(0h0)))
node _T_520 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_521 = cvt(_T_520)
node _T_522 = and(_T_521, asSInt(UInt<13>(0h1000)))
node _T_523 = asSInt(_T_522)
node _T_524 = eq(_T_523, asSInt(UInt<1>(0h0)))
node _T_525 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_526 = cvt(_T_525)
node _T_527 = and(_T_526, asSInt(UInt<29>(0h10000000)))
node _T_528 = asSInt(_T_527)
node _T_529 = eq(_T_528, asSInt(UInt<1>(0h0)))
node _T_530 = or(_T_479, _T_484)
node _T_531 = or(_T_530, _T_489)
node _T_532 = or(_T_531, _T_494)
node _T_533 = or(_T_532, _T_499)
node _T_534 = or(_T_533, _T_504)
node _T_535 = or(_T_534, _T_509)
node _T_536 = or(_T_535, _T_514)
node _T_537 = or(_T_536, _T_519)
node _T_538 = or(_T_537, _T_524)
node _T_539 = or(_T_538, _T_529)
node _T_540 = and(_T_474, _T_539)
node _T_541 = or(UInt<1>(0h0), _T_470)
node _T_542 = or(_T_541, _T_540)
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_542, UInt<1>(0h1), "") : assert_20
node _T_546 = asUInt(reset)
node _T_547 = eq(_T_546, UInt<1>(0h0))
when _T_547 :
node _T_548 = eq(source_ok, UInt<1>(0h0))
when _T_548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(is_aligned, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_552 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_552, UInt<1>(0h1), "") : assert_23
node _T_556 = eq(io.in.a.bits.mask, mask)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_556, UInt<1>(0h1), "") : assert_24
node _T_560 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_560, UInt<1>(0h1), "") : assert_25
node _T_564 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_564 :
node _T_565 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_566 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_567 = and(_T_565, _T_566)
node _T_568 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_569 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_570 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_571 = or(_T_568, _T_569)
node _T_572 = or(_T_571, _T_570)
node _T_573 = and(_T_567, _T_572)
node _T_574 = or(UInt<1>(0h0), _T_573)
node _T_575 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_576 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_577 = and(_T_575, _T_576)
node _T_578 = or(UInt<1>(0h0), _T_577)
node _T_579 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = and(_T_578, _T_583)
node _T_585 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_586 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_587 = and(_T_585, _T_586)
node _T_588 = or(UInt<1>(0h0), _T_587)
node _T_589 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_590 = cvt(_T_589)
node _T_591 = and(_T_590, asSInt(UInt<14>(0h2000)))
node _T_592 = asSInt(_T_591)
node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0)))
node _T_594 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_595 = cvt(_T_594)
node _T_596 = and(_T_595, asSInt(UInt<11>(0h400)))
node _T_597 = asSInt(_T_596)
node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0)))
node _T_599 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_600 = cvt(_T_599)
node _T_601 = and(_T_600, asSInt(UInt<9>(0h100)))
node _T_602 = asSInt(_T_601)
node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0)))
node _T_604 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_605 = cvt(_T_604)
node _T_606 = and(_T_605, asSInt(UInt<18>(0h2f000)))
node _T_607 = asSInt(_T_606)
node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0)))
node _T_609 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_610 = cvt(_T_609)
node _T_611 = and(_T_610, asSInt(UInt<17>(0h10000)))
node _T_612 = asSInt(_T_611)
node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0)))
node _T_614 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_615 = cvt(_T_614)
node _T_616 = and(_T_615, asSInt(UInt<13>(0h1000)))
node _T_617 = asSInt(_T_616)
node _T_618 = eq(_T_617, asSInt(UInt<1>(0h0)))
node _T_619 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_620 = cvt(_T_619)
node _T_621 = and(_T_620, asSInt(UInt<17>(0h10000)))
node _T_622 = asSInt(_T_621)
node _T_623 = eq(_T_622, asSInt(UInt<1>(0h0)))
node _T_624 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_625 = cvt(_T_624)
node _T_626 = and(_T_625, asSInt(UInt<27>(0h4000000)))
node _T_627 = asSInt(_T_626)
node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0)))
node _T_629 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_630 = cvt(_T_629)
node _T_631 = and(_T_630, asSInt(UInt<13>(0h1000)))
node _T_632 = asSInt(_T_631)
node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0)))
node _T_634 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_635 = cvt(_T_634)
node _T_636 = and(_T_635, asSInt(UInt<29>(0h10000000)))
node _T_637 = asSInt(_T_636)
node _T_638 = eq(_T_637, asSInt(UInt<1>(0h0)))
node _T_639 = or(_T_593, _T_598)
node _T_640 = or(_T_639, _T_603)
node _T_641 = or(_T_640, _T_608)
node _T_642 = or(_T_641, _T_613)
node _T_643 = or(_T_642, _T_618)
node _T_644 = or(_T_643, _T_623)
node _T_645 = or(_T_644, _T_628)
node _T_646 = or(_T_645, _T_633)
node _T_647 = or(_T_646, _T_638)
node _T_648 = and(_T_588, _T_647)
node _T_649 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_650 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_651 = cvt(_T_650)
node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000)))
node _T_653 = asSInt(_T_652)
node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0)))
node _T_655 = and(_T_649, _T_654)
node _T_656 = or(UInt<1>(0h0), _T_584)
node _T_657 = or(_T_656, _T_648)
node _T_658 = or(_T_657, _T_655)
node _T_659 = and(_T_574, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_659, UInt<1>(0h1), "") : assert_26
node _T_663 = asUInt(reset)
node _T_664 = eq(_T_663, UInt<1>(0h0))
when _T_664 :
node _T_665 = eq(source_ok, UInt<1>(0h0))
when _T_665 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(is_aligned, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_669 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_669, UInt<1>(0h1), "") : assert_29
node _T_673 = eq(io.in.a.bits.mask, mask)
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_673, UInt<1>(0h1), "") : assert_30
node _T_677 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_677 :
node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_679 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_680 = and(_T_678, _T_679)
node _T_681 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_682 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_683 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_684 = or(_T_681, _T_682)
node _T_685 = or(_T_684, _T_683)
node _T_686 = and(_T_680, _T_685)
node _T_687 = or(UInt<1>(0h0), _T_686)
node _T_688 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_689 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_690 = and(_T_688, _T_689)
node _T_691 = or(UInt<1>(0h0), _T_690)
node _T_692 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_693 = cvt(_T_692)
node _T_694 = and(_T_693, asSInt(UInt<13>(0h1000)))
node _T_695 = asSInt(_T_694)
node _T_696 = eq(_T_695, asSInt(UInt<1>(0h0)))
node _T_697 = and(_T_691, _T_696)
node _T_698 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_699 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_700 = and(_T_698, _T_699)
node _T_701 = or(UInt<1>(0h0), _T_700)
node _T_702 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_703 = cvt(_T_702)
node _T_704 = and(_T_703, asSInt(UInt<14>(0h2000)))
node _T_705 = asSInt(_T_704)
node _T_706 = eq(_T_705, asSInt(UInt<1>(0h0)))
node _T_707 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_708 = cvt(_T_707)
node _T_709 = and(_T_708, asSInt(UInt<11>(0h400)))
node _T_710 = asSInt(_T_709)
node _T_711 = eq(_T_710, asSInt(UInt<1>(0h0)))
node _T_712 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_713 = cvt(_T_712)
node _T_714 = and(_T_713, asSInt(UInt<9>(0h100)))
node _T_715 = asSInt(_T_714)
node _T_716 = eq(_T_715, asSInt(UInt<1>(0h0)))
node _T_717 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_718 = cvt(_T_717)
node _T_719 = and(_T_718, asSInt(UInt<18>(0h2f000)))
node _T_720 = asSInt(_T_719)
node _T_721 = eq(_T_720, asSInt(UInt<1>(0h0)))
node _T_722 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_723 = cvt(_T_722)
node _T_724 = and(_T_723, asSInt(UInt<17>(0h10000)))
node _T_725 = asSInt(_T_724)
node _T_726 = eq(_T_725, asSInt(UInt<1>(0h0)))
node _T_727 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_728 = cvt(_T_727)
node _T_729 = and(_T_728, asSInt(UInt<13>(0h1000)))
node _T_730 = asSInt(_T_729)
node _T_731 = eq(_T_730, asSInt(UInt<1>(0h0)))
node _T_732 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_733 = cvt(_T_732)
node _T_734 = and(_T_733, asSInt(UInt<17>(0h10000)))
node _T_735 = asSInt(_T_734)
node _T_736 = eq(_T_735, asSInt(UInt<1>(0h0)))
node _T_737 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_738 = cvt(_T_737)
node _T_739 = and(_T_738, asSInt(UInt<27>(0h4000000)))
node _T_740 = asSInt(_T_739)
node _T_741 = eq(_T_740, asSInt(UInt<1>(0h0)))
node _T_742 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_743 = cvt(_T_742)
node _T_744 = and(_T_743, asSInt(UInt<13>(0h1000)))
node _T_745 = asSInt(_T_744)
node _T_746 = eq(_T_745, asSInt(UInt<1>(0h0)))
node _T_747 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_748 = cvt(_T_747)
node _T_749 = and(_T_748, asSInt(UInt<29>(0h10000000)))
node _T_750 = asSInt(_T_749)
node _T_751 = eq(_T_750, asSInt(UInt<1>(0h0)))
node _T_752 = or(_T_706, _T_711)
node _T_753 = or(_T_752, _T_716)
node _T_754 = or(_T_753, _T_721)
node _T_755 = or(_T_754, _T_726)
node _T_756 = or(_T_755, _T_731)
node _T_757 = or(_T_756, _T_736)
node _T_758 = or(_T_757, _T_741)
node _T_759 = or(_T_758, _T_746)
node _T_760 = or(_T_759, _T_751)
node _T_761 = and(_T_701, _T_760)
node _T_762 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_763 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_764 = cvt(_T_763)
node _T_765 = and(_T_764, asSInt(UInt<17>(0h10000)))
node _T_766 = asSInt(_T_765)
node _T_767 = eq(_T_766, asSInt(UInt<1>(0h0)))
node _T_768 = and(_T_762, _T_767)
node _T_769 = or(UInt<1>(0h0), _T_697)
node _T_770 = or(_T_769, _T_761)
node _T_771 = or(_T_770, _T_768)
node _T_772 = and(_T_687, _T_771)
node _T_773 = asUInt(reset)
node _T_774 = eq(_T_773, UInt<1>(0h0))
when _T_774 :
node _T_775 = eq(_T_772, UInt<1>(0h0))
when _T_775 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_772, UInt<1>(0h1), "") : assert_31
node _T_776 = asUInt(reset)
node _T_777 = eq(_T_776, UInt<1>(0h0))
when _T_777 :
node _T_778 = eq(source_ok, UInt<1>(0h0))
when _T_778 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_779 = asUInt(reset)
node _T_780 = eq(_T_779, UInt<1>(0h0))
when _T_780 :
node _T_781 = eq(is_aligned, UInt<1>(0h0))
when _T_781 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_782 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_783 = asUInt(reset)
node _T_784 = eq(_T_783, UInt<1>(0h0))
when _T_784 :
node _T_785 = eq(_T_782, UInt<1>(0h0))
when _T_785 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_782, UInt<1>(0h1), "") : assert_34
node _T_786 = not(mask)
node _T_787 = and(io.in.a.bits.mask, _T_786)
node _T_788 = eq(_T_787, UInt<1>(0h0))
node _T_789 = asUInt(reset)
node _T_790 = eq(_T_789, UInt<1>(0h0))
when _T_790 :
node _T_791 = eq(_T_788, UInt<1>(0h0))
when _T_791 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_788, UInt<1>(0h1), "") : assert_35
node _T_792 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_792 :
node _T_793 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_794 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_795 = and(_T_793, _T_794)
node _T_796 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_797 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_798 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_799 = or(_T_796, _T_797)
node _T_800 = or(_T_799, _T_798)
node _T_801 = and(_T_795, _T_800)
node _T_802 = or(UInt<1>(0h0), _T_801)
node _T_803 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_804 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_805 = and(_T_803, _T_804)
node _T_806 = or(UInt<1>(0h0), _T_805)
node _T_807 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_808 = cvt(_T_807)
node _T_809 = and(_T_808, asSInt(UInt<14>(0h2000)))
node _T_810 = asSInt(_T_809)
node _T_811 = eq(_T_810, asSInt(UInt<1>(0h0)))
node _T_812 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_813 = cvt(_T_812)
node _T_814 = and(_T_813, asSInt(UInt<11>(0h400)))
node _T_815 = asSInt(_T_814)
node _T_816 = eq(_T_815, asSInt(UInt<1>(0h0)))
node _T_817 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_818 = cvt(_T_817)
node _T_819 = and(_T_818, asSInt(UInt<9>(0h100)))
node _T_820 = asSInt(_T_819)
node _T_821 = eq(_T_820, asSInt(UInt<1>(0h0)))
node _T_822 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_823 = cvt(_T_822)
node _T_824 = and(_T_823, asSInt(UInt<13>(0h1000)))
node _T_825 = asSInt(_T_824)
node _T_826 = eq(_T_825, asSInt(UInt<1>(0h0)))
node _T_827 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_828 = cvt(_T_827)
node _T_829 = and(_T_828, asSInt(UInt<18>(0h2f000)))
node _T_830 = asSInt(_T_829)
node _T_831 = eq(_T_830, asSInt(UInt<1>(0h0)))
node _T_832 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_833 = cvt(_T_832)
node _T_834 = and(_T_833, asSInt(UInt<17>(0h10000)))
node _T_835 = asSInt(_T_834)
node _T_836 = eq(_T_835, asSInt(UInt<1>(0h0)))
node _T_837 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_838 = cvt(_T_837)
node _T_839 = and(_T_838, asSInt(UInt<13>(0h1000)))
node _T_840 = asSInt(_T_839)
node _T_841 = eq(_T_840, asSInt(UInt<1>(0h0)))
node _T_842 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_843 = cvt(_T_842)
node _T_844 = and(_T_843, asSInt(UInt<17>(0h10000)))
node _T_845 = asSInt(_T_844)
node _T_846 = eq(_T_845, asSInt(UInt<1>(0h0)))
node _T_847 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_848 = cvt(_T_847)
node _T_849 = and(_T_848, asSInt(UInt<27>(0h4000000)))
node _T_850 = asSInt(_T_849)
node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0)))
node _T_852 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_853 = cvt(_T_852)
node _T_854 = and(_T_853, asSInt(UInt<13>(0h1000)))
node _T_855 = asSInt(_T_854)
node _T_856 = eq(_T_855, asSInt(UInt<1>(0h0)))
node _T_857 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_858 = cvt(_T_857)
node _T_859 = and(_T_858, asSInt(UInt<29>(0h10000000)))
node _T_860 = asSInt(_T_859)
node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0)))
node _T_862 = or(_T_811, _T_816)
node _T_863 = or(_T_862, _T_821)
node _T_864 = or(_T_863, _T_826)
node _T_865 = or(_T_864, _T_831)
node _T_866 = or(_T_865, _T_836)
node _T_867 = or(_T_866, _T_841)
node _T_868 = or(_T_867, _T_846)
node _T_869 = or(_T_868, _T_851)
node _T_870 = or(_T_869, _T_856)
node _T_871 = or(_T_870, _T_861)
node _T_872 = and(_T_806, _T_871)
node _T_873 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_874 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_875 = cvt(_T_874)
node _T_876 = and(_T_875, asSInt(UInt<17>(0h10000)))
node _T_877 = asSInt(_T_876)
node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0)))
node _T_879 = and(_T_873, _T_878)
node _T_880 = or(UInt<1>(0h0), _T_872)
node _T_881 = or(_T_880, _T_879)
node _T_882 = and(_T_802, _T_881)
node _T_883 = asUInt(reset)
node _T_884 = eq(_T_883, UInt<1>(0h0))
when _T_884 :
node _T_885 = eq(_T_882, UInt<1>(0h0))
when _T_885 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_882, UInt<1>(0h1), "") : assert_36
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(source_ok, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_889 = asUInt(reset)
node _T_890 = eq(_T_889, UInt<1>(0h0))
when _T_890 :
node _T_891 = eq(is_aligned, UInt<1>(0h0))
when _T_891 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_892 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_893 = asUInt(reset)
node _T_894 = eq(_T_893, UInt<1>(0h0))
when _T_894 :
node _T_895 = eq(_T_892, UInt<1>(0h0))
when _T_895 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_892, UInt<1>(0h1), "") : assert_39
node _T_896 = eq(io.in.a.bits.mask, mask)
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(_T_896, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_896, UInt<1>(0h1), "") : assert_40
node _T_900 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_900 :
node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_903 = and(_T_901, _T_902)
node _T_904 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_905 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_906 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_907 = or(_T_904, _T_905)
node _T_908 = or(_T_907, _T_906)
node _T_909 = and(_T_903, _T_908)
node _T_910 = or(UInt<1>(0h0), _T_909)
node _T_911 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_912 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_913 = and(_T_911, _T_912)
node _T_914 = or(UInt<1>(0h0), _T_913)
node _T_915 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_916 = cvt(_T_915)
node _T_917 = and(_T_916, asSInt(UInt<14>(0h2000)))
node _T_918 = asSInt(_T_917)
node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0)))
node _T_920 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_921 = cvt(_T_920)
node _T_922 = and(_T_921, asSInt(UInt<11>(0h400)))
node _T_923 = asSInt(_T_922)
node _T_924 = eq(_T_923, asSInt(UInt<1>(0h0)))
node _T_925 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_926 = cvt(_T_925)
node _T_927 = and(_T_926, asSInt(UInt<9>(0h100)))
node _T_928 = asSInt(_T_927)
node _T_929 = eq(_T_928, asSInt(UInt<1>(0h0)))
node _T_930 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_931 = cvt(_T_930)
node _T_932 = and(_T_931, asSInt(UInt<13>(0h1000)))
node _T_933 = asSInt(_T_932)
node _T_934 = eq(_T_933, asSInt(UInt<1>(0h0)))
node _T_935 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_936 = cvt(_T_935)
node _T_937 = and(_T_936, asSInt(UInt<18>(0h2f000)))
node _T_938 = asSInt(_T_937)
node _T_939 = eq(_T_938, asSInt(UInt<1>(0h0)))
node _T_940 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_941 = cvt(_T_940)
node _T_942 = and(_T_941, asSInt(UInt<17>(0h10000)))
node _T_943 = asSInt(_T_942)
node _T_944 = eq(_T_943, asSInt(UInt<1>(0h0)))
node _T_945 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_946 = cvt(_T_945)
node _T_947 = and(_T_946, asSInt(UInt<13>(0h1000)))
node _T_948 = asSInt(_T_947)
node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0)))
node _T_950 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_951 = cvt(_T_950)
node _T_952 = and(_T_951, asSInt(UInt<17>(0h10000)))
node _T_953 = asSInt(_T_952)
node _T_954 = eq(_T_953, asSInt(UInt<1>(0h0)))
node _T_955 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_956 = cvt(_T_955)
node _T_957 = and(_T_956, asSInt(UInt<27>(0h4000000)))
node _T_958 = asSInt(_T_957)
node _T_959 = eq(_T_958, asSInt(UInt<1>(0h0)))
node _T_960 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_961 = cvt(_T_960)
node _T_962 = and(_T_961, asSInt(UInt<13>(0h1000)))
node _T_963 = asSInt(_T_962)
node _T_964 = eq(_T_963, asSInt(UInt<1>(0h0)))
node _T_965 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_966 = cvt(_T_965)
node _T_967 = and(_T_966, asSInt(UInt<29>(0h10000000)))
node _T_968 = asSInt(_T_967)
node _T_969 = eq(_T_968, asSInt(UInt<1>(0h0)))
node _T_970 = or(_T_919, _T_924)
node _T_971 = or(_T_970, _T_929)
node _T_972 = or(_T_971, _T_934)
node _T_973 = or(_T_972, _T_939)
node _T_974 = or(_T_973, _T_944)
node _T_975 = or(_T_974, _T_949)
node _T_976 = or(_T_975, _T_954)
node _T_977 = or(_T_976, _T_959)
node _T_978 = or(_T_977, _T_964)
node _T_979 = or(_T_978, _T_969)
node _T_980 = and(_T_914, _T_979)
node _T_981 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_982 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_983 = cvt(_T_982)
node _T_984 = and(_T_983, asSInt(UInt<17>(0h10000)))
node _T_985 = asSInt(_T_984)
node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0)))
node _T_987 = and(_T_981, _T_986)
node _T_988 = or(UInt<1>(0h0), _T_980)
node _T_989 = or(_T_988, _T_987)
node _T_990 = and(_T_910, _T_989)
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(_T_990, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_990, UInt<1>(0h1), "") : assert_41
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(source_ok, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_997 = asUInt(reset)
node _T_998 = eq(_T_997, UInt<1>(0h0))
when _T_998 :
node _T_999 = eq(is_aligned, UInt<1>(0h0))
when _T_999 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1000 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1001 = asUInt(reset)
node _T_1002 = eq(_T_1001, UInt<1>(0h0))
when _T_1002 :
node _T_1003 = eq(_T_1000, UInt<1>(0h0))
when _T_1003 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1000, UInt<1>(0h1), "") : assert_44
node _T_1004 = eq(io.in.a.bits.mask, mask)
node _T_1005 = asUInt(reset)
node _T_1006 = eq(_T_1005, UInt<1>(0h0))
when _T_1006 :
node _T_1007 = eq(_T_1004, UInt<1>(0h0))
when _T_1007 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1004, UInt<1>(0h1), "") : assert_45
node _T_1008 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1008 :
node _T_1009 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1010 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1011 = and(_T_1009, _T_1010)
node _T_1012 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_1013 = eq(io.in.a.bits.source, UInt<1>(0h1))
node _T_1014 = eq(io.in.a.bits.source, UInt<2>(0h2))
node _T_1015 = or(_T_1012, _T_1013)
node _T_1016 = or(_T_1015, _T_1014)
node _T_1017 = and(_T_1011, _T_1016)
node _T_1018 = or(UInt<1>(0h0), _T_1017)
node _T_1019 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1020 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1021 = and(_T_1019, _T_1020)
node _T_1022 = or(UInt<1>(0h0), _T_1021)
node _T_1023 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1024 = cvt(_T_1023)
node _T_1025 = and(_T_1024, asSInt(UInt<13>(0h1000)))
node _T_1026 = asSInt(_T_1025)
node _T_1027 = eq(_T_1026, asSInt(UInt<1>(0h0)))
node _T_1028 = and(_T_1022, _T_1027)
node _T_1029 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1030 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1031 = cvt(_T_1030)
node _T_1032 = and(_T_1031, asSInt(UInt<14>(0h2000)))
node _T_1033 = asSInt(_T_1032)
node _T_1034 = eq(_T_1033, asSInt(UInt<1>(0h0)))
node _T_1035 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_1036 = cvt(_T_1035)
node _T_1037 = and(_T_1036, asSInt(UInt<11>(0h400)))
node _T_1038 = asSInt(_T_1037)
node _T_1039 = eq(_T_1038, asSInt(UInt<1>(0h0)))
node _T_1040 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_1041 = cvt(_T_1040)
node _T_1042 = and(_T_1041, asSInt(UInt<9>(0h100)))
node _T_1043 = asSInt(_T_1042)
node _T_1044 = eq(_T_1043, asSInt(UInt<1>(0h0)))
node _T_1045 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1046 = cvt(_T_1045)
node _T_1047 = and(_T_1046, asSInt(UInt<17>(0h10000)))
node _T_1048 = asSInt(_T_1047)
node _T_1049 = eq(_T_1048, asSInt(UInt<1>(0h0)))
node _T_1050 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1051 = cvt(_T_1050)
node _T_1052 = and(_T_1051, asSInt(UInt<18>(0h2f000)))
node _T_1053 = asSInt(_T_1052)
node _T_1054 = eq(_T_1053, asSInt(UInt<1>(0h0)))
node _T_1055 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1056 = cvt(_T_1055)
node _T_1057 = and(_T_1056, asSInt(UInt<17>(0h10000)))
node _T_1058 = asSInt(_T_1057)
node _T_1059 = eq(_T_1058, asSInt(UInt<1>(0h0)))
node _T_1060 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1061 = cvt(_T_1060)
node _T_1062 = and(_T_1061, asSInt(UInt<13>(0h1000)))
node _T_1063 = asSInt(_T_1062)
node _T_1064 = eq(_T_1063, asSInt(UInt<1>(0h0)))
node _T_1065 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1066 = cvt(_T_1065)
node _T_1067 = and(_T_1066, asSInt(UInt<27>(0h4000000)))
node _T_1068 = asSInt(_T_1067)
node _T_1069 = eq(_T_1068, asSInt(UInt<1>(0h0)))
node _T_1070 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1071 = cvt(_T_1070)
node _T_1072 = and(_T_1071, asSInt(UInt<13>(0h1000)))
node _T_1073 = asSInt(_T_1072)
node _T_1074 = eq(_T_1073, asSInt(UInt<1>(0h0)))
node _T_1075 = or(_T_1034, _T_1039)
node _T_1076 = or(_T_1075, _T_1044)
node _T_1077 = or(_T_1076, _T_1049)
node _T_1078 = or(_T_1077, _T_1054)
node _T_1079 = or(_T_1078, _T_1059)
node _T_1080 = or(_T_1079, _T_1064)
node _T_1081 = or(_T_1080, _T_1069)
node _T_1082 = or(_T_1081, _T_1074)
node _T_1083 = and(_T_1029, _T_1082)
node _T_1084 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1085 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1086 = and(_T_1084, _T_1085)
node _T_1087 = or(UInt<1>(0h0), _T_1086)
node _T_1088 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1089 = cvt(_T_1088)
node _T_1090 = and(_T_1089, asSInt(UInt<17>(0h10000)))
node _T_1091 = asSInt(_T_1090)
node _T_1092 = eq(_T_1091, asSInt(UInt<1>(0h0)))
node _T_1093 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1094 = cvt(_T_1093)
node _T_1095 = and(_T_1094, asSInt(UInt<29>(0h10000000)))
node _T_1096 = asSInt(_T_1095)
node _T_1097 = eq(_T_1096, asSInt(UInt<1>(0h0)))
node _T_1098 = or(_T_1092, _T_1097)
node _T_1099 = and(_T_1087, _T_1098)
node _T_1100 = or(UInt<1>(0h0), _T_1028)
node _T_1101 = or(_T_1100, _T_1083)
node _T_1102 = or(_T_1101, _T_1099)
node _T_1103 = and(_T_1018, _T_1102)
node _T_1104 = asUInt(reset)
node _T_1105 = eq(_T_1104, UInt<1>(0h0))
when _T_1105 :
node _T_1106 = eq(_T_1103, UInt<1>(0h0))
when _T_1106 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1103, UInt<1>(0h1), "") : assert_46
node _T_1107 = asUInt(reset)
node _T_1108 = eq(_T_1107, UInt<1>(0h0))
when _T_1108 :
node _T_1109 = eq(source_ok, UInt<1>(0h0))
when _T_1109 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1110 = asUInt(reset)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
when _T_1111 :
node _T_1112 = eq(is_aligned, UInt<1>(0h0))
when _T_1112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1113 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1114 = asUInt(reset)
node _T_1115 = eq(_T_1114, UInt<1>(0h0))
when _T_1115 :
node _T_1116 = eq(_T_1113, UInt<1>(0h0))
when _T_1116 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1113, UInt<1>(0h1), "") : assert_49
node _T_1117 = eq(io.in.a.bits.mask, mask)
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(_T_1117, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1117, UInt<1>(0h1), "") : assert_50
node _T_1121 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(_T_1121, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1121, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1125 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_52
node _source_ok_T_4 = eq(io.in.d.bits.source, UInt<1>(0h0))
node _source_ok_T_5 = eq(io.in.d.bits.source, UInt<1>(0h1))
node _source_ok_T_6 = eq(io.in.d.bits.source, UInt<2>(0h2))
wire _source_ok_WIRE_1 : UInt<1>[3]
connect _source_ok_WIRE_1[0], _source_ok_T_4
connect _source_ok_WIRE_1[1], _source_ok_T_5
connect _source_ok_WIRE_1[2], _source_ok_T_6
node _source_ok_T_7 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node source_ok_1 = or(_source_ok_T_7, _source_ok_WIRE_1[2])
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_1129 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1129 :
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(source_ok_1, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1133 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1134 = asUInt(reset)
node _T_1135 = eq(_T_1134, UInt<1>(0h0))
when _T_1135 :
node _T_1136 = eq(_T_1133, UInt<1>(0h0))
when _T_1136 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1133, UInt<1>(0h1), "") : assert_54
node _T_1137 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1138 = asUInt(reset)
node _T_1139 = eq(_T_1138, UInt<1>(0h0))
when _T_1139 :
node _T_1140 = eq(_T_1137, UInt<1>(0h0))
when _T_1140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1137, UInt<1>(0h1), "") : assert_55
node _T_1141 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1142 = asUInt(reset)
node _T_1143 = eq(_T_1142, UInt<1>(0h0))
when _T_1143 :
node _T_1144 = eq(_T_1141, UInt<1>(0h0))
when _T_1144 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1141, UInt<1>(0h1), "") : assert_56
node _T_1145 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_57
node _T_1149 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1149 :
node _T_1150 = asUInt(reset)
node _T_1151 = eq(_T_1150, UInt<1>(0h0))
when _T_1151 :
node _T_1152 = eq(source_ok_1, UInt<1>(0h0))
when _T_1152 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1153 = asUInt(reset)
node _T_1154 = eq(_T_1153, UInt<1>(0h0))
when _T_1154 :
node _T_1155 = eq(sink_ok, UInt<1>(0h0))
when _T_1155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1156 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1157 = asUInt(reset)
node _T_1158 = eq(_T_1157, UInt<1>(0h0))
when _T_1158 :
node _T_1159 = eq(_T_1156, UInt<1>(0h0))
when _T_1159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1156, UInt<1>(0h1), "") : assert_60
node _T_1160 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(_T_1160, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1160, UInt<1>(0h1), "") : assert_61
node _T_1164 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1165 = asUInt(reset)
node _T_1166 = eq(_T_1165, UInt<1>(0h0))
when _T_1166 :
node _T_1167 = eq(_T_1164, UInt<1>(0h0))
when _T_1167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1164, UInt<1>(0h1), "") : assert_62
node _T_1168 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1169 = asUInt(reset)
node _T_1170 = eq(_T_1169, UInt<1>(0h0))
when _T_1170 :
node _T_1171 = eq(_T_1168, UInt<1>(0h0))
when _T_1171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1168, UInt<1>(0h1), "") : assert_63
node _T_1172 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1173 = or(UInt<1>(0h1), _T_1172)
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(_T_1173, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1173, UInt<1>(0h1), "") : assert_64
node _T_1177 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1177 :
node _T_1178 = asUInt(reset)
node _T_1179 = eq(_T_1178, UInt<1>(0h0))
when _T_1179 :
node _T_1180 = eq(source_ok_1, UInt<1>(0h0))
when _T_1180 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1181 = asUInt(reset)
node _T_1182 = eq(_T_1181, UInt<1>(0h0))
when _T_1182 :
node _T_1183 = eq(sink_ok, UInt<1>(0h0))
when _T_1183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1184 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_67
node _T_1188 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1189 = asUInt(reset)
node _T_1190 = eq(_T_1189, UInt<1>(0h0))
when _T_1190 :
node _T_1191 = eq(_T_1188, UInt<1>(0h0))
when _T_1191 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1188, UInt<1>(0h1), "") : assert_68
node _T_1192 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1193 = asUInt(reset)
node _T_1194 = eq(_T_1193, UInt<1>(0h0))
when _T_1194 :
node _T_1195 = eq(_T_1192, UInt<1>(0h0))
when _T_1195 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1192, UInt<1>(0h1), "") : assert_69
node _T_1196 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1197 = or(_T_1196, io.in.d.bits.corrupt)
node _T_1198 = asUInt(reset)
node _T_1199 = eq(_T_1198, UInt<1>(0h0))
when _T_1199 :
node _T_1200 = eq(_T_1197, UInt<1>(0h0))
when _T_1200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1197, UInt<1>(0h1), "") : assert_70
node _T_1201 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1202 = or(UInt<1>(0h1), _T_1201)
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_71
node _T_1206 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1206 :
node _T_1207 = asUInt(reset)
node _T_1208 = eq(_T_1207, UInt<1>(0h0))
when _T_1208 :
node _T_1209 = eq(source_ok_1, UInt<1>(0h0))
when _T_1209 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1210 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1211 = asUInt(reset)
node _T_1212 = eq(_T_1211, UInt<1>(0h0))
when _T_1212 :
node _T_1213 = eq(_T_1210, UInt<1>(0h0))
when _T_1213 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1210, UInt<1>(0h1), "") : assert_73
node _T_1214 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1215 = asUInt(reset)
node _T_1216 = eq(_T_1215, UInt<1>(0h0))
when _T_1216 :
node _T_1217 = eq(_T_1214, UInt<1>(0h0))
when _T_1217 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1214, UInt<1>(0h1), "") : assert_74
node _T_1218 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1219 = or(UInt<1>(0h1), _T_1218)
node _T_1220 = asUInt(reset)
node _T_1221 = eq(_T_1220, UInt<1>(0h0))
when _T_1221 :
node _T_1222 = eq(_T_1219, UInt<1>(0h0))
when _T_1222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1219, UInt<1>(0h1), "") : assert_75
node _T_1223 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1223 :
node _T_1224 = asUInt(reset)
node _T_1225 = eq(_T_1224, UInt<1>(0h0))
when _T_1225 :
node _T_1226 = eq(source_ok_1, UInt<1>(0h0))
when _T_1226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1227 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1228 = asUInt(reset)
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(_T_1227, UInt<1>(0h0))
when _T_1230 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1227, UInt<1>(0h1), "") : assert_77
node _T_1231 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1232 = or(_T_1231, io.in.d.bits.corrupt)
node _T_1233 = asUInt(reset)
node _T_1234 = eq(_T_1233, UInt<1>(0h0))
when _T_1234 :
node _T_1235 = eq(_T_1232, UInt<1>(0h0))
when _T_1235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1232, UInt<1>(0h1), "") : assert_78
node _T_1236 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1237 = or(UInt<1>(0h1), _T_1236)
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_79
node _T_1241 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1241 :
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(source_ok_1, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1245 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1246 = asUInt(reset)
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
when _T_1247 :
node _T_1248 = eq(_T_1245, UInt<1>(0h0))
when _T_1248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1245, UInt<1>(0h1), "") : assert_81
node _T_1249 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1250 = asUInt(reset)
node _T_1251 = eq(_T_1250, UInt<1>(0h0))
when _T_1251 :
node _T_1252 = eq(_T_1249, UInt<1>(0h0))
when _T_1252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1249, UInt<1>(0h1), "") : assert_82
node _T_1253 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1254 = or(UInt<1>(0h1), _T_1253)
node _T_1255 = asUInt(reset)
node _T_1256 = eq(_T_1255, UInt<1>(0h0))
when _T_1256 :
node _T_1257 = eq(_T_1254, UInt<1>(0h0))
when _T_1257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1254, UInt<1>(0h1), "") : assert_83
when io.in.b.valid :
node _T_1258 = leq(io.in.b.bits.opcode, UInt<3>(0h6))
node _T_1259 = asUInt(reset)
node _T_1260 = eq(_T_1259, UInt<1>(0h0))
when _T_1260 :
node _T_1261 = eq(_T_1258, UInt<1>(0h0))
when _T_1261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1258, UInt<1>(0h1), "") : assert_84
node _T_1262 = eq(io.in.b.bits.source, UInt<1>(0h0))
node _T_1263 = eq(_T_1262, UInt<1>(0h0))
node _T_1264 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1265 = cvt(_T_1264)
node _T_1266 = and(_T_1265, asSInt(UInt<1>(0h0)))
node _T_1267 = asSInt(_T_1266)
node _T_1268 = eq(_T_1267, asSInt(UInt<1>(0h0)))
node _T_1269 = or(_T_1263, _T_1268)
node _T_1270 = eq(io.in.b.bits.source, UInt<1>(0h1))
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
node _T_1272 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1273 = cvt(_T_1272)
node _T_1274 = and(_T_1273, asSInt(UInt<1>(0h0)))
node _T_1275 = asSInt(_T_1274)
node _T_1276 = eq(_T_1275, asSInt(UInt<1>(0h0)))
node _T_1277 = or(_T_1271, _T_1276)
node _T_1278 = eq(io.in.b.bits.source, UInt<2>(0h2))
node _T_1279 = eq(_T_1278, UInt<1>(0h0))
node _T_1280 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1281 = cvt(_T_1280)
node _T_1282 = and(_T_1281, asSInt(UInt<1>(0h0)))
node _T_1283 = asSInt(_T_1282)
node _T_1284 = eq(_T_1283, asSInt(UInt<1>(0h0)))
node _T_1285 = or(_T_1279, _T_1284)
node _T_1286 = and(_T_1269, _T_1277)
node _T_1287 = and(_T_1286, _T_1285)
node _T_1288 = asUInt(reset)
node _T_1289 = eq(_T_1288, UInt<1>(0h0))
when _T_1289 :
node _T_1290 = eq(_T_1287, UInt<1>(0h0))
when _T_1290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1287, UInt<1>(0h1), "") : assert_85
node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0))
node _address_ok_T_1 = cvt(_address_ok_T)
node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000)))
node _address_ok_T_3 = asSInt(_address_ok_T_2)
node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0)))
node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000))
node _address_ok_T_6 = cvt(_address_ok_T_5)
node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000)))
node _address_ok_T_8 = asSInt(_address_ok_T_7)
node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0)))
node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h2000))
node _address_ok_T_11 = cvt(_address_ok_T_10)
node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<9>(0h100)))
node _address_ok_T_13 = asSInt(_address_ok_T_12)
node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0)))
node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<14>(0h2100))
node _address_ok_T_16 = cvt(_address_ok_T_15)
node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<9>(0h100)))
node _address_ok_T_18 = asSInt(_address_ok_T_17)
node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0)))
node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<14>(0h2200))
node _address_ok_T_21 = cvt(_address_ok_T_20)
node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<9>(0h100)))
node _address_ok_T_23 = asSInt(_address_ok_T_22)
node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0)))
node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<14>(0h2300))
node _address_ok_T_26 = cvt(_address_ok_T_25)
node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<9>(0h100)))
node _address_ok_T_28 = asSInt(_address_ok_T_27)
node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0)))
node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<14>(0h2400))
node _address_ok_T_31 = cvt(_address_ok_T_30)
node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<9>(0h100)))
node _address_ok_T_33 = asSInt(_address_ok_T_32)
node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0)))
node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _address_ok_T_36 = cvt(_address_ok_T_35)
node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000)))
node _address_ok_T_38 = asSInt(_address_ok_T_37)
node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0)))
node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _address_ok_T_41 = cvt(_address_ok_T_40)
node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000)))
node _address_ok_T_43 = asSInt(_address_ok_T_42)
node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0)))
node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _address_ok_T_46 = cvt(_address_ok_T_45)
node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<13>(0h1000)))
node _address_ok_T_48 = asSInt(_address_ok_T_47)
node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0)))
node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<21>(0h110000))
node _address_ok_T_51 = cvt(_address_ok_T_50)
node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000)))
node _address_ok_T_53 = asSInt(_address_ok_T_52)
node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0)))
node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _address_ok_T_56 = cvt(_address_ok_T_55)
node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<17>(0h10000)))
node _address_ok_T_58 = asSInt(_address_ok_T_57)
node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0)))
node _address_ok_T_60 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _address_ok_T_61 = cvt(_address_ok_T_60)
node _address_ok_T_62 = and(_address_ok_T_61, asSInt(UInt<13>(0h1000)))
node _address_ok_T_63 = asSInt(_address_ok_T_62)
node _address_ok_T_64 = eq(_address_ok_T_63, asSInt(UInt<1>(0h0)))
node _address_ok_T_65 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _address_ok_T_66 = cvt(_address_ok_T_65)
node _address_ok_T_67 = and(_address_ok_T_66, asSInt(UInt<17>(0h10000)))
node _address_ok_T_68 = asSInt(_address_ok_T_67)
node _address_ok_T_69 = eq(_address_ok_T_68, asSInt(UInt<1>(0h0)))
node _address_ok_T_70 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _address_ok_T_71 = cvt(_address_ok_T_70)
node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_73 = asSInt(_address_ok_T_72)
node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0)))
node _address_ok_T_75 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _address_ok_T_76 = cvt(_address_ok_T_75)
node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000)))
node _address_ok_T_78 = asSInt(_address_ok_T_77)
node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0)))
node _address_ok_T_80 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _address_ok_T_81 = cvt(_address_ok_T_80)
node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_83 = asSInt(_address_ok_T_82)
node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE : UInt<1>[17]
connect _address_ok_WIRE[0], _address_ok_T_4
connect _address_ok_WIRE[1], _address_ok_T_9
connect _address_ok_WIRE[2], _address_ok_T_14
connect _address_ok_WIRE[3], _address_ok_T_19
connect _address_ok_WIRE[4], _address_ok_T_24
connect _address_ok_WIRE[5], _address_ok_T_29
connect _address_ok_WIRE[6], _address_ok_T_34
connect _address_ok_WIRE[7], _address_ok_T_39
connect _address_ok_WIRE[8], _address_ok_T_44
connect _address_ok_WIRE[9], _address_ok_T_49
connect _address_ok_WIRE[10], _address_ok_T_54
connect _address_ok_WIRE[11], _address_ok_T_59
connect _address_ok_WIRE[12], _address_ok_T_64
connect _address_ok_WIRE[13], _address_ok_T_69
connect _address_ok_WIRE[14], _address_ok_T_74
connect _address_ok_WIRE[15], _address_ok_T_79
connect _address_ok_WIRE[16], _address_ok_T_84
node _address_ok_T_85 = or(_address_ok_WIRE[0], _address_ok_WIRE[1])
node _address_ok_T_86 = or(_address_ok_T_85, _address_ok_WIRE[2])
node _address_ok_T_87 = or(_address_ok_T_86, _address_ok_WIRE[3])
node _address_ok_T_88 = or(_address_ok_T_87, _address_ok_WIRE[4])
node _address_ok_T_89 = or(_address_ok_T_88, _address_ok_WIRE[5])
node _address_ok_T_90 = or(_address_ok_T_89, _address_ok_WIRE[6])
node _address_ok_T_91 = or(_address_ok_T_90, _address_ok_WIRE[7])
node _address_ok_T_92 = or(_address_ok_T_91, _address_ok_WIRE[8])
node _address_ok_T_93 = or(_address_ok_T_92, _address_ok_WIRE[9])
node _address_ok_T_94 = or(_address_ok_T_93, _address_ok_WIRE[10])
node _address_ok_T_95 = or(_address_ok_T_94, _address_ok_WIRE[11])
node _address_ok_T_96 = or(_address_ok_T_95, _address_ok_WIRE[12])
node _address_ok_T_97 = or(_address_ok_T_96, _address_ok_WIRE[13])
node _address_ok_T_98 = or(_address_ok_T_97, _address_ok_WIRE[14])
node _address_ok_T_99 = or(_address_ok_T_98, _address_ok_WIRE[15])
node address_ok = or(_address_ok_T_99, _address_ok_WIRE[16])
node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0)
node is_aligned_mask_1 = not(_is_aligned_mask_T_3)
node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1)
node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0))
node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0)
node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1)
node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0)
node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1))
node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3))
node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2)
node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2)
node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0))
node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1)
node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1)
node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2)
node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1)
node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1)
node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3)
node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1)
node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1)
node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0))
node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1)
node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4)
node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1)
node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5)
node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1)
node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1)
node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6)
node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1)
node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1)
node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7)
node mask_size_1 = bits(mask_sizeOH_1, 0, 0)
node mask_bit_1 = bits(io.in.b.bits.address, 0, 0)
node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0))
node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1)
node _mask_acc_T_8 = and(mask_size_1, mask_eq_8)
node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8)
node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1)
node _mask_acc_T_9 = and(mask_size_1, mask_eq_9)
node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9)
node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1)
node _mask_acc_T_10 = and(mask_size_1, mask_eq_10)
node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10)
node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1)
node _mask_acc_T_11 = and(mask_size_1, mask_eq_11)
node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11)
node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1)
node _mask_acc_T_12 = and(mask_size_1, mask_eq_12)
node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12)
node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1)
node _mask_acc_T_13 = and(mask_size_1, mask_eq_13)
node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13)
node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1)
node _mask_acc_T_14 = and(mask_size_1, mask_eq_14)
node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14)
node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1)
node _mask_acc_T_15 = and(mask_size_1, mask_eq_15)
node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15)
node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8)
node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10)
node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1)
node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12)
node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14)
node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1)
node mask_1 = cat(mask_hi_1, mask_lo_1)
node _legal_source_T = eq(io.in.b.bits.source, UInt<1>(0h0))
node _legal_source_T_1 = eq(io.in.b.bits.source, UInt<1>(0h1))
node _legal_source_T_2 = eq(io.in.b.bits.source, UInt<2>(0h2))
wire _legal_source_WIRE : UInt<1>[3]
connect _legal_source_WIRE[0], _legal_source_T
connect _legal_source_WIRE[1], _legal_source_T_1
connect _legal_source_WIRE[2], _legal_source_T_2
node _legal_source_T_3 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _legal_source_T_4 = mux(_legal_source_WIRE[1], UInt<1>(0h1), UInt<1>(0h0))
node _legal_source_T_5 = mux(_legal_source_WIRE[2], UInt<2>(0h2), UInt<1>(0h0))
node _legal_source_T_6 = or(_legal_source_T_3, _legal_source_T_4)
node _legal_source_T_7 = or(_legal_source_T_6, _legal_source_T_5)
wire _legal_source_WIRE_1 : UInt<2>
connect _legal_source_WIRE_1, _legal_source_T_7
node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source)
node _T_1291 = eq(io.in.b.bits.opcode, UInt<3>(0h6))
when _T_1291 :
node _T_1292 = eq(io.in.b.bits.source, UInt<1>(0h0))
node _T_1293 = eq(io.in.b.bits.source, UInt<1>(0h1))
node _T_1294 = eq(io.in.b.bits.source, UInt<2>(0h2))
wire _WIRE_4 : UInt<1>[3]
connect _WIRE_4[0], _T_1292
connect _WIRE_4[1], _T_1293
connect _WIRE_4[2], _T_1294
node _T_1295 = eq(UInt<3>(0h6), io.in.b.bits.size)
node _T_1296 = mux(_WIRE_4[0], _T_1295, UInt<1>(0h0))
node _T_1297 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_1298 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_1299 = or(_T_1296, _T_1297)
node _T_1300 = or(_T_1299, _T_1298)
wire _WIRE_5 : UInt<1>
connect _WIRE_5, _T_1300
node _T_1301 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1302 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1303 = and(_T_1301, _T_1302)
node _T_1304 = or(UInt<1>(0h0), _T_1303)
node _T_1305 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1306 = cvt(_T_1305)
node _T_1307 = and(_T_1306, asSInt(UInt<14>(0h2000)))
node _T_1308 = asSInt(_T_1307)
node _T_1309 = eq(_T_1308, asSInt(UInt<1>(0h0)))
node _T_1310 = xor(io.in.b.bits.address, UInt<14>(0h2000))
node _T_1311 = cvt(_T_1310)
node _T_1312 = and(_T_1311, asSInt(UInt<11>(0h400)))
node _T_1313 = asSInt(_T_1312)
node _T_1314 = eq(_T_1313, asSInt(UInt<1>(0h0)))
node _T_1315 = xor(io.in.b.bits.address, UInt<14>(0h2400))
node _T_1316 = cvt(_T_1315)
node _T_1317 = and(_T_1316, asSInt(UInt<9>(0h100)))
node _T_1318 = asSInt(_T_1317)
node _T_1319 = eq(_T_1318, asSInt(UInt<1>(0h0)))
node _T_1320 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1321 = cvt(_T_1320)
node _T_1322 = and(_T_1321, asSInt(UInt<13>(0h1000)))
node _T_1323 = asSInt(_T_1322)
node _T_1324 = eq(_T_1323, asSInt(UInt<1>(0h0)))
node _T_1325 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1326 = cvt(_T_1325)
node _T_1327 = and(_T_1326, asSInt(UInt<17>(0h10000)))
node _T_1328 = asSInt(_T_1327)
node _T_1329 = eq(_T_1328, asSInt(UInt<1>(0h0)))
node _T_1330 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1331 = cvt(_T_1330)
node _T_1332 = and(_T_1331, asSInt(UInt<18>(0h2f000)))
node _T_1333 = asSInt(_T_1332)
node _T_1334 = eq(_T_1333, asSInt(UInt<1>(0h0)))
node _T_1335 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1336 = cvt(_T_1335)
node _T_1337 = and(_T_1336, asSInt(UInt<17>(0h10000)))
node _T_1338 = asSInt(_T_1337)
node _T_1339 = eq(_T_1338, asSInt(UInt<1>(0h0)))
node _T_1340 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1341 = cvt(_T_1340)
node _T_1342 = and(_T_1341, asSInt(UInt<13>(0h1000)))
node _T_1343 = asSInt(_T_1342)
node _T_1344 = eq(_T_1343, asSInt(UInt<1>(0h0)))
node _T_1345 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1346 = cvt(_T_1345)
node _T_1347 = and(_T_1346, asSInt(UInt<17>(0h10000)))
node _T_1348 = asSInt(_T_1347)
node _T_1349 = eq(_T_1348, asSInt(UInt<1>(0h0)))
node _T_1350 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1351 = cvt(_T_1350)
node _T_1352 = and(_T_1351, asSInt(UInt<27>(0h4000000)))
node _T_1353 = asSInt(_T_1352)
node _T_1354 = eq(_T_1353, asSInt(UInt<1>(0h0)))
node _T_1355 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1356 = cvt(_T_1355)
node _T_1357 = and(_T_1356, asSInt(UInt<13>(0h1000)))
node _T_1358 = asSInt(_T_1357)
node _T_1359 = eq(_T_1358, asSInt(UInt<1>(0h0)))
node _T_1360 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1361 = cvt(_T_1360)
node _T_1362 = and(_T_1361, asSInt(UInt<29>(0h10000000)))
node _T_1363 = asSInt(_T_1362)
node _T_1364 = eq(_T_1363, asSInt(UInt<1>(0h0)))
node _T_1365 = or(_T_1309, _T_1314)
node _T_1366 = or(_T_1365, _T_1319)
node _T_1367 = or(_T_1366, _T_1324)
node _T_1368 = or(_T_1367, _T_1329)
node _T_1369 = or(_T_1368, _T_1334)
node _T_1370 = or(_T_1369, _T_1339)
node _T_1371 = or(_T_1370, _T_1344)
node _T_1372 = or(_T_1371, _T_1349)
node _T_1373 = or(_T_1372, _T_1354)
node _T_1374 = or(_T_1373, _T_1359)
node _T_1375 = or(_T_1374, _T_1364)
node _T_1376 = and(_T_1304, _T_1375)
node _T_1377 = or(UInt<1>(0h0), _T_1376)
node _T_1378 = and(_WIRE_5, _T_1377)
node _T_1379 = asUInt(reset)
node _T_1380 = eq(_T_1379, UInt<1>(0h0))
when _T_1380 :
node _T_1381 = eq(_T_1378, UInt<1>(0h0))
when _T_1381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86
assert(clock, _T_1378, UInt<1>(0h1), "") : assert_86
node _T_1382 = asUInt(reset)
node _T_1383 = eq(_T_1382, UInt<1>(0h0))
when _T_1383 :
node _T_1384 = eq(address_ok, UInt<1>(0h0))
when _T_1384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87
assert(clock, address_ok, UInt<1>(0h1), "") : assert_87
node _T_1385 = asUInt(reset)
node _T_1386 = eq(_T_1385, UInt<1>(0h0))
when _T_1386 :
node _T_1387 = eq(legal_source, UInt<1>(0h0))
when _T_1387 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88
assert(clock, legal_source, UInt<1>(0h1), "") : assert_88
node _T_1388 = asUInt(reset)
node _T_1389 = eq(_T_1388, UInt<1>(0h0))
when _T_1389 :
node _T_1390 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89
node _T_1391 = leq(io.in.b.bits.param, UInt<2>(0h2))
node _T_1392 = asUInt(reset)
node _T_1393 = eq(_T_1392, UInt<1>(0h0))
when _T_1393 :
node _T_1394 = eq(_T_1391, UInt<1>(0h0))
when _T_1394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90
assert(clock, _T_1391, UInt<1>(0h1), "") : assert_90
node _T_1395 = eq(io.in.b.bits.mask, mask_1)
node _T_1396 = asUInt(reset)
node _T_1397 = eq(_T_1396, UInt<1>(0h0))
when _T_1397 :
node _T_1398 = eq(_T_1395, UInt<1>(0h0))
when _T_1398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91
assert(clock, _T_1395, UInt<1>(0h1), "") : assert_91
node _T_1399 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1400 = asUInt(reset)
node _T_1401 = eq(_T_1400, UInt<1>(0h0))
when _T_1401 :
node _T_1402 = eq(_T_1399, UInt<1>(0h0))
when _T_1402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1399, UInt<1>(0h1), "") : assert_92
node _T_1403 = eq(io.in.b.bits.opcode, UInt<3>(0h4))
when _T_1403 :
node _T_1404 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1405 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1406 = and(_T_1404, _T_1405)
node _T_1407 = or(UInt<1>(0h0), _T_1406)
node _T_1408 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1409 = cvt(_T_1408)
node _T_1410 = and(_T_1409, asSInt(UInt<14>(0h2000)))
node _T_1411 = asSInt(_T_1410)
node _T_1412 = eq(_T_1411, asSInt(UInt<1>(0h0)))
node _T_1413 = xor(io.in.b.bits.address, UInt<14>(0h2000))
node _T_1414 = cvt(_T_1413)
node _T_1415 = and(_T_1414, asSInt(UInt<11>(0h400)))
node _T_1416 = asSInt(_T_1415)
node _T_1417 = eq(_T_1416, asSInt(UInt<1>(0h0)))
node _T_1418 = xor(io.in.b.bits.address, UInt<14>(0h2400))
node _T_1419 = cvt(_T_1418)
node _T_1420 = and(_T_1419, asSInt(UInt<9>(0h100)))
node _T_1421 = asSInt(_T_1420)
node _T_1422 = eq(_T_1421, asSInt(UInt<1>(0h0)))
node _T_1423 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1424 = cvt(_T_1423)
node _T_1425 = and(_T_1424, asSInt(UInt<13>(0h1000)))
node _T_1426 = asSInt(_T_1425)
node _T_1427 = eq(_T_1426, asSInt(UInt<1>(0h0)))
node _T_1428 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1429 = cvt(_T_1428)
node _T_1430 = and(_T_1429, asSInt(UInt<17>(0h10000)))
node _T_1431 = asSInt(_T_1430)
node _T_1432 = eq(_T_1431, asSInt(UInt<1>(0h0)))
node _T_1433 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1434 = cvt(_T_1433)
node _T_1435 = and(_T_1434, asSInt(UInt<18>(0h2f000)))
node _T_1436 = asSInt(_T_1435)
node _T_1437 = eq(_T_1436, asSInt(UInt<1>(0h0)))
node _T_1438 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1439 = cvt(_T_1438)
node _T_1440 = and(_T_1439, asSInt(UInt<17>(0h10000)))
node _T_1441 = asSInt(_T_1440)
node _T_1442 = eq(_T_1441, asSInt(UInt<1>(0h0)))
node _T_1443 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1444 = cvt(_T_1443)
node _T_1445 = and(_T_1444, asSInt(UInt<13>(0h1000)))
node _T_1446 = asSInt(_T_1445)
node _T_1447 = eq(_T_1446, asSInt(UInt<1>(0h0)))
node _T_1448 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1449 = cvt(_T_1448)
node _T_1450 = and(_T_1449, asSInt(UInt<17>(0h10000)))
node _T_1451 = asSInt(_T_1450)
node _T_1452 = eq(_T_1451, asSInt(UInt<1>(0h0)))
node _T_1453 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1454 = cvt(_T_1453)
node _T_1455 = and(_T_1454, asSInt(UInt<27>(0h4000000)))
node _T_1456 = asSInt(_T_1455)
node _T_1457 = eq(_T_1456, asSInt(UInt<1>(0h0)))
node _T_1458 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1459 = cvt(_T_1458)
node _T_1460 = and(_T_1459, asSInt(UInt<13>(0h1000)))
node _T_1461 = asSInt(_T_1460)
node _T_1462 = eq(_T_1461, asSInt(UInt<1>(0h0)))
node _T_1463 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1464 = cvt(_T_1463)
node _T_1465 = and(_T_1464, asSInt(UInt<29>(0h10000000)))
node _T_1466 = asSInt(_T_1465)
node _T_1467 = eq(_T_1466, asSInt(UInt<1>(0h0)))
node _T_1468 = or(_T_1412, _T_1417)
node _T_1469 = or(_T_1468, _T_1422)
node _T_1470 = or(_T_1469, _T_1427)
node _T_1471 = or(_T_1470, _T_1432)
node _T_1472 = or(_T_1471, _T_1437)
node _T_1473 = or(_T_1472, _T_1442)
node _T_1474 = or(_T_1473, _T_1447)
node _T_1475 = or(_T_1474, _T_1452)
node _T_1476 = or(_T_1475, _T_1457)
node _T_1477 = or(_T_1476, _T_1462)
node _T_1478 = or(_T_1477, _T_1467)
node _T_1479 = and(_T_1407, _T_1478)
node _T_1480 = or(UInt<1>(0h0), _T_1479)
node _T_1481 = and(UInt<1>(0h0), _T_1480)
node _T_1482 = asUInt(reset)
node _T_1483 = eq(_T_1482, UInt<1>(0h0))
when _T_1483 :
node _T_1484 = eq(_T_1481, UInt<1>(0h0))
when _T_1484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93
assert(clock, _T_1481, UInt<1>(0h1), "") : assert_93
node _T_1485 = asUInt(reset)
node _T_1486 = eq(_T_1485, UInt<1>(0h0))
when _T_1486 :
node _T_1487 = eq(address_ok, UInt<1>(0h0))
when _T_1487 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94
assert(clock, address_ok, UInt<1>(0h1), "") : assert_94
node _T_1488 = asUInt(reset)
node _T_1489 = eq(_T_1488, UInt<1>(0h0))
when _T_1489 :
node _T_1490 = eq(legal_source, UInt<1>(0h0))
when _T_1490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95
assert(clock, legal_source, UInt<1>(0h1), "") : assert_95
node _T_1491 = asUInt(reset)
node _T_1492 = eq(_T_1491, UInt<1>(0h0))
when _T_1492 :
node _T_1493 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96
node _T_1494 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1495 = asUInt(reset)
node _T_1496 = eq(_T_1495, UInt<1>(0h0))
when _T_1496 :
node _T_1497 = eq(_T_1494, UInt<1>(0h0))
when _T_1497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97
assert(clock, _T_1494, UInt<1>(0h1), "") : assert_97
node _T_1498 = eq(io.in.b.bits.mask, mask_1)
node _T_1499 = asUInt(reset)
node _T_1500 = eq(_T_1499, UInt<1>(0h0))
when _T_1500 :
node _T_1501 = eq(_T_1498, UInt<1>(0h0))
when _T_1501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1498, UInt<1>(0h1), "") : assert_98
node _T_1502 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_1503 = asUInt(reset)
node _T_1504 = eq(_T_1503, UInt<1>(0h0))
when _T_1504 :
node _T_1505 = eq(_T_1502, UInt<1>(0h0))
when _T_1505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99
assert(clock, _T_1502, UInt<1>(0h1), "") : assert_99
node _T_1506 = eq(io.in.b.bits.opcode, UInt<1>(0h0))
when _T_1506 :
node _T_1507 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1508 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1509 = and(_T_1507, _T_1508)
node _T_1510 = or(UInt<1>(0h0), _T_1509)
node _T_1511 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1512 = cvt(_T_1511)
node _T_1513 = and(_T_1512, asSInt(UInt<14>(0h2000)))
node _T_1514 = asSInt(_T_1513)
node _T_1515 = eq(_T_1514, asSInt(UInt<1>(0h0)))
node _T_1516 = xor(io.in.b.bits.address, UInt<14>(0h2000))
node _T_1517 = cvt(_T_1516)
node _T_1518 = and(_T_1517, asSInt(UInt<11>(0h400)))
node _T_1519 = asSInt(_T_1518)
node _T_1520 = eq(_T_1519, asSInt(UInt<1>(0h0)))
node _T_1521 = xor(io.in.b.bits.address, UInt<14>(0h2400))
node _T_1522 = cvt(_T_1521)
node _T_1523 = and(_T_1522, asSInt(UInt<9>(0h100)))
node _T_1524 = asSInt(_T_1523)
node _T_1525 = eq(_T_1524, asSInt(UInt<1>(0h0)))
node _T_1526 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1527 = cvt(_T_1526)
node _T_1528 = and(_T_1527, asSInt(UInt<13>(0h1000)))
node _T_1529 = asSInt(_T_1528)
node _T_1530 = eq(_T_1529, asSInt(UInt<1>(0h0)))
node _T_1531 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1532 = cvt(_T_1531)
node _T_1533 = and(_T_1532, asSInt(UInt<17>(0h10000)))
node _T_1534 = asSInt(_T_1533)
node _T_1535 = eq(_T_1534, asSInt(UInt<1>(0h0)))
node _T_1536 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1537 = cvt(_T_1536)
node _T_1538 = and(_T_1537, asSInt(UInt<18>(0h2f000)))
node _T_1539 = asSInt(_T_1538)
node _T_1540 = eq(_T_1539, asSInt(UInt<1>(0h0)))
node _T_1541 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1542 = cvt(_T_1541)
node _T_1543 = and(_T_1542, asSInt(UInt<17>(0h10000)))
node _T_1544 = asSInt(_T_1543)
node _T_1545 = eq(_T_1544, asSInt(UInt<1>(0h0)))
node _T_1546 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1547 = cvt(_T_1546)
node _T_1548 = and(_T_1547, asSInt(UInt<13>(0h1000)))
node _T_1549 = asSInt(_T_1548)
node _T_1550 = eq(_T_1549, asSInt(UInt<1>(0h0)))
node _T_1551 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1552 = cvt(_T_1551)
node _T_1553 = and(_T_1552, asSInt(UInt<17>(0h10000)))
node _T_1554 = asSInt(_T_1553)
node _T_1555 = eq(_T_1554, asSInt(UInt<1>(0h0)))
node _T_1556 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1557 = cvt(_T_1556)
node _T_1558 = and(_T_1557, asSInt(UInt<27>(0h4000000)))
node _T_1559 = asSInt(_T_1558)
node _T_1560 = eq(_T_1559, asSInt(UInt<1>(0h0)))
node _T_1561 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1562 = cvt(_T_1561)
node _T_1563 = and(_T_1562, asSInt(UInt<13>(0h1000)))
node _T_1564 = asSInt(_T_1563)
node _T_1565 = eq(_T_1564, asSInt(UInt<1>(0h0)))
node _T_1566 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1567 = cvt(_T_1566)
node _T_1568 = and(_T_1567, asSInt(UInt<29>(0h10000000)))
node _T_1569 = asSInt(_T_1568)
node _T_1570 = eq(_T_1569, asSInt(UInt<1>(0h0)))
node _T_1571 = or(_T_1515, _T_1520)
node _T_1572 = or(_T_1571, _T_1525)
node _T_1573 = or(_T_1572, _T_1530)
node _T_1574 = or(_T_1573, _T_1535)
node _T_1575 = or(_T_1574, _T_1540)
node _T_1576 = or(_T_1575, _T_1545)
node _T_1577 = or(_T_1576, _T_1550)
node _T_1578 = or(_T_1577, _T_1555)
node _T_1579 = or(_T_1578, _T_1560)
node _T_1580 = or(_T_1579, _T_1565)
node _T_1581 = or(_T_1580, _T_1570)
node _T_1582 = and(_T_1510, _T_1581)
node _T_1583 = or(UInt<1>(0h0), _T_1582)
node _T_1584 = and(UInt<1>(0h0), _T_1583)
node _T_1585 = asUInt(reset)
node _T_1586 = eq(_T_1585, UInt<1>(0h0))
when _T_1586 :
node _T_1587 = eq(_T_1584, UInt<1>(0h0))
when _T_1587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100
assert(clock, _T_1584, UInt<1>(0h1), "") : assert_100
node _T_1588 = asUInt(reset)
node _T_1589 = eq(_T_1588, UInt<1>(0h0))
when _T_1589 :
node _T_1590 = eq(address_ok, UInt<1>(0h0))
when _T_1590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101
assert(clock, address_ok, UInt<1>(0h1), "") : assert_101
node _T_1591 = asUInt(reset)
node _T_1592 = eq(_T_1591, UInt<1>(0h0))
when _T_1592 :
node _T_1593 = eq(legal_source, UInt<1>(0h0))
when _T_1593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102
assert(clock, legal_source, UInt<1>(0h1), "") : assert_102
node _T_1594 = asUInt(reset)
node _T_1595 = eq(_T_1594, UInt<1>(0h0))
when _T_1595 :
node _T_1596 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103
node _T_1597 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1598 = asUInt(reset)
node _T_1599 = eq(_T_1598, UInt<1>(0h0))
when _T_1599 :
node _T_1600 = eq(_T_1597, UInt<1>(0h0))
when _T_1600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104
assert(clock, _T_1597, UInt<1>(0h1), "") : assert_104
node _T_1601 = eq(io.in.b.bits.mask, mask_1)
node _T_1602 = asUInt(reset)
node _T_1603 = eq(_T_1602, UInt<1>(0h0))
when _T_1603 :
node _T_1604 = eq(_T_1601, UInt<1>(0h0))
when _T_1604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1601, UInt<1>(0h1), "") : assert_105
node _T_1605 = eq(io.in.b.bits.opcode, UInt<1>(0h1))
when _T_1605 :
node _T_1606 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1607 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1608 = and(_T_1606, _T_1607)
node _T_1609 = or(UInt<1>(0h0), _T_1608)
node _T_1610 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1611 = cvt(_T_1610)
node _T_1612 = and(_T_1611, asSInt(UInt<14>(0h2000)))
node _T_1613 = asSInt(_T_1612)
node _T_1614 = eq(_T_1613, asSInt(UInt<1>(0h0)))
node _T_1615 = xor(io.in.b.bits.address, UInt<14>(0h2000))
node _T_1616 = cvt(_T_1615)
node _T_1617 = and(_T_1616, asSInt(UInt<11>(0h400)))
node _T_1618 = asSInt(_T_1617)
node _T_1619 = eq(_T_1618, asSInt(UInt<1>(0h0)))
node _T_1620 = xor(io.in.b.bits.address, UInt<14>(0h2400))
node _T_1621 = cvt(_T_1620)
node _T_1622 = and(_T_1621, asSInt(UInt<9>(0h100)))
node _T_1623 = asSInt(_T_1622)
node _T_1624 = eq(_T_1623, asSInt(UInt<1>(0h0)))
node _T_1625 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1626 = cvt(_T_1625)
node _T_1627 = and(_T_1626, asSInt(UInt<13>(0h1000)))
node _T_1628 = asSInt(_T_1627)
node _T_1629 = eq(_T_1628, asSInt(UInt<1>(0h0)))
node _T_1630 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1631 = cvt(_T_1630)
node _T_1632 = and(_T_1631, asSInt(UInt<17>(0h10000)))
node _T_1633 = asSInt(_T_1632)
node _T_1634 = eq(_T_1633, asSInt(UInt<1>(0h0)))
node _T_1635 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1636 = cvt(_T_1635)
node _T_1637 = and(_T_1636, asSInt(UInt<18>(0h2f000)))
node _T_1638 = asSInt(_T_1637)
node _T_1639 = eq(_T_1638, asSInt(UInt<1>(0h0)))
node _T_1640 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1641 = cvt(_T_1640)
node _T_1642 = and(_T_1641, asSInt(UInt<17>(0h10000)))
node _T_1643 = asSInt(_T_1642)
node _T_1644 = eq(_T_1643, asSInt(UInt<1>(0h0)))
node _T_1645 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1646 = cvt(_T_1645)
node _T_1647 = and(_T_1646, asSInt(UInt<13>(0h1000)))
node _T_1648 = asSInt(_T_1647)
node _T_1649 = eq(_T_1648, asSInt(UInt<1>(0h0)))
node _T_1650 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1651 = cvt(_T_1650)
node _T_1652 = and(_T_1651, asSInt(UInt<17>(0h10000)))
node _T_1653 = asSInt(_T_1652)
node _T_1654 = eq(_T_1653, asSInt(UInt<1>(0h0)))
node _T_1655 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1656 = cvt(_T_1655)
node _T_1657 = and(_T_1656, asSInt(UInt<27>(0h4000000)))
node _T_1658 = asSInt(_T_1657)
node _T_1659 = eq(_T_1658, asSInt(UInt<1>(0h0)))
node _T_1660 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1661 = cvt(_T_1660)
node _T_1662 = and(_T_1661, asSInt(UInt<13>(0h1000)))
node _T_1663 = asSInt(_T_1662)
node _T_1664 = eq(_T_1663, asSInt(UInt<1>(0h0)))
node _T_1665 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1666 = cvt(_T_1665)
node _T_1667 = and(_T_1666, asSInt(UInt<29>(0h10000000)))
node _T_1668 = asSInt(_T_1667)
node _T_1669 = eq(_T_1668, asSInt(UInt<1>(0h0)))
node _T_1670 = or(_T_1614, _T_1619)
node _T_1671 = or(_T_1670, _T_1624)
node _T_1672 = or(_T_1671, _T_1629)
node _T_1673 = or(_T_1672, _T_1634)
node _T_1674 = or(_T_1673, _T_1639)
node _T_1675 = or(_T_1674, _T_1644)
node _T_1676 = or(_T_1675, _T_1649)
node _T_1677 = or(_T_1676, _T_1654)
node _T_1678 = or(_T_1677, _T_1659)
node _T_1679 = or(_T_1678, _T_1664)
node _T_1680 = or(_T_1679, _T_1669)
node _T_1681 = and(_T_1609, _T_1680)
node _T_1682 = or(UInt<1>(0h0), _T_1681)
node _T_1683 = and(UInt<1>(0h0), _T_1682)
node _T_1684 = asUInt(reset)
node _T_1685 = eq(_T_1684, UInt<1>(0h0))
when _T_1685 :
node _T_1686 = eq(_T_1683, UInt<1>(0h0))
when _T_1686 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1683, UInt<1>(0h1), "") : assert_106
node _T_1687 = asUInt(reset)
node _T_1688 = eq(_T_1687, UInt<1>(0h0))
when _T_1688 :
node _T_1689 = eq(address_ok, UInt<1>(0h0))
when _T_1689 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, address_ok, UInt<1>(0h1), "") : assert_107
node _T_1690 = asUInt(reset)
node _T_1691 = eq(_T_1690, UInt<1>(0h0))
when _T_1691 :
node _T_1692 = eq(legal_source, UInt<1>(0h0))
when _T_1692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108
assert(clock, legal_source, UInt<1>(0h1), "") : assert_108
node _T_1693 = asUInt(reset)
node _T_1694 = eq(_T_1693, UInt<1>(0h0))
when _T_1694 :
node _T_1695 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1695 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109
node _T_1696 = eq(io.in.b.bits.param, UInt<1>(0h0))
node _T_1697 = asUInt(reset)
node _T_1698 = eq(_T_1697, UInt<1>(0h0))
when _T_1698 :
node _T_1699 = eq(_T_1696, UInt<1>(0h0))
when _T_1699 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110
assert(clock, _T_1696, UInt<1>(0h1), "") : assert_110
node _T_1700 = not(mask_1)
node _T_1701 = and(io.in.b.bits.mask, _T_1700)
node _T_1702 = eq(_T_1701, UInt<1>(0h0))
node _T_1703 = asUInt(reset)
node _T_1704 = eq(_T_1703, UInt<1>(0h0))
when _T_1704 :
node _T_1705 = eq(_T_1702, UInt<1>(0h0))
when _T_1705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1702, UInt<1>(0h1), "") : assert_111
node _T_1706 = eq(io.in.b.bits.opcode, UInt<2>(0h2))
when _T_1706 :
node _T_1707 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1708 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1709 = and(_T_1707, _T_1708)
node _T_1710 = or(UInt<1>(0h0), _T_1709)
node _T_1711 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1712 = cvt(_T_1711)
node _T_1713 = and(_T_1712, asSInt(UInt<14>(0h2000)))
node _T_1714 = asSInt(_T_1713)
node _T_1715 = eq(_T_1714, asSInt(UInt<1>(0h0)))
node _T_1716 = xor(io.in.b.bits.address, UInt<14>(0h2000))
node _T_1717 = cvt(_T_1716)
node _T_1718 = and(_T_1717, asSInt(UInt<11>(0h400)))
node _T_1719 = asSInt(_T_1718)
node _T_1720 = eq(_T_1719, asSInt(UInt<1>(0h0)))
node _T_1721 = xor(io.in.b.bits.address, UInt<14>(0h2400))
node _T_1722 = cvt(_T_1721)
node _T_1723 = and(_T_1722, asSInt(UInt<9>(0h100)))
node _T_1724 = asSInt(_T_1723)
node _T_1725 = eq(_T_1724, asSInt(UInt<1>(0h0)))
node _T_1726 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1727 = cvt(_T_1726)
node _T_1728 = and(_T_1727, asSInt(UInt<13>(0h1000)))
node _T_1729 = asSInt(_T_1728)
node _T_1730 = eq(_T_1729, asSInt(UInt<1>(0h0)))
node _T_1731 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1732 = cvt(_T_1731)
node _T_1733 = and(_T_1732, asSInt(UInt<17>(0h10000)))
node _T_1734 = asSInt(_T_1733)
node _T_1735 = eq(_T_1734, asSInt(UInt<1>(0h0)))
node _T_1736 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1737 = cvt(_T_1736)
node _T_1738 = and(_T_1737, asSInt(UInt<18>(0h2f000)))
node _T_1739 = asSInt(_T_1738)
node _T_1740 = eq(_T_1739, asSInt(UInt<1>(0h0)))
node _T_1741 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1742 = cvt(_T_1741)
node _T_1743 = and(_T_1742, asSInt(UInt<17>(0h10000)))
node _T_1744 = asSInt(_T_1743)
node _T_1745 = eq(_T_1744, asSInt(UInt<1>(0h0)))
node _T_1746 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1747 = cvt(_T_1746)
node _T_1748 = and(_T_1747, asSInt(UInt<13>(0h1000)))
node _T_1749 = asSInt(_T_1748)
node _T_1750 = eq(_T_1749, asSInt(UInt<1>(0h0)))
node _T_1751 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1752 = cvt(_T_1751)
node _T_1753 = and(_T_1752, asSInt(UInt<17>(0h10000)))
node _T_1754 = asSInt(_T_1753)
node _T_1755 = eq(_T_1754, asSInt(UInt<1>(0h0)))
node _T_1756 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1757 = cvt(_T_1756)
node _T_1758 = and(_T_1757, asSInt(UInt<27>(0h4000000)))
node _T_1759 = asSInt(_T_1758)
node _T_1760 = eq(_T_1759, asSInt(UInt<1>(0h0)))
node _T_1761 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1762 = cvt(_T_1761)
node _T_1763 = and(_T_1762, asSInt(UInt<13>(0h1000)))
node _T_1764 = asSInt(_T_1763)
node _T_1765 = eq(_T_1764, asSInt(UInt<1>(0h0)))
node _T_1766 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1767 = cvt(_T_1766)
node _T_1768 = and(_T_1767, asSInt(UInt<29>(0h10000000)))
node _T_1769 = asSInt(_T_1768)
node _T_1770 = eq(_T_1769, asSInt(UInt<1>(0h0)))
node _T_1771 = or(_T_1715, _T_1720)
node _T_1772 = or(_T_1771, _T_1725)
node _T_1773 = or(_T_1772, _T_1730)
node _T_1774 = or(_T_1773, _T_1735)
node _T_1775 = or(_T_1774, _T_1740)
node _T_1776 = or(_T_1775, _T_1745)
node _T_1777 = or(_T_1776, _T_1750)
node _T_1778 = or(_T_1777, _T_1755)
node _T_1779 = or(_T_1778, _T_1760)
node _T_1780 = or(_T_1779, _T_1765)
node _T_1781 = or(_T_1780, _T_1770)
node _T_1782 = and(_T_1710, _T_1781)
node _T_1783 = or(UInt<1>(0h0), _T_1782)
node _T_1784 = and(UInt<1>(0h0), _T_1783)
node _T_1785 = asUInt(reset)
node _T_1786 = eq(_T_1785, UInt<1>(0h0))
when _T_1786 :
node _T_1787 = eq(_T_1784, UInt<1>(0h0))
when _T_1787 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112
assert(clock, _T_1784, UInt<1>(0h1), "") : assert_112
node _T_1788 = asUInt(reset)
node _T_1789 = eq(_T_1788, UInt<1>(0h0))
when _T_1789 :
node _T_1790 = eq(address_ok, UInt<1>(0h0))
when _T_1790 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, address_ok, UInt<1>(0h1), "") : assert_113
node _T_1791 = asUInt(reset)
node _T_1792 = eq(_T_1791, UInt<1>(0h0))
when _T_1792 :
node _T_1793 = eq(legal_source, UInt<1>(0h0))
when _T_1793 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114
assert(clock, legal_source, UInt<1>(0h1), "") : assert_114
node _T_1794 = asUInt(reset)
node _T_1795 = eq(_T_1794, UInt<1>(0h0))
when _T_1795 :
node _T_1796 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115
node _T_1797 = leq(io.in.b.bits.param, UInt<3>(0h4))
node _T_1798 = asUInt(reset)
node _T_1799 = eq(_T_1798, UInt<1>(0h0))
when _T_1799 :
node _T_1800 = eq(_T_1797, UInt<1>(0h0))
when _T_1800 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116
assert(clock, _T_1797, UInt<1>(0h1), "") : assert_116
node _T_1801 = eq(io.in.b.bits.mask, mask_1)
node _T_1802 = asUInt(reset)
node _T_1803 = eq(_T_1802, UInt<1>(0h0))
when _T_1803 :
node _T_1804 = eq(_T_1801, UInt<1>(0h0))
when _T_1804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117
assert(clock, _T_1801, UInt<1>(0h1), "") : assert_117
node _T_1805 = eq(io.in.b.bits.opcode, UInt<2>(0h3))
when _T_1805 :
node _T_1806 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1807 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1808 = and(_T_1806, _T_1807)
node _T_1809 = or(UInt<1>(0h0), _T_1808)
node _T_1810 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1811 = cvt(_T_1810)
node _T_1812 = and(_T_1811, asSInt(UInt<14>(0h2000)))
node _T_1813 = asSInt(_T_1812)
node _T_1814 = eq(_T_1813, asSInt(UInt<1>(0h0)))
node _T_1815 = xor(io.in.b.bits.address, UInt<14>(0h2000))
node _T_1816 = cvt(_T_1815)
node _T_1817 = and(_T_1816, asSInt(UInt<11>(0h400)))
node _T_1818 = asSInt(_T_1817)
node _T_1819 = eq(_T_1818, asSInt(UInt<1>(0h0)))
node _T_1820 = xor(io.in.b.bits.address, UInt<14>(0h2400))
node _T_1821 = cvt(_T_1820)
node _T_1822 = and(_T_1821, asSInt(UInt<9>(0h100)))
node _T_1823 = asSInt(_T_1822)
node _T_1824 = eq(_T_1823, asSInt(UInt<1>(0h0)))
node _T_1825 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1826 = cvt(_T_1825)
node _T_1827 = and(_T_1826, asSInt(UInt<13>(0h1000)))
node _T_1828 = asSInt(_T_1827)
node _T_1829 = eq(_T_1828, asSInt(UInt<1>(0h0)))
node _T_1830 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1831 = cvt(_T_1830)
node _T_1832 = and(_T_1831, asSInt(UInt<17>(0h10000)))
node _T_1833 = asSInt(_T_1832)
node _T_1834 = eq(_T_1833, asSInt(UInt<1>(0h0)))
node _T_1835 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1836 = cvt(_T_1835)
node _T_1837 = and(_T_1836, asSInt(UInt<18>(0h2f000)))
node _T_1838 = asSInt(_T_1837)
node _T_1839 = eq(_T_1838, asSInt(UInt<1>(0h0)))
node _T_1840 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1841 = cvt(_T_1840)
node _T_1842 = and(_T_1841, asSInt(UInt<17>(0h10000)))
node _T_1843 = asSInt(_T_1842)
node _T_1844 = eq(_T_1843, asSInt(UInt<1>(0h0)))
node _T_1845 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1846 = cvt(_T_1845)
node _T_1847 = and(_T_1846, asSInt(UInt<13>(0h1000)))
node _T_1848 = asSInt(_T_1847)
node _T_1849 = eq(_T_1848, asSInt(UInt<1>(0h0)))
node _T_1850 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1851 = cvt(_T_1850)
node _T_1852 = and(_T_1851, asSInt(UInt<17>(0h10000)))
node _T_1853 = asSInt(_T_1852)
node _T_1854 = eq(_T_1853, asSInt(UInt<1>(0h0)))
node _T_1855 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1856 = cvt(_T_1855)
node _T_1857 = and(_T_1856, asSInt(UInt<27>(0h4000000)))
node _T_1858 = asSInt(_T_1857)
node _T_1859 = eq(_T_1858, asSInt(UInt<1>(0h0)))
node _T_1860 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1861 = cvt(_T_1860)
node _T_1862 = and(_T_1861, asSInt(UInt<13>(0h1000)))
node _T_1863 = asSInt(_T_1862)
node _T_1864 = eq(_T_1863, asSInt(UInt<1>(0h0)))
node _T_1865 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1866 = cvt(_T_1865)
node _T_1867 = and(_T_1866, asSInt(UInt<29>(0h10000000)))
node _T_1868 = asSInt(_T_1867)
node _T_1869 = eq(_T_1868, asSInt(UInt<1>(0h0)))
node _T_1870 = or(_T_1814, _T_1819)
node _T_1871 = or(_T_1870, _T_1824)
node _T_1872 = or(_T_1871, _T_1829)
node _T_1873 = or(_T_1872, _T_1834)
node _T_1874 = or(_T_1873, _T_1839)
node _T_1875 = or(_T_1874, _T_1844)
node _T_1876 = or(_T_1875, _T_1849)
node _T_1877 = or(_T_1876, _T_1854)
node _T_1878 = or(_T_1877, _T_1859)
node _T_1879 = or(_T_1878, _T_1864)
node _T_1880 = or(_T_1879, _T_1869)
node _T_1881 = and(_T_1809, _T_1880)
node _T_1882 = or(UInt<1>(0h0), _T_1881)
node _T_1883 = and(UInt<1>(0h0), _T_1882)
node _T_1884 = asUInt(reset)
node _T_1885 = eq(_T_1884, UInt<1>(0h0))
when _T_1885 :
node _T_1886 = eq(_T_1883, UInt<1>(0h0))
when _T_1886 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118
assert(clock, _T_1883, UInt<1>(0h1), "") : assert_118
node _T_1887 = asUInt(reset)
node _T_1888 = eq(_T_1887, UInt<1>(0h0))
when _T_1888 :
node _T_1889 = eq(address_ok, UInt<1>(0h0))
when _T_1889 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119
assert(clock, address_ok, UInt<1>(0h1), "") : assert_119
node _T_1890 = asUInt(reset)
node _T_1891 = eq(_T_1890, UInt<1>(0h0))
when _T_1891 :
node _T_1892 = eq(legal_source, UInt<1>(0h0))
when _T_1892 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120
assert(clock, legal_source, UInt<1>(0h1), "") : assert_120
node _T_1893 = asUInt(reset)
node _T_1894 = eq(_T_1893, UInt<1>(0h0))
when _T_1894 :
node _T_1895 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1895 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121
node _T_1896 = leq(io.in.b.bits.param, UInt<3>(0h3))
node _T_1897 = asUInt(reset)
node _T_1898 = eq(_T_1897, UInt<1>(0h0))
when _T_1898 :
node _T_1899 = eq(_T_1896, UInt<1>(0h0))
when _T_1899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122
assert(clock, _T_1896, UInt<1>(0h1), "") : assert_122
node _T_1900 = eq(io.in.b.bits.mask, mask_1)
node _T_1901 = asUInt(reset)
node _T_1902 = eq(_T_1901, UInt<1>(0h0))
when _T_1902 :
node _T_1903 = eq(_T_1900, UInt<1>(0h0))
when _T_1903 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123
assert(clock, _T_1900, UInt<1>(0h1), "") : assert_123
node _T_1904 = eq(io.in.b.bits.opcode, UInt<3>(0h5))
when _T_1904 :
node _T_1905 = leq(UInt<1>(0h0), io.in.b.bits.size)
node _T_1906 = leq(io.in.b.bits.size, UInt<4>(0hc))
node _T_1907 = and(_T_1905, _T_1906)
node _T_1908 = or(UInt<1>(0h0), _T_1907)
node _T_1909 = xor(io.in.b.bits.address, UInt<1>(0h0))
node _T_1910 = cvt(_T_1909)
node _T_1911 = and(_T_1910, asSInt(UInt<14>(0h2000)))
node _T_1912 = asSInt(_T_1911)
node _T_1913 = eq(_T_1912, asSInt(UInt<1>(0h0)))
node _T_1914 = xor(io.in.b.bits.address, UInt<14>(0h2000))
node _T_1915 = cvt(_T_1914)
node _T_1916 = and(_T_1915, asSInt(UInt<11>(0h400)))
node _T_1917 = asSInt(_T_1916)
node _T_1918 = eq(_T_1917, asSInt(UInt<1>(0h0)))
node _T_1919 = xor(io.in.b.bits.address, UInt<14>(0h2400))
node _T_1920 = cvt(_T_1919)
node _T_1921 = and(_T_1920, asSInt(UInt<9>(0h100)))
node _T_1922 = asSInt(_T_1921)
node _T_1923 = eq(_T_1922, asSInt(UInt<1>(0h0)))
node _T_1924 = xor(io.in.b.bits.address, UInt<14>(0h3000))
node _T_1925 = cvt(_T_1924)
node _T_1926 = and(_T_1925, asSInt(UInt<13>(0h1000)))
node _T_1927 = asSInt(_T_1926)
node _T_1928 = eq(_T_1927, asSInt(UInt<1>(0h0)))
node _T_1929 = xor(io.in.b.bits.address, UInt<17>(0h10000))
node _T_1930 = cvt(_T_1929)
node _T_1931 = and(_T_1930, asSInt(UInt<17>(0h10000)))
node _T_1932 = asSInt(_T_1931)
node _T_1933 = eq(_T_1932, asSInt(UInt<1>(0h0)))
node _T_1934 = xor(io.in.b.bits.address, UInt<21>(0h100000))
node _T_1935 = cvt(_T_1934)
node _T_1936 = and(_T_1935, asSInt(UInt<18>(0h2f000)))
node _T_1937 = asSInt(_T_1936)
node _T_1938 = eq(_T_1937, asSInt(UInt<1>(0h0)))
node _T_1939 = xor(io.in.b.bits.address, UInt<26>(0h2000000))
node _T_1940 = cvt(_T_1939)
node _T_1941 = and(_T_1940, asSInt(UInt<17>(0h10000)))
node _T_1942 = asSInt(_T_1941)
node _T_1943 = eq(_T_1942, asSInt(UInt<1>(0h0)))
node _T_1944 = xor(io.in.b.bits.address, UInt<26>(0h2010000))
node _T_1945 = cvt(_T_1944)
node _T_1946 = and(_T_1945, asSInt(UInt<13>(0h1000)))
node _T_1947 = asSInt(_T_1946)
node _T_1948 = eq(_T_1947, asSInt(UInt<1>(0h0)))
node _T_1949 = xor(io.in.b.bits.address, UInt<28>(0h8000000))
node _T_1950 = cvt(_T_1949)
node _T_1951 = and(_T_1950, asSInt(UInt<17>(0h10000)))
node _T_1952 = asSInt(_T_1951)
node _T_1953 = eq(_T_1952, asSInt(UInt<1>(0h0)))
node _T_1954 = xor(io.in.b.bits.address, UInt<28>(0hc000000))
node _T_1955 = cvt(_T_1954)
node _T_1956 = and(_T_1955, asSInt(UInt<27>(0h4000000)))
node _T_1957 = asSInt(_T_1956)
node _T_1958 = eq(_T_1957, asSInt(UInt<1>(0h0)))
node _T_1959 = xor(io.in.b.bits.address, UInt<29>(0h10020000))
node _T_1960 = cvt(_T_1959)
node _T_1961 = and(_T_1960, asSInt(UInt<13>(0h1000)))
node _T_1962 = asSInt(_T_1961)
node _T_1963 = eq(_T_1962, asSInt(UInt<1>(0h0)))
node _T_1964 = xor(io.in.b.bits.address, UInt<32>(0h80000000))
node _T_1965 = cvt(_T_1964)
node _T_1966 = and(_T_1965, asSInt(UInt<29>(0h10000000)))
node _T_1967 = asSInt(_T_1966)
node _T_1968 = eq(_T_1967, asSInt(UInt<1>(0h0)))
node _T_1969 = or(_T_1913, _T_1918)
node _T_1970 = or(_T_1969, _T_1923)
node _T_1971 = or(_T_1970, _T_1928)
node _T_1972 = or(_T_1971, _T_1933)
node _T_1973 = or(_T_1972, _T_1938)
node _T_1974 = or(_T_1973, _T_1943)
node _T_1975 = or(_T_1974, _T_1948)
node _T_1976 = or(_T_1975, _T_1953)
node _T_1977 = or(_T_1976, _T_1958)
node _T_1978 = or(_T_1977, _T_1963)
node _T_1979 = or(_T_1978, _T_1968)
node _T_1980 = and(_T_1908, _T_1979)
node _T_1981 = or(UInt<1>(0h0), _T_1980)
node _T_1982 = and(UInt<1>(0h0), _T_1981)
node _T_1983 = asUInt(reset)
node _T_1984 = eq(_T_1983, UInt<1>(0h0))
when _T_1984 :
node _T_1985 = eq(_T_1982, UInt<1>(0h0))
when _T_1985 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124
assert(clock, _T_1982, UInt<1>(0h1), "") : assert_124
node _T_1986 = asUInt(reset)
node _T_1987 = eq(_T_1986, UInt<1>(0h0))
when _T_1987 :
node _T_1988 = eq(address_ok, UInt<1>(0h0))
when _T_1988 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125
assert(clock, address_ok, UInt<1>(0h1), "") : assert_125
node _T_1989 = asUInt(reset)
node _T_1990 = eq(_T_1989, UInt<1>(0h0))
when _T_1990 :
node _T_1991 = eq(legal_source, UInt<1>(0h0))
when _T_1991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126
assert(clock, legal_source, UInt<1>(0h1), "") : assert_126
node _T_1992 = asUInt(reset)
node _T_1993 = eq(_T_1992, UInt<1>(0h0))
when _T_1993 :
node _T_1994 = eq(is_aligned_1, UInt<1>(0h0))
when _T_1994 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127
assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127
node _T_1995 = eq(io.in.b.bits.mask, mask_1)
node _T_1996 = asUInt(reset)
node _T_1997 = eq(_T_1996, UInt<1>(0h0))
when _T_1997 :
node _T_1998 = eq(_T_1995, UInt<1>(0h0))
when _T_1998 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128
assert(clock, _T_1995, UInt<1>(0h1), "") : assert_128
node _T_1999 = eq(io.in.b.bits.corrupt, UInt<1>(0h0))
node _T_2000 = asUInt(reset)
node _T_2001 = eq(_T_2000, UInt<1>(0h0))
when _T_2001 :
node _T_2002 = eq(_T_1999, UInt<1>(0h0))
when _T_2002 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129
assert(clock, _T_1999, UInt<1>(0h1), "") : assert_129
when io.in.c.valid :
node _T_2003 = leq(io.in.c.bits.opcode, UInt<3>(0h7))
node _T_2004 = asUInt(reset)
node _T_2005 = eq(_T_2004, UInt<1>(0h0))
when _T_2005 :
node _T_2006 = eq(_T_2003, UInt<1>(0h0))
when _T_2006 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130
assert(clock, _T_2003, UInt<1>(0h1), "") : assert_130
node _source_ok_T_8 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _source_ok_T_9 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _source_ok_T_10 = eq(io.in.c.bits.source, UInt<2>(0h2))
wire _source_ok_WIRE_2 : UInt<1>[3]
connect _source_ok_WIRE_2[0], _source_ok_T_8
connect _source_ok_WIRE_2[1], _source_ok_T_9
connect _source_ok_WIRE_2[2], _source_ok_T_10
node _source_ok_T_11 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1])
node source_ok_2 = or(_source_ok_T_11, _source_ok_WIRE_2[2])
node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0)
node is_aligned_mask_2 = not(_is_aligned_mask_T_5)
node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2)
node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0))
node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _address_ok_T_101 = cvt(_address_ok_T_100)
node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<13>(0h1000)))
node _address_ok_T_103 = asSInt(_address_ok_T_102)
node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0)))
node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<13>(0h1000))
node _address_ok_T_106 = cvt(_address_ok_T_105)
node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000)))
node _address_ok_T_108 = asSInt(_address_ok_T_107)
node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0)))
node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<14>(0h2000))
node _address_ok_T_111 = cvt(_address_ok_T_110)
node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<9>(0h100)))
node _address_ok_T_113 = asSInt(_address_ok_T_112)
node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0)))
node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<14>(0h2100))
node _address_ok_T_116 = cvt(_address_ok_T_115)
node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<9>(0h100)))
node _address_ok_T_118 = asSInt(_address_ok_T_117)
node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0)))
node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<14>(0h2200))
node _address_ok_T_121 = cvt(_address_ok_T_120)
node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<9>(0h100)))
node _address_ok_T_123 = asSInt(_address_ok_T_122)
node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0)))
node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<14>(0h2300))
node _address_ok_T_126 = cvt(_address_ok_T_125)
node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<9>(0h100)))
node _address_ok_T_128 = asSInt(_address_ok_T_127)
node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0)))
node _address_ok_T_130 = xor(io.in.c.bits.address, UInt<14>(0h2400))
node _address_ok_T_131 = cvt(_address_ok_T_130)
node _address_ok_T_132 = and(_address_ok_T_131, asSInt(UInt<9>(0h100)))
node _address_ok_T_133 = asSInt(_address_ok_T_132)
node _address_ok_T_134 = eq(_address_ok_T_133, asSInt(UInt<1>(0h0)))
node _address_ok_T_135 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _address_ok_T_136 = cvt(_address_ok_T_135)
node _address_ok_T_137 = and(_address_ok_T_136, asSInt(UInt<13>(0h1000)))
node _address_ok_T_138 = asSInt(_address_ok_T_137)
node _address_ok_T_139 = eq(_address_ok_T_138, asSInt(UInt<1>(0h0)))
node _address_ok_T_140 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _address_ok_T_141 = cvt(_address_ok_T_140)
node _address_ok_T_142 = and(_address_ok_T_141, asSInt(UInt<17>(0h10000)))
node _address_ok_T_143 = asSInt(_address_ok_T_142)
node _address_ok_T_144 = eq(_address_ok_T_143, asSInt(UInt<1>(0h0)))
node _address_ok_T_145 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _address_ok_T_146 = cvt(_address_ok_T_145)
node _address_ok_T_147 = and(_address_ok_T_146, asSInt(UInt<13>(0h1000)))
node _address_ok_T_148 = asSInt(_address_ok_T_147)
node _address_ok_T_149 = eq(_address_ok_T_148, asSInt(UInt<1>(0h0)))
node _address_ok_T_150 = xor(io.in.c.bits.address, UInt<21>(0h110000))
node _address_ok_T_151 = cvt(_address_ok_T_150)
node _address_ok_T_152 = and(_address_ok_T_151, asSInt(UInt<13>(0h1000)))
node _address_ok_T_153 = asSInt(_address_ok_T_152)
node _address_ok_T_154 = eq(_address_ok_T_153, asSInt(UInt<1>(0h0)))
node _address_ok_T_155 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _address_ok_T_156 = cvt(_address_ok_T_155)
node _address_ok_T_157 = and(_address_ok_T_156, asSInt(UInt<17>(0h10000)))
node _address_ok_T_158 = asSInt(_address_ok_T_157)
node _address_ok_T_159 = eq(_address_ok_T_158, asSInt(UInt<1>(0h0)))
node _address_ok_T_160 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _address_ok_T_161 = cvt(_address_ok_T_160)
node _address_ok_T_162 = and(_address_ok_T_161, asSInt(UInt<13>(0h1000)))
node _address_ok_T_163 = asSInt(_address_ok_T_162)
node _address_ok_T_164 = eq(_address_ok_T_163, asSInt(UInt<1>(0h0)))
node _address_ok_T_165 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _address_ok_T_166 = cvt(_address_ok_T_165)
node _address_ok_T_167 = and(_address_ok_T_166, asSInt(UInt<17>(0h10000)))
node _address_ok_T_168 = asSInt(_address_ok_T_167)
node _address_ok_T_169 = eq(_address_ok_T_168, asSInt(UInt<1>(0h0)))
node _address_ok_T_170 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _address_ok_T_171 = cvt(_address_ok_T_170)
node _address_ok_T_172 = and(_address_ok_T_171, asSInt(UInt<27>(0h4000000)))
node _address_ok_T_173 = asSInt(_address_ok_T_172)
node _address_ok_T_174 = eq(_address_ok_T_173, asSInt(UInt<1>(0h0)))
node _address_ok_T_175 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _address_ok_T_176 = cvt(_address_ok_T_175)
node _address_ok_T_177 = and(_address_ok_T_176, asSInt(UInt<13>(0h1000)))
node _address_ok_T_178 = asSInt(_address_ok_T_177)
node _address_ok_T_179 = eq(_address_ok_T_178, asSInt(UInt<1>(0h0)))
node _address_ok_T_180 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _address_ok_T_181 = cvt(_address_ok_T_180)
node _address_ok_T_182 = and(_address_ok_T_181, asSInt(UInt<29>(0h10000000)))
node _address_ok_T_183 = asSInt(_address_ok_T_182)
node _address_ok_T_184 = eq(_address_ok_T_183, asSInt(UInt<1>(0h0)))
wire _address_ok_WIRE_1 : UInt<1>[17]
connect _address_ok_WIRE_1[0], _address_ok_T_104
connect _address_ok_WIRE_1[1], _address_ok_T_109
connect _address_ok_WIRE_1[2], _address_ok_T_114
connect _address_ok_WIRE_1[3], _address_ok_T_119
connect _address_ok_WIRE_1[4], _address_ok_T_124
connect _address_ok_WIRE_1[5], _address_ok_T_129
connect _address_ok_WIRE_1[6], _address_ok_T_134
connect _address_ok_WIRE_1[7], _address_ok_T_139
connect _address_ok_WIRE_1[8], _address_ok_T_144
connect _address_ok_WIRE_1[9], _address_ok_T_149
connect _address_ok_WIRE_1[10], _address_ok_T_154
connect _address_ok_WIRE_1[11], _address_ok_T_159
connect _address_ok_WIRE_1[12], _address_ok_T_164
connect _address_ok_WIRE_1[13], _address_ok_T_169
connect _address_ok_WIRE_1[14], _address_ok_T_174
connect _address_ok_WIRE_1[15], _address_ok_T_179
connect _address_ok_WIRE_1[16], _address_ok_T_184
node _address_ok_T_185 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1])
node _address_ok_T_186 = or(_address_ok_T_185, _address_ok_WIRE_1[2])
node _address_ok_T_187 = or(_address_ok_T_186, _address_ok_WIRE_1[3])
node _address_ok_T_188 = or(_address_ok_T_187, _address_ok_WIRE_1[4])
node _address_ok_T_189 = or(_address_ok_T_188, _address_ok_WIRE_1[5])
node _address_ok_T_190 = or(_address_ok_T_189, _address_ok_WIRE_1[6])
node _address_ok_T_191 = or(_address_ok_T_190, _address_ok_WIRE_1[7])
node _address_ok_T_192 = or(_address_ok_T_191, _address_ok_WIRE_1[8])
node _address_ok_T_193 = or(_address_ok_T_192, _address_ok_WIRE_1[9])
node _address_ok_T_194 = or(_address_ok_T_193, _address_ok_WIRE_1[10])
node _address_ok_T_195 = or(_address_ok_T_194, _address_ok_WIRE_1[11])
node _address_ok_T_196 = or(_address_ok_T_195, _address_ok_WIRE_1[12])
node _address_ok_T_197 = or(_address_ok_T_196, _address_ok_WIRE_1[13])
node _address_ok_T_198 = or(_address_ok_T_197, _address_ok_WIRE_1[14])
node _address_ok_T_199 = or(_address_ok_T_198, _address_ok_WIRE_1[15])
node address_ok_1 = or(_address_ok_T_199, _address_ok_WIRE_1[16])
node _T_2007 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2008 = eq(_T_2007, UInt<1>(0h0))
node _T_2009 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2010 = cvt(_T_2009)
node _T_2011 = and(_T_2010, asSInt(UInt<1>(0h0)))
node _T_2012 = asSInt(_T_2011)
node _T_2013 = eq(_T_2012, asSInt(UInt<1>(0h0)))
node _T_2014 = or(_T_2008, _T_2013)
node _T_2015 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_2016 = eq(_T_2015, UInt<1>(0h0))
node _T_2017 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2018 = cvt(_T_2017)
node _T_2019 = and(_T_2018, asSInt(UInt<1>(0h0)))
node _T_2020 = asSInt(_T_2019)
node _T_2021 = eq(_T_2020, asSInt(UInt<1>(0h0)))
node _T_2022 = or(_T_2016, _T_2021)
node _T_2023 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_2024 = eq(_T_2023, UInt<1>(0h0))
node _T_2025 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2026 = cvt(_T_2025)
node _T_2027 = and(_T_2026, asSInt(UInt<1>(0h0)))
node _T_2028 = asSInt(_T_2027)
node _T_2029 = eq(_T_2028, asSInt(UInt<1>(0h0)))
node _T_2030 = or(_T_2024, _T_2029)
node _T_2031 = and(_T_2014, _T_2022)
node _T_2032 = and(_T_2031, _T_2030)
node _T_2033 = asUInt(reset)
node _T_2034 = eq(_T_2033, UInt<1>(0h0))
when _T_2034 :
node _T_2035 = eq(_T_2032, UInt<1>(0h0))
when _T_2035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131
assert(clock, _T_2032, UInt<1>(0h1), "") : assert_131
node _T_2036 = eq(io.in.c.bits.opcode, UInt<3>(0h4))
when _T_2036 :
node _T_2037 = asUInt(reset)
node _T_2038 = eq(_T_2037, UInt<1>(0h0))
when _T_2038 :
node _T_2039 = eq(address_ok_1, UInt<1>(0h0))
when _T_2039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132
node _T_2040 = asUInt(reset)
node _T_2041 = eq(_T_2040, UInt<1>(0h0))
when _T_2041 :
node _T_2042 = eq(source_ok_2, UInt<1>(0h0))
when _T_2042 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133
node _T_2043 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2044 = asUInt(reset)
node _T_2045 = eq(_T_2044, UInt<1>(0h0))
when _T_2045 :
node _T_2046 = eq(_T_2043, UInt<1>(0h0))
when _T_2046 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134
assert(clock, _T_2043, UInt<1>(0h1), "") : assert_134
node _T_2047 = asUInt(reset)
node _T_2048 = eq(_T_2047, UInt<1>(0h0))
when _T_2048 :
node _T_2049 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2049 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135
node _T_2050 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2051 = asUInt(reset)
node _T_2052 = eq(_T_2051, UInt<1>(0h0))
when _T_2052 :
node _T_2053 = eq(_T_2050, UInt<1>(0h0))
when _T_2053 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136
assert(clock, _T_2050, UInt<1>(0h1), "") : assert_136
node _T_2054 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2055 = asUInt(reset)
node _T_2056 = eq(_T_2055, UInt<1>(0h0))
when _T_2056 :
node _T_2057 = eq(_T_2054, UInt<1>(0h0))
when _T_2057 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137
assert(clock, _T_2054, UInt<1>(0h1), "") : assert_137
node _T_2058 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
when _T_2058 :
node _T_2059 = asUInt(reset)
node _T_2060 = eq(_T_2059, UInt<1>(0h0))
when _T_2060 :
node _T_2061 = eq(address_ok_1, UInt<1>(0h0))
when _T_2061 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138
node _T_2062 = asUInt(reset)
node _T_2063 = eq(_T_2062, UInt<1>(0h0))
when _T_2063 :
node _T_2064 = eq(source_ok_2, UInt<1>(0h0))
when _T_2064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139
node _T_2065 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2066 = asUInt(reset)
node _T_2067 = eq(_T_2066, UInt<1>(0h0))
when _T_2067 :
node _T_2068 = eq(_T_2065, UInt<1>(0h0))
when _T_2068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140
assert(clock, _T_2065, UInt<1>(0h1), "") : assert_140
node _T_2069 = asUInt(reset)
node _T_2070 = eq(_T_2069, UInt<1>(0h0))
when _T_2070 :
node _T_2071 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141
node _T_2072 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2073 = asUInt(reset)
node _T_2074 = eq(_T_2073, UInt<1>(0h0))
when _T_2074 :
node _T_2075 = eq(_T_2072, UInt<1>(0h0))
when _T_2075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142
assert(clock, _T_2072, UInt<1>(0h1), "") : assert_142
node _T_2076 = eq(io.in.c.bits.opcode, UInt<3>(0h6))
when _T_2076 :
node _T_2077 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2078 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2079 = and(_T_2077, _T_2078)
node _T_2080 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2081 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_2082 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_2083 = or(_T_2080, _T_2081)
node _T_2084 = or(_T_2083, _T_2082)
node _T_2085 = and(_T_2079, _T_2084)
node _T_2086 = or(UInt<1>(0h0), _T_2085)
node _T_2087 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2088 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2089 = cvt(_T_2088)
node _T_2090 = and(_T_2089, asSInt(UInt<14>(0h2000)))
node _T_2091 = asSInt(_T_2090)
node _T_2092 = eq(_T_2091, asSInt(UInt<1>(0h0)))
node _T_2093 = xor(io.in.c.bits.address, UInt<14>(0h2000))
node _T_2094 = cvt(_T_2093)
node _T_2095 = and(_T_2094, asSInt(UInt<11>(0h400)))
node _T_2096 = asSInt(_T_2095)
node _T_2097 = eq(_T_2096, asSInt(UInt<1>(0h0)))
node _T_2098 = xor(io.in.c.bits.address, UInt<14>(0h2400))
node _T_2099 = cvt(_T_2098)
node _T_2100 = and(_T_2099, asSInt(UInt<9>(0h100)))
node _T_2101 = asSInt(_T_2100)
node _T_2102 = eq(_T_2101, asSInt(UInt<1>(0h0)))
node _T_2103 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2104 = cvt(_T_2103)
node _T_2105 = and(_T_2104, asSInt(UInt<13>(0h1000)))
node _T_2106 = asSInt(_T_2105)
node _T_2107 = eq(_T_2106, asSInt(UInt<1>(0h0)))
node _T_2108 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2109 = cvt(_T_2108)
node _T_2110 = and(_T_2109, asSInt(UInt<17>(0h10000)))
node _T_2111 = asSInt(_T_2110)
node _T_2112 = eq(_T_2111, asSInt(UInt<1>(0h0)))
node _T_2113 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2114 = cvt(_T_2113)
node _T_2115 = and(_T_2114, asSInt(UInt<18>(0h2f000)))
node _T_2116 = asSInt(_T_2115)
node _T_2117 = eq(_T_2116, asSInt(UInt<1>(0h0)))
node _T_2118 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2119 = cvt(_T_2118)
node _T_2120 = and(_T_2119, asSInt(UInt<17>(0h10000)))
node _T_2121 = asSInt(_T_2120)
node _T_2122 = eq(_T_2121, asSInt(UInt<1>(0h0)))
node _T_2123 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2124 = cvt(_T_2123)
node _T_2125 = and(_T_2124, asSInt(UInt<13>(0h1000)))
node _T_2126 = asSInt(_T_2125)
node _T_2127 = eq(_T_2126, asSInt(UInt<1>(0h0)))
node _T_2128 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2129 = cvt(_T_2128)
node _T_2130 = and(_T_2129, asSInt(UInt<27>(0h4000000)))
node _T_2131 = asSInt(_T_2130)
node _T_2132 = eq(_T_2131, asSInt(UInt<1>(0h0)))
node _T_2133 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2134 = cvt(_T_2133)
node _T_2135 = and(_T_2134, asSInt(UInt<13>(0h1000)))
node _T_2136 = asSInt(_T_2135)
node _T_2137 = eq(_T_2136, asSInt(UInt<1>(0h0)))
node _T_2138 = or(_T_2092, _T_2097)
node _T_2139 = or(_T_2138, _T_2102)
node _T_2140 = or(_T_2139, _T_2107)
node _T_2141 = or(_T_2140, _T_2112)
node _T_2142 = or(_T_2141, _T_2117)
node _T_2143 = or(_T_2142, _T_2122)
node _T_2144 = or(_T_2143, _T_2127)
node _T_2145 = or(_T_2144, _T_2132)
node _T_2146 = or(_T_2145, _T_2137)
node _T_2147 = and(_T_2087, _T_2146)
node _T_2148 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2149 = or(UInt<1>(0h0), _T_2148)
node _T_2150 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2151 = cvt(_T_2150)
node _T_2152 = and(_T_2151, asSInt(UInt<17>(0h10000)))
node _T_2153 = asSInt(_T_2152)
node _T_2154 = eq(_T_2153, asSInt(UInt<1>(0h0)))
node _T_2155 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2156 = cvt(_T_2155)
node _T_2157 = and(_T_2156, asSInt(UInt<29>(0h10000000)))
node _T_2158 = asSInt(_T_2157)
node _T_2159 = eq(_T_2158, asSInt(UInt<1>(0h0)))
node _T_2160 = or(_T_2154, _T_2159)
node _T_2161 = and(_T_2149, _T_2160)
node _T_2162 = or(UInt<1>(0h0), _T_2147)
node _T_2163 = or(_T_2162, _T_2161)
node _T_2164 = and(_T_2086, _T_2163)
node _T_2165 = asUInt(reset)
node _T_2166 = eq(_T_2165, UInt<1>(0h0))
when _T_2166 :
node _T_2167 = eq(_T_2164, UInt<1>(0h0))
when _T_2167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143
assert(clock, _T_2164, UInt<1>(0h1), "") : assert_143
node _T_2168 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2169 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_2170 = eq(io.in.c.bits.source, UInt<2>(0h2))
wire _WIRE_6 : UInt<1>[3]
connect _WIRE_6[0], _T_2168
connect _WIRE_6[1], _T_2169
connect _WIRE_6[2], _T_2170
node _T_2171 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2172 = mux(_WIRE_6[0], _T_2171, UInt<1>(0h0))
node _T_2173 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2174 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2175 = or(_T_2172, _T_2173)
node _T_2176 = or(_T_2175, _T_2174)
wire _WIRE_7 : UInt<1>
connect _WIRE_7, _T_2176
node _T_2177 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2178 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2179 = and(_T_2177, _T_2178)
node _T_2180 = or(UInt<1>(0h0), _T_2179)
node _T_2181 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2182 = cvt(_T_2181)
node _T_2183 = and(_T_2182, asSInt(UInt<14>(0h2000)))
node _T_2184 = asSInt(_T_2183)
node _T_2185 = eq(_T_2184, asSInt(UInt<1>(0h0)))
node _T_2186 = xor(io.in.c.bits.address, UInt<14>(0h2000))
node _T_2187 = cvt(_T_2186)
node _T_2188 = and(_T_2187, asSInt(UInt<11>(0h400)))
node _T_2189 = asSInt(_T_2188)
node _T_2190 = eq(_T_2189, asSInt(UInt<1>(0h0)))
node _T_2191 = xor(io.in.c.bits.address, UInt<14>(0h2400))
node _T_2192 = cvt(_T_2191)
node _T_2193 = and(_T_2192, asSInt(UInt<9>(0h100)))
node _T_2194 = asSInt(_T_2193)
node _T_2195 = eq(_T_2194, asSInt(UInt<1>(0h0)))
node _T_2196 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2197 = cvt(_T_2196)
node _T_2198 = and(_T_2197, asSInt(UInt<13>(0h1000)))
node _T_2199 = asSInt(_T_2198)
node _T_2200 = eq(_T_2199, asSInt(UInt<1>(0h0)))
node _T_2201 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2202 = cvt(_T_2201)
node _T_2203 = and(_T_2202, asSInt(UInt<17>(0h10000)))
node _T_2204 = asSInt(_T_2203)
node _T_2205 = eq(_T_2204, asSInt(UInt<1>(0h0)))
node _T_2206 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2207 = cvt(_T_2206)
node _T_2208 = and(_T_2207, asSInt(UInt<18>(0h2f000)))
node _T_2209 = asSInt(_T_2208)
node _T_2210 = eq(_T_2209, asSInt(UInt<1>(0h0)))
node _T_2211 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2212 = cvt(_T_2211)
node _T_2213 = and(_T_2212, asSInt(UInt<17>(0h10000)))
node _T_2214 = asSInt(_T_2213)
node _T_2215 = eq(_T_2214, asSInt(UInt<1>(0h0)))
node _T_2216 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2217 = cvt(_T_2216)
node _T_2218 = and(_T_2217, asSInt(UInt<13>(0h1000)))
node _T_2219 = asSInt(_T_2218)
node _T_2220 = eq(_T_2219, asSInt(UInt<1>(0h0)))
node _T_2221 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2222 = cvt(_T_2221)
node _T_2223 = and(_T_2222, asSInt(UInt<17>(0h10000)))
node _T_2224 = asSInt(_T_2223)
node _T_2225 = eq(_T_2224, asSInt(UInt<1>(0h0)))
node _T_2226 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2227 = cvt(_T_2226)
node _T_2228 = and(_T_2227, asSInt(UInt<27>(0h4000000)))
node _T_2229 = asSInt(_T_2228)
node _T_2230 = eq(_T_2229, asSInt(UInt<1>(0h0)))
node _T_2231 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2232 = cvt(_T_2231)
node _T_2233 = and(_T_2232, asSInt(UInt<13>(0h1000)))
node _T_2234 = asSInt(_T_2233)
node _T_2235 = eq(_T_2234, asSInt(UInt<1>(0h0)))
node _T_2236 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2237 = cvt(_T_2236)
node _T_2238 = and(_T_2237, asSInt(UInt<29>(0h10000000)))
node _T_2239 = asSInt(_T_2238)
node _T_2240 = eq(_T_2239, asSInt(UInt<1>(0h0)))
node _T_2241 = or(_T_2185, _T_2190)
node _T_2242 = or(_T_2241, _T_2195)
node _T_2243 = or(_T_2242, _T_2200)
node _T_2244 = or(_T_2243, _T_2205)
node _T_2245 = or(_T_2244, _T_2210)
node _T_2246 = or(_T_2245, _T_2215)
node _T_2247 = or(_T_2246, _T_2220)
node _T_2248 = or(_T_2247, _T_2225)
node _T_2249 = or(_T_2248, _T_2230)
node _T_2250 = or(_T_2249, _T_2235)
node _T_2251 = or(_T_2250, _T_2240)
node _T_2252 = and(_T_2180, _T_2251)
node _T_2253 = or(UInt<1>(0h0), _T_2252)
node _T_2254 = and(_WIRE_7, _T_2253)
node _T_2255 = asUInt(reset)
node _T_2256 = eq(_T_2255, UInt<1>(0h0))
when _T_2256 :
node _T_2257 = eq(_T_2254, UInt<1>(0h0))
when _T_2257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144
assert(clock, _T_2254, UInt<1>(0h1), "") : assert_144
node _T_2258 = asUInt(reset)
node _T_2259 = eq(_T_2258, UInt<1>(0h0))
when _T_2259 :
node _T_2260 = eq(source_ok_2, UInt<1>(0h0))
when _T_2260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145
node _T_2261 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2262 = asUInt(reset)
node _T_2263 = eq(_T_2262, UInt<1>(0h0))
when _T_2263 :
node _T_2264 = eq(_T_2261, UInt<1>(0h0))
when _T_2264 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146
assert(clock, _T_2261, UInt<1>(0h1), "") : assert_146
node _T_2265 = asUInt(reset)
node _T_2266 = eq(_T_2265, UInt<1>(0h0))
when _T_2266 :
node _T_2267 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147
node _T_2268 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2269 = asUInt(reset)
node _T_2270 = eq(_T_2269, UInt<1>(0h0))
when _T_2270 :
node _T_2271 = eq(_T_2268, UInt<1>(0h0))
when _T_2271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148
assert(clock, _T_2268, UInt<1>(0h1), "") : assert_148
node _T_2272 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2273 = asUInt(reset)
node _T_2274 = eq(_T_2273, UInt<1>(0h0))
when _T_2274 :
node _T_2275 = eq(_T_2272, UInt<1>(0h0))
when _T_2275 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149
assert(clock, _T_2272, UInt<1>(0h1), "") : assert_149
node _T_2276 = eq(io.in.c.bits.opcode, UInt<3>(0h7))
when _T_2276 :
node _T_2277 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2278 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2279 = and(_T_2277, _T_2278)
node _T_2280 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2281 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_2282 = eq(io.in.c.bits.source, UInt<2>(0h2))
node _T_2283 = or(_T_2280, _T_2281)
node _T_2284 = or(_T_2283, _T_2282)
node _T_2285 = and(_T_2279, _T_2284)
node _T_2286 = or(UInt<1>(0h0), _T_2285)
node _T_2287 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_2288 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2289 = cvt(_T_2288)
node _T_2290 = and(_T_2289, asSInt(UInt<14>(0h2000)))
node _T_2291 = asSInt(_T_2290)
node _T_2292 = eq(_T_2291, asSInt(UInt<1>(0h0)))
node _T_2293 = xor(io.in.c.bits.address, UInt<14>(0h2000))
node _T_2294 = cvt(_T_2293)
node _T_2295 = and(_T_2294, asSInt(UInt<11>(0h400)))
node _T_2296 = asSInt(_T_2295)
node _T_2297 = eq(_T_2296, asSInt(UInt<1>(0h0)))
node _T_2298 = xor(io.in.c.bits.address, UInt<14>(0h2400))
node _T_2299 = cvt(_T_2298)
node _T_2300 = and(_T_2299, asSInt(UInt<9>(0h100)))
node _T_2301 = asSInt(_T_2300)
node _T_2302 = eq(_T_2301, asSInt(UInt<1>(0h0)))
node _T_2303 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2304 = cvt(_T_2303)
node _T_2305 = and(_T_2304, asSInt(UInt<13>(0h1000)))
node _T_2306 = asSInt(_T_2305)
node _T_2307 = eq(_T_2306, asSInt(UInt<1>(0h0)))
node _T_2308 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2309 = cvt(_T_2308)
node _T_2310 = and(_T_2309, asSInt(UInt<17>(0h10000)))
node _T_2311 = asSInt(_T_2310)
node _T_2312 = eq(_T_2311, asSInt(UInt<1>(0h0)))
node _T_2313 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2314 = cvt(_T_2313)
node _T_2315 = and(_T_2314, asSInt(UInt<18>(0h2f000)))
node _T_2316 = asSInt(_T_2315)
node _T_2317 = eq(_T_2316, asSInt(UInt<1>(0h0)))
node _T_2318 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2319 = cvt(_T_2318)
node _T_2320 = and(_T_2319, asSInt(UInt<17>(0h10000)))
node _T_2321 = asSInt(_T_2320)
node _T_2322 = eq(_T_2321, asSInt(UInt<1>(0h0)))
node _T_2323 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2324 = cvt(_T_2323)
node _T_2325 = and(_T_2324, asSInt(UInt<13>(0h1000)))
node _T_2326 = asSInt(_T_2325)
node _T_2327 = eq(_T_2326, asSInt(UInt<1>(0h0)))
node _T_2328 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2329 = cvt(_T_2328)
node _T_2330 = and(_T_2329, asSInt(UInt<27>(0h4000000)))
node _T_2331 = asSInt(_T_2330)
node _T_2332 = eq(_T_2331, asSInt(UInt<1>(0h0)))
node _T_2333 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2334 = cvt(_T_2333)
node _T_2335 = and(_T_2334, asSInt(UInt<13>(0h1000)))
node _T_2336 = asSInt(_T_2335)
node _T_2337 = eq(_T_2336, asSInt(UInt<1>(0h0)))
node _T_2338 = or(_T_2292, _T_2297)
node _T_2339 = or(_T_2338, _T_2302)
node _T_2340 = or(_T_2339, _T_2307)
node _T_2341 = or(_T_2340, _T_2312)
node _T_2342 = or(_T_2341, _T_2317)
node _T_2343 = or(_T_2342, _T_2322)
node _T_2344 = or(_T_2343, _T_2327)
node _T_2345 = or(_T_2344, _T_2332)
node _T_2346 = or(_T_2345, _T_2337)
node _T_2347 = and(_T_2287, _T_2346)
node _T_2348 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2349 = or(UInt<1>(0h0), _T_2348)
node _T_2350 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2351 = cvt(_T_2350)
node _T_2352 = and(_T_2351, asSInt(UInt<17>(0h10000)))
node _T_2353 = asSInt(_T_2352)
node _T_2354 = eq(_T_2353, asSInt(UInt<1>(0h0)))
node _T_2355 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2356 = cvt(_T_2355)
node _T_2357 = and(_T_2356, asSInt(UInt<29>(0h10000000)))
node _T_2358 = asSInt(_T_2357)
node _T_2359 = eq(_T_2358, asSInt(UInt<1>(0h0)))
node _T_2360 = or(_T_2354, _T_2359)
node _T_2361 = and(_T_2349, _T_2360)
node _T_2362 = or(UInt<1>(0h0), _T_2347)
node _T_2363 = or(_T_2362, _T_2361)
node _T_2364 = and(_T_2286, _T_2363)
node _T_2365 = asUInt(reset)
node _T_2366 = eq(_T_2365, UInt<1>(0h0))
when _T_2366 :
node _T_2367 = eq(_T_2364, UInt<1>(0h0))
when _T_2367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150
assert(clock, _T_2364, UInt<1>(0h1), "") : assert_150
node _T_2368 = eq(io.in.c.bits.source, UInt<1>(0h0))
node _T_2369 = eq(io.in.c.bits.source, UInt<1>(0h1))
node _T_2370 = eq(io.in.c.bits.source, UInt<2>(0h2))
wire _WIRE_8 : UInt<1>[3]
connect _WIRE_8[0], _T_2368
connect _WIRE_8[1], _T_2369
connect _WIRE_8[2], _T_2370
node _T_2371 = eq(UInt<3>(0h6), io.in.c.bits.size)
node _T_2372 = mux(_WIRE_8[0], _T_2371, UInt<1>(0h0))
node _T_2373 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_2374 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_2375 = or(_T_2372, _T_2373)
node _T_2376 = or(_T_2375, _T_2374)
wire _WIRE_9 : UInt<1>
connect _WIRE_9, _T_2376
node _T_2377 = leq(UInt<1>(0h0), io.in.c.bits.size)
node _T_2378 = leq(io.in.c.bits.size, UInt<4>(0hc))
node _T_2379 = and(_T_2377, _T_2378)
node _T_2380 = or(UInt<1>(0h0), _T_2379)
node _T_2381 = xor(io.in.c.bits.address, UInt<1>(0h0))
node _T_2382 = cvt(_T_2381)
node _T_2383 = and(_T_2382, asSInt(UInt<14>(0h2000)))
node _T_2384 = asSInt(_T_2383)
node _T_2385 = eq(_T_2384, asSInt(UInt<1>(0h0)))
node _T_2386 = xor(io.in.c.bits.address, UInt<14>(0h2000))
node _T_2387 = cvt(_T_2386)
node _T_2388 = and(_T_2387, asSInt(UInt<11>(0h400)))
node _T_2389 = asSInt(_T_2388)
node _T_2390 = eq(_T_2389, asSInt(UInt<1>(0h0)))
node _T_2391 = xor(io.in.c.bits.address, UInt<14>(0h2400))
node _T_2392 = cvt(_T_2391)
node _T_2393 = and(_T_2392, asSInt(UInt<9>(0h100)))
node _T_2394 = asSInt(_T_2393)
node _T_2395 = eq(_T_2394, asSInt(UInt<1>(0h0)))
node _T_2396 = xor(io.in.c.bits.address, UInt<14>(0h3000))
node _T_2397 = cvt(_T_2396)
node _T_2398 = and(_T_2397, asSInt(UInt<13>(0h1000)))
node _T_2399 = asSInt(_T_2398)
node _T_2400 = eq(_T_2399, asSInt(UInt<1>(0h0)))
node _T_2401 = xor(io.in.c.bits.address, UInt<17>(0h10000))
node _T_2402 = cvt(_T_2401)
node _T_2403 = and(_T_2402, asSInt(UInt<17>(0h10000)))
node _T_2404 = asSInt(_T_2403)
node _T_2405 = eq(_T_2404, asSInt(UInt<1>(0h0)))
node _T_2406 = xor(io.in.c.bits.address, UInt<21>(0h100000))
node _T_2407 = cvt(_T_2406)
node _T_2408 = and(_T_2407, asSInt(UInt<18>(0h2f000)))
node _T_2409 = asSInt(_T_2408)
node _T_2410 = eq(_T_2409, asSInt(UInt<1>(0h0)))
node _T_2411 = xor(io.in.c.bits.address, UInt<26>(0h2000000))
node _T_2412 = cvt(_T_2411)
node _T_2413 = and(_T_2412, asSInt(UInt<17>(0h10000)))
node _T_2414 = asSInt(_T_2413)
node _T_2415 = eq(_T_2414, asSInt(UInt<1>(0h0)))
node _T_2416 = xor(io.in.c.bits.address, UInt<26>(0h2010000))
node _T_2417 = cvt(_T_2416)
node _T_2418 = and(_T_2417, asSInt(UInt<13>(0h1000)))
node _T_2419 = asSInt(_T_2418)
node _T_2420 = eq(_T_2419, asSInt(UInt<1>(0h0)))
node _T_2421 = xor(io.in.c.bits.address, UInt<28>(0h8000000))
node _T_2422 = cvt(_T_2421)
node _T_2423 = and(_T_2422, asSInt(UInt<17>(0h10000)))
node _T_2424 = asSInt(_T_2423)
node _T_2425 = eq(_T_2424, asSInt(UInt<1>(0h0)))
node _T_2426 = xor(io.in.c.bits.address, UInt<28>(0hc000000))
node _T_2427 = cvt(_T_2426)
node _T_2428 = and(_T_2427, asSInt(UInt<27>(0h4000000)))
node _T_2429 = asSInt(_T_2428)
node _T_2430 = eq(_T_2429, asSInt(UInt<1>(0h0)))
node _T_2431 = xor(io.in.c.bits.address, UInt<29>(0h10020000))
node _T_2432 = cvt(_T_2431)
node _T_2433 = and(_T_2432, asSInt(UInt<13>(0h1000)))
node _T_2434 = asSInt(_T_2433)
node _T_2435 = eq(_T_2434, asSInt(UInt<1>(0h0)))
node _T_2436 = xor(io.in.c.bits.address, UInt<32>(0h80000000))
node _T_2437 = cvt(_T_2436)
node _T_2438 = and(_T_2437, asSInt(UInt<29>(0h10000000)))
node _T_2439 = asSInt(_T_2438)
node _T_2440 = eq(_T_2439, asSInt(UInt<1>(0h0)))
node _T_2441 = or(_T_2385, _T_2390)
node _T_2442 = or(_T_2441, _T_2395)
node _T_2443 = or(_T_2442, _T_2400)
node _T_2444 = or(_T_2443, _T_2405)
node _T_2445 = or(_T_2444, _T_2410)
node _T_2446 = or(_T_2445, _T_2415)
node _T_2447 = or(_T_2446, _T_2420)
node _T_2448 = or(_T_2447, _T_2425)
node _T_2449 = or(_T_2448, _T_2430)
node _T_2450 = or(_T_2449, _T_2435)
node _T_2451 = or(_T_2450, _T_2440)
node _T_2452 = and(_T_2380, _T_2451)
node _T_2453 = or(UInt<1>(0h0), _T_2452)
node _T_2454 = and(_WIRE_9, _T_2453)
node _T_2455 = asUInt(reset)
node _T_2456 = eq(_T_2455, UInt<1>(0h0))
when _T_2456 :
node _T_2457 = eq(_T_2454, UInt<1>(0h0))
when _T_2457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151
assert(clock, _T_2454, UInt<1>(0h1), "") : assert_151
node _T_2458 = asUInt(reset)
node _T_2459 = eq(_T_2458, UInt<1>(0h0))
when _T_2459 :
node _T_2460 = eq(source_ok_2, UInt<1>(0h0))
when _T_2460 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152
node _T_2461 = geq(io.in.c.bits.size, UInt<2>(0h3))
node _T_2462 = asUInt(reset)
node _T_2463 = eq(_T_2462, UInt<1>(0h0))
when _T_2463 :
node _T_2464 = eq(_T_2461, UInt<1>(0h0))
when _T_2464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153
assert(clock, _T_2461, UInt<1>(0h1), "") : assert_153
node _T_2465 = asUInt(reset)
node _T_2466 = eq(_T_2465, UInt<1>(0h0))
when _T_2466 :
node _T_2467 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154
node _T_2468 = leq(io.in.c.bits.param, UInt<3>(0h5))
node _T_2469 = asUInt(reset)
node _T_2470 = eq(_T_2469, UInt<1>(0h0))
when _T_2470 :
node _T_2471 = eq(_T_2468, UInt<1>(0h0))
when _T_2471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155
assert(clock, _T_2468, UInt<1>(0h1), "") : assert_155
node _T_2472 = eq(io.in.c.bits.opcode, UInt<1>(0h0))
when _T_2472 :
node _T_2473 = asUInt(reset)
node _T_2474 = eq(_T_2473, UInt<1>(0h0))
when _T_2474 :
node _T_2475 = eq(address_ok_1, UInt<1>(0h0))
when _T_2475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156
node _T_2476 = asUInt(reset)
node _T_2477 = eq(_T_2476, UInt<1>(0h0))
when _T_2477 :
node _T_2478 = eq(source_ok_2, UInt<1>(0h0))
when _T_2478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157
node _T_2479 = asUInt(reset)
node _T_2480 = eq(_T_2479, UInt<1>(0h0))
when _T_2480 :
node _T_2481 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158
node _T_2482 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2483 = asUInt(reset)
node _T_2484 = eq(_T_2483, UInt<1>(0h0))
when _T_2484 :
node _T_2485 = eq(_T_2482, UInt<1>(0h0))
when _T_2485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159
assert(clock, _T_2482, UInt<1>(0h1), "") : assert_159
node _T_2486 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2487 = asUInt(reset)
node _T_2488 = eq(_T_2487, UInt<1>(0h0))
when _T_2488 :
node _T_2489 = eq(_T_2486, UInt<1>(0h0))
when _T_2489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160
assert(clock, _T_2486, UInt<1>(0h1), "") : assert_160
node _T_2490 = eq(io.in.c.bits.opcode, UInt<1>(0h1))
when _T_2490 :
node _T_2491 = asUInt(reset)
node _T_2492 = eq(_T_2491, UInt<1>(0h0))
when _T_2492 :
node _T_2493 = eq(address_ok_1, UInt<1>(0h0))
when _T_2493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161
node _T_2494 = asUInt(reset)
node _T_2495 = eq(_T_2494, UInt<1>(0h0))
when _T_2495 :
node _T_2496 = eq(source_ok_2, UInt<1>(0h0))
when _T_2496 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162
node _T_2497 = asUInt(reset)
node _T_2498 = eq(_T_2497, UInt<1>(0h0))
when _T_2498 :
node _T_2499 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2499 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163
node _T_2500 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2501 = asUInt(reset)
node _T_2502 = eq(_T_2501, UInt<1>(0h0))
when _T_2502 :
node _T_2503 = eq(_T_2500, UInt<1>(0h0))
when _T_2503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164
assert(clock, _T_2500, UInt<1>(0h1), "") : assert_164
node _T_2504 = eq(io.in.c.bits.opcode, UInt<2>(0h2))
when _T_2504 :
node _T_2505 = asUInt(reset)
node _T_2506 = eq(_T_2505, UInt<1>(0h0))
when _T_2506 :
node _T_2507 = eq(address_ok_1, UInt<1>(0h0))
when _T_2507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165
assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165
node _T_2508 = asUInt(reset)
node _T_2509 = eq(_T_2508, UInt<1>(0h0))
when _T_2509 :
node _T_2510 = eq(source_ok_2, UInt<1>(0h0))
when _T_2510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166
assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166
node _T_2511 = asUInt(reset)
node _T_2512 = eq(_T_2511, UInt<1>(0h0))
when _T_2512 :
node _T_2513 = eq(is_aligned_2, UInt<1>(0h0))
when _T_2513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167
assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167
node _T_2514 = eq(io.in.c.bits.param, UInt<1>(0h0))
node _T_2515 = asUInt(reset)
node _T_2516 = eq(_T_2515, UInt<1>(0h0))
when _T_2516 :
node _T_2517 = eq(_T_2514, UInt<1>(0h0))
when _T_2517 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168
assert(clock, _T_2514, UInt<1>(0h1), "") : assert_168
node _T_2518 = eq(io.in.c.bits.corrupt, UInt<1>(0h0))
node _T_2519 = asUInt(reset)
node _T_2520 = eq(_T_2519, UInt<1>(0h0))
when _T_2520 :
node _T_2521 = eq(_T_2518, UInt<1>(0h0))
when _T_2521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169
assert(clock, _T_2518, UInt<1>(0h1), "") : assert_169
when io.in.e.valid :
node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8))
node _T_2522 = asUInt(reset)
node _T_2523 = eq(_T_2522, UInt<1>(0h0))
when _T_2523 :
node _T_2524 = eq(sink_ok_1, UInt<1>(0h0))
when _T_2524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170
assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_2525 = eq(a_first, UInt<1>(0h0))
node _T_2526 = and(io.in.a.valid, _T_2525)
when _T_2526 :
node _T_2527 = eq(io.in.a.bits.opcode, opcode)
node _T_2528 = asUInt(reset)
node _T_2529 = eq(_T_2528, UInt<1>(0h0))
when _T_2529 :
node _T_2530 = eq(_T_2527, UInt<1>(0h0))
when _T_2530 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171
assert(clock, _T_2527, UInt<1>(0h1), "") : assert_171
node _T_2531 = eq(io.in.a.bits.param, param)
node _T_2532 = asUInt(reset)
node _T_2533 = eq(_T_2532, UInt<1>(0h0))
when _T_2533 :
node _T_2534 = eq(_T_2531, UInt<1>(0h0))
when _T_2534 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172
assert(clock, _T_2531, UInt<1>(0h1), "") : assert_172
node _T_2535 = eq(io.in.a.bits.size, size)
node _T_2536 = asUInt(reset)
node _T_2537 = eq(_T_2536, UInt<1>(0h0))
when _T_2537 :
node _T_2538 = eq(_T_2535, UInt<1>(0h0))
when _T_2538 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173
assert(clock, _T_2535, UInt<1>(0h1), "") : assert_173
node _T_2539 = eq(io.in.a.bits.source, source)
node _T_2540 = asUInt(reset)
node _T_2541 = eq(_T_2540, UInt<1>(0h0))
when _T_2541 :
node _T_2542 = eq(_T_2539, UInt<1>(0h0))
when _T_2542 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174
assert(clock, _T_2539, UInt<1>(0h1), "") : assert_174
node _T_2543 = eq(io.in.a.bits.address, address)
node _T_2544 = asUInt(reset)
node _T_2545 = eq(_T_2544, UInt<1>(0h0))
when _T_2545 :
node _T_2546 = eq(_T_2543, UInt<1>(0h0))
when _T_2546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175
assert(clock, _T_2543, UInt<1>(0h1), "") : assert_175
node _T_2547 = and(io.in.a.ready, io.in.a.valid)
node _T_2548 = and(_T_2547, a_first)
when _T_2548 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_2549 = eq(d_first, UInt<1>(0h0))
node _T_2550 = and(io.in.d.valid, _T_2549)
when _T_2550 :
node _T_2551 = eq(io.in.d.bits.opcode, opcode_1)
node _T_2552 = asUInt(reset)
node _T_2553 = eq(_T_2552, UInt<1>(0h0))
when _T_2553 :
node _T_2554 = eq(_T_2551, UInt<1>(0h0))
when _T_2554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176
assert(clock, _T_2551, UInt<1>(0h1), "") : assert_176
node _T_2555 = eq(io.in.d.bits.param, param_1)
node _T_2556 = asUInt(reset)
node _T_2557 = eq(_T_2556, UInt<1>(0h0))
when _T_2557 :
node _T_2558 = eq(_T_2555, UInt<1>(0h0))
when _T_2558 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177
assert(clock, _T_2555, UInt<1>(0h1), "") : assert_177
node _T_2559 = eq(io.in.d.bits.size, size_1)
node _T_2560 = asUInt(reset)
node _T_2561 = eq(_T_2560, UInt<1>(0h0))
when _T_2561 :
node _T_2562 = eq(_T_2559, UInt<1>(0h0))
when _T_2562 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178
assert(clock, _T_2559, UInt<1>(0h1), "") : assert_178
node _T_2563 = eq(io.in.d.bits.source, source_1)
node _T_2564 = asUInt(reset)
node _T_2565 = eq(_T_2564, UInt<1>(0h0))
when _T_2565 :
node _T_2566 = eq(_T_2563, UInt<1>(0h0))
when _T_2566 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179
assert(clock, _T_2563, UInt<1>(0h1), "") : assert_179
node _T_2567 = eq(io.in.d.bits.sink, sink)
node _T_2568 = asUInt(reset)
node _T_2569 = eq(_T_2568, UInt<1>(0h0))
when _T_2569 :
node _T_2570 = eq(_T_2567, UInt<1>(0h0))
when _T_2570 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180
assert(clock, _T_2567, UInt<1>(0h1), "") : assert_180
node _T_2571 = eq(io.in.d.bits.denied, denied)
node _T_2572 = asUInt(reset)
node _T_2573 = eq(_T_2572, UInt<1>(0h0))
when _T_2573 :
node _T_2574 = eq(_T_2571, UInt<1>(0h0))
when _T_2574 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181
assert(clock, _T_2571, UInt<1>(0h1), "") : assert_181
node _T_2575 = and(io.in.d.ready, io.in.d.valid)
node _T_2576 = and(_T_2575, d_first)
when _T_2576 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
node _b_first_T = and(io.in.b.ready, io.in.b.valid)
node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size)
node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0)
node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1)
node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3)
node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2)
node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0))
node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0))
regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1))
node b_first_counter1 = tail(_b_first_counter1_T, 1)
node b_first = eq(b_first_counter, UInt<1>(0h0))
node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1))
node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0))
node b_first_last = or(_b_first_last_T, _b_first_last_T_1)
node b_first_done = and(b_first_last, _b_first_T)
node _b_first_count_T = not(b_first_counter1)
node b_first_count = and(b_first_beats1, _b_first_count_T)
when _b_first_T :
node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1)
connect b_first_counter, _b_first_counter_T
reg opcode_2 : UInt, clock
reg param_2 : UInt, clock
reg size_2 : UInt, clock
reg source_2 : UInt, clock
reg address_1 : UInt, clock
node _T_2577 = eq(b_first, UInt<1>(0h0))
node _T_2578 = and(io.in.b.valid, _T_2577)
when _T_2578 :
node _T_2579 = eq(io.in.b.bits.opcode, opcode_2)
node _T_2580 = asUInt(reset)
node _T_2581 = eq(_T_2580, UInt<1>(0h0))
when _T_2581 :
node _T_2582 = eq(_T_2579, UInt<1>(0h0))
when _T_2582 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182
assert(clock, _T_2579, UInt<1>(0h1), "") : assert_182
node _T_2583 = eq(io.in.b.bits.param, param_2)
node _T_2584 = asUInt(reset)
node _T_2585 = eq(_T_2584, UInt<1>(0h0))
when _T_2585 :
node _T_2586 = eq(_T_2583, UInt<1>(0h0))
when _T_2586 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183
assert(clock, _T_2583, UInt<1>(0h1), "") : assert_183
node _T_2587 = eq(io.in.b.bits.size, size_2)
node _T_2588 = asUInt(reset)
node _T_2589 = eq(_T_2588, UInt<1>(0h0))
when _T_2589 :
node _T_2590 = eq(_T_2587, UInt<1>(0h0))
when _T_2590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184
assert(clock, _T_2587, UInt<1>(0h1), "") : assert_184
node _T_2591 = eq(io.in.b.bits.source, source_2)
node _T_2592 = asUInt(reset)
node _T_2593 = eq(_T_2592, UInt<1>(0h0))
when _T_2593 :
node _T_2594 = eq(_T_2591, UInt<1>(0h0))
when _T_2594 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185
assert(clock, _T_2591, UInt<1>(0h1), "") : assert_185
node _T_2595 = eq(io.in.b.bits.address, address_1)
node _T_2596 = asUInt(reset)
node _T_2597 = eq(_T_2596, UInt<1>(0h0))
when _T_2597 :
node _T_2598 = eq(_T_2595, UInt<1>(0h0))
when _T_2598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186
assert(clock, _T_2595, UInt<1>(0h1), "") : assert_186
node _T_2599 = and(io.in.b.ready, io.in.b.valid)
node _T_2600 = and(_T_2599, b_first)
when _T_2600 :
connect opcode_2, io.in.b.bits.opcode
connect param_2, io.in.b.bits.param
connect size_2, io.in.b.bits.size
connect source_2, io.in.b.bits.source
connect address_1, io.in.b.bits.address
node _c_first_T = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
reg opcode_3 : UInt, clock
reg param_3 : UInt, clock
reg size_3 : UInt, clock
reg source_3 : UInt, clock
reg address_2 : UInt, clock
node _T_2601 = eq(c_first, UInt<1>(0h0))
node _T_2602 = and(io.in.c.valid, _T_2601)
when _T_2602 :
node _T_2603 = eq(io.in.c.bits.opcode, opcode_3)
node _T_2604 = asUInt(reset)
node _T_2605 = eq(_T_2604, UInt<1>(0h0))
when _T_2605 :
node _T_2606 = eq(_T_2603, UInt<1>(0h0))
when _T_2606 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187
assert(clock, _T_2603, UInt<1>(0h1), "") : assert_187
node _T_2607 = eq(io.in.c.bits.param, param_3)
node _T_2608 = asUInt(reset)
node _T_2609 = eq(_T_2608, UInt<1>(0h0))
when _T_2609 :
node _T_2610 = eq(_T_2607, UInt<1>(0h0))
when _T_2610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188
assert(clock, _T_2607, UInt<1>(0h1), "") : assert_188
node _T_2611 = eq(io.in.c.bits.size, size_3)
node _T_2612 = asUInt(reset)
node _T_2613 = eq(_T_2612, UInt<1>(0h0))
when _T_2613 :
node _T_2614 = eq(_T_2611, UInt<1>(0h0))
when _T_2614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189
assert(clock, _T_2611, UInt<1>(0h1), "") : assert_189
node _T_2615 = eq(io.in.c.bits.source, source_3)
node _T_2616 = asUInt(reset)
node _T_2617 = eq(_T_2616, UInt<1>(0h0))
when _T_2617 :
node _T_2618 = eq(_T_2615, UInt<1>(0h0))
when _T_2618 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190
assert(clock, _T_2615, UInt<1>(0h1), "") : assert_190
node _T_2619 = eq(io.in.c.bits.address, address_2)
node _T_2620 = asUInt(reset)
node _T_2621 = eq(_T_2620, UInt<1>(0h0))
when _T_2621 :
node _T_2622 = eq(_T_2619, UInt<1>(0h0))
when _T_2622 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191
assert(clock, _T_2619, UInt<1>(0h1), "") : assert_191
node _T_2623 = and(io.in.c.ready, io.in.c.valid)
node _T_2624 = and(_T_2623, c_first)
when _T_2624 :
connect opcode_3, io.in.c.bits.opcode
connect param_3, io.in.c.bits.param
connect size_3, io.in.c.bits.size
connect source_3, io.in.c.bits.source
connect address_2, io.in.c.bits.address
regreset inflight : UInt<3>, clock, reset, UInt<3>(0h0)
regreset inflight_opcodes : UInt<12>, clock, reset, UInt<12>(0h0)
regreset inflight_sizes : UInt<24>, clock, reset, UInt<24>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<3>
connect a_set, UInt<3>(0h0)
wire a_set_wo_ready : UInt<3>
connect a_set_wo_ready, UInt<3>(0h0)
wire a_opcodes_set : UInt<12>
connect a_opcodes_set, UInt<12>(0h0)
wire a_sizes_set : UInt<24>
connect a_sizes_set, UInt<24>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_2625 = and(io.in.a.valid, a_first_1)
node _T_2626 = and(_T_2625, UInt<1>(0h1))
when _T_2626 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_2627 = and(io.in.a.ready, io.in.a.valid)
node _T_2628 = and(_T_2627, a_first_1)
node _T_2629 = and(_T_2628, UInt<1>(0h1))
when _T_2629 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_2630 = dshr(inflight, io.in.a.bits.source)
node _T_2631 = bits(_T_2630, 0, 0)
node _T_2632 = eq(_T_2631, UInt<1>(0h0))
node _T_2633 = asUInt(reset)
node _T_2634 = eq(_T_2633, UInt<1>(0h0))
when _T_2634 :
node _T_2635 = eq(_T_2632, UInt<1>(0h0))
when _T_2635 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192
assert(clock, _T_2632, UInt<1>(0h1), "") : assert_192
wire d_clr : UInt<3>
connect d_clr, UInt<3>(0h0)
wire d_clr_wo_ready : UInt<3>
connect d_clr_wo_ready, UInt<3>(0h0)
wire d_opcodes_clr : UInt<12>
connect d_opcodes_clr, UInt<12>(0h0)
wire d_sizes_clr : UInt<24>
connect d_sizes_clr, UInt<24>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2636 = and(io.in.d.valid, d_first_1)
node _T_2637 = and(_T_2636, UInt<1>(0h1))
node _T_2638 = eq(d_release_ack, UInt<1>(0h0))
node _T_2639 = and(_T_2637, _T_2638)
when _T_2639 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_2640 = and(io.in.d.ready, io.in.d.valid)
node _T_2641 = and(_T_2640, d_first_1)
node _T_2642 = and(_T_2641, UInt<1>(0h1))
node _T_2643 = eq(d_release_ack, UInt<1>(0h0))
node _T_2644 = and(_T_2642, _T_2643)
when _T_2644 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_2645 = and(io.in.d.valid, d_first_1)
node _T_2646 = and(_T_2645, UInt<1>(0h1))
node _T_2647 = eq(d_release_ack, UInt<1>(0h0))
node _T_2648 = and(_T_2646, _T_2647)
when _T_2648 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_2649 = dshr(inflight, io.in.d.bits.source)
node _T_2650 = bits(_T_2649, 0, 0)
node _T_2651 = or(_T_2650, same_cycle_resp)
node _T_2652 = asUInt(reset)
node _T_2653 = eq(_T_2652, UInt<1>(0h0))
when _T_2653 :
node _T_2654 = eq(_T_2651, UInt<1>(0h0))
when _T_2654 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193
assert(clock, _T_2651, UInt<1>(0h1), "") : assert_193
when same_cycle_resp :
node _T_2655 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_2656 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_2657 = or(_T_2655, _T_2656)
node _T_2658 = asUInt(reset)
node _T_2659 = eq(_T_2658, UInt<1>(0h0))
when _T_2659 :
node _T_2660 = eq(_T_2657, UInt<1>(0h0))
when _T_2660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194
assert(clock, _T_2657, UInt<1>(0h1), "") : assert_194
node _T_2661 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_2662 = asUInt(reset)
node _T_2663 = eq(_T_2662, UInt<1>(0h0))
when _T_2663 :
node _T_2664 = eq(_T_2661, UInt<1>(0h0))
when _T_2664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195
assert(clock, _T_2661, UInt<1>(0h1), "") : assert_195
else :
node _T_2665 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_2666 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_2667 = or(_T_2665, _T_2666)
node _T_2668 = asUInt(reset)
node _T_2669 = eq(_T_2668, UInt<1>(0h0))
when _T_2669 :
node _T_2670 = eq(_T_2667, UInt<1>(0h0))
when _T_2670 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196
assert(clock, _T_2667, UInt<1>(0h1), "") : assert_196
node _T_2671 = eq(io.in.d.bits.size, a_size_lookup)
node _T_2672 = asUInt(reset)
node _T_2673 = eq(_T_2672, UInt<1>(0h0))
when _T_2673 :
node _T_2674 = eq(_T_2671, UInt<1>(0h0))
when _T_2674 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197
assert(clock, _T_2671, UInt<1>(0h1), "") : assert_197
node _T_2675 = and(io.in.d.valid, d_first_1)
node _T_2676 = and(_T_2675, a_first_1)
node _T_2677 = and(_T_2676, io.in.a.valid)
node _T_2678 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_2679 = and(_T_2677, _T_2678)
node _T_2680 = eq(d_release_ack, UInt<1>(0h0))
node _T_2681 = and(_T_2679, _T_2680)
when _T_2681 :
node _T_2682 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2683 = or(_T_2682, io.in.a.ready)
node _T_2684 = asUInt(reset)
node _T_2685 = eq(_T_2684, UInt<1>(0h0))
when _T_2685 :
node _T_2686 = eq(_T_2683, UInt<1>(0h0))
when _T_2686 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198
assert(clock, _T_2683, UInt<1>(0h1), "") : assert_198
node _T_2687 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_2688 = orr(a_set_wo_ready)
node _T_2689 = eq(_T_2688, UInt<1>(0h0))
node _T_2690 = or(_T_2687, _T_2689)
node _T_2691 = asUInt(reset)
node _T_2692 = eq(_T_2691, UInt<1>(0h0))
when _T_2692 :
node _T_2693 = eq(_T_2690, UInt<1>(0h0))
when _T_2693 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199
assert(clock, _T_2690, UInt<1>(0h1), "") : assert_199
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_2
node _T_2694 = orr(inflight)
node _T_2695 = eq(_T_2694, UInt<1>(0h0))
node _T_2696 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_2697 = or(_T_2695, _T_2696)
node _T_2698 = lt(watchdog, plusarg_reader.out)
node _T_2699 = or(_T_2697, _T_2698)
node _T_2700 = asUInt(reset)
node _T_2701 = eq(_T_2700, UInt<1>(0h0))
when _T_2701 :
node _T_2702 = eq(_T_2699, UInt<1>(0h0))
when _T_2702 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200
assert(clock, _T_2699, UInt<1>(0h1), "") : assert_200
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_2703 = and(io.in.a.ready, io.in.a.valid)
node _T_2704 = and(io.in.d.ready, io.in.d.valid)
node _T_2705 = or(_T_2703, _T_2704)
when _T_2705 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<3>, clock, reset, UInt<3>(0h0)
regreset inflight_opcodes_1 : UInt<12>, clock, reset, UInt<12>(0h0)
regreset inflight_sizes_1 : UInt<24>, clock, reset, UInt<24>(0h0)
node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid)
node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size)
node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0)
node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4)
node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3)
node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0)
node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0))
regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1))
node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1)
node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0))
node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1))
node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0))
node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3)
node c_first_done_1 = and(c_first_last_1, _c_first_T_1)
node _c_first_count_T_1 = not(c_first_counter1_1)
node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1)
when _c_first_T_1 :
node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1)
connect c_first_counter_1, _c_first_counter_T_1
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<3>
connect c_set, UInt<3>(0h0)
wire c_set_wo_ready : UInt<3>
connect c_set_wo_ready, UInt<3>(0h0)
wire c_opcodes_set : UInt<12>
connect c_opcodes_set, UInt<12>(0h0)
wire c_sizes_set : UInt<24>
connect c_sizes_set, UInt<24>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
node _T_2706 = and(io.in.c.valid, c_first_1)
node _T_2707 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2708 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2709 = and(_T_2707, _T_2708)
node _T_2710 = and(_T_2706, _T_2709)
when _T_2710 :
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
node _T_2711 = and(io.in.c.ready, io.in.c.valid)
node _T_2712 = and(_T_2711, c_first_1)
node _T_2713 = bits(io.in.c.bits.opcode, 2, 2)
node _T_2714 = bits(io.in.c.bits.opcode, 1, 1)
node _T_2715 = and(_T_2713, _T_2714)
node _T_2716 = and(_T_2712, _T_2715)
when _T_2716 :
node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source)
connect c_set, _c_set_T
node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
node _T_2717 = dshr(inflight_1, io.in.c.bits.source)
node _T_2718 = bits(_T_2717, 0, 0)
node _T_2719 = eq(_T_2718, UInt<1>(0h0))
node _T_2720 = asUInt(reset)
node _T_2721 = eq(_T_2720, UInt<1>(0h0))
when _T_2721 :
node _T_2722 = eq(_T_2719, UInt<1>(0h0))
when _T_2722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201
assert(clock, _T_2719, UInt<1>(0h1), "") : assert_201
node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4))
node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<3>
connect d_clr_1, UInt<3>(0h0)
wire d_clr_wo_ready_1 : UInt<3>
connect d_clr_wo_ready_1, UInt<3>(0h0)
wire d_opcodes_clr_1 : UInt<12>
connect d_opcodes_clr_1, UInt<12>(0h0)
wire d_sizes_clr_1 : UInt<24>
connect d_sizes_clr_1, UInt<24>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_2723 = and(io.in.d.valid, d_first_2)
node _T_2724 = and(_T_2723, UInt<1>(0h1))
node _T_2725 = and(_T_2724, d_release_ack_1)
when _T_2725 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_2726 = and(io.in.d.ready, io.in.d.valid)
node _T_2727 = and(_T_2726, d_first_2)
node _T_2728 = and(_T_2727, UInt<1>(0h1))
node _T_2729 = and(_T_2728, d_release_ack_1)
when _T_2729 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_2730 = and(io.in.d.valid, d_first_2)
node _T_2731 = and(_T_2730, UInt<1>(0h1))
node _T_2732 = and(_T_2731, d_release_ack_1)
when _T_2732 :
node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1)
node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_2733 = dshr(inflight_1, io.in.d.bits.source)
node _T_2734 = bits(_T_2733, 0, 0)
node _T_2735 = or(_T_2734, same_cycle_resp_1)
node _T_2736 = asUInt(reset)
node _T_2737 = eq(_T_2736, UInt<1>(0h0))
when _T_2737 :
node _T_2738 = eq(_T_2735, UInt<1>(0h0))
when _T_2738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202
assert(clock, _T_2735, UInt<1>(0h1), "") : assert_202
when same_cycle_resp_1 :
node _T_2739 = eq(io.in.d.bits.size, io.in.c.bits.size)
node _T_2740 = asUInt(reset)
node _T_2741 = eq(_T_2740, UInt<1>(0h0))
when _T_2741 :
node _T_2742 = eq(_T_2739, UInt<1>(0h0))
when _T_2742 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203
assert(clock, _T_2739, UInt<1>(0h1), "") : assert_203
else :
node _T_2743 = eq(io.in.d.bits.size, c_size_lookup)
node _T_2744 = asUInt(reset)
node _T_2745 = eq(_T_2744, UInt<1>(0h0))
when _T_2745 :
node _T_2746 = eq(_T_2743, UInt<1>(0h0))
when _T_2746 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204
assert(clock, _T_2743, UInt<1>(0h1), "") : assert_204
node _T_2747 = and(io.in.d.valid, d_first_2)
node _T_2748 = and(_T_2747, c_first_1)
node _T_2749 = and(_T_2748, io.in.c.valid)
node _T_2750 = eq(io.in.c.bits.source, io.in.d.bits.source)
node _T_2751 = and(_T_2749, _T_2750)
node _T_2752 = and(_T_2751, d_release_ack_1)
node _T_2753 = eq(c_probe_ack, UInt<1>(0h0))
node _T_2754 = and(_T_2752, _T_2753)
when _T_2754 :
node _T_2755 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_2756 = or(_T_2755, io.in.c.ready)
node _T_2757 = asUInt(reset)
node _T_2758 = eq(_T_2757, UInt<1>(0h0))
when _T_2758 :
node _T_2759 = eq(_T_2756, UInt<1>(0h0))
when _T_2759 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205
assert(clock, _T_2756, UInt<1>(0h1), "") : assert_205
node _T_2760 = orr(c_set_wo_ready)
when _T_2760 :
node _T_2761 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_2762 = asUInt(reset)
node _T_2763 = eq(_T_2762, UInt<1>(0h0))
when _T_2763 :
node _T_2764 = eq(_T_2761, UInt<1>(0h0))
when _T_2764 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206
assert(clock, _T_2761, UInt<1>(0h1), "") : assert_206
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_3
node _T_2765 = orr(inflight_1)
node _T_2766 = eq(_T_2765, UInt<1>(0h0))
node _T_2767 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_2768 = or(_T_2766, _T_2767)
node _T_2769 = lt(watchdog_1, plusarg_reader_1.out)
node _T_2770 = or(_T_2768, _T_2769)
node _T_2771 = asUInt(reset)
node _T_2772 = eq(_T_2771, UInt<1>(0h0))
when _T_2772 :
node _T_2773 = eq(_T_2770, UInt<1>(0h0))
when _T_2773 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207
assert(clock, _T_2770, UInt<1>(0h1), "") : assert_207
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
node _T_2774 = and(io.in.c.ready, io.in.c.valid)
node _T_2775 = and(io.in.d.ready, io.in.d.valid)
node _T_2776 = or(_T_2774, _T_2775)
when _T_2776 :
connect watchdog_1, UInt<1>(0h0)
regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0)
node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0)
node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10)
node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3)
node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0))
regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1))
node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1)
node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0))
node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1))
node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0))
node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7)
node d_first_done_3 = and(d_first_last_3, _d_first_T_3)
node _d_first_count_T_3 = not(d_first_counter1_3)
node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3)
when _d_first_T_3 :
node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3)
connect d_first_counter_3, _d_first_counter_T_3
wire d_set : UInt<8>
connect d_set, UInt<8>(0h0)
node _T_2777 = and(io.in.d.ready, io.in.d.valid)
node _T_2778 = and(_T_2777, d_first_3)
node _T_2779 = bits(io.in.d.bits.opcode, 2, 2)
node _T_2780 = bits(io.in.d.bits.opcode, 1, 1)
node _T_2781 = eq(_T_2780, UInt<1>(0h0))
node _T_2782 = and(_T_2779, _T_2781)
node _T_2783 = and(_T_2778, _T_2782)
when _T_2783 :
node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink)
connect d_set, _d_set_T
node _T_2784 = dshr(inflight_2, io.in.d.bits.sink)
node _T_2785 = bits(_T_2784, 0, 0)
node _T_2786 = eq(_T_2785, UInt<1>(0h0))
node _T_2787 = asUInt(reset)
node _T_2788 = eq(_T_2787, UInt<1>(0h0))
when _T_2788 :
node _T_2789 = eq(_T_2786, UInt<1>(0h0))
when _T_2789 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208
assert(clock, _T_2786, UInt<1>(0h1), "") : assert_208
wire e_clr : UInt<8>
connect e_clr, UInt<8>(0h0)
node _T_2790 = and(io.in.e.ready, io.in.e.valid)
node _T_2791 = and(_T_2790, UInt<1>(0h1))
node _T_2792 = and(_T_2791, UInt<1>(0h1))
when _T_2792 :
node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink)
connect e_clr, _e_clr_T
node _T_2793 = or(d_set, inflight_2)
node _T_2794 = dshr(_T_2793, io.in.e.bits.sink)
node _T_2795 = bits(_T_2794, 0, 0)
node _T_2796 = asUInt(reset)
node _T_2797 = eq(_T_2796, UInt<1>(0h0))
when _T_2797 :
node _T_2798 = eq(_T_2795, UInt<1>(0h0))
when _T_2798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209
assert(clock, _T_2795, UInt<1>(0h1), "") : assert_209
node _inflight_T_6 = or(inflight_2, d_set)
node _inflight_T_7 = not(e_clr)
node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7)
connect inflight_2, _inflight_T_8 | module TLMonitor_1( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input io_in_c_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire [26:0] _GEN_0 = {23'h0, io_in_c_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [1:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [1:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [8:0] b_first_counter; // @[Edges.scala:229:27]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35]
reg [8:0] c_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [3:0] size_3; // @[Monitor.scala:517:22]
reg [1:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [2:0] inflight; // @[Monitor.scala:614:27]
reg [11:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [23:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [3:0] _GEN_1 = {2'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [3:0] _GEN_4 = {2'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [2:0] inflight_1; // @[Monitor.scala:726:35]
reg [23:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] c_first_counter_1; // @[Edges.scala:229:27]
wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}]
wire [3:0] _GEN_6 = {2'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
reg [8:0] d_first_counter_3; // @[Edges.scala:229:27]
wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_9 = {5'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35]
wire [7:0] d_set = _GEN_8 ? 8'h1 << _GEN_9 : 8'h0; // @[OneHot.scala:58:35]
wire [7:0] _GEN_10 = {5'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35] |
Generate the Verilog code corresponding to this FIRRTL code module TLError :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_21
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
connect nodeIn, auto.in
inst a_q of Queue1_TLBundleA_a14d64s7k1z4u
connect a_q.clock, clock
connect a_q.reset, reset
connect a_q.io.enq.valid, nodeIn.a.valid
connect a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect a_q.io.enq.bits.data, nodeIn.a.bits.data
connect a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect a_q.io.enq.bits.address, nodeIn.a.bits.address
connect a_q.io.enq.bits.source, nodeIn.a.bits.source
connect a_q.io.enq.bits.size, nodeIn.a.bits.size
connect a_q.io.enq.bits.param, nodeIn.a.bits.param
connect a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, a_q.io.enq.ready
wire da : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
regreset idle : UInt<1>, clock, reset, UInt<1>(0h1)
node _a_last_T = and(a_q.io.deq.ready, a_q.io.deq.valid)
node _a_last_beats1_decode_T = dshl(UInt<12>(0hfff), a_q.io.deq.bits.size)
node _a_last_beats1_decode_T_1 = bits(_a_last_beats1_decode_T, 11, 0)
node _a_last_beats1_decode_T_2 = not(_a_last_beats1_decode_T_1)
node a_last_beats1_decode = shr(_a_last_beats1_decode_T_2, 3)
node _a_last_beats1_opdata_T = bits(a_q.io.deq.bits.opcode, 2, 2)
node a_last_beats1_opdata = eq(_a_last_beats1_opdata_T, UInt<1>(0h0))
node a_last_beats1 = mux(a_last_beats1_opdata, a_last_beats1_decode, UInt<1>(0h0))
regreset a_last_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_last_counter1_T = sub(a_last_counter, UInt<1>(0h1))
node a_last_counter1 = tail(_a_last_counter1_T, 1)
node a_last_first = eq(a_last_counter, UInt<1>(0h0))
node _a_last_last_T = eq(a_last_counter, UInt<1>(0h1))
node _a_last_last_T_1 = eq(a_last_beats1, UInt<1>(0h0))
node a_last = or(_a_last_last_T, _a_last_last_T_1)
node a_last_done = and(a_last, _a_last_T)
node _a_last_count_T = not(a_last_counter1)
node a_last_count = and(a_last_beats1, _a_last_count_T)
when _a_last_T :
node _a_last_counter_T = mux(a_last_first, a_last_beats1, a_last_counter1)
connect a_last_counter, _a_last_counter_T
node _T = and(da.ready, da.valid)
node _r_beats1_decode_T = dshl(UInt<12>(0hfff), da.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 3)
node r_beats1_opdata = bits(da.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node da_first = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node da_last = or(_r_last_T, _r_last_T_1)
node r_3 = and(da_last, _T)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(da_first, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node _T_1 = or(idle, da_first)
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Error.scala:34 assert (idle || da_first) // we only send Grant, never GrantData => simplified flow control below\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _q_io_deq_ready_T = and(da.ready, da_last)
node _q_io_deq_ready_T_1 = and(_q_io_deq_ready_T, idle)
node _q_io_deq_ready_T_2 = eq(a_last, UInt<1>(0h0))
node _q_io_deq_ready_T_3 = or(_q_io_deq_ready_T_1, _q_io_deq_ready_T_2)
connect a_q.io.deq.ready, _q_io_deq_ready_T_3
node _da_valid_T = and(a_q.io.deq.valid, a_last)
node _da_valid_T_1 = and(_da_valid_T, idle)
connect da.valid, _da_valid_T_1
wire _da_bits_opcode_WIRE : UInt<3>[8]
connect _da_bits_opcode_WIRE[0], UInt<1>(0h0)
connect _da_bits_opcode_WIRE[1], UInt<1>(0h0)
connect _da_bits_opcode_WIRE[2], UInt<1>(0h1)
connect _da_bits_opcode_WIRE[3], UInt<1>(0h1)
connect _da_bits_opcode_WIRE[4], UInt<1>(0h1)
connect _da_bits_opcode_WIRE[5], UInt<2>(0h2)
connect _da_bits_opcode_WIRE[6], UInt<3>(0h4)
connect _da_bits_opcode_WIRE[7], UInt<3>(0h4)
connect da.bits.opcode, _da_bits_opcode_WIRE[a_q.io.deq.bits.opcode]
connect da.bits.param, UInt<1>(0h0)
connect da.bits.size, a_q.io.deq.bits.size
connect da.bits.source, a_q.io.deq.bits.source
connect da.bits.sink, UInt<1>(0h0)
connect da.bits.denied, UInt<1>(0h1)
connect da.bits.data, UInt<1>(0h0)
node da_bits_corrupt_opdata = bits(da.bits.opcode, 0, 0)
connect da.bits.corrupt, da_bits_corrupt_opdata
connect nodeIn.d, da
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<14>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_2.bits.sink, UInt<1>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
extmodule plusarg_reader_44 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_45 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module TLError( // @[Error.scala:21:9]
input clock, // @[Error.scala:21:9]
input reset, // @[Error.scala:21:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _a_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _a_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [3:0] _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Error.scala:21:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Error.scala:21:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Error.scala:21:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Error.scala:21:9]
wire [6:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Error.scala:21:9]
wire [13:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Error.scala:21:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Error.scala:21:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Error.scala:21:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Error.scala:21:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Error.scala:21:9]
wire [7:0][2:0] _GEN = '{3'h4, 3'h4, 3'h2, 3'h1, 3'h1, 3'h1, 3'h0, 3'h0};
wire auto_in_d_bits_denied = 1'h1; // @[Error.scala:21:9]
wire nodeIn_d_bits_denied = 1'h1; // @[MixedNode.scala:551:17]
wire da_bits_denied = 1'h1; // @[Error.scala:28:18]
wire [1:0] auto_in_d_bits_param = 2'h0; // @[Error.scala:21:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] da_bits_param = 2'h0; // @[Error.scala:28:18]
wire auto_in_d_bits_sink = 1'h0; // @[Error.scala:21:9]
wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire da_bits_sink = 1'h0; // @[Error.scala:28:18]
wire [63:0] auto_in_d_bits_data = 64'h0; // @[Error.scala:21:9]
wire [63:0] nodeIn_d_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] da_bits_data = 64'h0; // @[Error.scala:28:18]
wire [2:0] _da_bits_opcode_WIRE_6 = 3'h4; // @[Bundles.scala:47:27]
wire [2:0] _da_bits_opcode_WIRE_7 = 3'h4; // @[Bundles.scala:47:27]
wire [2:0] _da_bits_opcode_WIRE_5 = 3'h2; // @[Bundles.scala:47:27]
wire [2:0] _da_bits_opcode_WIRE_2 = 3'h1; // @[Bundles.scala:47:27]
wire [2:0] _da_bits_opcode_WIRE_3 = 3'h1; // @[Bundles.scala:47:27]
wire [2:0] _da_bits_opcode_WIRE_4 = 3'h1; // @[Bundles.scala:47:27]
wire [2:0] _da_bits_opcode_WIRE_0 = 3'h0; // @[Bundles.scala:47:27]
wire [2:0] _da_bits_opcode_WIRE_1 = 3'h0; // @[Bundles.scala:47:27]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Error.scala:21:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Error.scala:21:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Error.scala:21:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Error.scala:21:9]
wire [6:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Error.scala:21:9]
wire [13:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Error.scala:21:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Error.scala:21:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Error.scala:21:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Error.scala:21:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Error.scala:21:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire auto_in_a_ready_0; // @[Error.scala:21:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Error.scala:21:9]
wire [3:0] auto_in_d_bits_size_0; // @[Error.scala:21:9]
wire [6:0] auto_in_d_bits_source_0; // @[Error.scala:21:9]
wire auto_in_d_bits_corrupt_0; // @[Error.scala:21:9]
wire auto_in_d_valid_0; // @[Error.scala:21:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Error.scala:21:9]
wire da_ready = nodeIn_d_ready; // @[Error.scala:28:18]
wire da_valid; // @[Error.scala:28:18]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Error.scala:21:9]
wire [2:0] da_bits_opcode; // @[Error.scala:28:18]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Error.scala:21:9]
wire [3:0] da_bits_size; // @[Error.scala:28:18]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Error.scala:21:9]
wire [6:0] da_bits_source; // @[Error.scala:28:18]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Error.scala:21:9]
wire da_bits_corrupt; // @[Error.scala:28:18]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Error.scala:21:9]
wire _da_valid_T_1; // @[Error.scala:36:35]
assign nodeIn_d_valid = da_valid; // @[Error.scala:28:18]
assign nodeIn_d_bits_opcode = da_bits_opcode; // @[Error.scala:28:18]
assign nodeIn_d_bits_size = da_bits_size; // @[Error.scala:28:18]
assign nodeIn_d_bits_source = da_bits_source; // @[Error.scala:28:18]
wire da_bits_corrupt_opdata; // @[Edges.scala:106:36]
assign nodeIn_d_bits_corrupt = da_bits_corrupt; // @[Error.scala:28:18]
wire _q_io_deq_ready_T_3; // @[Error.scala:35:46]
wire _a_last_T = _q_io_deq_ready_T_3 & _a_q_io_deq_valid; // @[Decoupled.scala:51:35, :362:21]
wire [26:0] _a_last_beats1_decode_T = 27'hFFF << _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [11:0] _a_last_beats1_decode_T_1 = _a_last_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_last_beats1_decode_T_2 = ~_a_last_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_last_beats1_decode = _a_last_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_last_beats1_opdata_T = _a_q_io_deq_bits_opcode[2]; // @[Decoupled.scala:362:21]
wire a_last_beats1_opdata = ~_a_last_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_last_beats1 = a_last_beats1_opdata ? a_last_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_last_counter; // @[Edges.scala:229:27]
wire [9:0] _a_last_counter1_T = {1'h0, a_last_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_last_counter1 = _a_last_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_last_first = a_last_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_last_last_T = a_last_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_last_last_T_1 = a_last_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_last = _a_last_last_T | _a_last_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_last_done = a_last & _a_last_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_last_count_T = ~a_last_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_last_count = a_last_beats1 & _a_last_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_last_counter_T = a_last_first ? a_last_beats1 : a_last_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _T = da_ready & da_valid; // @[Decoupled.scala:51:35]
wire [26:0] _r_beats1_decode_T = 27'hFFF << da_bits_size; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire r_beats1_opdata = da_bits_opcode[0]; // @[Edges.scala:106:36]
assign da_bits_corrupt_opdata = da_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] r_counter; // @[Edges.scala:229:27]
wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28]
wire da_first = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire da_last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire r_3 = da_last & _T; // @[Decoupled.scala:51:35]
wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _r_counter_T = da_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire _q_io_deq_ready_T = da_ready & da_last; // @[Edges.scala:232:33]
wire _q_io_deq_ready_T_1 = _q_io_deq_ready_T; // @[Error.scala:35:{26,37}]
wire _q_io_deq_ready_T_2 = ~a_last; // @[Edges.scala:232:33]
assign _q_io_deq_ready_T_3 = _q_io_deq_ready_T_1 | _q_io_deq_ready_T_2; // @[Error.scala:35:{37,46,49}]
wire _da_valid_T = _a_q_io_deq_valid & a_last; // @[Decoupled.scala:362:21]
assign _da_valid_T_1 = _da_valid_T; // @[Error.scala:36:{25,35}]
assign da_valid = _da_valid_T_1; // @[Error.scala:28:18, :36:35]
assign da_bits_opcode = _GEN[_a_q_io_deq_bits_opcode]; // @[Decoupled.scala:362:21]
assign da_bits_corrupt = da_bits_corrupt_opdata; // @[Edges.scala:106:36]
always @(posedge clock) begin // @[Error.scala:21:9]
if (reset) begin // @[Error.scala:21:9]
a_last_counter <= 9'h0; // @[Edges.scala:229:27]
r_counter <= 9'h0; // @[Edges.scala:229:27]
end
else begin // @[Error.scala:21:9]
if (_a_last_T) // @[Decoupled.scala:51:35]
a_last_counter <= _a_last_counter_T; // @[Edges.scala:229:27, :236:21]
if (_T) // @[Decoupled.scala:51:35]
r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21]
end
always @(posedge)
TLMonitor_21 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue1_TLBundleA_a14d64s7k1z4u a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (_q_io_deq_ready_T_3), // @[Error.scala:35:46]
.io_deq_valid (_a_q_io_deq_valid),
.io_deq_bits_opcode (_a_q_io_deq_bits_opcode),
.io_deq_bits_size (_a_q_io_deq_bits_size),
.io_deq_bits_source (da_bits_source)
); // @[Decoupled.scala:362:21]
assign da_bits_size = _a_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Error.scala:21:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Error.scala:21:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Error.scala:21:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Error.scala:21:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Error.scala:21:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Error.scala:21:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_1 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}}
inst input_buffer of InputBuffer_1
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
connect input_buffer.io.deq[3].ready, UInt<1>(0h0)
connect input_buffer.io.deq[4].ready, UInt<1>(0h0)
connect input_buffer.io.deq[5].ready, UInt<1>(0h0)
connect input_buffer.io.deq[6].ready, UInt<1>(0h0)
connect input_buffer.io.deq[7].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter8_RouteComputerReq_1
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<1>(0h1))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1)
node _T_10 = eq(UInt<1>(0h1), io.in.flit[0].bits.flow.egress_node_id)
when _T_10 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
connect route_arbiter.io.in[0].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[0].bits.flow.egress_node_id
invalidate route_arbiter.io.in[0].bits.flow.egress_node
invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[0].bits.flow.ingress_node
invalidate route_arbiter.io.in[0].bits.flow.vnet_id
invalidate route_arbiter.io.in[0].bits.src_virt_id
node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1))
connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T
connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id
connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node
connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id
connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node
connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id
connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1)
node _T_11 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_11 :
connect states[1].g, UInt<3>(0h2)
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_12 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_12 :
connect states[2].g, UInt<3>(0h2)
node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1))
connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T
connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id
connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node
connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id
connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node
connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id
connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3)
node _T_13 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid)
when _T_13 :
connect states[3].g, UInt<3>(0h2)
node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1))
connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T
connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id
connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node
connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id
connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node
connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id
connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4)
node _T_14 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid)
when _T_14 :
connect states[4].g, UInt<3>(0h2)
node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1))
connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T
connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id
connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node
connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id
connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node
connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id
connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5)
node _T_15 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid)
when _T_15 :
connect states[5].g, UInt<3>(0h2)
node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1))
connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T
connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id
connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node
connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id
connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node
connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id
connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6)
node _T_16 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid)
when _T_16 :
connect states[6].g, UInt<3>(0h2)
node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1))
connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T
connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id
connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node
connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id
connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node
connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id
connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7)
node _T_17 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid)
when _T_17 :
connect states[7].g, UInt<3>(0h2)
node _T_18 = and(io.router_req.ready, io.router_req.valid)
when _T_18 :
node _T_19 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_19, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_23 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_23 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_24 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_24 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_25 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_25 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_26 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id)
when _T_26 :
connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_27 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id)
when _T_27 :
connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_28 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id)
when _T_28 :
connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_29 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id)
when _T_29 :
connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2`
node _T_30 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id)
when _T_30 :
connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2`
regreset mask : UInt<8>, clock, reset, UInt<8>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}[8]
wire vcalloc_vals : UInt<1>[8]
node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo)
node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo)
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo)
node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2])
node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1)
node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4])
node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6])
node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1)
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1)
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6)
node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7)
node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8)
node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9)
node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10)
node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11)
node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12)
node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13)
node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14)
node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15)
node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0))
node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21)
node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22)
node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23)
node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24)
node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25)
node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26)
node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27)
node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28)
node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29)
node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30)
node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31)
node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32)
node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33)
node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35)
node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_31 = and(io.router_req.ready, io.router_req.valid)
when _T_31 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_32 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_33 = or(_T_32, vcalloc_vals[2])
node _T_34 = or(_T_33, vcalloc_vals[3])
node _T_35 = or(_T_34, vcalloc_vals[4])
node _T_36 = or(_T_35, vcalloc_vals[5])
node _T_37 = or(_T_36, vcalloc_vals[6])
node _T_38 = or(_T_37, vcalloc_vals[7])
when _T_38 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = not(UInt<4>(0h0))
node _mask_T_7 = not(UInt<5>(0h0))
node _mask_T_8 = not(UInt<6>(0h0))
node _mask_T_9 = not(UInt<7>(0h0))
node _mask_T_10 = not(UInt<8>(0h0))
node _mask_T_11 = bits(vcalloc_sel, 0, 0)
node _mask_T_12 = bits(vcalloc_sel, 1, 1)
node _mask_T_13 = bits(vcalloc_sel, 2, 2)
node _mask_T_14 = bits(vcalloc_sel, 3, 3)
node _mask_T_15 = bits(vcalloc_sel, 4, 4)
node _mask_T_16 = bits(vcalloc_sel, 5, 5)
node _mask_T_17 = bits(vcalloc_sel, 6, 6)
node _mask_T_18 = bits(vcalloc_sel, 7, 7)
node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0))
node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0))
node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0))
node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0))
node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0))
node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0))
node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0))
node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0))
node _mask_T_27 = or(_mask_T_19, _mask_T_20)
node _mask_T_28 = or(_mask_T_27, _mask_T_21)
node _mask_T_29 = or(_mask_T_28, _mask_T_22)
node _mask_T_30 = or(_mask_T_29, _mask_T_23)
node _mask_T_31 = or(_mask_T_30, _mask_T_24)
node _mask_T_32 = or(_mask_T_31, _mask_T_25)
node _mask_T_33 = or(_mask_T_32, _mask_T_26)
wire _mask_WIRE : UInt<8>
connect _mask_WIRE, _mask_T_33
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3])
node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4])
node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5])
node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6])
node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3)
node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4)
node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5)
node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6)
node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8]
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10)
node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11)
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12)
node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13)
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25)
node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26)
node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27)
node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28)
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40)
node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41)
node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42)
node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43)
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55)
node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56)
node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57)
node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58)
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70)
node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71)
node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72)
node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73)
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82
connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84)
node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85)
node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86)
node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87)
node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88)
node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89)
node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97
connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99)
node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100)
node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101)
node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102)
node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103)
node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104)
node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112
connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114)
node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115)
node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116)
node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117)
node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118)
node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119)
node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127
connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[1]
node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129)
node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130)
node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131)
node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132)
node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133)
node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134)
node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142
connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>[1]
node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144)
node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145)
node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146)
node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147)
node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148)
node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149)
node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150)
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_157
connect _io_vcalloc_req_bits_WIRE_13[0], _io_vcalloc_req_bits_WIRE_14
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_13
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159)
node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160)
node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161)
node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162)
node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163)
node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164)
node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_172
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_15
wire _io_vcalloc_req_bits_WIRE_16 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174)
node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175)
node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176)
node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177)
node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178)
node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179)
node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180)
wire _io_vcalloc_req_bits_WIRE_17 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_187
connect _io_vcalloc_req_bits_WIRE_16.egress_node_id, _io_vcalloc_req_bits_WIRE_17
node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189)
node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190)
node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191)
node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192)
node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193)
node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194)
node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_202
connect _io_vcalloc_req_bits_WIRE_16.egress_node, _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204)
node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205)
node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206)
node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207)
node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208)
node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209)
node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_217
connect _io_vcalloc_req_bits_WIRE_16.ingress_node_id, _io_vcalloc_req_bits_WIRE_19
node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219)
node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220)
node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221)
node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222)
node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223)
node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224)
node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225)
wire _io_vcalloc_req_bits_WIRE_20 : UInt<5>
connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_232
connect _io_vcalloc_req_bits_WIRE_16.ingress_node, _io_vcalloc_req_bits_WIRE_20
node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234)
node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235)
node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236)
node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237)
node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238)
node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239)
node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_247
connect _io_vcalloc_req_bits_WIRE_16.vnet_id, _io_vcalloc_req_bits_WIRE_21
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_16
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
connect vcalloc_vals[0], UInt<1>(0h0)
invalidate vcalloc_reqs[0].vc_sel.`0`[0]
invalidate vcalloc_reqs[0].vc_sel.`0`[1]
invalidate vcalloc_reqs[0].vc_sel.`0`[2]
invalidate vcalloc_reqs[0].vc_sel.`0`[3]
invalidate vcalloc_reqs[0].vc_sel.`0`[4]
invalidate vcalloc_reqs[0].vc_sel.`0`[5]
invalidate vcalloc_reqs[0].vc_sel.`0`[6]
invalidate vcalloc_reqs[0].vc_sel.`0`[7]
invalidate vcalloc_reqs[0].vc_sel.`1`[0]
invalidate vcalloc_reqs[0].vc_sel.`2`[0]
invalidate vcalloc_reqs[0].in_vc
invalidate vcalloc_reqs[0].flow.egress_node_id
invalidate vcalloc_reqs[0].flow.egress_node
invalidate vcalloc_reqs[0].flow.ingress_node_id
invalidate vcalloc_reqs[0].flow.ingress_node
invalidate vcalloc_reqs[0].flow.vnet_id
node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2))
node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1)
connect vcalloc_vals[1], _vcalloc_vals_1_T_2
connect vcalloc_reqs[1].in_vc, UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1`
connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2`
connect vcalloc_reqs[1].flow, states[1].flow
node _T_39 = bits(vcalloc_sel, 1, 1)
node _T_40 = and(vcalloc_vals[1], _T_39)
node _T_41 = and(_T_40, io.vcalloc_req.ready)
when _T_41 :
connect states[1].g, UInt<3>(0h3)
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_42 = bits(vcalloc_sel, 2, 2)
node _T_43 = and(vcalloc_vals[2], _T_42)
node _T_44 = and(_T_43, io.vcalloc_req.ready)
when _T_44 :
connect states[2].g, UInt<3>(0h3)
node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2))
node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1)
connect vcalloc_vals[3], _vcalloc_vals_3_T_2
connect vcalloc_reqs[3].in_vc, UInt<2>(0h3)
connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0`
connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1`
connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2`
connect vcalloc_reqs[3].flow, states[3].flow
node _T_45 = bits(vcalloc_sel, 3, 3)
node _T_46 = and(vcalloc_vals[3], _T_45)
node _T_47 = and(_T_46, io.vcalloc_req.ready)
when _T_47 :
connect states[3].g, UInt<3>(0h3)
node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2))
node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1)
connect vcalloc_vals[4], _vcalloc_vals_4_T_2
connect vcalloc_reqs[4].in_vc, UInt<3>(0h4)
connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0`
connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1`
connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2`
connect vcalloc_reqs[4].flow, states[4].flow
node _T_48 = bits(vcalloc_sel, 4, 4)
node _T_49 = and(vcalloc_vals[4], _T_48)
node _T_50 = and(_T_49, io.vcalloc_req.ready)
when _T_50 :
connect states[4].g, UInt<3>(0h3)
node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2))
node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1)
connect vcalloc_vals[5], _vcalloc_vals_5_T_2
connect vcalloc_reqs[5].in_vc, UInt<3>(0h5)
connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0`
connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1`
connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2`
connect vcalloc_reqs[5].flow, states[5].flow
node _T_51 = bits(vcalloc_sel, 5, 5)
node _T_52 = and(vcalloc_vals[5], _T_51)
node _T_53 = and(_T_52, io.vcalloc_req.ready)
when _T_53 :
connect states[5].g, UInt<3>(0h3)
node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2))
node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1)
connect vcalloc_vals[6], _vcalloc_vals_6_T_2
connect vcalloc_reqs[6].in_vc, UInt<3>(0h6)
connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0`
connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1`
connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2`
connect vcalloc_reqs[6].flow, states[6].flow
node _T_54 = bits(vcalloc_sel, 6, 6)
node _T_55 = and(vcalloc_vals[6], _T_54)
node _T_56 = and(_T_55, io.vcalloc_req.ready)
when _T_56 :
connect states[6].g, UInt<3>(0h3)
node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2))
node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1)
connect vcalloc_vals[7], _vcalloc_vals_7_T_2
connect vcalloc_reqs[7].in_vc, UInt<3>(0h7)
connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0`
connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1`
connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2`
connect vcalloc_reqs[7].flow, states[7].flow
node _T_57 = bits(vcalloc_sel, 7, 7)
node _T_58 = and(vcalloc_vals[7], _T_57)
node _T_59 = and(_T_58, io.vcalloc_req.ready)
when _T_59 :
connect states[7].g, UInt<3>(0h3)
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3])
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3)
node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0)
node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5])
node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0)
node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7])
node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0)
node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9)
node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0)
node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11)
node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0)
node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready)
node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_15
node _T_60 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_60 :
node _T_61 = bits(vcalloc_sel, 0, 0)
when _T_61 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].g, UInt<3>(0h3)
node _T_62 = eq(states[0].g, UInt<3>(0h2))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3
assert(clock, _T_62, UInt<1>(0h1), "") : assert_3
node _T_66 = bits(vcalloc_sel, 1, 1)
when _T_66 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].g, UInt<3>(0h3)
node _T_67 = eq(states[1].g, UInt<3>(0h2))
node _T_68 = asUInt(reset)
node _T_69 = eq(_T_68, UInt<1>(0h0))
when _T_69 :
node _T_70 = eq(_T_67, UInt<1>(0h0))
when _T_70 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4
assert(clock, _T_67, UInt<1>(0h1), "") : assert_4
node _T_71 = bits(vcalloc_sel, 2, 2)
when _T_71 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].g, UInt<3>(0h3)
node _T_72 = eq(states[2].g, UInt<3>(0h2))
node _T_73 = asUInt(reset)
node _T_74 = eq(_T_73, UInt<1>(0h0))
when _T_74 :
node _T_75 = eq(_T_72, UInt<1>(0h0))
when _T_75 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5
assert(clock, _T_72, UInt<1>(0h1), "") : assert_5
node _T_76 = bits(vcalloc_sel, 3, 3)
when _T_76 :
connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[3].g, UInt<3>(0h3)
node _T_77 = eq(states[3].g, UInt<3>(0h2))
node _T_78 = asUInt(reset)
node _T_79 = eq(_T_78, UInt<1>(0h0))
when _T_79 :
node _T_80 = eq(_T_77, UInt<1>(0h0))
when _T_80 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6
assert(clock, _T_77, UInt<1>(0h1), "") : assert_6
node _T_81 = bits(vcalloc_sel, 4, 4)
when _T_81 :
connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[4].g, UInt<3>(0h3)
node _T_82 = eq(states[4].g, UInt<3>(0h2))
node _T_83 = asUInt(reset)
node _T_84 = eq(_T_83, UInt<1>(0h0))
when _T_84 :
node _T_85 = eq(_T_82, UInt<1>(0h0))
when _T_85 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7
assert(clock, _T_82, UInt<1>(0h1), "") : assert_7
node _T_86 = bits(vcalloc_sel, 5, 5)
when _T_86 :
connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[5].g, UInt<3>(0h3)
node _T_87 = eq(states[5].g, UInt<3>(0h2))
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8
assert(clock, _T_87, UInt<1>(0h1), "") : assert_8
node _T_91 = bits(vcalloc_sel, 6, 6)
when _T_91 :
connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[6].g, UInt<3>(0h3)
node _T_92 = eq(states[6].g, UInt<3>(0h2))
node _T_93 = asUInt(reset)
node _T_94 = eq(_T_93, UInt<1>(0h0))
when _T_94 :
node _T_95 = eq(_T_92, UInt<1>(0h0))
when _T_95 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9
assert(clock, _T_92, UInt<1>(0h1), "") : assert_9
node _T_96 = bits(vcalloc_sel, 7, 7)
when _T_96 :
connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[7].g, UInt<3>(0h3)
node _T_97 = eq(states[7].g, UInt<3>(0h2))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10
assert(clock, _T_97, UInt<1>(0h1), "") : assert_10
inst salloc_arb of SwitchArbiter_4
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
connect salloc_arb.io.in[0].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[0].bits.tail
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0]
node credit_available_lo_lo = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0])
node credit_available_lo_hi = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2])
node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo)
node credit_available_hi_lo = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4])
node credit_available_hi_hi = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6])
node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo)
node _credit_available_T = cat(credit_available_hi, credit_available_lo)
node credit_available_hi_1 = cat(states[1].vc_sel.`2`[0], states[1].vc_sel.`1`[0])
node _credit_available_T_1 = cat(credit_available_hi_1, _credit_available_T)
node credit_available_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1)
node credit_available_hi_lo_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_1 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_2 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1)
node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_1)
node credit_available_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0])
node _credit_available_T_3 = cat(credit_available_hi_3, _credit_available_T_2)
node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3)
node credit_available = neq(_credit_available_T_4, UInt<1>(0h0))
node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3))
node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available)
node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid)
connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2
connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0]
connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail
node _T_101 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid)
node _T_102 = and(_T_101, input_buffer.io.deq[1].bits.tail)
when _T_102 :
connect states[1].g, UInt<3>(0h0)
connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready
node credit_available_lo_lo_2 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0])
node credit_available_lo_hi_2 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2])
node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2)
node credit_available_hi_lo_2 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4])
node credit_available_hi_hi_2 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6])
node credit_available_hi_4 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2)
node _credit_available_T_5 = cat(credit_available_hi_4, credit_available_lo_2)
node credit_available_hi_5 = cat(states[2].vc_sel.`2`[0], states[2].vc_sel.`1`[0])
node _credit_available_T_6 = cat(credit_available_hi_5, _credit_available_T_5)
node credit_available_lo_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_3 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3)
node credit_available_hi_lo_3 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_3 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_6 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3)
node _credit_available_T_7 = cat(credit_available_hi_6, credit_available_lo_3)
node credit_available_hi_7 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0])
node _credit_available_T_8 = cat(credit_available_hi_7, _credit_available_T_7)
node _credit_available_T_9 = and(_credit_available_T_6, _credit_available_T_8)
node credit_available_1 = neq(_credit_available_T_9, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_103 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_104 = and(_T_103, input_buffer.io.deq[2].bits.tail)
when _T_104 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node credit_available_lo_lo_4 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0])
node credit_available_lo_hi_4 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2])
node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4)
node credit_available_hi_lo_4 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4])
node credit_available_hi_hi_4 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6])
node credit_available_hi_8 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4)
node _credit_available_T_10 = cat(credit_available_hi_8, credit_available_lo_4)
node credit_available_hi_9 = cat(states[3].vc_sel.`2`[0], states[3].vc_sel.`1`[0])
node _credit_available_T_11 = cat(credit_available_hi_9, _credit_available_T_10)
node credit_available_lo_lo_5 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_5 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_5 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5)
node credit_available_hi_lo_5 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_5 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_10 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5)
node _credit_available_T_12 = cat(credit_available_hi_10, credit_available_lo_5)
node credit_available_hi_11 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0])
node _credit_available_T_13 = cat(credit_available_hi_11, _credit_available_T_12)
node _credit_available_T_14 = and(_credit_available_T_11, _credit_available_T_13)
node credit_available_2 = neq(_credit_available_T_14, UInt<1>(0h0))
node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3))
node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_2)
node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid)
connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2
connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6]
connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7]
connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0]
connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0]
connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail
node _T_105 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid)
node _T_106 = and(_T_105, input_buffer.io.deq[3].bits.tail)
when _T_106 :
connect states[3].g, UInt<3>(0h0)
connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready
node credit_available_lo_lo_6 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0])
node credit_available_lo_hi_6 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2])
node credit_available_lo_6 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6)
node credit_available_hi_lo_6 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4])
node credit_available_hi_hi_6 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6])
node credit_available_hi_12 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6)
node _credit_available_T_15 = cat(credit_available_hi_12, credit_available_lo_6)
node credit_available_hi_13 = cat(states[4].vc_sel.`2`[0], states[4].vc_sel.`1`[0])
node _credit_available_T_16 = cat(credit_available_hi_13, _credit_available_T_15)
node credit_available_lo_lo_7 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_7 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_7 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7)
node credit_available_hi_lo_7 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_7 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_14 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7)
node _credit_available_T_17 = cat(credit_available_hi_14, credit_available_lo_7)
node credit_available_hi_15 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0])
node _credit_available_T_18 = cat(credit_available_hi_15, _credit_available_T_17)
node _credit_available_T_19 = and(_credit_available_T_16, _credit_available_T_18)
node credit_available_3 = neq(_credit_available_T_19, UInt<1>(0h0))
node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3))
node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_3)
node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid)
connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2
connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6]
connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7]
connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0]
connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0]
connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail
node _T_107 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid)
node _T_108 = and(_T_107, input_buffer.io.deq[4].bits.tail)
when _T_108 :
connect states[4].g, UInt<3>(0h0)
connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready
node credit_available_lo_lo_8 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0])
node credit_available_lo_hi_8 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2])
node credit_available_lo_8 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8)
node credit_available_hi_lo_8 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4])
node credit_available_hi_hi_8 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6])
node credit_available_hi_16 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8)
node _credit_available_T_20 = cat(credit_available_hi_16, credit_available_lo_8)
node credit_available_hi_17 = cat(states[5].vc_sel.`2`[0], states[5].vc_sel.`1`[0])
node _credit_available_T_21 = cat(credit_available_hi_17, _credit_available_T_20)
node credit_available_lo_lo_9 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_9 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_9 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9)
node credit_available_hi_lo_9 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_9 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_18 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9)
node _credit_available_T_22 = cat(credit_available_hi_18, credit_available_lo_9)
node credit_available_hi_19 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0])
node _credit_available_T_23 = cat(credit_available_hi_19, _credit_available_T_22)
node _credit_available_T_24 = and(_credit_available_T_21, _credit_available_T_23)
node credit_available_4 = neq(_credit_available_T_24, UInt<1>(0h0))
node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3))
node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_4)
node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid)
connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2
connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6]
connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7]
connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0]
connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0]
connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail
node _T_109 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid)
node _T_110 = and(_T_109, input_buffer.io.deq[5].bits.tail)
when _T_110 :
connect states[5].g, UInt<3>(0h0)
connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready
node credit_available_lo_lo_10 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0])
node credit_available_lo_hi_10 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2])
node credit_available_lo_10 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10)
node credit_available_hi_lo_10 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4])
node credit_available_hi_hi_10 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6])
node credit_available_hi_20 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10)
node _credit_available_T_25 = cat(credit_available_hi_20, credit_available_lo_10)
node credit_available_hi_21 = cat(states[6].vc_sel.`2`[0], states[6].vc_sel.`1`[0])
node _credit_available_T_26 = cat(credit_available_hi_21, _credit_available_T_25)
node credit_available_lo_lo_11 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_11 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_11 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11)
node credit_available_hi_lo_11 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_11 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_22 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11)
node _credit_available_T_27 = cat(credit_available_hi_22, credit_available_lo_11)
node credit_available_hi_23 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0])
node _credit_available_T_28 = cat(credit_available_hi_23, _credit_available_T_27)
node _credit_available_T_29 = and(_credit_available_T_26, _credit_available_T_28)
node credit_available_5 = neq(_credit_available_T_29, UInt<1>(0h0))
node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3))
node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_5)
node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid)
connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2
connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6]
connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7]
connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0]
connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0]
connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail
node _T_111 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid)
node _T_112 = and(_T_111, input_buffer.io.deq[6].bits.tail)
when _T_112 :
connect states[6].g, UInt<3>(0h0)
connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready
node credit_available_lo_lo_12 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0])
node credit_available_lo_hi_12 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2])
node credit_available_lo_12 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12)
node credit_available_hi_lo_12 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4])
node credit_available_hi_hi_12 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6])
node credit_available_hi_24 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12)
node _credit_available_T_30 = cat(credit_available_hi_24, credit_available_lo_12)
node credit_available_hi_25 = cat(states[7].vc_sel.`2`[0], states[7].vc_sel.`1`[0])
node _credit_available_T_31 = cat(credit_available_hi_25, _credit_available_T_30)
node credit_available_lo_lo_13 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node credit_available_lo_hi_13 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node credit_available_lo_13 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13)
node credit_available_hi_lo_13 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node credit_available_hi_hi_13 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node credit_available_hi_26 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13)
node _credit_available_T_32 = cat(credit_available_hi_26, credit_available_lo_13)
node credit_available_hi_27 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0])
node _credit_available_T_33 = cat(credit_available_hi_27, _credit_available_T_32)
node _credit_available_T_34 = and(_credit_available_T_31, _credit_available_T_33)
node credit_available_6 = neq(_credit_available_T_34, UInt<1>(0h0))
node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3))
node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_6)
node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid)
connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2
connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6]
connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7]
connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0]
connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0]
connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail
node _T_113 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid)
node _T_114 = and(_T_113, input_buffer.io.deq[7].bits.tail)
when _T_114 :
connect states[7].g, UInt<3>(0h0)
connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6)
node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8)
node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10)
node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12)
node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14)
node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0)
node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0)
node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19)
node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0)
node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11)
node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0)
node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15)
node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0)
node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25)
node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0)
node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27)
node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_29
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10)
node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11)
node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12)
node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13)
node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14)
node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15)
node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23
node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_25
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2)
node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0)
node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1)
node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1)
node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1)
node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4)
node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}
wire _vc_sel_WIRE : UInt<1>[8]
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10)
node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11)
node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12)
node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13)
node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_22
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25)
node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26)
node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27)
node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28)
node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_37
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40)
node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41)
node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42)
node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43)
node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44)
node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_52
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0))
node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54)
node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55)
node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56)
node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57)
node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58)
node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59)
node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_67
connect _vc_sel_WIRE[3], _vc_sel_WIRE_4
node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0))
node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69)
node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70)
node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71)
node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72)
node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73)
node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74)
node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_82
connect _vc_sel_WIRE[4], _vc_sel_WIRE_5
node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0))
node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84)
node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85)
node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86)
node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87)
node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88)
node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89)
node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_97
connect _vc_sel_WIRE[5], _vc_sel_WIRE_6
node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0))
node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99)
node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100)
node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101)
node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102)
node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103)
node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104)
node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_112
connect _vc_sel_WIRE[6], _vc_sel_WIRE_7
node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0))
node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114)
node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115)
node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116)
node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117)
node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118)
node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119)
node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_127
connect _vc_sel_WIRE[7], _vc_sel_WIRE_8
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_9 : UInt<1>[1]
node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129)
node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130)
node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131)
node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132)
node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133)
node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134)
node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_142
connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10
connect vc_sel.`1`, _vc_sel_WIRE_9
wire _vc_sel_WIRE_11 : UInt<1>[1]
node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144)
node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145)
node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146)
node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147)
node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148)
node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149)
node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150)
wire _vc_sel_WIRE_12 : UInt<1>
connect _vc_sel_WIRE_12, _vc_sel_T_157
connect _vc_sel_WIRE_11[0], _vc_sel_WIRE_12
connect vc_sel.`2`, _vc_sel_WIRE_11
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3])
node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4])
node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5])
node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6])
node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7])
node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2])
node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo)
node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4])
node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6])
node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo)
node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo)
node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4)
node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1)
node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0)
node _virt_channel_T_3 = orr(virt_channel_hi_2)
node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2)
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5)
node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6)
node _virt_channel_T_8 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_9 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_10 = mux(vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_11 = or(_virt_channel_T_8, _virt_channel_T_9)
node _virt_channel_T_12 = or(_virt_channel_T_11, _virt_channel_T_10)
wire virt_channel : UInt<3>
connect virt_channel, _virt_channel_T_12
node _T_115 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_115 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9)
node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10)
node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11)
node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12)
node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13)
node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14)
node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15)
wire _salloc_outs_0_flit_payload_WIRE : UInt<73>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9)
node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10)
node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11)
node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12)
node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13)
node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14)
node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9)
node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10)
node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11)
node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12)
node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13)
node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14)
node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3)
node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4)
node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5)
node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6)
node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10)
node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11)
node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12)
node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13)
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25)
node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26)
node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27)
node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28)
node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29)
node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39)
node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40)
node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41)
node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42)
node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43)
node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44)
node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54)
node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55)
node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56)
node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57)
node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58)
node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59)
node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69)
node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70)
node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71)
node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72)
node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73)
node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74)
node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
invalidate states[0].fifo_deps
invalidate states[0].flow.egress_node_id
invalidate states[0].flow.egress_node
invalidate states[0].flow.ingress_node_id
invalidate states[0].flow.ingress_node
invalidate states[0].flow.vnet_id
invalidate states[0].vc_sel.`0`[0]
invalidate states[0].vc_sel.`0`[1]
invalidate states[0].vc_sel.`0`[2]
invalidate states[0].vc_sel.`0`[3]
invalidate states[0].vc_sel.`0`[4]
invalidate states[0].vc_sel.`0`[5]
invalidate states[0].vc_sel.`0`[6]
invalidate states[0].vc_sel.`0`[7]
invalidate states[0].vc_sel.`1`[0]
invalidate states[0].vc_sel.`2`[0]
invalidate states[0].g
connect states[1].vc_sel.`0`[0], UInt<1>(0h0)
connect states[1].vc_sel.`0`[1], UInt<1>(0h0)
connect states[1].vc_sel.`0`[2], UInt<1>(0h0)
connect states[1].vc_sel.`0`[3], UInt<1>(0h0)
connect states[1].vc_sel.`0`[4], UInt<1>(0h0)
connect states[1].vc_sel.`0`[5], UInt<1>(0h0)
connect states[1].vc_sel.`0`[6], UInt<1>(0h0)
connect states[1].vc_sel.`0`[7], UInt<1>(0h0)
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`0`[1], UInt<1>(0h0)
connect states[2].vc_sel.`0`[2], UInt<1>(0h0)
connect states[2].vc_sel.`0`[3], UInt<1>(0h0)
connect states[2].vc_sel.`0`[4], UInt<1>(0h0)
connect states[2].vc_sel.`0`[5], UInt<1>(0h0)
connect states[2].vc_sel.`0`[6], UInt<1>(0h0)
connect states[2].vc_sel.`0`[7], UInt<1>(0h0)
connect states[3].vc_sel.`0`[0], UInt<1>(0h0)
connect states[3].vc_sel.`0`[1], UInt<1>(0h0)
connect states[3].vc_sel.`0`[2], UInt<1>(0h0)
connect states[3].vc_sel.`0`[3], UInt<1>(0h0)
connect states[3].vc_sel.`0`[4], UInt<1>(0h0)
connect states[3].vc_sel.`0`[5], UInt<1>(0h0)
connect states[3].vc_sel.`0`[6], UInt<1>(0h0)
connect states[3].vc_sel.`0`[7], UInt<1>(0h0)
connect states[4].vc_sel.`0`[0], UInt<1>(0h0)
connect states[4].vc_sel.`0`[1], UInt<1>(0h0)
connect states[4].vc_sel.`0`[2], UInt<1>(0h0)
connect states[4].vc_sel.`0`[3], UInt<1>(0h0)
connect states[4].vc_sel.`0`[4], UInt<1>(0h0)
connect states[4].vc_sel.`0`[5], UInt<1>(0h0)
connect states[4].vc_sel.`0`[6], UInt<1>(0h0)
connect states[4].vc_sel.`0`[7], UInt<1>(0h0)
connect states[5].vc_sel.`0`[0], UInt<1>(0h0)
connect states[5].vc_sel.`0`[1], UInt<1>(0h0)
connect states[5].vc_sel.`0`[2], UInt<1>(0h0)
connect states[5].vc_sel.`0`[3], UInt<1>(0h0)
connect states[5].vc_sel.`0`[4], UInt<1>(0h0)
connect states[5].vc_sel.`0`[5], UInt<1>(0h0)
connect states[5].vc_sel.`0`[6], UInt<1>(0h0)
connect states[5].vc_sel.`0`[7], UInt<1>(0h0)
connect states[6].vc_sel.`0`[0], UInt<1>(0h0)
connect states[6].vc_sel.`0`[1], UInt<1>(0h0)
connect states[6].vc_sel.`0`[2], UInt<1>(0h0)
connect states[6].vc_sel.`0`[3], UInt<1>(0h0)
connect states[6].vc_sel.`0`[4], UInt<1>(0h0)
connect states[6].vc_sel.`0`[5], UInt<1>(0h0)
connect states[6].vc_sel.`0`[6], UInt<1>(0h0)
connect states[6].vc_sel.`0`[7], UInt<1>(0h0)
connect states[7].vc_sel.`0`[0], UInt<1>(0h0)
connect states[7].vc_sel.`0`[1], UInt<1>(0h0)
connect states[7].vc_sel.`0`[2], UInt<1>(0h0)
connect states[7].vc_sel.`0`[3], UInt<1>(0h0)
connect states[7].vc_sel.`0`[4], UInt<1>(0h0)
connect states[7].vc_sel.`0`[5], UInt<1>(0h0)
connect states[7].vc_sel.`0`[6], UInt<1>(0h0)
connect states[7].vc_sel.`0`[7], UInt<1>(0h0)
node _T_116 = asUInt(reset)
when _T_116 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0)
connect states[3].g, UInt<3>(0h0)
connect states[4].g, UInt<3>(0h0)
connect states[5].g, UInt<3>(0h0)
connect states[6].g, UInt<3>(0h0)
connect states[7].g, UInt<3>(0h0) | module InputUnit_1( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [7:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_2_0; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [7:0] mask; // @[InputUnit.scala:250:21]
wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_6 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_7 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to this FIRRTL code module DatPath :
input clock : Clock
input reset : Reset
output io : { flip ddpath : { addr : UInt<5>, wdata : UInt<32>, validreq : UInt<1>, flip rdata : UInt<32>, resetpc : UInt<1>}, flip imem : { flip req : { valid : UInt<1>, bits : { pc : UInt<32>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { pc : UInt<32>, inst : UInt<32>}}, debug : { if_pc : UInt<32>, if_inst : UInt<32>}, imiss : UInt<1>, flip exe_kill : UInt<1>}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, flip ctl : { exe_kill : UInt<1>, pc_sel : UInt<3>, brjmp_sel : UInt<1>, op1_sel : UInt<2>, op2_sel : UInt<2>, alu_fun : UInt<4>, wb_sel : UInt<2>, rf_wen : UInt<1>, bypassable : UInt<1>, csr_cmd : UInt<3>, dmem_val : UInt<1>, dmem_fcn : UInt<1>, dmem_typ : UInt<3>, exception : UInt<1>, exception_cause : UInt<32>}, dat : { br_eq : UInt<1>, br_lt : UInt<1>, br_ltu : UInt<1>, inst_misaligned : UInt<1>, data_misaligned : UInt<1>, wb_hazard_stall : UInt<1>, csr_eret : UInt<1>, csr_interrupt : UInt<1>}, flip interrupt : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt}
invalidate io.hartid
invalidate io.interrupt.meip
invalidate io.interrupt.msip
invalidate io.interrupt.mtip
invalidate io.interrupt.debug
invalidate io.dat.csr_interrupt
invalidate io.dat.csr_eret
invalidate io.dat.wb_hazard_stall
invalidate io.dat.data_misaligned
invalidate io.dat.inst_misaligned
invalidate io.dat.br_ltu
invalidate io.dat.br_lt
invalidate io.dat.br_eq
invalidate io.ctl.exception_cause
invalidate io.ctl.exception
invalidate io.ctl.dmem_typ
invalidate io.ctl.dmem_fcn
invalidate io.ctl.dmem_val
invalidate io.ctl.csr_cmd
invalidate io.ctl.bypassable
invalidate io.ctl.rf_wen
invalidate io.ctl.wb_sel
invalidate io.ctl.alu_fun
invalidate io.ctl.op2_sel
invalidate io.ctl.op1_sel
invalidate io.ctl.brjmp_sel
invalidate io.ctl.pc_sel
invalidate io.ctl.exe_kill
invalidate io.dmem.resp.bits.data
invalidate io.dmem.resp.valid
invalidate io.dmem.req.bits.typ
invalidate io.dmem.req.bits.fcn
invalidate io.dmem.req.bits.data
invalidate io.dmem.req.bits.addr
invalidate io.dmem.req.valid
invalidate io.dmem.req.ready
invalidate io.imem.exe_kill
invalidate io.imem.imiss
invalidate io.imem.debug.if_inst
invalidate io.imem.debug.if_pc
invalidate io.imem.resp.bits.inst
invalidate io.imem.resp.bits.pc
invalidate io.imem.resp.valid
invalidate io.imem.resp.ready
invalidate io.imem.req.bits.pc
invalidate io.imem.req.valid
invalidate io.ddpath.resetpc
invalidate io.ddpath.rdata
invalidate io.ddpath.validreq
invalidate io.ddpath.wdata
invalidate io.ddpath.addr
wire tval_data_ma : UInt<32>
wire tval_inst_ma : UInt<32>
regreset wb_reg_inst : UInt<32>, clock, reset, UInt<32>(0h4033)
regreset wb_reg_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg wb_reg_ctrl : { exe_kill : UInt<1>, pc_sel : UInt<3>, brjmp_sel : UInt<1>, op1_sel : UInt<2>, op2_sel : UInt<2>, alu_fun : UInt<4>, wb_sel : UInt<2>, rf_wen : UInt<1>, bypassable : UInt<1>, csr_cmd : UInt<3>, dmem_val : UInt<1>, dmem_fcn : UInt<1>, dmem_typ : UInt<3>, exception : UInt<1>, exception_cause : UInt<32>}, clock
reg wb_reg_pc : UInt<32>, clock
reg wb_reg_alu : UInt<32>, clock
reg wb_reg_csr_addr : UInt<12>, clock
reg wb_reg_wbaddr : UInt<5>, clock
reg wb_reg_target_pc : UInt<32>, clock
regreset wb_reg_mem : UInt<1>, clock, reset, UInt<1>(0h0)
wire wb_hazard_stall : UInt<1>
wire wb_dmiss_stall : UInt<1>
wire exe_brjmp_target : UInt<32>
wire exe_jump_reg_target : UInt<32>
wire exception_target : UInt<32>
node _io_imem_resp_ready_T = eq(wb_hazard_stall, UInt<1>(0h0))
node _io_imem_resp_ready_T_1 = eq(wb_dmiss_stall, UInt<1>(0h0))
node _io_imem_resp_ready_T_2 = and(_io_imem_resp_ready_T, _io_imem_resp_ready_T_1)
connect io.imem.resp.ready, _io_imem_resp_ready_T_2
node _take_pc_T = eq(io.ctl.pc_sel, UInt<3>(0h4))
node _take_pc_T_1 = eq(io.ctl.pc_sel, UInt<3>(0h3))
node _take_pc_T_2 = mux(_take_pc_T_1, exe_jump_reg_target, exe_brjmp_target)
node take_pc = mux(_take_pc_T, exception_target, _take_pc_T_2)
node _io_dat_inst_misaligned_T = bits(exe_brjmp_target, 1, 0)
node _io_dat_inst_misaligned_T_1 = orr(_io_dat_inst_misaligned_T)
node _io_dat_inst_misaligned_T_2 = eq(io.ctl.pc_sel, UInt<3>(0h1))
node _io_dat_inst_misaligned_T_3 = eq(io.ctl.pc_sel, UInt<3>(0h2))
node _io_dat_inst_misaligned_T_4 = or(_io_dat_inst_misaligned_T_2, _io_dat_inst_misaligned_T_3)
node _io_dat_inst_misaligned_T_5 = and(_io_dat_inst_misaligned_T_1, _io_dat_inst_misaligned_T_4)
node _io_dat_inst_misaligned_T_6 = bits(exe_jump_reg_target, 1, 0)
node _io_dat_inst_misaligned_T_7 = orr(_io_dat_inst_misaligned_T_6)
node _io_dat_inst_misaligned_T_8 = eq(io.ctl.pc_sel, UInt<3>(0h3))
node _io_dat_inst_misaligned_T_9 = and(_io_dat_inst_misaligned_T_7, _io_dat_inst_misaligned_T_8)
node _io_dat_inst_misaligned_T_10 = or(_io_dat_inst_misaligned_T_5, _io_dat_inst_misaligned_T_9)
node _io_dat_inst_misaligned_T_11 = and(_io_dat_inst_misaligned_T_10, io.imem.resp.valid)
connect io.dat.inst_misaligned, _io_dat_inst_misaligned_T_11
node _exe_target_pc_T = eq(io.ctl.pc_sel, UInt<3>(0h3))
node exe_target_pc = mux(_exe_target_pc_T, exe_jump_reg_target, exe_brjmp_target)
connect io.imem.req.bits.pc, take_pc
node exe_rs1_addr = bits(io.imem.resp.bits.inst, 19, 15)
node exe_rs2_addr = bits(io.imem.resp.bits.inst, 24, 20)
node exe_wbaddr = bits(io.imem.resp.bits.inst, 11, 7)
wire wb_wbdata : UInt<32>
connect io.dat.wb_hazard_stall, wb_hazard_stall
regreset count : UInt<2>, clock, reset, UInt<2>(0h1)
node _T = eq(wb_reg_wbaddr, exe_rs1_addr)
node _T_1 = and(io.ctl.dmem_val, _T)
node _T_2 = neq(exe_rs1_addr, UInt<1>(0h0))
node _T_3 = and(_T_1, _T_2)
node _T_4 = and(_T_3, wb_reg_ctrl.rf_wen)
node _T_5 = eq(wb_reg_ctrl.bypassable, UInt<1>(0h0))
node _T_6 = and(_T_4, _T_5)
when _T_6 :
connect count, UInt<1>(0h0)
node _T_7 = neq(count, UInt<2>(0h2))
when _T_7 :
node _count_T = add(count, UInt<1>(0h1))
node _count_T_1 = tail(_count_T, 1)
connect count, _count_T_1
node _wb_hazard_stall_T = eq(wb_reg_wbaddr, exe_rs1_addr)
node _wb_hazard_stall_T_1 = neq(exe_rs1_addr, UInt<1>(0h0))
node _wb_hazard_stall_T_2 = and(_wb_hazard_stall_T, _wb_hazard_stall_T_1)
node _wb_hazard_stall_T_3 = and(_wb_hazard_stall_T_2, wb_reg_ctrl.rf_wen)
node _wb_hazard_stall_T_4 = eq(wb_reg_ctrl.bypassable, UInt<1>(0h0))
node _wb_hazard_stall_T_5 = and(_wb_hazard_stall_T_3, _wb_hazard_stall_T_4)
node _wb_hazard_stall_T_6 = eq(wb_reg_wbaddr, exe_rs2_addr)
node _wb_hazard_stall_T_7 = neq(exe_rs2_addr, UInt<1>(0h0))
node _wb_hazard_stall_T_8 = and(_wb_hazard_stall_T_6, _wb_hazard_stall_T_7)
node _wb_hazard_stall_T_9 = and(_wb_hazard_stall_T_8, wb_reg_ctrl.rf_wen)
node _wb_hazard_stall_T_10 = eq(wb_reg_ctrl.bypassable, UInt<1>(0h0))
node _wb_hazard_stall_T_11 = and(_wb_hazard_stall_T_9, _wb_hazard_stall_T_10)
node _wb_hazard_stall_T_12 = or(_wb_hazard_stall_T_5, _wb_hazard_stall_T_11)
reg wb_hazard_stall_REG : UInt<1>, clock
connect wb_hazard_stall_REG, wb_hazard_stall
node _wb_hazard_stall_T_13 = eq(wb_hazard_stall_REG, UInt<1>(0h0))
node _wb_hazard_stall_T_14 = and(io.ctl.dmem_val, _wb_hazard_stall_T_13)
node _wb_hazard_stall_T_15 = or(_wb_hazard_stall_T_12, _wb_hazard_stall_T_14)
node _wb_hazard_stall_T_16 = neq(count, UInt<2>(0h2))
node _wb_hazard_stall_T_17 = and(io.ctl.dmem_val, _wb_hazard_stall_T_16)
node _wb_hazard_stall_T_18 = or(_wb_hazard_stall_T_15, _wb_hazard_stall_T_17)
connect wb_hazard_stall, _wb_hazard_stall_T_18
cmem regfile : UInt<32> [32]
infer mport io_ddpath_rdata_MPORT = regfile[io.ddpath.addr], clock
connect io.ddpath.rdata, io_ddpath_rdata_MPORT
when io.ddpath.validreq :
infer mport MPORT = regfile[io.ddpath.addr], clock
connect MPORT, io.ddpath.wdata
node _T_8 = neq(wb_reg_wbaddr, UInt<1>(0h0))
node _T_9 = and(wb_reg_ctrl.rf_wen, _T_8)
node _T_10 = eq(wb_dmiss_stall, UInt<1>(0h0))
node _T_11 = and(_T_9, _T_10)
node _T_12 = eq(io.ctl.exception, UInt<1>(0h0))
node _T_13 = and(_T_11, _T_12)
when _T_13 :
infer mport MPORT_1 = regfile[wb_reg_wbaddr], clock
connect MPORT_1, wb_wbdata
node _rf_rs1_data_T = neq(exe_rs1_addr, UInt<1>(0h0))
infer mport rf_rs1_data_MPORT = regfile[exe_rs1_addr], clock
node rf_rs1_data = mux(_rf_rs1_data_T, rf_rs1_data_MPORT, UInt<32>(0h0))
node _rf_rs2_data_T = neq(exe_rs2_addr, UInt<1>(0h0))
infer mport rf_rs2_data_MPORT = regfile[exe_rs2_addr], clock
node rf_rs2_data = mux(_rf_rs2_data_T, rf_rs2_data_MPORT, UInt<32>(0h0))
node imm_i = bits(io.imem.resp.bits.inst, 31, 20)
node _imm_s_T = bits(io.imem.resp.bits.inst, 31, 25)
node _imm_s_T_1 = bits(io.imem.resp.bits.inst, 11, 7)
node imm_s = cat(_imm_s_T, _imm_s_T_1)
node _imm_b_T = bits(io.imem.resp.bits.inst, 31, 31)
node _imm_b_T_1 = bits(io.imem.resp.bits.inst, 7, 7)
node _imm_b_T_2 = bits(io.imem.resp.bits.inst, 30, 25)
node _imm_b_T_3 = bits(io.imem.resp.bits.inst, 11, 8)
node imm_b_lo = cat(_imm_b_T_2, _imm_b_T_3)
node imm_b_hi = cat(_imm_b_T, _imm_b_T_1)
node imm_b = cat(imm_b_hi, imm_b_lo)
node _imm_u_T = bits(io.imem.resp.bits.inst, 31, 12)
node _imm_u_T_1 = mux(UInt<1>(0h0), UInt<12>(0hfff), UInt<12>(0h0))
node imm_u = cat(_imm_u_T, _imm_u_T_1)
node _imm_j_T = bits(io.imem.resp.bits.inst, 31, 31)
node _imm_j_T_1 = bits(io.imem.resp.bits.inst, 19, 12)
node _imm_j_T_2 = bits(io.imem.resp.bits.inst, 20, 20)
node _imm_j_T_3 = bits(io.imem.resp.bits.inst, 30, 21)
node imm_j_lo = cat(_imm_j_T_2, _imm_j_T_3)
node imm_j_hi = cat(_imm_j_T, _imm_j_T_1)
node imm_j = cat(imm_j_hi, imm_j_lo)
node imm_z = bits(io.imem.resp.bits.inst, 19, 15)
node _imm_i_sext_T = bits(imm_i, 11, 11)
node _imm_i_sext_T_1 = mux(_imm_i_sext_T, UInt<20>(0hfffff), UInt<20>(0h0))
node imm_i_sext = cat(_imm_i_sext_T_1, imm_i)
node _imm_s_sext_T = bits(imm_s, 11, 11)
node _imm_s_sext_T_1 = mux(_imm_s_sext_T, UInt<20>(0hfffff), UInt<20>(0h0))
node imm_s_sext = cat(_imm_s_sext_T_1, imm_s)
node _imm_b_sext_T = bits(imm_b, 11, 11)
node _imm_b_sext_T_1 = mux(_imm_b_sext_T, UInt<19>(0h7ffff), UInt<19>(0h0))
node imm_b_sext_hi = cat(_imm_b_sext_T_1, imm_b)
node imm_b_sext = cat(imm_b_sext_hi, UInt<1>(0h0))
node _imm_j_sext_T = bits(imm_j, 19, 19)
node _imm_j_sext_T_1 = mux(_imm_j_sext_T, UInt<11>(0h7ff), UInt<11>(0h0))
node imm_j_sext_hi = cat(_imm_j_sext_T_1, imm_j)
node imm_j_sext = cat(imm_j_sext_hi, UInt<1>(0h0))
node _exe_rs1_data_T = eq(wb_reg_wbaddr, exe_rs1_addr)
node _exe_rs1_data_T_1 = neq(exe_rs1_addr, UInt<1>(0h0))
node _exe_rs1_data_T_2 = and(_exe_rs1_data_T, _exe_rs1_data_T_1)
node _exe_rs1_data_T_3 = and(_exe_rs1_data_T_2, wb_reg_ctrl.rf_wen)
node _exe_rs1_data_T_4 = and(_exe_rs1_data_T_3, wb_reg_ctrl.bypassable)
node exe_rs1_data = mux(_exe_rs1_data_T_4, wb_reg_alu, rf_rs1_data)
node _exe_rs2_data_T = eq(wb_reg_wbaddr, exe_rs2_addr)
node _exe_rs2_data_T_1 = neq(exe_rs2_addr, UInt<1>(0h0))
node _exe_rs2_data_T_2 = and(_exe_rs2_data_T, _exe_rs2_data_T_1)
node _exe_rs2_data_T_3 = and(_exe_rs2_data_T_2, wb_reg_ctrl.rf_wen)
node _exe_rs2_data_T_4 = and(_exe_rs2_data_T_3, wb_reg_ctrl.bypassable)
node exe_rs2_data = mux(_exe_rs2_data_T_4, wb_reg_alu, rf_rs2_data)
node _exe_alu_op1_T = eq(io.ctl.op1_sel, UInt<2>(0h2))
node _exe_alu_op1_T_1 = eq(io.ctl.op1_sel, UInt<2>(0h1))
node _exe_alu_op1_T_2 = mux(_exe_alu_op1_T_1, imm_u, exe_rs1_data)
node exe_alu_op1 = mux(_exe_alu_op1_T, imm_z, _exe_alu_op1_T_2)
node _exe_alu_op2_T = eq(io.ctl.op2_sel, UInt<2>(0h1))
node _exe_alu_op2_T_1 = eq(io.ctl.op2_sel, UInt<2>(0h3))
node _exe_alu_op2_T_2 = eq(io.ctl.op2_sel, UInt<2>(0h2))
node _exe_alu_op2_T_3 = mux(_exe_alu_op2_T_2, imm_s_sext, exe_rs2_data)
node _exe_alu_op2_T_4 = mux(_exe_alu_op2_T_1, io.imem.resp.bits.pc, _exe_alu_op2_T_3)
node exe_alu_op2 = mux(_exe_alu_op2_T, imm_i_sext, _exe_alu_op2_T_4)
inst alu of ALU
connect alu.clock, clock
connect alu.reset, reset
connect alu.io.in1, exe_alu_op1
connect alu.io.in2, exe_alu_op2
connect alu.io.fn, io.ctl.alu_fun
node imm_brjmp = mux(io.ctl.brjmp_sel, imm_j_sext, imm_b_sext)
node _exe_brjmp_target_T = add(io.imem.resp.bits.pc, imm_brjmp)
node _exe_brjmp_target_T_1 = tail(_exe_brjmp_target_T, 1)
connect exe_brjmp_target, _exe_brjmp_target_T_1
node _exe_jump_reg_target_T = not(UInt<32>(0h1))
node _exe_jump_reg_target_T_1 = and(alu.io.adder_out, _exe_jump_reg_target_T)
connect exe_jump_reg_target, _exe_jump_reg_target_T_1
node _io_dat_br_eq_T = eq(exe_rs1_data, exe_rs2_data)
connect io.dat.br_eq, _io_dat_br_eq_T
node _io_dat_br_lt_T = asSInt(exe_rs1_data)
node _io_dat_br_lt_T_1 = asSInt(exe_rs2_data)
node _io_dat_br_lt_T_2 = lt(_io_dat_br_lt_T, _io_dat_br_lt_T_1)
connect io.dat.br_lt, _io_dat_br_lt_T_2
node _io_dat_br_ltu_T = lt(exe_rs1_data, exe_rs2_data)
connect io.dat.br_ltu, _io_dat_br_ltu_T
node mem_address_low = bits(alu.io.out, 2, 0)
wire misaligned_mask : UInt<3>
node _misaligned_mask_T = sub(io.ctl.dmem_typ, UInt<1>(0h1))
node _misaligned_mask_T_1 = tail(_misaligned_mask_T, 1)
node _misaligned_mask_T_2 = bits(_misaligned_mask_T_1, 1, 0)
node _misaligned_mask_T_3 = dshl(UInt<3>(0h7), _misaligned_mask_T_2)
node _misaligned_mask_T_4 = not(_misaligned_mask_T_3)
connect misaligned_mask, _misaligned_mask_T_4
node _io_dat_data_misaligned_T = and(misaligned_mask, mem_address_low)
node _io_dat_data_misaligned_T_1 = orr(_io_dat_data_misaligned_T)
node _io_dat_data_misaligned_T_2 = and(_io_dat_data_misaligned_T_1, io.ctl.dmem_val)
connect io.dat.data_misaligned, _io_dat_data_misaligned_T_2
node _io_dmem_req_valid_T = eq(io.dat.data_misaligned, UInt<1>(0h0))
node _io_dmem_req_valid_T_1 = and(io.ctl.dmem_val, _io_dmem_req_valid_T)
node _io_dmem_req_valid_T_2 = eq(wb_hazard_stall, UInt<1>(0h0))
node _io_dmem_req_valid_T_3 = and(_io_dmem_req_valid_T_1, _io_dmem_req_valid_T_2)
connect io.dmem.req.valid, _io_dmem_req_valid_T_3
node _io_dmem_req_bits_fcn_T = and(io.ctl.dmem_fcn, io.imem.resp.valid)
node _io_dmem_req_bits_fcn_T_1 = eq(wb_reg_wbaddr, exe_rs1_addr)
node _io_dmem_req_bits_fcn_T_2 = neq(exe_rs1_addr, UInt<1>(0h0))
node _io_dmem_req_bits_fcn_T_3 = and(_io_dmem_req_bits_fcn_T_1, _io_dmem_req_bits_fcn_T_2)
node _io_dmem_req_bits_fcn_T_4 = and(_io_dmem_req_bits_fcn_T_3, wb_reg_ctrl.rf_wen)
node _io_dmem_req_bits_fcn_T_5 = eq(wb_reg_ctrl.bypassable, UInt<1>(0h0))
node _io_dmem_req_bits_fcn_T_6 = and(_io_dmem_req_bits_fcn_T_4, _io_dmem_req_bits_fcn_T_5)
node _io_dmem_req_bits_fcn_T_7 = eq(_io_dmem_req_bits_fcn_T_6, UInt<1>(0h0))
node _io_dmem_req_bits_fcn_T_8 = and(_io_dmem_req_bits_fcn_T, _io_dmem_req_bits_fcn_T_7)
connect io.dmem.req.bits.fcn, _io_dmem_req_bits_fcn_T_8
connect io.dmem.req.bits.typ, io.ctl.dmem_typ
connect io.dmem.req.bits.addr, alu.io.out
connect io.dmem.req.bits.data, exe_rs2_data
node _wb_dmiss_stall_T = eq(io.dmem.req.ready, UInt<1>(0h0))
node _wb_dmiss_stall_T_1 = and(_wb_dmiss_stall_T, io.dmem.req.valid)
node _wb_dmiss_stall_T_2 = eq(io.dmem.resp.valid, UInt<1>(0h0))
node _wb_dmiss_stall_T_3 = and(wb_reg_mem, _wb_dmiss_stall_T_2)
node _wb_dmiss_stall_T_4 = or(_wb_dmiss_stall_T_1, _wb_dmiss_stall_T_3)
connect wb_dmiss_stall, _wb_dmiss_stall_T_4
node _T_14 = eq(wb_dmiss_stall, UInt<1>(0h0))
when _T_14 :
node _T_15 = or(wb_hazard_stall, io.ctl.exe_kill)
node _T_16 = eq(io.imem.resp.valid, UInt<1>(0h0))
node _T_17 = or(_T_15, _T_16)
when _T_17 :
connect wb_reg_inst, UInt<32>(0h4033)
connect wb_reg_valid, UInt<1>(0h0)
connect wb_reg_ctrl.rf_wen, UInt<1>(0h0)
connect wb_reg_ctrl.csr_cmd, UInt<3>(0h0)
connect wb_reg_ctrl.dmem_val, UInt<1>(0h0)
connect wb_reg_ctrl.exception, UInt<1>(0h0)
connect wb_reg_mem, UInt<1>(0h0)
else :
connect wb_reg_inst, io.imem.resp.bits.inst
connect wb_reg_valid, io.imem.resp.valid
connect wb_reg_ctrl, io.ctl
connect wb_reg_pc, io.imem.resp.bits.pc
connect wb_reg_alu, alu.io.out
connect wb_reg_wbaddr, exe_wbaddr
node _wb_reg_csr_addr_T = bits(io.imem.resp.bits.inst, 31, 20)
connect wb_reg_csr_addr, _wb_reg_csr_addr_T
connect wb_reg_target_pc, exe_target_pc
connect wb_reg_mem, io.dmem.req.valid
wire _hits_WIRE : UInt<1>[1]
connect _hits_WIRE[0], UInt<1>(0h0)
wire hits : UInt<1>[1]
connect hits, _hits_WIRE
inst csr of CSRFile
connect csr.clock, clock
connect csr.reset, reset
invalidate csr.io.fiom
invalidate csr.io.scontext
invalidate csr.io.mcontext
invalidate csr.io.trace[0].tval
invalidate csr.io.trace[0].cause
invalidate csr.io.trace[0].interrupt
invalidate csr.io.trace[0].exception
invalidate csr.io.trace[0].priv
invalidate csr.io.trace[0].insn
invalidate csr.io.trace[0].iaddr
invalidate csr.io.trace[0].valid
invalidate csr.io.inst[0]
invalidate csr.io.inhibit_cycle
invalidate csr.io.csrw_counter
invalidate csr.io.interrupt_cause
invalidate csr.io.interrupt
invalidate csr.io.rocc_interrupt
invalidate csr.io.fcsr_flags.bits
invalidate csr.io.fcsr_flags.valid
invalidate csr.io.fcsr_rm
invalidate csr.io.time
invalidate csr.io.gva
invalidate csr.io.mhtinst_read_pseudo
invalidate csr.io.htval
invalidate csr.io.tval
invalidate csr.io.pc
invalidate csr.io.cause
invalidate csr.io.retire
invalidate csr.io.exception
invalidate csr.io.evec
invalidate csr.io.vsatp.ppn
invalidate csr.io.vsatp.asid
invalidate csr.io.vsatp.mode
invalidate csr.io.hgatp.ppn
invalidate csr.io.hgatp.asid
invalidate csr.io.hgatp.mode
invalidate csr.io.ptbr.ppn
invalidate csr.io.ptbr.asid
invalidate csr.io.ptbr.mode
invalidate csr.io.gstatus.uie
invalidate csr.io.gstatus.sie
invalidate csr.io.gstatus.hie
invalidate csr.io.gstatus.mie
invalidate csr.io.gstatus.upie
invalidate csr.io.gstatus.spie
invalidate csr.io.gstatus.ube
invalidate csr.io.gstatus.mpie
invalidate csr.io.gstatus.spp
invalidate csr.io.gstatus.vs
invalidate csr.io.gstatus.mpp
invalidate csr.io.gstatus.fs
invalidate csr.io.gstatus.xs
invalidate csr.io.gstatus.mprv
invalidate csr.io.gstatus.sum
invalidate csr.io.gstatus.mxr
invalidate csr.io.gstatus.tvm
invalidate csr.io.gstatus.tw
invalidate csr.io.gstatus.tsr
invalidate csr.io.gstatus.zero1
invalidate csr.io.gstatus.sd_rv32
invalidate csr.io.gstatus.uxl
invalidate csr.io.gstatus.sxl
invalidate csr.io.gstatus.sbe
invalidate csr.io.gstatus.mbe
invalidate csr.io.gstatus.gva
invalidate csr.io.gstatus.mpv
invalidate csr.io.gstatus.zero2
invalidate csr.io.gstatus.sd
invalidate csr.io.gstatus.v
invalidate csr.io.gstatus.prv
invalidate csr.io.gstatus.dv
invalidate csr.io.gstatus.dprv
invalidate csr.io.gstatus.isa
invalidate csr.io.gstatus.wfi
invalidate csr.io.gstatus.cease
invalidate csr.io.gstatus.debug
invalidate csr.io.hstatus.zero1
invalidate csr.io.hstatus.vsbe
invalidate csr.io.hstatus.gva
invalidate csr.io.hstatus.spv
invalidate csr.io.hstatus.spvp
invalidate csr.io.hstatus.hu
invalidate csr.io.hstatus.zero2
invalidate csr.io.hstatus.vgein
invalidate csr.io.hstatus.zero3
invalidate csr.io.hstatus.vtvm
invalidate csr.io.hstatus.vtw
invalidate csr.io.hstatus.vtsr
invalidate csr.io.hstatus.zero5
invalidate csr.io.hstatus.vsxl
invalidate csr.io.hstatus.zero6
invalidate csr.io.status.uie
invalidate csr.io.status.sie
invalidate csr.io.status.hie
invalidate csr.io.status.mie
invalidate csr.io.status.upie
invalidate csr.io.status.spie
invalidate csr.io.status.ube
invalidate csr.io.status.mpie
invalidate csr.io.status.spp
invalidate csr.io.status.vs
invalidate csr.io.status.mpp
invalidate csr.io.status.fs
invalidate csr.io.status.xs
invalidate csr.io.status.mprv
invalidate csr.io.status.sum
invalidate csr.io.status.mxr
invalidate csr.io.status.tvm
invalidate csr.io.status.tw
invalidate csr.io.status.tsr
invalidate csr.io.status.zero1
invalidate csr.io.status.sd_rv32
invalidate csr.io.status.uxl
invalidate csr.io.status.sxl
invalidate csr.io.status.sbe
invalidate csr.io.status.mbe
invalidate csr.io.status.gva
invalidate csr.io.status.mpv
invalidate csr.io.status.zero2
invalidate csr.io.status.sd
invalidate csr.io.status.v
invalidate csr.io.status.prv
invalidate csr.io.status.dv
invalidate csr.io.status.dprv
invalidate csr.io.status.isa
invalidate csr.io.status.wfi
invalidate csr.io.status.cease
invalidate csr.io.status.debug
invalidate csr.io.singleStep
invalidate csr.io.eret
invalidate csr.io.rw_stall
invalidate csr.io.csr_stall
invalidate csr.io.decode[0].virtual_system_illegal
invalidate csr.io.decode[0].virtual_access_illegal
invalidate csr.io.decode[0].system_illegal
invalidate csr.io.decode[0].write_flush
invalidate csr.io.decode[0].write_illegal
invalidate csr.io.decode[0].read_illegal
invalidate csr.io.decode[0].rocc_illegal
invalidate csr.io.decode[0].vector_csr
invalidate csr.io.decode[0].fp_csr
invalidate csr.io.decode[0].vector_illegal
invalidate csr.io.decode[0].fp_illegal
invalidate csr.io.decode[0].inst
invalidate csr.io.rw.wdata
invalidate csr.io.rw.rdata
invalidate csr.io.rw.cmd
invalidate csr.io.rw.addr
invalidate csr.io.hartid
invalidate csr.io.interrupts.meip
invalidate csr.io.interrupts.msip
invalidate csr.io.interrupts.mtip
invalidate csr.io.interrupts.debug
invalidate csr.io.ungated_clock
node _csr_io_decode_0_inst_T = shl(wb_reg_csr_addr, 20)
connect csr.io.decode[0].inst, _csr_io_decode_0_inst_T
node _csr_io_rw_addr_T = bits(wb_reg_inst, 31, 20)
connect csr.io.rw.addr, _csr_io_rw_addr_T
connect csr.io.rw.wdata, wb_reg_alu
node _csr_io_rw_cmd_T = mux(wb_dmiss_stall, UInt<3>(0h0), wb_reg_ctrl.csr_cmd)
connect csr.io.rw.cmd, _csr_io_rw_cmd_T
node _csr_io_retire_T = eq(io.ctl.exception, UInt<1>(0h0))
node _csr_io_retire_T_1 = and(wb_reg_valid, _csr_io_retire_T)
connect csr.io.retire, _csr_io_retire_T_1
connect csr.io.exception, io.ctl.exception
connect csr.io.pc, wb_reg_pc
connect exception_target, csr.io.evec
connect io.dat.csr_eret, csr.io.eret
connect tval_data_ma, wb_reg_alu
connect tval_inst_ma, wb_reg_target_pc
node _csr_io_tval_T = eq(io.ctl.exception_cause, UInt<2>(0h2))
node _csr_io_tval_T_1 = eq(io.ctl.exception_cause, UInt<1>(0h0))
node _csr_io_tval_T_2 = eq(io.ctl.exception_cause, UInt<3>(0h6))
node _csr_io_tval_T_3 = eq(io.ctl.exception_cause, UInt<3>(0h4))
node _csr_io_tval_T_4 = mux(_csr_io_tval_T_3, tval_data_ma, UInt<1>(0h0))
node _csr_io_tval_T_5 = mux(_csr_io_tval_T_2, tval_data_ma, _csr_io_tval_T_4)
node _csr_io_tval_T_6 = mux(_csr_io_tval_T_1, tval_inst_ma, _csr_io_tval_T_5)
node _csr_io_tval_T_7 = mux(_csr_io_tval_T, wb_reg_inst, _csr_io_tval_T_6)
connect csr.io.tval, _csr_io_tval_T_7
regreset reg_interrupt_flag : UInt<1>, clock, reset, UInt<1>(0h0)
connect reg_interrupt_flag, csr.io.interrupt
node _interrupt_edge_T = eq(reg_interrupt_flag, UInt<1>(0h0))
node interrupt_edge = and(csr.io.interrupt, _interrupt_edge_T)
connect csr.io.interrupts.meip, io.interrupt.meip
connect csr.io.interrupts.msip, io.interrupt.msip
connect csr.io.interrupts.mtip, io.interrupt.mtip
connect csr.io.interrupts.debug, io.interrupt.debug
connect csr.io.hartid, io.hartid
connect io.dat.csr_interrupt, interrupt_edge
node _csr_io_cause_T = mux(io.ctl.exception, io.ctl.exception_cause, csr.io.interrupt_cause)
connect csr.io.cause, _csr_io_cause_T
connect csr.io.ungated_clock, clock
node _wb_wbdata_T = eq(wb_reg_ctrl.wb_sel, UInt<2>(0h0))
node _wb_wbdata_T_1 = eq(wb_reg_ctrl.wb_sel, UInt<2>(0h1))
node _wb_wbdata_T_2 = eq(wb_reg_ctrl.wb_sel, UInt<2>(0h2))
node _wb_wbdata_T_3 = eq(wb_reg_ctrl.wb_sel, UInt<2>(0h3))
node _wb_wbdata_T_4 = mux(_wb_wbdata_T_3, csr.io.rw.rdata, wb_reg_alu)
node _wb_wbdata_T_5 = mux(_wb_wbdata_T_2, io.imem.resp.bits.pc, _wb_wbdata_T_4)
node _wb_wbdata_T_6 = mux(_wb_wbdata_T_1, io.dmem.resp.bits.data, _wb_wbdata_T_5)
node _wb_wbdata_T_7 = mux(_wb_wbdata_T, wb_reg_alu, _wb_wbdata_T_6)
connect wb_wbdata, _wb_wbdata_T_7
node _debug_wb_inst_T = or(wb_hazard_stall, io.ctl.exe_kill)
node _debug_wb_inst_T_1 = eq(io.imem.resp.valid, UInt<1>(0h0))
node _debug_wb_inst_T_2 = or(_debug_wb_inst_T, _debug_wb_inst_T_1)
node _debug_wb_inst_T_3 = mux(_debug_wb_inst_T_2, UInt<32>(0h4033), io.imem.resp.bits.inst)
reg debug_wb_inst : UInt, clock
connect debug_wb_inst, _debug_wb_inst_T_3
node _T_18 = bits(csr.io.time, 31, 0)
reg REG : UInt, clock
connect REG, exe_rs1_addr
reg REG_1 : UInt, clock
connect REG_1, exe_alu_op1
reg REG_2 : UInt, clock
connect REG_2, exe_rs2_addr
reg REG_3 : UInt, clock
connect REG_3, exe_alu_op2
node _T_19 = mux(io.ctl.exe_kill, UInt<8>(0h4b), UInt<8>(0h20))
node _T_20 = mux(wb_hazard_stall, UInt<8>(0h48), _T_19)
node _T_21 = eq(UInt<3>(0h1), io.ctl.pc_sel)
node _T_22 = mux(_T_21, UInt<8>(0h42), UInt<8>(0h3f))
node _T_23 = eq(UInt<3>(0h2), io.ctl.pc_sel)
node _T_24 = mux(_T_23, UInt<8>(0h4a), _T_22)
node _T_25 = eq(UInt<3>(0h3), io.ctl.pc_sel)
node _T_26 = mux(_T_25, UInt<8>(0h52), _T_24)
node _T_27 = eq(UInt<3>(0h4), io.ctl.pc_sel)
node _T_28 = mux(_T_27, UInt<8>(0h45), _T_26)
node _T_29 = eq(UInt<3>(0h0), io.ctl.pc_sel)
node _T_30 = mux(_T_29, UInt<8>(0h20), _T_28)
node _T_31 = mux(csr.io.exception, UInt<8>(0h58), UInt<8>(0h20))
node _T_32 = asUInt(reset)
node _T_33 = eq(_T_32, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "Cyc= %d [%d] pc=[%x] W[r%d=%x][%d] Op1=[r%d][%x] Op2=[r%d][%x] inst=[%x] %c%c%c DASM(%x)\n", _T_18, csr.io.retire, wb_reg_pc, wb_reg_wbaddr, wb_wbdata, wb_reg_ctrl.rf_wen, REG, REG_1, REG_2, REG_3, debug_wb_inst, _T_20, _T_30, _T_31, debug_wb_inst) : printf | module DatPath( // @[dpath.scala:50:7]
input clock, // @[dpath.scala:50:7]
input reset, // @[dpath.scala:50:7]
output [31:0] io_ddpath_rdata, // @[dpath.scala:52:15]
output [31:0] io_imem_req_bits_pc, // @[dpath.scala:52:15]
output io_imem_resp_ready, // @[dpath.scala:52:15]
input io_imem_resp_valid, // @[dpath.scala:52:15]
input [31:0] io_imem_resp_bits_pc, // @[dpath.scala:52:15]
input [31:0] io_imem_resp_bits_inst, // @[dpath.scala:52:15]
input [31:0] io_imem_debug_if_pc, // @[dpath.scala:52:15]
input [31:0] io_imem_debug_if_inst, // @[dpath.scala:52:15]
input io_dmem_req_ready, // @[dpath.scala:52:15]
output io_dmem_req_valid, // @[dpath.scala:52:15]
output [31:0] io_dmem_req_bits_addr, // @[dpath.scala:52:15]
output [31:0] io_dmem_req_bits_data, // @[dpath.scala:52:15]
output io_dmem_req_bits_fcn, // @[dpath.scala:52:15]
output [2:0] io_dmem_req_bits_typ, // @[dpath.scala:52:15]
input io_dmem_resp_valid, // @[dpath.scala:52:15]
input [31:0] io_dmem_resp_bits_data, // @[dpath.scala:52:15]
input io_ctl_exe_kill, // @[dpath.scala:52:15]
input [2:0] io_ctl_pc_sel, // @[dpath.scala:52:15]
input io_ctl_brjmp_sel, // @[dpath.scala:52:15]
input [1:0] io_ctl_op1_sel, // @[dpath.scala:52:15]
input [1:0] io_ctl_op2_sel, // @[dpath.scala:52:15]
input [3:0] io_ctl_alu_fun, // @[dpath.scala:52:15]
input [1:0] io_ctl_wb_sel, // @[dpath.scala:52:15]
input io_ctl_rf_wen, // @[dpath.scala:52:15]
input io_ctl_bypassable, // @[dpath.scala:52:15]
input [2:0] io_ctl_csr_cmd, // @[dpath.scala:52:15]
input io_ctl_dmem_val, // @[dpath.scala:52:15]
input io_ctl_dmem_fcn, // @[dpath.scala:52:15]
input [2:0] io_ctl_dmem_typ, // @[dpath.scala:52:15]
input io_ctl_exception, // @[dpath.scala:52:15]
input [31:0] io_ctl_exception_cause, // @[dpath.scala:52:15]
output io_dat_br_eq, // @[dpath.scala:52:15]
output io_dat_br_lt, // @[dpath.scala:52:15]
output io_dat_br_ltu, // @[dpath.scala:52:15]
output io_dat_inst_misaligned, // @[dpath.scala:52:15]
output io_dat_data_misaligned, // @[dpath.scala:52:15]
output io_dat_wb_hazard_stall, // @[dpath.scala:52:15]
output io_dat_csr_eret, // @[dpath.scala:52:15]
output io_dat_csr_interrupt, // @[dpath.scala:52:15]
input io_interrupt_debug, // @[dpath.scala:52:15]
input io_interrupt_mtip, // @[dpath.scala:52:15]
input io_interrupt_msip, // @[dpath.scala:52:15]
input io_interrupt_meip, // @[dpath.scala:52:15]
input io_hartid // @[dpath.scala:52:15]
);
wire [31:0] _csr_io_rw_rdata; // @[dpath.scala:259:20]
wire [31:0] _csr_io_time; // @[dpath.scala:259:20]
wire _csr_io_interrupt; // @[dpath.scala:259:20]
wire [31:0] _csr_io_interrupt_cause; // @[dpath.scala:259:20]
wire [31:0] _alu_io_out; // @[dpath.scala:190:20]
wire [31:0] _alu_io_adder_out; // @[dpath.scala:190:20]
wire [31:0] _regfile_ext_R0_data; // @[dpath.scala:135:21]
wire [31:0] _regfile_ext_R1_data; // @[dpath.scala:135:21]
wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[dpath.scala:50:7]
wire [31:0] io_imem_resp_bits_pc_0 = io_imem_resp_bits_pc; // @[dpath.scala:50:7]
wire [31:0] io_imem_resp_bits_inst_0 = io_imem_resp_bits_inst; // @[dpath.scala:50:7]
wire [31:0] io_imem_debug_if_pc_0 = io_imem_debug_if_pc; // @[dpath.scala:50:7]
wire [31:0] io_imem_debug_if_inst_0 = io_imem_debug_if_inst; // @[dpath.scala:50:7]
wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[dpath.scala:50:7]
wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[dpath.scala:50:7]
wire [31:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[dpath.scala:50:7]
wire io_ctl_exe_kill_0 = io_ctl_exe_kill; // @[dpath.scala:50:7]
wire [2:0] io_ctl_pc_sel_0 = io_ctl_pc_sel; // @[dpath.scala:50:7]
wire io_ctl_brjmp_sel_0 = io_ctl_brjmp_sel; // @[dpath.scala:50:7]
wire [1:0] io_ctl_op1_sel_0 = io_ctl_op1_sel; // @[dpath.scala:50:7]
wire [1:0] io_ctl_op2_sel_0 = io_ctl_op2_sel; // @[dpath.scala:50:7]
wire [3:0] io_ctl_alu_fun_0 = io_ctl_alu_fun; // @[dpath.scala:50:7]
wire [1:0] io_ctl_wb_sel_0 = io_ctl_wb_sel; // @[dpath.scala:50:7]
wire io_ctl_rf_wen_0 = io_ctl_rf_wen; // @[dpath.scala:50:7]
wire io_ctl_bypassable_0 = io_ctl_bypassable; // @[dpath.scala:50:7]
wire [2:0] io_ctl_csr_cmd_0 = io_ctl_csr_cmd; // @[dpath.scala:50:7]
wire io_ctl_dmem_val_0 = io_ctl_dmem_val; // @[dpath.scala:50:7]
wire io_ctl_dmem_fcn_0 = io_ctl_dmem_fcn; // @[dpath.scala:50:7]
wire [2:0] io_ctl_dmem_typ_0 = io_ctl_dmem_typ; // @[dpath.scala:50:7]
wire io_ctl_exception_0 = io_ctl_exception; // @[dpath.scala:50:7]
wire [31:0] io_ctl_exception_cause_0 = io_ctl_exception_cause; // @[dpath.scala:50:7]
wire io_interrupt_debug_0 = io_interrupt_debug; // @[dpath.scala:50:7]
wire io_interrupt_mtip_0 = io_interrupt_mtip; // @[dpath.scala:50:7]
wire io_interrupt_msip_0 = io_interrupt_msip; // @[dpath.scala:50:7]
wire io_interrupt_meip_0 = io_interrupt_meip; // @[dpath.scala:50:7]
wire io_hartid_0 = io_hartid; // @[dpath.scala:50:7]
wire [4:0] io_ddpath_addr = 5'h0; // @[dpath.scala:50:7]
wire [31:0] io_ddpath_wdata = 32'h0; // @[dpath.scala:50:7]
wire io_ddpath_validreq = 1'h0; // @[dpath.scala:50:7]
wire io_ddpath_resetpc = 1'h0; // @[dpath.scala:50:7]
wire io_imem_req_valid = 1'h0; // @[dpath.scala:50:7]
wire io_imem_imiss = 1'h0; // @[dpath.scala:50:7]
wire io_imem_exe_kill = 1'h0; // @[dpath.scala:50:7]
wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33]
wire hits_0 = 1'h0; // @[Events.scala:13:25]
wire [31:0] _exe_jump_reg_target_T = 32'hFFFFFFFE; // @[dpath.scala:201:46]
wire [11:0] _imm_u_T_1 = 12'h0; // @[dpath.scala:157:42]
wire [31:0] take_pc; // @[dpath.scala:83:21]
wire _io_imem_resp_ready_T_2; // @[dpath.scala:80:43]
wire _io_dmem_req_valid_T_3; // @[dpath.scala:217:72]
wire [31:0] exe_rs2_data; // @[Mux.scala:126:16]
wire _io_dmem_req_bits_fcn_T_8; // @[dpath.scala:219:60]
wire [2:0] io_dmem_req_bits_typ_0 = io_ctl_dmem_typ_0; // @[dpath.scala:50:7]
wire _io_dat_br_eq_T; // @[dpath.scala:205:35]
wire _io_dat_br_lt_T_2; // @[dpath.scala:206:42]
wire _io_dat_br_ltu_T; // @[dpath.scala:207:42]
wire _io_dat_inst_misaligned_T_11; // @[dpath.scala:91:91]
wire _io_dat_data_misaligned_T_2; // @[dpath.scala:214:70]
wire wb_hazard_stall; // @[dpath.scala:71:31]
wire interrupt_edge; // @[dpath.scala:284:42]
wire [31:0] io_ddpath_rdata_0; // @[dpath.scala:50:7]
wire [31:0] io_imem_req_bits_pc_0; // @[dpath.scala:50:7]
wire io_imem_resp_ready_0; // @[dpath.scala:50:7]
wire [31:0] io_dmem_req_bits_addr_0; // @[dpath.scala:50:7]
wire [31:0] io_dmem_req_bits_data_0; // @[dpath.scala:50:7]
wire io_dmem_req_bits_fcn_0; // @[dpath.scala:50:7]
wire io_dmem_req_valid_0; // @[dpath.scala:50:7]
wire io_dat_br_eq_0; // @[dpath.scala:50:7]
wire io_dat_br_lt_0; // @[dpath.scala:50:7]
wire io_dat_br_ltu_0; // @[dpath.scala:50:7]
wire io_dat_inst_misaligned_0; // @[dpath.scala:50:7]
wire io_dat_data_misaligned_0; // @[dpath.scala:50:7]
wire io_dat_wb_hazard_stall_0; // @[dpath.scala:50:7]
wire io_dat_csr_eret_0; // @[dpath.scala:50:7]
wire io_dat_csr_interrupt_0; // @[dpath.scala:50:7]
wire [31:0] tval_data_ma; // @[dpath.scala:56:27]
wire [31:0] tval_inst_ma; // @[dpath.scala:57:27]
reg [31:0] wb_reg_inst; // @[dpath.scala:61:34]
reg wb_reg_valid; // @[dpath.scala:62:34]
reg wb_reg_ctrl_exe_kill; // @[dpath.scala:63:30]
reg [2:0] wb_reg_ctrl_pc_sel; // @[dpath.scala:63:30]
reg wb_reg_ctrl_brjmp_sel; // @[dpath.scala:63:30]
reg [1:0] wb_reg_ctrl_op1_sel; // @[dpath.scala:63:30]
reg [1:0] wb_reg_ctrl_op2_sel; // @[dpath.scala:63:30]
reg [3:0] wb_reg_ctrl_alu_fun; // @[dpath.scala:63:30]
reg [1:0] wb_reg_ctrl_wb_sel; // @[dpath.scala:63:30]
reg wb_reg_ctrl_rf_wen; // @[dpath.scala:63:30]
reg wb_reg_ctrl_bypassable; // @[dpath.scala:63:30]
reg [2:0] wb_reg_ctrl_csr_cmd; // @[dpath.scala:63:30]
reg wb_reg_ctrl_dmem_val; // @[dpath.scala:63:30]
reg wb_reg_ctrl_dmem_fcn; // @[dpath.scala:63:30]
reg [2:0] wb_reg_ctrl_dmem_typ; // @[dpath.scala:63:30]
reg wb_reg_ctrl_exception; // @[dpath.scala:63:30]
reg [31:0] wb_reg_ctrl_exception_cause; // @[dpath.scala:63:30]
reg [31:0] wb_reg_pc; // @[dpath.scala:64:30]
reg [31:0] wb_reg_alu; // @[dpath.scala:65:30]
assign tval_data_ma = wb_reg_alu; // @[dpath.scala:56:27, :65:30]
reg [11:0] wb_reg_csr_addr; // @[dpath.scala:66:30]
reg [4:0] wb_reg_wbaddr; // @[dpath.scala:67:30]
reg [31:0] wb_reg_target_pc; // @[dpath.scala:68:30]
assign tval_inst_ma = wb_reg_target_pc; // @[dpath.scala:57:27, :68:30]
reg wb_reg_mem; // @[dpath.scala:69:34]
wire _wb_hazard_stall_T_18; // @[dpath.scala:125:73]
assign io_dat_wb_hazard_stall_0 = wb_hazard_stall; // @[dpath.scala:50:7, :71:31]
wire _wb_dmiss_stall_T_4; // @[dpath.scala:227:64]
wire wb_dmiss_stall; // @[dpath.scala:72:31]
wire [31:0] _exe_brjmp_target_T_1; // @[dpath.scala:200:31]
wire [31:0] exe_brjmp_target; // @[dpath.scala:76:34]
wire [31:0] _exe_jump_reg_target_T_1; // @[dpath.scala:201:44]
wire [31:0] exe_jump_reg_target; // @[dpath.scala:77:34]
wire [31:0] exception_target; // @[dpath.scala:78:34]
wire _io_imem_resp_ready_T = ~wb_hazard_stall; // @[dpath.scala:71:31, :80:26]
wire _io_imem_resp_ready_T_1 = ~wb_dmiss_stall; // @[dpath.scala:72:31, :80:46]
assign _io_imem_resp_ready_T_2 = _io_imem_resp_ready_T & _io_imem_resp_ready_T_1; // @[dpath.scala:80:{26,43,46}]
assign io_imem_resp_ready_0 = _io_imem_resp_ready_T_2; // @[dpath.scala:50:7, :80:43]
wire _take_pc_T = io_ctl_pc_sel_0 == 3'h4; // @[dpath.scala:50:7, :83:36]
wire _T_25 = io_ctl_pc_sel_0 == 3'h3; // @[dpath.scala:50:7, :84:36]
wire _take_pc_T_1; // @[dpath.scala:84:36]
assign _take_pc_T_1 = _T_25; // @[dpath.scala:84:36]
wire _io_dat_inst_misaligned_T_8; // @[dpath.scala:91:79]
assign _io_dat_inst_misaligned_T_8 = _T_25; // @[dpath.scala:84:36, :91:79]
wire _exe_target_pc_T; // @[dpath.scala:93:43]
assign _exe_target_pc_T = _T_25; // @[dpath.scala:84:36, :93:43]
wire [31:0] _take_pc_T_2 = _take_pc_T_1 ? exe_jump_reg_target : exe_brjmp_target; // @[dpath.scala:76:34, :77:34, :84:{21,36}]
assign take_pc = _take_pc_T ? exception_target : _take_pc_T_2; // @[dpath.scala:78:34, :83:{21,36}, :84:21]
assign io_imem_req_bits_pc_0 = take_pc; // @[dpath.scala:50:7, :83:21]
wire [1:0] _io_dat_inst_misaligned_T = exe_brjmp_target[1:0]; // @[dpath.scala:76:34, :90:48]
wire _io_dat_inst_misaligned_T_1 = |_io_dat_inst_misaligned_T; // @[dpath.scala:90:{48,55}]
wire _io_dat_inst_misaligned_T_2 = io_ctl_pc_sel_0 == 3'h1; // @[dpath.scala:50:7, :90:80]
wire _io_dat_inst_misaligned_T_3 = io_ctl_pc_sel_0 == 3'h2; // @[dpath.scala:50:7, :90:107]
wire _io_dat_inst_misaligned_T_4 = _io_dat_inst_misaligned_T_2 | _io_dat_inst_misaligned_T_3; // @[dpath.scala:90:{80,90,107}]
wire _io_dat_inst_misaligned_T_5 = _io_dat_inst_misaligned_T_1 & _io_dat_inst_misaligned_T_4; // @[dpath.scala:90:{55,62,90}]
wire [1:0] _io_dat_inst_misaligned_T_6 = exe_jump_reg_target[1:0]; // @[dpath.scala:77:34, :91:51]
wire _io_dat_inst_misaligned_T_7 = |_io_dat_inst_misaligned_T_6; // @[dpath.scala:91:{51,58}]
wire _io_dat_inst_misaligned_T_9 = _io_dat_inst_misaligned_T_7 & _io_dat_inst_misaligned_T_8; // @[dpath.scala:91:{58,62,79}]
wire _io_dat_inst_misaligned_T_10 = _io_dat_inst_misaligned_T_5 | _io_dat_inst_misaligned_T_9; // @[dpath.scala:90:{62,118}, :91:62]
assign _io_dat_inst_misaligned_T_11 = _io_dat_inst_misaligned_T_10 & io_imem_resp_valid_0; // @[dpath.scala:50:7, :90:118, :91:91]
assign io_dat_inst_misaligned_0 = _io_dat_inst_misaligned_T_11; // @[dpath.scala:50:7, :91:91]
wire [31:0] exe_target_pc = _exe_target_pc_T ? exe_jump_reg_target : exe_brjmp_target; // @[dpath.scala:76:34, :77:34, :93:{27,43}]
wire [4:0] exe_rs1_addr = io_imem_resp_bits_inst_0[19:15]; // @[dpath.scala:50:7, :105:31]
wire [4:0] imm_z = io_imem_resp_bits_inst_0[19:15]; // @[dpath.scala:50:7, :105:31, :159:24]
wire [4:0] exe_rs2_addr = io_imem_resp_bits_inst_0[24:20]; // @[dpath.scala:50:7, :106:31]
wire [4:0] exe_wbaddr = io_imem_resp_bits_inst_0[11:7]; // @[dpath.scala:50:7, :107:31]
wire [4:0] _imm_s_T_1 = io_imem_resp_bits_inst_0[11:7]; // @[dpath.scala:50:7, :107:31, :155:46]
wire [31:0] _wb_wbdata_T_7; // @[Mux.scala:126:16]
wire [31:0] wb_wbdata; // @[dpath.scala:109:27]
reg [1:0] count; // @[dpath.scala:115:26]
wire _T = wb_reg_wbaddr == exe_rs1_addr; // @[dpath.scala:67:30, :105:31, :116:47]
wire _wb_hazard_stall_T; // @[dpath.scala:123:42]
assign _wb_hazard_stall_T = _T; // @[dpath.scala:116:47, :123:42]
wire _exe_rs1_data_T; // @[dpath.scala:171:44]
assign _exe_rs1_data_T = _T; // @[dpath.scala:116:47, :171:44]
wire _io_dmem_req_bits_fcn_T_1; // @[dpath.scala:219:79]
assign _io_dmem_req_bits_fcn_T_1 = _T; // @[dpath.scala:116:47, :219:79]
wire _wb_hazard_stall_T_16 = count != 2'h2; // @[dpath.scala:115:26, :120:18, :125:103]
wire [2:0] _count_T = {1'h0, count} + 3'h1; // @[dpath.scala:115:26, :121:25]
wire [1:0] _count_T_1 = _count_T[1:0]; // @[dpath.scala:121:25]
wire _wb_hazard_stall_T_1 = |exe_rs1_addr; // @[dpath.scala:105:31, :116:82, :123:77]
wire _wb_hazard_stall_T_2 = _wb_hazard_stall_T & _wb_hazard_stall_T_1; // @[dpath.scala:123:{42,60,77}]
wire _wb_hazard_stall_T_3 = _wb_hazard_stall_T_2 & wb_reg_ctrl_rf_wen; // @[dpath.scala:63:30, :123:{60,86}]
wire _wb_hazard_stall_T_4 = ~wb_reg_ctrl_bypassable; // @[dpath.scala:63:30, :116:116, :123:111]
wire _wb_hazard_stall_T_5 = _wb_hazard_stall_T_3 & _wb_hazard_stall_T_4; // @[dpath.scala:123:{86,108,111}]
wire _GEN = wb_reg_wbaddr == exe_rs2_addr; // @[dpath.scala:67:30, :106:31, :124:42]
wire _wb_hazard_stall_T_6; // @[dpath.scala:124:42]
assign _wb_hazard_stall_T_6 = _GEN; // @[dpath.scala:124:42]
wire _exe_rs2_data_T; // @[dpath.scala:174:44]
assign _exe_rs2_data_T = _GEN; // @[dpath.scala:124:42, :174:44]
wire _wb_hazard_stall_T_7 = |exe_rs2_addr; // @[dpath.scala:106:31, :124:77]
wire _wb_hazard_stall_T_8 = _wb_hazard_stall_T_6 & _wb_hazard_stall_T_7; // @[dpath.scala:124:{42,60,77}]
wire _wb_hazard_stall_T_9 = _wb_hazard_stall_T_8 & wb_reg_ctrl_rf_wen; // @[dpath.scala:63:30, :124:{60,86}]
wire _wb_hazard_stall_T_10 = ~wb_reg_ctrl_bypassable; // @[dpath.scala:63:30, :116:116, :124:111]
wire _wb_hazard_stall_T_11 = _wb_hazard_stall_T_9 & _wb_hazard_stall_T_10; // @[dpath.scala:124:{86,108,111}]
wire _wb_hazard_stall_T_12 = _wb_hazard_stall_T_5 | _wb_hazard_stall_T_11; // @[dpath.scala:123:{108,136}, :124:108]
reg wb_hazard_stall_REG; // @[dpath.scala:125:54]
wire _wb_hazard_stall_T_13 = ~wb_hazard_stall_REG; // @[dpath.scala:125:{46,54}]
wire _wb_hazard_stall_T_14 = io_ctl_dmem_val_0 & _wb_hazard_stall_T_13; // @[dpath.scala:50:7, :125:{43,46}]
wire _wb_hazard_stall_T_15 = _wb_hazard_stall_T_12 | _wb_hazard_stall_T_14; // @[dpath.scala:123:136, :124:136, :125:43]
wire _wb_hazard_stall_T_17 = io_ctl_dmem_val_0 & _wb_hazard_stall_T_16; // @[dpath.scala:50:7, :125:{93,103}]
assign _wb_hazard_stall_T_18 = _wb_hazard_stall_T_15 | _wb_hazard_stall_T_17; // @[dpath.scala:124:136, :125:{73,93}]
assign wb_hazard_stall = _wb_hazard_stall_T_18; // @[dpath.scala:71:31, :125:73]
wire _rf_rs1_data_T = |exe_rs1_addr; // @[dpath.scala:105:31, :116:82, :149:40]
wire [31:0] rf_rs1_data = _rf_rs1_data_T ? _regfile_ext_R1_data : 32'h0; // @[dpath.scala:135:21, :149:{25,40}]
wire _rf_rs2_data_T = |exe_rs2_addr; // @[dpath.scala:106:31, :124:77, :150:40]
wire [31:0] rf_rs2_data = _rf_rs2_data_T ? _regfile_ext_R0_data : 32'h0; // @[dpath.scala:135:21, :150:{25,40}]
wire [11:0] imm_i = io_imem_resp_bits_inst_0[31:20]; // @[dpath.scala:50:7, :154:24]
wire [11:0] _wb_reg_csr_addr_T = io_imem_resp_bits_inst_0[31:20]; // @[dpath.scala:50:7, :154:24, :249:37]
wire [6:0] _imm_s_T = io_imem_resp_bits_inst_0[31:25]; // @[dpath.scala:50:7, :155:28]
wire [11:0] imm_s = {_imm_s_T, _imm_s_T_1}; // @[dpath.scala:155:{19,28,46}]
wire _imm_b_T = io_imem_resp_bits_inst_0[31]; // @[dpath.scala:50:7, :156:28]
wire _imm_j_T = io_imem_resp_bits_inst_0[31]; // @[dpath.scala:50:7, :156:28, :158:28]
wire _imm_b_T_1 = io_imem_resp_bits_inst_0[7]; // @[dpath.scala:50:7, :156:42]
wire [5:0] _imm_b_T_2 = io_imem_resp_bits_inst_0[30:25]; // @[dpath.scala:50:7, :156:55]
wire [3:0] _imm_b_T_3 = io_imem_resp_bits_inst_0[11:8]; // @[dpath.scala:50:7, :156:72]
wire [9:0] imm_b_lo = {_imm_b_T_2, _imm_b_T_3}; // @[dpath.scala:156:{19,55,72}]
wire [1:0] imm_b_hi = {_imm_b_T, _imm_b_T_1}; // @[dpath.scala:156:{19,28,42}]
wire [11:0] imm_b = {imm_b_hi, imm_b_lo}; // @[dpath.scala:156:19]
wire [19:0] _imm_u_T = io_imem_resp_bits_inst_0[31:12]; // @[dpath.scala:50:7, :157:28]
wire [31:0] imm_u = {_imm_u_T, 12'h0}; // @[dpath.scala:157:{19,28}]
wire [7:0] _imm_j_T_1 = io_imem_resp_bits_inst_0[19:12]; // @[dpath.scala:50:7, :158:42]
wire _imm_j_T_2 = io_imem_resp_bits_inst_0[20]; // @[dpath.scala:50:7, :158:59]
wire [9:0] _imm_j_T_3 = io_imem_resp_bits_inst_0[30:21]; // @[dpath.scala:50:7, :158:73]
wire [10:0] imm_j_lo = {_imm_j_T_2, _imm_j_T_3}; // @[dpath.scala:158:{19,59,73}]
wire [8:0] imm_j_hi = {_imm_j_T, _imm_j_T_1}; // @[dpath.scala:158:{19,28,42}]
wire [19:0] imm_j = {imm_j_hi, imm_j_lo}; // @[dpath.scala:158:19]
wire _imm_i_sext_T = imm_i[11]; // @[dpath.scala:154:24, :162:38]
wire [19:0] _imm_i_sext_T_1 = {20{_imm_i_sext_T}}; // @[dpath.scala:162:{29,38}]
wire [31:0] imm_i_sext = {_imm_i_sext_T_1, imm_i}; // @[dpath.scala:154:24, :162:{24,29}]
wire _imm_s_sext_T = imm_s[11]; // @[dpath.scala:155:19, :163:38]
wire [19:0] _imm_s_sext_T_1 = {20{_imm_s_sext_T}}; // @[dpath.scala:163:{29,38}]
wire [31:0] imm_s_sext = {_imm_s_sext_T_1, imm_s}; // @[dpath.scala:155:19, :163:{24,29}]
wire _imm_b_sext_T = imm_b[11]; // @[dpath.scala:156:19, :164:38]
wire [18:0] _imm_b_sext_T_1 = {19{_imm_b_sext_T}}; // @[dpath.scala:164:{29,38}]
wire [30:0] imm_b_sext_hi = {_imm_b_sext_T_1, imm_b}; // @[dpath.scala:156:19, :164:{24,29}]
wire [31:0] imm_b_sext = {imm_b_sext_hi, 1'h0}; // @[dpath.scala:164:24]
wire _imm_j_sext_T = imm_j[19]; // @[dpath.scala:158:19, :165:38]
wire [10:0] _imm_j_sext_T_1 = {11{_imm_j_sext_T}}; // @[dpath.scala:165:{29,38}]
wire [30:0] imm_j_sext_hi = {_imm_j_sext_T_1, imm_j}; // @[dpath.scala:158:19, :165:{24,29}]
wire [31:0] imm_j_sext = {imm_j_sext_hi, 1'h0}; // @[dpath.scala:165:24]
wire _exe_rs1_data_T_1 = |exe_rs1_addr; // @[dpath.scala:105:31, :116:82, :171:79]
wire _exe_rs1_data_T_2 = _exe_rs1_data_T & _exe_rs1_data_T_1; // @[dpath.scala:171:{44,62,79}]
wire _exe_rs1_data_T_3 = _exe_rs1_data_T_2 & wb_reg_ctrl_rf_wen; // @[dpath.scala:63:30, :171:{62,88}]
wire _exe_rs1_data_T_4 = _exe_rs1_data_T_3 & wb_reg_ctrl_bypassable; // @[dpath.scala:63:30, :171:{88,110}]
wire [31:0] exe_rs1_data = _exe_rs1_data_T_4 ? wb_reg_alu : rf_rs1_data; // @[Mux.scala:126:16]
wire [31:0] _io_dat_br_lt_T = exe_rs1_data; // @[Mux.scala:126:16]
wire _exe_rs2_data_T_1 = |exe_rs2_addr; // @[dpath.scala:106:31, :124:77, :174:79]
wire _exe_rs2_data_T_2 = _exe_rs2_data_T & _exe_rs2_data_T_1; // @[dpath.scala:174:{44,62,79}]
wire _exe_rs2_data_T_3 = _exe_rs2_data_T_2 & wb_reg_ctrl_rf_wen; // @[dpath.scala:63:30, :174:{62,88}]
wire _exe_rs2_data_T_4 = _exe_rs2_data_T_3 & wb_reg_ctrl_bypassable; // @[dpath.scala:63:30, :174:{88,110}]
assign exe_rs2_data = _exe_rs2_data_T_4 ? wb_reg_alu : rf_rs2_data; // @[Mux.scala:126:16]
assign io_dmem_req_bits_data_0 = exe_rs2_data; // @[Mux.scala:126:16]
wire [31:0] _io_dat_br_lt_T_1 = exe_rs2_data; // @[Mux.scala:126:16]
wire _exe_alu_op1_T = io_ctl_op1_sel_0 == 2'h2; // @[dpath.scala:50:7, :179:41]
wire _exe_alu_op1_T_1 = io_ctl_op1_sel_0 == 2'h1; // @[dpath.scala:50:7, :180:41]
wire [31:0] _exe_alu_op1_T_2 = _exe_alu_op1_T_1 ? imm_u : exe_rs1_data; // @[Mux.scala:126:16]
wire [31:0] exe_alu_op1 = _exe_alu_op1_T ? {27'h0, imm_z} : _exe_alu_op1_T_2; // @[dpath.scala:159:24, :179:{25,41}, :180:25]
wire _exe_alu_op2_T = io_ctl_op2_sel_0 == 2'h1; // @[dpath.scala:50:7, :183:41]
wire _exe_alu_op2_T_1 = &io_ctl_op2_sel_0; // @[dpath.scala:50:7, :184:41]
wire _exe_alu_op2_T_2 = io_ctl_op2_sel_0 == 2'h2; // @[dpath.scala:50:7, :185:41]
wire [31:0] _exe_alu_op2_T_3 = _exe_alu_op2_T_2 ? imm_s_sext : exe_rs2_data; // @[Mux.scala:126:16]
wire [31:0] _exe_alu_op2_T_4 = _exe_alu_op2_T_1 ? io_imem_resp_bits_pc_0 : _exe_alu_op2_T_3; // @[dpath.scala:50:7, :184:{25,41}, :185:25]
wire [31:0] exe_alu_op2 = _exe_alu_op2_T ? imm_i_sext : _exe_alu_op2_T_4; // @[dpath.scala:162:24, :183:{25,41}, :184:25]
wire [31:0] imm_brjmp = io_ctl_brjmp_sel_0 ? imm_j_sext : imm_b_sext; // @[dpath.scala:50:7, :164:24, :165:24, :199:23]
wire [32:0] _exe_brjmp_target_T = {1'h0, io_imem_resp_bits_pc_0} + {1'h0, imm_brjmp}; // @[dpath.scala:50:7, :199:23, :200:31]
assign _exe_brjmp_target_T_1 = _exe_brjmp_target_T[31:0]; // @[dpath.scala:200:31]
assign exe_brjmp_target = _exe_brjmp_target_T_1; // @[dpath.scala:76:34, :200:31]
assign _exe_jump_reg_target_T_1 = _alu_io_adder_out & 32'hFFFFFFFE; // @[dpath.scala:190:20, :201:44]
assign exe_jump_reg_target = _exe_jump_reg_target_T_1; // @[dpath.scala:77:34, :201:44]
assign _io_dat_br_eq_T = exe_rs1_data == exe_rs2_data; // @[Mux.scala:126:16]
assign io_dat_br_eq_0 = _io_dat_br_eq_T; // @[dpath.scala:50:7, :205:35]
assign _io_dat_br_lt_T_2 = $signed(_io_dat_br_lt_T) < $signed(_io_dat_br_lt_T_1); // @[dpath.scala:206:{35,42,57}]
assign io_dat_br_lt_0 = _io_dat_br_lt_T_2; // @[dpath.scala:50:7, :206:42]
assign _io_dat_br_ltu_T = exe_rs1_data < exe_rs2_data; // @[Mux.scala:126:16]
assign io_dat_br_ltu_0 = _io_dat_br_ltu_T; // @[dpath.scala:50:7, :207:42]
wire [2:0] mem_address_low = _alu_io_out[2:0]; // @[dpath.scala:190:20, :211:37]
wire [2:0] misaligned_mask; // @[dpath.scala:212:30]
wire [3:0] _misaligned_mask_T = {1'h0, io_ctl_dmem_typ_0} - 4'h1; // @[dpath.scala:50:7, :213:54]
wire [2:0] _misaligned_mask_T_1 = _misaligned_mask_T[2:0]; // @[dpath.scala:213:54]
wire [1:0] _misaligned_mask_T_2 = _misaligned_mask_T_1[1:0]; // @[dpath.scala:213:{54,60}]
wire [5:0] _misaligned_mask_T_3 = 6'h7 << _misaligned_mask_T_2; // @[dpath.scala:213:{34,60}]
wire [5:0] _misaligned_mask_T_4 = ~_misaligned_mask_T_3; // @[dpath.scala:213:{23,34}]
assign misaligned_mask = _misaligned_mask_T_4[2:0]; // @[dpath.scala:212:30, :213:{20,23}]
wire [2:0] _io_dat_data_misaligned_T = misaligned_mask & mem_address_low; // @[dpath.scala:211:37, :212:30, :214:47]
wire _io_dat_data_misaligned_T_1 = |_io_dat_data_misaligned_T; // @[dpath.scala:214:{47,66}]
assign _io_dat_data_misaligned_T_2 = _io_dat_data_misaligned_T_1 & io_ctl_dmem_val_0; // @[dpath.scala:50:7, :214:{66,70}]
assign io_dat_data_misaligned_0 = _io_dat_data_misaligned_T_2; // @[dpath.scala:50:7, :214:70]
wire _io_dmem_req_valid_T = ~io_dat_data_misaligned_0; // @[dpath.scala:50:7, :217:48]
wire _io_dmem_req_valid_T_1 = io_ctl_dmem_val_0 & _io_dmem_req_valid_T; // @[dpath.scala:50:7, :217:{45,48}]
wire _io_dmem_req_valid_T_2 = ~wb_hazard_stall; // @[dpath.scala:71:31, :80:26, :217:75]
assign _io_dmem_req_valid_T_3 = _io_dmem_req_valid_T_1 & _io_dmem_req_valid_T_2; // @[dpath.scala:217:{45,72,75}]
assign io_dmem_req_valid_0 = _io_dmem_req_valid_T_3; // @[dpath.scala:50:7, :217:72]
wire _io_dmem_req_bits_fcn_T = io_ctl_dmem_fcn_0 & io_imem_resp_valid_0; // @[dpath.scala:50:7, :219:48]
wire _io_dmem_req_bits_fcn_T_2 = |exe_rs1_addr; // @[dpath.scala:105:31, :116:82, :219:114]
wire _io_dmem_req_bits_fcn_T_3 = _io_dmem_req_bits_fcn_T_1 & _io_dmem_req_bits_fcn_T_2; // @[dpath.scala:219:{79,97,114}]
wire _io_dmem_req_bits_fcn_T_4 = _io_dmem_req_bits_fcn_T_3 & wb_reg_ctrl_rf_wen; // @[dpath.scala:63:30, :219:{97,123}]
wire _io_dmem_req_bits_fcn_T_5 = ~wb_reg_ctrl_bypassable; // @[dpath.scala:63:30, :116:116, :219:148]
wire _io_dmem_req_bits_fcn_T_6 = _io_dmem_req_bits_fcn_T_4 & _io_dmem_req_bits_fcn_T_5; // @[dpath.scala:219:{123,145,148}]
wire _io_dmem_req_bits_fcn_T_7 = ~_io_dmem_req_bits_fcn_T_6; // @[dpath.scala:219:{62,145}]
assign _io_dmem_req_bits_fcn_T_8 = _io_dmem_req_bits_fcn_T & _io_dmem_req_bits_fcn_T_7; // @[dpath.scala:219:{48,60,62}]
assign io_dmem_req_bits_fcn_0 = _io_dmem_req_bits_fcn_T_8; // @[dpath.scala:50:7, :219:60]
wire _wb_dmiss_stall_T = ~io_dmem_req_ready_0; // @[dpath.scala:50:7, :227:23]
wire _wb_dmiss_stall_T_1 = _wb_dmiss_stall_T & io_dmem_req_valid_0; // @[dpath.scala:50:7, :227:{23,42}]
wire _wb_dmiss_stall_T_2 = ~io_dmem_resp_valid_0; // @[dpath.scala:50:7, :227:82]
wire _wb_dmiss_stall_T_3 = wb_reg_mem & _wb_dmiss_stall_T_2; // @[dpath.scala:69:34, :227:{79,82}]
assign _wb_dmiss_stall_T_4 = _wb_dmiss_stall_T_1 | _wb_dmiss_stall_T_3; // @[dpath.scala:227:{42,64,79}]
assign wb_dmiss_stall = _wb_dmiss_stall_T_4; // @[dpath.scala:72:31, :227:64]
wire [31:0] _csr_io_decode_0_inst_T = {wb_reg_csr_addr, 20'h0}; // @[dpath.scala:66:30, :261:47]
wire [11:0] _csr_io_rw_addr_T = wb_reg_inst[31:20]; // @[dpath.scala:61:34, :262:35]
wire [2:0] _csr_io_rw_cmd_T = wb_dmiss_stall ? 3'h0 : wb_reg_ctrl_csr_cmd; // @[dpath.scala:63:30, :72:31, :264:27]
wire _csr_io_retire_T = ~io_ctl_exception_0; // @[dpath.scala:50:7, :144:78, :267:40]
wire _csr_io_retire_T_1 = wb_reg_valid & _csr_io_retire_T; // @[dpath.scala:62:34, :267:{37,40}]
wire _csr_io_tval_T = io_ctl_exception_cause_0 == 32'h2; // @[dpath.scala:50:7, :276:43]
wire _csr_io_tval_T_1 = io_ctl_exception_cause_0 == 32'h0; // @[dpath.scala:50:7, :277:43]
wire _csr_io_tval_T_2 = io_ctl_exception_cause_0 == 32'h6; // @[dpath.scala:50:7, :278:43]
wire _csr_io_tval_T_3 = io_ctl_exception_cause_0 == 32'h4; // @[dpath.scala:50:7, :279:43]
wire [31:0] _csr_io_tval_T_4 = _csr_io_tval_T_3 ? tval_data_ma : 32'h0; // @[Mux.scala:126:16]
wire [31:0] _csr_io_tval_T_5 = _csr_io_tval_T_2 ? tval_data_ma : _csr_io_tval_T_4; // @[Mux.scala:126:16]
wire [31:0] _csr_io_tval_T_6 = _csr_io_tval_T_1 ? tval_inst_ma : _csr_io_tval_T_5; // @[Mux.scala:126:16]
wire [31:0] _csr_io_tval_T_7 = _csr_io_tval_T ? wb_reg_inst : _csr_io_tval_T_6; // @[Mux.scala:126:16]
reg reg_interrupt_flag; // @[dpath.scala:283:36]
wire _interrupt_edge_T = ~reg_interrupt_flag; // @[dpath.scala:283:36, :284:45]
assign interrupt_edge = _csr_io_interrupt & _interrupt_edge_T; // @[dpath.scala:259:20, :284:{42,45}]
assign io_dat_csr_interrupt_0 = interrupt_edge; // @[dpath.scala:50:7, :284:42]
wire [31:0] _csr_io_cause_T = io_ctl_exception_0 ? io_ctl_exception_cause_0 : _csr_io_interrupt_cause; // @[dpath.scala:50:7, :259:20, :289:23]
wire _wb_wbdata_T = wb_reg_ctrl_wb_sel == 2'h0; // @[dpath.scala:63:30, :301:39]
wire _wb_wbdata_T_1 = wb_reg_ctrl_wb_sel == 2'h1; // @[dpath.scala:63:30, :302:39]
wire _wb_wbdata_T_2 = wb_reg_ctrl_wb_sel == 2'h2; // @[dpath.scala:63:30, :303:39]
wire _wb_wbdata_T_3 = &wb_reg_ctrl_wb_sel; // @[dpath.scala:63:30, :304:39]
wire [31:0] _wb_wbdata_T_4 = _wb_wbdata_T_3 ? _csr_io_rw_rdata : wb_reg_alu; // @[Mux.scala:126:16]
wire [31:0] _wb_wbdata_T_5 = _wb_wbdata_T_2 ? io_imem_resp_bits_pc_0 : _wb_wbdata_T_4; // @[Mux.scala:126:16]
wire [31:0] _wb_wbdata_T_6 = _wb_wbdata_T_1 ? io_dmem_resp_bits_data_0 : _wb_wbdata_T_5; // @[Mux.scala:126:16]
assign _wb_wbdata_T_7 = _wb_wbdata_T ? wb_reg_alu : _wb_wbdata_T_6; // @[Mux.scala:126:16]
assign wb_wbdata = _wb_wbdata_T_7; // @[Mux.scala:126:16]
wire _debug_wb_inst_T = wb_hazard_stall | io_ctl_exe_kill_0; // @[dpath.scala:50:7, :71:31, :310:53]
wire _debug_wb_inst_T_1 = ~io_imem_resp_valid_0; // @[dpath.scala:50:7, :310:75]
wire _debug_wb_inst_T_2 = _debug_wb_inst_T | _debug_wb_inst_T_1; // @[dpath.scala:310:{53,72,75}]
wire [31:0] _debug_wb_inst_T_3 = _debug_wb_inst_T_2 ? 32'h4033 : io_imem_resp_bits_inst_0; // @[dpath.scala:50:7, :310:{35,72}]
reg [31:0] debug_wb_inst; // @[dpath.scala:310:31]
reg [4:0] REG; // @[dpath.scala:319:14]
reg [31:0] REG_1; // @[dpath.scala:320:14]
reg [4:0] REG_2; // @[dpath.scala:321:14]
reg [31:0] REG_3; // @[dpath.scala:322:14] |
Generate the Verilog code corresponding to this FIRRTL code module MSHR_77 :
input clock : Clock
input reset : Reset
output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, status : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>, way : UInt<4>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<11>, tag : UInt<9>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}}
regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}, clock
regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}, clock
when meta_valid :
node _T = eq(meta.state, UInt<2>(0h0))
when _T :
node _T_1 = orr(meta.clients)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _T_6 = eq(meta.dirty, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = eq(meta.state, UInt<2>(0h1))
when _T_10 :
node _T_11 = eq(meta.dirty, UInt<1>(0h0))
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2
assert(clock, _T_11, UInt<1>(0h1), "") : assert_2
node _T_15 = eq(meta.state, UInt<2>(0h2))
when _T_15 :
node _T_16 = orr(meta.clients)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3
assert(clock, _T_16, UInt<1>(0h1), "") : assert_3
node _T_20 = sub(meta.clients, UInt<1>(0h1))
node _T_21 = tail(_T_20, 1)
node _T_22 = and(meta.clients, _T_21)
node _T_23 = eq(_T_22, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4
assert(clock, _T_23, UInt<1>(0h1), "") : assert_4
node _T_27 = eq(meta.state, UInt<2>(0h3))
when _T_27 :
skip
regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1)
regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1)
regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1)
reg sink : UInt<3>, clock
reg gotT : UInt<1>, clock
reg bad_grant : UInt<1>, clock
reg probes_done : UInt<1>, clock
reg probes_toN : UInt<1>, clock
reg probes_noT : UInt<1>, clock
node _T_28 = neq(meta.state, UInt<2>(0h0))
node _T_29 = and(meta_valid, _T_28)
node _T_30 = eq(io.nestedwb.set, request.set)
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.nestedwb.tag, meta.tag)
node _T_33 = and(_T_31, _T_32)
when _T_33 :
when io.nestedwb.b_clr_dirty :
connect meta.dirty, UInt<1>(0h0)
when io.nestedwb.c_set_dirty :
connect meta.dirty, UInt<1>(0h1)
when io.nestedwb.b_toB :
connect meta.state, UInt<2>(0h1)
when io.nestedwb.b_toN :
connect meta.hit, UInt<1>(0h0)
connect io.status.valid, request_valid
connect io.status.bits.set, request.set
connect io.status.bits.tag, request.tag
connect io.status.bits.way, meta.way
node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0))
node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0))
node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2)
node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0))
node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4)
node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6)
node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7)
connect io.status.bits.blockB, _io_status_bits_blockB_T_8
node _io_status_bits_nestB_T = and(meta_valid, w_releaseack)
node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast)
node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast)
node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3)
connect io.status.bits.nestB, _io_status_bits_nestB_T_4
node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0))
connect io.status.bits.blockC, _io_status_bits_blockC_T
node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1)
node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0))
node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3)
node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4)
connect io.status.bits.nestC, _io_status_bits_nestC_T_5
node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0))
node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0))
node _T_36 = or(_T_34, _T_35)
node _T_37 = asUInt(reset)
node _T_38 = eq(_T_37, UInt<1>(0h0))
when _T_38 :
node _T_39 = eq(_T_36, UInt<1>(0h0))
when _T_39 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5
assert(clock, _T_36, UInt<1>(0h1), "") : assert_5
node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0))
node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0))
node _T_42 = or(_T_40, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6
assert(clock, _T_42, UInt<1>(0h1), "") : assert_6
node _no_wait_T = and(w_rprobeacklast, w_releaseack)
node _no_wait_T_1 = and(_no_wait_T, w_grantlast)
node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast)
node no_wait = and(_no_wait_T_2, w_grantack)
node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0))
node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release)
node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe)
connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2
node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0))
node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1)
connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2
node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst)
node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0))
node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst)
node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3)
connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4
node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0))
node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack)
node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant)
connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2
node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0))
node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst)
connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1
node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0))
node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack)
connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1
node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst)
node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0))
node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait)
node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3)
connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4
connect io.schedule.bits.reload, no_wait
node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid)
node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid)
node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid)
node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid)
node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid)
node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid)
connect io.schedule.valid, _io_schedule_valid_T_5
when io.schedule.ready :
connect s_rprobe, UInt<1>(0h1)
when w_rprobeackfirst :
connect s_release, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
node _T_46 = and(s_release, s_pprobe)
when _T_46 :
connect s_acquire, UInt<1>(0h1)
when w_releaseack :
connect s_flush, UInt<1>(0h1)
when w_pprobeackfirst :
connect s_probeack, UInt<1>(0h1)
when w_grantfirst :
connect s_grantack, UInt<1>(0h1)
node _T_47 = and(w_pprobeack, w_grant)
when _T_47 :
connect s_execute, UInt<1>(0h1)
when no_wait :
connect s_writeback, UInt<1>(0h1)
when no_wait :
connect request_valid, UInt<1>(0h0)
connect meta_valid, UInt<1>(0h0)
wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}
connect final_meta_writeback, meta
node req_clientBit = eq(request.source, UInt<6>(0h28))
node _req_needT_T = bits(request.opcode, 2, 2)
node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0))
node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5))
node _req_needT_T_3 = eq(request.param, UInt<1>(0h1))
node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3)
node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4)
node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6))
node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7))
node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7)
node _req_needT_T_9 = neq(request.param, UInt<2>(0h0))
node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9)
node req_needT = or(_req_needT_T_5, _req_needT_T_10)
node _req_acquire_T = eq(request.opcode, UInt<3>(0h6))
node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7))
node req_acquire = or(_req_acquire_T, _req_acquire_T_1)
node _meta_no_clients_T = orr(meta.clients)
node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0))
node _req_promoteT_T = eq(meta.state, UInt<2>(0h3))
node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T)
node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT)
node req_promoteT = and(req_acquire, _req_promoteT_T_2)
node _T_48 = and(request.prio[2], UInt<1>(0h1))
when _T_48 :
node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0)
node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1
node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3))
node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2))
node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1)
node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state)
connect final_meta_writeback.state, _final_meta_writeback_state_T_3
node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1))
node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2))
node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1)
node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5))
node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3)
node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5)
node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7
connect final_meta_writeback.hit, UInt<1>(0h1)
else :
node _T_49 = and(request.control, UInt<1>(0h1))
when _T_49 :
when meta.hit :
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
node _final_meta_writeback_clients_T_8 = not(probes_toN)
node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9
connect final_meta_writeback.hit, UInt<1>(0h0)
else :
node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty)
node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2)
node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0))
node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4)
connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5
node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0))
node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1))
node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire)
node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state)
node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1))
node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state)
node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11)
node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state)
node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13)
node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15)
node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16)
connect final_meta_writeback.state, _final_meta_writeback_state_T_17
node _final_meta_writeback_clients_T_10 = not(probes_toN)
node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10)
node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0))
node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0))
node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14
connect final_meta_writeback.tag, request.tag
connect final_meta_writeback.hit, UInt<1>(0h1)
when bad_grant :
when meta.hit :
node _T_50 = eq(meta_valid, UInt<1>(0h0))
node _T_51 = eq(meta.state, UInt<2>(0h1))
node _T_52 = or(_T_50, _T_51)
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7
assert(clock, _T_52, UInt<1>(0h1), "") : assert_7
connect final_meta_writeback.hit, UInt<1>(0h1)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h1)
node _final_meta_writeback_clients_T_15 = not(probes_toN)
node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15)
connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16
else :
connect final_meta_writeback.hit, UInt<1>(0h0)
connect final_meta_writeback.dirty, UInt<1>(0h0)
connect final_meta_writeback.state, UInt<2>(0h0)
connect final_meta_writeback.clients, UInt<1>(0h0)
wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect invalid.dirty, UInt<1>(0h0)
connect invalid.state, UInt<2>(0h0)
connect invalid.clients, UInt<1>(0h0)
connect invalid.tag, UInt<1>(0h0)
node _honour_BtoT_T = and(meta.clients, req_clientBit)
node _honour_BtoT_T_1 = orr(_honour_BtoT_T)
node honour_BtoT = and(meta.hit, _honour_BtoT_T_1)
node _excluded_client_T = and(meta.hit, request.prio[0])
node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6))
node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7))
node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2)
node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4))
node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4)
node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5))
node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0))
node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7)
node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8)
node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0))
connect io.schedule.bits.a.bits.tag, request.tag
connect io.schedule.bits.a.bits.set, request.set
node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0))
connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1
node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6))
node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7))
node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2)
node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0))
node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4)
connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5
connect io.schedule.bits.a.bits.source, UInt<1>(0h0)
node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1)
node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2)
connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3
node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0))
node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag)
connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1
connect io.schedule.bits.b.bits.set, request.set
node _io_schedule_bits_b_bits_clients_T = not(excluded_client)
node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T)
connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1
node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6))
connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T
node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1))
node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1))
connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1
connect io.schedule.bits.c.bits.source, UInt<1>(0h0)
connect io.schedule.bits.c.bits.tag, meta.tag
connect io.schedule.bits.c.bits.set, request.set
connect io.schedule.bits.c.bits.way, meta.way
connect io.schedule.bits.c.bits.dirty, meta.dirty
connect io.schedule.bits.d.bits.set, request.set
connect io.schedule.bits.d.bits.put, request.put
connect io.schedule.bits.d.bits.offset, request.offset
connect io.schedule.bits.d.bits.tag, request.tag
connect io.schedule.bits.d.bits.source, request.source
connect io.schedule.bits.d.bits.size, request.size
connect io.schedule.bits.d.bits.param, request.param
connect io.schedule.bits.d.bits.opcode, request.opcode
connect io.schedule.bits.d.bits.control, request.control
connect io.schedule.bits.d.bits.prio, request.prio
node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0))
node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0))
node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1))
node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param)
node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param)
node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param)
node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4)
node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param)
node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6)
node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8)
connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9
connect io.schedule.bits.d.bits.sink, UInt<1>(0h0)
connect io.schedule.bits.d.bits.way, meta.way
connect io.schedule.bits.d.bits.bad, bad_grant
connect io.schedule.bits.e.bits.sink, sink
connect io.schedule.bits.x.bits.fail, UInt<1>(0h0)
connect io.schedule.bits.dir.bits.set, request.set
connect io.schedule.bits.dir.bits.way, meta.way
node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0))
wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}
connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag
connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients
connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state
connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty
node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE)
connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1
node _evict_T = eq(meta.hit, UInt<1>(0h0))
wire evict : UInt
connect evict, UInt<1>(0h0)
node evict_c = orr(meta.clients)
node _evict_T_1 = eq(UInt<2>(0h1), meta.state)
when _evict_T_1 :
node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1))
connect evict, _evict_out_T
else :
node _evict_T_2 = eq(UInt<2>(0h2), meta.state)
when _evict_T_2 :
node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect evict, _evict_out_T_1
else :
node _evict_T_3 = eq(UInt<2>(0h3), meta.state)
when _evict_T_3 :
node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3)
connect evict, _evict_out_T_4
else :
node _evict_T_4 = eq(UInt<2>(0h0), meta.state)
when _evict_T_4 :
connect evict, UInt<4>(0h8)
node _evict_T_5 = eq(_evict_T, UInt<1>(0h0))
when _evict_T_5 :
connect evict, UInt<4>(0h8)
wire before : UInt
connect before, UInt<1>(0h0)
node before_c = orr(meta.clients)
node _before_T = eq(UInt<2>(0h1), meta.state)
when _before_T :
node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1))
connect before, _before_out_T
else :
node _before_T_1 = eq(UInt<2>(0h2), meta.state)
when _before_T_1 :
node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect before, _before_out_T_1
else :
node _before_T_2 = eq(UInt<2>(0h3), meta.state)
when _before_T_2 :
node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3)
connect before, _before_out_T_4
else :
node _before_T_3 = eq(UInt<2>(0h0), meta.state)
when _before_T_3 :
connect before, UInt<4>(0h8)
node _before_T_4 = eq(meta.hit, UInt<1>(0h0))
when _before_T_4 :
connect before, UInt<4>(0h8)
wire after : UInt
connect after, UInt<1>(0h0)
node after_c = orr(final_meta_writeback.clients)
node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _after_T :
node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1))
connect after, _after_out_T
else :
node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _after_T_1 :
node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect after, _after_out_T_1
else :
node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _after_T_2 :
node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3)
connect after, _after_out_T_4
else :
node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _after_T_3 :
connect after, UInt<4>(0h8)
node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _after_T_4 :
connect after, UInt<4>(0h8)
node _T_56 = eq(s_release, UInt<1>(0h0))
node _T_57 = and(_T_56, w_rprobeackfirst)
node _T_58 = and(_T_57, io.schedule.ready)
when _T_58 :
node _T_59 = eq(evict, UInt<1>(0h1))
node _T_60 = eq(_T_59, UInt<1>(0h0))
node _T_61 = asUInt(reset)
node _T_62 = eq(_T_61, UInt<1>(0h0))
when _T_62 :
node _T_63 = eq(_T_60, UInt<1>(0h0))
when _T_63 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8
assert(clock, _T_60, UInt<1>(0h1), "") : assert_8
node _T_64 = eq(before, UInt<1>(0h1))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(_T_65, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9
assert(clock, _T_65, UInt<1>(0h1), "") : assert_9
node _T_69 = eq(evict, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10
assert(clock, _T_70, UInt<1>(0h1), "") : assert_10
node _T_74 = eq(before, UInt<1>(0h0))
node _T_75 = eq(_T_74, UInt<1>(0h0))
node _T_76 = asUInt(reset)
node _T_77 = eq(_T_76, UInt<1>(0h0))
when _T_77 :
node _T_78 = eq(_T_75, UInt<1>(0h0))
when _T_78 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11
assert(clock, _T_75, UInt<1>(0h1), "") : assert_11
node _T_79 = eq(evict, UInt<3>(0h7))
node _T_80 = eq(before, UInt<3>(0h7))
node _T_81 = eq(evict, UInt<3>(0h5))
node _T_82 = eq(before, UInt<3>(0h5))
node _T_83 = eq(evict, UInt<3>(0h4))
node _T_84 = eq(before, UInt<3>(0h4))
node _T_85 = eq(evict, UInt<3>(0h6))
node _T_86 = eq(before, UInt<3>(0h6))
node _T_87 = eq(evict, UInt<2>(0h3))
node _T_88 = eq(before, UInt<2>(0h3))
node _T_89 = eq(evict, UInt<2>(0h2))
node _T_90 = eq(before, UInt<2>(0h2))
node _T_91 = eq(s_writeback, UInt<1>(0h0))
node _T_92 = and(_T_91, no_wait)
node _T_93 = and(_T_92, io.schedule.ready)
when _T_93 :
node _T_94 = eq(before, UInt<4>(0h8))
node _T_95 = eq(after, UInt<1>(0h1))
node _T_96 = and(_T_94, _T_95)
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = asUInt(reset)
node _T_99 = eq(_T_98, UInt<1>(0h0))
when _T_99 :
node _T_100 = eq(_T_97, UInt<1>(0h0))
when _T_100 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12
assert(clock, _T_97, UInt<1>(0h1), "") : assert_12
node _T_101 = eq(before, UInt<4>(0h8))
node _T_102 = eq(after, UInt<1>(0h0))
node _T_103 = and(_T_101, _T_102)
node _T_104 = eq(_T_103, UInt<1>(0h0))
node _T_105 = asUInt(reset)
node _T_106 = eq(_T_105, UInt<1>(0h0))
when _T_106 :
node _T_107 = eq(_T_104, UInt<1>(0h0))
when _T_107 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13
assert(clock, _T_104, UInt<1>(0h1), "") : assert_13
node _T_108 = eq(before, UInt<4>(0h8))
node _T_109 = eq(after, UInt<3>(0h7))
node _T_110 = and(_T_108, _T_109)
node _T_111 = eq(before, UInt<4>(0h8))
node _T_112 = eq(after, UInt<3>(0h5))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14
assert(clock, _T_114, UInt<1>(0h1), "") : assert_14
node _T_118 = eq(before, UInt<4>(0h8))
node _T_119 = eq(after, UInt<3>(0h4))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15
assert(clock, _T_121, UInt<1>(0h1), "") : assert_15
node _T_125 = eq(before, UInt<4>(0h8))
node _T_126 = eq(after, UInt<3>(0h6))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(before, UInt<4>(0h8))
node _T_129 = eq(after, UInt<2>(0h3))
node _T_130 = and(_T_128, _T_129)
node _T_131 = eq(before, UInt<4>(0h8))
node _T_132 = eq(after, UInt<2>(0h2))
node _T_133 = and(_T_131, _T_132)
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = asUInt(reset)
node _T_136 = eq(_T_135, UInt<1>(0h0))
when _T_136 :
node _T_137 = eq(_T_134, UInt<1>(0h0))
when _T_137 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16
assert(clock, _T_134, UInt<1>(0h1), "") : assert_16
node _T_138 = eq(before, UInt<1>(0h1))
node _T_139 = eq(after, UInt<4>(0h8))
node _T_140 = and(_T_138, _T_139)
node _T_141 = eq(_T_140, UInt<1>(0h0))
node _T_142 = asUInt(reset)
node _T_143 = eq(_T_142, UInt<1>(0h0))
when _T_143 :
node _T_144 = eq(_T_141, UInt<1>(0h0))
when _T_144 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17
assert(clock, _T_141, UInt<1>(0h1), "") : assert_17
node _T_145 = eq(before, UInt<1>(0h1))
node _T_146 = eq(after, UInt<1>(0h0))
node _T_147 = and(_T_145, _T_146)
node _T_148 = eq(_T_147, UInt<1>(0h0))
node _T_149 = asUInt(reset)
node _T_150 = eq(_T_149, UInt<1>(0h0))
when _T_150 :
node _T_151 = eq(_T_148, UInt<1>(0h0))
when _T_151 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18
assert(clock, _T_148, UInt<1>(0h1), "") : assert_18
node _T_152 = eq(before, UInt<1>(0h1))
node _T_153 = eq(after, UInt<3>(0h7))
node _T_154 = and(_T_152, _T_153)
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = asUInt(reset)
node _T_157 = eq(_T_156, UInt<1>(0h0))
when _T_157 :
node _T_158 = eq(_T_155, UInt<1>(0h0))
when _T_158 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19
assert(clock, _T_155, UInt<1>(0h1), "") : assert_19
node _T_159 = eq(before, UInt<1>(0h1))
node _T_160 = eq(after, UInt<3>(0h5))
node _T_161 = and(_T_159, _T_160)
node _T_162 = eq(_T_161, UInt<1>(0h0))
node _T_163 = asUInt(reset)
node _T_164 = eq(_T_163, UInt<1>(0h0))
when _T_164 :
node _T_165 = eq(_T_162, UInt<1>(0h0))
when _T_165 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20
assert(clock, _T_162, UInt<1>(0h1), "") : assert_20
node _T_166 = eq(before, UInt<1>(0h1))
node _T_167 = eq(after, UInt<3>(0h4))
node _T_168 = and(_T_166, _T_167)
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21
assert(clock, _T_169, UInt<1>(0h1), "") : assert_21
node _T_173 = eq(before, UInt<1>(0h1))
node _T_174 = eq(after, UInt<3>(0h6))
node _T_175 = and(_T_173, _T_174)
node _T_176 = eq(_T_175, UInt<1>(0h0))
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_T_176, UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22
assert(clock, _T_176, UInt<1>(0h1), "") : assert_22
node _T_180 = eq(before, UInt<1>(0h1))
node _T_181 = eq(after, UInt<2>(0h3))
node _T_182 = and(_T_180, _T_181)
node _T_183 = eq(_T_182, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(before, UInt<1>(0h1))
node _T_188 = eq(after, UInt<2>(0h2))
node _T_189 = and(_T_187, _T_188)
node _T_190 = eq(_T_189, UInt<1>(0h0))
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(_T_190, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24
assert(clock, _T_190, UInt<1>(0h1), "") : assert_24
node _T_194 = eq(before, UInt<1>(0h0))
node _T_195 = eq(after, UInt<4>(0h8))
node _T_196 = and(_T_194, _T_195)
node _T_197 = eq(_T_196, UInt<1>(0h0))
node _T_198 = asUInt(reset)
node _T_199 = eq(_T_198, UInt<1>(0h0))
when _T_199 :
node _T_200 = eq(_T_197, UInt<1>(0h0))
when _T_200 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25
assert(clock, _T_197, UInt<1>(0h1), "") : assert_25
node _T_201 = eq(before, UInt<1>(0h0))
node _T_202 = eq(after, UInt<1>(0h1))
node _T_203 = and(_T_201, _T_202)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = asUInt(reset)
node _T_206 = eq(_T_205, UInt<1>(0h0))
when _T_206 :
node _T_207 = eq(_T_204, UInt<1>(0h0))
when _T_207 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26
assert(clock, _T_204, UInt<1>(0h1), "") : assert_26
node _T_208 = eq(before, UInt<1>(0h0))
node _T_209 = eq(after, UInt<3>(0h7))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(_T_210, UInt<1>(0h0))
node _T_212 = asUInt(reset)
node _T_213 = eq(_T_212, UInt<1>(0h0))
when _T_213 :
node _T_214 = eq(_T_211, UInt<1>(0h0))
when _T_214 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27
assert(clock, _T_211, UInt<1>(0h1), "") : assert_27
node _T_215 = eq(before, UInt<1>(0h0))
node _T_216 = eq(after, UInt<3>(0h5))
node _T_217 = and(_T_215, _T_216)
node _T_218 = eq(_T_217, UInt<1>(0h0))
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28
assert(clock, _T_218, UInt<1>(0h1), "") : assert_28
node _T_222 = eq(before, UInt<1>(0h0))
node _T_223 = eq(after, UInt<3>(0h6))
node _T_224 = and(_T_222, _T_223)
node _T_225 = eq(_T_224, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(before, UInt<1>(0h0))
node _T_230 = eq(after, UInt<3>(0h4))
node _T_231 = and(_T_229, _T_230)
node _T_232 = eq(_T_231, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(before, UInt<1>(0h0))
node _T_237 = eq(after, UInt<2>(0h3))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31
assert(clock, _T_239, UInt<1>(0h1), "") : assert_31
node _T_243 = eq(before, UInt<1>(0h0))
node _T_244 = eq(after, UInt<2>(0h2))
node _T_245 = and(_T_243, _T_244)
node _T_246 = eq(_T_245, UInt<1>(0h0))
node _T_247 = asUInt(reset)
node _T_248 = eq(_T_247, UInt<1>(0h0))
when _T_248 :
node _T_249 = eq(_T_246, UInt<1>(0h0))
when _T_249 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32
assert(clock, _T_246, UInt<1>(0h1), "") : assert_32
node _T_250 = eq(before, UInt<3>(0h7))
node _T_251 = eq(after, UInt<4>(0h8))
node _T_252 = and(_T_250, _T_251)
node _T_253 = eq(_T_252, UInt<1>(0h0))
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33
assert(clock, _T_253, UInt<1>(0h1), "") : assert_33
node _T_257 = eq(before, UInt<3>(0h7))
node _T_258 = eq(after, UInt<1>(0h1))
node _T_259 = and(_T_257, _T_258)
node _T_260 = eq(_T_259, UInt<1>(0h0))
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(_T_260, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34
assert(clock, _T_260, UInt<1>(0h1), "") : assert_34
node _T_264 = eq(before, UInt<3>(0h7))
node _T_265 = eq(after, UInt<1>(0h0))
node _T_266 = and(_T_264, _T_265)
node _T_267 = eq(_T_266, UInt<1>(0h0))
node _T_268 = asUInt(reset)
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(_T_267, UInt<1>(0h0))
when _T_270 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35
assert(clock, _T_267, UInt<1>(0h1), "") : assert_35
node _T_271 = eq(before, UInt<3>(0h7))
node _T_272 = eq(after, UInt<3>(0h5))
node _T_273 = and(_T_271, _T_272)
node _T_274 = eq(_T_273, UInt<1>(0h0))
node _T_275 = asUInt(reset)
node _T_276 = eq(_T_275, UInt<1>(0h0))
when _T_276 :
node _T_277 = eq(_T_274, UInt<1>(0h0))
when _T_277 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36
assert(clock, _T_274, UInt<1>(0h1), "") : assert_36
node _T_278 = eq(before, UInt<3>(0h7))
node _T_279 = eq(after, UInt<3>(0h6))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(before, UInt<3>(0h7))
node _T_282 = eq(after, UInt<3>(0h4))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37
assert(clock, _T_284, UInt<1>(0h1), "") : assert_37
node _T_288 = eq(before, UInt<3>(0h7))
node _T_289 = eq(after, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(before, UInt<3>(0h7))
node _T_292 = eq(after, UInt<2>(0h2))
node _T_293 = and(_T_291, _T_292)
node _T_294 = eq(_T_293, UInt<1>(0h0))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38
assert(clock, _T_294, UInt<1>(0h1), "") : assert_38
node _T_298 = eq(before, UInt<3>(0h5))
node _T_299 = eq(after, UInt<4>(0h8))
node _T_300 = and(_T_298, _T_299)
node _T_301 = eq(_T_300, UInt<1>(0h0))
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(_T_301, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39
assert(clock, _T_301, UInt<1>(0h1), "") : assert_39
node _T_305 = eq(before, UInt<3>(0h5))
node _T_306 = eq(after, UInt<1>(0h1))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(_T_307, UInt<1>(0h0))
node _T_309 = asUInt(reset)
node _T_310 = eq(_T_309, UInt<1>(0h0))
when _T_310 :
node _T_311 = eq(_T_308, UInt<1>(0h0))
when _T_311 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40
assert(clock, _T_308, UInt<1>(0h1), "") : assert_40
node _T_312 = eq(before, UInt<3>(0h5))
node _T_313 = eq(after, UInt<1>(0h0))
node _T_314 = and(_T_312, _T_313)
node _T_315 = eq(_T_314, UInt<1>(0h0))
node _T_316 = asUInt(reset)
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(_T_315, UInt<1>(0h0))
when _T_318 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41
assert(clock, _T_315, UInt<1>(0h1), "") : assert_41
node _T_319 = eq(before, UInt<3>(0h5))
node _T_320 = eq(after, UInt<3>(0h7))
node _T_321 = and(_T_319, _T_320)
node _T_322 = eq(before, UInt<3>(0h5))
node _T_323 = eq(after, UInt<3>(0h6))
node _T_324 = and(_T_322, _T_323)
node _T_325 = eq(before, UInt<3>(0h5))
node _T_326 = eq(after, UInt<3>(0h4))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(_T_327, UInt<1>(0h0))
node _T_329 = asUInt(reset)
node _T_330 = eq(_T_329, UInt<1>(0h0))
when _T_330 :
node _T_331 = eq(_T_328, UInt<1>(0h0))
when _T_331 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42
assert(clock, _T_328, UInt<1>(0h1), "") : assert_42
node _T_332 = eq(before, UInt<3>(0h5))
node _T_333 = eq(after, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(before, UInt<3>(0h5))
node _T_336 = eq(after, UInt<2>(0h2))
node _T_337 = and(_T_335, _T_336)
node _T_338 = eq(_T_337, UInt<1>(0h0))
node _T_339 = asUInt(reset)
node _T_340 = eq(_T_339, UInt<1>(0h0))
when _T_340 :
node _T_341 = eq(_T_338, UInt<1>(0h0))
when _T_341 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43
assert(clock, _T_338, UInt<1>(0h1), "") : assert_43
node _T_342 = eq(before, UInt<3>(0h6))
node _T_343 = eq(after, UInt<4>(0h8))
node _T_344 = and(_T_342, _T_343)
node _T_345 = eq(_T_344, UInt<1>(0h0))
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44
assert(clock, _T_345, UInt<1>(0h1), "") : assert_44
node _T_349 = eq(before, UInt<3>(0h6))
node _T_350 = eq(after, UInt<1>(0h1))
node _T_351 = and(_T_349, _T_350)
node _T_352 = eq(_T_351, UInt<1>(0h0))
node _T_353 = asUInt(reset)
node _T_354 = eq(_T_353, UInt<1>(0h0))
when _T_354 :
node _T_355 = eq(_T_352, UInt<1>(0h0))
when _T_355 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45
assert(clock, _T_352, UInt<1>(0h1), "") : assert_45
node _T_356 = eq(before, UInt<3>(0h6))
node _T_357 = eq(after, UInt<1>(0h0))
node _T_358 = and(_T_356, _T_357)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46
assert(clock, _T_359, UInt<1>(0h1), "") : assert_46
node _T_363 = eq(before, UInt<3>(0h6))
node _T_364 = eq(after, UInt<3>(0h7))
node _T_365 = and(_T_363, _T_364)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47
assert(clock, _T_366, UInt<1>(0h1), "") : assert_47
node _T_370 = eq(before, UInt<3>(0h6))
node _T_371 = eq(after, UInt<3>(0h5))
node _T_372 = and(_T_370, _T_371)
node _T_373 = eq(_T_372, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48
assert(clock, _T_373, UInt<1>(0h1), "") : assert_48
node _T_377 = eq(before, UInt<3>(0h6))
node _T_378 = eq(after, UInt<3>(0h4))
node _T_379 = and(_T_377, _T_378)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = asUInt(reset)
node _T_382 = eq(_T_381, UInt<1>(0h0))
when _T_382 :
node _T_383 = eq(_T_380, UInt<1>(0h0))
when _T_383 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49
assert(clock, _T_380, UInt<1>(0h1), "") : assert_49
node _T_384 = eq(before, UInt<3>(0h6))
node _T_385 = eq(after, UInt<2>(0h3))
node _T_386 = and(_T_384, _T_385)
node _T_387 = eq(_T_386, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50
assert(clock, _T_387, UInt<1>(0h1), "") : assert_50
node _T_391 = eq(before, UInt<3>(0h6))
node _T_392 = eq(after, UInt<2>(0h2))
node _T_393 = and(_T_391, _T_392)
node _T_394 = eq(before, UInt<3>(0h4))
node _T_395 = eq(after, UInt<4>(0h8))
node _T_396 = and(_T_394, _T_395)
node _T_397 = eq(_T_396, UInt<1>(0h0))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51
assert(clock, _T_397, UInt<1>(0h1), "") : assert_51
node _T_401 = eq(before, UInt<3>(0h4))
node _T_402 = eq(after, UInt<1>(0h1))
node _T_403 = and(_T_401, _T_402)
node _T_404 = eq(_T_403, UInt<1>(0h0))
node _T_405 = asUInt(reset)
node _T_406 = eq(_T_405, UInt<1>(0h0))
when _T_406 :
node _T_407 = eq(_T_404, UInt<1>(0h0))
when _T_407 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52
assert(clock, _T_404, UInt<1>(0h1), "") : assert_52
node _T_408 = eq(before, UInt<3>(0h4))
node _T_409 = eq(after, UInt<1>(0h0))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(_T_410, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53
assert(clock, _T_411, UInt<1>(0h1), "") : assert_53
node _T_415 = eq(before, UInt<3>(0h4))
node _T_416 = eq(after, UInt<3>(0h7))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(_T_417, UInt<1>(0h0))
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(_T_418, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54
assert(clock, _T_418, UInt<1>(0h1), "") : assert_54
node _T_422 = eq(before, UInt<3>(0h4))
node _T_423 = eq(after, UInt<3>(0h5))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(_T_424, UInt<1>(0h0))
node _T_426 = asUInt(reset)
node _T_427 = eq(_T_426, UInt<1>(0h0))
when _T_427 :
node _T_428 = eq(_T_425, UInt<1>(0h0))
when _T_428 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55
assert(clock, _T_425, UInt<1>(0h1), "") : assert_55
node _T_429 = eq(before, UInt<3>(0h4))
node _T_430 = eq(after, UInt<3>(0h6))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(before, UInt<3>(0h4))
node _T_433 = eq(after, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(_T_434, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56
assert(clock, _T_435, UInt<1>(0h1), "") : assert_56
node _T_439 = eq(before, UInt<3>(0h4))
node _T_440 = eq(after, UInt<2>(0h2))
node _T_441 = and(_T_439, _T_440)
node _T_442 = eq(before, UInt<2>(0h3))
node _T_443 = eq(after, UInt<4>(0h8))
node _T_444 = and(_T_442, _T_443)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57
assert(clock, _T_445, UInt<1>(0h1), "") : assert_57
node _T_449 = eq(before, UInt<2>(0h3))
node _T_450 = eq(after, UInt<1>(0h1))
node _T_451 = and(_T_449, _T_450)
node _T_452 = eq(_T_451, UInt<1>(0h0))
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58
assert(clock, _T_452, UInt<1>(0h1), "") : assert_58
node _T_456 = eq(before, UInt<2>(0h3))
node _T_457 = eq(after, UInt<1>(0h0))
node _T_458 = and(_T_456, _T_457)
node _T_459 = eq(_T_458, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59
assert(clock, _T_459, UInt<1>(0h1), "") : assert_59
node _T_463 = eq(before, UInt<2>(0h3))
node _T_464 = eq(after, UInt<3>(0h7))
node _T_465 = and(_T_463, _T_464)
node _T_466 = eq(before, UInt<2>(0h3))
node _T_467 = eq(after, UInt<3>(0h5))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(before, UInt<2>(0h3))
node _T_470 = eq(after, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(before, UInt<2>(0h3))
node _T_473 = eq(after, UInt<3>(0h4))
node _T_474 = and(_T_472, _T_473)
node _T_475 = eq(before, UInt<2>(0h3))
node _T_476 = eq(after, UInt<2>(0h2))
node _T_477 = and(_T_475, _T_476)
node _T_478 = eq(before, UInt<2>(0h2))
node _T_479 = eq(after, UInt<4>(0h8))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(_T_480, UInt<1>(0h0))
node _T_482 = asUInt(reset)
node _T_483 = eq(_T_482, UInt<1>(0h0))
when _T_483 :
node _T_484 = eq(_T_481, UInt<1>(0h0))
when _T_484 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60
assert(clock, _T_481, UInt<1>(0h1), "") : assert_60
node _T_485 = eq(before, UInt<2>(0h2))
node _T_486 = eq(after, UInt<1>(0h1))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(_T_487, UInt<1>(0h0))
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61
assert(clock, _T_488, UInt<1>(0h1), "") : assert_61
node _T_492 = eq(before, UInt<2>(0h2))
node _T_493 = eq(after, UInt<1>(0h0))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(_T_494, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62
assert(clock, _T_495, UInt<1>(0h1), "") : assert_62
node _T_499 = eq(before, UInt<2>(0h2))
node _T_500 = eq(after, UInt<3>(0h7))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(_T_501, UInt<1>(0h0))
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63
assert(clock, _T_502, UInt<1>(0h1), "") : assert_63
node _T_506 = eq(before, UInt<2>(0h2))
node _T_507 = eq(after, UInt<3>(0h5))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(_T_508, UInt<1>(0h0))
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64
assert(clock, _T_509, UInt<1>(0h1), "") : assert_64
node _T_513 = eq(before, UInt<2>(0h2))
node _T_514 = eq(after, UInt<3>(0h6))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(before, UInt<2>(0h2))
node _T_517 = eq(after, UInt<3>(0h4))
node _T_518 = and(_T_516, _T_517)
node _T_519 = eq(before, UInt<2>(0h2))
node _T_520 = eq(after, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _T_522 = eq(_T_521, UInt<1>(0h0))
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65
assert(clock, _T_522, UInt<1>(0h1), "") : assert_65
node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h28))
node _last_probe_T = or(probes_done, probe_bit)
node _last_probe_T_1 = not(excluded_client)
node _last_probe_T_2 = and(meta.clients, _last_probe_T_1)
node last_probe = eq(_last_probe_T, _last_probe_T_2)
node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1))
node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2))
node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1)
node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5))
node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3)
when io.sinkc.valid :
node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_527 = and(probe_toN, _T_526)
node _T_528 = eq(probe_toN, UInt<1>(0h0))
node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1))
node _T_530 = and(_T_528, _T_529)
node _probes_done_T = or(probes_done, probe_bit)
connect probes_done, _probes_done_T
node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0))
node _probes_toN_T_1 = or(probes_toN, _probes_toN_T)
connect probes_toN, _probes_toN_T_1
node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3))
node _probes_noT_T_1 = or(probes_noT, _probes_noT_T)
connect probes_noT, _probes_noT_T_1
node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe)
connect w_rprobeackfirst, _w_rprobeackfirst_T
node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T)
connect w_rprobeacklast, _w_rprobeacklast_T_1
node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe)
connect w_pprobeackfirst, _w_pprobeackfirst_T
node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last)
node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T)
connect w_pprobeacklast, _w_pprobeacklast_T_1
node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0))
node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T)
node set_pprobeack = and(last_probe, _set_pprobeack_T_1)
node _w_pprobeack_T = or(w_pprobeack, set_pprobeack)
connect w_pprobeack, _w_pprobeack_T
node _T_531 = eq(set_pprobeack, UInt<1>(0h0))
node _T_532 = and(_T_531, w_rprobeackfirst)
node _T_533 = and(set_pprobeack, w_rprobeackfirst)
node _T_534 = neq(meta.state, UInt<2>(0h0))
node _T_535 = eq(io.sinkc.bits.tag, meta.tag)
node _T_536 = and(_T_534, _T_535)
node _T_537 = and(_T_536, io.sinkc.bits.data)
when _T_537 :
connect meta.dirty, UInt<1>(0h1)
when io.sinkd.valid :
node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4))
node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_540 = or(_T_538, _T_539)
when _T_540 :
connect sink, io.sinkd.bits.sink
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, io.sinkd.bits.last
connect bad_grant, io.sinkd.bits.denied
node _w_grant_T = eq(request.offset, UInt<1>(0h0))
node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last)
connect w_grant, _w_grant_T_1
node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_542 = eq(request.offset, UInt<1>(0h0))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5))
node _T_545 = neq(request.offset, UInt<1>(0h0))
node _T_546 = and(_T_544, _T_545)
node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0))
connect gotT, _gotT_T
else :
node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6))
when _T_547 :
connect w_releaseack, UInt<1>(0h1)
when io.sinke.valid :
connect w_grantack, UInt<1>(0h1)
wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}
connect allocate_as_full.set, io.allocate.bits.set
connect allocate_as_full.put, io.allocate.bits.put
connect allocate_as_full.offset, io.allocate.bits.offset
connect allocate_as_full.tag, io.allocate.bits.tag
connect allocate_as_full.source, io.allocate.bits.source
connect allocate_as_full.size, io.allocate.bits.size
connect allocate_as_full.param, io.allocate.bits.param
connect allocate_as_full.opcode, io.allocate.bits.opcode
connect allocate_as_full.control, io.allocate.bits.control
connect allocate_as_full.prio, io.allocate.bits.prio
node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat)
node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits)
node new_request = mux(io.allocate.valid, allocate_as_full, request)
node _new_needT_T = bits(new_request.opcode, 2, 2)
node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0))
node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5))
node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1))
node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3)
node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4)
node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6))
node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7))
node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7)
node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0))
node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9)
node new_needT = or(_new_needT_T_5, _new_needT_T_10)
node new_clientBit = eq(new_request.source, UInt<6>(0h28))
node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6))
node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7))
node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1)
node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4))
node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3)
node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5))
node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0))
node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6)
node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0))
wire prior : UInt
connect prior, UInt<1>(0h0)
node prior_c = orr(final_meta_writeback.clients)
node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state)
when _prior_T :
node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1))
connect prior, _prior_out_T
else :
node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state)
when _prior_T_1 :
node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3))
connect prior, _prior_out_T_1
else :
node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state)
when _prior_T_2 :
node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5))
node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7))
node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3)
connect prior, _prior_out_T_4
else :
node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state)
when _prior_T_3 :
connect prior, UInt<4>(0h8)
node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
when _prior_T_4 :
connect prior, UInt<4>(0h8)
node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat)
when _T_548 :
node _T_549 = eq(prior, UInt<4>(0h8))
node _T_550 = eq(prior, UInt<1>(0h1))
node _T_551 = eq(_T_550, UInt<1>(0h0))
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_T_551, UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66
assert(clock, _T_551, UInt<1>(0h1), "") : assert_66
node _T_555 = eq(prior, UInt<1>(0h0))
node _T_556 = eq(_T_555, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67
assert(clock, _T_556, UInt<1>(0h1), "") : assert_67
node _T_560 = eq(prior, UInt<3>(0h7))
node _T_561 = eq(prior, UInt<3>(0h5))
node _T_562 = eq(prior, UInt<3>(0h4))
node _T_563 = eq(prior, UInt<3>(0h6))
node _T_564 = eq(prior, UInt<2>(0h3))
node _T_565 = eq(prior, UInt<2>(0h2))
when io.allocate.valid :
node _T_566 = eq(request_valid, UInt<1>(0h0))
node _T_567 = and(io.schedule.ready, io.schedule.valid)
node _T_568 = and(no_wait, _T_567)
node _T_569 = or(_T_566, _T_568)
node _T_570 = asUInt(reset)
node _T_571 = eq(_T_570, UInt<1>(0h0))
when _T_571 :
node _T_572 = eq(_T_569, UInt<1>(0h0))
when _T_572 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68
assert(clock, _T_569, UInt<1>(0h1), "") : assert_68
connect request_valid, UInt<1>(0h1)
connect request.set, io.allocate.bits.set
connect request.put, io.allocate.bits.put
connect request.offset, io.allocate.bits.offset
connect request.tag, io.allocate.bits.tag
connect request.source, io.allocate.bits.source
connect request.size, io.allocate.bits.size
connect request.param, io.allocate.bits.param
connect request.opcode, io.allocate.bits.opcode
connect request.control, io.allocate.bits.control
connect request.prio, io.allocate.bits.prio
node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat)
node _T_574 = or(io.directory.valid, _T_573)
when _T_574 :
connect meta_valid, UInt<1>(0h1)
connect meta, new_meta
connect probes_done, UInt<1>(0h0)
connect probes_toN, UInt<1>(0h0)
connect probes_noT, UInt<1>(0h0)
connect gotT, UInt<1>(0h0)
connect bad_grant, UInt<1>(0h0)
connect s_rprobe, UInt<1>(0h1)
connect w_rprobeackfirst, UInt<1>(0h1)
connect w_rprobeacklast, UInt<1>(0h1)
connect s_release, UInt<1>(0h1)
connect w_releaseack, UInt<1>(0h1)
connect s_pprobe, UInt<1>(0h1)
connect s_acquire, UInt<1>(0h1)
connect s_flush, UInt<1>(0h1)
connect w_grantfirst, UInt<1>(0h1)
connect w_grantlast, UInt<1>(0h1)
connect w_grant, UInt<1>(0h1)
connect w_pprobeackfirst, UInt<1>(0h1)
connect w_pprobeacklast, UInt<1>(0h1)
connect w_pprobeack, UInt<1>(0h1)
connect s_probeack, UInt<1>(0h1)
connect s_grantack, UInt<1>(0h1)
connect s_execute, UInt<1>(0h1)
connect w_grantack, UInt<1>(0h1)
connect s_writeback, UInt<1>(0h1)
node _T_575 = and(new_request.prio[2], UInt<1>(0h1))
when _T_575 :
connect s_execute, UInt<1>(0h0)
node _T_576 = bits(new_request.opcode, 0, 0)
node _T_577 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_578 = and(_T_576, _T_577)
when _T_578 :
connect s_writeback, UInt<1>(0h0)
node _T_579 = eq(new_request.param, UInt<3>(0h0))
node _T_580 = eq(new_request.param, UInt<3>(0h4))
node _T_581 = or(_T_579, _T_580)
node _T_582 = eq(new_meta.state, UInt<2>(0h2))
node _T_583 = and(_T_581, _T_582)
when _T_583 :
connect s_writeback, UInt<1>(0h0)
node _T_584 = eq(new_request.param, UInt<3>(0h1))
node _T_585 = eq(new_request.param, UInt<3>(0h2))
node _T_586 = or(_T_584, _T_585)
node _T_587 = eq(new_request.param, UInt<3>(0h5))
node _T_588 = or(_T_586, _T_587)
node _T_589 = and(new_meta.clients, new_clientBit)
node _T_590 = neq(_T_589, UInt<1>(0h0))
node _T_591 = and(_T_588, _T_590)
when _T_591 :
connect s_writeback, UInt<1>(0h0)
node _T_592 = asUInt(reset)
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(new_meta.hit, UInt<1>(0h0))
when _T_594 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69
assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69
else :
node _T_595 = and(new_request.control, UInt<1>(0h1))
when _T_595 :
connect s_flush, UInt<1>(0h0)
when new_meta.hit :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_596 = neq(new_meta.clients, UInt<1>(0h0))
node _T_597 = and(UInt<1>(0h1), _T_596)
when _T_597 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
else :
connect s_execute, UInt<1>(0h0)
node _T_598 = eq(new_meta.hit, UInt<1>(0h0))
node _T_599 = neq(new_meta.state, UInt<2>(0h0))
node _T_600 = and(_T_598, _T_599)
when _T_600 :
connect s_release, UInt<1>(0h0)
connect w_releaseack, UInt<1>(0h0)
node _T_601 = neq(new_meta.clients, UInt<1>(0h0))
node _T_602 = and(UInt<1>(0h1), _T_601)
when _T_602 :
connect s_rprobe, UInt<1>(0h0)
connect w_rprobeackfirst, UInt<1>(0h0)
connect w_rprobeacklast, UInt<1>(0h0)
node _T_603 = eq(new_meta.hit, UInt<1>(0h0))
node _T_604 = eq(new_meta.state, UInt<2>(0h1))
node _T_605 = and(_T_604, new_needT)
node _T_606 = or(_T_603, _T_605)
when _T_606 :
connect s_acquire, UInt<1>(0h0)
connect w_grantfirst, UInt<1>(0h0)
connect w_grantlast, UInt<1>(0h0)
connect w_grant, UInt<1>(0h0)
connect s_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_607 = eq(new_meta.state, UInt<2>(0h2))
node _T_608 = or(new_needT, _T_607)
node _T_609 = and(new_meta.hit, _T_608)
node _T_610 = not(new_skipProbe)
node _T_611 = and(new_meta.clients, _T_610)
node _T_612 = neq(_T_611, UInt<1>(0h0))
node _T_613 = and(_T_609, _T_612)
node _T_614 = and(UInt<1>(0h1), _T_613)
when _T_614 :
connect s_pprobe, UInt<1>(0h0)
connect w_pprobeackfirst, UInt<1>(0h0)
connect w_pprobeacklast, UInt<1>(0h0)
connect w_pprobeack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_615 = eq(new_request.opcode, UInt<3>(0h6))
node _T_616 = eq(new_request.opcode, UInt<3>(0h7))
node _T_617 = or(_T_615, _T_616)
when _T_617 :
connect w_grantack, UInt<1>(0h0)
connect s_writeback, UInt<1>(0h0)
node _T_618 = bits(new_request.opcode, 2, 2)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = and(_T_619, new_meta.hit)
node _T_621 = eq(new_meta.dirty, UInt<1>(0h0))
node _T_622 = and(_T_620, _T_621)
when _T_622 :
connect s_writeback, UInt<1>(0h0) | module MSHR_77( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [10:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [3:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [8:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [10:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [8:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [3:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_78 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_126
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_78( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_126 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module GenericSerializer_TLBeatw88_f32_1 :
input clock : Clock
input reset : Reset
output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { payload : UInt<86>, head : UInt<1>, tail : UInt<1>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, busy : UInt<1>}
reg data : UInt<32>[3], clock
regreset beat : UInt<2>, clock, reset, UInt<2>(0h0)
node _io_in_ready_T = eq(beat, UInt<1>(0h0))
node _io_in_ready_T_1 = and(io.out.ready, _io_in_ready_T)
connect io.in.ready, _io_in_ready_T_1
node _io_out_valid_T = neq(beat, UInt<1>(0h0))
node _io_out_valid_T_1 = or(io.in.valid, _io_out_valid_T)
connect io.out.valid, _io_out_valid_T_1
node _io_out_bits_flit_T = eq(beat, UInt<1>(0h0))
node io_out_bits_flit_hi = cat(io.in.bits.payload, io.in.bits.head)
node _io_out_bits_flit_T_1 = cat(io_out_bits_flit_hi, io.in.bits.tail)
node _io_out_bits_flit_T_2 = mux(_io_out_bits_flit_T, _io_out_bits_flit_T_1, data[beat])
connect io.out.bits.flit, _io_out_bits_flit_T_2
node _T = and(io.out.ready, io.out.valid)
when _T :
node _beat_T = eq(beat, UInt<2>(0h2))
node _beat_T_1 = add(beat, UInt<1>(0h1))
node _beat_T_2 = tail(_beat_T_1, 1)
node _beat_T_3 = mux(_beat_T, UInt<1>(0h0), _beat_T_2)
connect beat, _beat_T_3
node _T_1 = eq(beat, UInt<1>(0h0))
when _T_1 :
wire _WIRE : UInt<32>[3]
node hi = cat(io.in.bits.payload, io.in.bits.head)
node _T_2 = cat(hi, io.in.bits.tail)
wire _WIRE_1 : UInt<96>
connect _WIRE_1, _T_2
node _T_3 = bits(_WIRE_1, 31, 0)
connect _WIRE[0], _T_3
node _T_4 = bits(_WIRE_1, 63, 32)
connect _WIRE[1], _T_4
node _T_5 = bits(_WIRE_1, 95, 64)
connect _WIRE[2], _T_5
connect data, _WIRE
invalidate data[0]
connect io.busy, io.out.valid | module GenericSerializer_TLBeatw88_f32_1( // @[Serdes.scala:8:7]
input clock, // @[Serdes.scala:8:7]
input reset, // @[Serdes.scala:8:7]
output io_in_ready, // @[Serdes.scala:10:14]
input io_in_valid, // @[Serdes.scala:10:14]
input [85:0] io_in_bits_payload, // @[Serdes.scala:10:14]
input io_in_bits_head, // @[Serdes.scala:10:14]
input io_in_bits_tail, // @[Serdes.scala:10:14]
input io_out_ready, // @[Serdes.scala:10:14]
output io_out_valid, // @[Serdes.scala:10:14]
output [31:0] io_out_bits_flit, // @[Serdes.scala:10:14]
output io_busy // @[Serdes.scala:10:14]
);
wire io_out_valid_0; // @[Serdes.scala:8:7]
wire io_in_valid_0 = io_in_valid; // @[Serdes.scala:8:7]
wire [85:0] io_in_bits_payload_0 = io_in_bits_payload; // @[Serdes.scala:8:7]
wire io_in_bits_head_0 = io_in_bits_head; // @[Serdes.scala:8:7]
wire io_in_bits_tail_0 = io_in_bits_tail; // @[Serdes.scala:8:7]
wire io_out_ready_0 = io_out_ready; // @[Serdes.scala:8:7]
wire [0:0][31:0] _GEN = '{32'h0};
wire _io_in_ready_T_1; // @[Serdes.scala:22:31]
wire _io_out_valid_T_1; // @[Serdes.scala:23:31]
wire io_busy_0 = io_out_valid_0; // @[Serdes.scala:8:7]
wire io_in_ready_0; // @[Serdes.scala:8:7]
wire [31:0] io_out_bits_flit_0; // @[Serdes.scala:8:7]
reg [31:0] data_1; // @[Serdes.scala:19:17]
reg [31:0] data_2; // @[Serdes.scala:19:17]
reg [1:0] beat; // @[Serdes.scala:20:21]
wire _io_in_ready_T = ~(|beat); // @[Serdes.scala:20:21, :22:39]
assign _io_in_ready_T_1 = io_out_ready_0 & _io_in_ready_T; // @[Serdes.scala:8:7, :22:{31,39}]
assign io_in_ready_0 = _io_in_ready_T_1; // @[Serdes.scala:8:7, :22:31]
wire _io_out_valid_T = |beat; // @[Serdes.scala:20:21, :22:39, :23:39]
assign _io_out_valid_T_1 = io_in_valid_0 | _io_out_valid_T; // @[Serdes.scala:8:7, :23:{31,39}]
assign io_out_valid_0 = _io_out_valid_T_1; // @[Serdes.scala:8:7, :23:31]
wire _io_out_bits_flit_T = ~(|beat); // @[Serdes.scala:20:21, :22:39, :24:32]
wire [86:0] _GEN_0 = {io_in_bits_payload_0, io_in_bits_head_0}; // @[Serdes.scala:8:7, :24:52]
wire [86:0] io_out_bits_flit_hi; // @[Serdes.scala:24:52]
assign io_out_bits_flit_hi = _GEN_0; // @[Serdes.scala:24:52]
wire [86:0] hi; // @[Serdes.scala:29:34]
assign hi = _GEN_0; // @[Serdes.scala:24:52, :29:34]
wire [87:0] _io_out_bits_flit_T_1 = {io_out_bits_flit_hi, io_in_bits_tail_0}; // @[Serdes.scala:8:7, :24:52]
wire [3:0][31:0] _GEN_1 = {_GEN, {{data_2}, {data_1}, {32'h0}}}; // @[Serdes.scala:19:17, :24:26]
wire [87:0] _io_out_bits_flit_T_2 = _io_out_bits_flit_T ? _io_out_bits_flit_T_1 : {56'h0, _GEN_1[beat]}; // @[Serdes.scala:20:21, :24:{26,32,52}]
assign io_out_bits_flit_0 = _io_out_bits_flit_T_2[31:0]; // @[Serdes.scala:8:7, :24:{20,26}]
wire _beat_T = beat == 2'h2; // @[Serdes.scala:20:21, :27:22]
wire [2:0] _beat_T_1 = {1'h0, beat} + 3'h1; // @[Serdes.scala:20:21, :27:53]
wire [1:0] _beat_T_2 = _beat_T_1[1:0]; // @[Serdes.scala:27:53]
wire [1:0] _beat_T_3 = _beat_T ? 2'h0 : _beat_T_2; // @[Serdes.scala:27:{16,22,53}]
wire _T = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Serdes.scala:8:7]
if (_T & ~(|beat)) begin // @[Decoupled.scala:51:35]
data_1 <= hi[62:31]; // @[Serdes.scala:19:17, :29:34]
data_2 <= {8'h0, hi[86:63]}; // @[Serdes.scala:19:17, :29:34]
end
if (reset) // @[Serdes.scala:8:7]
beat <= 2'h0; // @[Serdes.scala:20:21]
else if (_T) // @[Decoupled.scala:51:35]
beat <= _beat_T_3; // @[Serdes.scala:20:21, :27:16]
always @(posedge)
assign io_in_ready = io_in_ready_0; // @[Serdes.scala:8:7]
assign io_out_valid = io_out_valid_0; // @[Serdes.scala:8:7]
assign io_out_bits_flit = io_out_bits_flit_0; // @[Serdes.scala:8:7]
assign io_busy = io_busy_0; // @[Serdes.scala:8:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_66 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_66( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_17 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[12]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
connect _source_ok_WIRE[11], _source_ok_T_31
node _source_ok_T_32 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[2])
node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[3])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[4])
node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[5])
node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[6])
node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[7])
node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[8])
node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[9])
node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[10])
node source_ok = or(_source_ok_T_41, _source_ok_WIRE[11])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _T_112 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = or(_T_113, _T_118)
node _T_120 = and(_T_11, _T_24)
node _T_121 = and(_T_120, _T_37)
node _T_122 = and(_T_121, _T_50)
node _T_123 = and(_T_122, _T_63)
node _T_124 = and(_T_123, _T_71)
node _T_125 = and(_T_124, _T_79)
node _T_126 = and(_T_125, _T_87)
node _T_127 = and(_T_126, _T_95)
node _T_128 = and(_T_127, _T_103)
node _T_129 = and(_T_128, _T_111)
node _T_130 = and(_T_129, _T_119)
node _T_131 = asUInt(reset)
node _T_132 = eq(_T_131, UInt<1>(0h0))
when _T_132 :
node _T_133 = eq(_T_130, UInt<1>(0h0))
when _T_133 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_130, UInt<1>(0h1), "") : assert_1
node _T_134 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_134 :
node _T_135 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_136 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_137 = and(_T_135, _T_136)
node _T_138 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_139 = shr(io.in.a.bits.source, 2)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_142 = and(_T_140, _T_141)
node _T_143 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_144 = and(_T_142, _T_143)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_145 = shr(io.in.a.bits.source, 2)
node _T_146 = eq(_T_145, UInt<1>(0h1))
node _T_147 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_148 = and(_T_146, _T_147)
node _T_149 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_150 = and(_T_148, _T_149)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_151 = shr(io.in.a.bits.source, 2)
node _T_152 = eq(_T_151, UInt<2>(0h2))
node _T_153 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_154 = and(_T_152, _T_153)
node _T_155 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_156 = and(_T_154, _T_155)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_157 = shr(io.in.a.bits.source, 2)
node _T_158 = eq(_T_157, UInt<2>(0h3))
node _T_159 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_160 = and(_T_158, _T_159)
node _T_161 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_162 = and(_T_160, _T_161)
node _T_163 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_164 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_165 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_166 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_167 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_169 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_170 = or(_T_138, _T_144)
node _T_171 = or(_T_170, _T_150)
node _T_172 = or(_T_171, _T_156)
node _T_173 = or(_T_172, _T_162)
node _T_174 = or(_T_173, _T_163)
node _T_175 = or(_T_174, _T_164)
node _T_176 = or(_T_175, _T_165)
node _T_177 = or(_T_176, _T_166)
node _T_178 = or(_T_177, _T_167)
node _T_179 = or(_T_178, _T_168)
node _T_180 = or(_T_179, _T_169)
node _T_181 = and(_T_137, _T_180)
node _T_182 = or(UInt<1>(0h0), _T_181)
node _T_183 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_184 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<14>(0h2000)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<13>(0h1000)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<17>(0h10000)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<18>(0h2f000)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<17>(0h10000)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_210 = cvt(_T_209)
node _T_211 = and(_T_210, asSInt(UInt<13>(0h1000)))
node _T_212 = asSInt(_T_211)
node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0)))
node _T_214 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_215 = cvt(_T_214)
node _T_216 = and(_T_215, asSInt(UInt<27>(0h4000000)))
node _T_217 = asSInt(_T_216)
node _T_218 = eq(_T_217, asSInt(UInt<1>(0h0)))
node _T_219 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_220 = cvt(_T_219)
node _T_221 = and(_T_220, asSInt(UInt<13>(0h1000)))
node _T_222 = asSInt(_T_221)
node _T_223 = eq(_T_222, asSInt(UInt<1>(0h0)))
node _T_224 = or(_T_188, _T_193)
node _T_225 = or(_T_224, _T_198)
node _T_226 = or(_T_225, _T_203)
node _T_227 = or(_T_226, _T_208)
node _T_228 = or(_T_227, _T_213)
node _T_229 = or(_T_228, _T_218)
node _T_230 = or(_T_229, _T_223)
node _T_231 = and(_T_183, _T_230)
node _T_232 = or(UInt<1>(0h0), _T_231)
node _T_233 = and(_T_182, _T_232)
node _T_234 = asUInt(reset)
node _T_235 = eq(_T_234, UInt<1>(0h0))
when _T_235 :
node _T_236 = eq(_T_233, UInt<1>(0h0))
when _T_236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_233, UInt<1>(0h1), "") : assert_2
node _T_237 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_238 = shr(io.in.a.bits.source, 2)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_241 = and(_T_239, _T_240)
node _T_242 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_243 = and(_T_241, _T_242)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_244 = shr(io.in.a.bits.source, 2)
node _T_245 = eq(_T_244, UInt<1>(0h1))
node _T_246 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_247 = and(_T_245, _T_246)
node _T_248 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_249 = and(_T_247, _T_248)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_250 = shr(io.in.a.bits.source, 2)
node _T_251 = eq(_T_250, UInt<2>(0h2))
node _T_252 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_253 = and(_T_251, _T_252)
node _T_254 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_255 = and(_T_253, _T_254)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_256 = shr(io.in.a.bits.source, 2)
node _T_257 = eq(_T_256, UInt<2>(0h3))
node _T_258 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_259 = and(_T_257, _T_258)
node _T_260 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_261 = and(_T_259, _T_260)
node _T_262 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_263 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_264 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_265 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_266 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_267 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_268 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[12]
connect _WIRE[0], _T_237
connect _WIRE[1], _T_243
connect _WIRE[2], _T_249
connect _WIRE[3], _T_255
connect _WIRE[4], _T_261
connect _WIRE[5], _T_262
connect _WIRE[6], _T_263
connect _WIRE[7], _T_264
connect _WIRE[8], _T_265
connect _WIRE[9], _T_266
connect _WIRE[10], _T_267
connect _WIRE[11], _T_268
node _T_269 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_270 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_271 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_272 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_273 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_274 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_275 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_276 = mux(_WIRE[5], _T_269, UInt<1>(0h0))
node _T_277 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_278 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_279 = mux(_WIRE[8], _T_270, UInt<1>(0h0))
node _T_280 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_281 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_282 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_283 = or(_T_271, _T_272)
node _T_284 = or(_T_283, _T_273)
node _T_285 = or(_T_284, _T_274)
node _T_286 = or(_T_285, _T_275)
node _T_287 = or(_T_286, _T_276)
node _T_288 = or(_T_287, _T_277)
node _T_289 = or(_T_288, _T_278)
node _T_290 = or(_T_289, _T_279)
node _T_291 = or(_T_290, _T_280)
node _T_292 = or(_T_291, _T_281)
node _T_293 = or(_T_292, _T_282)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_293
node _T_294 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_295 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_296 = and(_T_294, _T_295)
node _T_297 = or(UInt<1>(0h0), _T_296)
node _T_298 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_299 = cvt(_T_298)
node _T_300 = and(_T_299, asSInt(UInt<14>(0h2000)))
node _T_301 = asSInt(_T_300)
node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0)))
node _T_303 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_304 = cvt(_T_303)
node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000)))
node _T_306 = asSInt(_T_305)
node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0)))
node _T_308 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_309 = cvt(_T_308)
node _T_310 = and(_T_309, asSInt(UInt<17>(0h10000)))
node _T_311 = asSInt(_T_310)
node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0)))
node _T_313 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_314 = cvt(_T_313)
node _T_315 = and(_T_314, asSInt(UInt<18>(0h2f000)))
node _T_316 = asSInt(_T_315)
node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0)))
node _T_318 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_319 = cvt(_T_318)
node _T_320 = and(_T_319, asSInt(UInt<17>(0h10000)))
node _T_321 = asSInt(_T_320)
node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0)))
node _T_323 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_324 = cvt(_T_323)
node _T_325 = and(_T_324, asSInt(UInt<13>(0h1000)))
node _T_326 = asSInt(_T_325)
node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0)))
node _T_328 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_329 = cvt(_T_328)
node _T_330 = and(_T_329, asSInt(UInt<27>(0h4000000)))
node _T_331 = asSInt(_T_330)
node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0)))
node _T_333 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_334 = cvt(_T_333)
node _T_335 = and(_T_334, asSInt(UInt<13>(0h1000)))
node _T_336 = asSInt(_T_335)
node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0)))
node _T_338 = or(_T_302, _T_307)
node _T_339 = or(_T_338, _T_312)
node _T_340 = or(_T_339, _T_317)
node _T_341 = or(_T_340, _T_322)
node _T_342 = or(_T_341, _T_327)
node _T_343 = or(_T_342, _T_332)
node _T_344 = or(_T_343, _T_337)
node _T_345 = and(_T_297, _T_344)
node _T_346 = or(UInt<1>(0h0), _T_345)
node _T_347 = and(_WIRE_1, _T_346)
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_347, UInt<1>(0h1), "") : assert_3
node _T_351 = asUInt(reset)
node _T_352 = eq(_T_351, UInt<1>(0h0))
when _T_352 :
node _T_353 = eq(source_ok, UInt<1>(0h0))
when _T_353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_354 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_355 = asUInt(reset)
node _T_356 = eq(_T_355, UInt<1>(0h0))
when _T_356 :
node _T_357 = eq(_T_354, UInt<1>(0h0))
when _T_357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_354, UInt<1>(0h1), "") : assert_5
node _T_358 = asUInt(reset)
node _T_359 = eq(_T_358, UInt<1>(0h0))
when _T_359 :
node _T_360 = eq(is_aligned, UInt<1>(0h0))
when _T_360 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_361 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_362 = asUInt(reset)
node _T_363 = eq(_T_362, UInt<1>(0h0))
when _T_363 :
node _T_364 = eq(_T_361, UInt<1>(0h0))
when _T_364 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_361, UInt<1>(0h1), "") : assert_7
node _T_365 = not(io.in.a.bits.mask)
node _T_366 = eq(_T_365, UInt<1>(0h0))
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_T_366, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_366, UInt<1>(0h1), "") : assert_8
node _T_370 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(_T_370, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_370, UInt<1>(0h1), "") : assert_9
node _T_374 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_374 :
node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_376 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_377 = and(_T_375, _T_376)
node _T_378 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_379 = shr(io.in.a.bits.source, 2)
node _T_380 = eq(_T_379, UInt<1>(0h0))
node _T_381 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_382 = and(_T_380, _T_381)
node _T_383 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_384 = and(_T_382, _T_383)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_385 = shr(io.in.a.bits.source, 2)
node _T_386 = eq(_T_385, UInt<1>(0h1))
node _T_387 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_388 = and(_T_386, _T_387)
node _T_389 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_390 = and(_T_388, _T_389)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_391 = shr(io.in.a.bits.source, 2)
node _T_392 = eq(_T_391, UInt<2>(0h2))
node _T_393 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_394 = and(_T_392, _T_393)
node _T_395 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_396 = and(_T_394, _T_395)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_397 = shr(io.in.a.bits.source, 2)
node _T_398 = eq(_T_397, UInt<2>(0h3))
node _T_399 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_400 = and(_T_398, _T_399)
node _T_401 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_402 = and(_T_400, _T_401)
node _T_403 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_404 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_405 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_406 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_407 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_408 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_409 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_410 = or(_T_378, _T_384)
node _T_411 = or(_T_410, _T_390)
node _T_412 = or(_T_411, _T_396)
node _T_413 = or(_T_412, _T_402)
node _T_414 = or(_T_413, _T_403)
node _T_415 = or(_T_414, _T_404)
node _T_416 = or(_T_415, _T_405)
node _T_417 = or(_T_416, _T_406)
node _T_418 = or(_T_417, _T_407)
node _T_419 = or(_T_418, _T_408)
node _T_420 = or(_T_419, _T_409)
node _T_421 = and(_T_377, _T_420)
node _T_422 = or(UInt<1>(0h0), _T_421)
node _T_423 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_424 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_425 = cvt(_T_424)
node _T_426 = and(_T_425, asSInt(UInt<14>(0h2000)))
node _T_427 = asSInt(_T_426)
node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0)))
node _T_429 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_430 = cvt(_T_429)
node _T_431 = and(_T_430, asSInt(UInt<13>(0h1000)))
node _T_432 = asSInt(_T_431)
node _T_433 = eq(_T_432, asSInt(UInt<1>(0h0)))
node _T_434 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_435 = cvt(_T_434)
node _T_436 = and(_T_435, asSInt(UInt<17>(0h10000)))
node _T_437 = asSInt(_T_436)
node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0)))
node _T_439 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_440 = cvt(_T_439)
node _T_441 = and(_T_440, asSInt(UInt<18>(0h2f000)))
node _T_442 = asSInt(_T_441)
node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0)))
node _T_444 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_445 = cvt(_T_444)
node _T_446 = and(_T_445, asSInt(UInt<17>(0h10000)))
node _T_447 = asSInt(_T_446)
node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0)))
node _T_449 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_450 = cvt(_T_449)
node _T_451 = and(_T_450, asSInt(UInt<13>(0h1000)))
node _T_452 = asSInt(_T_451)
node _T_453 = eq(_T_452, asSInt(UInt<1>(0h0)))
node _T_454 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_455 = cvt(_T_454)
node _T_456 = and(_T_455, asSInt(UInt<27>(0h4000000)))
node _T_457 = asSInt(_T_456)
node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0)))
node _T_459 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_460 = cvt(_T_459)
node _T_461 = and(_T_460, asSInt(UInt<13>(0h1000)))
node _T_462 = asSInt(_T_461)
node _T_463 = eq(_T_462, asSInt(UInt<1>(0h0)))
node _T_464 = or(_T_428, _T_433)
node _T_465 = or(_T_464, _T_438)
node _T_466 = or(_T_465, _T_443)
node _T_467 = or(_T_466, _T_448)
node _T_468 = or(_T_467, _T_453)
node _T_469 = or(_T_468, _T_458)
node _T_470 = or(_T_469, _T_463)
node _T_471 = and(_T_423, _T_470)
node _T_472 = or(UInt<1>(0h0), _T_471)
node _T_473 = and(_T_422, _T_472)
node _T_474 = asUInt(reset)
node _T_475 = eq(_T_474, UInt<1>(0h0))
when _T_475 :
node _T_476 = eq(_T_473, UInt<1>(0h0))
when _T_476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_473, UInt<1>(0h1), "") : assert_10
node _T_477 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_478 = shr(io.in.a.bits.source, 2)
node _T_479 = eq(_T_478, UInt<1>(0h0))
node _T_480 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_481 = and(_T_479, _T_480)
node _T_482 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_483 = and(_T_481, _T_482)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_484 = shr(io.in.a.bits.source, 2)
node _T_485 = eq(_T_484, UInt<1>(0h1))
node _T_486 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_487 = and(_T_485, _T_486)
node _T_488 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_489 = and(_T_487, _T_488)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_490 = shr(io.in.a.bits.source, 2)
node _T_491 = eq(_T_490, UInt<2>(0h2))
node _T_492 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_493 = and(_T_491, _T_492)
node _T_494 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_495 = and(_T_493, _T_494)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_496 = shr(io.in.a.bits.source, 2)
node _T_497 = eq(_T_496, UInt<2>(0h3))
node _T_498 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_499 = and(_T_497, _T_498)
node _T_500 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_503 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_504 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_505 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_506 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_507 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_508 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[12]
connect _WIRE_2[0], _T_477
connect _WIRE_2[1], _T_483
connect _WIRE_2[2], _T_489
connect _WIRE_2[3], _T_495
connect _WIRE_2[4], _T_501
connect _WIRE_2[5], _T_502
connect _WIRE_2[6], _T_503
connect _WIRE_2[7], _T_504
connect _WIRE_2[8], _T_505
connect _WIRE_2[9], _T_506
connect _WIRE_2[10], _T_507
connect _WIRE_2[11], _T_508
node _T_509 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_510 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_511 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_512 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_513 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_514 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_515 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_516 = mux(_WIRE_2[5], _T_509, UInt<1>(0h0))
node _T_517 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_518 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_519 = mux(_WIRE_2[8], _T_510, UInt<1>(0h0))
node _T_520 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_521 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_522 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_523 = or(_T_511, _T_512)
node _T_524 = or(_T_523, _T_513)
node _T_525 = or(_T_524, _T_514)
node _T_526 = or(_T_525, _T_515)
node _T_527 = or(_T_526, _T_516)
node _T_528 = or(_T_527, _T_517)
node _T_529 = or(_T_528, _T_518)
node _T_530 = or(_T_529, _T_519)
node _T_531 = or(_T_530, _T_520)
node _T_532 = or(_T_531, _T_521)
node _T_533 = or(_T_532, _T_522)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_533
node _T_534 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_535 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_536 = and(_T_534, _T_535)
node _T_537 = or(UInt<1>(0h0), _T_536)
node _T_538 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_539 = cvt(_T_538)
node _T_540 = and(_T_539, asSInt(UInt<14>(0h2000)))
node _T_541 = asSInt(_T_540)
node _T_542 = eq(_T_541, asSInt(UInt<1>(0h0)))
node _T_543 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_544 = cvt(_T_543)
node _T_545 = and(_T_544, asSInt(UInt<13>(0h1000)))
node _T_546 = asSInt(_T_545)
node _T_547 = eq(_T_546, asSInt(UInt<1>(0h0)))
node _T_548 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_549 = cvt(_T_548)
node _T_550 = and(_T_549, asSInt(UInt<17>(0h10000)))
node _T_551 = asSInt(_T_550)
node _T_552 = eq(_T_551, asSInt(UInt<1>(0h0)))
node _T_553 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_554 = cvt(_T_553)
node _T_555 = and(_T_554, asSInt(UInt<18>(0h2f000)))
node _T_556 = asSInt(_T_555)
node _T_557 = eq(_T_556, asSInt(UInt<1>(0h0)))
node _T_558 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_559 = cvt(_T_558)
node _T_560 = and(_T_559, asSInt(UInt<17>(0h10000)))
node _T_561 = asSInt(_T_560)
node _T_562 = eq(_T_561, asSInt(UInt<1>(0h0)))
node _T_563 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_564 = cvt(_T_563)
node _T_565 = and(_T_564, asSInt(UInt<13>(0h1000)))
node _T_566 = asSInt(_T_565)
node _T_567 = eq(_T_566, asSInt(UInt<1>(0h0)))
node _T_568 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_569 = cvt(_T_568)
node _T_570 = and(_T_569, asSInt(UInt<27>(0h4000000)))
node _T_571 = asSInt(_T_570)
node _T_572 = eq(_T_571, asSInt(UInt<1>(0h0)))
node _T_573 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_574 = cvt(_T_573)
node _T_575 = and(_T_574, asSInt(UInt<13>(0h1000)))
node _T_576 = asSInt(_T_575)
node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0)))
node _T_578 = or(_T_542, _T_547)
node _T_579 = or(_T_578, _T_552)
node _T_580 = or(_T_579, _T_557)
node _T_581 = or(_T_580, _T_562)
node _T_582 = or(_T_581, _T_567)
node _T_583 = or(_T_582, _T_572)
node _T_584 = or(_T_583, _T_577)
node _T_585 = and(_T_537, _T_584)
node _T_586 = or(UInt<1>(0h0), _T_585)
node _T_587 = and(_WIRE_3, _T_586)
node _T_588 = asUInt(reset)
node _T_589 = eq(_T_588, UInt<1>(0h0))
when _T_589 :
node _T_590 = eq(_T_587, UInt<1>(0h0))
when _T_590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_587, UInt<1>(0h1), "") : assert_11
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(source_ok, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_594 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_594, UInt<1>(0h1), "") : assert_13
node _T_598 = asUInt(reset)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
node _T_600 = eq(is_aligned, UInt<1>(0h0))
when _T_600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_601 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_601, UInt<1>(0h1), "") : assert_15
node _T_605 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_606 = asUInt(reset)
node _T_607 = eq(_T_606, UInt<1>(0h0))
when _T_607 :
node _T_608 = eq(_T_605, UInt<1>(0h0))
when _T_608 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_605, UInt<1>(0h1), "") : assert_16
node _T_609 = not(io.in.a.bits.mask)
node _T_610 = eq(_T_609, UInt<1>(0h0))
node _T_611 = asUInt(reset)
node _T_612 = eq(_T_611, UInt<1>(0h0))
when _T_612 :
node _T_613 = eq(_T_610, UInt<1>(0h0))
when _T_613 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_610, UInt<1>(0h1), "") : assert_17
node _T_614 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_614, UInt<1>(0h1), "") : assert_18
node _T_618 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_618 :
node _T_619 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_620 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_621 = and(_T_619, _T_620)
node _T_622 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_623 = shr(io.in.a.bits.source, 2)
node _T_624 = eq(_T_623, UInt<1>(0h0))
node _T_625 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_626 = and(_T_624, _T_625)
node _T_627 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_628 = and(_T_626, _T_627)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_629 = shr(io.in.a.bits.source, 2)
node _T_630 = eq(_T_629, UInt<1>(0h1))
node _T_631 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_632 = and(_T_630, _T_631)
node _T_633 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_634 = and(_T_632, _T_633)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_635 = shr(io.in.a.bits.source, 2)
node _T_636 = eq(_T_635, UInt<2>(0h2))
node _T_637 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_638 = and(_T_636, _T_637)
node _T_639 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_640 = and(_T_638, _T_639)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_641 = shr(io.in.a.bits.source, 2)
node _T_642 = eq(_T_641, UInt<2>(0h3))
node _T_643 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_644 = and(_T_642, _T_643)
node _T_645 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_646 = and(_T_644, _T_645)
node _T_647 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_648 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_649 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_650 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_651 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_652 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_653 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_654 = or(_T_622, _T_628)
node _T_655 = or(_T_654, _T_634)
node _T_656 = or(_T_655, _T_640)
node _T_657 = or(_T_656, _T_646)
node _T_658 = or(_T_657, _T_647)
node _T_659 = or(_T_658, _T_648)
node _T_660 = or(_T_659, _T_649)
node _T_661 = or(_T_660, _T_650)
node _T_662 = or(_T_661, _T_651)
node _T_663 = or(_T_662, _T_652)
node _T_664 = or(_T_663, _T_653)
node _T_665 = and(_T_621, _T_664)
node _T_666 = or(UInt<1>(0h0), _T_665)
node _T_667 = asUInt(reset)
node _T_668 = eq(_T_667, UInt<1>(0h0))
when _T_668 :
node _T_669 = eq(_T_666, UInt<1>(0h0))
when _T_669 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_666, UInt<1>(0h1), "") : assert_19
node _T_670 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_671 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_672 = and(_T_670, _T_671)
node _T_673 = or(UInt<1>(0h0), _T_672)
node _T_674 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_675 = cvt(_T_674)
node _T_676 = and(_T_675, asSInt(UInt<13>(0h1000)))
node _T_677 = asSInt(_T_676)
node _T_678 = eq(_T_677, asSInt(UInt<1>(0h0)))
node _T_679 = and(_T_673, _T_678)
node _T_680 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_681 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_682 = and(_T_680, _T_681)
node _T_683 = or(UInt<1>(0h0), _T_682)
node _T_684 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_685 = cvt(_T_684)
node _T_686 = and(_T_685, asSInt(UInt<14>(0h2000)))
node _T_687 = asSInt(_T_686)
node _T_688 = eq(_T_687, asSInt(UInt<1>(0h0)))
node _T_689 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_690 = cvt(_T_689)
node _T_691 = and(_T_690, asSInt(UInt<17>(0h10000)))
node _T_692 = asSInt(_T_691)
node _T_693 = eq(_T_692, asSInt(UInt<1>(0h0)))
node _T_694 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_695 = cvt(_T_694)
node _T_696 = and(_T_695, asSInt(UInt<18>(0h2f000)))
node _T_697 = asSInt(_T_696)
node _T_698 = eq(_T_697, asSInt(UInt<1>(0h0)))
node _T_699 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_700 = cvt(_T_699)
node _T_701 = and(_T_700, asSInt(UInt<17>(0h10000)))
node _T_702 = asSInt(_T_701)
node _T_703 = eq(_T_702, asSInt(UInt<1>(0h0)))
node _T_704 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_705 = cvt(_T_704)
node _T_706 = and(_T_705, asSInt(UInt<13>(0h1000)))
node _T_707 = asSInt(_T_706)
node _T_708 = eq(_T_707, asSInt(UInt<1>(0h0)))
node _T_709 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_710 = cvt(_T_709)
node _T_711 = and(_T_710, asSInt(UInt<27>(0h4000000)))
node _T_712 = asSInt(_T_711)
node _T_713 = eq(_T_712, asSInt(UInt<1>(0h0)))
node _T_714 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_715 = cvt(_T_714)
node _T_716 = and(_T_715, asSInt(UInt<13>(0h1000)))
node _T_717 = asSInt(_T_716)
node _T_718 = eq(_T_717, asSInt(UInt<1>(0h0)))
node _T_719 = or(_T_688, _T_693)
node _T_720 = or(_T_719, _T_698)
node _T_721 = or(_T_720, _T_703)
node _T_722 = or(_T_721, _T_708)
node _T_723 = or(_T_722, _T_713)
node _T_724 = or(_T_723, _T_718)
node _T_725 = and(_T_683, _T_724)
node _T_726 = or(UInt<1>(0h0), _T_679)
node _T_727 = or(_T_726, _T_725)
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_727, UInt<1>(0h1), "") : assert_20
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(source_ok, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_734 = asUInt(reset)
node _T_735 = eq(_T_734, UInt<1>(0h0))
when _T_735 :
node _T_736 = eq(is_aligned, UInt<1>(0h0))
when _T_736 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_737 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(_T_737, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_737, UInt<1>(0h1), "") : assert_23
node _T_741 = eq(io.in.a.bits.mask, mask)
node _T_742 = asUInt(reset)
node _T_743 = eq(_T_742, UInt<1>(0h0))
when _T_743 :
node _T_744 = eq(_T_741, UInt<1>(0h0))
when _T_744 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_741, UInt<1>(0h1), "") : assert_24
node _T_745 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_746 = asUInt(reset)
node _T_747 = eq(_T_746, UInt<1>(0h0))
when _T_747 :
node _T_748 = eq(_T_745, UInt<1>(0h0))
when _T_748 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_745, UInt<1>(0h1), "") : assert_25
node _T_749 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_749 :
node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_752 = and(_T_750, _T_751)
node _T_753 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_754 = shr(io.in.a.bits.source, 2)
node _T_755 = eq(_T_754, UInt<1>(0h0))
node _T_756 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_757 = and(_T_755, _T_756)
node _T_758 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_759 = and(_T_757, _T_758)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_760 = shr(io.in.a.bits.source, 2)
node _T_761 = eq(_T_760, UInt<1>(0h1))
node _T_762 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_763 = and(_T_761, _T_762)
node _T_764 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_765 = and(_T_763, _T_764)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_766 = shr(io.in.a.bits.source, 2)
node _T_767 = eq(_T_766, UInt<2>(0h2))
node _T_768 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_769 = and(_T_767, _T_768)
node _T_770 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_771 = and(_T_769, _T_770)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_772 = shr(io.in.a.bits.source, 2)
node _T_773 = eq(_T_772, UInt<2>(0h3))
node _T_774 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_775 = and(_T_773, _T_774)
node _T_776 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_777 = and(_T_775, _T_776)
node _T_778 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_779 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_780 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_781 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_782 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_783 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_784 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_785 = or(_T_753, _T_759)
node _T_786 = or(_T_785, _T_765)
node _T_787 = or(_T_786, _T_771)
node _T_788 = or(_T_787, _T_777)
node _T_789 = or(_T_788, _T_778)
node _T_790 = or(_T_789, _T_779)
node _T_791 = or(_T_790, _T_780)
node _T_792 = or(_T_791, _T_781)
node _T_793 = or(_T_792, _T_782)
node _T_794 = or(_T_793, _T_783)
node _T_795 = or(_T_794, _T_784)
node _T_796 = and(_T_752, _T_795)
node _T_797 = or(UInt<1>(0h0), _T_796)
node _T_798 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_799 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_800 = and(_T_798, _T_799)
node _T_801 = or(UInt<1>(0h0), _T_800)
node _T_802 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_803 = cvt(_T_802)
node _T_804 = and(_T_803, asSInt(UInt<13>(0h1000)))
node _T_805 = asSInt(_T_804)
node _T_806 = eq(_T_805, asSInt(UInt<1>(0h0)))
node _T_807 = and(_T_801, _T_806)
node _T_808 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_809 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_810 = and(_T_808, _T_809)
node _T_811 = or(UInt<1>(0h0), _T_810)
node _T_812 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_813 = cvt(_T_812)
node _T_814 = and(_T_813, asSInt(UInt<14>(0h2000)))
node _T_815 = asSInt(_T_814)
node _T_816 = eq(_T_815, asSInt(UInt<1>(0h0)))
node _T_817 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_818 = cvt(_T_817)
node _T_819 = and(_T_818, asSInt(UInt<18>(0h2f000)))
node _T_820 = asSInt(_T_819)
node _T_821 = eq(_T_820, asSInt(UInt<1>(0h0)))
node _T_822 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_823 = cvt(_T_822)
node _T_824 = and(_T_823, asSInt(UInt<17>(0h10000)))
node _T_825 = asSInt(_T_824)
node _T_826 = eq(_T_825, asSInt(UInt<1>(0h0)))
node _T_827 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_828 = cvt(_T_827)
node _T_829 = and(_T_828, asSInt(UInt<13>(0h1000)))
node _T_830 = asSInt(_T_829)
node _T_831 = eq(_T_830, asSInt(UInt<1>(0h0)))
node _T_832 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_833 = cvt(_T_832)
node _T_834 = and(_T_833, asSInt(UInt<27>(0h4000000)))
node _T_835 = asSInt(_T_834)
node _T_836 = eq(_T_835, asSInt(UInt<1>(0h0)))
node _T_837 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_838 = cvt(_T_837)
node _T_839 = and(_T_838, asSInt(UInt<13>(0h1000)))
node _T_840 = asSInt(_T_839)
node _T_841 = eq(_T_840, asSInt(UInt<1>(0h0)))
node _T_842 = or(_T_816, _T_821)
node _T_843 = or(_T_842, _T_826)
node _T_844 = or(_T_843, _T_831)
node _T_845 = or(_T_844, _T_836)
node _T_846 = or(_T_845, _T_841)
node _T_847 = and(_T_811, _T_846)
node _T_848 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_849 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_850 = cvt(_T_849)
node _T_851 = and(_T_850, asSInt(UInt<17>(0h10000)))
node _T_852 = asSInt(_T_851)
node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0)))
node _T_854 = and(_T_848, _T_853)
node _T_855 = or(UInt<1>(0h0), _T_807)
node _T_856 = or(_T_855, _T_847)
node _T_857 = or(_T_856, _T_854)
node _T_858 = and(_T_797, _T_857)
node _T_859 = asUInt(reset)
node _T_860 = eq(_T_859, UInt<1>(0h0))
when _T_860 :
node _T_861 = eq(_T_858, UInt<1>(0h0))
when _T_861 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_858, UInt<1>(0h1), "") : assert_26
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(source_ok, UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_865 = asUInt(reset)
node _T_866 = eq(_T_865, UInt<1>(0h0))
when _T_866 :
node _T_867 = eq(is_aligned, UInt<1>(0h0))
when _T_867 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_868 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_869 = asUInt(reset)
node _T_870 = eq(_T_869, UInt<1>(0h0))
when _T_870 :
node _T_871 = eq(_T_868, UInt<1>(0h0))
when _T_871 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_868, UInt<1>(0h1), "") : assert_29
node _T_872 = eq(io.in.a.bits.mask, mask)
node _T_873 = asUInt(reset)
node _T_874 = eq(_T_873, UInt<1>(0h0))
when _T_874 :
node _T_875 = eq(_T_872, UInt<1>(0h0))
when _T_875 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_872, UInt<1>(0h1), "") : assert_30
node _T_876 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_876 :
node _T_877 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_878 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_879 = and(_T_877, _T_878)
node _T_880 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_881 = shr(io.in.a.bits.source, 2)
node _T_882 = eq(_T_881, UInt<1>(0h0))
node _T_883 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_884 = and(_T_882, _T_883)
node _T_885 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_886 = and(_T_884, _T_885)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_887 = shr(io.in.a.bits.source, 2)
node _T_888 = eq(_T_887, UInt<1>(0h1))
node _T_889 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_890 = and(_T_888, _T_889)
node _T_891 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_892 = and(_T_890, _T_891)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_893 = shr(io.in.a.bits.source, 2)
node _T_894 = eq(_T_893, UInt<2>(0h2))
node _T_895 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_896 = and(_T_894, _T_895)
node _T_897 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_898 = and(_T_896, _T_897)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_899 = shr(io.in.a.bits.source, 2)
node _T_900 = eq(_T_899, UInt<2>(0h3))
node _T_901 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_902 = and(_T_900, _T_901)
node _T_903 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_904 = and(_T_902, _T_903)
node _T_905 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_906 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_907 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_908 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_909 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_910 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_911 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_912 = or(_T_880, _T_886)
node _T_913 = or(_T_912, _T_892)
node _T_914 = or(_T_913, _T_898)
node _T_915 = or(_T_914, _T_904)
node _T_916 = or(_T_915, _T_905)
node _T_917 = or(_T_916, _T_906)
node _T_918 = or(_T_917, _T_907)
node _T_919 = or(_T_918, _T_908)
node _T_920 = or(_T_919, _T_909)
node _T_921 = or(_T_920, _T_910)
node _T_922 = or(_T_921, _T_911)
node _T_923 = and(_T_879, _T_922)
node _T_924 = or(UInt<1>(0h0), _T_923)
node _T_925 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_926 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_927 = and(_T_925, _T_926)
node _T_928 = or(UInt<1>(0h0), _T_927)
node _T_929 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_930 = cvt(_T_929)
node _T_931 = and(_T_930, asSInt(UInt<13>(0h1000)))
node _T_932 = asSInt(_T_931)
node _T_933 = eq(_T_932, asSInt(UInt<1>(0h0)))
node _T_934 = and(_T_928, _T_933)
node _T_935 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_936 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_937 = and(_T_935, _T_936)
node _T_938 = or(UInt<1>(0h0), _T_937)
node _T_939 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_940 = cvt(_T_939)
node _T_941 = and(_T_940, asSInt(UInt<14>(0h2000)))
node _T_942 = asSInt(_T_941)
node _T_943 = eq(_T_942, asSInt(UInt<1>(0h0)))
node _T_944 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_945 = cvt(_T_944)
node _T_946 = and(_T_945, asSInt(UInt<18>(0h2f000)))
node _T_947 = asSInt(_T_946)
node _T_948 = eq(_T_947, asSInt(UInt<1>(0h0)))
node _T_949 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_950 = cvt(_T_949)
node _T_951 = and(_T_950, asSInt(UInt<17>(0h10000)))
node _T_952 = asSInt(_T_951)
node _T_953 = eq(_T_952, asSInt(UInt<1>(0h0)))
node _T_954 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_955 = cvt(_T_954)
node _T_956 = and(_T_955, asSInt(UInt<13>(0h1000)))
node _T_957 = asSInt(_T_956)
node _T_958 = eq(_T_957, asSInt(UInt<1>(0h0)))
node _T_959 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_960 = cvt(_T_959)
node _T_961 = and(_T_960, asSInt(UInt<27>(0h4000000)))
node _T_962 = asSInt(_T_961)
node _T_963 = eq(_T_962, asSInt(UInt<1>(0h0)))
node _T_964 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_965 = cvt(_T_964)
node _T_966 = and(_T_965, asSInt(UInt<13>(0h1000)))
node _T_967 = asSInt(_T_966)
node _T_968 = eq(_T_967, asSInt(UInt<1>(0h0)))
node _T_969 = or(_T_943, _T_948)
node _T_970 = or(_T_969, _T_953)
node _T_971 = or(_T_970, _T_958)
node _T_972 = or(_T_971, _T_963)
node _T_973 = or(_T_972, _T_968)
node _T_974 = and(_T_938, _T_973)
node _T_975 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_976 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_977 = cvt(_T_976)
node _T_978 = and(_T_977, asSInt(UInt<17>(0h10000)))
node _T_979 = asSInt(_T_978)
node _T_980 = eq(_T_979, asSInt(UInt<1>(0h0)))
node _T_981 = and(_T_975, _T_980)
node _T_982 = or(UInt<1>(0h0), _T_934)
node _T_983 = or(_T_982, _T_974)
node _T_984 = or(_T_983, _T_981)
node _T_985 = and(_T_924, _T_984)
node _T_986 = asUInt(reset)
node _T_987 = eq(_T_986, UInt<1>(0h0))
when _T_987 :
node _T_988 = eq(_T_985, UInt<1>(0h0))
when _T_988 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_985, UInt<1>(0h1), "") : assert_31
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(source_ok, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_992 = asUInt(reset)
node _T_993 = eq(_T_992, UInt<1>(0h0))
when _T_993 :
node _T_994 = eq(is_aligned, UInt<1>(0h0))
when _T_994 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_995 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_996 = asUInt(reset)
node _T_997 = eq(_T_996, UInt<1>(0h0))
when _T_997 :
node _T_998 = eq(_T_995, UInt<1>(0h0))
when _T_998 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_995, UInt<1>(0h1), "") : assert_34
node _T_999 = not(mask)
node _T_1000 = and(io.in.a.bits.mask, _T_999)
node _T_1001 = eq(_T_1000, UInt<1>(0h0))
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(_T_1001, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1001, UInt<1>(0h1), "") : assert_35
node _T_1005 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1005 :
node _T_1006 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1007 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1008 = and(_T_1006, _T_1007)
node _T_1009 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1010 = shr(io.in.a.bits.source, 2)
node _T_1011 = eq(_T_1010, UInt<1>(0h0))
node _T_1012 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1013 = and(_T_1011, _T_1012)
node _T_1014 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1015 = and(_T_1013, _T_1014)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1016 = shr(io.in.a.bits.source, 2)
node _T_1017 = eq(_T_1016, UInt<1>(0h1))
node _T_1018 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1019 = and(_T_1017, _T_1018)
node _T_1020 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1021 = and(_T_1019, _T_1020)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1022 = shr(io.in.a.bits.source, 2)
node _T_1023 = eq(_T_1022, UInt<2>(0h2))
node _T_1024 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1025 = and(_T_1023, _T_1024)
node _T_1026 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1027 = and(_T_1025, _T_1026)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1028 = shr(io.in.a.bits.source, 2)
node _T_1029 = eq(_T_1028, UInt<2>(0h3))
node _T_1030 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1031 = and(_T_1029, _T_1030)
node _T_1032 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1033 = and(_T_1031, _T_1032)
node _T_1034 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1035 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1036 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1037 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1038 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1039 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1040 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1041 = or(_T_1009, _T_1015)
node _T_1042 = or(_T_1041, _T_1021)
node _T_1043 = or(_T_1042, _T_1027)
node _T_1044 = or(_T_1043, _T_1033)
node _T_1045 = or(_T_1044, _T_1034)
node _T_1046 = or(_T_1045, _T_1035)
node _T_1047 = or(_T_1046, _T_1036)
node _T_1048 = or(_T_1047, _T_1037)
node _T_1049 = or(_T_1048, _T_1038)
node _T_1050 = or(_T_1049, _T_1039)
node _T_1051 = or(_T_1050, _T_1040)
node _T_1052 = and(_T_1008, _T_1051)
node _T_1053 = or(UInt<1>(0h0), _T_1052)
node _T_1054 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1055 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1056 = and(_T_1054, _T_1055)
node _T_1057 = or(UInt<1>(0h0), _T_1056)
node _T_1058 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1059 = cvt(_T_1058)
node _T_1060 = and(_T_1059, asSInt(UInt<15>(0h5000)))
node _T_1061 = asSInt(_T_1060)
node _T_1062 = eq(_T_1061, asSInt(UInt<1>(0h0)))
node _T_1063 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1064 = cvt(_T_1063)
node _T_1065 = and(_T_1064, asSInt(UInt<13>(0h1000)))
node _T_1066 = asSInt(_T_1065)
node _T_1067 = eq(_T_1066, asSInt(UInt<1>(0h0)))
node _T_1068 = or(_T_1062, _T_1067)
node _T_1069 = and(_T_1057, _T_1068)
node _T_1070 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1071 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1072 = cvt(_T_1071)
node _T_1073 = and(_T_1072, asSInt(UInt<13>(0h1000)))
node _T_1074 = asSInt(_T_1073)
node _T_1075 = eq(_T_1074, asSInt(UInt<1>(0h0)))
node _T_1076 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1077 = cvt(_T_1076)
node _T_1078 = and(_T_1077, asSInt(UInt<17>(0h10000)))
node _T_1079 = asSInt(_T_1078)
node _T_1080 = eq(_T_1079, asSInt(UInt<1>(0h0)))
node _T_1081 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1082 = cvt(_T_1081)
node _T_1083 = and(_T_1082, asSInt(UInt<18>(0h2f000)))
node _T_1084 = asSInt(_T_1083)
node _T_1085 = eq(_T_1084, asSInt(UInt<1>(0h0)))
node _T_1086 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1087 = cvt(_T_1086)
node _T_1088 = and(_T_1087, asSInt(UInt<17>(0h10000)))
node _T_1089 = asSInt(_T_1088)
node _T_1090 = eq(_T_1089, asSInt(UInt<1>(0h0)))
node _T_1091 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1092 = cvt(_T_1091)
node _T_1093 = and(_T_1092, asSInt(UInt<13>(0h1000)))
node _T_1094 = asSInt(_T_1093)
node _T_1095 = eq(_T_1094, asSInt(UInt<1>(0h0)))
node _T_1096 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1097 = cvt(_T_1096)
node _T_1098 = and(_T_1097, asSInt(UInt<27>(0h4000000)))
node _T_1099 = asSInt(_T_1098)
node _T_1100 = eq(_T_1099, asSInt(UInt<1>(0h0)))
node _T_1101 = or(_T_1075, _T_1080)
node _T_1102 = or(_T_1101, _T_1085)
node _T_1103 = or(_T_1102, _T_1090)
node _T_1104 = or(_T_1103, _T_1095)
node _T_1105 = or(_T_1104, _T_1100)
node _T_1106 = and(_T_1070, _T_1105)
node _T_1107 = or(UInt<1>(0h0), _T_1069)
node _T_1108 = or(_T_1107, _T_1106)
node _T_1109 = and(_T_1053, _T_1108)
node _T_1110 = asUInt(reset)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
when _T_1111 :
node _T_1112 = eq(_T_1109, UInt<1>(0h0))
when _T_1112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1109, UInt<1>(0h1), "") : assert_36
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(source_ok, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(is_aligned, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1119 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1120 = asUInt(reset)
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(_T_1119, UInt<1>(0h0))
when _T_1122 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1119, UInt<1>(0h1), "") : assert_39
node _T_1123 = eq(io.in.a.bits.mask, mask)
node _T_1124 = asUInt(reset)
node _T_1125 = eq(_T_1124, UInt<1>(0h0))
when _T_1125 :
node _T_1126 = eq(_T_1123, UInt<1>(0h0))
when _T_1126 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1123, UInt<1>(0h1), "") : assert_40
node _T_1127 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1127 :
node _T_1128 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1129 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1130 = and(_T_1128, _T_1129)
node _T_1131 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_1132 = shr(io.in.a.bits.source, 2)
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
node _T_1134 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_1135 = and(_T_1133, _T_1134)
node _T_1136 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_1137 = and(_T_1135, _T_1136)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_1138 = shr(io.in.a.bits.source, 2)
node _T_1139 = eq(_T_1138, UInt<1>(0h1))
node _T_1140 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_1141 = and(_T_1139, _T_1140)
node _T_1142 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_1143 = and(_T_1141, _T_1142)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_1144 = shr(io.in.a.bits.source, 2)
node _T_1145 = eq(_T_1144, UInt<2>(0h2))
node _T_1146 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_1147 = and(_T_1145, _T_1146)
node _T_1148 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_1149 = and(_T_1147, _T_1148)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_1150 = shr(io.in.a.bits.source, 2)
node _T_1151 = eq(_T_1150, UInt<2>(0h3))
node _T_1152 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_1153 = and(_T_1151, _T_1152)
node _T_1154 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_1155 = and(_T_1153, _T_1154)
node _T_1156 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1157 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1158 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1159 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1160 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1161 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1162 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1163 = or(_T_1131, _T_1137)
node _T_1164 = or(_T_1163, _T_1143)
node _T_1165 = or(_T_1164, _T_1149)
node _T_1166 = or(_T_1165, _T_1155)
node _T_1167 = or(_T_1166, _T_1156)
node _T_1168 = or(_T_1167, _T_1157)
node _T_1169 = or(_T_1168, _T_1158)
node _T_1170 = or(_T_1169, _T_1159)
node _T_1171 = or(_T_1170, _T_1160)
node _T_1172 = or(_T_1171, _T_1161)
node _T_1173 = or(_T_1172, _T_1162)
node _T_1174 = and(_T_1130, _T_1173)
node _T_1175 = or(UInt<1>(0h0), _T_1174)
node _T_1176 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1177 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_1178 = and(_T_1176, _T_1177)
node _T_1179 = or(UInt<1>(0h0), _T_1178)
node _T_1180 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1181 = cvt(_T_1180)
node _T_1182 = and(_T_1181, asSInt(UInt<15>(0h5000)))
node _T_1183 = asSInt(_T_1182)
node _T_1184 = eq(_T_1183, asSInt(UInt<1>(0h0)))
node _T_1185 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1186 = cvt(_T_1185)
node _T_1187 = and(_T_1186, asSInt(UInt<13>(0h1000)))
node _T_1188 = asSInt(_T_1187)
node _T_1189 = eq(_T_1188, asSInt(UInt<1>(0h0)))
node _T_1190 = or(_T_1184, _T_1189)
node _T_1191 = and(_T_1179, _T_1190)
node _T_1192 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1193 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1194 = cvt(_T_1193)
node _T_1195 = and(_T_1194, asSInt(UInt<13>(0h1000)))
node _T_1196 = asSInt(_T_1195)
node _T_1197 = eq(_T_1196, asSInt(UInt<1>(0h0)))
node _T_1198 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1199 = cvt(_T_1198)
node _T_1200 = and(_T_1199, asSInt(UInt<17>(0h10000)))
node _T_1201 = asSInt(_T_1200)
node _T_1202 = eq(_T_1201, asSInt(UInt<1>(0h0)))
node _T_1203 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1204 = cvt(_T_1203)
node _T_1205 = and(_T_1204, asSInt(UInt<18>(0h2f000)))
node _T_1206 = asSInt(_T_1205)
node _T_1207 = eq(_T_1206, asSInt(UInt<1>(0h0)))
node _T_1208 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1209 = cvt(_T_1208)
node _T_1210 = and(_T_1209, asSInt(UInt<17>(0h10000)))
node _T_1211 = asSInt(_T_1210)
node _T_1212 = eq(_T_1211, asSInt(UInt<1>(0h0)))
node _T_1213 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1214 = cvt(_T_1213)
node _T_1215 = and(_T_1214, asSInt(UInt<13>(0h1000)))
node _T_1216 = asSInt(_T_1215)
node _T_1217 = eq(_T_1216, asSInt(UInt<1>(0h0)))
node _T_1218 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1219 = cvt(_T_1218)
node _T_1220 = and(_T_1219, asSInt(UInt<27>(0h4000000)))
node _T_1221 = asSInt(_T_1220)
node _T_1222 = eq(_T_1221, asSInt(UInt<1>(0h0)))
node _T_1223 = or(_T_1197, _T_1202)
node _T_1224 = or(_T_1223, _T_1207)
node _T_1225 = or(_T_1224, _T_1212)
node _T_1226 = or(_T_1225, _T_1217)
node _T_1227 = or(_T_1226, _T_1222)
node _T_1228 = and(_T_1192, _T_1227)
node _T_1229 = or(UInt<1>(0h0), _T_1191)
node _T_1230 = or(_T_1229, _T_1228)
node _T_1231 = and(_T_1175, _T_1230)
node _T_1232 = asUInt(reset)
node _T_1233 = eq(_T_1232, UInt<1>(0h0))
when _T_1233 :
node _T_1234 = eq(_T_1231, UInt<1>(0h0))
when _T_1234 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1231, UInt<1>(0h1), "") : assert_41
node _T_1235 = asUInt(reset)
node _T_1236 = eq(_T_1235, UInt<1>(0h0))
when _T_1236 :
node _T_1237 = eq(source_ok, UInt<1>(0h0))
when _T_1237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(is_aligned, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1241 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_44
node _T_1245 = eq(io.in.a.bits.mask, mask)
node _T_1246 = asUInt(reset)
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
when _T_1247 :
node _T_1248 = eq(_T_1245, UInt<1>(0h0))
when _T_1248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1245, UInt<1>(0h1), "") : assert_45
node _T_1249 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1249 :
node _T_1250 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1251 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1252 = and(_T_1250, _T_1251)
node _T_1253 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_1254 = shr(io.in.a.bits.source, 2)
node _T_1255 = eq(_T_1254, UInt<1>(0h0))
node _T_1256 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_1257 = and(_T_1255, _T_1256)
node _T_1258 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_1259 = and(_T_1257, _T_1258)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_1260 = shr(io.in.a.bits.source, 2)
node _T_1261 = eq(_T_1260, UInt<1>(0h1))
node _T_1262 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_1263 = and(_T_1261, _T_1262)
node _T_1264 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_1265 = and(_T_1263, _T_1264)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_1266 = shr(io.in.a.bits.source, 2)
node _T_1267 = eq(_T_1266, UInt<2>(0h2))
node _T_1268 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1269 = and(_T_1267, _T_1268)
node _T_1270 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_1271 = and(_T_1269, _T_1270)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_1272 = shr(io.in.a.bits.source, 2)
node _T_1273 = eq(_T_1272, UInt<2>(0h3))
node _T_1274 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1275 = and(_T_1273, _T_1274)
node _T_1276 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_1277 = and(_T_1275, _T_1276)
node _T_1278 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1279 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1280 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1281 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1282 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1283 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1284 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1285 = or(_T_1253, _T_1259)
node _T_1286 = or(_T_1285, _T_1265)
node _T_1287 = or(_T_1286, _T_1271)
node _T_1288 = or(_T_1287, _T_1277)
node _T_1289 = or(_T_1288, _T_1278)
node _T_1290 = or(_T_1289, _T_1279)
node _T_1291 = or(_T_1290, _T_1280)
node _T_1292 = or(_T_1291, _T_1281)
node _T_1293 = or(_T_1292, _T_1282)
node _T_1294 = or(_T_1293, _T_1283)
node _T_1295 = or(_T_1294, _T_1284)
node _T_1296 = and(_T_1252, _T_1295)
node _T_1297 = or(UInt<1>(0h0), _T_1296)
node _T_1298 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1299 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1300 = and(_T_1298, _T_1299)
node _T_1301 = or(UInt<1>(0h0), _T_1300)
node _T_1302 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1303 = cvt(_T_1302)
node _T_1304 = and(_T_1303, asSInt(UInt<13>(0h1000)))
node _T_1305 = asSInt(_T_1304)
node _T_1306 = eq(_T_1305, asSInt(UInt<1>(0h0)))
node _T_1307 = and(_T_1301, _T_1306)
node _T_1308 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1309 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1310 = cvt(_T_1309)
node _T_1311 = and(_T_1310, asSInt(UInt<14>(0h2000)))
node _T_1312 = asSInt(_T_1311)
node _T_1313 = eq(_T_1312, asSInt(UInt<1>(0h0)))
node _T_1314 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1315 = cvt(_T_1314)
node _T_1316 = and(_T_1315, asSInt(UInt<17>(0h10000)))
node _T_1317 = asSInt(_T_1316)
node _T_1318 = eq(_T_1317, asSInt(UInt<1>(0h0)))
node _T_1319 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1320 = cvt(_T_1319)
node _T_1321 = and(_T_1320, asSInt(UInt<18>(0h2f000)))
node _T_1322 = asSInt(_T_1321)
node _T_1323 = eq(_T_1322, asSInt(UInt<1>(0h0)))
node _T_1324 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1325 = cvt(_T_1324)
node _T_1326 = and(_T_1325, asSInt(UInt<17>(0h10000)))
node _T_1327 = asSInt(_T_1326)
node _T_1328 = eq(_T_1327, asSInt(UInt<1>(0h0)))
node _T_1329 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_1330 = cvt(_T_1329)
node _T_1331 = and(_T_1330, asSInt(UInt<13>(0h1000)))
node _T_1332 = asSInt(_T_1331)
node _T_1333 = eq(_T_1332, asSInt(UInt<1>(0h0)))
node _T_1334 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1335 = cvt(_T_1334)
node _T_1336 = and(_T_1335, asSInt(UInt<27>(0h4000000)))
node _T_1337 = asSInt(_T_1336)
node _T_1338 = eq(_T_1337, asSInt(UInt<1>(0h0)))
node _T_1339 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1340 = cvt(_T_1339)
node _T_1341 = and(_T_1340, asSInt(UInt<13>(0h1000)))
node _T_1342 = asSInt(_T_1341)
node _T_1343 = eq(_T_1342, asSInt(UInt<1>(0h0)))
node _T_1344 = or(_T_1313, _T_1318)
node _T_1345 = or(_T_1344, _T_1323)
node _T_1346 = or(_T_1345, _T_1328)
node _T_1347 = or(_T_1346, _T_1333)
node _T_1348 = or(_T_1347, _T_1338)
node _T_1349 = or(_T_1348, _T_1343)
node _T_1350 = and(_T_1308, _T_1349)
node _T_1351 = or(UInt<1>(0h0), _T_1307)
node _T_1352 = or(_T_1351, _T_1350)
node _T_1353 = and(_T_1297, _T_1352)
node _T_1354 = asUInt(reset)
node _T_1355 = eq(_T_1354, UInt<1>(0h0))
when _T_1355 :
node _T_1356 = eq(_T_1353, UInt<1>(0h0))
when _T_1356 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1353, UInt<1>(0h1), "") : assert_46
node _T_1357 = asUInt(reset)
node _T_1358 = eq(_T_1357, UInt<1>(0h0))
when _T_1358 :
node _T_1359 = eq(source_ok, UInt<1>(0h0))
when _T_1359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1360 = asUInt(reset)
node _T_1361 = eq(_T_1360, UInt<1>(0h0))
when _T_1361 :
node _T_1362 = eq(is_aligned, UInt<1>(0h0))
when _T_1362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1363 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1364 = asUInt(reset)
node _T_1365 = eq(_T_1364, UInt<1>(0h0))
when _T_1365 :
node _T_1366 = eq(_T_1363, UInt<1>(0h0))
when _T_1366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1363, UInt<1>(0h1), "") : assert_49
node _T_1367 = eq(io.in.a.bits.mask, mask)
node _T_1368 = asUInt(reset)
node _T_1369 = eq(_T_1368, UInt<1>(0h0))
when _T_1369 :
node _T_1370 = eq(_T_1367, UInt<1>(0h0))
when _T_1370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1367, UInt<1>(0h1), "") : assert_50
node _T_1371 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1372 = asUInt(reset)
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(_T_1371, UInt<1>(0h0))
when _T_1374 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1371, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1375 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_52
node _source_ok_T_42 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_43 = shr(io.in.d.bits.source, 2)
node _source_ok_T_44 = eq(_source_ok_T_43, UInt<1>(0h0))
node _source_ok_T_45 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45)
node _source_ok_T_47 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_49 = shr(io.in.d.bits.source, 2)
node _source_ok_T_50 = eq(_source_ok_T_49, UInt<1>(0h1))
node _source_ok_T_51 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51)
node _source_ok_T_53 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_55 = shr(io.in.d.bits.source, 2)
node _source_ok_T_56 = eq(_source_ok_T_55, UInt<2>(0h2))
node _source_ok_T_57 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_58 = and(_source_ok_T_56, _source_ok_T_57)
node _source_ok_T_59 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_61 = shr(io.in.d.bits.source, 2)
node _source_ok_T_62 = eq(_source_ok_T_61, UInt<2>(0h3))
node _source_ok_T_63 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_T_65 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65)
node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_68 = eq(io.in.d.bits.source, UInt<6>(0h25))
node _source_ok_T_69 = eq(io.in.d.bits.source, UInt<6>(0h26))
node _source_ok_T_70 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_71 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[12]
connect _source_ok_WIRE_1[0], _source_ok_T_42
connect _source_ok_WIRE_1[1], _source_ok_T_48
connect _source_ok_WIRE_1[2], _source_ok_T_54
connect _source_ok_WIRE_1[3], _source_ok_T_60
connect _source_ok_WIRE_1[4], _source_ok_T_66
connect _source_ok_WIRE_1[5], _source_ok_T_67
connect _source_ok_WIRE_1[6], _source_ok_T_68
connect _source_ok_WIRE_1[7], _source_ok_T_69
connect _source_ok_WIRE_1[8], _source_ok_T_70
connect _source_ok_WIRE_1[9], _source_ok_T_71
connect _source_ok_WIRE_1[10], _source_ok_T_72
connect _source_ok_WIRE_1[11], _source_ok_T_73
node _source_ok_T_74 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[2])
node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[3])
node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[4])
node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[5])
node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[6])
node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[7])
node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[8])
node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[9])
node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[10])
node source_ok_1 = or(_source_ok_T_83, _source_ok_WIRE_1[11])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1379 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1379 :
node _T_1380 = asUInt(reset)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
when _T_1381 :
node _T_1382 = eq(source_ok_1, UInt<1>(0h0))
when _T_1382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1383 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1384 = asUInt(reset)
node _T_1385 = eq(_T_1384, UInt<1>(0h0))
when _T_1385 :
node _T_1386 = eq(_T_1383, UInt<1>(0h0))
when _T_1386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1383, UInt<1>(0h1), "") : assert_54
node _T_1387 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1388 = asUInt(reset)
node _T_1389 = eq(_T_1388, UInt<1>(0h0))
when _T_1389 :
node _T_1390 = eq(_T_1387, UInt<1>(0h0))
when _T_1390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1387, UInt<1>(0h1), "") : assert_55
node _T_1391 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1392 = asUInt(reset)
node _T_1393 = eq(_T_1392, UInt<1>(0h0))
when _T_1393 :
node _T_1394 = eq(_T_1391, UInt<1>(0h0))
when _T_1394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1391, UInt<1>(0h1), "") : assert_56
node _T_1395 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1396 = asUInt(reset)
node _T_1397 = eq(_T_1396, UInt<1>(0h0))
when _T_1397 :
node _T_1398 = eq(_T_1395, UInt<1>(0h0))
when _T_1398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1395, UInt<1>(0h1), "") : assert_57
node _T_1399 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1399 :
node _T_1400 = asUInt(reset)
node _T_1401 = eq(_T_1400, UInt<1>(0h0))
when _T_1401 :
node _T_1402 = eq(source_ok_1, UInt<1>(0h0))
when _T_1402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1403 = asUInt(reset)
node _T_1404 = eq(_T_1403, UInt<1>(0h0))
when _T_1404 :
node _T_1405 = eq(sink_ok, UInt<1>(0h0))
when _T_1405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1406 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1407 = asUInt(reset)
node _T_1408 = eq(_T_1407, UInt<1>(0h0))
when _T_1408 :
node _T_1409 = eq(_T_1406, UInt<1>(0h0))
when _T_1409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1406, UInt<1>(0h1), "") : assert_60
node _T_1410 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1411 = asUInt(reset)
node _T_1412 = eq(_T_1411, UInt<1>(0h0))
when _T_1412 :
node _T_1413 = eq(_T_1410, UInt<1>(0h0))
when _T_1413 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1410, UInt<1>(0h1), "") : assert_61
node _T_1414 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1415 = asUInt(reset)
node _T_1416 = eq(_T_1415, UInt<1>(0h0))
when _T_1416 :
node _T_1417 = eq(_T_1414, UInt<1>(0h0))
when _T_1417 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1414, UInt<1>(0h1), "") : assert_62
node _T_1418 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1419 = asUInt(reset)
node _T_1420 = eq(_T_1419, UInt<1>(0h0))
when _T_1420 :
node _T_1421 = eq(_T_1418, UInt<1>(0h0))
when _T_1421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1418, UInt<1>(0h1), "") : assert_63
node _T_1422 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1423 = or(UInt<1>(0h1), _T_1422)
node _T_1424 = asUInt(reset)
node _T_1425 = eq(_T_1424, UInt<1>(0h0))
when _T_1425 :
node _T_1426 = eq(_T_1423, UInt<1>(0h0))
when _T_1426 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1423, UInt<1>(0h1), "") : assert_64
node _T_1427 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1427 :
node _T_1428 = asUInt(reset)
node _T_1429 = eq(_T_1428, UInt<1>(0h0))
when _T_1429 :
node _T_1430 = eq(source_ok_1, UInt<1>(0h0))
when _T_1430 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1431 = asUInt(reset)
node _T_1432 = eq(_T_1431, UInt<1>(0h0))
when _T_1432 :
node _T_1433 = eq(sink_ok, UInt<1>(0h0))
when _T_1433 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1434 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1435 = asUInt(reset)
node _T_1436 = eq(_T_1435, UInt<1>(0h0))
when _T_1436 :
node _T_1437 = eq(_T_1434, UInt<1>(0h0))
when _T_1437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1434, UInt<1>(0h1), "") : assert_67
node _T_1438 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1439 = asUInt(reset)
node _T_1440 = eq(_T_1439, UInt<1>(0h0))
when _T_1440 :
node _T_1441 = eq(_T_1438, UInt<1>(0h0))
when _T_1441 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1438, UInt<1>(0h1), "") : assert_68
node _T_1442 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1443 = asUInt(reset)
node _T_1444 = eq(_T_1443, UInt<1>(0h0))
when _T_1444 :
node _T_1445 = eq(_T_1442, UInt<1>(0h0))
when _T_1445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1442, UInt<1>(0h1), "") : assert_69
node _T_1446 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1447 = or(_T_1446, io.in.d.bits.corrupt)
node _T_1448 = asUInt(reset)
node _T_1449 = eq(_T_1448, UInt<1>(0h0))
when _T_1449 :
node _T_1450 = eq(_T_1447, UInt<1>(0h0))
when _T_1450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1447, UInt<1>(0h1), "") : assert_70
node _T_1451 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1452 = or(UInt<1>(0h1), _T_1451)
node _T_1453 = asUInt(reset)
node _T_1454 = eq(_T_1453, UInt<1>(0h0))
when _T_1454 :
node _T_1455 = eq(_T_1452, UInt<1>(0h0))
when _T_1455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1452, UInt<1>(0h1), "") : assert_71
node _T_1456 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1456 :
node _T_1457 = asUInt(reset)
node _T_1458 = eq(_T_1457, UInt<1>(0h0))
when _T_1458 :
node _T_1459 = eq(source_ok_1, UInt<1>(0h0))
when _T_1459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1460 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1461 = asUInt(reset)
node _T_1462 = eq(_T_1461, UInt<1>(0h0))
when _T_1462 :
node _T_1463 = eq(_T_1460, UInt<1>(0h0))
when _T_1463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1460, UInt<1>(0h1), "") : assert_73
node _T_1464 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(_T_1464, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1464, UInt<1>(0h1), "") : assert_74
node _T_1468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1469 = or(UInt<1>(0h1), _T_1468)
node _T_1470 = asUInt(reset)
node _T_1471 = eq(_T_1470, UInt<1>(0h0))
when _T_1471 :
node _T_1472 = eq(_T_1469, UInt<1>(0h0))
when _T_1472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1469, UInt<1>(0h1), "") : assert_75
node _T_1473 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1473 :
node _T_1474 = asUInt(reset)
node _T_1475 = eq(_T_1474, UInt<1>(0h0))
when _T_1475 :
node _T_1476 = eq(source_ok_1, UInt<1>(0h0))
when _T_1476 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1477 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1478 = asUInt(reset)
node _T_1479 = eq(_T_1478, UInt<1>(0h0))
when _T_1479 :
node _T_1480 = eq(_T_1477, UInt<1>(0h0))
when _T_1480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1477, UInt<1>(0h1), "") : assert_77
node _T_1481 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1482 = or(_T_1481, io.in.d.bits.corrupt)
node _T_1483 = asUInt(reset)
node _T_1484 = eq(_T_1483, UInt<1>(0h0))
when _T_1484 :
node _T_1485 = eq(_T_1482, UInt<1>(0h0))
when _T_1485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1482, UInt<1>(0h1), "") : assert_78
node _T_1486 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1487 = or(UInt<1>(0h1), _T_1486)
node _T_1488 = asUInt(reset)
node _T_1489 = eq(_T_1488, UInt<1>(0h0))
when _T_1489 :
node _T_1490 = eq(_T_1487, UInt<1>(0h0))
when _T_1490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1487, UInt<1>(0h1), "") : assert_79
node _T_1491 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1491 :
node _T_1492 = asUInt(reset)
node _T_1493 = eq(_T_1492, UInt<1>(0h0))
when _T_1493 :
node _T_1494 = eq(source_ok_1, UInt<1>(0h0))
when _T_1494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1495 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1496 = asUInt(reset)
node _T_1497 = eq(_T_1496, UInt<1>(0h0))
when _T_1497 :
node _T_1498 = eq(_T_1495, UInt<1>(0h0))
when _T_1498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1495, UInt<1>(0h1), "") : assert_81
node _T_1499 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1500 = asUInt(reset)
node _T_1501 = eq(_T_1500, UInt<1>(0h0))
when _T_1501 :
node _T_1502 = eq(_T_1499, UInt<1>(0h0))
when _T_1502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1499, UInt<1>(0h1), "") : assert_82
node _T_1503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1504 = or(UInt<1>(0h1), _T_1503)
node _T_1505 = asUInt(reset)
node _T_1506 = eq(_T_1505, UInt<1>(0h0))
when _T_1506 :
node _T_1507 = eq(_T_1504, UInt<1>(0h0))
when _T_1507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1504, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<29>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1508 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1509 = asUInt(reset)
node _T_1510 = eq(_T_1509, UInt<1>(0h0))
when _T_1510 :
node _T_1511 = eq(_T_1508, UInt<1>(0h0))
when _T_1511 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1508, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<29>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1512 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1513 = asUInt(reset)
node _T_1514 = eq(_T_1513, UInt<1>(0h0))
when _T_1514 :
node _T_1515 = eq(_T_1512, UInt<1>(0h0))
when _T_1515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1512, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1516 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1517 = asUInt(reset)
node _T_1518 = eq(_T_1517, UInt<1>(0h0))
when _T_1518 :
node _T_1519 = eq(_T_1516, UInt<1>(0h0))
when _T_1519 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1516, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1520 = eq(a_first, UInt<1>(0h0))
node _T_1521 = and(io.in.a.valid, _T_1520)
when _T_1521 :
node _T_1522 = eq(io.in.a.bits.opcode, opcode)
node _T_1523 = asUInt(reset)
node _T_1524 = eq(_T_1523, UInt<1>(0h0))
when _T_1524 :
node _T_1525 = eq(_T_1522, UInt<1>(0h0))
when _T_1525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1522, UInt<1>(0h1), "") : assert_87
node _T_1526 = eq(io.in.a.bits.param, param)
node _T_1527 = asUInt(reset)
node _T_1528 = eq(_T_1527, UInt<1>(0h0))
when _T_1528 :
node _T_1529 = eq(_T_1526, UInt<1>(0h0))
when _T_1529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1526, UInt<1>(0h1), "") : assert_88
node _T_1530 = eq(io.in.a.bits.size, size)
node _T_1531 = asUInt(reset)
node _T_1532 = eq(_T_1531, UInt<1>(0h0))
when _T_1532 :
node _T_1533 = eq(_T_1530, UInt<1>(0h0))
when _T_1533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1530, UInt<1>(0h1), "") : assert_89
node _T_1534 = eq(io.in.a.bits.source, source)
node _T_1535 = asUInt(reset)
node _T_1536 = eq(_T_1535, UInt<1>(0h0))
when _T_1536 :
node _T_1537 = eq(_T_1534, UInt<1>(0h0))
when _T_1537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1534, UInt<1>(0h1), "") : assert_90
node _T_1538 = eq(io.in.a.bits.address, address)
node _T_1539 = asUInt(reset)
node _T_1540 = eq(_T_1539, UInt<1>(0h0))
when _T_1540 :
node _T_1541 = eq(_T_1538, UInt<1>(0h0))
when _T_1541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1538, UInt<1>(0h1), "") : assert_91
node _T_1542 = and(io.in.a.ready, io.in.a.valid)
node _T_1543 = and(_T_1542, a_first)
when _T_1543 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1544 = eq(d_first, UInt<1>(0h0))
node _T_1545 = and(io.in.d.valid, _T_1544)
when _T_1545 :
node _T_1546 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1547 = asUInt(reset)
node _T_1548 = eq(_T_1547, UInt<1>(0h0))
when _T_1548 :
node _T_1549 = eq(_T_1546, UInt<1>(0h0))
when _T_1549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1546, UInt<1>(0h1), "") : assert_92
node _T_1550 = eq(io.in.d.bits.param, param_1)
node _T_1551 = asUInt(reset)
node _T_1552 = eq(_T_1551, UInt<1>(0h0))
when _T_1552 :
node _T_1553 = eq(_T_1550, UInt<1>(0h0))
when _T_1553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1550, UInt<1>(0h1), "") : assert_93
node _T_1554 = eq(io.in.d.bits.size, size_1)
node _T_1555 = asUInt(reset)
node _T_1556 = eq(_T_1555, UInt<1>(0h0))
when _T_1556 :
node _T_1557 = eq(_T_1554, UInt<1>(0h0))
when _T_1557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1554, UInt<1>(0h1), "") : assert_94
node _T_1558 = eq(io.in.d.bits.source, source_1)
node _T_1559 = asUInt(reset)
node _T_1560 = eq(_T_1559, UInt<1>(0h0))
when _T_1560 :
node _T_1561 = eq(_T_1558, UInt<1>(0h0))
when _T_1561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1558, UInt<1>(0h1), "") : assert_95
node _T_1562 = eq(io.in.d.bits.sink, sink)
node _T_1563 = asUInt(reset)
node _T_1564 = eq(_T_1563, UInt<1>(0h0))
when _T_1564 :
node _T_1565 = eq(_T_1562, UInt<1>(0h0))
when _T_1565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1562, UInt<1>(0h1), "") : assert_96
node _T_1566 = eq(io.in.d.bits.denied, denied)
node _T_1567 = asUInt(reset)
node _T_1568 = eq(_T_1567, UInt<1>(0h0))
when _T_1568 :
node _T_1569 = eq(_T_1566, UInt<1>(0h0))
when _T_1569 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1566, UInt<1>(0h1), "") : assert_97
node _T_1570 = and(io.in.d.ready, io.in.d.valid)
node _T_1571 = and(_T_1570, d_first)
when _T_1571 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<520>
connect a_sizes_set, UInt<520>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1572 = and(io.in.a.valid, a_first_1)
node _T_1573 = and(_T_1572, UInt<1>(0h1))
when _T_1573 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1574 = and(io.in.a.ready, io.in.a.valid)
node _T_1575 = and(_T_1574, a_first_1)
node _T_1576 = and(_T_1575, UInt<1>(0h1))
when _T_1576 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1577 = dshr(inflight, io.in.a.bits.source)
node _T_1578 = bits(_T_1577, 0, 0)
node _T_1579 = eq(_T_1578, UInt<1>(0h0))
node _T_1580 = asUInt(reset)
node _T_1581 = eq(_T_1580, UInt<1>(0h0))
when _T_1581 :
node _T_1582 = eq(_T_1579, UInt<1>(0h0))
when _T_1582 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1579, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<520>
connect d_sizes_clr, UInt<520>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1583 = and(io.in.d.valid, d_first_1)
node _T_1584 = and(_T_1583, UInt<1>(0h1))
node _T_1585 = eq(d_release_ack, UInt<1>(0h0))
node _T_1586 = and(_T_1584, _T_1585)
when _T_1586 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1587 = and(io.in.d.ready, io.in.d.valid)
node _T_1588 = and(_T_1587, d_first_1)
node _T_1589 = and(_T_1588, UInt<1>(0h1))
node _T_1590 = eq(d_release_ack, UInt<1>(0h0))
node _T_1591 = and(_T_1589, _T_1590)
when _T_1591 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1592 = and(io.in.d.valid, d_first_1)
node _T_1593 = and(_T_1592, UInt<1>(0h1))
node _T_1594 = eq(d_release_ack, UInt<1>(0h0))
node _T_1595 = and(_T_1593, _T_1594)
when _T_1595 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1596 = dshr(inflight, io.in.d.bits.source)
node _T_1597 = bits(_T_1596, 0, 0)
node _T_1598 = or(_T_1597, same_cycle_resp)
node _T_1599 = asUInt(reset)
node _T_1600 = eq(_T_1599, UInt<1>(0h0))
when _T_1600 :
node _T_1601 = eq(_T_1598, UInt<1>(0h0))
when _T_1601 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1598, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1602 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1603 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1604 = or(_T_1602, _T_1603)
node _T_1605 = asUInt(reset)
node _T_1606 = eq(_T_1605, UInt<1>(0h0))
when _T_1606 :
node _T_1607 = eq(_T_1604, UInt<1>(0h0))
when _T_1607 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1604, UInt<1>(0h1), "") : assert_100
node _T_1608 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1609 = asUInt(reset)
node _T_1610 = eq(_T_1609, UInt<1>(0h0))
when _T_1610 :
node _T_1611 = eq(_T_1608, UInt<1>(0h0))
when _T_1611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1608, UInt<1>(0h1), "") : assert_101
else :
node _T_1612 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1613 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1614 = or(_T_1612, _T_1613)
node _T_1615 = asUInt(reset)
node _T_1616 = eq(_T_1615, UInt<1>(0h0))
when _T_1616 :
node _T_1617 = eq(_T_1614, UInt<1>(0h0))
when _T_1617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1614, UInt<1>(0h1), "") : assert_102
node _T_1618 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1619 = asUInt(reset)
node _T_1620 = eq(_T_1619, UInt<1>(0h0))
when _T_1620 :
node _T_1621 = eq(_T_1618, UInt<1>(0h0))
when _T_1621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1618, UInt<1>(0h1), "") : assert_103
node _T_1622 = and(io.in.d.valid, d_first_1)
node _T_1623 = and(_T_1622, a_first_1)
node _T_1624 = and(_T_1623, io.in.a.valid)
node _T_1625 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1626 = and(_T_1624, _T_1625)
node _T_1627 = eq(d_release_ack, UInt<1>(0h0))
node _T_1628 = and(_T_1626, _T_1627)
when _T_1628 :
node _T_1629 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1630 = or(_T_1629, io.in.a.ready)
node _T_1631 = asUInt(reset)
node _T_1632 = eq(_T_1631, UInt<1>(0h0))
when _T_1632 :
node _T_1633 = eq(_T_1630, UInt<1>(0h0))
when _T_1633 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1630, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_34
node _T_1634 = orr(inflight)
node _T_1635 = eq(_T_1634, UInt<1>(0h0))
node _T_1636 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1637 = or(_T_1635, _T_1636)
node _T_1638 = lt(watchdog, plusarg_reader.out)
node _T_1639 = or(_T_1637, _T_1638)
node _T_1640 = asUInt(reset)
node _T_1641 = eq(_T_1640, UInt<1>(0h0))
when _T_1641 :
node _T_1642 = eq(_T_1639, UInt<1>(0h0))
when _T_1642 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1639, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1643 = and(io.in.a.ready, io.in.a.valid)
node _T_1644 = and(io.in.d.ready, io.in.d.valid)
node _T_1645 = or(_T_1643, _T_1644)
when _T_1645 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<29>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<520>
connect c_sizes_set, UInt<520>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<29>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1646 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<29>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1647 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1648 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1649 = and(_T_1647, _T_1648)
node _T_1650 = and(_T_1646, _T_1649)
when _T_1650 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<29>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1651 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1652 = and(_T_1651, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<29>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1653 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1654 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1655 = and(_T_1653, _T_1654)
node _T_1656 = and(_T_1652, _T_1655)
when _T_1656 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<29>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1657 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1658 = bits(_T_1657, 0, 0)
node _T_1659 = eq(_T_1658, UInt<1>(0h0))
node _T_1660 = asUInt(reset)
node _T_1661 = eq(_T_1660, UInt<1>(0h0))
when _T_1661 :
node _T_1662 = eq(_T_1659, UInt<1>(0h0))
when _T_1662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1659, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<520>
connect d_sizes_clr_1, UInt<520>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1663 = and(io.in.d.valid, d_first_2)
node _T_1664 = and(_T_1663, UInt<1>(0h1))
node _T_1665 = and(_T_1664, d_release_ack_1)
when _T_1665 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1666 = and(io.in.d.ready, io.in.d.valid)
node _T_1667 = and(_T_1666, d_first_2)
node _T_1668 = and(_T_1667, UInt<1>(0h1))
node _T_1669 = and(_T_1668, d_release_ack_1)
when _T_1669 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1670 = and(io.in.d.valid, d_first_2)
node _T_1671 = and(_T_1670, UInt<1>(0h1))
node _T_1672 = and(_T_1671, d_release_ack_1)
when _T_1672 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1673 = dshr(inflight_1, io.in.d.bits.source)
node _T_1674 = bits(_T_1673, 0, 0)
node _T_1675 = or(_T_1674, same_cycle_resp_1)
node _T_1676 = asUInt(reset)
node _T_1677 = eq(_T_1676, UInt<1>(0h0))
when _T_1677 :
node _T_1678 = eq(_T_1675, UInt<1>(0h0))
when _T_1678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1675, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<29>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1679 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1680 = asUInt(reset)
node _T_1681 = eq(_T_1680, UInt<1>(0h0))
when _T_1681 :
node _T_1682 = eq(_T_1679, UInt<1>(0h0))
when _T_1682 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1679, UInt<1>(0h1), "") : assert_108
else :
node _T_1683 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1684 = asUInt(reset)
node _T_1685 = eq(_T_1684, UInt<1>(0h0))
when _T_1685 :
node _T_1686 = eq(_T_1683, UInt<1>(0h0))
when _T_1686 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1683, UInt<1>(0h1), "") : assert_109
node _T_1687 = and(io.in.d.valid, d_first_2)
node _T_1688 = and(_T_1687, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<29>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1689 = and(_T_1688, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<29>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1690 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1691 = and(_T_1689, _T_1690)
node _T_1692 = and(_T_1691, d_release_ack_1)
node _T_1693 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1694 = and(_T_1692, _T_1693)
when _T_1694 :
node _T_1695 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<29>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1696 = or(_T_1695, _WIRE_27.ready)
node _T_1697 = asUInt(reset)
node _T_1698 = eq(_T_1697, UInt<1>(0h0))
when _T_1698 :
node _T_1699 = eq(_T_1696, UInt<1>(0h0))
when _T_1699 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1696, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_35
node _T_1700 = orr(inflight_1)
node _T_1701 = eq(_T_1700, UInt<1>(0h0))
node _T_1702 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1703 = or(_T_1701, _T_1702)
node _T_1704 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1705 = or(_T_1703, _T_1704)
node _T_1706 = asUInt(reset)
node _T_1707 = eq(_T_1706, UInt<1>(0h0))
when _T_1707 :
node _T_1708 = eq(_T_1705, UInt<1>(0h0))
when _T_1708 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:60:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1705, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<29>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1709 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1710 = and(io.in.d.ready, io.in.d.valid)
node _T_1711 = or(_T_1709, _T_1710)
when _T_1711 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_17( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_33 = _source_ok_T_32 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_34 = _source_ok_T_33 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_41 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_42 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_61 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_44 = _source_ok_T_43 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = _source_ok_T_49 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_56 = _source_ok_T_55 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_62 = _source_ok_T_61 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_66; // @[Parameters.scala:1138:31]
wire _source_ok_T_67 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_67; // @[Parameters.scala:1138:31]
wire _source_ok_T_68 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_68; // @[Parameters.scala:1138:31]
wire _source_ok_T_69 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_69; // @[Parameters.scala:1138:31]
wire _source_ok_T_70 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire _source_ok_T_71 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_71; // @[Parameters.scala:1138:31]
wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_11 = _source_ok_T_73; // @[Parameters.scala:1138:31]
wire _source_ok_T_74 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_82 = _source_ok_T_81 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_83 = _source_ok_T_82 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_83 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1643 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1643; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1643; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1711 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1711; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1711; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1711; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [519:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [519:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1576 = _T_1643 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1576 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1576 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1576 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1576 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1576 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1622 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1622 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1591 = _T_1711 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1591 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1591 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1591 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1687 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1687 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1669 = _T_1711 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1669 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1669 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1669 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module MemExeUnit :
input clock : Clock
input reset : Reset
input io_kill : UInt<1>
input io_brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}
input io_status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}
output io_ready_fu_types : UInt<1>[10]
input io_fcsr_rm : UInt<3>
input io_iss_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}
output io_arb_irf_reqs : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<7>}[1]
input io_arb_rebusys : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}[1]
input io_rrd_irf_resps : UInt<64>[1]
input io_rrd_irf_bypasses : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}[4]
output io_arb_immrf_req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>}
input io_rrd_immrf_resp : UInt<64>
output io_rrd_immrf_wakeup : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<3>, rebusy : UInt<1>}}
output io_squash_iss : UInt<1>
output io_dgen : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>}}
reg arb_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, clock
node _arb_uop_valid_T = and(io_brupdate.b1.mispredict_mask, io_iss_uop.bits.br_mask)
node _arb_uop_valid_T_1 = neq(_arb_uop_valid_T, UInt<1>(0h0))
node _arb_uop_valid_T_2 = or(_arb_uop_valid_T_1, io_kill)
node _arb_uop_valid_T_3 = eq(_arb_uop_valid_T_2, UInt<1>(0h0))
node _arb_uop_valid_T_4 = and(io_iss_uop.valid, _arb_uop_valid_T_3)
connect arb_uop.valid, _arb_uop_valid_T_4
wire arb_uop_bits_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect arb_uop_bits_out, io_iss_uop.bits
node _arb_uop_bits_out_br_mask_T = not(io_brupdate.b1.resolve_mask)
node _arb_uop_bits_out_br_mask_T_1 = and(io_iss_uop.bits.br_mask, _arb_uop_bits_out_br_mask_T)
connect arb_uop_bits_out.br_mask, _arb_uop_bits_out_br_mask_T_1
connect arb_uop.bits, arb_uop_bits_out
reg rrd_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, clock
node _rrd_uop_valid_T = and(io_brupdate.b1.mispredict_mask, arb_uop.bits.br_mask)
node _rrd_uop_valid_T_1 = neq(_rrd_uop_valid_T, UInt<1>(0h0))
node _rrd_uop_valid_T_2 = or(_rrd_uop_valid_T_1, io_kill)
node _rrd_uop_valid_T_3 = eq(_rrd_uop_valid_T_2, UInt<1>(0h0))
node _rrd_uop_valid_T_4 = and(arb_uop.valid, _rrd_uop_valid_T_3)
connect rrd_uop.valid, _rrd_uop_valid_T_4
wire rrd_uop_bits_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect rrd_uop_bits_out, arb_uop.bits
node _rrd_uop_bits_out_br_mask_T = not(io_brupdate.b1.resolve_mask)
node _rrd_uop_bits_out_br_mask_T_1 = and(arb_uop.bits.br_mask, _rrd_uop_bits_out_br_mask_T)
connect rrd_uop_bits_out.br_mask, _rrd_uop_bits_out_br_mask_T_1
connect rrd_uop.bits, rrd_uop_bits_out
reg exe_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, clock
node _exe_uop_valid_T = and(io_brupdate.b1.mispredict_mask, rrd_uop.bits.br_mask)
node _exe_uop_valid_T_1 = neq(_exe_uop_valid_T, UInt<1>(0h0))
node _exe_uop_valid_T_2 = or(_exe_uop_valid_T_1, io_kill)
node _exe_uop_valid_T_3 = eq(_exe_uop_valid_T_2, UInt<1>(0h0))
node _exe_uop_valid_T_4 = and(rrd_uop.valid, _exe_uop_valid_T_3)
connect exe_uop.valid, _exe_uop_valid_T_4
wire exe_uop_bits_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect exe_uop_bits_out, rrd_uop.bits
node _exe_uop_bits_out_br_mask_T = not(io_brupdate.b1.resolve_mask)
node _exe_uop_bits_out_br_mask_T_1 = and(rrd_uop.bits.br_mask, _exe_uop_bits_out_br_mask_T)
connect exe_uop_bits_out.br_mask, _exe_uop_bits_out_br_mask_T_1
connect exe_uop.bits, exe_uop_bits_out
node _io_arb_irf_reqs_0_valid_T = eq(arb_uop.bits.lrs1_rtype, UInt<2>(0h0))
node _io_arb_irf_reqs_0_valid_T_1 = and(arb_uop.valid, _io_arb_irf_reqs_0_valid_T)
node _io_arb_irf_reqs_0_valid_T_2 = eq(arb_uop.bits.iw_p1_bypass_hint, UInt<1>(0h0))
node _io_arb_irf_reqs_0_valid_T_3 = and(_io_arb_irf_reqs_0_valid_T_1, _io_arb_irf_reqs_0_valid_T_2)
connect io_arb_irf_reqs[0].valid, _io_arb_irf_reqs_0_valid_T_3
connect io_arb_irf_reqs[0].bits, arb_uop.bits.prs1
node _arb_rebusied_prs1_T = eq(arb_uop.bits.lrs1_rtype, UInt<2>(0h0))
node _arb_rebusied_prs1_T_1 = and(io_arb_rebusys[0].valid, io_arb_rebusys[0].bits.rebusy)
node _arb_rebusied_prs1_T_2 = eq(io_arb_rebusys[0].bits.uop.pdst, arb_uop.bits.prs1)
node _arb_rebusied_prs1_T_3 = and(_arb_rebusied_prs1_T_1, _arb_rebusied_prs1_T_2)
node arb_rebusied_prs1 = and(_arb_rebusied_prs1_T, _arb_rebusied_prs1_T_3)
node _arb_rebusied_prs2_T = eq(arb_uop.bits.lrs2_rtype, UInt<2>(0h0))
node _arb_rebusied_prs2_T_1 = and(io_arb_rebusys[0].valid, io_arb_rebusys[0].bits.rebusy)
node _arb_rebusied_prs2_T_2 = eq(io_arb_rebusys[0].bits.uop.pdst, arb_uop.bits.prs2)
node _arb_rebusied_prs2_T_3 = and(_arb_rebusied_prs2_T_1, _arb_rebusied_prs2_T_2)
node _arb_rebusied_prs2_T_4 = and(_arb_rebusied_prs2_T, _arb_rebusied_prs2_T_3)
node arb_rebusied_prs2 = and(_arb_rebusied_prs2_T_4, UInt<1>(0h0))
node arb_rebusied = or(arb_rebusied_prs1, arb_rebusied_prs2)
reg exe_rs1_data : UInt<64>, clock
reg exe_rs2_data : UInt<64>, clock
node _hits_T = eq(rrd_uop.bits.prs1, io_rrd_irf_bypasses[0].bits.uop.pdst)
node hits_0 = and(io_rrd_irf_bypasses[0].valid, _hits_T)
node _hits_T_1 = eq(rrd_uop.bits.prs1, io_rrd_irf_bypasses[1].bits.uop.pdst)
node hits_1 = and(io_rrd_irf_bypasses[1].valid, _hits_T_1)
node _hits_T_2 = eq(rrd_uop.bits.prs1, io_rrd_irf_bypasses[2].bits.uop.pdst)
node hits_2 = and(io_rrd_irf_bypasses[2].valid, _hits_T_2)
node _hits_T_3 = eq(rrd_uop.bits.prs1, io_rrd_irf_bypasses[3].bits.uop.pdst)
node hits_3 = and(io_rrd_irf_bypasses[3].valid, _hits_T_3)
node _T = or(hits_0, hits_1)
node _T_1 = or(_T, hits_2)
node rs1_hit = or(_T_1, hits_3)
node _T_2 = or(hits_0, hits_1)
node _T_3 = or(_T_2, hits_2)
node _T_4 = or(_T_3, hits_3)
node _T_5 = mux(hits_0, io_rrd_irf_bypasses[0].bits.data, UInt<1>(0h0))
node _T_6 = mux(hits_1, io_rrd_irf_bypasses[1].bits.data, UInt<1>(0h0))
node _T_7 = mux(hits_2, io_rrd_irf_bypasses[2].bits.data, UInt<1>(0h0))
node _T_8 = mux(hits_3, io_rrd_irf_bypasses[3].bits.data, UInt<1>(0h0))
node _T_9 = or(_T_5, _T_6)
node _T_10 = or(_T_9, _T_7)
node _T_11 = or(_T_10, _T_8)
wire _WIRE : UInt<64>
connect _WIRE, _T_11
node rs1_data = mux(_T_4, _WIRE, io_rrd_irf_resps[0])
node _T_12 = eq(rrd_uop.bits.lrs1_rtype, UInt<2>(0h0))
node _T_13 = and(rrd_uop.valid, _T_12)
node _T_14 = and(_T_13, rrd_uop.bits.iw_p1_bypass_hint)
node _T_15 = eq(rs1_hit, UInt<1>(0h0))
node _T_16 = and(_T_14, _T_15)
node _T_17 = eq(_T_16, UInt<1>(0h0))
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
node _T_20 = eq(_T_17, UInt<1>(0h0))
when _T_20 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at execution-unit.scala:136 assert(!(rrd_uop.valid && rrd_uop.bits.lrs1_rtype === RT_FIX && rrd_uop.bits.iw_p1_bypass_hint && !rs1_hit))\n") : printf
assert(clock, _T_17, UInt<1>(0h1), "") : assert
node _exe_rs1_data_T = eq(rrd_uop.bits.lrs1_rtype, UInt<2>(0h3))
node _exe_rs1_data_T_1 = mux(_exe_rs1_data_T, UInt<1>(0h0), rs1_data)
connect exe_rs1_data, _exe_rs1_data_T_1
invalidate exe_rs2_data
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
node _T_23 = eq(io_arb_immrf_req.ready, UInt<1>(0h0))
when _T_23 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at execution-unit.scala:152 assert(io_arb_immrf_req.ready)\n") : printf_1
assert(clock, io_arb_immrf_req.ready, UInt<1>(0h1), "") : assert_1
node _io_arb_immrf_req_valid_T = eq(arb_uop.bits.imm_sel, UInt<3>(0h6))
node _io_arb_immrf_req_valid_T_1 = eq(arb_uop.bits.imm_sel, UInt<3>(0h5))
node _io_arb_immrf_req_valid_T_2 = or(_io_arb_immrf_req_valid_T, _io_arb_immrf_req_valid_T_1)
node _io_arb_immrf_req_valid_T_3 = eq(_io_arb_immrf_req_valid_T_2, UInt<1>(0h0))
node _io_arb_immrf_req_valid_T_4 = and(arb_uop.valid, _io_arb_immrf_req_valid_T_3)
connect io_arb_immrf_req.valid, _io_arb_immrf_req_valid_T_4
connect io_arb_immrf_req.bits, arb_uop.bits.pimm
node _io_rrd_immrf_wakeup_valid_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h6))
node _io_rrd_immrf_wakeup_valid_T_1 = eq(rrd_uop.bits.imm_sel, UInt<3>(0h5))
node _io_rrd_immrf_wakeup_valid_T_2 = or(_io_rrd_immrf_wakeup_valid_T, _io_rrd_immrf_wakeup_valid_T_1)
node _io_rrd_immrf_wakeup_valid_T_3 = eq(_io_rrd_immrf_wakeup_valid_T_2, UInt<1>(0h0))
node _io_rrd_immrf_wakeup_valid_T_4 = and(rrd_uop.valid, _io_rrd_immrf_wakeup_valid_T_3)
connect io_rrd_immrf_wakeup.valid, _io_rrd_immrf_wakeup_valid_T_4
connect io_rrd_immrf_wakeup.bits.speculative_mask, UInt<1>(0h0)
connect io_rrd_immrf_wakeup.bits.rebusy, UInt<1>(0h0)
connect io_rrd_immrf_wakeup.bits.bypassable, UInt<1>(0h0)
connect io_rrd_immrf_wakeup.bits.uop, rrd_uop.bits
node _exe_imm_data_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h5))
node _exe_imm_data_T_1 = bits(rrd_uop.bits.pimm, 4, 4)
node _exe_imm_data_T_2 = mux(_exe_imm_data_T_1, UInt<59>(0h7ffffffffffffff), UInt<59>(0h0))
node _exe_imm_data_T_3 = cat(_exe_imm_data_T_2, rrd_uop.bits.pimm)
node _exe_imm_data_ip_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h6))
node exe_imm_data_ip = mux(_exe_imm_data_ip_T, UInt<20>(0h0), io_rrd_immrf_resp)
node _exe_imm_data_sign_T = bits(exe_imm_data_ip, 19, 19)
node exe_imm_data_sign = asSInt(_exe_imm_data_sign_T)
node _exe_imm_data_i30_20_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h3))
node _exe_imm_data_i30_20_T_1 = bits(exe_imm_data_ip, 18, 8)
node _exe_imm_data_i30_20_T_2 = asSInt(_exe_imm_data_i30_20_T_1)
node exe_imm_data_i30_20 = mux(_exe_imm_data_i30_20_T, _exe_imm_data_i30_20_T_2, exe_imm_data_sign)
node _exe_imm_data_i19_12_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h3))
node _exe_imm_data_i19_12_T_1 = eq(rrd_uop.bits.imm_sel, UInt<3>(0h4))
node _exe_imm_data_i19_12_T_2 = or(_exe_imm_data_i19_12_T, _exe_imm_data_i19_12_T_1)
node _exe_imm_data_i19_12_T_3 = bits(exe_imm_data_ip, 7, 0)
node _exe_imm_data_i19_12_T_4 = asSInt(_exe_imm_data_i19_12_T_3)
node exe_imm_data_i19_12 = mux(_exe_imm_data_i19_12_T_2, _exe_imm_data_i19_12_T_4, exe_imm_data_sign)
node _exe_imm_data_i11_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h3))
node _exe_imm_data_i11_T_1 = eq(rrd_uop.bits.imm_sel, UInt<3>(0h4))
node _exe_imm_data_i11_T_2 = eq(rrd_uop.bits.imm_sel, UInt<3>(0h2))
node _exe_imm_data_i11_T_3 = or(_exe_imm_data_i11_T_1, _exe_imm_data_i11_T_2)
node _exe_imm_data_i11_T_4 = bits(exe_imm_data_ip, 8, 8)
node _exe_imm_data_i11_T_5 = asSInt(_exe_imm_data_i11_T_4)
node _exe_imm_data_i11_T_6 = mux(_exe_imm_data_i11_T_3, _exe_imm_data_i11_T_5, exe_imm_data_sign)
node exe_imm_data_i11 = mux(_exe_imm_data_i11_T, asSInt(UInt<1>(0h0)), _exe_imm_data_i11_T_6)
node _exe_imm_data_i10_5_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h3))
node _exe_imm_data_i10_5_T_1 = bits(exe_imm_data_ip, 18, 14)
node _exe_imm_data_i10_5_T_2 = asSInt(_exe_imm_data_i10_5_T_1)
node exe_imm_data_i10_5 = mux(_exe_imm_data_i10_5_T, asSInt(UInt<1>(0h0)), _exe_imm_data_i10_5_T_2)
node _exe_imm_data_i4_1_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h3))
node _exe_imm_data_i4_1_T_1 = bits(exe_imm_data_ip, 13, 9)
node _exe_imm_data_i4_1_T_2 = asSInt(_exe_imm_data_i4_1_T_1)
node exe_imm_data_i4_1 = mux(_exe_imm_data_i4_1_T, asSInt(UInt<1>(0h0)), _exe_imm_data_i4_1_T_2)
node _exe_imm_data_i0_T = eq(rrd_uop.bits.imm_sel, UInt<3>(0h1))
node _exe_imm_data_i0_T_1 = eq(rrd_uop.bits.imm_sel, UInt<3>(0h0))
node _exe_imm_data_i0_T_2 = or(_exe_imm_data_i0_T, _exe_imm_data_i0_T_1)
node _exe_imm_data_i0_T_3 = bits(exe_imm_data_ip, 8, 8)
node _exe_imm_data_i0_T_4 = asSInt(_exe_imm_data_i0_T_3)
node exe_imm_data_i0 = mux(_exe_imm_data_i0_T_2, _exe_imm_data_i0_T_4, asSInt(UInt<1>(0h0)))
node exe_imm_data_lo_lo = asUInt(exe_imm_data_i0)
node exe_imm_data_lo_hi_lo = asUInt(exe_imm_data_i4_1)
node exe_imm_data_lo_hi_hi = asUInt(exe_imm_data_i10_5)
node exe_imm_data_lo_hi = cat(exe_imm_data_lo_hi_hi, exe_imm_data_lo_hi_lo)
node exe_imm_data_lo = cat(exe_imm_data_lo_hi, exe_imm_data_lo_lo)
node exe_imm_data_hi_lo_lo = asUInt(exe_imm_data_i11)
node exe_imm_data_hi_lo_hi = asUInt(exe_imm_data_i19_12)
node exe_imm_data_hi_lo = cat(exe_imm_data_hi_lo_hi, exe_imm_data_hi_lo_lo)
node exe_imm_data_hi_hi_lo = asUInt(exe_imm_data_i30_20)
node exe_imm_data_hi_hi_hi = asUInt(exe_imm_data_sign)
node exe_imm_data_hi_hi = cat(exe_imm_data_hi_hi_hi, exe_imm_data_hi_hi_lo)
node exe_imm_data_hi = cat(exe_imm_data_hi_hi, exe_imm_data_hi_lo)
node _exe_imm_data_T_4 = cat(exe_imm_data_hi, exe_imm_data_lo)
node _exe_imm_data_T_5 = bits(_exe_imm_data_T_4, 31, 31)
node _exe_imm_data_T_6 = mux(_exe_imm_data_T_5, UInt<32>(0hffffffff), UInt<32>(0h0))
node _exe_imm_data_T_7 = cat(_exe_imm_data_T_6, _exe_imm_data_T_4)
node _exe_imm_data_T_8 = mux(_exe_imm_data_T, _exe_imm_data_T_3, _exe_imm_data_T_7)
reg exe_imm_data : UInt, clock
connect exe_imm_data, _exe_imm_data_T_8
node _io_squash_iss_T = eq(io_arb_irf_reqs[0].ready, UInt<1>(0h0))
node _io_squash_iss_T_1 = and(io_arb_irf_reqs[0].valid, _io_squash_iss_T)
connect io_squash_iss, _io_squash_iss_T_1
node _T_24 = or(io_squash_iss, arb_rebusied)
when _T_24 :
node _will_replay_T = and(io_brupdate.b1.mispredict_mask, arb_uop.bits.br_mask)
node _will_replay_T_1 = neq(_will_replay_T, UInt<1>(0h0))
node _will_replay_T_2 = or(_will_replay_T_1, io_kill)
node _will_replay_T_3 = eq(_will_replay_T_2, UInt<1>(0h0))
node _will_replay_T_4 = and(arb_uop.valid, _will_replay_T_3)
node _will_replay_T_5 = eq(arb_rebusied, UInt<1>(0h0))
node will_replay = and(_will_replay_T_4, _will_replay_T_5)
connect arb_uop.valid, will_replay
wire arb_uop_bits_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect arb_uop_bits_out_1, arb_uop.bits
node _arb_uop_bits_out_br_mask_T_2 = not(io_brupdate.b1.resolve_mask)
node _arb_uop_bits_out_br_mask_T_3 = and(arb_uop.bits.br_mask, _arb_uop_bits_out_br_mask_T_2)
connect arb_uop_bits_out_1.br_mask, _arb_uop_bits_out_br_mask_T_3
connect arb_uop.bits, arb_uop_bits_out_1
connect arb_uop.bits.iw_p1_bypass_hint, UInt<1>(0h0)
connect arb_uop.bits.iw_p2_bypass_hint, UInt<1>(0h0)
connect rrd_uop.valid, UInt<1>(0h0)
node _io_agen_T = and(exe_uop.valid, exe_uop.bits.fu_code[1])
node _io_agen_T_1 = eq(_io_agen_T, UInt<1>(0h0))
node _io_agen_T_2 = asUInt(reset)
node _io_agen_T_3 = eq(_io_agen_T_2, UInt<1>(0h0))
when _io_agen_T_3 :
node _io_agen_T_4 = eq(_io_agen_T_1, UInt<1>(0h0))
when _io_agen_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at execution-unit.scala:311 assert(!(exe_uop.valid && exe_uop.bits.fu_code(FC_AGEN)))\n") : io_agen_printf
assert(clock, _io_agen_T_1, UInt<1>(0h1), "") : io_agen_assert
node _io_dgen_dgen_valid_T = and(exe_uop.valid, exe_uop.bits.fu_code[2])
connect io_dgen.valid, _io_dgen_dgen_valid_T
connect io_dgen.bits.data, exe_rs1_data
connect io_dgen.bits.uop, exe_uop.bits
wire _r_WIRE : UInt<1>[10]
connect _r_WIRE[0], UInt<1>(0h0)
connect _r_WIRE[1], UInt<1>(0h0)
connect _r_WIRE[2], UInt<1>(0h0)
connect _r_WIRE[3], UInt<1>(0h0)
connect _r_WIRE[4], UInt<1>(0h0)
connect _r_WIRE[5], UInt<1>(0h0)
connect _r_WIRE[6], UInt<1>(0h0)
connect _r_WIRE[7], UInt<1>(0h0)
connect _r_WIRE[8], UInt<1>(0h0)
connect _r_WIRE[9], UInt<1>(0h0)
wire r : UInt<1>[10]
connect r, _r_WIRE
when UInt<1>(0h1) :
connect r[2], UInt<1>(0h1)
connect io_ready_fu_types, r | module MemExeUnit( // @[execution-unit.scala:255:7]
input clock, // @[execution-unit.scala:255:7]
input reset, // @[execution-unit.scala:255:7]
input io_kill, // @[execution-unit.scala:79:19]
input [15:0] io_brupdate_b1_resolve_mask, // @[execution-unit.scala:80:23]
input [15:0] io_brupdate_b1_mispredict_mask, // @[execution-unit.scala:80:23]
input [31:0] io_brupdate_b2_uop_inst, // @[execution-unit.scala:80:23]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_rvc, // @[execution-unit.scala:80:23]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iq_type_0, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iq_type_1, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iq_type_2, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iq_type_3, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_0, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_1, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_2, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_3, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_4, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_5, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_6, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_7, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_8, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fu_code_9, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iw_issued, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[execution-unit.scala:80:23]
input [15:0] io_brupdate_b2_uop_br_mask, // @[execution-unit.scala:80:23]
input [3:0] io_brupdate_b2_uop_br_tag, // @[execution-unit.scala:80:23]
input [3:0] io_brupdate_b2_uop_br_type, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_sfb, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_fence, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_fencei, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_sfence, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_amo, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_eret, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_rocc, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_mov, // @[execution-unit.scala:80:23]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_edge_inst, // @[execution-unit.scala:80:23]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_taken, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_imm_rename, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[execution-unit.scala:80:23]
input [4:0] io_brupdate_b2_uop_pimm, // @[execution-unit.scala:80:23]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_div, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[execution-unit.scala:80:23]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[execution-unit.scala:80:23]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[execution-unit.scala:80:23]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[execution-unit.scala:80:23]
input [6:0] io_brupdate_b2_uop_pdst, // @[execution-unit.scala:80:23]
input [6:0] io_brupdate_b2_uop_prs1, // @[execution-unit.scala:80:23]
input [6:0] io_brupdate_b2_uop_prs2, // @[execution-unit.scala:80:23]
input [6:0] io_brupdate_b2_uop_prs3, // @[execution-unit.scala:80:23]
input [4:0] io_brupdate_b2_uop_ppred, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_prs1_busy, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_prs2_busy, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_prs3_busy, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_ppred_busy, // @[execution-unit.scala:80:23]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_exception, // @[execution-unit.scala:80:23]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[execution-unit.scala:80:23]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_mem_size, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_mem_signed, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_uses_ldq, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_uses_stq, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_is_unique, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_flush_on_commit, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_ldst_is_rs1, // @[execution-unit.scala:80:23]
input [5:0] io_brupdate_b2_uop_ldst, // @[execution-unit.scala:80:23]
input [5:0] io_brupdate_b2_uop_lrs1, // @[execution-unit.scala:80:23]
input [5:0] io_brupdate_b2_uop_lrs2, // @[execution-unit.scala:80:23]
input [5:0] io_brupdate_b2_uop_lrs3, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_frs3_en, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fcn_dw, // @[execution-unit.scala:80:23]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_fp_val, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_xcpt_pf_if, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_xcpt_ae_if, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_xcpt_ma_if, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_bp_debug_if, // @[execution-unit.scala:80:23]
input io_brupdate_b2_uop_bp_xcpt_if, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[execution-unit.scala:80:23]
input io_brupdate_b2_mispredict, // @[execution-unit.scala:80:23]
input io_brupdate_b2_taken, // @[execution-unit.scala:80:23]
input [2:0] io_brupdate_b2_cfi_type, // @[execution-unit.scala:80:23]
input [1:0] io_brupdate_b2_pc_sel, // @[execution-unit.scala:80:23]
input [39:0] io_brupdate_b2_jalr_target, // @[execution-unit.scala:80:23]
input [20:0] io_brupdate_b2_target_offset, // @[execution-unit.scala:80:23]
input io_status_debug, // @[execution-unit.scala:81:21]
input io_status_cease, // @[execution-unit.scala:81:21]
input io_status_wfi, // @[execution-unit.scala:81:21]
input [1:0] io_status_dprv, // @[execution-unit.scala:81:21]
input io_status_dv, // @[execution-unit.scala:81:21]
input [1:0] io_status_prv, // @[execution-unit.scala:81:21]
input io_status_v, // @[execution-unit.scala:81:21]
input io_status_sd, // @[execution-unit.scala:81:21]
input io_status_mpv, // @[execution-unit.scala:81:21]
input io_status_gva, // @[execution-unit.scala:81:21]
input io_status_tsr, // @[execution-unit.scala:81:21]
input io_status_tw, // @[execution-unit.scala:81:21]
input io_status_tvm, // @[execution-unit.scala:81:21]
input io_status_mxr, // @[execution-unit.scala:81:21]
input io_status_sum, // @[execution-unit.scala:81:21]
input io_status_mprv, // @[execution-unit.scala:81:21]
input [1:0] io_status_fs, // @[execution-unit.scala:81:21]
input [1:0] io_status_mpp, // @[execution-unit.scala:81:21]
input io_status_spp, // @[execution-unit.scala:81:21]
input io_status_mpie, // @[execution-unit.scala:81:21]
input io_status_spie, // @[execution-unit.scala:81:21]
input io_status_mie, // @[execution-unit.scala:81:21]
input io_status_sie, // @[execution-unit.scala:81:21]
input [2:0] io_fcsr_rm, // @[execution-unit.scala:84:22]
input io_iss_uop_valid, // @[execution-unit.scala:90:22]
input [31:0] io_iss_uop_bits_inst, // @[execution-unit.scala:90:22]
input [31:0] io_iss_uop_bits_debug_inst, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_rvc, // @[execution-unit.scala:90:22]
input [39:0] io_iss_uop_bits_debug_pc, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iq_type_0, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iq_type_1, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iq_type_2, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iq_type_3, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_0, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_1, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_2, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_3, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_4, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_5, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_6, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_7, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_8, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fu_code_9, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iw_issued, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iw_issued_partial_agen, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iw_issued_partial_dgen, // @[execution-unit.scala:90:22]
input [2:0] io_iss_uop_bits_iw_p1_speculative_child, // @[execution-unit.scala:90:22]
input [2:0] io_iss_uop_bits_iw_p2_speculative_child, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iw_p1_bypass_hint, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iw_p2_bypass_hint, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_iw_p3_bypass_hint, // @[execution-unit.scala:90:22]
input [2:0] io_iss_uop_bits_dis_col_sel, // @[execution-unit.scala:90:22]
input [15:0] io_iss_uop_bits_br_mask, // @[execution-unit.scala:90:22]
input [3:0] io_iss_uop_bits_br_tag, // @[execution-unit.scala:90:22]
input [3:0] io_iss_uop_bits_br_type, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_sfb, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_fence, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_fencei, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_sfence, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_amo, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_eret, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_sys_pc2epc, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_rocc, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_mov, // @[execution-unit.scala:90:22]
input [4:0] io_iss_uop_bits_ftq_idx, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_edge_inst, // @[execution-unit.scala:90:22]
input [5:0] io_iss_uop_bits_pc_lob, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_taken, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_imm_rename, // @[execution-unit.scala:90:22]
input [2:0] io_iss_uop_bits_imm_sel, // @[execution-unit.scala:90:22]
input [4:0] io_iss_uop_bits_pimm, // @[execution-unit.scala:90:22]
input [19:0] io_iss_uop_bits_imm_packed, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_op1_sel, // @[execution-unit.scala:90:22]
input [2:0] io_iss_uop_bits_op2_sel, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_ldst, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_wen, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_ren1, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_ren2, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_ren3, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_swap12, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_swap23, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_fp_ctrl_typeTagIn, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_fp_ctrl_typeTagOut, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_fromint, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_toint, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_fastpipe, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_fma, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_div, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_sqrt, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_wflags, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_ctrl_vec, // @[execution-unit.scala:90:22]
input [6:0] io_iss_uop_bits_rob_idx, // @[execution-unit.scala:90:22]
input [4:0] io_iss_uop_bits_ldq_idx, // @[execution-unit.scala:90:22]
input [4:0] io_iss_uop_bits_stq_idx, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_rxq_idx, // @[execution-unit.scala:90:22]
input [6:0] io_iss_uop_bits_pdst, // @[execution-unit.scala:90:22]
input [6:0] io_iss_uop_bits_prs1, // @[execution-unit.scala:90:22]
input [6:0] io_iss_uop_bits_prs2, // @[execution-unit.scala:90:22]
input [6:0] io_iss_uop_bits_prs3, // @[execution-unit.scala:90:22]
input [4:0] io_iss_uop_bits_ppred, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_prs1_busy, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_prs2_busy, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_prs3_busy, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_ppred_busy, // @[execution-unit.scala:90:22]
input [6:0] io_iss_uop_bits_stale_pdst, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_exception, // @[execution-unit.scala:90:22]
input [63:0] io_iss_uop_bits_exc_cause, // @[execution-unit.scala:90:22]
input [4:0] io_iss_uop_bits_mem_cmd, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_mem_size, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_mem_signed, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_uses_ldq, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_uses_stq, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_is_unique, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_flush_on_commit, // @[execution-unit.scala:90:22]
input [2:0] io_iss_uop_bits_csr_cmd, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_ldst_is_rs1, // @[execution-unit.scala:90:22]
input [5:0] io_iss_uop_bits_ldst, // @[execution-unit.scala:90:22]
input [5:0] io_iss_uop_bits_lrs1, // @[execution-unit.scala:90:22]
input [5:0] io_iss_uop_bits_lrs2, // @[execution-unit.scala:90:22]
input [5:0] io_iss_uop_bits_lrs3, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_dst_rtype, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_lrs1_rtype, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_frs3_en, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fcn_dw, // @[execution-unit.scala:90:22]
input [4:0] io_iss_uop_bits_fcn_op, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_fp_val, // @[execution-unit.scala:90:22]
input [2:0] io_iss_uop_bits_fp_rm, // @[execution-unit.scala:90:22]
input [1:0] io_iss_uop_bits_fp_typ, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_xcpt_pf_if, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_xcpt_ae_if, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_xcpt_ma_if, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_bp_debug_if, // @[execution-unit.scala:90:22]
input io_iss_uop_bits_bp_xcpt_if, // @[execution-unit.scala:90:22]
input [2:0] io_iss_uop_bits_debug_fsrc, // @[execution-unit.scala:90:22]
input [2:0] io_iss_uop_bits_debug_tsrc, // @[execution-unit.scala:90:22]
input io_arb_irf_reqs_0_ready, // @[execution-unit.scala:106:27]
output io_arb_irf_reqs_0_valid, // @[execution-unit.scala:106:27]
output [6:0] io_arb_irf_reqs_0_bits, // @[execution-unit.scala:106:27]
input io_arb_rebusys_0_valid, // @[execution-unit.scala:107:27]
input [31:0] io_arb_rebusys_0_bits_uop_inst, // @[execution-unit.scala:107:27]
input [31:0] io_arb_rebusys_0_bits_uop_debug_inst, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_rvc, // @[execution-unit.scala:107:27]
input [39:0] io_arb_rebusys_0_bits_uop_debug_pc, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iq_type_0, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iq_type_1, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iq_type_2, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iq_type_3, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_0, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_1, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_2, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_3, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_4, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_5, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_6, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_7, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_8, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fu_code_9, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iw_issued, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:107:27]
input [2:0] io_arb_rebusys_0_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:107:27]
input [2:0] io_arb_rebusys_0_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:107:27]
input [2:0] io_arb_rebusys_0_bits_uop_dis_col_sel, // @[execution-unit.scala:107:27]
input [15:0] io_arb_rebusys_0_bits_uop_br_mask, // @[execution-unit.scala:107:27]
input [3:0] io_arb_rebusys_0_bits_uop_br_tag, // @[execution-unit.scala:107:27]
input [3:0] io_arb_rebusys_0_bits_uop_br_type, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_sfb, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_fence, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_fencei, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_sfence, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_amo, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_eret, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_rocc, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_mov, // @[execution-unit.scala:107:27]
input [4:0] io_arb_rebusys_0_bits_uop_ftq_idx, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_edge_inst, // @[execution-unit.scala:107:27]
input [5:0] io_arb_rebusys_0_bits_uop_pc_lob, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_taken, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_imm_rename, // @[execution-unit.scala:107:27]
input [2:0] io_arb_rebusys_0_bits_uop_imm_sel, // @[execution-unit.scala:107:27]
input [4:0] io_arb_rebusys_0_bits_uop_pimm, // @[execution-unit.scala:107:27]
input [19:0] io_arb_rebusys_0_bits_uop_imm_packed, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_op1_sel, // @[execution-unit.scala:107:27]
input [2:0] io_arb_rebusys_0_bits_uop_op2_sel, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_div, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:107:27]
input [6:0] io_arb_rebusys_0_bits_uop_rob_idx, // @[execution-unit.scala:107:27]
input [4:0] io_arb_rebusys_0_bits_uop_ldq_idx, // @[execution-unit.scala:107:27]
input [4:0] io_arb_rebusys_0_bits_uop_stq_idx, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_rxq_idx, // @[execution-unit.scala:107:27]
input [6:0] io_arb_rebusys_0_bits_uop_pdst, // @[execution-unit.scala:107:27]
input [6:0] io_arb_rebusys_0_bits_uop_prs1, // @[execution-unit.scala:107:27]
input [6:0] io_arb_rebusys_0_bits_uop_prs2, // @[execution-unit.scala:107:27]
input [6:0] io_arb_rebusys_0_bits_uop_prs3, // @[execution-unit.scala:107:27]
input [4:0] io_arb_rebusys_0_bits_uop_ppred, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_prs1_busy, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_prs2_busy, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_prs3_busy, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_ppred_busy, // @[execution-unit.scala:107:27]
input [6:0] io_arb_rebusys_0_bits_uop_stale_pdst, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_exception, // @[execution-unit.scala:107:27]
input [63:0] io_arb_rebusys_0_bits_uop_exc_cause, // @[execution-unit.scala:107:27]
input [4:0] io_arb_rebusys_0_bits_uop_mem_cmd, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_mem_size, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_mem_signed, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_uses_ldq, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_uses_stq, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_is_unique, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_flush_on_commit, // @[execution-unit.scala:107:27]
input [2:0] io_arb_rebusys_0_bits_uop_csr_cmd, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_ldst_is_rs1, // @[execution-unit.scala:107:27]
input [5:0] io_arb_rebusys_0_bits_uop_ldst, // @[execution-unit.scala:107:27]
input [5:0] io_arb_rebusys_0_bits_uop_lrs1, // @[execution-unit.scala:107:27]
input [5:0] io_arb_rebusys_0_bits_uop_lrs2, // @[execution-unit.scala:107:27]
input [5:0] io_arb_rebusys_0_bits_uop_lrs3, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_dst_rtype, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_lrs1_rtype, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_lrs2_rtype, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_frs3_en, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fcn_dw, // @[execution-unit.scala:107:27]
input [4:0] io_arb_rebusys_0_bits_uop_fcn_op, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_fp_val, // @[execution-unit.scala:107:27]
input [2:0] io_arb_rebusys_0_bits_uop_fp_rm, // @[execution-unit.scala:107:27]
input [1:0] io_arb_rebusys_0_bits_uop_fp_typ, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_xcpt_pf_if, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_xcpt_ae_if, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_xcpt_ma_if, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_bp_debug_if, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_uop_bp_xcpt_if, // @[execution-unit.scala:107:27]
input [2:0] io_arb_rebusys_0_bits_uop_debug_fsrc, // @[execution-unit.scala:107:27]
input [2:0] io_arb_rebusys_0_bits_uop_debug_tsrc, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_bypassable, // @[execution-unit.scala:107:27]
input [2:0] io_arb_rebusys_0_bits_speculative_mask, // @[execution-unit.scala:107:27]
input io_arb_rebusys_0_bits_rebusy, // @[execution-unit.scala:107:27]
input [63:0] io_rrd_irf_resps_0, // @[execution-unit.scala:108:31]
input io_rrd_irf_bypasses_0_valid, // @[execution-unit.scala:109:31]
input [31:0] io_rrd_irf_bypasses_0_bits_uop_inst, // @[execution-unit.scala:109:31]
input [31:0] io_rrd_irf_bypasses_0_bits_uop_debug_inst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_rvc, // @[execution-unit.scala:109:31]
input [39:0] io_rrd_irf_bypasses_0_bits_uop_debug_pc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iq_type_0, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iq_type_1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iq_type_2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iq_type_3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_0, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_4, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_5, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_6, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_7, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_8, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fu_code_9, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iw_issued, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_0_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_0_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_0_bits_uop_dis_col_sel, // @[execution-unit.scala:109:31]
input [15:0] io_rrd_irf_bypasses_0_bits_uop_br_mask, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_0_bits_uop_br_tag, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_0_bits_uop_br_type, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_sfb, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_fence, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_fencei, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_sfence, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_amo, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_eret, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_rocc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_mov, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_0_bits_uop_ftq_idx, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_edge_inst, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_0_bits_uop_pc_lob, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_taken, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_imm_rename, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_0_bits_uop_imm_sel, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_0_bits_uop_pimm, // @[execution-unit.scala:109:31]
input [19:0] io_rrd_irf_bypasses_0_bits_uop_imm_packed, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_op1_sel, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_0_bits_uop_op2_sel, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_div, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_0_bits_uop_rob_idx, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_0_bits_uop_ldq_idx, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_0_bits_uop_stq_idx, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_rxq_idx, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_0_bits_uop_pdst, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_0_bits_uop_prs1, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_0_bits_uop_prs2, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_0_bits_uop_prs3, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_0_bits_uop_ppred, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_prs1_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_prs2_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_prs3_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_ppred_busy, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_0_bits_uop_stale_pdst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_exception, // @[execution-unit.scala:109:31]
input [63:0] io_rrd_irf_bypasses_0_bits_uop_exc_cause, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_0_bits_uop_mem_cmd, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_mem_size, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_mem_signed, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_uses_ldq, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_uses_stq, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_is_unique, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_flush_on_commit, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_0_bits_uop_csr_cmd, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_ldst_is_rs1, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_0_bits_uop_ldst, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_0_bits_uop_lrs1, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_0_bits_uop_lrs2, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_0_bits_uop_lrs3, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_dst_rtype, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_lrs1_rtype, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_lrs2_rtype, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_frs3_en, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fcn_dw, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_0_bits_uop_fcn_op, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_fp_val, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_0_bits_uop_fp_rm, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_0_bits_uop_fp_typ, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_xcpt_pf_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_xcpt_ae_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_xcpt_ma_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_bp_debug_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_uop_bp_xcpt_if, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_0_bits_uop_debug_fsrc, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_0_bits_uop_debug_tsrc, // @[execution-unit.scala:109:31]
input [63:0] io_rrd_irf_bypasses_0_bits_data, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_predicated, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_0_bits_fflags_valid, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_0_bits_fflags_bits, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_valid, // @[execution-unit.scala:109:31]
input [31:0] io_rrd_irf_bypasses_1_bits_uop_inst, // @[execution-unit.scala:109:31]
input [31:0] io_rrd_irf_bypasses_1_bits_uop_debug_inst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_rvc, // @[execution-unit.scala:109:31]
input [39:0] io_rrd_irf_bypasses_1_bits_uop_debug_pc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iq_type_0, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iq_type_1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iq_type_2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iq_type_3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_0, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_4, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_5, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_6, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_7, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_8, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fu_code_9, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iw_issued, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_1_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_1_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_1_bits_uop_dis_col_sel, // @[execution-unit.scala:109:31]
input [15:0] io_rrd_irf_bypasses_1_bits_uop_br_mask, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_1_bits_uop_br_tag, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_1_bits_uop_br_type, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_sfb, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_fence, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_fencei, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_sfence, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_amo, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_eret, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_rocc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_mov, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_1_bits_uop_ftq_idx, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_edge_inst, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_1_bits_uop_pc_lob, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_taken, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_imm_rename, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_1_bits_uop_imm_sel, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_1_bits_uop_pimm, // @[execution-unit.scala:109:31]
input [19:0] io_rrd_irf_bypasses_1_bits_uop_imm_packed, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_op1_sel, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_1_bits_uop_op2_sel, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_div, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_1_bits_uop_rob_idx, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_1_bits_uop_ldq_idx, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_1_bits_uop_stq_idx, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_rxq_idx, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_1_bits_uop_pdst, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_1_bits_uop_prs1, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_1_bits_uop_prs2, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_1_bits_uop_prs3, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_1_bits_uop_ppred, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_prs1_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_prs2_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_prs3_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_ppred_busy, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_1_bits_uop_stale_pdst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_exception, // @[execution-unit.scala:109:31]
input [63:0] io_rrd_irf_bypasses_1_bits_uop_exc_cause, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_1_bits_uop_mem_cmd, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_mem_size, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_mem_signed, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_uses_ldq, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_uses_stq, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_is_unique, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_flush_on_commit, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_1_bits_uop_csr_cmd, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_ldst_is_rs1, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_1_bits_uop_ldst, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_1_bits_uop_lrs1, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_1_bits_uop_lrs2, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_1_bits_uop_lrs3, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_dst_rtype, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_lrs1_rtype, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_lrs2_rtype, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_frs3_en, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fcn_dw, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_1_bits_uop_fcn_op, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_fp_val, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_1_bits_uop_fp_rm, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_1_bits_uop_fp_typ, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_xcpt_pf_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_xcpt_ae_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_xcpt_ma_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_bp_debug_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_uop_bp_xcpt_if, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_1_bits_uop_debug_fsrc, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_1_bits_uop_debug_tsrc, // @[execution-unit.scala:109:31]
input [63:0] io_rrd_irf_bypasses_1_bits_data, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_1_bits_predicated, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_valid, // @[execution-unit.scala:109:31]
input [31:0] io_rrd_irf_bypasses_2_bits_uop_inst, // @[execution-unit.scala:109:31]
input [31:0] io_rrd_irf_bypasses_2_bits_uop_debug_inst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_rvc, // @[execution-unit.scala:109:31]
input [39:0] io_rrd_irf_bypasses_2_bits_uop_debug_pc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iq_type_0, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iq_type_1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iq_type_2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iq_type_3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_0, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_4, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_5, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_6, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_7, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_8, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fu_code_9, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iw_issued, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_2_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_2_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_2_bits_uop_dis_col_sel, // @[execution-unit.scala:109:31]
input [15:0] io_rrd_irf_bypasses_2_bits_uop_br_mask, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_2_bits_uop_br_tag, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_2_bits_uop_br_type, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_sfb, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_fence, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_fencei, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_sfence, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_amo, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_eret, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_rocc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_mov, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_2_bits_uop_ftq_idx, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_edge_inst, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_2_bits_uop_pc_lob, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_taken, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_imm_rename, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_2_bits_uop_imm_sel, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_2_bits_uop_pimm, // @[execution-unit.scala:109:31]
input [19:0] io_rrd_irf_bypasses_2_bits_uop_imm_packed, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_op1_sel, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_2_bits_uop_op2_sel, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_div, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_2_bits_uop_rob_idx, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_2_bits_uop_ldq_idx, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_2_bits_uop_stq_idx, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_rxq_idx, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_2_bits_uop_pdst, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_2_bits_uop_prs1, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_2_bits_uop_prs2, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_2_bits_uop_prs3, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_2_bits_uop_ppred, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_prs1_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_prs2_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_prs3_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_ppred_busy, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_2_bits_uop_stale_pdst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_exception, // @[execution-unit.scala:109:31]
input [63:0] io_rrd_irf_bypasses_2_bits_uop_exc_cause, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_2_bits_uop_mem_cmd, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_mem_size, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_mem_signed, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_uses_ldq, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_uses_stq, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_is_unique, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_flush_on_commit, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_2_bits_uop_csr_cmd, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_ldst_is_rs1, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_2_bits_uop_ldst, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_2_bits_uop_lrs1, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_2_bits_uop_lrs2, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_2_bits_uop_lrs3, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_dst_rtype, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_lrs1_rtype, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_lrs2_rtype, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_frs3_en, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fcn_dw, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_2_bits_uop_fcn_op, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_fp_val, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_2_bits_uop_fp_rm, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_2_bits_uop_fp_typ, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_xcpt_pf_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_xcpt_ae_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_xcpt_ma_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_bp_debug_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_uop_bp_xcpt_if, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_2_bits_uop_debug_fsrc, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_2_bits_uop_debug_tsrc, // @[execution-unit.scala:109:31]
input [63:0] io_rrd_irf_bypasses_2_bits_data, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_2_bits_predicated, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_valid, // @[execution-unit.scala:109:31]
input [31:0] io_rrd_irf_bypasses_3_bits_uop_inst, // @[execution-unit.scala:109:31]
input [31:0] io_rrd_irf_bypasses_3_bits_uop_debug_inst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_is_rvc, // @[execution-unit.scala:109:31]
input [39:0] io_rrd_irf_bypasses_3_bits_uop_debug_pc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_iq_type_0, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_iq_type_1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_iq_type_2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_iq_type_3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fu_code_0, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fu_code_1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fu_code_2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fu_code_3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fu_code_4, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fu_code_5, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fu_code_6, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fu_code_7, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fu_code_8, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fu_code_9, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_iw_issued, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_3_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_3_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_3_bits_uop_dis_col_sel, // @[execution-unit.scala:109:31]
input [15:0] io_rrd_irf_bypasses_3_bits_uop_br_mask, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_3_bits_uop_br_tag, // @[execution-unit.scala:109:31]
input [3:0] io_rrd_irf_bypasses_3_bits_uop_br_type, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_is_sfb, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_is_fence, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_is_fencei, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_is_sfence, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_is_amo, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_is_eret, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_is_rocc, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_is_mov, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_3_bits_uop_ftq_idx, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_edge_inst, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_3_bits_uop_pc_lob, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_taken, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_imm_rename, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_3_bits_uop_imm_sel, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_3_bits_uop_pimm, // @[execution-unit.scala:109:31]
input [19:0] io_rrd_irf_bypasses_3_bits_uop_imm_packed, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_3_bits_uop_op1_sel, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_3_bits_uop_op2_sel, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_div, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_3_bits_uop_rob_idx, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_3_bits_uop_ldq_idx, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_3_bits_uop_stq_idx, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_3_bits_uop_rxq_idx, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_3_bits_uop_pdst, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_3_bits_uop_prs1, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_3_bits_uop_prs2, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_3_bits_uop_prs3, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_3_bits_uop_ppred, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_prs1_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_prs2_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_prs3_busy, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_ppred_busy, // @[execution-unit.scala:109:31]
input [6:0] io_rrd_irf_bypasses_3_bits_uop_stale_pdst, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_exception, // @[execution-unit.scala:109:31]
input [63:0] io_rrd_irf_bypasses_3_bits_uop_exc_cause, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_3_bits_uop_mem_cmd, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_3_bits_uop_mem_size, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_mem_signed, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_uses_ldq, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_uses_stq, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_is_unique, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_flush_on_commit, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_3_bits_uop_csr_cmd, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_ldst_is_rs1, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_3_bits_uop_ldst, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_3_bits_uop_lrs1, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_3_bits_uop_lrs2, // @[execution-unit.scala:109:31]
input [5:0] io_rrd_irf_bypasses_3_bits_uop_lrs3, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_3_bits_uop_dst_rtype, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_3_bits_uop_lrs1_rtype, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_3_bits_uop_lrs2_rtype, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_frs3_en, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fcn_dw, // @[execution-unit.scala:109:31]
input [4:0] io_rrd_irf_bypasses_3_bits_uop_fcn_op, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_fp_val, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_3_bits_uop_fp_rm, // @[execution-unit.scala:109:31]
input [1:0] io_rrd_irf_bypasses_3_bits_uop_fp_typ, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_xcpt_pf_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_xcpt_ae_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_xcpt_ma_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_bp_debug_if, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_uop_bp_xcpt_if, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_3_bits_uop_debug_fsrc, // @[execution-unit.scala:109:31]
input [2:0] io_rrd_irf_bypasses_3_bits_uop_debug_tsrc, // @[execution-unit.scala:109:31]
input [63:0] io_rrd_irf_bypasses_3_bits_data, // @[execution-unit.scala:109:31]
input io_rrd_irf_bypasses_3_bits_predicated, // @[execution-unit.scala:109:31]
output io_arb_immrf_req_valid, // @[execution-unit.scala:151:31]
output [4:0] io_arb_immrf_req_bits, // @[execution-unit.scala:151:31]
input [63:0] io_rrd_immrf_resp, // @[execution-unit.scala:153:31]
output io_rrd_immrf_wakeup_valid, // @[execution-unit.scala:154:31]
output [31:0] io_rrd_immrf_wakeup_bits_uop_inst, // @[execution-unit.scala:154:31]
output [31:0] io_rrd_immrf_wakeup_bits_uop_debug_inst, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_rvc, // @[execution-unit.scala:154:31]
output [39:0] io_rrd_immrf_wakeup_bits_uop_debug_pc, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iq_type_0, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iq_type_1, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iq_type_2, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iq_type_3, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_0, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_1, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_2, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_3, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_4, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_5, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_6, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_7, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_8, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fu_code_9, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iw_issued, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:154:31]
output [2:0] io_rrd_immrf_wakeup_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:154:31]
output [2:0] io_rrd_immrf_wakeup_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:154:31]
output [2:0] io_rrd_immrf_wakeup_bits_uop_dis_col_sel, // @[execution-unit.scala:154:31]
output [15:0] io_rrd_immrf_wakeup_bits_uop_br_mask, // @[execution-unit.scala:154:31]
output [3:0] io_rrd_immrf_wakeup_bits_uop_br_tag, // @[execution-unit.scala:154:31]
output [3:0] io_rrd_immrf_wakeup_bits_uop_br_type, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_sfb, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_fence, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_fencei, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_sfence, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_amo, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_eret, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_rocc, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_mov, // @[execution-unit.scala:154:31]
output [4:0] io_rrd_immrf_wakeup_bits_uop_ftq_idx, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_edge_inst, // @[execution-unit.scala:154:31]
output [5:0] io_rrd_immrf_wakeup_bits_uop_pc_lob, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_taken, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_imm_rename, // @[execution-unit.scala:154:31]
output [2:0] io_rrd_immrf_wakeup_bits_uop_imm_sel, // @[execution-unit.scala:154:31]
output [4:0] io_rrd_immrf_wakeup_bits_uop_pimm, // @[execution-unit.scala:154:31]
output [19:0] io_rrd_immrf_wakeup_bits_uop_imm_packed, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_op1_sel, // @[execution-unit.scala:154:31]
output [2:0] io_rrd_immrf_wakeup_bits_uop_op2_sel, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_div, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:154:31]
output [6:0] io_rrd_immrf_wakeup_bits_uop_rob_idx, // @[execution-unit.scala:154:31]
output [4:0] io_rrd_immrf_wakeup_bits_uop_ldq_idx, // @[execution-unit.scala:154:31]
output [4:0] io_rrd_immrf_wakeup_bits_uop_stq_idx, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_rxq_idx, // @[execution-unit.scala:154:31]
output [6:0] io_rrd_immrf_wakeup_bits_uop_pdst, // @[execution-unit.scala:154:31]
output [6:0] io_rrd_immrf_wakeup_bits_uop_prs1, // @[execution-unit.scala:154:31]
output [6:0] io_rrd_immrf_wakeup_bits_uop_prs2, // @[execution-unit.scala:154:31]
output [6:0] io_rrd_immrf_wakeup_bits_uop_prs3, // @[execution-unit.scala:154:31]
output [4:0] io_rrd_immrf_wakeup_bits_uop_ppred, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_prs1_busy, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_prs2_busy, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_prs3_busy, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_ppred_busy, // @[execution-unit.scala:154:31]
output [6:0] io_rrd_immrf_wakeup_bits_uop_stale_pdst, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_exception, // @[execution-unit.scala:154:31]
output [63:0] io_rrd_immrf_wakeup_bits_uop_exc_cause, // @[execution-unit.scala:154:31]
output [4:0] io_rrd_immrf_wakeup_bits_uop_mem_cmd, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_mem_size, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_mem_signed, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_uses_ldq, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_uses_stq, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_is_unique, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_flush_on_commit, // @[execution-unit.scala:154:31]
output [2:0] io_rrd_immrf_wakeup_bits_uop_csr_cmd, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_ldst_is_rs1, // @[execution-unit.scala:154:31]
output [5:0] io_rrd_immrf_wakeup_bits_uop_ldst, // @[execution-unit.scala:154:31]
output [5:0] io_rrd_immrf_wakeup_bits_uop_lrs1, // @[execution-unit.scala:154:31]
output [5:0] io_rrd_immrf_wakeup_bits_uop_lrs2, // @[execution-unit.scala:154:31]
output [5:0] io_rrd_immrf_wakeup_bits_uop_lrs3, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_dst_rtype, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_lrs1_rtype, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_lrs2_rtype, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_frs3_en, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fcn_dw, // @[execution-unit.scala:154:31]
output [4:0] io_rrd_immrf_wakeup_bits_uop_fcn_op, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_fp_val, // @[execution-unit.scala:154:31]
output [2:0] io_rrd_immrf_wakeup_bits_uop_fp_rm, // @[execution-unit.scala:154:31]
output [1:0] io_rrd_immrf_wakeup_bits_uop_fp_typ, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_xcpt_pf_if, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_xcpt_ae_if, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_xcpt_ma_if, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_bp_debug_if, // @[execution-unit.scala:154:31]
output io_rrd_immrf_wakeup_bits_uop_bp_xcpt_if, // @[execution-unit.scala:154:31]
output [2:0] io_rrd_immrf_wakeup_bits_uop_debug_fsrc, // @[execution-unit.scala:154:31]
output [2:0] io_rrd_immrf_wakeup_bits_uop_debug_tsrc, // @[execution-unit.scala:154:31]
output io_squash_iss, // @[execution-unit.scala:264:25]
output io_dgen_valid, // @[execution-unit.scala:317:18]
output [31:0] io_dgen_bits_uop_inst, // @[execution-unit.scala:317:18]
output [31:0] io_dgen_bits_uop_debug_inst, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_rvc, // @[execution-unit.scala:317:18]
output [39:0] io_dgen_bits_uop_debug_pc, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iq_type_0, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iq_type_1, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iq_type_2, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iq_type_3, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_0, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_1, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_2, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_3, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_4, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_5, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_6, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_7, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_8, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fu_code_9, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iw_issued, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iw_issued_partial_agen, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iw_issued_partial_dgen, // @[execution-unit.scala:317:18]
output [2:0] io_dgen_bits_uop_iw_p1_speculative_child, // @[execution-unit.scala:317:18]
output [2:0] io_dgen_bits_uop_iw_p2_speculative_child, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iw_p1_bypass_hint, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iw_p2_bypass_hint, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_iw_p3_bypass_hint, // @[execution-unit.scala:317:18]
output [2:0] io_dgen_bits_uop_dis_col_sel, // @[execution-unit.scala:317:18]
output [15:0] io_dgen_bits_uop_br_mask, // @[execution-unit.scala:317:18]
output [3:0] io_dgen_bits_uop_br_tag, // @[execution-unit.scala:317:18]
output [3:0] io_dgen_bits_uop_br_type, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_sfb, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_fence, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_fencei, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_sfence, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_amo, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_eret, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_rocc, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_mov, // @[execution-unit.scala:317:18]
output [4:0] io_dgen_bits_uop_ftq_idx, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_edge_inst, // @[execution-unit.scala:317:18]
output [5:0] io_dgen_bits_uop_pc_lob, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_taken, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_imm_rename, // @[execution-unit.scala:317:18]
output [2:0] io_dgen_bits_uop_imm_sel, // @[execution-unit.scala:317:18]
output [4:0] io_dgen_bits_uop_pimm, // @[execution-unit.scala:317:18]
output [19:0] io_dgen_bits_uop_imm_packed, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_op1_sel, // @[execution-unit.scala:317:18]
output [2:0] io_dgen_bits_uop_op2_sel, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_ldst, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_wen, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_ren1, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_ren2, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_ren3, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_swap12, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_swap23, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_fp_ctrl_typeTagIn, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_fp_ctrl_typeTagOut, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_fromint, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_toint, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_fastpipe, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_fma, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_div, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_sqrt, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_wflags, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_ctrl_vec, // @[execution-unit.scala:317:18]
output [6:0] io_dgen_bits_uop_rob_idx, // @[execution-unit.scala:317:18]
output [4:0] io_dgen_bits_uop_ldq_idx, // @[execution-unit.scala:317:18]
output [4:0] io_dgen_bits_uop_stq_idx, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_rxq_idx, // @[execution-unit.scala:317:18]
output [6:0] io_dgen_bits_uop_pdst, // @[execution-unit.scala:317:18]
output [6:0] io_dgen_bits_uop_prs1, // @[execution-unit.scala:317:18]
output [6:0] io_dgen_bits_uop_prs2, // @[execution-unit.scala:317:18]
output [6:0] io_dgen_bits_uop_prs3, // @[execution-unit.scala:317:18]
output [4:0] io_dgen_bits_uop_ppred, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_prs1_busy, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_prs2_busy, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_prs3_busy, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_ppred_busy, // @[execution-unit.scala:317:18]
output [6:0] io_dgen_bits_uop_stale_pdst, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_exception, // @[execution-unit.scala:317:18]
output [63:0] io_dgen_bits_uop_exc_cause, // @[execution-unit.scala:317:18]
output [4:0] io_dgen_bits_uop_mem_cmd, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_mem_size, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_mem_signed, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_uses_ldq, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_uses_stq, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_is_unique, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_flush_on_commit, // @[execution-unit.scala:317:18]
output [2:0] io_dgen_bits_uop_csr_cmd, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_ldst_is_rs1, // @[execution-unit.scala:317:18]
output [5:0] io_dgen_bits_uop_ldst, // @[execution-unit.scala:317:18]
output [5:0] io_dgen_bits_uop_lrs1, // @[execution-unit.scala:317:18]
output [5:0] io_dgen_bits_uop_lrs2, // @[execution-unit.scala:317:18]
output [5:0] io_dgen_bits_uop_lrs3, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_dst_rtype, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_lrs1_rtype, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_lrs2_rtype, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_frs3_en, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fcn_dw, // @[execution-unit.scala:317:18]
output [4:0] io_dgen_bits_uop_fcn_op, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_fp_val, // @[execution-unit.scala:317:18]
output [2:0] io_dgen_bits_uop_fp_rm, // @[execution-unit.scala:317:18]
output [1:0] io_dgen_bits_uop_fp_typ, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_xcpt_pf_if, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_xcpt_ae_if, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_xcpt_ma_if, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_bp_debug_if, // @[execution-unit.scala:317:18]
output io_dgen_bits_uop_bp_xcpt_if, // @[execution-unit.scala:317:18]
output [2:0] io_dgen_bits_uop_debug_fsrc, // @[execution-unit.scala:317:18]
output [2:0] io_dgen_bits_uop_debug_tsrc, // @[execution-unit.scala:317:18]
output [63:0] io_dgen_bits_data // @[execution-unit.scala:317:18]
);
reg [63:0] exe_rs1_data; // @[execution-unit.scala:133:25]
reg [2:0] exe_uop_bits_debug_tsrc; // @[execution-unit.scala:98:20]
reg [2:0] exe_uop_bits_debug_fsrc; // @[execution-unit.scala:98:20]
reg exe_uop_bits_bp_xcpt_if; // @[execution-unit.scala:98:20]
reg exe_uop_bits_bp_debug_if; // @[execution-unit.scala:98:20]
reg exe_uop_bits_xcpt_ma_if; // @[execution-unit.scala:98:20]
reg exe_uop_bits_xcpt_ae_if; // @[execution-unit.scala:98:20]
reg exe_uop_bits_xcpt_pf_if; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_fp_typ; // @[execution-unit.scala:98:20]
reg [2:0] exe_uop_bits_fp_rm; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_val; // @[execution-unit.scala:98:20]
reg [4:0] exe_uop_bits_fcn_op; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fcn_dw; // @[execution-unit.scala:98:20]
reg exe_uop_bits_frs3_en; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_lrs2_rtype; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_lrs1_rtype; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_dst_rtype; // @[execution-unit.scala:98:20]
reg [5:0] exe_uop_bits_lrs3; // @[execution-unit.scala:98:20]
reg [5:0] exe_uop_bits_lrs2; // @[execution-unit.scala:98:20]
reg [5:0] exe_uop_bits_lrs1; // @[execution-unit.scala:98:20]
reg [5:0] exe_uop_bits_ldst; // @[execution-unit.scala:98:20]
reg exe_uop_bits_ldst_is_rs1; // @[execution-unit.scala:98:20]
reg [2:0] exe_uop_bits_csr_cmd; // @[execution-unit.scala:98:20]
reg exe_uop_bits_flush_on_commit; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_unique; // @[execution-unit.scala:98:20]
reg exe_uop_bits_uses_stq; // @[execution-unit.scala:98:20]
reg exe_uop_bits_uses_ldq; // @[execution-unit.scala:98:20]
reg exe_uop_bits_mem_signed; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_mem_size; // @[execution-unit.scala:98:20]
reg [4:0] exe_uop_bits_mem_cmd; // @[execution-unit.scala:98:20]
reg [63:0] exe_uop_bits_exc_cause; // @[execution-unit.scala:98:20]
reg exe_uop_bits_exception; // @[execution-unit.scala:98:20]
reg [6:0] exe_uop_bits_stale_pdst; // @[execution-unit.scala:98:20]
reg exe_uop_bits_ppred_busy; // @[execution-unit.scala:98:20]
reg exe_uop_bits_prs3_busy; // @[execution-unit.scala:98:20]
reg exe_uop_bits_prs2_busy; // @[execution-unit.scala:98:20]
reg exe_uop_bits_prs1_busy; // @[execution-unit.scala:98:20]
reg [4:0] exe_uop_bits_ppred; // @[execution-unit.scala:98:20]
reg [6:0] exe_uop_bits_prs3; // @[execution-unit.scala:98:20]
reg [6:0] exe_uop_bits_prs2; // @[execution-unit.scala:98:20]
reg [6:0] exe_uop_bits_prs1; // @[execution-unit.scala:98:20]
reg [6:0] exe_uop_bits_pdst; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_rxq_idx; // @[execution-unit.scala:98:20]
reg [4:0] exe_uop_bits_stq_idx; // @[execution-unit.scala:98:20]
reg [4:0] exe_uop_bits_ldq_idx; // @[execution-unit.scala:98:20]
reg [6:0] exe_uop_bits_rob_idx; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_div; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:98:20]
reg [2:0] exe_uop_bits_op2_sel; // @[execution-unit.scala:98:20]
reg [1:0] exe_uop_bits_op1_sel; // @[execution-unit.scala:98:20]
reg [19:0] exe_uop_bits_imm_packed; // @[execution-unit.scala:98:20]
reg [4:0] exe_uop_bits_pimm; // @[execution-unit.scala:98:20]
reg [2:0] exe_uop_bits_imm_sel; // @[execution-unit.scala:98:20]
reg exe_uop_bits_imm_rename; // @[execution-unit.scala:98:20]
reg exe_uop_bits_taken; // @[execution-unit.scala:98:20]
reg [5:0] exe_uop_bits_pc_lob; // @[execution-unit.scala:98:20]
reg exe_uop_bits_edge_inst; // @[execution-unit.scala:98:20]
reg [4:0] exe_uop_bits_ftq_idx; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_mov; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_rocc; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_eret; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_amo; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_sfence; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_fencei; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_fence; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_sfb; // @[execution-unit.scala:98:20]
reg [3:0] exe_uop_bits_br_type; // @[execution-unit.scala:98:20]
reg [3:0] exe_uop_bits_br_tag; // @[execution-unit.scala:98:20]
reg [15:0] exe_uop_bits_br_mask; // @[execution-unit.scala:98:20]
reg [2:0] exe_uop_bits_dis_col_sel; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:98:20]
reg [2:0] exe_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:98:20]
reg [2:0] exe_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iw_issued; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_9; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_8; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_7; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_6; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_5; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_4; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_3; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_2; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_1; // @[execution-unit.scala:98:20]
reg exe_uop_bits_fu_code_0; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iq_type_3; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iq_type_2; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iq_type_1; // @[execution-unit.scala:98:20]
reg exe_uop_bits_iq_type_0; // @[execution-unit.scala:98:20]
reg [39:0] exe_uop_bits_debug_pc; // @[execution-unit.scala:98:20]
reg exe_uop_bits_is_rvc; // @[execution-unit.scala:98:20]
reg [31:0] exe_uop_bits_debug_inst; // @[execution-unit.scala:98:20]
reg [31:0] exe_uop_bits_inst; // @[execution-unit.scala:98:20]
reg [2:0] rrd_uop_bits_debug_tsrc; // @[execution-unit.scala:95:20]
reg [2:0] rrd_uop_bits_debug_fsrc; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_bp_xcpt_if; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_bp_debug_if; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_xcpt_ma_if; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_xcpt_ae_if; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_xcpt_pf_if; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_fp_typ; // @[execution-unit.scala:95:20]
reg [2:0] rrd_uop_bits_fp_rm; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_val; // @[execution-unit.scala:95:20]
reg [4:0] rrd_uop_bits_fcn_op; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fcn_dw; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_frs3_en; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_lrs2_rtype; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_lrs1_rtype; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_dst_rtype; // @[execution-unit.scala:95:20]
reg [5:0] rrd_uop_bits_lrs3; // @[execution-unit.scala:95:20]
reg [5:0] rrd_uop_bits_lrs2; // @[execution-unit.scala:95:20]
reg [5:0] rrd_uop_bits_lrs1; // @[execution-unit.scala:95:20]
reg [5:0] rrd_uop_bits_ldst; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_ldst_is_rs1; // @[execution-unit.scala:95:20]
reg [2:0] rrd_uop_bits_csr_cmd; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_flush_on_commit; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_unique; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_uses_stq; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_uses_ldq; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_mem_signed; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_mem_size; // @[execution-unit.scala:95:20]
reg [4:0] rrd_uop_bits_mem_cmd; // @[execution-unit.scala:95:20]
reg [63:0] rrd_uop_bits_exc_cause; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_exception; // @[execution-unit.scala:95:20]
reg [6:0] rrd_uop_bits_stale_pdst; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_ppred_busy; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_prs3_busy; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_prs2_busy; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_prs1_busy; // @[execution-unit.scala:95:20]
reg [4:0] rrd_uop_bits_ppred; // @[execution-unit.scala:95:20]
reg [6:0] rrd_uop_bits_prs3; // @[execution-unit.scala:95:20]
reg [6:0] rrd_uop_bits_prs2; // @[execution-unit.scala:95:20]
reg [6:0] rrd_uop_bits_prs1; // @[execution-unit.scala:95:20]
reg [6:0] rrd_uop_bits_pdst; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_rxq_idx; // @[execution-unit.scala:95:20]
reg [4:0] rrd_uop_bits_stq_idx; // @[execution-unit.scala:95:20]
reg [4:0] rrd_uop_bits_ldq_idx; // @[execution-unit.scala:95:20]
reg [6:0] rrd_uop_bits_rob_idx; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_div; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:95:20]
reg [2:0] rrd_uop_bits_op2_sel; // @[execution-unit.scala:95:20]
reg [1:0] rrd_uop_bits_op1_sel; // @[execution-unit.scala:95:20]
reg [19:0] rrd_uop_bits_imm_packed; // @[execution-unit.scala:95:20]
reg [4:0] rrd_uop_bits_pimm; // @[execution-unit.scala:95:20]
reg [2:0] rrd_uop_bits_imm_sel; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_imm_rename; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_taken; // @[execution-unit.scala:95:20]
reg [5:0] rrd_uop_bits_pc_lob; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_edge_inst; // @[execution-unit.scala:95:20]
reg [4:0] rrd_uop_bits_ftq_idx; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_mov; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_rocc; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_eret; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_amo; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_sfence; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_fencei; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_fence; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_sfb; // @[execution-unit.scala:95:20]
reg [3:0] rrd_uop_bits_br_type; // @[execution-unit.scala:95:20]
reg [3:0] rrd_uop_bits_br_tag; // @[execution-unit.scala:95:20]
reg [15:0] rrd_uop_bits_br_mask; // @[execution-unit.scala:95:20]
reg [2:0] rrd_uop_bits_dis_col_sel; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:95:20]
reg [2:0] rrd_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:95:20]
reg [2:0] rrd_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iw_issued; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_9; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_8; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_7; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_6; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_5; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_4; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_3; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_2; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_1; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_fu_code_0; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iq_type_3; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iq_type_2; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iq_type_1; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_iq_type_0; // @[execution-unit.scala:95:20]
reg [39:0] rrd_uop_bits_debug_pc; // @[execution-unit.scala:95:20]
reg rrd_uop_bits_is_rvc; // @[execution-unit.scala:95:20]
reg [31:0] rrd_uop_bits_debug_inst; // @[execution-unit.scala:95:20]
reg [31:0] rrd_uop_bits_inst; // @[execution-unit.scala:95:20]
wire io_arb_irf_reqs_0_ready_0 = io_arb_irf_reqs_0_ready; // @[execution-unit.scala:255:7]
wire [31:0] arb_uop_bits_out_inst = io_iss_uop_bits_inst; // @[util.scala:104:23]
wire [31:0] arb_uop_bits_out_debug_inst = io_iss_uop_bits_debug_inst; // @[util.scala:104:23]
wire arb_uop_bits_out_is_rvc = io_iss_uop_bits_is_rvc; // @[util.scala:104:23]
wire [39:0] arb_uop_bits_out_debug_pc = io_iss_uop_bits_debug_pc; // @[util.scala:104:23]
wire arb_uop_bits_out_iq_type_0 = io_iss_uop_bits_iq_type_0; // @[util.scala:104:23]
wire arb_uop_bits_out_iq_type_1 = io_iss_uop_bits_iq_type_1; // @[util.scala:104:23]
wire arb_uop_bits_out_iq_type_2 = io_iss_uop_bits_iq_type_2; // @[util.scala:104:23]
wire arb_uop_bits_out_iq_type_3 = io_iss_uop_bits_iq_type_3; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_0 = io_iss_uop_bits_fu_code_0; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_1 = io_iss_uop_bits_fu_code_1; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_2 = io_iss_uop_bits_fu_code_2; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_3 = io_iss_uop_bits_fu_code_3; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_4 = io_iss_uop_bits_fu_code_4; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_5 = io_iss_uop_bits_fu_code_5; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_6 = io_iss_uop_bits_fu_code_6; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_7 = io_iss_uop_bits_fu_code_7; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_8 = io_iss_uop_bits_fu_code_8; // @[util.scala:104:23]
wire arb_uop_bits_out_fu_code_9 = io_iss_uop_bits_fu_code_9; // @[util.scala:104:23]
wire arb_uop_bits_out_iw_issued = io_iss_uop_bits_iw_issued; // @[util.scala:104:23]
wire arb_uop_bits_out_iw_issued_partial_agen = io_iss_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23]
wire arb_uop_bits_out_iw_issued_partial_dgen = io_iss_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_iw_p1_speculative_child = io_iss_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_iw_p2_speculative_child = io_iss_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23]
wire arb_uop_bits_out_iw_p1_bypass_hint = io_iss_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23]
wire arb_uop_bits_out_iw_p2_bypass_hint = io_iss_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23]
wire arb_uop_bits_out_iw_p3_bypass_hint = io_iss_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_dis_col_sel = io_iss_uop_bits_dis_col_sel; // @[util.scala:104:23]
wire [3:0] arb_uop_bits_out_br_tag = io_iss_uop_bits_br_tag; // @[util.scala:104:23]
wire [3:0] arb_uop_bits_out_br_type = io_iss_uop_bits_br_type; // @[util.scala:104:23]
wire arb_uop_bits_out_is_sfb = io_iss_uop_bits_is_sfb; // @[util.scala:104:23]
wire arb_uop_bits_out_is_fence = io_iss_uop_bits_is_fence; // @[util.scala:104:23]
wire arb_uop_bits_out_is_fencei = io_iss_uop_bits_is_fencei; // @[util.scala:104:23]
wire arb_uop_bits_out_is_sfence = io_iss_uop_bits_is_sfence; // @[util.scala:104:23]
wire arb_uop_bits_out_is_amo = io_iss_uop_bits_is_amo; // @[util.scala:104:23]
wire arb_uop_bits_out_is_eret = io_iss_uop_bits_is_eret; // @[util.scala:104:23]
wire arb_uop_bits_out_is_sys_pc2epc = io_iss_uop_bits_is_sys_pc2epc; // @[util.scala:104:23]
wire arb_uop_bits_out_is_rocc = io_iss_uop_bits_is_rocc; // @[util.scala:104:23]
wire arb_uop_bits_out_is_mov = io_iss_uop_bits_is_mov; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_ftq_idx = io_iss_uop_bits_ftq_idx; // @[util.scala:104:23]
wire arb_uop_bits_out_edge_inst = io_iss_uop_bits_edge_inst; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_pc_lob = io_iss_uop_bits_pc_lob; // @[util.scala:104:23]
wire arb_uop_bits_out_taken = io_iss_uop_bits_taken; // @[util.scala:104:23]
wire arb_uop_bits_out_imm_rename = io_iss_uop_bits_imm_rename; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_imm_sel = io_iss_uop_bits_imm_sel; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_pimm = io_iss_uop_bits_pimm; // @[util.scala:104:23]
wire [19:0] arb_uop_bits_out_imm_packed = io_iss_uop_bits_imm_packed; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_op1_sel = io_iss_uop_bits_op1_sel; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_op2_sel = io_iss_uop_bits_op2_sel; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_ldst = io_iss_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_wen = io_iss_uop_bits_fp_ctrl_wen; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_ren1 = io_iss_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_ren2 = io_iss_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_ren3 = io_iss_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_swap12 = io_iss_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_swap23 = io_iss_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_fp_ctrl_typeTagIn = io_iss_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_fp_ctrl_typeTagOut = io_iss_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_fromint = io_iss_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_toint = io_iss_uop_bits_fp_ctrl_toint; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_fastpipe = io_iss_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_fma = io_iss_uop_bits_fp_ctrl_fma; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_div = io_iss_uop_bits_fp_ctrl_div; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_sqrt = io_iss_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_wflags = io_iss_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_ctrl_vec = io_iss_uop_bits_fp_ctrl_vec; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_rob_idx = io_iss_uop_bits_rob_idx; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_ldq_idx = io_iss_uop_bits_ldq_idx; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_stq_idx = io_iss_uop_bits_stq_idx; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_rxq_idx = io_iss_uop_bits_rxq_idx; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_pdst = io_iss_uop_bits_pdst; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_prs1 = io_iss_uop_bits_prs1; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_prs2 = io_iss_uop_bits_prs2; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_prs3 = io_iss_uop_bits_prs3; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_ppred = io_iss_uop_bits_ppred; // @[util.scala:104:23]
wire arb_uop_bits_out_prs1_busy = io_iss_uop_bits_prs1_busy; // @[util.scala:104:23]
wire arb_uop_bits_out_prs2_busy = io_iss_uop_bits_prs2_busy; // @[util.scala:104:23]
wire arb_uop_bits_out_prs3_busy = io_iss_uop_bits_prs3_busy; // @[util.scala:104:23]
wire arb_uop_bits_out_ppred_busy = io_iss_uop_bits_ppred_busy; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_stale_pdst = io_iss_uop_bits_stale_pdst; // @[util.scala:104:23]
wire arb_uop_bits_out_exception = io_iss_uop_bits_exception; // @[util.scala:104:23]
wire [63:0] arb_uop_bits_out_exc_cause = io_iss_uop_bits_exc_cause; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_mem_cmd = io_iss_uop_bits_mem_cmd; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_mem_size = io_iss_uop_bits_mem_size; // @[util.scala:104:23]
wire arb_uop_bits_out_mem_signed = io_iss_uop_bits_mem_signed; // @[util.scala:104:23]
wire arb_uop_bits_out_uses_ldq = io_iss_uop_bits_uses_ldq; // @[util.scala:104:23]
wire arb_uop_bits_out_uses_stq = io_iss_uop_bits_uses_stq; // @[util.scala:104:23]
wire arb_uop_bits_out_is_unique = io_iss_uop_bits_is_unique; // @[util.scala:104:23]
wire arb_uop_bits_out_flush_on_commit = io_iss_uop_bits_flush_on_commit; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_csr_cmd = io_iss_uop_bits_csr_cmd; // @[util.scala:104:23]
wire arb_uop_bits_out_ldst_is_rs1 = io_iss_uop_bits_ldst_is_rs1; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_ldst = io_iss_uop_bits_ldst; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_lrs1 = io_iss_uop_bits_lrs1; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_lrs2 = io_iss_uop_bits_lrs2; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_lrs3 = io_iss_uop_bits_lrs3; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_dst_rtype = io_iss_uop_bits_dst_rtype; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_lrs1_rtype = io_iss_uop_bits_lrs1_rtype; // @[util.scala:104:23]
wire arb_uop_bits_out_frs3_en = io_iss_uop_bits_frs3_en; // @[util.scala:104:23]
wire arb_uop_bits_out_fcn_dw = io_iss_uop_bits_fcn_dw; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_fcn_op = io_iss_uop_bits_fcn_op; // @[util.scala:104:23]
wire arb_uop_bits_out_fp_val = io_iss_uop_bits_fp_val; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_fp_rm = io_iss_uop_bits_fp_rm; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_fp_typ = io_iss_uop_bits_fp_typ; // @[util.scala:104:23]
wire arb_uop_bits_out_xcpt_pf_if = io_iss_uop_bits_xcpt_pf_if; // @[util.scala:104:23]
wire arb_uop_bits_out_xcpt_ae_if = io_iss_uop_bits_xcpt_ae_if; // @[util.scala:104:23]
wire arb_uop_bits_out_xcpt_ma_if = io_iss_uop_bits_xcpt_ma_if; // @[util.scala:104:23]
wire arb_uop_bits_out_bp_debug_if = io_iss_uop_bits_bp_debug_if; // @[util.scala:104:23]
wire arb_uop_bits_out_bp_xcpt_if = io_iss_uop_bits_bp_xcpt_if; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_debug_fsrc = io_iss_uop_bits_debug_fsrc; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_debug_tsrc = io_iss_uop_bits_debug_tsrc; // @[util.scala:104:23]
wire _io_agen_T_2 = reset; // @[execution-unit.scala:311:11]
wire arb_rebusied_prs2 = 1'h0; // @[execution-unit.scala:129:93]
wire _r_WIRE_0 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_1 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_2 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_3 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_4 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_5 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_6 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_7 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_8 = 1'h0; // @[execution-unit.scala:74:29]
wire _r_WIRE_9 = 1'h0; // @[execution-unit.scala:74:29]
wire r_0 = 1'h0; // @[execution-unit.scala:74:21]
wire r_1 = 1'h0; // @[execution-unit.scala:74:21]
wire r_3 = 1'h0; // @[execution-unit.scala:74:21]
wire r_4 = 1'h0; // @[execution-unit.scala:74:21]
wire r_5 = 1'h0; // @[execution-unit.scala:74:21]
wire r_6 = 1'h0; // @[execution-unit.scala:74:21]
wire r_7 = 1'h0; // @[execution-unit.scala:74:21]
wire r_8 = 1'h0; // @[execution-unit.scala:74:21]
wire r_9 = 1'h0; // @[execution-unit.scala:74:21]
wire [1:0] arb_uop_bits_out_lrs2_rtype = 2'h2; // @[util.scala:104:23]
wire io_arb_immrf_req_ready = 1'h1; // @[execution-unit.scala:255:7]
wire r_2 = 1'h1; // @[execution-unit.scala:74:21]
wire _io_arb_irf_reqs_0_valid_T_3; // @[execution-unit.scala:121:83]
wire _io_arb_immrf_req_valid_T_4; // @[execution-unit.scala:157:44]
wire io_arb_irf_reqs_0_valid_0; // @[execution-unit.scala:255:7]
wire [6:0] io_arb_irf_reqs_0_bits_0; // @[execution-unit.scala:255:7]
wire io_arb_immrf_req_valid_0; // @[execution-unit.scala:255:7]
wire [4:0] io_arb_immrf_req_bits_0; // @[execution-unit.scala:255:7]
wire _io_rrd_immrf_wakeup_valid_T_4; // @[execution-unit.scala:162:47]
wire _io_squash_iss_T_1; // @[execution-unit.scala:265:46]
wire _io_dgen_dgen_valid_T; // @[execution-unit.scala:318:37]
reg arb_uop_valid; // @[execution-unit.scala:92:20]
reg [31:0] arb_uop_bits_inst; // @[execution-unit.scala:92:20]
wire [31:0] rrd_uop_bits_out_inst = arb_uop_bits_inst; // @[util.scala:104:23]
wire [31:0] arb_uop_bits_out_1_inst = arb_uop_bits_inst; // @[util.scala:104:23]
reg [31:0] arb_uop_bits_debug_inst; // @[execution-unit.scala:92:20]
wire [31:0] rrd_uop_bits_out_debug_inst = arb_uop_bits_debug_inst; // @[util.scala:104:23]
wire [31:0] arb_uop_bits_out_1_debug_inst = arb_uop_bits_debug_inst; // @[util.scala:104:23]
reg arb_uop_bits_is_rvc; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_rvc = arb_uop_bits_is_rvc; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_rvc = arb_uop_bits_is_rvc; // @[util.scala:104:23]
reg [39:0] arb_uop_bits_debug_pc; // @[execution-unit.scala:92:20]
wire [39:0] rrd_uop_bits_out_debug_pc = arb_uop_bits_debug_pc; // @[util.scala:104:23]
wire [39:0] arb_uop_bits_out_1_debug_pc = arb_uop_bits_debug_pc; // @[util.scala:104:23]
reg arb_uop_bits_iq_type_0; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iq_type_0 = arb_uop_bits_iq_type_0; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iq_type_0 = arb_uop_bits_iq_type_0; // @[util.scala:104:23]
reg arb_uop_bits_iq_type_1; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iq_type_1 = arb_uop_bits_iq_type_1; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iq_type_1 = arb_uop_bits_iq_type_1; // @[util.scala:104:23]
reg arb_uop_bits_iq_type_2; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iq_type_2 = arb_uop_bits_iq_type_2; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iq_type_2 = arb_uop_bits_iq_type_2; // @[util.scala:104:23]
reg arb_uop_bits_iq_type_3; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iq_type_3 = arb_uop_bits_iq_type_3; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iq_type_3 = arb_uop_bits_iq_type_3; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_0; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_0 = arb_uop_bits_fu_code_0; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_0 = arb_uop_bits_fu_code_0; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_1; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_1 = arb_uop_bits_fu_code_1; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_1 = arb_uop_bits_fu_code_1; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_2; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_2 = arb_uop_bits_fu_code_2; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_2 = arb_uop_bits_fu_code_2; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_3; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_3 = arb_uop_bits_fu_code_3; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_3 = arb_uop_bits_fu_code_3; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_4; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_4 = arb_uop_bits_fu_code_4; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_4 = arb_uop_bits_fu_code_4; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_5; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_5 = arb_uop_bits_fu_code_5; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_5 = arb_uop_bits_fu_code_5; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_6; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_6 = arb_uop_bits_fu_code_6; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_6 = arb_uop_bits_fu_code_6; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_7; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_7 = arb_uop_bits_fu_code_7; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_7 = arb_uop_bits_fu_code_7; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_8; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_8 = arb_uop_bits_fu_code_8; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_8 = arb_uop_bits_fu_code_8; // @[util.scala:104:23]
reg arb_uop_bits_fu_code_9; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fu_code_9 = arb_uop_bits_fu_code_9; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fu_code_9 = arb_uop_bits_fu_code_9; // @[util.scala:104:23]
reg arb_uop_bits_iw_issued; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iw_issued = arb_uop_bits_iw_issued; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iw_issued = arb_uop_bits_iw_issued; // @[util.scala:104:23]
reg arb_uop_bits_iw_issued_partial_agen; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iw_issued_partial_agen = arb_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iw_issued_partial_agen = arb_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23]
reg arb_uop_bits_iw_issued_partial_dgen; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iw_issued_partial_dgen = arb_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iw_issued_partial_dgen = arb_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23]
reg [2:0] arb_uop_bits_iw_p1_speculative_child; // @[execution-unit.scala:92:20]
wire [2:0] rrd_uop_bits_out_iw_p1_speculative_child = arb_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_1_iw_p1_speculative_child = arb_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23]
reg [2:0] arb_uop_bits_iw_p2_speculative_child; // @[execution-unit.scala:92:20]
wire [2:0] rrd_uop_bits_out_iw_p2_speculative_child = arb_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_1_iw_p2_speculative_child = arb_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23]
reg arb_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iw_p1_bypass_hint = arb_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iw_p1_bypass_hint = arb_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23]
reg arb_uop_bits_iw_p2_bypass_hint; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iw_p2_bypass_hint = arb_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iw_p2_bypass_hint = arb_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23]
reg arb_uop_bits_iw_p3_bypass_hint; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_iw_p3_bypass_hint = arb_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23]
wire arb_uop_bits_out_1_iw_p3_bypass_hint = arb_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [2:0] arb_uop_bits_dis_col_sel; // @[execution-unit.scala:92:20]
wire [2:0] rrd_uop_bits_out_dis_col_sel = arb_uop_bits_dis_col_sel; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_1_dis_col_sel = arb_uop_bits_dis_col_sel; // @[util.scala:104:23]
reg [15:0] arb_uop_bits_br_mask; // @[execution-unit.scala:92:20]
reg [3:0] arb_uop_bits_br_tag; // @[execution-unit.scala:92:20]
wire [3:0] rrd_uop_bits_out_br_tag = arb_uop_bits_br_tag; // @[util.scala:104:23]
wire [3:0] arb_uop_bits_out_1_br_tag = arb_uop_bits_br_tag; // @[util.scala:104:23]
reg [3:0] arb_uop_bits_br_type; // @[execution-unit.scala:92:20]
wire [3:0] rrd_uop_bits_out_br_type = arb_uop_bits_br_type; // @[util.scala:104:23]
wire [3:0] arb_uop_bits_out_1_br_type = arb_uop_bits_br_type; // @[util.scala:104:23]
reg arb_uop_bits_is_sfb; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_sfb = arb_uop_bits_is_sfb; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_sfb = arb_uop_bits_is_sfb; // @[util.scala:104:23]
reg arb_uop_bits_is_fence; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_fence = arb_uop_bits_is_fence; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_fence = arb_uop_bits_is_fence; // @[util.scala:104:23]
reg arb_uop_bits_is_fencei; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_fencei = arb_uop_bits_is_fencei; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_fencei = arb_uop_bits_is_fencei; // @[util.scala:104:23]
reg arb_uop_bits_is_sfence; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_sfence = arb_uop_bits_is_sfence; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_sfence = arb_uop_bits_is_sfence; // @[util.scala:104:23]
reg arb_uop_bits_is_amo; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_amo = arb_uop_bits_is_amo; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_amo = arb_uop_bits_is_amo; // @[util.scala:104:23]
reg arb_uop_bits_is_eret; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_eret = arb_uop_bits_is_eret; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_eret = arb_uop_bits_is_eret; // @[util.scala:104:23]
reg arb_uop_bits_is_sys_pc2epc; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_sys_pc2epc = arb_uop_bits_is_sys_pc2epc; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_sys_pc2epc = arb_uop_bits_is_sys_pc2epc; // @[util.scala:104:23]
reg arb_uop_bits_is_rocc; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_rocc = arb_uop_bits_is_rocc; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_rocc = arb_uop_bits_is_rocc; // @[util.scala:104:23]
reg arb_uop_bits_is_mov; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_mov = arb_uop_bits_is_mov; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_mov = arb_uop_bits_is_mov; // @[util.scala:104:23]
reg [4:0] arb_uop_bits_ftq_idx; // @[execution-unit.scala:92:20]
wire [4:0] rrd_uop_bits_out_ftq_idx = arb_uop_bits_ftq_idx; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_1_ftq_idx = arb_uop_bits_ftq_idx; // @[util.scala:104:23]
reg arb_uop_bits_edge_inst; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_edge_inst = arb_uop_bits_edge_inst; // @[util.scala:104:23]
wire arb_uop_bits_out_1_edge_inst = arb_uop_bits_edge_inst; // @[util.scala:104:23]
reg [5:0] arb_uop_bits_pc_lob; // @[execution-unit.scala:92:20]
wire [5:0] rrd_uop_bits_out_pc_lob = arb_uop_bits_pc_lob; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_1_pc_lob = arb_uop_bits_pc_lob; // @[util.scala:104:23]
reg arb_uop_bits_taken; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_taken = arb_uop_bits_taken; // @[util.scala:104:23]
wire arb_uop_bits_out_1_taken = arb_uop_bits_taken; // @[util.scala:104:23]
reg arb_uop_bits_imm_rename; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_imm_rename = arb_uop_bits_imm_rename; // @[util.scala:104:23]
wire arb_uop_bits_out_1_imm_rename = arb_uop_bits_imm_rename; // @[util.scala:104:23]
reg [2:0] arb_uop_bits_imm_sel; // @[execution-unit.scala:92:20]
wire [2:0] rrd_uop_bits_out_imm_sel = arb_uop_bits_imm_sel; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_1_imm_sel = arb_uop_bits_imm_sel; // @[util.scala:104:23]
reg [4:0] arb_uop_bits_pimm; // @[execution-unit.scala:92:20]
assign io_arb_immrf_req_bits_0 = arb_uop_bits_pimm; // @[execution-unit.scala:92:20, :255:7]
wire [4:0] rrd_uop_bits_out_pimm = arb_uop_bits_pimm; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_1_pimm = arb_uop_bits_pimm; // @[util.scala:104:23]
reg [19:0] arb_uop_bits_imm_packed; // @[execution-unit.scala:92:20]
wire [19:0] rrd_uop_bits_out_imm_packed = arb_uop_bits_imm_packed; // @[util.scala:104:23]
wire [19:0] arb_uop_bits_out_1_imm_packed = arb_uop_bits_imm_packed; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_op1_sel; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_op1_sel = arb_uop_bits_op1_sel; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_op1_sel = arb_uop_bits_op1_sel; // @[util.scala:104:23]
reg [2:0] arb_uop_bits_op2_sel; // @[execution-unit.scala:92:20]
wire [2:0] rrd_uop_bits_out_op2_sel = arb_uop_bits_op2_sel; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_1_op2_sel = arb_uop_bits_op2_sel; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_ldst; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_ldst = arb_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_ldst = arb_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_wen; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_wen = arb_uop_bits_fp_ctrl_wen; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_wen = arb_uop_bits_fp_ctrl_wen; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_ren1; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_ren1 = arb_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_ren1 = arb_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_ren2; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_ren2 = arb_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_ren2 = arb_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_ren3; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_ren3 = arb_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_ren3 = arb_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_swap12; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_swap12 = arb_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_swap12 = arb_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_swap23; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_swap23 = arb_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_swap23 = arb_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_fp_ctrl_typeTagIn; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_fp_ctrl_typeTagIn = arb_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_fp_ctrl_typeTagIn = arb_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_fp_ctrl_typeTagOut; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_fp_ctrl_typeTagOut = arb_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_fp_ctrl_typeTagOut = arb_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_fromint; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_fromint = arb_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_fromint = arb_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_toint; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_toint = arb_uop_bits_fp_ctrl_toint; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_toint = arb_uop_bits_fp_ctrl_toint; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_fastpipe; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_fastpipe = arb_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_fastpipe = arb_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_fma; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_fma = arb_uop_bits_fp_ctrl_fma; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_fma = arb_uop_bits_fp_ctrl_fma; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_div; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_div = arb_uop_bits_fp_ctrl_div; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_div = arb_uop_bits_fp_ctrl_div; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_sqrt; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_sqrt = arb_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_sqrt = arb_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_wflags; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_wflags = arb_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_wflags = arb_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23]
reg arb_uop_bits_fp_ctrl_vec; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_ctrl_vec = arb_uop_bits_fp_ctrl_vec; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_ctrl_vec = arb_uop_bits_fp_ctrl_vec; // @[util.scala:104:23]
reg [6:0] arb_uop_bits_rob_idx; // @[execution-unit.scala:92:20]
wire [6:0] rrd_uop_bits_out_rob_idx = arb_uop_bits_rob_idx; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_1_rob_idx = arb_uop_bits_rob_idx; // @[util.scala:104:23]
reg [4:0] arb_uop_bits_ldq_idx; // @[execution-unit.scala:92:20]
wire [4:0] rrd_uop_bits_out_ldq_idx = arb_uop_bits_ldq_idx; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_1_ldq_idx = arb_uop_bits_ldq_idx; // @[util.scala:104:23]
reg [4:0] arb_uop_bits_stq_idx; // @[execution-unit.scala:92:20]
wire [4:0] rrd_uop_bits_out_stq_idx = arb_uop_bits_stq_idx; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_1_stq_idx = arb_uop_bits_stq_idx; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_rxq_idx; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_rxq_idx = arb_uop_bits_rxq_idx; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_rxq_idx = arb_uop_bits_rxq_idx; // @[util.scala:104:23]
reg [6:0] arb_uop_bits_pdst; // @[execution-unit.scala:92:20]
wire [6:0] rrd_uop_bits_out_pdst = arb_uop_bits_pdst; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_1_pdst = arb_uop_bits_pdst; // @[util.scala:104:23]
reg [6:0] arb_uop_bits_prs1; // @[execution-unit.scala:92:20]
assign io_arb_irf_reqs_0_bits_0 = arb_uop_bits_prs1; // @[execution-unit.scala:92:20, :255:7]
wire [6:0] rrd_uop_bits_out_prs1 = arb_uop_bits_prs1; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_1_prs1 = arb_uop_bits_prs1; // @[util.scala:104:23]
reg [6:0] arb_uop_bits_prs2; // @[execution-unit.scala:92:20]
wire [6:0] rrd_uop_bits_out_prs2 = arb_uop_bits_prs2; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_1_prs2 = arb_uop_bits_prs2; // @[util.scala:104:23]
reg [6:0] arb_uop_bits_prs3; // @[execution-unit.scala:92:20]
wire [6:0] rrd_uop_bits_out_prs3 = arb_uop_bits_prs3; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_1_prs3 = arb_uop_bits_prs3; // @[util.scala:104:23]
reg [4:0] arb_uop_bits_ppred; // @[execution-unit.scala:92:20]
wire [4:0] rrd_uop_bits_out_ppred = arb_uop_bits_ppred; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_1_ppred = arb_uop_bits_ppred; // @[util.scala:104:23]
reg arb_uop_bits_prs1_busy; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_prs1_busy = arb_uop_bits_prs1_busy; // @[util.scala:104:23]
wire arb_uop_bits_out_1_prs1_busy = arb_uop_bits_prs1_busy; // @[util.scala:104:23]
reg arb_uop_bits_prs2_busy; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_prs2_busy = arb_uop_bits_prs2_busy; // @[util.scala:104:23]
wire arb_uop_bits_out_1_prs2_busy = arb_uop_bits_prs2_busy; // @[util.scala:104:23]
reg arb_uop_bits_prs3_busy; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_prs3_busy = arb_uop_bits_prs3_busy; // @[util.scala:104:23]
wire arb_uop_bits_out_1_prs3_busy = arb_uop_bits_prs3_busy; // @[util.scala:104:23]
reg arb_uop_bits_ppred_busy; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_ppred_busy = arb_uop_bits_ppred_busy; // @[util.scala:104:23]
wire arb_uop_bits_out_1_ppred_busy = arb_uop_bits_ppred_busy; // @[util.scala:104:23]
reg [6:0] arb_uop_bits_stale_pdst; // @[execution-unit.scala:92:20]
wire [6:0] rrd_uop_bits_out_stale_pdst = arb_uop_bits_stale_pdst; // @[util.scala:104:23]
wire [6:0] arb_uop_bits_out_1_stale_pdst = arb_uop_bits_stale_pdst; // @[util.scala:104:23]
reg arb_uop_bits_exception; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_exception = arb_uop_bits_exception; // @[util.scala:104:23]
wire arb_uop_bits_out_1_exception = arb_uop_bits_exception; // @[util.scala:104:23]
reg [63:0] arb_uop_bits_exc_cause; // @[execution-unit.scala:92:20]
wire [63:0] rrd_uop_bits_out_exc_cause = arb_uop_bits_exc_cause; // @[util.scala:104:23]
wire [63:0] arb_uop_bits_out_1_exc_cause = arb_uop_bits_exc_cause; // @[util.scala:104:23]
reg [4:0] arb_uop_bits_mem_cmd; // @[execution-unit.scala:92:20]
wire [4:0] rrd_uop_bits_out_mem_cmd = arb_uop_bits_mem_cmd; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_1_mem_cmd = arb_uop_bits_mem_cmd; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_mem_size; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_mem_size = arb_uop_bits_mem_size; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_mem_size = arb_uop_bits_mem_size; // @[util.scala:104:23]
reg arb_uop_bits_mem_signed; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_mem_signed = arb_uop_bits_mem_signed; // @[util.scala:104:23]
wire arb_uop_bits_out_1_mem_signed = arb_uop_bits_mem_signed; // @[util.scala:104:23]
reg arb_uop_bits_uses_ldq; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_uses_ldq = arb_uop_bits_uses_ldq; // @[util.scala:104:23]
wire arb_uop_bits_out_1_uses_ldq = arb_uop_bits_uses_ldq; // @[util.scala:104:23]
reg arb_uop_bits_uses_stq; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_uses_stq = arb_uop_bits_uses_stq; // @[util.scala:104:23]
wire arb_uop_bits_out_1_uses_stq = arb_uop_bits_uses_stq; // @[util.scala:104:23]
reg arb_uop_bits_is_unique; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_is_unique = arb_uop_bits_is_unique; // @[util.scala:104:23]
wire arb_uop_bits_out_1_is_unique = arb_uop_bits_is_unique; // @[util.scala:104:23]
reg arb_uop_bits_flush_on_commit; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_flush_on_commit = arb_uop_bits_flush_on_commit; // @[util.scala:104:23]
wire arb_uop_bits_out_1_flush_on_commit = arb_uop_bits_flush_on_commit; // @[util.scala:104:23]
reg [2:0] arb_uop_bits_csr_cmd; // @[execution-unit.scala:92:20]
wire [2:0] rrd_uop_bits_out_csr_cmd = arb_uop_bits_csr_cmd; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_1_csr_cmd = arb_uop_bits_csr_cmd; // @[util.scala:104:23]
reg arb_uop_bits_ldst_is_rs1; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_ldst_is_rs1 = arb_uop_bits_ldst_is_rs1; // @[util.scala:104:23]
wire arb_uop_bits_out_1_ldst_is_rs1 = arb_uop_bits_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] arb_uop_bits_ldst; // @[execution-unit.scala:92:20]
wire [5:0] rrd_uop_bits_out_ldst = arb_uop_bits_ldst; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_1_ldst = arb_uop_bits_ldst; // @[util.scala:104:23]
reg [5:0] arb_uop_bits_lrs1; // @[execution-unit.scala:92:20]
wire [5:0] rrd_uop_bits_out_lrs1 = arb_uop_bits_lrs1; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_1_lrs1 = arb_uop_bits_lrs1; // @[util.scala:104:23]
reg [5:0] arb_uop_bits_lrs2; // @[execution-unit.scala:92:20]
wire [5:0] rrd_uop_bits_out_lrs2 = arb_uop_bits_lrs2; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_1_lrs2 = arb_uop_bits_lrs2; // @[util.scala:104:23]
reg [5:0] arb_uop_bits_lrs3; // @[execution-unit.scala:92:20]
wire [5:0] rrd_uop_bits_out_lrs3 = arb_uop_bits_lrs3; // @[util.scala:104:23]
wire [5:0] arb_uop_bits_out_1_lrs3 = arb_uop_bits_lrs3; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_dst_rtype; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_dst_rtype = arb_uop_bits_dst_rtype; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_dst_rtype = arb_uop_bits_dst_rtype; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_lrs1_rtype; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_lrs1_rtype = arb_uop_bits_lrs1_rtype; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_lrs1_rtype = arb_uop_bits_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_lrs2_rtype; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_lrs2_rtype = arb_uop_bits_lrs2_rtype; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_lrs2_rtype = arb_uop_bits_lrs2_rtype; // @[util.scala:104:23]
reg arb_uop_bits_frs3_en; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_frs3_en = arb_uop_bits_frs3_en; // @[util.scala:104:23]
wire arb_uop_bits_out_1_frs3_en = arb_uop_bits_frs3_en; // @[util.scala:104:23]
reg arb_uop_bits_fcn_dw; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fcn_dw = arb_uop_bits_fcn_dw; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fcn_dw = arb_uop_bits_fcn_dw; // @[util.scala:104:23]
reg [4:0] arb_uop_bits_fcn_op; // @[execution-unit.scala:92:20]
wire [4:0] rrd_uop_bits_out_fcn_op = arb_uop_bits_fcn_op; // @[util.scala:104:23]
wire [4:0] arb_uop_bits_out_1_fcn_op = arb_uop_bits_fcn_op; // @[util.scala:104:23]
reg arb_uop_bits_fp_val; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_fp_val = arb_uop_bits_fp_val; // @[util.scala:104:23]
wire arb_uop_bits_out_1_fp_val = arb_uop_bits_fp_val; // @[util.scala:104:23]
reg [2:0] arb_uop_bits_fp_rm; // @[execution-unit.scala:92:20]
wire [2:0] rrd_uop_bits_out_fp_rm = arb_uop_bits_fp_rm; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_1_fp_rm = arb_uop_bits_fp_rm; // @[util.scala:104:23]
reg [1:0] arb_uop_bits_fp_typ; // @[execution-unit.scala:92:20]
wire [1:0] rrd_uop_bits_out_fp_typ = arb_uop_bits_fp_typ; // @[util.scala:104:23]
wire [1:0] arb_uop_bits_out_1_fp_typ = arb_uop_bits_fp_typ; // @[util.scala:104:23]
reg arb_uop_bits_xcpt_pf_if; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_xcpt_pf_if = arb_uop_bits_xcpt_pf_if; // @[util.scala:104:23]
wire arb_uop_bits_out_1_xcpt_pf_if = arb_uop_bits_xcpt_pf_if; // @[util.scala:104:23]
reg arb_uop_bits_xcpt_ae_if; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_xcpt_ae_if = arb_uop_bits_xcpt_ae_if; // @[util.scala:104:23]
wire arb_uop_bits_out_1_xcpt_ae_if = arb_uop_bits_xcpt_ae_if; // @[util.scala:104:23]
reg arb_uop_bits_xcpt_ma_if; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_xcpt_ma_if = arb_uop_bits_xcpt_ma_if; // @[util.scala:104:23]
wire arb_uop_bits_out_1_xcpt_ma_if = arb_uop_bits_xcpt_ma_if; // @[util.scala:104:23]
reg arb_uop_bits_bp_debug_if; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_bp_debug_if = arb_uop_bits_bp_debug_if; // @[util.scala:104:23]
wire arb_uop_bits_out_1_bp_debug_if = arb_uop_bits_bp_debug_if; // @[util.scala:104:23]
reg arb_uop_bits_bp_xcpt_if; // @[execution-unit.scala:92:20]
wire rrd_uop_bits_out_bp_xcpt_if = arb_uop_bits_bp_xcpt_if; // @[util.scala:104:23]
wire arb_uop_bits_out_1_bp_xcpt_if = arb_uop_bits_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] arb_uop_bits_debug_fsrc; // @[execution-unit.scala:92:20]
wire [2:0] rrd_uop_bits_out_debug_fsrc = arb_uop_bits_debug_fsrc; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_1_debug_fsrc = arb_uop_bits_debug_fsrc; // @[util.scala:104:23]
reg [2:0] arb_uop_bits_debug_tsrc; // @[execution-unit.scala:92:20]
wire [2:0] rrd_uop_bits_out_debug_tsrc = arb_uop_bits_debug_tsrc; // @[util.scala:104:23]
wire [2:0] arb_uop_bits_out_1_debug_tsrc = arb_uop_bits_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _arb_uop_valid_T = io_brupdate_b1_mispredict_mask & io_iss_uop_bits_br_mask; // @[util.scala:126:51]
wire _arb_uop_valid_T_1 = |_arb_uop_valid_T; // @[util.scala:126:{51,59}]
wire _arb_uop_valid_T_2 = _arb_uop_valid_T_1 | io_kill; // @[util.scala:61:61, :126:59]
wire _arb_uop_valid_T_3 = ~_arb_uop_valid_T_2; // @[util.scala:61:61]
wire _arb_uop_valid_T_4 = io_iss_uop_valid & _arb_uop_valid_T_3; // @[execution-unit.scala:93:{37,40}]
wire [15:0] _arb_uop_bits_out_br_mask_T_1; // @[util.scala:93:25]
wire [15:0] arb_uop_bits_out_br_mask; // @[util.scala:104:23]
wire [15:0] _arb_uop_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27]
assign _arb_uop_bits_out_br_mask_T_1 = io_iss_uop_bits_br_mask & _arb_uop_bits_out_br_mask_T; // @[util.scala:93:{25,27}]
assign arb_uop_bits_out_br_mask = _arb_uop_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
reg rrd_uop_valid; // @[execution-unit.scala:95:20]
wire [31:0] exe_uop_bits_out_inst = rrd_uop_bits_inst; // @[util.scala:104:23]
wire [31:0] exe_uop_bits_out_debug_inst = rrd_uop_bits_debug_inst; // @[util.scala:104:23]
wire exe_uop_bits_out_is_rvc = rrd_uop_bits_is_rvc; // @[util.scala:104:23]
wire [39:0] exe_uop_bits_out_debug_pc = rrd_uop_bits_debug_pc; // @[util.scala:104:23]
wire exe_uop_bits_out_iq_type_0 = rrd_uop_bits_iq_type_0; // @[util.scala:104:23]
wire exe_uop_bits_out_iq_type_1 = rrd_uop_bits_iq_type_1; // @[util.scala:104:23]
wire exe_uop_bits_out_iq_type_2 = rrd_uop_bits_iq_type_2; // @[util.scala:104:23]
wire exe_uop_bits_out_iq_type_3 = rrd_uop_bits_iq_type_3; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_0 = rrd_uop_bits_fu_code_0; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_1 = rrd_uop_bits_fu_code_1; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_2 = rrd_uop_bits_fu_code_2; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_3 = rrd_uop_bits_fu_code_3; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_4 = rrd_uop_bits_fu_code_4; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_5 = rrd_uop_bits_fu_code_5; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_6 = rrd_uop_bits_fu_code_6; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_7 = rrd_uop_bits_fu_code_7; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_8 = rrd_uop_bits_fu_code_8; // @[util.scala:104:23]
wire exe_uop_bits_out_fu_code_9 = rrd_uop_bits_fu_code_9; // @[util.scala:104:23]
wire exe_uop_bits_out_iw_issued = rrd_uop_bits_iw_issued; // @[util.scala:104:23]
wire exe_uop_bits_out_iw_issued_partial_agen = rrd_uop_bits_iw_issued_partial_agen; // @[util.scala:104:23]
wire exe_uop_bits_out_iw_issued_partial_dgen = rrd_uop_bits_iw_issued_partial_dgen; // @[util.scala:104:23]
wire [2:0] exe_uop_bits_out_iw_p1_speculative_child = rrd_uop_bits_iw_p1_speculative_child; // @[util.scala:104:23]
wire [2:0] exe_uop_bits_out_iw_p2_speculative_child = rrd_uop_bits_iw_p2_speculative_child; // @[util.scala:104:23]
wire exe_uop_bits_out_iw_p1_bypass_hint = rrd_uop_bits_iw_p1_bypass_hint; // @[util.scala:104:23]
wire exe_uop_bits_out_iw_p2_bypass_hint = rrd_uop_bits_iw_p2_bypass_hint; // @[util.scala:104:23]
wire exe_uop_bits_out_iw_p3_bypass_hint = rrd_uop_bits_iw_p3_bypass_hint; // @[util.scala:104:23]
wire [2:0] exe_uop_bits_out_dis_col_sel = rrd_uop_bits_dis_col_sel; // @[util.scala:104:23]
wire [3:0] exe_uop_bits_out_br_tag = rrd_uop_bits_br_tag; // @[util.scala:104:23]
wire [3:0] exe_uop_bits_out_br_type = rrd_uop_bits_br_type; // @[util.scala:104:23]
wire exe_uop_bits_out_is_sfb = rrd_uop_bits_is_sfb; // @[util.scala:104:23]
wire exe_uop_bits_out_is_fence = rrd_uop_bits_is_fence; // @[util.scala:104:23]
wire exe_uop_bits_out_is_fencei = rrd_uop_bits_is_fencei; // @[util.scala:104:23]
wire exe_uop_bits_out_is_sfence = rrd_uop_bits_is_sfence; // @[util.scala:104:23]
wire exe_uop_bits_out_is_amo = rrd_uop_bits_is_amo; // @[util.scala:104:23]
wire exe_uop_bits_out_is_eret = rrd_uop_bits_is_eret; // @[util.scala:104:23]
wire exe_uop_bits_out_is_sys_pc2epc = rrd_uop_bits_is_sys_pc2epc; // @[util.scala:104:23]
wire exe_uop_bits_out_is_rocc = rrd_uop_bits_is_rocc; // @[util.scala:104:23]
wire exe_uop_bits_out_is_mov = rrd_uop_bits_is_mov; // @[util.scala:104:23]
wire [4:0] exe_uop_bits_out_ftq_idx = rrd_uop_bits_ftq_idx; // @[util.scala:104:23]
wire exe_uop_bits_out_edge_inst = rrd_uop_bits_edge_inst; // @[util.scala:104:23]
wire [5:0] exe_uop_bits_out_pc_lob = rrd_uop_bits_pc_lob; // @[util.scala:104:23]
wire exe_uop_bits_out_taken = rrd_uop_bits_taken; // @[util.scala:104:23]
wire exe_uop_bits_out_imm_rename = rrd_uop_bits_imm_rename; // @[util.scala:104:23]
wire [2:0] exe_uop_bits_out_imm_sel = rrd_uop_bits_imm_sel; // @[util.scala:104:23]
wire [4:0] exe_uop_bits_out_pimm = rrd_uop_bits_pimm; // @[util.scala:104:23]
wire [19:0] exe_uop_bits_out_imm_packed = rrd_uop_bits_imm_packed; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_op1_sel = rrd_uop_bits_op1_sel; // @[util.scala:104:23]
wire [2:0] exe_uop_bits_out_op2_sel = rrd_uop_bits_op2_sel; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_ldst = rrd_uop_bits_fp_ctrl_ldst; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_wen = rrd_uop_bits_fp_ctrl_wen; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_ren1 = rrd_uop_bits_fp_ctrl_ren1; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_ren2 = rrd_uop_bits_fp_ctrl_ren2; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_ren3 = rrd_uop_bits_fp_ctrl_ren3; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_swap12 = rrd_uop_bits_fp_ctrl_swap12; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_swap23 = rrd_uop_bits_fp_ctrl_swap23; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_fp_ctrl_typeTagIn = rrd_uop_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_fp_ctrl_typeTagOut = rrd_uop_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_fromint = rrd_uop_bits_fp_ctrl_fromint; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_toint = rrd_uop_bits_fp_ctrl_toint; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_fastpipe = rrd_uop_bits_fp_ctrl_fastpipe; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_fma = rrd_uop_bits_fp_ctrl_fma; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_div = rrd_uop_bits_fp_ctrl_div; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_sqrt = rrd_uop_bits_fp_ctrl_sqrt; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_wflags = rrd_uop_bits_fp_ctrl_wflags; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_ctrl_vec = rrd_uop_bits_fp_ctrl_vec; // @[util.scala:104:23]
wire [6:0] exe_uop_bits_out_rob_idx = rrd_uop_bits_rob_idx; // @[util.scala:104:23]
wire [4:0] exe_uop_bits_out_ldq_idx = rrd_uop_bits_ldq_idx; // @[util.scala:104:23]
wire [4:0] exe_uop_bits_out_stq_idx = rrd_uop_bits_stq_idx; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_rxq_idx = rrd_uop_bits_rxq_idx; // @[util.scala:104:23]
wire [6:0] exe_uop_bits_out_pdst = rrd_uop_bits_pdst; // @[util.scala:104:23]
wire [6:0] exe_uop_bits_out_prs1 = rrd_uop_bits_prs1; // @[util.scala:104:23]
wire [6:0] exe_uop_bits_out_prs2 = rrd_uop_bits_prs2; // @[util.scala:104:23]
wire [6:0] exe_uop_bits_out_prs3 = rrd_uop_bits_prs3; // @[util.scala:104:23]
wire [4:0] exe_uop_bits_out_ppred = rrd_uop_bits_ppred; // @[util.scala:104:23]
wire exe_uop_bits_out_prs1_busy = rrd_uop_bits_prs1_busy; // @[util.scala:104:23]
wire exe_uop_bits_out_prs2_busy = rrd_uop_bits_prs2_busy; // @[util.scala:104:23]
wire exe_uop_bits_out_prs3_busy = rrd_uop_bits_prs3_busy; // @[util.scala:104:23]
wire exe_uop_bits_out_ppred_busy = rrd_uop_bits_ppred_busy; // @[util.scala:104:23]
wire [6:0] exe_uop_bits_out_stale_pdst = rrd_uop_bits_stale_pdst; // @[util.scala:104:23]
wire exe_uop_bits_out_exception = rrd_uop_bits_exception; // @[util.scala:104:23]
wire [63:0] exe_uop_bits_out_exc_cause = rrd_uop_bits_exc_cause; // @[util.scala:104:23]
wire [4:0] exe_uop_bits_out_mem_cmd = rrd_uop_bits_mem_cmd; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_mem_size = rrd_uop_bits_mem_size; // @[util.scala:104:23]
wire exe_uop_bits_out_mem_signed = rrd_uop_bits_mem_signed; // @[util.scala:104:23]
wire exe_uop_bits_out_uses_ldq = rrd_uop_bits_uses_ldq; // @[util.scala:104:23]
wire exe_uop_bits_out_uses_stq = rrd_uop_bits_uses_stq; // @[util.scala:104:23]
wire exe_uop_bits_out_is_unique = rrd_uop_bits_is_unique; // @[util.scala:104:23]
wire exe_uop_bits_out_flush_on_commit = rrd_uop_bits_flush_on_commit; // @[util.scala:104:23]
wire [2:0] exe_uop_bits_out_csr_cmd = rrd_uop_bits_csr_cmd; // @[util.scala:104:23]
wire exe_uop_bits_out_ldst_is_rs1 = rrd_uop_bits_ldst_is_rs1; // @[util.scala:104:23]
wire [5:0] exe_uop_bits_out_ldst = rrd_uop_bits_ldst; // @[util.scala:104:23]
wire [5:0] exe_uop_bits_out_lrs1 = rrd_uop_bits_lrs1; // @[util.scala:104:23]
wire [5:0] exe_uop_bits_out_lrs2 = rrd_uop_bits_lrs2; // @[util.scala:104:23]
wire [5:0] exe_uop_bits_out_lrs3 = rrd_uop_bits_lrs3; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_dst_rtype = rrd_uop_bits_dst_rtype; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_lrs1_rtype = rrd_uop_bits_lrs1_rtype; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_lrs2_rtype = rrd_uop_bits_lrs2_rtype; // @[util.scala:104:23]
wire exe_uop_bits_out_frs3_en = rrd_uop_bits_frs3_en; // @[util.scala:104:23]
wire exe_uop_bits_out_fcn_dw = rrd_uop_bits_fcn_dw; // @[util.scala:104:23]
wire [4:0] exe_uop_bits_out_fcn_op = rrd_uop_bits_fcn_op; // @[util.scala:104:23]
wire exe_uop_bits_out_fp_val = rrd_uop_bits_fp_val; // @[util.scala:104:23]
wire [2:0] exe_uop_bits_out_fp_rm = rrd_uop_bits_fp_rm; // @[util.scala:104:23]
wire [1:0] exe_uop_bits_out_fp_typ = rrd_uop_bits_fp_typ; // @[util.scala:104:23]
wire exe_uop_bits_out_xcpt_pf_if = rrd_uop_bits_xcpt_pf_if; // @[util.scala:104:23]
wire exe_uop_bits_out_xcpt_ae_if = rrd_uop_bits_xcpt_ae_if; // @[util.scala:104:23]
wire exe_uop_bits_out_xcpt_ma_if = rrd_uop_bits_xcpt_ma_if; // @[util.scala:104:23]
wire exe_uop_bits_out_bp_debug_if = rrd_uop_bits_bp_debug_if; // @[util.scala:104:23]
wire exe_uop_bits_out_bp_xcpt_if = rrd_uop_bits_bp_xcpt_if; // @[util.scala:104:23]
wire [2:0] exe_uop_bits_out_debug_fsrc = rrd_uop_bits_debug_fsrc; // @[util.scala:104:23]
wire [2:0] exe_uop_bits_out_debug_tsrc = rrd_uop_bits_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _GEN = io_brupdate_b1_mispredict_mask & arb_uop_bits_br_mask; // @[util.scala:126:51]
wire [15:0] _rrd_uop_valid_T; // @[util.scala:126:51]
assign _rrd_uop_valid_T = _GEN; // @[util.scala:126:51]
wire [15:0] _will_replay_T; // @[util.scala:126:51]
assign _will_replay_T = _GEN; // @[util.scala:126:51]
wire _rrd_uop_valid_T_1 = |_rrd_uop_valid_T; // @[util.scala:126:{51,59}]
wire _rrd_uop_valid_T_2 = _rrd_uop_valid_T_1 | io_kill; // @[util.scala:61:61, :126:59]
wire _rrd_uop_valid_T_3 = ~_rrd_uop_valid_T_2; // @[util.scala:61:61]
wire _rrd_uop_valid_T_4 = arb_uop_valid & _rrd_uop_valid_T_3; // @[execution-unit.scala:92:20, :96:{34,37}]
wire [15:0] _rrd_uop_bits_out_br_mask_T_1; // @[util.scala:93:25]
wire [15:0] rrd_uop_bits_out_br_mask; // @[util.scala:104:23]
wire [15:0] _rrd_uop_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27]
assign _rrd_uop_bits_out_br_mask_T_1 = arb_uop_bits_br_mask & _rrd_uop_bits_out_br_mask_T; // @[util.scala:93:{25,27}]
assign rrd_uop_bits_out_br_mask = _rrd_uop_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
reg exe_uop_valid; // @[execution-unit.scala:98:20]
wire [15:0] _exe_uop_valid_T = io_brupdate_b1_mispredict_mask & rrd_uop_bits_br_mask; // @[util.scala:126:51]
wire _exe_uop_valid_T_1 = |_exe_uop_valid_T; // @[util.scala:126:{51,59}]
wire _exe_uop_valid_T_2 = _exe_uop_valid_T_1 | io_kill; // @[util.scala:61:61, :126:59]
wire _exe_uop_valid_T_3 = ~_exe_uop_valid_T_2; // @[util.scala:61:61]
wire _exe_uop_valid_T_4 = rrd_uop_valid & _exe_uop_valid_T_3; // @[execution-unit.scala:95:20, :99:{34,37}]
wire [15:0] _exe_uop_bits_out_br_mask_T_1; // @[util.scala:93:25]
wire [15:0] exe_uop_bits_out_br_mask; // @[util.scala:104:23]
wire [15:0] _exe_uop_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27]
assign _exe_uop_bits_out_br_mask_T_1 = rrd_uop_bits_br_mask & _exe_uop_bits_out_br_mask_T; // @[util.scala:93:{25,27}]
assign exe_uop_bits_out_br_mask = _exe_uop_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
wire _GEN_0 = arb_uop_bits_lrs1_rtype == 2'h0; // @[execution-unit.scala:92:20, :121:72]
wire _io_arb_irf_reqs_0_valid_T; // @[execution-unit.scala:121:72]
assign _io_arb_irf_reqs_0_valid_T = _GEN_0; // @[execution-unit.scala:121:72]
wire _arb_rebusied_prs1_T; // @[execution-unit.scala:128:51]
assign _arb_rebusied_prs1_T = _GEN_0; // @[execution-unit.scala:121:72, :128:51]
wire _io_arb_irf_reqs_0_valid_T_1 = arb_uop_valid & _io_arb_irf_reqs_0_valid_T; // @[execution-unit.scala:92:20, :121:{45,72}]
wire _io_arb_irf_reqs_0_valid_T_2 = ~arb_uop_bits_iw_p1_bypass_hint; // @[execution-unit.scala:92:20, :121:86]
assign _io_arb_irf_reqs_0_valid_T_3 = _io_arb_irf_reqs_0_valid_T_1 & _io_arb_irf_reqs_0_valid_T_2; // @[execution-unit.scala:121:{45,83,86}]
assign io_arb_irf_reqs_0_valid_0 = _io_arb_irf_reqs_0_valid_T_3; // @[execution-unit.scala:121:83, :255:7]
wire _GEN_1 = io_arb_rebusys_0_valid & io_arb_rebusys_0_bits_rebusy; // @[execution-unit.scala:118:39]
wire _arb_rebusied_prs1_T_1; // @[execution-unit.scala:118:39]
assign _arb_rebusied_prs1_T_1 = _GEN_1; // @[execution-unit.scala:118:39]
wire _arb_rebusied_prs2_T_1; // @[execution-unit.scala:118:39]
assign _arb_rebusied_prs2_T_1 = _GEN_1; // @[execution-unit.scala:118:39]
wire _arb_rebusied_prs1_T_2 = io_arb_rebusys_0_bits_uop_pdst == arb_uop_bits_prs1; // @[execution-unit.scala:92:20, :118:75]
wire _arb_rebusied_prs1_T_3 = _arb_rebusied_prs1_T_1 & _arb_rebusied_prs1_T_2; // @[execution-unit.scala:118:{39,56,75}]
wire arb_rebusied_prs1 = _arb_rebusied_prs1_T & _arb_rebusied_prs1_T_3; // @[execution-unit.scala:118:56, :128:{51,62}]
wire arb_rebusied = arb_rebusied_prs1; // @[execution-unit.scala:128:62, :130:45]
wire _arb_rebusied_prs2_T = arb_uop_bits_lrs2_rtype == 2'h0; // @[execution-unit.scala:92:20, :129:51]
wire _arb_rebusied_prs2_T_2 = io_arb_rebusys_0_bits_uop_pdst == arb_uop_bits_prs2; // @[execution-unit.scala:92:20, :118:75]
wire _arb_rebusied_prs2_T_3 = _arb_rebusied_prs2_T_1 & _arb_rebusied_prs2_T_2; // @[execution-unit.scala:118:{39,56,75}]
wire _arb_rebusied_prs2_T_4 = _arb_rebusied_prs2_T & _arb_rebusied_prs2_T_3; // @[execution-unit.scala:118:56, :129:{51,62}]
wire _hits_T = rrd_uop_bits_prs1 == io_rrd_irf_bypasses_0_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62]
wire hits_0 = io_rrd_irf_bypasses_0_valid & _hits_T; // @[execution-unit.scala:113:{55,62}]
wire _hits_T_1 = rrd_uop_bits_prs1 == io_rrd_irf_bypasses_1_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62]
wire hits_1 = io_rrd_irf_bypasses_1_valid & _hits_T_1; // @[execution-unit.scala:113:{55,62}]
wire _hits_T_2 = rrd_uop_bits_prs1 == io_rrd_irf_bypasses_2_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62]
wire hits_2 = io_rrd_irf_bypasses_2_valid & _hits_T_2; // @[execution-unit.scala:113:{55,62}]
wire _hits_T_3 = rrd_uop_bits_prs1 == io_rrd_irf_bypasses_3_bits_uop_pdst; // @[execution-unit.scala:95:20, :113:62]
wire hits_3 = io_rrd_irf_bypasses_3_valid & _hits_T_3; // @[execution-unit.scala:113:{55,62}]
wire _T_2 = hits_0 | hits_1; // @[execution-unit.scala:113:55, :114:19]
wire rs1_hit = _T_2 | hits_2 | hits_3; // @[execution-unit.scala:113:55, :114:19]
wire [63:0] rs1_data = _T_2 | hits_2 | hits_3 ? (hits_0 ? io_rrd_irf_bypasses_0_bits_data : 64'h0) | (hits_1 ? io_rrd_irf_bypasses_1_bits_data : 64'h0) | (hits_2 ? io_rrd_irf_bypasses_2_bits_data : 64'h0) | (hits_3 ? io_rrd_irf_bypasses_3_bits_data : 64'h0) : io_rrd_irf_resps_0; // @[Mux.scala:30:73]
wire _exe_rs1_data_T = &rrd_uop_bits_lrs1_rtype; // @[execution-unit.scala:95:20, :137:47]
wire [63:0] _exe_rs1_data_T_1 = _exe_rs1_data_T ? 64'h0 : rs1_data; // @[execution-unit.scala:114:28, :137:{22,47}]
wire _io_arb_immrf_req_valid_T = arb_uop_bits_imm_sel == 3'h6; // @[package.scala:16:47]
wire _io_arb_immrf_req_valid_T_1 = arb_uop_bits_imm_sel == 3'h5; // @[package.scala:16:47]
wire _io_arb_immrf_req_valid_T_2 = _io_arb_immrf_req_valid_T | _io_arb_immrf_req_valid_T_1; // @[package.scala:16:47, :81:59]
wire _io_arb_immrf_req_valid_T_3 = ~_io_arb_immrf_req_valid_T_2; // @[package.scala:81:59]
assign _io_arb_immrf_req_valid_T_4 = arb_uop_valid & _io_arb_immrf_req_valid_T_3; // @[execution-unit.scala:92:20, :157:44, :158:5]
assign io_arb_immrf_req_valid_0 = _io_arb_immrf_req_valid_T_4; // @[execution-unit.scala:157:44, :255:7]
wire _GEN_2 = rrd_uop_bits_imm_sel == 3'h6; // @[package.scala:16:47]
wire _io_rrd_immrf_wakeup_valid_T; // @[package.scala:16:47]
assign _io_rrd_immrf_wakeup_valid_T = _GEN_2; // @[package.scala:16:47]
wire _exe_imm_data_ip_T; // @[util.scala:282:23]
assign _exe_imm_data_ip_T = _GEN_2; // @[package.scala:16:47]
wire _GEN_3 = rrd_uop_bits_imm_sel == 3'h5; // @[package.scala:16:47]
wire _io_rrd_immrf_wakeup_valid_T_1; // @[package.scala:16:47]
assign _io_rrd_immrf_wakeup_valid_T_1 = _GEN_3; // @[package.scala:16:47]
wire _exe_imm_data_T; // @[execution-unit.scala:170:55]
assign _exe_imm_data_T = _GEN_3; // @[package.scala:16:47]
wire _io_rrd_immrf_wakeup_valid_T_2 = _io_rrd_immrf_wakeup_valid_T | _io_rrd_immrf_wakeup_valid_T_1; // @[package.scala:16:47, :81:59]
wire _io_rrd_immrf_wakeup_valid_T_3 = ~_io_rrd_immrf_wakeup_valid_T_2; // @[package.scala:81:59]
assign _io_rrd_immrf_wakeup_valid_T_4 = rrd_uop_valid & _io_rrd_immrf_wakeup_valid_T_3; // @[execution-unit.scala:95:20, :162:47, :163:5]
wire _exe_imm_data_T_1 = rrd_uop_bits_pimm[4]; // @[util.scala:269:46]
wire [58:0] _exe_imm_data_T_2 = {59{_exe_imm_data_T_1}}; // @[util.scala:269:{25,46}]
wire [63:0] _exe_imm_data_T_3 = {_exe_imm_data_T_2, rrd_uop_bits_pimm}; // @[util.scala:269:{20,25}]
wire [63:0] exe_imm_data_ip = _exe_imm_data_ip_T ? 64'h0 : io_rrd_immrf_resp; // @[util.scala:282:{17,23}]
wire _exe_imm_data_sign_T = exe_imm_data_ip[19]; // @[util.scala:282:17, :284:18]
wire exe_imm_data_sign = _exe_imm_data_sign_T; // @[util.scala:284:{18,37}]
wire exe_imm_data_hi_hi_hi = exe_imm_data_sign; // @[util.scala:284:37, :294:15]
wire _GEN_4 = rrd_uop_bits_imm_sel == 3'h3; // @[util.scala:285:27]
wire _exe_imm_data_i30_20_T; // @[util.scala:285:27]
assign _exe_imm_data_i30_20_T = _GEN_4; // @[util.scala:285:27]
wire _exe_imm_data_i19_12_T; // @[util.scala:286:27]
assign _exe_imm_data_i19_12_T = _GEN_4; // @[util.scala:285:27, :286:27]
wire _exe_imm_data_i11_T; // @[util.scala:287:27]
assign _exe_imm_data_i11_T = _GEN_4; // @[util.scala:285:27, :287:27]
wire _exe_imm_data_i10_5_T; // @[util.scala:289:27]
assign _exe_imm_data_i10_5_T = _GEN_4; // @[util.scala:285:27, :289:27]
wire _exe_imm_data_i4_1_T; // @[util.scala:290:27]
assign _exe_imm_data_i4_1_T = _GEN_4; // @[util.scala:285:27, :290:27]
wire [10:0] _exe_imm_data_i30_20_T_1 = exe_imm_data_ip[18:8]; // @[util.scala:282:17, :285:39]
wire [10:0] _exe_imm_data_i30_20_T_2 = _exe_imm_data_i30_20_T_1; // @[util.scala:285:{39,46}]
wire [10:0] exe_imm_data_i30_20 = _exe_imm_data_i30_20_T ? _exe_imm_data_i30_20_T_2 : {11{exe_imm_data_sign}}; // @[util.scala:284:37, :285:{21,27,46}]
wire [10:0] exe_imm_data_hi_hi_lo = exe_imm_data_i30_20; // @[util.scala:285:21, :294:15]
wire _GEN_5 = rrd_uop_bits_imm_sel == 3'h4; // @[util.scala:286:44]
wire _exe_imm_data_i19_12_T_1; // @[util.scala:286:44]
assign _exe_imm_data_i19_12_T_1 = _GEN_5; // @[util.scala:286:44]
wire _exe_imm_data_i11_T_1; // @[util.scala:288:27]
assign _exe_imm_data_i11_T_1 = _GEN_5; // @[util.scala:286:44, :288:27]
wire _exe_imm_data_i19_12_T_2 = _exe_imm_data_i19_12_T | _exe_imm_data_i19_12_T_1; // @[util.scala:286:{27,36,44}]
wire [7:0] _exe_imm_data_i19_12_T_3 = exe_imm_data_ip[7:0]; // @[util.scala:282:17, :286:56]
wire [7:0] _exe_imm_data_i19_12_T_4 = _exe_imm_data_i19_12_T_3; // @[util.scala:286:{56,62}]
wire [7:0] exe_imm_data_i19_12 = _exe_imm_data_i19_12_T_2 ? _exe_imm_data_i19_12_T_4 : {8{exe_imm_data_sign}}; // @[util.scala:284:37, :286:{21,36,62}]
wire [7:0] exe_imm_data_hi_lo_hi = exe_imm_data_i19_12; // @[util.scala:286:21, :294:15]
wire _exe_imm_data_i11_T_2 = rrd_uop_bits_imm_sel == 3'h2; // @[util.scala:288:44]
wire _exe_imm_data_i11_T_3 = _exe_imm_data_i11_T_1 | _exe_imm_data_i11_T_2; // @[util.scala:288:{27,36,44}]
wire _exe_imm_data_i11_T_4 = exe_imm_data_ip[8]; // @[util.scala:282:17, :288:56]
wire _exe_imm_data_i0_T_3 = exe_imm_data_ip[8]; // @[util.scala:282:17, :288:56, :291:56]
wire _exe_imm_data_i11_T_5 = _exe_imm_data_i11_T_4; // @[util.scala:288:{56,60}]
wire _exe_imm_data_i11_T_6 = _exe_imm_data_i11_T_3 ? _exe_imm_data_i11_T_5 : exe_imm_data_sign; // @[util.scala:284:37, :288:{21,36,60}]
wire exe_imm_data_i11 = ~_exe_imm_data_i11_T & _exe_imm_data_i11_T_6; // @[util.scala:287:{21,27}, :288:21]
wire exe_imm_data_hi_lo_lo = exe_imm_data_i11; // @[util.scala:287:21, :294:15]
wire [4:0] _exe_imm_data_i10_5_T_1 = exe_imm_data_ip[18:14]; // @[util.scala:282:17, :289:44]
wire [4:0] _exe_imm_data_i10_5_T_2 = _exe_imm_data_i10_5_T_1; // @[util.scala:289:{44,52}]
wire [4:0] exe_imm_data_i10_5 = _exe_imm_data_i10_5_T ? 5'h0 : _exe_imm_data_i10_5_T_2; // @[util.scala:289:{21,27,52}]
wire [4:0] exe_imm_data_lo_hi_hi = exe_imm_data_i10_5; // @[util.scala:289:21, :294:15]
wire [4:0] _exe_imm_data_i4_1_T_1 = exe_imm_data_ip[13:9]; // @[util.scala:282:17, :290:44]
wire [4:0] _exe_imm_data_i4_1_T_2 = _exe_imm_data_i4_1_T_1; // @[util.scala:290:{44,51}]
wire [4:0] exe_imm_data_i4_1 = _exe_imm_data_i4_1_T ? 5'h0 : _exe_imm_data_i4_1_T_2; // @[util.scala:290:{21,27,51}]
wire [4:0] exe_imm_data_lo_hi_lo = exe_imm_data_i4_1; // @[util.scala:290:21, :294:15]
wire _exe_imm_data_i0_T = rrd_uop_bits_imm_sel == 3'h1; // @[util.scala:291:27]
wire _exe_imm_data_i0_T_1 = rrd_uop_bits_imm_sel == 3'h0; // @[util.scala:291:44]
wire _exe_imm_data_i0_T_2 = _exe_imm_data_i0_T | _exe_imm_data_i0_T_1; // @[util.scala:291:{27,36,44}]
wire _exe_imm_data_i0_T_4 = _exe_imm_data_i0_T_3; // @[util.scala:291:{56,60}]
wire exe_imm_data_i0 = _exe_imm_data_i0_T_2 & _exe_imm_data_i0_T_4; // @[util.scala:291:{21,36,60}]
wire exe_imm_data_lo_lo = exe_imm_data_i0; // @[util.scala:291:21, :294:15]
wire [9:0] exe_imm_data_lo_hi = {exe_imm_data_lo_hi_hi, exe_imm_data_lo_hi_lo}; // @[util.scala:294:15]
wire [10:0] exe_imm_data_lo = {exe_imm_data_lo_hi, exe_imm_data_lo_lo}; // @[util.scala:294:15]
wire [8:0] exe_imm_data_hi_lo = {exe_imm_data_hi_lo_hi, exe_imm_data_hi_lo_lo}; // @[util.scala:294:15]
wire [11:0] exe_imm_data_hi_hi = {exe_imm_data_hi_hi_hi, exe_imm_data_hi_hi_lo}; // @[util.scala:294:15]
wire [20:0] exe_imm_data_hi = {exe_imm_data_hi_hi, exe_imm_data_hi_lo}; // @[util.scala:294:15]
wire [31:0] _exe_imm_data_T_4 = {exe_imm_data_hi, exe_imm_data_lo}; // @[util.scala:294:15]
wire _exe_imm_data_T_5 = _exe_imm_data_T_4[31]; // @[util.scala:269:46, :294:15]
wire [31:0] _exe_imm_data_T_6 = {32{_exe_imm_data_T_5}}; // @[util.scala:269:{25,46}]
wire [63:0] _exe_imm_data_T_7 = {_exe_imm_data_T_6, _exe_imm_data_T_4}; // @[util.scala:269:{20,25}, :294:15]
wire [63:0] _exe_imm_data_T_8 = _exe_imm_data_T ? _exe_imm_data_T_3 : _exe_imm_data_T_7; // @[util.scala:269:20]
reg [63:0] exe_imm_data; // @[execution-unit.scala:170:29]
wire _io_squash_iss_T = ~io_arb_irf_reqs_0_ready_0; // @[execution-unit.scala:255:7, :265:49]
assign _io_squash_iss_T_1 = io_arb_irf_reqs_0_valid_0 & _io_squash_iss_T; // @[execution-unit.scala:255:7, :265:{46,49}]
wire _will_replay_T_1 = |_will_replay_T; // @[util.scala:126:{51,59}]
wire _will_replay_T_2 = _will_replay_T_1 | io_kill; // @[util.scala:61:61, :126:59]
wire _will_replay_T_3 = ~_will_replay_T_2; // @[util.scala:61:61]
wire _will_replay_T_4 = arb_uop_valid & _will_replay_T_3; // @[execution-unit.scala:92:20, :268:{37,40}]
wire _will_replay_T_5 = ~arb_rebusied; // @[execution-unit.scala:130:45, :268:97]
wire will_replay = _will_replay_T_4 & _will_replay_T_5; // @[execution-unit.scala:268:{37,94,97}]
wire [15:0] _arb_uop_bits_out_br_mask_T_3; // @[util.scala:93:25]
wire [15:0] arb_uop_bits_out_1_br_mask; // @[util.scala:104:23]
wire [15:0] _arb_uop_bits_out_br_mask_T_2 = ~io_brupdate_b1_resolve_mask; // @[util.scala:93:27]
assign _arb_uop_bits_out_br_mask_T_3 = arb_uop_bits_br_mask & _arb_uop_bits_out_br_mask_T_2; // @[util.scala:93:{25,27}]
assign arb_uop_bits_out_1_br_mask = _arb_uop_bits_out_br_mask_T_3; // @[util.scala:93:25, :104:23]
wire _io_agen_T = exe_uop_valid & exe_uop_bits_fu_code_1; // @[execution-unit.scala:98:20, :311:28]
wire _io_agen_T_1 = ~_io_agen_T; // @[execution-unit.scala:311:{12,28}]
wire _io_agen_T_3 = ~_io_agen_T_2; // @[execution-unit.scala:311:11]
wire _io_agen_T_4 = ~_io_agen_T_1; // @[execution-unit.scala:311:{11,12}] |
Generate the Verilog code corresponding to this FIRRTL code module ICache_3 :
input clock : Clock
input reset : Reset
output auto : { master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<39>}}, flip s1_paddr : UInt<32>, flip s2_vaddr : UInt<39>, flip s1_kill : UInt<1>, flip s2_kill : UInt<1>, flip s2_cacheable : UInt<1>, flip s2_prefetch : UInt<1>, resp : { valid : UInt<1>, bits : { data : UInt<32>, replay : UInt<1>, ae : UInt<1>}}, flip invalidate : UInt<1>, errors : { bus : { valid : UInt<1>, bits : UInt<32>}}, perf : { acquire : UInt<1>}, flip clock_enabled : UInt<1>, keep_clock_enabled : UInt<1>}
wire masterNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate masterNodeOut.d.bits.corrupt
invalidate masterNodeOut.d.bits.data
invalidate masterNodeOut.d.bits.denied
invalidate masterNodeOut.d.bits.sink
invalidate masterNodeOut.d.bits.source
invalidate masterNodeOut.d.bits.size
invalidate masterNodeOut.d.bits.param
invalidate masterNodeOut.d.bits.opcode
invalidate masterNodeOut.d.valid
invalidate masterNodeOut.d.ready
invalidate masterNodeOut.a.bits.corrupt
invalidate masterNodeOut.a.bits.data
invalidate masterNodeOut.a.bits.mask
invalidate masterNodeOut.a.bits.address
invalidate masterNodeOut.a.bits.source
invalidate masterNodeOut.a.bits.size
invalidate masterNodeOut.a.bits.param
invalidate masterNodeOut.a.bits.opcode
invalidate masterNodeOut.a.valid
invalidate masterNodeOut.a.ready
connect auto.master_out, masterNodeOut
regreset scratchpadOn : UInt<1>, clock, reset, UInt<1>(0h0)
regreset s1_slaveValid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s1_slaveValid, UInt<1>(0h0)
regreset s2_slaveValid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s2_slaveValid, s1_slaveValid
reg s3_slaveValid : UInt<1>, clock
connect s3_slaveValid, UInt<1>(0h0)
node s0_valid = and(io.req.ready, io.req.valid)
regreset s1_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg s1_vaddr : UInt<39>, clock
when s0_valid :
connect s1_vaddr, io.req.bits.addr
wire s1_tag_hit : UInt<1>[8]
node _s1_hit_T = or(s1_tag_hit[0], s1_tag_hit[1])
node _s1_hit_T_1 = or(_s1_hit_T, s1_tag_hit[2])
node _s1_hit_T_2 = or(_s1_hit_T_1, s1_tag_hit[3])
node _s1_hit_T_3 = or(_s1_hit_T_2, s1_tag_hit[4])
node _s1_hit_T_4 = or(_s1_hit_T_3, s1_tag_hit[5])
node _s1_hit_T_5 = or(_s1_hit_T_4, s1_tag_hit[6])
node _s1_hit_T_6 = or(_s1_hit_T_5, s1_tag_hit[7])
node _s1_hit_T_7 = mux(s1_slaveValid, UInt<1>(0h1), UInt<1>(0h0))
node s1_hit = or(_s1_hit_T_6, _s1_hit_T_7)
node _s2_valid_T = eq(io.s1_kill, UInt<1>(0h0))
node _s2_valid_T_1 = and(s1_valid, _s2_valid_T)
regreset s2_valid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s2_valid, _s2_valid_T_1
reg s2_hit : UInt<1>, clock
connect s2_hit, s1_hit
reg invalidated : UInt<1>, clock
regreset refill_valid : UInt<1>, clock, reset, UInt<1>(0h0)
regreset send_hint : UInt<1>, clock, reset, UInt<1>(0h0)
node _refill_fire_T = and(masterNodeOut.a.ready, masterNodeOut.a.valid)
node _refill_fire_T_1 = eq(send_hint, UInt<1>(0h0))
node refill_fire = and(_refill_fire_T, _refill_fire_T_1)
regreset hint_outstanding : UInt<1>, clock, reset, UInt<1>(0h0)
node _s2_miss_T = eq(s2_hit, UInt<1>(0h0))
node _s2_miss_T_1 = and(s2_valid, _s2_miss_T)
node _s2_miss_T_2 = eq(io.s2_kill, UInt<1>(0h0))
node s2_miss = and(_s2_miss_T_1, _s2_miss_T_2)
node _s1_can_request_refill_T = or(s2_miss, refill_valid)
node s1_can_request_refill = eq(_s1_can_request_refill_T, UInt<1>(0h0))
reg s2_request_refill_REG : UInt<1>, clock
connect s2_request_refill_REG, s1_can_request_refill
node s2_request_refill = and(s2_miss, s2_request_refill_REG)
node _refill_paddr_T = and(s1_valid, s1_can_request_refill)
reg refill_paddr : UInt<32>, clock
when _refill_paddr_T :
connect refill_paddr, io.s1_paddr
node _refill_vaddr_T = and(s1_valid, s1_can_request_refill)
reg refill_vaddr : UInt<39>, clock
when _refill_vaddr_T :
connect refill_vaddr, s1_vaddr
node refill_tag = shr(refill_paddr, 12)
node refill_idx = bits(refill_paddr, 11, 6)
node _refill_one_beat_T = and(masterNodeOut.d.ready, masterNodeOut.d.valid)
node refill_one_beat_opdata = bits(masterNodeOut.d.bits.opcode, 0, 0)
node refill_one_beat = and(_refill_one_beat_T, refill_one_beat_opdata)
node _io_req_ready_T = or(refill_one_beat, UInt<1>(0h0))
node _io_req_ready_T_1 = or(_io_req_ready_T, s3_slaveValid)
node _io_req_ready_T_2 = eq(_io_req_ready_T_1, UInt<1>(0h0))
connect io.req.ready, _io_req_ready_T_2
connect s1_valid, s0_valid
node _T = and(masterNodeOut.d.ready, masterNodeOut.d.valid)
node _r_beats1_decode_T = dshl(UInt<12>(0hfff), masterNodeOut.d.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 3)
node r_beats1_opdata = bits(masterNodeOut.d.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node r_1 = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node r_2 = or(_r_last_T, _r_last_T_1)
node d_done = and(r_2, _T)
node _r_count_T = not(r_counter1)
node refill_cnt = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(r_1, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node refill_done = and(refill_one_beat, d_done)
node _masterNodeOut_d_ready_T = eq(s3_slaveValid, UInt<1>(0h0))
connect masterNodeOut.d.ready, _masterNodeOut_d_ready_T
inst repl_way_v0_prng of MaxPeriodFibonacciLFSR_8
connect repl_way_v0_prng.clock, clock
connect repl_way_v0_prng.reset, reset
connect repl_way_v0_prng.io.seed.valid, UInt<1>(0h0)
invalidate repl_way_v0_prng.io.seed.bits[0]
invalidate repl_way_v0_prng.io.seed.bits[1]
invalidate repl_way_v0_prng.io.seed.bits[2]
invalidate repl_way_v0_prng.io.seed.bits[3]
invalidate repl_way_v0_prng.io.seed.bits[4]
invalidate repl_way_v0_prng.io.seed.bits[5]
invalidate repl_way_v0_prng.io.seed.bits[6]
invalidate repl_way_v0_prng.io.seed.bits[7]
invalidate repl_way_v0_prng.io.seed.bits[8]
invalidate repl_way_v0_prng.io.seed.bits[9]
invalidate repl_way_v0_prng.io.seed.bits[10]
invalidate repl_way_v0_prng.io.seed.bits[11]
invalidate repl_way_v0_prng.io.seed.bits[12]
invalidate repl_way_v0_prng.io.seed.bits[13]
invalidate repl_way_v0_prng.io.seed.bits[14]
invalidate repl_way_v0_prng.io.seed.bits[15]
connect repl_way_v0_prng.io.increment, refill_fire
node repl_way_v0_lo_lo_lo = cat(repl_way_v0_prng.io.out[1], repl_way_v0_prng.io.out[0])
node repl_way_v0_lo_lo_hi = cat(repl_way_v0_prng.io.out[3], repl_way_v0_prng.io.out[2])
node repl_way_v0_lo_lo = cat(repl_way_v0_lo_lo_hi, repl_way_v0_lo_lo_lo)
node repl_way_v0_lo_hi_lo = cat(repl_way_v0_prng.io.out[5], repl_way_v0_prng.io.out[4])
node repl_way_v0_lo_hi_hi = cat(repl_way_v0_prng.io.out[7], repl_way_v0_prng.io.out[6])
node repl_way_v0_lo_hi = cat(repl_way_v0_lo_hi_hi, repl_way_v0_lo_hi_lo)
node repl_way_v0_lo = cat(repl_way_v0_lo_hi, repl_way_v0_lo_lo)
node repl_way_v0_hi_lo_lo = cat(repl_way_v0_prng.io.out[9], repl_way_v0_prng.io.out[8])
node repl_way_v0_hi_lo_hi = cat(repl_way_v0_prng.io.out[11], repl_way_v0_prng.io.out[10])
node repl_way_v0_hi_lo = cat(repl_way_v0_hi_lo_hi, repl_way_v0_hi_lo_lo)
node repl_way_v0_hi_hi_lo = cat(repl_way_v0_prng.io.out[13], repl_way_v0_prng.io.out[12])
node repl_way_v0_hi_hi_hi = cat(repl_way_v0_prng.io.out[15], repl_way_v0_prng.io.out[14])
node repl_way_v0_hi_hi = cat(repl_way_v0_hi_hi_hi, repl_way_v0_hi_hi_lo)
node repl_way_v0_hi = cat(repl_way_v0_hi_hi, repl_way_v0_hi_lo)
node _repl_way_v0_T = cat(repl_way_v0_hi, repl_way_v0_lo)
node repl_way_v0 = bits(_repl_way_v0_T, 2, 0)
node _repl_way_T = or(repl_way_v0, UInt<1>(0h0))
node _repl_way_T_1 = cat(_repl_way_T, refill_idx)
node _repl_way_T_2 = shl(UInt<1>(0h0), 2)
node _repl_way_T_3 = or(repl_way_v0, _repl_way_T_2)
node _repl_way_T_4 = or(repl_way_v0, UInt<3>(0h4))
node _repl_way_T_5 = cat(_repl_way_T_4, refill_idx)
node _repl_way_T_6 = shl(UInt<1>(0h0), 1)
node _repl_way_T_7 = or(_repl_way_T_3, _repl_way_T_6)
node _repl_way_T_8 = or(repl_way_v0, UInt<3>(0h6))
node _repl_way_T_9 = cat(_repl_way_T_8, refill_idx)
node _repl_way_T_10 = shl(UInt<1>(0h0), 0)
node repl_way = or(_repl_way_T_7, _repl_way_T_10)
node _repl_way_T_11 = cat(repl_way, refill_idx)
node _repl_way_T_12 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _repl_way_T_13 = asUInt(reset)
node _repl_way_T_14 = eq(_repl_way_T_13, UInt<1>(0h0))
when _repl_way_T_14 :
node _repl_way_T_15 = eq(_repl_way_T_12, UInt<1>(0h0))
when _repl_way_T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at ICache.scala:413 assert(!lineInScratchpad(Cat(v, refill_idx)))\n") : repl_way_printf
assert(clock, _repl_way_T_12, UInt<1>(0h1), "") : repl_way_assert
smem rockettile_icache_tag_array : UInt<21>[8] [64]
node _tag_rdata_T = bits(io.req.bits.addr, 11, 6)
node _tag_rdata_T_1 = eq(refill_done, UInt<1>(0h0))
node _tag_rdata_T_2 = and(_tag_rdata_T_1, s0_valid)
wire _tag_rdata_WIRE : UInt<6>
invalidate _tag_rdata_WIRE
when _tag_rdata_T_2 :
connect _tag_rdata_WIRE, _tag_rdata_T
read mport tag_rdata = rockettile_icache_tag_array[_tag_rdata_WIRE], clock
reg accruedRefillError : UInt<1>, clock
node _refillError_T = gt(refill_cnt, UInt<1>(0h0))
node _refillError_T_1 = and(_refillError_T, accruedRefillError)
node refillError = or(masterNodeOut.d.bits.corrupt, _refillError_T_1)
when refill_done :
node enc_tag = cat(refillError, refill_tag)
wire _WIRE : UInt<21>[8]
connect _WIRE[0], enc_tag
connect _WIRE[1], enc_tag
connect _WIRE[2], enc_tag
connect _WIRE[3], enc_tag
connect _WIRE[4], enc_tag
connect _WIRE[5], enc_tag
connect _WIRE[6], enc_tag
connect _WIRE[7], enc_tag
node _T_1 = eq(repl_way, UInt<1>(0h0))
node _T_2 = eq(repl_way, UInt<1>(0h1))
node _T_3 = eq(repl_way, UInt<2>(0h2))
node _T_4 = eq(repl_way, UInt<2>(0h3))
node _T_5 = eq(repl_way, UInt<3>(0h4))
node _T_6 = eq(repl_way, UInt<3>(0h5))
node _T_7 = eq(repl_way, UInt<3>(0h6))
node _T_8 = eq(repl_way, UInt<3>(0h7))
write mport MPORT = rockettile_icache_tag_array[refill_idx], clock
when _T_1 :
connect MPORT[0], _WIRE[0]
when _T_2 :
connect MPORT[1], _WIRE[1]
when _T_3 :
connect MPORT[2], _WIRE[2]
when _T_4 :
connect MPORT[3], _WIRE[3]
when _T_5 :
connect MPORT[4], _WIRE[4]
when _T_6 :
connect MPORT[5], _WIRE[5]
when _T_7 :
connect MPORT[6], _WIRE[6]
when _T_8 :
connect MPORT[7], _WIRE[7]
node _io_errors_bus_valid_T = and(masterNodeOut.d.ready, masterNodeOut.d.valid)
node _io_errors_bus_valid_T_1 = or(masterNodeOut.d.bits.denied, masterNodeOut.d.bits.corrupt)
node _io_errors_bus_valid_T_2 = and(_io_errors_bus_valid_T, _io_errors_bus_valid_T_1)
connect io.errors.bus.valid, _io_errors_bus_valid_T_2
node _io_errors_bus_bits_T = shr(refill_paddr, 6)
node _io_errors_bus_bits_T_1 = shl(_io_errors_bus_bits_T, 6)
connect io.errors.bus.bits, _io_errors_bus_bits_T_1
regreset vb_array : UInt<512>, clock, reset, UInt<512>(0h0)
when refill_one_beat :
connect accruedRefillError, refillError
node _vb_array_T = cat(repl_way, refill_idx)
node _vb_array_T_1 = eq(invalidated, UInt<1>(0h0))
node _vb_array_T_2 = and(refill_done, _vb_array_T_1)
node _vb_array_T_3 = dshl(UInt<1>(0h1), _vb_array_T)
node _vb_array_T_4 = or(vb_array, _vb_array_T_3)
node _vb_array_T_5 = not(vb_array)
node _vb_array_T_6 = or(_vb_array_T_5, _vb_array_T_3)
node _vb_array_T_7 = not(_vb_array_T_6)
node _vb_array_T_8 = mux(_vb_array_T_2, _vb_array_T_4, _vb_array_T_7)
connect vb_array, _vb_array_T_8
wire invalidate : UInt<1>
connect invalidate, io.invalidate
when invalidate :
connect vb_array, UInt<1>(0h0)
connect invalidated, UInt<1>(0h1)
wire s1_tag_disparity : UInt<1>[8]
wire s1_tl_error : UInt<1>[8]
wire s1_dout : UInt<32>[8]
invalidate s1_dout[0]
invalidate s1_dout[1]
invalidate s1_dout[2]
invalidate s1_dout[3]
invalidate s1_dout[4]
invalidate s1_dout[5]
invalidate s1_dout[6]
invalidate s1_dout[7]
reg s1s3_slaveAddr : UInt<15>, clock
reg s1s3_slaveData : UInt<32>, clock
node s1_idx = bits(io.s1_paddr, 11, 6)
node s1_tag = shr(io.s1_paddr, 12)
node _scratchpadHit_T = lt(UInt<1>(0h0), UInt<3>(0h7))
node _scratchpadHit_T_1 = bits(s1s3_slaveAddr, 14, 6)
node _scratchpadHit_T_2 = bits(s1s3_slaveAddr, 14, 12)
node _scratchpadHit_T_3 = eq(_scratchpadHit_T_2, UInt<1>(0h0))
node _scratchpadHit_T_4 = and(UInt<1>(0h0), _scratchpadHit_T_3)
node _scratchpadHit_T_5 = bits(io.s1_paddr, 14, 6)
node _scratchpadHit_T_6 = and(UInt<1>(0h0), UInt<1>(0h0))
node _scratchpadHit_T_7 = bits(io.s1_paddr, 14, 12)
node _scratchpadHit_T_8 = eq(_scratchpadHit_T_7, UInt<1>(0h0))
node _scratchpadHit_T_9 = and(_scratchpadHit_T_6, _scratchpadHit_T_8)
node _scratchpadHit_T_10 = mux(s1_slaveValid, _scratchpadHit_T_4, _scratchpadHit_T_9)
node scratchpadHit = and(_scratchpadHit_T, _scratchpadHit_T_10)
node _s1_vb_T = cat(UInt<1>(0h0), s1_idx)
node _s1_vb_T_1 = pad(_s1_vb_T, 9)
node _s1_vb_T_2 = dshr(vb_array, _s1_vb_T_1)
node _s1_vb_T_3 = bits(_s1_vb_T_2, 0, 0)
node _s1_vb_T_4 = eq(s1_slaveValid, UInt<1>(0h0))
node s1_vb = and(_s1_vb_T_3, _s1_vb_T_4)
node tl_error = bits(tag_rdata[0], 20, 20)
node tag = bits(tag_rdata[0], 19, 0)
node _tagMatch_T = eq(tag, s1_tag)
node tagMatch = and(s1_vb, _tagMatch_T)
node _s1_tag_disparity_0_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s1_tag_disparity_0_T_1 = and(s1_vb, _s1_tag_disparity_0_T)
connect s1_tag_disparity[0], _s1_tag_disparity_0_T_1
node _s1_tl_error_0_T = bits(tl_error, 0, 0)
node _s1_tl_error_0_T_1 = and(tagMatch, _s1_tl_error_0_T)
connect s1_tl_error[0], _s1_tl_error_0_T_1
node _s1_tag_hit_0_T = or(tagMatch, scratchpadHit)
connect s1_tag_hit[0], _s1_tag_hit_0_T
node s1_idx_1 = bits(io.s1_paddr, 11, 6)
node s1_tag_1 = shr(io.s1_paddr, 12)
node _scratchpadHit_T_11 = lt(UInt<1>(0h1), UInt<3>(0h7))
node _scratchpadHit_T_12 = bits(s1s3_slaveAddr, 14, 6)
node _scratchpadHit_T_13 = bits(s1s3_slaveAddr, 14, 12)
node _scratchpadHit_T_14 = eq(_scratchpadHit_T_13, UInt<1>(0h1))
node _scratchpadHit_T_15 = and(UInt<1>(0h0), _scratchpadHit_T_14)
node _scratchpadHit_T_16 = bits(io.s1_paddr, 14, 6)
node _scratchpadHit_T_17 = and(UInt<1>(0h0), UInt<1>(0h0))
node _scratchpadHit_T_18 = bits(io.s1_paddr, 14, 12)
node _scratchpadHit_T_19 = eq(_scratchpadHit_T_18, UInt<1>(0h1))
node _scratchpadHit_T_20 = and(_scratchpadHit_T_17, _scratchpadHit_T_19)
node _scratchpadHit_T_21 = mux(s1_slaveValid, _scratchpadHit_T_15, _scratchpadHit_T_20)
node scratchpadHit_1 = and(_scratchpadHit_T_11, _scratchpadHit_T_21)
node _s1_vb_T_5 = cat(UInt<1>(0h1), s1_idx_1)
node _s1_vb_T_6 = pad(_s1_vb_T_5, 9)
node _s1_vb_T_7 = dshr(vb_array, _s1_vb_T_6)
node _s1_vb_T_8 = bits(_s1_vb_T_7, 0, 0)
node _s1_vb_T_9 = eq(s1_slaveValid, UInt<1>(0h0))
node s1_vb_1 = and(_s1_vb_T_8, _s1_vb_T_9)
node tl_error_1 = bits(tag_rdata[1], 20, 20)
node tag_1 = bits(tag_rdata[1], 19, 0)
node _tagMatch_T_1 = eq(tag_1, s1_tag_1)
node tagMatch_1 = and(s1_vb_1, _tagMatch_T_1)
node _s1_tag_disparity_1_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s1_tag_disparity_1_T_1 = and(s1_vb_1, _s1_tag_disparity_1_T)
connect s1_tag_disparity[1], _s1_tag_disparity_1_T_1
node _s1_tl_error_1_T = bits(tl_error_1, 0, 0)
node _s1_tl_error_1_T_1 = and(tagMatch_1, _s1_tl_error_1_T)
connect s1_tl_error[1], _s1_tl_error_1_T_1
node _s1_tag_hit_1_T = or(tagMatch_1, scratchpadHit_1)
connect s1_tag_hit[1], _s1_tag_hit_1_T
node s1_idx_2 = bits(io.s1_paddr, 11, 6)
node s1_tag_2 = shr(io.s1_paddr, 12)
node _scratchpadHit_T_22 = lt(UInt<2>(0h2), UInt<3>(0h7))
node _scratchpadHit_T_23 = bits(s1s3_slaveAddr, 14, 6)
node _scratchpadHit_T_24 = bits(s1s3_slaveAddr, 14, 12)
node _scratchpadHit_T_25 = eq(_scratchpadHit_T_24, UInt<2>(0h2))
node _scratchpadHit_T_26 = and(UInt<1>(0h0), _scratchpadHit_T_25)
node _scratchpadHit_T_27 = bits(io.s1_paddr, 14, 6)
node _scratchpadHit_T_28 = and(UInt<1>(0h0), UInt<1>(0h0))
node _scratchpadHit_T_29 = bits(io.s1_paddr, 14, 12)
node _scratchpadHit_T_30 = eq(_scratchpadHit_T_29, UInt<2>(0h2))
node _scratchpadHit_T_31 = and(_scratchpadHit_T_28, _scratchpadHit_T_30)
node _scratchpadHit_T_32 = mux(s1_slaveValid, _scratchpadHit_T_26, _scratchpadHit_T_31)
node scratchpadHit_2 = and(_scratchpadHit_T_22, _scratchpadHit_T_32)
node _s1_vb_T_10 = cat(UInt<2>(0h2), s1_idx_2)
node _s1_vb_T_11 = pad(_s1_vb_T_10, 9)
node _s1_vb_T_12 = dshr(vb_array, _s1_vb_T_11)
node _s1_vb_T_13 = bits(_s1_vb_T_12, 0, 0)
node _s1_vb_T_14 = eq(s1_slaveValid, UInt<1>(0h0))
node s1_vb_2 = and(_s1_vb_T_13, _s1_vb_T_14)
node tl_error_2 = bits(tag_rdata[2], 20, 20)
node tag_2 = bits(tag_rdata[2], 19, 0)
node _tagMatch_T_2 = eq(tag_2, s1_tag_2)
node tagMatch_2 = and(s1_vb_2, _tagMatch_T_2)
node _s1_tag_disparity_2_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s1_tag_disparity_2_T_1 = and(s1_vb_2, _s1_tag_disparity_2_T)
connect s1_tag_disparity[2], _s1_tag_disparity_2_T_1
node _s1_tl_error_2_T = bits(tl_error_2, 0, 0)
node _s1_tl_error_2_T_1 = and(tagMatch_2, _s1_tl_error_2_T)
connect s1_tl_error[2], _s1_tl_error_2_T_1
node _s1_tag_hit_2_T = or(tagMatch_2, scratchpadHit_2)
connect s1_tag_hit[2], _s1_tag_hit_2_T
node s1_idx_3 = bits(io.s1_paddr, 11, 6)
node s1_tag_3 = shr(io.s1_paddr, 12)
node _scratchpadHit_T_33 = lt(UInt<2>(0h3), UInt<3>(0h7))
node _scratchpadHit_T_34 = bits(s1s3_slaveAddr, 14, 6)
node _scratchpadHit_T_35 = bits(s1s3_slaveAddr, 14, 12)
node _scratchpadHit_T_36 = eq(_scratchpadHit_T_35, UInt<2>(0h3))
node _scratchpadHit_T_37 = and(UInt<1>(0h0), _scratchpadHit_T_36)
node _scratchpadHit_T_38 = bits(io.s1_paddr, 14, 6)
node _scratchpadHit_T_39 = and(UInt<1>(0h0), UInt<1>(0h0))
node _scratchpadHit_T_40 = bits(io.s1_paddr, 14, 12)
node _scratchpadHit_T_41 = eq(_scratchpadHit_T_40, UInt<2>(0h3))
node _scratchpadHit_T_42 = and(_scratchpadHit_T_39, _scratchpadHit_T_41)
node _scratchpadHit_T_43 = mux(s1_slaveValid, _scratchpadHit_T_37, _scratchpadHit_T_42)
node scratchpadHit_3 = and(_scratchpadHit_T_33, _scratchpadHit_T_43)
node _s1_vb_T_15 = cat(UInt<2>(0h3), s1_idx_3)
node _s1_vb_T_16 = pad(_s1_vb_T_15, 9)
node _s1_vb_T_17 = dshr(vb_array, _s1_vb_T_16)
node _s1_vb_T_18 = bits(_s1_vb_T_17, 0, 0)
node _s1_vb_T_19 = eq(s1_slaveValid, UInt<1>(0h0))
node s1_vb_3 = and(_s1_vb_T_18, _s1_vb_T_19)
node tl_error_3 = bits(tag_rdata[3], 20, 20)
node tag_3 = bits(tag_rdata[3], 19, 0)
node _tagMatch_T_3 = eq(tag_3, s1_tag_3)
node tagMatch_3 = and(s1_vb_3, _tagMatch_T_3)
node _s1_tag_disparity_3_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s1_tag_disparity_3_T_1 = and(s1_vb_3, _s1_tag_disparity_3_T)
connect s1_tag_disparity[3], _s1_tag_disparity_3_T_1
node _s1_tl_error_3_T = bits(tl_error_3, 0, 0)
node _s1_tl_error_3_T_1 = and(tagMatch_3, _s1_tl_error_3_T)
connect s1_tl_error[3], _s1_tl_error_3_T_1
node _s1_tag_hit_3_T = or(tagMatch_3, scratchpadHit_3)
connect s1_tag_hit[3], _s1_tag_hit_3_T
node s1_idx_4 = bits(io.s1_paddr, 11, 6)
node s1_tag_4 = shr(io.s1_paddr, 12)
node _scratchpadHit_T_44 = lt(UInt<3>(0h4), UInt<3>(0h7))
node _scratchpadHit_T_45 = bits(s1s3_slaveAddr, 14, 6)
node _scratchpadHit_T_46 = bits(s1s3_slaveAddr, 14, 12)
node _scratchpadHit_T_47 = eq(_scratchpadHit_T_46, UInt<3>(0h4))
node _scratchpadHit_T_48 = and(UInt<1>(0h0), _scratchpadHit_T_47)
node _scratchpadHit_T_49 = bits(io.s1_paddr, 14, 6)
node _scratchpadHit_T_50 = and(UInt<1>(0h0), UInt<1>(0h0))
node _scratchpadHit_T_51 = bits(io.s1_paddr, 14, 12)
node _scratchpadHit_T_52 = eq(_scratchpadHit_T_51, UInt<3>(0h4))
node _scratchpadHit_T_53 = and(_scratchpadHit_T_50, _scratchpadHit_T_52)
node _scratchpadHit_T_54 = mux(s1_slaveValid, _scratchpadHit_T_48, _scratchpadHit_T_53)
node scratchpadHit_4 = and(_scratchpadHit_T_44, _scratchpadHit_T_54)
node _s1_vb_T_20 = cat(UInt<3>(0h4), s1_idx_4)
node _s1_vb_T_21 = dshr(vb_array, _s1_vb_T_20)
node _s1_vb_T_22 = bits(_s1_vb_T_21, 0, 0)
node _s1_vb_T_23 = eq(s1_slaveValid, UInt<1>(0h0))
node s1_vb_4 = and(_s1_vb_T_22, _s1_vb_T_23)
node tl_error_4 = bits(tag_rdata[4], 20, 20)
node tag_4 = bits(tag_rdata[4], 19, 0)
node _tagMatch_T_4 = eq(tag_4, s1_tag_4)
node tagMatch_4 = and(s1_vb_4, _tagMatch_T_4)
node _s1_tag_disparity_4_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s1_tag_disparity_4_T_1 = and(s1_vb_4, _s1_tag_disparity_4_T)
connect s1_tag_disparity[4], _s1_tag_disparity_4_T_1
node _s1_tl_error_4_T = bits(tl_error_4, 0, 0)
node _s1_tl_error_4_T_1 = and(tagMatch_4, _s1_tl_error_4_T)
connect s1_tl_error[4], _s1_tl_error_4_T_1
node _s1_tag_hit_4_T = or(tagMatch_4, scratchpadHit_4)
connect s1_tag_hit[4], _s1_tag_hit_4_T
node s1_idx_5 = bits(io.s1_paddr, 11, 6)
node s1_tag_5 = shr(io.s1_paddr, 12)
node _scratchpadHit_T_55 = lt(UInt<3>(0h5), UInt<3>(0h7))
node _scratchpadHit_T_56 = bits(s1s3_slaveAddr, 14, 6)
node _scratchpadHit_T_57 = bits(s1s3_slaveAddr, 14, 12)
node _scratchpadHit_T_58 = eq(_scratchpadHit_T_57, UInt<3>(0h5))
node _scratchpadHit_T_59 = and(UInt<1>(0h0), _scratchpadHit_T_58)
node _scratchpadHit_T_60 = bits(io.s1_paddr, 14, 6)
node _scratchpadHit_T_61 = and(UInt<1>(0h0), UInt<1>(0h0))
node _scratchpadHit_T_62 = bits(io.s1_paddr, 14, 12)
node _scratchpadHit_T_63 = eq(_scratchpadHit_T_62, UInt<3>(0h5))
node _scratchpadHit_T_64 = and(_scratchpadHit_T_61, _scratchpadHit_T_63)
node _scratchpadHit_T_65 = mux(s1_slaveValid, _scratchpadHit_T_59, _scratchpadHit_T_64)
node scratchpadHit_5 = and(_scratchpadHit_T_55, _scratchpadHit_T_65)
node _s1_vb_T_24 = cat(UInt<3>(0h5), s1_idx_5)
node _s1_vb_T_25 = dshr(vb_array, _s1_vb_T_24)
node _s1_vb_T_26 = bits(_s1_vb_T_25, 0, 0)
node _s1_vb_T_27 = eq(s1_slaveValid, UInt<1>(0h0))
node s1_vb_5 = and(_s1_vb_T_26, _s1_vb_T_27)
node tl_error_5 = bits(tag_rdata[5], 20, 20)
node tag_5 = bits(tag_rdata[5], 19, 0)
node _tagMatch_T_5 = eq(tag_5, s1_tag_5)
node tagMatch_5 = and(s1_vb_5, _tagMatch_T_5)
node _s1_tag_disparity_5_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s1_tag_disparity_5_T_1 = and(s1_vb_5, _s1_tag_disparity_5_T)
connect s1_tag_disparity[5], _s1_tag_disparity_5_T_1
node _s1_tl_error_5_T = bits(tl_error_5, 0, 0)
node _s1_tl_error_5_T_1 = and(tagMatch_5, _s1_tl_error_5_T)
connect s1_tl_error[5], _s1_tl_error_5_T_1
node _s1_tag_hit_5_T = or(tagMatch_5, scratchpadHit_5)
connect s1_tag_hit[5], _s1_tag_hit_5_T
node s1_idx_6 = bits(io.s1_paddr, 11, 6)
node s1_tag_6 = shr(io.s1_paddr, 12)
node _scratchpadHit_T_66 = lt(UInt<3>(0h6), UInt<3>(0h7))
node _scratchpadHit_T_67 = bits(s1s3_slaveAddr, 14, 6)
node _scratchpadHit_T_68 = bits(s1s3_slaveAddr, 14, 12)
node _scratchpadHit_T_69 = eq(_scratchpadHit_T_68, UInt<3>(0h6))
node _scratchpadHit_T_70 = and(UInt<1>(0h0), _scratchpadHit_T_69)
node _scratchpadHit_T_71 = bits(io.s1_paddr, 14, 6)
node _scratchpadHit_T_72 = and(UInt<1>(0h0), UInt<1>(0h0))
node _scratchpadHit_T_73 = bits(io.s1_paddr, 14, 12)
node _scratchpadHit_T_74 = eq(_scratchpadHit_T_73, UInt<3>(0h6))
node _scratchpadHit_T_75 = and(_scratchpadHit_T_72, _scratchpadHit_T_74)
node _scratchpadHit_T_76 = mux(s1_slaveValid, _scratchpadHit_T_70, _scratchpadHit_T_75)
node scratchpadHit_6 = and(_scratchpadHit_T_66, _scratchpadHit_T_76)
node _s1_vb_T_28 = cat(UInt<3>(0h6), s1_idx_6)
node _s1_vb_T_29 = dshr(vb_array, _s1_vb_T_28)
node _s1_vb_T_30 = bits(_s1_vb_T_29, 0, 0)
node _s1_vb_T_31 = eq(s1_slaveValid, UInt<1>(0h0))
node s1_vb_6 = and(_s1_vb_T_30, _s1_vb_T_31)
node tl_error_6 = bits(tag_rdata[6], 20, 20)
node tag_6 = bits(tag_rdata[6], 19, 0)
node _tagMatch_T_6 = eq(tag_6, s1_tag_6)
node tagMatch_6 = and(s1_vb_6, _tagMatch_T_6)
node _s1_tag_disparity_6_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s1_tag_disparity_6_T_1 = and(s1_vb_6, _s1_tag_disparity_6_T)
connect s1_tag_disparity[6], _s1_tag_disparity_6_T_1
node _s1_tl_error_6_T = bits(tl_error_6, 0, 0)
node _s1_tl_error_6_T_1 = and(tagMatch_6, _s1_tl_error_6_T)
connect s1_tl_error[6], _s1_tl_error_6_T_1
node _s1_tag_hit_6_T = or(tagMatch_6, scratchpadHit_6)
connect s1_tag_hit[6], _s1_tag_hit_6_T
node s1_idx_7 = bits(io.s1_paddr, 11, 6)
node s1_tag_7 = shr(io.s1_paddr, 12)
node _scratchpadHit_T_77 = lt(UInt<3>(0h7), UInt<3>(0h7))
node _scratchpadHit_T_78 = bits(s1s3_slaveAddr, 14, 6)
node _scratchpadHit_T_79 = bits(s1s3_slaveAddr, 14, 12)
node _scratchpadHit_T_80 = eq(_scratchpadHit_T_79, UInt<3>(0h7))
node _scratchpadHit_T_81 = and(UInt<1>(0h0), _scratchpadHit_T_80)
node _scratchpadHit_T_82 = bits(io.s1_paddr, 14, 6)
node _scratchpadHit_T_83 = and(UInt<1>(0h0), UInt<1>(0h0))
node _scratchpadHit_T_84 = bits(io.s1_paddr, 14, 12)
node _scratchpadHit_T_85 = eq(_scratchpadHit_T_84, UInt<3>(0h7))
node _scratchpadHit_T_86 = and(_scratchpadHit_T_83, _scratchpadHit_T_85)
node _scratchpadHit_T_87 = mux(s1_slaveValid, _scratchpadHit_T_81, _scratchpadHit_T_86)
node scratchpadHit_7 = and(_scratchpadHit_T_77, _scratchpadHit_T_87)
node _s1_vb_T_32 = cat(UInt<3>(0h7), s1_idx_7)
node _s1_vb_T_33 = dshr(vb_array, _s1_vb_T_32)
node _s1_vb_T_34 = bits(_s1_vb_T_33, 0, 0)
node _s1_vb_T_35 = eq(s1_slaveValid, UInt<1>(0h0))
node s1_vb_7 = and(_s1_vb_T_34, _s1_vb_T_35)
node tl_error_7 = bits(tag_rdata[7], 20, 20)
node tag_7 = bits(tag_rdata[7], 19, 0)
node _tagMatch_T_7 = eq(tag_7, s1_tag_7)
node tagMatch_7 = and(s1_vb_7, _tagMatch_T_7)
node _s1_tag_disparity_7_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s1_tag_disparity_7_T_1 = and(s1_vb_7, _s1_tag_disparity_7_T)
connect s1_tag_disparity[7], _s1_tag_disparity_7_T_1
node _s1_tl_error_7_T = bits(tl_error_7, 0, 0)
node _s1_tl_error_7_T_1 = and(tagMatch_7, _s1_tl_error_7_T)
connect s1_tl_error[7], _s1_tl_error_7_T_1
node _s1_tag_hit_7_T = or(tagMatch_7, scratchpadHit_7)
connect s1_tag_hit[7], _s1_tag_hit_7_T
node _T_9 = or(s1_valid, s1_slaveValid)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = eq(s1_tag_disparity[0], UInt<1>(0h0))
node _T_12 = and(s1_tag_hit[0], _T_11)
node _T_13 = eq(s1_tag_disparity[1], UInt<1>(0h0))
node _T_14 = and(s1_tag_hit[1], _T_13)
node _T_15 = eq(s1_tag_disparity[2], UInt<1>(0h0))
node _T_16 = and(s1_tag_hit[2], _T_15)
node _T_17 = eq(s1_tag_disparity[3], UInt<1>(0h0))
node _T_18 = and(s1_tag_hit[3], _T_17)
node _T_19 = eq(s1_tag_disparity[4], UInt<1>(0h0))
node _T_20 = and(s1_tag_hit[4], _T_19)
node _T_21 = eq(s1_tag_disparity[5], UInt<1>(0h0))
node _T_22 = and(s1_tag_hit[5], _T_21)
node _T_23 = eq(s1_tag_disparity[6], UInt<1>(0h0))
node _T_24 = and(s1_tag_hit[6], _T_23)
node _T_25 = eq(s1_tag_disparity[7], UInt<1>(0h0))
node _T_26 = and(s1_tag_hit[7], _T_25)
node _T_27 = add(_T_12, _T_14)
node _T_28 = bits(_T_27, 1, 0)
node _T_29 = add(_T_16, _T_18)
node _T_30 = bits(_T_29, 1, 0)
node _T_31 = add(_T_28, _T_30)
node _T_32 = bits(_T_31, 2, 0)
node _T_33 = add(_T_20, _T_22)
node _T_34 = bits(_T_33, 1, 0)
node _T_35 = add(_T_24, _T_26)
node _T_36 = bits(_T_35, 1, 0)
node _T_37 = add(_T_34, _T_36)
node _T_38 = bits(_T_37, 2, 0)
node _T_39 = add(_T_32, _T_38)
node _T_40 = bits(_T_39, 3, 0)
node _T_41 = leq(_T_40, UInt<1>(0h1))
node _T_42 = or(_T_10, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at ICache.scala:521 assert(!(s1_valid || s1_slaveValid) || PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1.U)\n") : printf
assert(clock, _T_42, UInt<1>(0h1), "") : assert
smem rockettile_icache_data_arrays_0 : UInt<32>[8] [512]
smem rockettile_icache_data_arrays_1 : UInt<32>[8] [512]
node _s0_ren_T = bits(io.req.bits.addr, 2, 2)
node _s0_ren_T_1 = eq(_s0_ren_T, UInt<1>(0h0))
node _s0_ren_T_2 = and(s0_valid, _s0_ren_T_1)
node _s0_ren_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _s0_ren_T_4 = and(UInt<1>(0h0), _s0_ren_T_3)
node s0_ren = or(_s0_ren_T_2, _s0_ren_T_4)
node _wen_T = eq(invalidated, UInt<1>(0h0))
node _wen_T_1 = and(refill_one_beat, _wen_T)
node _wen_T_2 = bits(s1s3_slaveAddr, 2, 2)
node _wen_T_3 = eq(_wen_T_2, UInt<1>(0h0))
node _wen_T_4 = and(s3_slaveValid, _wen_T_3)
node wen = or(_wen_T_1, _wen_T_4)
node _mem_idx_T = shl(refill_idx, 3)
node _mem_idx_T_1 = or(_mem_idx_T, refill_cnt)
node _mem_idx_T_2 = bits(s1s3_slaveAddr, 11, 3)
node _mem_idx_T_3 = bits(io.req.bits.addr, 11, 3)
node _mem_idx_T_4 = mux(UInt<1>(0h0), UInt<9>(0h0), _mem_idx_T_3)
node _mem_idx_T_5 = mux(s3_slaveValid, _mem_idx_T_2, _mem_idx_T_4)
node mem_idx = mux(refill_one_beat, _mem_idx_T_1, _mem_idx_T_5)
when wen :
node _data_T = bits(masterNodeOut.d.bits.data, 31, 0)
node data = mux(s3_slaveValid, s1s3_slaveData, _data_T)
node _way_T = bits(s1s3_slaveAddr, 14, 12)
node way = mux(s3_slaveValid, _way_T, repl_way)
wire _WIRE_1 : UInt<32>[8]
connect _WIRE_1[0], data
connect _WIRE_1[1], data
connect _WIRE_1[2], data
connect _WIRE_1[3], data
connect _WIRE_1[4], data
connect _WIRE_1[5], data
connect _WIRE_1[6], data
connect _WIRE_1[7], data
node _T_46 = eq(way, UInt<1>(0h0))
node _T_47 = eq(way, UInt<1>(0h1))
node _T_48 = eq(way, UInt<2>(0h2))
node _T_49 = eq(way, UInt<2>(0h3))
node _T_50 = eq(way, UInt<3>(0h4))
node _T_51 = eq(way, UInt<3>(0h5))
node _T_52 = eq(way, UInt<3>(0h6))
node _T_53 = eq(way, UInt<3>(0h7))
write mport MPORT_1 = rockettile_icache_data_arrays_0[mem_idx], clock
when _T_46 :
connect MPORT_1[0], _WIRE_1[0]
when _T_47 :
connect MPORT_1[1], _WIRE_1[1]
when _T_48 :
connect MPORT_1[2], _WIRE_1[2]
when _T_49 :
connect MPORT_1[3], _WIRE_1[3]
when _T_50 :
connect MPORT_1[4], _WIRE_1[4]
when _T_51 :
connect MPORT_1[5], _WIRE_1[5]
when _T_52 :
connect MPORT_1[6], _WIRE_1[6]
when _T_53 :
connect MPORT_1[7], _WIRE_1[7]
node _dout_T = eq(wen, UInt<1>(0h0))
node _dout_T_1 = and(_dout_T, s0_ren)
wire _dout_WIRE : UInt<9>
invalidate _dout_WIRE
when _dout_T_1 :
connect _dout_WIRE, mem_idx
read mport dout = rockettile_icache_data_arrays_0[_dout_WIRE], clock
node _T_54 = mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr)
node _T_55 = bits(_T_54, 2, 2)
node _T_56 = eq(_T_55, UInt<1>(0h0))
when _T_56 :
connect s1_dout, dout
node _s0_ren_T_5 = bits(io.req.bits.addr, 2, 2)
node _s0_ren_T_6 = eq(_s0_ren_T_5, UInt<1>(0h1))
node _s0_ren_T_7 = and(s0_valid, _s0_ren_T_6)
node _s0_ren_T_8 = eq(UInt<1>(0h0), UInt<1>(0h1))
node _s0_ren_T_9 = and(UInt<1>(0h0), _s0_ren_T_8)
node s0_ren_1 = or(_s0_ren_T_7, _s0_ren_T_9)
node _wen_T_5 = eq(invalidated, UInt<1>(0h0))
node _wen_T_6 = and(refill_one_beat, _wen_T_5)
node _wen_T_7 = bits(s1s3_slaveAddr, 2, 2)
node _wen_T_8 = eq(_wen_T_7, UInt<1>(0h1))
node _wen_T_9 = and(s3_slaveValid, _wen_T_8)
node wen_1 = or(_wen_T_6, _wen_T_9)
node _mem_idx_T_6 = shl(refill_idx, 3)
node _mem_idx_T_7 = or(_mem_idx_T_6, refill_cnt)
node _mem_idx_T_8 = bits(s1s3_slaveAddr, 11, 3)
node _mem_idx_T_9 = bits(io.req.bits.addr, 11, 3)
node _mem_idx_T_10 = mux(UInt<1>(0h0), UInt<9>(0h0), _mem_idx_T_9)
node _mem_idx_T_11 = mux(s3_slaveValid, _mem_idx_T_8, _mem_idx_T_10)
node mem_idx_1 = mux(refill_one_beat, _mem_idx_T_7, _mem_idx_T_11)
when wen_1 :
node _data_T_1 = bits(masterNodeOut.d.bits.data, 63, 32)
node data_1 = mux(s3_slaveValid, s1s3_slaveData, _data_T_1)
node _way_T_1 = bits(s1s3_slaveAddr, 14, 12)
node way_1 = mux(s3_slaveValid, _way_T_1, repl_way)
wire _WIRE_2 : UInt<32>[8]
connect _WIRE_2[0], data_1
connect _WIRE_2[1], data_1
connect _WIRE_2[2], data_1
connect _WIRE_2[3], data_1
connect _WIRE_2[4], data_1
connect _WIRE_2[5], data_1
connect _WIRE_2[6], data_1
connect _WIRE_2[7], data_1
node _T_57 = eq(way_1, UInt<1>(0h0))
node _T_58 = eq(way_1, UInt<1>(0h1))
node _T_59 = eq(way_1, UInt<2>(0h2))
node _T_60 = eq(way_1, UInt<2>(0h3))
node _T_61 = eq(way_1, UInt<3>(0h4))
node _T_62 = eq(way_1, UInt<3>(0h5))
node _T_63 = eq(way_1, UInt<3>(0h6))
node _T_64 = eq(way_1, UInt<3>(0h7))
write mport MPORT_2 = rockettile_icache_data_arrays_1[mem_idx_1], clock
when _T_57 :
connect MPORT_2[0], _WIRE_2[0]
when _T_58 :
connect MPORT_2[1], _WIRE_2[1]
when _T_59 :
connect MPORT_2[2], _WIRE_2[2]
when _T_60 :
connect MPORT_2[3], _WIRE_2[3]
when _T_61 :
connect MPORT_2[4], _WIRE_2[4]
when _T_62 :
connect MPORT_2[5], _WIRE_2[5]
when _T_63 :
connect MPORT_2[6], _WIRE_2[6]
when _T_64 :
connect MPORT_2[7], _WIRE_2[7]
node _dout_T_2 = eq(wen_1, UInt<1>(0h0))
node _dout_T_3 = and(_dout_T_2, s0_ren_1)
wire _dout_WIRE_1 : UInt<9>
invalidate _dout_WIRE_1
when _dout_T_3 :
connect _dout_WIRE_1, mem_idx_1
read mport dout_1 = rockettile_icache_data_arrays_1[_dout_WIRE_1], clock
node _T_65 = mux(s1_slaveValid, s1s3_slaveAddr, io.s1_paddr)
node _T_66 = bits(_T_65, 2, 2)
node _T_67 = eq(_T_66, UInt<1>(0h1))
when _T_67 :
connect s1_dout, dout_1
wire s1s2_full_word_write : UInt<1>
connect s1s2_full_word_write, UInt<1>(0h0)
node s1_dont_read = and(s1_slaveValid, s1s2_full_word_write)
node s1_clk_en = or(s1_valid, s1_slaveValid)
wire _s2_tag_hit_WIRE : UInt<1>[8]
connect _s2_tag_hit_WIRE[0], UInt<1>(0h0)
connect _s2_tag_hit_WIRE[1], UInt<1>(0h0)
connect _s2_tag_hit_WIRE[2], UInt<1>(0h0)
connect _s2_tag_hit_WIRE[3], UInt<1>(0h0)
connect _s2_tag_hit_WIRE[4], UInt<1>(0h0)
connect _s2_tag_hit_WIRE[5], UInt<1>(0h0)
connect _s2_tag_hit_WIRE[6], UInt<1>(0h0)
connect _s2_tag_hit_WIRE[7], UInt<1>(0h0)
node _s2_tag_hit_T = mux(s1_dont_read, _s2_tag_hit_WIRE, s1_tag_hit)
reg s2_tag_hit : UInt<1>[8], clock
when s1_clk_en :
connect s2_tag_hit, _s2_tag_hit_T
node s2_hit_way_lo_lo = cat(s2_tag_hit[1], s2_tag_hit[0])
node s2_hit_way_lo_hi = cat(s2_tag_hit[3], s2_tag_hit[2])
node s2_hit_way_lo = cat(s2_hit_way_lo_hi, s2_hit_way_lo_lo)
node s2_hit_way_hi_lo = cat(s2_tag_hit[5], s2_tag_hit[4])
node s2_hit_way_hi_hi = cat(s2_tag_hit[7], s2_tag_hit[6])
node s2_hit_way_hi = cat(s2_hit_way_hi_hi, s2_hit_way_hi_lo)
node _s2_hit_way_T = cat(s2_hit_way_hi, s2_hit_way_lo)
node s2_hit_way_hi_1 = bits(_s2_hit_way_T, 7, 4)
node s2_hit_way_lo_1 = bits(_s2_hit_way_T, 3, 0)
node _s2_hit_way_T_1 = orr(s2_hit_way_hi_1)
node _s2_hit_way_T_2 = or(s2_hit_way_hi_1, s2_hit_way_lo_1)
node s2_hit_way_hi_2 = bits(_s2_hit_way_T_2, 3, 2)
node s2_hit_way_lo_2 = bits(_s2_hit_way_T_2, 1, 0)
node _s2_hit_way_T_3 = orr(s2_hit_way_hi_2)
node _s2_hit_way_T_4 = or(s2_hit_way_hi_2, s2_hit_way_lo_2)
node _s2_hit_way_T_5 = bits(_s2_hit_way_T_4, 1, 1)
node _s2_hit_way_T_6 = cat(_s2_hit_way_T_3, _s2_hit_way_T_5)
node s2_hit_way = cat(_s2_hit_way_T_1, _s2_hit_way_T_6)
node _s2_scratchpad_word_addr_T = mux(s2_slaveValid, s1s3_slaveAddr, io.s2_vaddr)
node _s2_scratchpad_word_addr_T_1 = bits(_s2_scratchpad_word_addr_T, 11, 2)
node s2_scratchpad_word_addr_hi = cat(s2_hit_way, _s2_scratchpad_word_addr_T_1)
node s2_scratchpad_word_addr = cat(s2_scratchpad_word_addr_hi, UInt<2>(0h0))
reg s2_dout : UInt<32>[8], clock
when s1_clk_en :
connect s2_dout, s1_dout
node _s2_way_mux_T = mux(s2_tag_hit[0], s2_dout[0], UInt<1>(0h0))
node _s2_way_mux_T_1 = mux(s2_tag_hit[1], s2_dout[1], UInt<1>(0h0))
node _s2_way_mux_T_2 = mux(s2_tag_hit[2], s2_dout[2], UInt<1>(0h0))
node _s2_way_mux_T_3 = mux(s2_tag_hit[3], s2_dout[3], UInt<1>(0h0))
node _s2_way_mux_T_4 = mux(s2_tag_hit[4], s2_dout[4], UInt<1>(0h0))
node _s2_way_mux_T_5 = mux(s2_tag_hit[5], s2_dout[5], UInt<1>(0h0))
node _s2_way_mux_T_6 = mux(s2_tag_hit[6], s2_dout[6], UInt<1>(0h0))
node _s2_way_mux_T_7 = mux(s2_tag_hit[7], s2_dout[7], UInt<1>(0h0))
node _s2_way_mux_T_8 = or(_s2_way_mux_T, _s2_way_mux_T_1)
node _s2_way_mux_T_9 = or(_s2_way_mux_T_8, _s2_way_mux_T_2)
node _s2_way_mux_T_10 = or(_s2_way_mux_T_9, _s2_way_mux_T_3)
node _s2_way_mux_T_11 = or(_s2_way_mux_T_10, _s2_way_mux_T_4)
node _s2_way_mux_T_12 = or(_s2_way_mux_T_11, _s2_way_mux_T_5)
node _s2_way_mux_T_13 = or(_s2_way_mux_T_12, _s2_way_mux_T_6)
node _s2_way_mux_T_14 = or(_s2_way_mux_T_13, _s2_way_mux_T_7)
wire s2_way_mux : UInt<32>
connect s2_way_mux, _s2_way_mux_T_14
reg s2_tag_disparity_r : UInt<1>[8], clock
when s1_clk_en :
connect s2_tag_disparity_r, s1_tag_disparity
node s2_tag_disparity_lo_lo = cat(s2_tag_disparity_r[1], s2_tag_disparity_r[0])
node s2_tag_disparity_lo_hi = cat(s2_tag_disparity_r[3], s2_tag_disparity_r[2])
node s2_tag_disparity_lo = cat(s2_tag_disparity_lo_hi, s2_tag_disparity_lo_lo)
node s2_tag_disparity_hi_lo = cat(s2_tag_disparity_r[5], s2_tag_disparity_r[4])
node s2_tag_disparity_hi_hi = cat(s2_tag_disparity_r[7], s2_tag_disparity_r[6])
node s2_tag_disparity_hi = cat(s2_tag_disparity_hi_hi, s2_tag_disparity_hi_lo)
node _s2_tag_disparity_T = cat(s2_tag_disparity_hi, s2_tag_disparity_lo)
node s2_tag_disparity = orr(_s2_tag_disparity_T)
node s2_tl_error_lo_lo = cat(s1_tl_error[1], s1_tl_error[0])
node s2_tl_error_lo_hi = cat(s1_tl_error[3], s1_tl_error[2])
node s2_tl_error_lo = cat(s2_tl_error_lo_hi, s2_tl_error_lo_lo)
node s2_tl_error_hi_lo = cat(s1_tl_error[5], s1_tl_error[4])
node s2_tl_error_hi_hi = cat(s1_tl_error[7], s1_tl_error[6])
node s2_tl_error_hi = cat(s2_tl_error_hi_hi, s2_tl_error_hi_lo)
node _s2_tl_error_T = cat(s2_tl_error_hi, s2_tl_error_lo)
node _s2_tl_error_T_1 = orr(_s2_tl_error_T)
reg s2_tl_error : UInt<1>, clock
when s1_clk_en :
connect s2_tl_error, _s2_tl_error_T_1
node _s2_disparity_T = or(UInt<1>(0h0), UInt<1>(0h0))
node s2_disparity = or(s2_tag_disparity, _s2_disparity_T)
node _s1_scratchpad_hit_T = bits(s1s3_slaveAddr, 14, 6)
node _s1_scratchpad_hit_T_1 = bits(io.s1_paddr, 14, 6)
node _s1_scratchpad_hit_T_2 = and(UInt<1>(0h0), UInt<1>(0h0))
node s1_scratchpad_hit = mux(s1_slaveValid, UInt<1>(0h0), _s1_scratchpad_hit_T_2)
reg s2_scratchpad_hit : UInt<1>, clock
when s1_clk_en :
connect s2_scratchpad_hit, s1_scratchpad_hit
node _s2_report_uncorrectable_error_T = and(s2_scratchpad_hit, UInt<1>(0h0))
node _s2_report_uncorrectable_error_T_1 = eq(s1s2_full_word_write, UInt<1>(0h0))
node _s2_report_uncorrectable_error_T_2 = and(s2_slaveValid, _s2_report_uncorrectable_error_T_1)
node _s2_report_uncorrectable_error_T_3 = or(s2_valid, _s2_report_uncorrectable_error_T_2)
node s2_report_uncorrectable_error = and(_s2_report_uncorrectable_error_T, _s2_report_uncorrectable_error_T_3)
node _T_68 = and(s2_valid, s2_disparity)
when _T_68 :
connect invalidate, UInt<1>(0h1)
connect io.resp.bits.data, s2_way_mux
connect io.resp.bits.ae, s2_tl_error
connect io.resp.bits.replay, s2_disparity
node _io_resp_valid_T = and(s2_valid, s2_hit)
connect io.resp.valid, _io_resp_valid_T
connect masterNodeOut.a.valid, s2_request_refill
node _masterNodeOut_a_bits_T = shr(refill_paddr, 6)
node _masterNodeOut_a_bits_T_1 = shl(_masterNodeOut_a_bits_T, 6)
node _masterNodeOut_a_bits_legal_T = leq(UInt<1>(0h0), UInt<3>(0h6))
node _masterNodeOut_a_bits_legal_T_1 = leq(UInt<3>(0h6), UInt<4>(0hc))
node _masterNodeOut_a_bits_legal_T_2 = and(_masterNodeOut_a_bits_legal_T, _masterNodeOut_a_bits_legal_T_1)
node _masterNodeOut_a_bits_legal_T_3 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_2)
node _masterNodeOut_a_bits_legal_T_4 = xor(_masterNodeOut_a_bits_T_1, UInt<14>(0h3000))
node _masterNodeOut_a_bits_legal_T_5 = cvt(_masterNodeOut_a_bits_legal_T_4)
node _masterNodeOut_a_bits_legal_T_6 = and(_masterNodeOut_a_bits_legal_T_5, asSInt(UInt<33>(0h9a013000)))
node _masterNodeOut_a_bits_legal_T_7 = asSInt(_masterNodeOut_a_bits_legal_T_6)
node _masterNodeOut_a_bits_legal_T_8 = eq(_masterNodeOut_a_bits_legal_T_7, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_9 = and(_masterNodeOut_a_bits_legal_T_3, _masterNodeOut_a_bits_legal_T_8)
node _masterNodeOut_a_bits_legal_T_10 = leq(UInt<1>(0h0), UInt<3>(0h6))
node _masterNodeOut_a_bits_legal_T_11 = leq(UInt<3>(0h6), UInt<3>(0h6))
node _masterNodeOut_a_bits_legal_T_12 = and(_masterNodeOut_a_bits_legal_T_10, _masterNodeOut_a_bits_legal_T_11)
node _masterNodeOut_a_bits_legal_T_13 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_12)
node _masterNodeOut_a_bits_legal_T_14 = xor(_masterNodeOut_a_bits_T_1, UInt<1>(0h0))
node _masterNodeOut_a_bits_legal_T_15 = cvt(_masterNodeOut_a_bits_legal_T_14)
node _masterNodeOut_a_bits_legal_T_16 = and(_masterNodeOut_a_bits_legal_T_15, asSInt(UInt<33>(0h9a012000)))
node _masterNodeOut_a_bits_legal_T_17 = asSInt(_masterNodeOut_a_bits_legal_T_16)
node _masterNodeOut_a_bits_legal_T_18 = eq(_masterNodeOut_a_bits_legal_T_17, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_19 = xor(_masterNodeOut_a_bits_T_1, UInt<17>(0h10000))
node _masterNodeOut_a_bits_legal_T_20 = cvt(_masterNodeOut_a_bits_legal_T_19)
node _masterNodeOut_a_bits_legal_T_21 = and(_masterNodeOut_a_bits_legal_T_20, asSInt(UInt<33>(0h98013000)))
node _masterNodeOut_a_bits_legal_T_22 = asSInt(_masterNodeOut_a_bits_legal_T_21)
node _masterNodeOut_a_bits_legal_T_23 = eq(_masterNodeOut_a_bits_legal_T_22, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_24 = xor(_masterNodeOut_a_bits_T_1, UInt<17>(0h10000))
node _masterNodeOut_a_bits_legal_T_25 = cvt(_masterNodeOut_a_bits_legal_T_24)
node _masterNodeOut_a_bits_legal_T_26 = and(_masterNodeOut_a_bits_legal_T_25, asSInt(UInt<33>(0h9a010000)))
node _masterNodeOut_a_bits_legal_T_27 = asSInt(_masterNodeOut_a_bits_legal_T_26)
node _masterNodeOut_a_bits_legal_T_28 = eq(_masterNodeOut_a_bits_legal_T_27, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_29 = xor(_masterNodeOut_a_bits_T_1, UInt<26>(0h2000000))
node _masterNodeOut_a_bits_legal_T_30 = cvt(_masterNodeOut_a_bits_legal_T_29)
node _masterNodeOut_a_bits_legal_T_31 = and(_masterNodeOut_a_bits_legal_T_30, asSInt(UInt<33>(0h9a010000)))
node _masterNodeOut_a_bits_legal_T_32 = asSInt(_masterNodeOut_a_bits_legal_T_31)
node _masterNodeOut_a_bits_legal_T_33 = eq(_masterNodeOut_a_bits_legal_T_32, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_34 = xor(_masterNodeOut_a_bits_T_1, UInt<28>(0h8000000))
node _masterNodeOut_a_bits_legal_T_35 = cvt(_masterNodeOut_a_bits_legal_T_34)
node _masterNodeOut_a_bits_legal_T_36 = and(_masterNodeOut_a_bits_legal_T_35, asSInt(UInt<33>(0h98000000)))
node _masterNodeOut_a_bits_legal_T_37 = asSInt(_masterNodeOut_a_bits_legal_T_36)
node _masterNodeOut_a_bits_legal_T_38 = eq(_masterNodeOut_a_bits_legal_T_37, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_39 = xor(_masterNodeOut_a_bits_T_1, UInt<28>(0h8000000))
node _masterNodeOut_a_bits_legal_T_40 = cvt(_masterNodeOut_a_bits_legal_T_39)
node _masterNodeOut_a_bits_legal_T_41 = and(_masterNodeOut_a_bits_legal_T_40, asSInt(UInt<33>(0h9a010000)))
node _masterNodeOut_a_bits_legal_T_42 = asSInt(_masterNodeOut_a_bits_legal_T_41)
node _masterNodeOut_a_bits_legal_T_43 = eq(_masterNodeOut_a_bits_legal_T_42, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_44 = xor(_masterNodeOut_a_bits_T_1, UInt<29>(0h10000000))
node _masterNodeOut_a_bits_legal_T_45 = cvt(_masterNodeOut_a_bits_legal_T_44)
node _masterNodeOut_a_bits_legal_T_46 = and(_masterNodeOut_a_bits_legal_T_45, asSInt(UInt<33>(0h9a013000)))
node _masterNodeOut_a_bits_legal_T_47 = asSInt(_masterNodeOut_a_bits_legal_T_46)
node _masterNodeOut_a_bits_legal_T_48 = eq(_masterNodeOut_a_bits_legal_T_47, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_49 = xor(_masterNodeOut_a_bits_T_1, UInt<32>(0h80000000))
node _masterNodeOut_a_bits_legal_T_50 = cvt(_masterNodeOut_a_bits_legal_T_49)
node _masterNodeOut_a_bits_legal_T_51 = and(_masterNodeOut_a_bits_legal_T_50, asSInt(UInt<33>(0h90000000)))
node _masterNodeOut_a_bits_legal_T_52 = asSInt(_masterNodeOut_a_bits_legal_T_51)
node _masterNodeOut_a_bits_legal_T_53 = eq(_masterNodeOut_a_bits_legal_T_52, asSInt(UInt<1>(0h0)))
node _masterNodeOut_a_bits_legal_T_54 = or(_masterNodeOut_a_bits_legal_T_18, _masterNodeOut_a_bits_legal_T_23)
node _masterNodeOut_a_bits_legal_T_55 = or(_masterNodeOut_a_bits_legal_T_54, _masterNodeOut_a_bits_legal_T_28)
node _masterNodeOut_a_bits_legal_T_56 = or(_masterNodeOut_a_bits_legal_T_55, _masterNodeOut_a_bits_legal_T_33)
node _masterNodeOut_a_bits_legal_T_57 = or(_masterNodeOut_a_bits_legal_T_56, _masterNodeOut_a_bits_legal_T_38)
node _masterNodeOut_a_bits_legal_T_58 = or(_masterNodeOut_a_bits_legal_T_57, _masterNodeOut_a_bits_legal_T_43)
node _masterNodeOut_a_bits_legal_T_59 = or(_masterNodeOut_a_bits_legal_T_58, _masterNodeOut_a_bits_legal_T_48)
node _masterNodeOut_a_bits_legal_T_60 = or(_masterNodeOut_a_bits_legal_T_59, _masterNodeOut_a_bits_legal_T_53)
node _masterNodeOut_a_bits_legal_T_61 = and(_masterNodeOut_a_bits_legal_T_13, _masterNodeOut_a_bits_legal_T_60)
node _masterNodeOut_a_bits_legal_T_62 = or(UInt<1>(0h0), _masterNodeOut_a_bits_legal_T_9)
node masterNodeOut_a_bits_legal = or(_masterNodeOut_a_bits_legal_T_62, _masterNodeOut_a_bits_legal_T_61)
wire masterNodeOut_a_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect masterNodeOut_a_bits_a.opcode, UInt<3>(0h4)
connect masterNodeOut_a_bits_a.param, UInt<1>(0h0)
connect masterNodeOut_a_bits_a.size, UInt<3>(0h6)
connect masterNodeOut_a_bits_a.source, UInt<1>(0h0)
connect masterNodeOut_a_bits_a.address, _masterNodeOut_a_bits_T_1
node _masterNodeOut_a_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0))
node masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount = bits(_masterNodeOut_a_bits_a_mask_sizeOH_T, 1, 0)
node _masterNodeOut_a_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount)
node _masterNodeOut_a_bits_a_mask_sizeOH_T_2 = bits(_masterNodeOut_a_bits_a_mask_sizeOH_T_1, 2, 0)
node masterNodeOut_a_bits_a_mask_sizeOH = or(_masterNodeOut_a_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3))
node masterNodeOut_a_bits_a_mask_sub_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 2, 2)
node masterNodeOut_a_bits_a_mask_sub_sub_bit = bits(_masterNodeOut_a_bits_T_1, 2, 2)
node masterNodeOut_a_bits_a_mask_sub_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node masterNodeOut_a_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sub_sub_nbit)
node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_0_2)
node masterNodeOut_a_bits_a_mask_sub_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T)
node masterNodeOut_a_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), masterNodeOut_a_bits_a_mask_sub_sub_bit)
node _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_sub_size, masterNodeOut_a_bits_a_mask_sub_sub_1_2)
node masterNodeOut_a_bits_a_mask_sub_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_sub_acc_T_1)
node masterNodeOut_a_bits_a_mask_sub_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 1, 1)
node masterNodeOut_a_bits_a_mask_sub_bit = bits(_masterNodeOut_a_bits_T_1, 1, 1)
node masterNodeOut_a_bits_a_mask_sub_nbit = eq(masterNodeOut_a_bits_a_mask_sub_bit, UInt<1>(0h0))
node masterNodeOut_a_bits_a_mask_sub_0_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_nbit)
node _masterNodeOut_a_bits_a_mask_sub_acc_T = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_0_2)
node masterNodeOut_a_bits_a_mask_sub_0_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_acc_T)
node masterNodeOut_a_bits_a_mask_sub_1_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_0_2, masterNodeOut_a_bits_a_mask_sub_bit)
node _masterNodeOut_a_bits_a_mask_sub_acc_T_1 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_1_2)
node masterNodeOut_a_bits_a_mask_sub_1_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_0_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_1)
node masterNodeOut_a_bits_a_mask_sub_2_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_nbit)
node _masterNodeOut_a_bits_a_mask_sub_acc_T_2 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_2_2)
node masterNodeOut_a_bits_a_mask_sub_2_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_2)
node masterNodeOut_a_bits_a_mask_sub_3_2 = and(masterNodeOut_a_bits_a_mask_sub_sub_1_2, masterNodeOut_a_bits_a_mask_sub_bit)
node _masterNodeOut_a_bits_a_mask_sub_acc_T_3 = and(masterNodeOut_a_bits_a_mask_sub_size, masterNodeOut_a_bits_a_mask_sub_3_2)
node masterNodeOut_a_bits_a_mask_sub_3_1 = or(masterNodeOut_a_bits_a_mask_sub_sub_1_1, _masterNodeOut_a_bits_a_mask_sub_acc_T_3)
node masterNodeOut_a_bits_a_mask_size = bits(masterNodeOut_a_bits_a_mask_sizeOH, 0, 0)
node masterNodeOut_a_bits_a_mask_bit = bits(_masterNodeOut_a_bits_T_1, 0, 0)
node masterNodeOut_a_bits_a_mask_nbit = eq(masterNodeOut_a_bits_a_mask_bit, UInt<1>(0h0))
node masterNodeOut_a_bits_a_mask_eq = and(masterNodeOut_a_bits_a_mask_sub_0_2, masterNodeOut_a_bits_a_mask_nbit)
node _masterNodeOut_a_bits_a_mask_acc_T = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq)
node masterNodeOut_a_bits_a_mask_acc = or(masterNodeOut_a_bits_a_mask_sub_0_1, _masterNodeOut_a_bits_a_mask_acc_T)
node masterNodeOut_a_bits_a_mask_eq_1 = and(masterNodeOut_a_bits_a_mask_sub_0_2, masterNodeOut_a_bits_a_mask_bit)
node _masterNodeOut_a_bits_a_mask_acc_T_1 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_1)
node masterNodeOut_a_bits_a_mask_acc_1 = or(masterNodeOut_a_bits_a_mask_sub_0_1, _masterNodeOut_a_bits_a_mask_acc_T_1)
node masterNodeOut_a_bits_a_mask_eq_2 = and(masterNodeOut_a_bits_a_mask_sub_1_2, masterNodeOut_a_bits_a_mask_nbit)
node _masterNodeOut_a_bits_a_mask_acc_T_2 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_2)
node masterNodeOut_a_bits_a_mask_acc_2 = or(masterNodeOut_a_bits_a_mask_sub_1_1, _masterNodeOut_a_bits_a_mask_acc_T_2)
node masterNodeOut_a_bits_a_mask_eq_3 = and(masterNodeOut_a_bits_a_mask_sub_1_2, masterNodeOut_a_bits_a_mask_bit)
node _masterNodeOut_a_bits_a_mask_acc_T_3 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_3)
node masterNodeOut_a_bits_a_mask_acc_3 = or(masterNodeOut_a_bits_a_mask_sub_1_1, _masterNodeOut_a_bits_a_mask_acc_T_3)
node masterNodeOut_a_bits_a_mask_eq_4 = and(masterNodeOut_a_bits_a_mask_sub_2_2, masterNodeOut_a_bits_a_mask_nbit)
node _masterNodeOut_a_bits_a_mask_acc_T_4 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_4)
node masterNodeOut_a_bits_a_mask_acc_4 = or(masterNodeOut_a_bits_a_mask_sub_2_1, _masterNodeOut_a_bits_a_mask_acc_T_4)
node masterNodeOut_a_bits_a_mask_eq_5 = and(masterNodeOut_a_bits_a_mask_sub_2_2, masterNodeOut_a_bits_a_mask_bit)
node _masterNodeOut_a_bits_a_mask_acc_T_5 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_5)
node masterNodeOut_a_bits_a_mask_acc_5 = or(masterNodeOut_a_bits_a_mask_sub_2_1, _masterNodeOut_a_bits_a_mask_acc_T_5)
node masterNodeOut_a_bits_a_mask_eq_6 = and(masterNodeOut_a_bits_a_mask_sub_3_2, masterNodeOut_a_bits_a_mask_nbit)
node _masterNodeOut_a_bits_a_mask_acc_T_6 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_6)
node masterNodeOut_a_bits_a_mask_acc_6 = or(masterNodeOut_a_bits_a_mask_sub_3_1, _masterNodeOut_a_bits_a_mask_acc_T_6)
node masterNodeOut_a_bits_a_mask_eq_7 = and(masterNodeOut_a_bits_a_mask_sub_3_2, masterNodeOut_a_bits_a_mask_bit)
node _masterNodeOut_a_bits_a_mask_acc_T_7 = and(masterNodeOut_a_bits_a_mask_size, masterNodeOut_a_bits_a_mask_eq_7)
node masterNodeOut_a_bits_a_mask_acc_7 = or(masterNodeOut_a_bits_a_mask_sub_3_1, _masterNodeOut_a_bits_a_mask_acc_T_7)
node masterNodeOut_a_bits_a_mask_lo_lo = cat(masterNodeOut_a_bits_a_mask_acc_1, masterNodeOut_a_bits_a_mask_acc)
node masterNodeOut_a_bits_a_mask_lo_hi = cat(masterNodeOut_a_bits_a_mask_acc_3, masterNodeOut_a_bits_a_mask_acc_2)
node masterNodeOut_a_bits_a_mask_lo = cat(masterNodeOut_a_bits_a_mask_lo_hi, masterNodeOut_a_bits_a_mask_lo_lo)
node masterNodeOut_a_bits_a_mask_hi_lo = cat(masterNodeOut_a_bits_a_mask_acc_5, masterNodeOut_a_bits_a_mask_acc_4)
node masterNodeOut_a_bits_a_mask_hi_hi = cat(masterNodeOut_a_bits_a_mask_acc_7, masterNodeOut_a_bits_a_mask_acc_6)
node masterNodeOut_a_bits_a_mask_hi = cat(masterNodeOut_a_bits_a_mask_hi_hi, masterNodeOut_a_bits_a_mask_hi_lo)
node _masterNodeOut_a_bits_a_mask_T = cat(masterNodeOut_a_bits_a_mask_hi, masterNodeOut_a_bits_a_mask_lo)
connect masterNodeOut_a_bits_a.mask, _masterNodeOut_a_bits_a_mask_T
invalidate masterNodeOut_a_bits_a.data
connect masterNodeOut_a_bits_a.corrupt, UInt<1>(0h0)
connect masterNodeOut.a.bits, masterNodeOut_a_bits_a
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits.corrupt, UInt<1>(0h0)
connect _WIRE_3.bits.data, UInt<64>(0h0)
connect _WIRE_3.bits.mask, UInt<8>(0h0)
connect _WIRE_3.bits.address, UInt<32>(0h0)
connect _WIRE_3.bits.source, UInt<1>(0h0)
connect _WIRE_3.bits.size, UInt<4>(0h0)
connect _WIRE_3.bits.param, UInt<2>(0h0)
connect _WIRE_3.bits.opcode, UInt<3>(0h0)
connect _WIRE_3.valid, UInt<1>(0h0)
connect _WIRE_3.ready, UInt<1>(0h0)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits, _WIRE_3.bits
connect _WIRE_4.valid, _WIRE_3.valid
connect _WIRE_4.ready, _WIRE_3.ready
connect _WIRE_4.ready, UInt<1>(0h1)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits.corrupt, UInt<1>(0h0)
connect _WIRE_5.bits.data, UInt<64>(0h0)
connect _WIRE_5.bits.address, UInt<32>(0h0)
connect _WIRE_5.bits.source, UInt<1>(0h0)
connect _WIRE_5.bits.size, UInt<4>(0h0)
connect _WIRE_5.bits.param, UInt<3>(0h0)
connect _WIRE_5.bits.opcode, UInt<3>(0h0)
connect _WIRE_5.valid, UInt<1>(0h0)
connect _WIRE_5.ready, UInt<1>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits, _WIRE_5.bits
connect _WIRE_6.valid, _WIRE_5.valid
connect _WIRE_6.ready, _WIRE_5.ready
connect _WIRE_6.valid, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_7.bits.sink, UInt<3>(0h0)
connect _WIRE_7.valid, UInt<1>(0h0)
connect _WIRE_7.ready, UInt<1>(0h0)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_8.bits, _WIRE_7.bits
connect _WIRE_8.valid, _WIRE_7.valid
connect _WIRE_8.ready, _WIRE_7.ready
connect _WIRE_8.valid, UInt<1>(0h0)
node _T_69 = and(masterNodeOut.a.valid, UInt<1>(0h0))
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = asUInt(reset)
node _T_72 = eq(_T_71, UInt<1>(0h0))
when _T_72 :
node _T_73 = eq(_T_70, UInt<1>(0h0))
when _T_73 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at ICache.scala:826 assert(!(tl_out.a.valid && addrMaybeInScratchpad(tl_out.a.bits.address)))\n") : printf_1
assert(clock, _T_70, UInt<1>(0h1), "") : assert_1
node _T_74 = eq(refill_valid, UInt<1>(0h0))
when _T_74 :
connect invalidated, UInt<1>(0h0)
when refill_fire :
connect refill_valid, UInt<1>(0h1)
when refill_done :
connect refill_valid, UInt<1>(0h0)
connect io.perf.acquire, refill_fire
node _io_keep_clock_enabled_T = or(UInt<1>(0h0), s1_valid)
node _io_keep_clock_enabled_T_1 = or(_io_keep_clock_enabled_T, s2_valid)
node _io_keep_clock_enabled_T_2 = or(_io_keep_clock_enabled_T_1, refill_valid)
node _io_keep_clock_enabled_T_3 = or(_io_keep_clock_enabled_T_2, send_hint)
node _io_keep_clock_enabled_T_4 = or(_io_keep_clock_enabled_T_3, hint_outstanding)
connect io.keep_clock_enabled, _io_keep_clock_enabled_T_4
node _T_75 = eq(send_hint, UInt<1>(0h0))
node _T_76 = eq(masterNodeOut.a.ready, UInt<1>(0h0))
node _T_77 = and(masterNodeOut.a.valid, _T_76)
node _T_78 = and(_T_75, _T_77)
node _T_79 = and(invalidate, refill_valid)
node _T_80 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_81 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(s2_slaveValid, UInt<1>(0h0))
node _T_84 = eq(s2_tag_disparity, UInt<1>(0h0))
node _T_85 = eq(s2_scratchpad_hit, UInt<1>(0h0))
node _T_86 = and(_T_83, s2_scratchpad_hit)
node _T_87 = and(_T_83, _T_85)
node _T_88 = and(s2_slaveValid, s2_scratchpad_hit)
node _T_89 = and(s2_slaveValid, _T_85)
node _T_90 = and(_T_84, _T_86)
node _T_91 = and(_T_84, _T_87)
node _T_92 = and(_T_84, _T_88)
node _T_93 = and(_T_84, _T_89)
node _T_94 = and(_T_83, s2_scratchpad_hit)
node _T_95 = and(_T_83, _T_85)
node _T_96 = and(s2_slaveValid, s2_scratchpad_hit)
node _T_97 = and(s2_slaveValid, _T_85)
node _T_98 = and(s2_tag_disparity, _T_94)
node _T_99 = and(s2_tag_disparity, _T_95)
node _T_100 = and(s2_tag_disparity, _T_96)
node _T_101 = and(s2_tag_disparity, _T_97)
node _T_102 = and(_T_82, _T_90)
node _T_103 = and(_T_82, _T_91)
node _T_104 = and(_T_82, _T_92)
node _T_105 = and(_T_82, _T_93)
node _T_106 = and(_T_82, _T_98)
node _T_107 = and(_T_82, _T_99)
node _T_108 = and(_T_82, _T_100)
node _T_109 = and(_T_82, _T_101)
node _T_110 = and(_T_83, s2_scratchpad_hit)
node _T_111 = and(_T_83, _T_85)
node _T_112 = and(s2_slaveValid, s2_scratchpad_hit)
node _T_113 = and(s2_slaveValid, _T_85)
node _T_114 = and(_T_84, _T_110)
node _T_115 = and(_T_84, _T_111)
node _T_116 = and(_T_84, _T_112)
node _T_117 = and(_T_84, _T_113)
node _T_118 = and(_T_83, s2_scratchpad_hit)
node _T_119 = and(_T_83, _T_85)
node _T_120 = and(s2_slaveValid, s2_scratchpad_hit)
node _T_121 = and(s2_slaveValid, _T_85)
node _T_122 = and(s2_tag_disparity, _T_118)
node _T_123 = and(s2_tag_disparity, _T_119)
node _T_124 = and(s2_tag_disparity, _T_120)
node _T_125 = and(s2_tag_disparity, _T_121)
node _T_126 = and(UInt<1>(0h0), _T_114)
node _T_127 = and(UInt<1>(0h0), _T_115)
node _T_128 = and(UInt<1>(0h0), _T_116)
node _T_129 = and(UInt<1>(0h0), _T_117)
node _T_130 = and(UInt<1>(0h0), _T_122)
node _T_131 = and(UInt<1>(0h0), _T_123)
node _T_132 = and(UInt<1>(0h0), _T_124)
node _T_133 = and(UInt<1>(0h0), _T_125)
node _T_134 = and(_T_83, s2_scratchpad_hit)
node _T_135 = and(_T_83, _T_85)
node _T_136 = and(s2_slaveValid, s2_scratchpad_hit)
node _T_137 = and(s2_slaveValid, _T_85)
node _T_138 = and(_T_84, _T_134)
node _T_139 = and(_T_84, _T_135)
node _T_140 = and(_T_84, _T_136)
node _T_141 = and(_T_84, _T_137)
node _T_142 = and(_T_83, s2_scratchpad_hit)
node _T_143 = and(_T_83, _T_85)
node _T_144 = and(s2_slaveValid, s2_scratchpad_hit)
node _T_145 = and(s2_slaveValid, _T_85)
node _T_146 = and(s2_tag_disparity, _T_142)
node _T_147 = and(s2_tag_disparity, _T_143)
node _T_148 = and(s2_tag_disparity, _T_144)
node _T_149 = and(s2_tag_disparity, _T_145)
node _T_150 = and(UInt<1>(0h0), _T_138)
node _T_151 = and(UInt<1>(0h0), _T_139)
node _T_152 = and(UInt<1>(0h0), _T_140)
node _T_153 = and(UInt<1>(0h0), _T_141)
node _T_154 = and(UInt<1>(0h0), _T_146)
node _T_155 = and(UInt<1>(0h0), _T_147)
node _T_156 = and(UInt<1>(0h0), _T_148)
node _T_157 = and(UInt<1>(0h0), _T_149)
node _T_158 = and(s2_valid, _T_102)
node _T_159 = and(s2_valid, _T_103)
node _T_160 = and(s2_valid, _T_104)
node _T_161 = and(s2_valid, _T_105)
node _T_162 = and(s2_valid, _T_106)
node _T_163 = and(s2_valid, _T_107)
node _T_164 = and(s2_valid, _T_108)
node _T_165 = and(s2_valid, _T_109)
node _T_166 = and(s2_valid, _T_126)
node _T_167 = and(s2_valid, _T_127)
node _T_168 = and(s2_valid, _T_128)
node _T_169 = and(s2_valid, _T_129)
node _T_170 = and(s2_valid, _T_130)
node _T_171 = and(s2_valid, _T_131)
node _T_172 = and(s2_valid, _T_132)
node _T_173 = and(s2_valid, _T_133)
node _T_174 = and(s2_valid, _T_150)
node _T_175 = and(s2_valid, _T_151)
node _T_176 = and(s2_valid, _T_152)
node _T_177 = and(s2_valid, _T_153)
node _T_178 = and(s2_valid, _T_154)
node _T_179 = and(s2_valid, _T_155)
node _T_180 = and(s2_valid, _T_156)
node _T_181 = and(s2_valid, _T_157) | module ICache_3( // @[ICache.scala:251:7]
input clock, // @[ICache.scala:251:7]
input reset, // @[ICache.scala:251:7]
input auto_master_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_master_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_master_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input io_req_valid, // @[ICache.scala:256:14]
input [38:0] io_req_bits_addr, // @[ICache.scala:256:14]
input [31:0] io_s1_paddr, // @[ICache.scala:256:14]
input [38:0] io_s2_vaddr, // @[ICache.scala:256:14]
input io_s1_kill, // @[ICache.scala:256:14]
input io_s2_kill, // @[ICache.scala:256:14]
input io_s2_cacheable, // @[ICache.scala:256:14]
input io_s2_prefetch, // @[ICache.scala:256:14]
output io_resp_valid, // @[ICache.scala:256:14]
output [31:0] io_resp_bits_data, // @[ICache.scala:256:14]
output io_resp_bits_ae, // @[ICache.scala:256:14]
input io_invalidate, // @[ICache.scala:256:14]
output io_errors_bus_valid, // @[ICache.scala:256:14]
output [31:0] io_errors_bus_bits, // @[ICache.scala:256:14]
output io_perf_acquire // @[ICache.scala:256:14]
);
wire rockettile_icache_data_arrays_1_MPORT_2_mask_7; // @[ICache.scala:586:102]
wire rockettile_icache_data_arrays_1_MPORT_2_mask_6; // @[ICache.scala:586:102]
wire rockettile_icache_data_arrays_1_MPORT_2_mask_5; // @[ICache.scala:586:102]
wire rockettile_icache_data_arrays_1_MPORT_2_mask_4; // @[ICache.scala:586:102]
wire rockettile_icache_data_arrays_1_MPORT_2_mask_3; // @[ICache.scala:586:102]
wire rockettile_icache_data_arrays_1_MPORT_2_mask_2; // @[ICache.scala:586:102]
wire rockettile_icache_data_arrays_1_MPORT_2_mask_1; // @[ICache.scala:586:102]
wire rockettile_icache_data_arrays_1_MPORT_2_mask_0; // @[ICache.scala:586:102]
wire rockettile_icache_data_arrays_0_MPORT_1_mask_7; // @[ICache.scala:586:102]
wire rockettile_icache_data_arrays_0_MPORT_1_mask_6; // @[ICache.scala:586:102]
wire rockettile_icache_data_arrays_0_MPORT_1_mask_5; // @[ICache.scala:586:102]
wire rockettile_icache_data_arrays_0_MPORT_1_mask_4; // @[ICache.scala:586:102]
wire rockettile_icache_data_arrays_0_MPORT_1_mask_3; // @[ICache.scala:586:102]
wire rockettile_icache_data_arrays_0_MPORT_1_mask_2; // @[ICache.scala:586:102]
wire rockettile_icache_data_arrays_0_MPORT_1_mask_1; // @[ICache.scala:586:102]
wire rockettile_icache_data_arrays_0_MPORT_1_mask_0; // @[ICache.scala:586:102]
wire rockettile_icache_tag_array_MPORT_mask_7; // @[ICache.scala:436:97]
wire rockettile_icache_tag_array_MPORT_mask_6; // @[ICache.scala:436:97]
wire rockettile_icache_tag_array_MPORT_mask_5; // @[ICache.scala:436:97]
wire rockettile_icache_tag_array_MPORT_mask_4; // @[ICache.scala:436:97]
wire rockettile_icache_tag_array_MPORT_mask_3; // @[ICache.scala:436:97]
wire rockettile_icache_tag_array_MPORT_mask_2; // @[ICache.scala:436:97]
wire rockettile_icache_tag_array_MPORT_mask_1; // @[ICache.scala:436:97]
wire rockettile_icache_tag_array_MPORT_mask_0; // @[ICache.scala:436:97]
wire s1_tag_hit_6; // @[ICache.scala:345:24]
wire s1_tag_hit_5; // @[ICache.scala:345:24]
wire s1_tag_hit_4; // @[ICache.scala:345:24]
wire s1_tag_hit_3; // @[ICache.scala:345:24]
wire s1_tag_hit_2; // @[ICache.scala:345:24]
wire s1_tag_hit_1; // @[ICache.scala:345:24]
wire s1_tag_hit_0; // @[ICache.scala:345:24]
wire [255:0] _rockettile_icache_data_arrays_1_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire [255:0] _rockettile_icache_data_arrays_0_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire [167:0] _rockettile_icache_tag_array_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire _repl_way_v0_prng_io_out_0; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_1; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_2; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_3; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_4; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_5; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_6; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_7; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_8; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_9; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_10; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_11; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_12; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_13; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_14; // @[PRNG.scala:91:22]
wire _repl_way_v0_prng_io_out_15; // @[PRNG.scala:91:22]
wire auto_master_out_a_ready_0 = auto_master_out_a_ready; // @[ICache.scala:251:7]
wire auto_master_out_d_valid_0 = auto_master_out_d_valid; // @[ICache.scala:251:7]
wire [2:0] auto_master_out_d_bits_opcode_0 = auto_master_out_d_bits_opcode; // @[ICache.scala:251:7]
wire [1:0] auto_master_out_d_bits_param_0 = auto_master_out_d_bits_param; // @[ICache.scala:251:7]
wire [3:0] auto_master_out_d_bits_size_0 = auto_master_out_d_bits_size; // @[ICache.scala:251:7]
wire [2:0] auto_master_out_d_bits_sink_0 = auto_master_out_d_bits_sink; // @[ICache.scala:251:7]
wire auto_master_out_d_bits_denied_0 = auto_master_out_d_bits_denied; // @[ICache.scala:251:7]
wire [63:0] auto_master_out_d_bits_data_0 = auto_master_out_d_bits_data; // @[ICache.scala:251:7]
wire auto_master_out_d_bits_corrupt_0 = auto_master_out_d_bits_corrupt; // @[ICache.scala:251:7]
wire io_req_valid_0 = io_req_valid; // @[ICache.scala:251:7]
wire [38:0] io_req_bits_addr_0 = io_req_bits_addr; // @[ICache.scala:251:7]
wire [31:0] io_s1_paddr_0 = io_s1_paddr; // @[ICache.scala:251:7]
wire [38:0] io_s2_vaddr_0 = io_s2_vaddr; // @[ICache.scala:251:7]
wire io_s1_kill_0 = io_s1_kill; // @[ICache.scala:251:7]
wire io_s2_kill_0 = io_s2_kill; // @[ICache.scala:251:7]
wire io_s2_cacheable_0 = io_s2_cacheable; // @[ICache.scala:251:7]
wire io_s2_prefetch_0 = io_s2_prefetch; // @[ICache.scala:251:7]
wire io_invalidate_0 = io_invalidate; // @[ICache.scala:251:7]
wire _repl_way_T_13 = reset; // @[ICache.scala:413:11]
wire auto_master_out_d_ready = 1'h1; // @[ICache.scala:251:7]
wire io_clock_enabled = 1'h1; // @[ICache.scala:251:7]
wire masterNodeOut_d_ready = 1'h1; // @[MixedNode.scala:542:17]
wire _refill_fire_T_1 = 1'h1; // @[ICache.scala:374:38]
wire _masterNodeOut_d_ready_T = 1'h1; // @[ICache.scala:401:21]
wire _repl_way_T_12 = 1'h1; // @[ICache.scala:413:12]
wire _scratchpadHit_T = 1'h1; // @[ICache.scala:316:43]
wire _s1_vb_T_4 = 1'h1; // @[ICache.scala:508:74]
wire _scratchpadHit_T_11 = 1'h1; // @[ICache.scala:316:43]
wire _s1_vb_T_9 = 1'h1; // @[ICache.scala:508:74]
wire _scratchpadHit_T_22 = 1'h1; // @[ICache.scala:316:43]
wire _s1_vb_T_14 = 1'h1; // @[ICache.scala:508:74]
wire _scratchpadHit_T_33 = 1'h1; // @[ICache.scala:316:43]
wire _s1_vb_T_19 = 1'h1; // @[ICache.scala:508:74]
wire _scratchpadHit_T_44 = 1'h1; // @[ICache.scala:316:43]
wire _s1_vb_T_23 = 1'h1; // @[ICache.scala:508:74]
wire _scratchpadHit_T_55 = 1'h1; // @[ICache.scala:316:43]
wire _s1_vb_T_27 = 1'h1; // @[ICache.scala:508:74]
wire _scratchpadHit_T_66 = 1'h1; // @[ICache.scala:316:43]
wire _s1_vb_T_31 = 1'h1; // @[ICache.scala:508:74]
wire _s1_vb_T_35 = 1'h1; // @[ICache.scala:508:74]
wire _s0_ren_T_3 = 1'h1; // @[ICache.scala:564:111]
wire _s2_report_uncorrectable_error_T_1 = 1'h1; // @[ICache.scala:632:124]
wire _masterNodeOut_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _masterNodeOut_a_bits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _masterNodeOut_a_bits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _masterNodeOut_a_bits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _masterNodeOut_a_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _masterNodeOut_a_bits_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _masterNodeOut_a_bits_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _masterNodeOut_a_bits_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire masterNodeOut_a_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire masterNodeOut_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire masterNodeOut_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire masterNodeOut_a_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire masterNodeOut_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire masterNodeOut_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire masterNodeOut_a_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire masterNodeOut_a_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire masterNodeOut_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire masterNodeOut_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire masterNodeOut_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire masterNodeOut_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire masterNodeOut_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire masterNodeOut_a_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire masterNodeOut_a_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire masterNodeOut_a_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire masterNodeOut_a_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire auto_master_out_a_bits_source = 1'h0; // @[ICache.scala:251:7]
wire auto_master_out_a_bits_corrupt = 1'h0; // @[ICache.scala:251:7]
wire auto_master_out_d_bits_source = 1'h0; // @[ICache.scala:251:7]
wire io_resp_bits_replay = 1'h0; // @[ICache.scala:251:7]
wire masterNodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire masterNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire masterNodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire _s1_hit_T_7 = 1'h0; // @[ICache.scala:361:46]
wire _repl_way_T_10 = 1'h0; // @[ICache.scala:411:63]
wire _repl_way_T_15 = 1'h0; // @[ICache.scala:413:11]
wire s1_tag_disparity_0 = 1'h0; // @[ICache.scala:465:30]
wire s1_tag_disparity_1 = 1'h0; // @[ICache.scala:465:30]
wire s1_tag_disparity_2 = 1'h0; // @[ICache.scala:465:30]
wire s1_tag_disparity_3 = 1'h0; // @[ICache.scala:465:30]
wire s1_tag_disparity_4 = 1'h0; // @[ICache.scala:465:30]
wire s1_tag_disparity_5 = 1'h0; // @[ICache.scala:465:30]
wire s1_tag_disparity_6 = 1'h0; // @[ICache.scala:465:30]
wire s1_tag_disparity_7 = 1'h0; // @[ICache.scala:465:30]
wire _scratchpadHit_T_4 = 1'h0; // @[ICache.scala:503:58]
wire _scratchpadHit_T_6 = 1'h0; // @[ICache.scala:302:66]
wire _scratchpadHit_T_9 = 1'h0; // @[ICache.scala:507:39]
wire _scratchpadHit_T_10 = 1'h0; // @[ICache.scala:498:10]
wire scratchpadHit = 1'h0; // @[ICache.scala:497:49]
wire _s1_tag_disparity_0_T = 1'h0; // @[ECC.scala:15:27]
wire _s1_tag_disparity_0_T_1 = 1'h0; // @[ICache.scala:516:34]
wire _scratchpadHit_T_15 = 1'h0; // @[ICache.scala:503:58]
wire _scratchpadHit_T_17 = 1'h0; // @[ICache.scala:302:66]
wire _scratchpadHit_T_20 = 1'h0; // @[ICache.scala:507:39]
wire _scratchpadHit_T_21 = 1'h0; // @[ICache.scala:498:10]
wire scratchpadHit_1 = 1'h0; // @[ICache.scala:497:49]
wire _s1_tag_disparity_1_T = 1'h0; // @[ECC.scala:15:27]
wire _s1_tag_disparity_1_T_1 = 1'h0; // @[ICache.scala:516:34]
wire _scratchpadHit_T_26 = 1'h0; // @[ICache.scala:503:58]
wire _scratchpadHit_T_28 = 1'h0; // @[ICache.scala:302:66]
wire _scratchpadHit_T_31 = 1'h0; // @[ICache.scala:507:39]
wire _scratchpadHit_T_32 = 1'h0; // @[ICache.scala:498:10]
wire scratchpadHit_2 = 1'h0; // @[ICache.scala:497:49]
wire _s1_tag_disparity_2_T = 1'h0; // @[ECC.scala:15:27]
wire _s1_tag_disparity_2_T_1 = 1'h0; // @[ICache.scala:516:34]
wire _scratchpadHit_T_37 = 1'h0; // @[ICache.scala:503:58]
wire _scratchpadHit_T_39 = 1'h0; // @[ICache.scala:302:66]
wire _scratchpadHit_T_42 = 1'h0; // @[ICache.scala:507:39]
wire _scratchpadHit_T_43 = 1'h0; // @[ICache.scala:498:10]
wire scratchpadHit_3 = 1'h0; // @[ICache.scala:497:49]
wire _s1_tag_disparity_3_T = 1'h0; // @[ECC.scala:15:27]
wire _s1_tag_disparity_3_T_1 = 1'h0; // @[ICache.scala:516:34]
wire _scratchpadHit_T_48 = 1'h0; // @[ICache.scala:503:58]
wire _scratchpadHit_T_50 = 1'h0; // @[ICache.scala:302:66]
wire _scratchpadHit_T_53 = 1'h0; // @[ICache.scala:507:39]
wire _scratchpadHit_T_54 = 1'h0; // @[ICache.scala:498:10]
wire scratchpadHit_4 = 1'h0; // @[ICache.scala:497:49]
wire _s1_tag_disparity_4_T = 1'h0; // @[ECC.scala:15:27]
wire _s1_tag_disparity_4_T_1 = 1'h0; // @[ICache.scala:516:34]
wire _scratchpadHit_T_59 = 1'h0; // @[ICache.scala:503:58]
wire _scratchpadHit_T_61 = 1'h0; // @[ICache.scala:302:66]
wire _scratchpadHit_T_64 = 1'h0; // @[ICache.scala:507:39]
wire _scratchpadHit_T_65 = 1'h0; // @[ICache.scala:498:10]
wire scratchpadHit_5 = 1'h0; // @[ICache.scala:497:49]
wire _s1_tag_disparity_5_T = 1'h0; // @[ECC.scala:15:27]
wire _s1_tag_disparity_5_T_1 = 1'h0; // @[ICache.scala:516:34]
wire _scratchpadHit_T_70 = 1'h0; // @[ICache.scala:503:58]
wire _scratchpadHit_T_72 = 1'h0; // @[ICache.scala:302:66]
wire _scratchpadHit_T_75 = 1'h0; // @[ICache.scala:507:39]
wire _scratchpadHit_T_76 = 1'h0; // @[ICache.scala:498:10]
wire scratchpadHit_6 = 1'h0; // @[ICache.scala:497:49]
wire _s1_tag_disparity_6_T = 1'h0; // @[ECC.scala:15:27]
wire _s1_tag_disparity_6_T_1 = 1'h0; // @[ICache.scala:516:34]
wire _scratchpadHit_T_77 = 1'h0; // @[ICache.scala:316:43]
wire _scratchpadHit_T_81 = 1'h0; // @[ICache.scala:503:58]
wire _scratchpadHit_T_83 = 1'h0; // @[ICache.scala:302:66]
wire _scratchpadHit_T_86 = 1'h0; // @[ICache.scala:507:39]
wire _scratchpadHit_T_87 = 1'h0; // @[ICache.scala:498:10]
wire scratchpadHit_7 = 1'h0; // @[ICache.scala:497:49]
wire _s1_tag_disparity_7_T = 1'h0; // @[ECC.scala:15:27]
wire _s1_tag_disparity_7_T_1 = 1'h0; // @[ICache.scala:516:34]
wire _s0_ren_T_4 = 1'h0; // @[ICache.scala:567:70]
wire _wen_T_2 = 1'h0; // @[package.scala:163:13]
wire _wen_T_4 = 1'h0; // @[ICache.scala:570:67]
wire _s0_ren_T_8 = 1'h0; // @[ICache.scala:564:111]
wire _s0_ren_T_9 = 1'h0; // @[ICache.scala:567:70]
wire _wen_T_7 = 1'h0; // @[package.scala:163:13]
wire _wen_T_9 = 1'h0; // @[ICache.scala:570:67]
wire s1s2_full_word_write = 1'h0; // @[ICache.scala:600:41]
wire s1_dont_read = 1'h0; // @[ICache.scala:601:36]
wire _s2_tag_hit_WIRE_0 = 1'h0; // @[ICache.scala:605:60]
wire _s2_tag_hit_WIRE_1 = 1'h0; // @[ICache.scala:605:60]
wire _s2_tag_hit_WIRE_2 = 1'h0; // @[ICache.scala:605:60]
wire _s2_tag_hit_WIRE_3 = 1'h0; // @[ICache.scala:605:60]
wire _s2_tag_hit_WIRE_4 = 1'h0; // @[ICache.scala:605:60]
wire _s2_tag_hit_WIRE_5 = 1'h0; // @[ICache.scala:605:60]
wire _s2_tag_hit_WIRE_6 = 1'h0; // @[ICache.scala:605:60]
wire _s2_tag_hit_WIRE_7 = 1'h0; // @[ICache.scala:605:60]
wire s2_tag_disparity = 1'h0; // @[ICache.scala:614:72]
wire _s2_disparity_T = 1'h0; // @[ECC.scala:15:27]
wire s2_disparity = 1'h0; // @[ICache.scala:619:39]
wire _s1_scratchpad_hit_T_2 = 1'h0; // @[ICache.scala:302:66]
wire s1_scratchpad_hit = 1'h0; // @[ICache.scala:621:30]
wire _s2_report_uncorrectable_error_T = 1'h0; // @[ICache.scala:632:57]
wire _s2_report_uncorrectable_error_T_2 = 1'h0; // @[ICache.scala:632:121]
wire s2_report_uncorrectable_error = 1'h0; // @[ICache.scala:632:90]
wire masterNodeOut_a_bits_a_source = 1'h0; // @[Edges.scala:460:17]
wire masterNodeOut_a_bits_a_corrupt = 1'h0; // @[Edges.scala:460:17]
wire masterNodeOut_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _masterNodeOut_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _masterNodeOut_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _masterNodeOut_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _masterNodeOut_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire [7:0] _s2_tag_disparity_T = 8'h0; // @[ICache.scala:614:65]
wire [3:0] s2_tag_disparity_lo = 4'h0; // @[ICache.scala:614:65]
wire [3:0] s2_tag_disparity_hi = 4'h0; // @[ICache.scala:614:65]
wire [1:0] _repl_way_T_6 = 2'h0; // @[ICache.scala:411:63]
wire [1:0] s2_tag_disparity_lo_lo = 2'h0; // @[ICache.scala:614:65]
wire [1:0] s2_tag_disparity_lo_hi = 2'h0; // @[ICache.scala:614:65]
wire [1:0] s2_tag_disparity_hi_lo = 2'h0; // @[ICache.scala:614:65]
wire [1:0] s2_tag_disparity_hi_hi = 2'h0; // @[ICache.scala:614:65]
wire [2:0] auto_master_out_a_bits_opcode = 3'h4; // @[ICache.scala:251:7]
wire [2:0] masterNodeOut_a_bits_opcode = 3'h4; // @[MixedNode.scala:542:17]
wire [2:0] masterNodeOut_a_bits_a_opcode = 3'h4; // @[Edges.scala:460:17]
wire [2:0] _masterNodeOut_a_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27]
wire [2:0] auto_master_out_a_bits_param = 3'h0; // @[ICache.scala:251:7]
wire [2:0] masterNodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] _repl_way_T_2 = 3'h0; // @[ICache.scala:411:63]
wire [2:0] _scratchpadHit_T_2 = 3'h0; // @[package.scala:163:13]
wire [2:0] _scratchpadHit_T_13 = 3'h0; // @[package.scala:163:13]
wire [2:0] _scratchpadHit_T_24 = 3'h0; // @[package.scala:163:13]
wire [2:0] _scratchpadHit_T_35 = 3'h0; // @[package.scala:163:13]
wire [2:0] _scratchpadHit_T_46 = 3'h0; // @[package.scala:163:13]
wire [2:0] _scratchpadHit_T_57 = 3'h0; // @[package.scala:163:13]
wire [2:0] _scratchpadHit_T_68 = 3'h0; // @[package.scala:163:13]
wire [2:0] _scratchpadHit_T_79 = 3'h0; // @[package.scala:163:13]
wire [2:0] _way_T = 3'h0; // @[package.scala:163:13]
wire [2:0] _way_T_1 = 3'h0; // @[package.scala:163:13]
wire [2:0] masterNodeOut_a_bits_a_param = 3'h0; // @[Edges.scala:460:17]
wire [3:0] auto_master_out_a_bits_size = 4'h6; // @[ICache.scala:251:7]
wire [3:0] masterNodeOut_a_bits_size = 4'h6; // @[MixedNode.scala:542:17]
wire [3:0] masterNodeOut_a_bits_a_size = 4'h6; // @[Edges.scala:460:17]
wire [7:0] auto_master_out_a_bits_mask = 8'hFF; // @[ICache.scala:251:7]
wire [7:0] masterNodeOut_a_bits_mask = 8'hFF; // @[MixedNode.scala:542:17]
wire [7:0] masterNodeOut_a_bits_a_mask = 8'hFF; // @[Edges.scala:460:17]
wire [7:0] _masterNodeOut_a_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10]
wire [63:0] auto_master_out_a_bits_data = 64'h0; // @[ICache.scala:251:7]
wire [63:0] masterNodeOut_a_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] masterNodeOut_a_bits_a_data = 64'h0; // @[Edges.scala:460:17]
wire [3:0] masterNodeOut_a_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] masterNodeOut_a_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10]
wire [1:0] masterNodeOut_a_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] masterNodeOut_a_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] masterNodeOut_a_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] masterNodeOut_a_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [2:0] masterNodeOut_a_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81]
wire [3:0] _masterNodeOut_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [1:0] masterNodeOut_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [2:0] _masterNodeOut_a_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34]
wire [8:0] _scratchpadHit_T_1 = 9'h0; // @[ICache.scala:327:40]
wire [8:0] _scratchpadHit_T_12 = 9'h0; // @[ICache.scala:327:40]
wire [8:0] _scratchpadHit_T_23 = 9'h0; // @[ICache.scala:327:40]
wire [8:0] _scratchpadHit_T_34 = 9'h0; // @[ICache.scala:327:40]
wire [8:0] _scratchpadHit_T_45 = 9'h0; // @[ICache.scala:327:40]
wire [8:0] _scratchpadHit_T_56 = 9'h0; // @[ICache.scala:327:40]
wire [8:0] _scratchpadHit_T_67 = 9'h0; // @[ICache.scala:327:40]
wire [8:0] _scratchpadHit_T_78 = 9'h0; // @[ICache.scala:327:40]
wire [8:0] _mem_idx_T_2 = 9'h0; // @[ICache.scala:565:31]
wire [8:0] _mem_idx_T_8 = 9'h0; // @[ICache.scala:565:31]
wire [8:0] _s1_scratchpad_hit_T = 9'h0; // @[ICache.scala:327:40]
wire masterNodeOut_a_ready = auto_master_out_a_ready_0; // @[ICache.scala:251:7]
wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire masterNodeOut_d_valid = auto_master_out_d_valid_0; // @[ICache.scala:251:7]
wire [2:0] masterNodeOut_d_bits_opcode = auto_master_out_d_bits_opcode_0; // @[ICache.scala:251:7]
wire [1:0] masterNodeOut_d_bits_param = auto_master_out_d_bits_param_0; // @[ICache.scala:251:7]
wire [3:0] masterNodeOut_d_bits_size = auto_master_out_d_bits_size_0; // @[ICache.scala:251:7]
wire [2:0] masterNodeOut_d_bits_sink = auto_master_out_d_bits_sink_0; // @[ICache.scala:251:7]
wire masterNodeOut_d_bits_denied = auto_master_out_d_bits_denied_0; // @[ICache.scala:251:7]
wire [63:0] masterNodeOut_d_bits_data = auto_master_out_d_bits_data_0; // @[ICache.scala:251:7]
wire masterNodeOut_d_bits_corrupt = auto_master_out_d_bits_corrupt_0; // @[ICache.scala:251:7]
wire _io_req_ready_T_2; // @[ICache.scala:394:19]
wire [38:0] _s2_scratchpad_word_addr_T = io_s2_vaddr_0; // @[ICache.scala:251:7, :611:52]
wire _io_resp_valid_T; // @[ICache.scala:659:33]
wire [31:0] s2_way_mux; // @[Mux.scala:30:73]
wire _io_errors_bus_valid_T_2; // @[ICache.scala:441:40]
wire invalidate = io_invalidate_0; // @[ICache.scala:251:7, :456:31]
wire [31:0] _io_errors_bus_bits_T_1; // @[ICache.scala:442:57]
wire refill_fire; // @[ICache.scala:374:35]
wire _io_keep_clock_enabled_T_4; // @[ICache.scala:837:55]
wire [31:0] auto_master_out_a_bits_address_0; // @[ICache.scala:251:7]
wire auto_master_out_a_valid_0; // @[ICache.scala:251:7]
wire io_req_ready; // @[ICache.scala:251:7]
wire [31:0] io_resp_bits_data_0; // @[ICache.scala:251:7]
wire io_resp_bits_ae_0; // @[ICache.scala:251:7]
wire io_resp_valid_0; // @[ICache.scala:251:7]
wire io_errors_bus_valid_0; // @[ICache.scala:251:7]
wire [31:0] io_errors_bus_bits_0; // @[ICache.scala:251:7]
wire io_perf_acquire_0; // @[ICache.scala:251:7]
wire io_keep_clock_enabled; // @[ICache.scala:251:7]
wire s2_request_refill; // @[ICache.scala:385:35]
assign auto_master_out_a_valid_0 = masterNodeOut_a_valid; // @[ICache.scala:251:7]
wire [31:0] masterNodeOut_a_bits_a_address; // @[Edges.scala:460:17]
assign auto_master_out_a_bits_address_0 = masterNodeOut_a_bits_address; // @[ICache.scala:251:7]
wire _refill_one_beat_T = masterNodeOut_d_valid; // @[Decoupled.scala:51:35]
wire _io_errors_bus_valid_T = masterNodeOut_d_valid; // @[Decoupled.scala:51:35]
wire s0_valid = io_req_ready & io_req_valid_0; // @[Decoupled.scala:51:35]
reg s1_valid; // @[ICache.scala:341:25]
wire s1_clk_en = s1_valid; // @[ICache.scala:341:25, :604:28]
wire _io_keep_clock_enabled_T = s1_valid; // @[ICache.scala:341:25, :836:117]
reg [38:0] s1_vaddr; // @[ICache.scala:343:27]
wire _s1_tag_hit_0_T; // @[ICache.scala:519:31]
wire _s1_tag_hit_1_T; // @[ICache.scala:519:31]
wire _s2_tag_hit_T_0 = s1_tag_hit_0; // @[ICache.scala:345:24, :605:33]
wire _s1_tag_hit_2_T; // @[ICache.scala:519:31]
wire _s2_tag_hit_T_1 = s1_tag_hit_1; // @[ICache.scala:345:24, :605:33]
wire _s1_tag_hit_3_T; // @[ICache.scala:519:31]
wire _s2_tag_hit_T_2 = s1_tag_hit_2; // @[ICache.scala:345:24, :605:33]
wire _s1_tag_hit_4_T; // @[ICache.scala:519:31]
wire _s2_tag_hit_T_3 = s1_tag_hit_3; // @[ICache.scala:345:24, :605:33]
wire _s1_tag_hit_5_T; // @[ICache.scala:519:31]
wire _s2_tag_hit_T_4 = s1_tag_hit_4; // @[ICache.scala:345:24, :605:33]
wire _s1_tag_hit_6_T; // @[ICache.scala:519:31]
wire _s2_tag_hit_T_5 = s1_tag_hit_5; // @[ICache.scala:345:24, :605:33]
wire _s1_tag_hit_7_T; // @[ICache.scala:519:31]
wire _s2_tag_hit_T_6 = s1_tag_hit_6; // @[ICache.scala:345:24, :605:33]
wire s1_tag_hit_7; // @[ICache.scala:345:24]
wire _s2_tag_hit_T_7 = s1_tag_hit_7; // @[ICache.scala:345:24, :605:33]
wire _s1_hit_T = s1_tag_hit_0 | s1_tag_hit_1; // @[ICache.scala:345:24, :361:35]
wire _s1_hit_T_1 = _s1_hit_T | s1_tag_hit_2; // @[ICache.scala:345:24, :361:35]
wire _s1_hit_T_2 = _s1_hit_T_1 | s1_tag_hit_3; // @[ICache.scala:345:24, :361:35]
wire _s1_hit_T_3 = _s1_hit_T_2 | s1_tag_hit_4; // @[ICache.scala:345:24, :361:35]
wire _s1_hit_T_4 = _s1_hit_T_3 | s1_tag_hit_5; // @[ICache.scala:345:24, :361:35]
wire _s1_hit_T_5 = _s1_hit_T_4 | s1_tag_hit_6; // @[ICache.scala:345:24, :361:35]
wire _s1_hit_T_6 = _s1_hit_T_5 | s1_tag_hit_7; // @[ICache.scala:345:24, :361:35]
wire s1_hit = _s1_hit_T_6; // @[ICache.scala:361:{35,40}]
wire _s2_valid_T = ~io_s1_kill_0; // @[ICache.scala:251:7, :363:38]
wire _s2_valid_T_1 = s1_valid & _s2_valid_T; // @[ICache.scala:341:25, :363:{35,38}]
reg s2_valid; // @[ICache.scala:363:25]
wire _s2_report_uncorrectable_error_T_3 = s2_valid; // @[ICache.scala:363:25, :632:103]
reg s2_hit; // @[ICache.scala:364:23]
reg invalidated; // @[ICache.scala:367:24]
reg refill_valid; // @[ICache.scala:368:29]
wire _refill_fire_T = masterNodeOut_a_ready & masterNodeOut_a_valid; // @[Decoupled.scala:51:35]
assign refill_fire = _refill_fire_T; // @[Decoupled.scala:51:35]
assign io_perf_acquire_0 = refill_fire; // @[ICache.scala:251:7, :374:35]
wire _s2_miss_T = ~s2_hit; // @[ICache.scala:364:23, :378:29]
wire _s2_miss_T_1 = s2_valid & _s2_miss_T; // @[ICache.scala:363:25, :378:{26,29}]
wire _s2_miss_T_2 = ~io_s2_kill_0; // @[ICache.scala:251:7, :378:40]
wire s2_miss = _s2_miss_T_1 & _s2_miss_T_2; // @[ICache.scala:378:{26,37,40}]
wire _s1_can_request_refill_T = s2_miss | refill_valid; // @[ICache.scala:368:29, :378:37, :380:41]
wire s1_can_request_refill = ~_s1_can_request_refill_T; // @[ICache.scala:380:{31,41}]
reg s2_request_refill_REG; // @[ICache.scala:385:45]
assign s2_request_refill = s2_miss & s2_request_refill_REG; // @[ICache.scala:378:37, :385:{35,45}]
assign masterNodeOut_a_valid = s2_request_refill; // @[ICache.scala:385:35]
wire _GEN = s1_valid & s1_can_request_refill; // @[ICache.scala:341:25, :380:31, :386:54]
wire _refill_paddr_T; // @[ICache.scala:386:54]
assign _refill_paddr_T = _GEN; // @[ICache.scala:386:54]
wire _refill_vaddr_T; // @[ICache.scala:387:51]
assign _refill_vaddr_T = _GEN; // @[ICache.scala:386:54, :387:51]
reg [31:0] refill_paddr; // @[ICache.scala:386:31]
reg [38:0] refill_vaddr; // @[ICache.scala:387:31]
wire [19:0] refill_tag = refill_paddr[31:12]; // @[ICache.scala:386:31, :388:33]
wire [5:0] refill_idx = refill_paddr[11:6]; // @[ICache.scala:386:31, :859:21]
wire refill_one_beat_opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire r_beats1_opdata = masterNodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire refill_one_beat = _refill_one_beat_T & refill_one_beat_opdata; // @[Decoupled.scala:51:35]
wire _io_req_ready_T = refill_one_beat; // @[ICache.scala:391:39, :394:37]
wire _io_req_ready_T_1 = _io_req_ready_T; // @[ICache.scala:394:{37,54}]
assign _io_req_ready_T_2 = ~_io_req_ready_T_1; // @[ICache.scala:394:{19,54}]
assign io_req_ready = _io_req_ready_T_2; // @[ICache.scala:251:7, :394:19]
wire [26:0] _r_beats1_decode_T = 27'hFFF << masterNodeOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] r_counter; // @[Edges.scala:229:27]
wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28]
wire r_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_done = r_2 & masterNodeOut_d_valid; // @[Edges.scala:232:33, :233:22]
wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] refill_cnt = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _r_counter_T = r_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire refill_done = refill_one_beat & d_done; // @[Edges.scala:233:22]
wire [1:0] repl_way_v0_lo_lo_lo = {_repl_way_v0_prng_io_out_1, _repl_way_v0_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] repl_way_v0_lo_lo_hi = {_repl_way_v0_prng_io_out_3, _repl_way_v0_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] repl_way_v0_lo_lo = {repl_way_v0_lo_lo_hi, repl_way_v0_lo_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] repl_way_v0_lo_hi_lo = {_repl_way_v0_prng_io_out_5, _repl_way_v0_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] repl_way_v0_lo_hi_hi = {_repl_way_v0_prng_io_out_7, _repl_way_v0_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] repl_way_v0_lo_hi = {repl_way_v0_lo_hi_hi, repl_way_v0_lo_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] repl_way_v0_lo = {repl_way_v0_lo_hi, repl_way_v0_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] repl_way_v0_hi_lo_lo = {_repl_way_v0_prng_io_out_9, _repl_way_v0_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] repl_way_v0_hi_lo_hi = {_repl_way_v0_prng_io_out_11, _repl_way_v0_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] repl_way_v0_hi_lo = {repl_way_v0_hi_lo_hi, repl_way_v0_hi_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] repl_way_v0_hi_hi_lo = {_repl_way_v0_prng_io_out_13, _repl_way_v0_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] repl_way_v0_hi_hi_hi = {_repl_way_v0_prng_io_out_15, _repl_way_v0_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] repl_way_v0_hi_hi = {repl_way_v0_hi_hi_hi, repl_way_v0_hi_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] repl_way_v0_hi = {repl_way_v0_hi_hi, repl_way_v0_hi_lo}; // @[PRNG.scala:95:17]
wire [15:0] _repl_way_v0_T = {repl_way_v0_hi, repl_way_v0_lo}; // @[PRNG.scala:95:17]
wire [2:0] repl_way_v0 = _repl_way_v0_T[2:0]; // @[PRNG.scala:95:17]
wire [2:0] _repl_way_T = repl_way_v0; // @[ICache.scala:407:35, :411:40]
wire [2:0] _repl_way_T_3 = repl_way_v0; // @[ICache.scala:407:35, :411:13]
wire [8:0] _repl_way_T_1 = {_repl_way_T, refill_idx}; // @[ICache.scala:411:{36,40}, :859:21]
wire [2:0] _repl_way_T_7 = _repl_way_T_3; // @[ICache.scala:411:13]
wire [2:0] _repl_way_T_4 = repl_way_v0 | 3'h4; // @[ICache.scala:407:35, :411:40]
wire [8:0] _repl_way_T_5 = {_repl_way_T_4, refill_idx}; // @[ICache.scala:411:{36,40}, :859:21]
wire [2:0] repl_way = _repl_way_T_7; // @[ICache.scala:411:13]
wire [2:0] _repl_way_T_8 = repl_way_v0 | 3'h6; // @[ICache.scala:407:35, :411:40]
wire [8:0] _repl_way_T_9 = {_repl_way_T_8, refill_idx}; // @[ICache.scala:411:{36,40}, :859:21]
wire [2:0] way = repl_way; // @[ICache.scala:411:13, :585:20]
wire [2:0] way_1 = repl_way; // @[ICache.scala:411:13, :585:20]
wire [8:0] _GEN_0 = {repl_way, refill_idx}; // @[ICache.scala:411:13, :413:33, :859:21]
wire [8:0] _repl_way_T_11; // @[ICache.scala:413:33]
assign _repl_way_T_11 = _GEN_0; // @[ICache.scala:413:33]
wire [8:0] _vb_array_T; // @[ICache.scala:452:36]
assign _vb_array_T = _GEN_0; // @[ICache.scala:413:33, :452:36]
wire _repl_way_T_14 = ~_repl_way_T_13; // @[ICache.scala:413:11]
wire [5:0] _tag_rdata_WIRE; // @[ICache.scala:426:33]
wire _tag_rdata_T_2; // @[ICache.scala:426:83]
wire [20:0] enc_tag; // @[ICache.scala:435:34]
wire [5:0] _tag_rdata_T = io_req_bits_addr_0[11:6]; // @[ICache.scala:251:7, :426:42]
assign _tag_rdata_WIRE = _tag_rdata_T; // @[ICache.scala:426:{33,42}]
wire _tag_rdata_T_1 = ~refill_done; // @[ICache.scala:399:37, :426:70]
assign _tag_rdata_T_2 = _tag_rdata_T_1 & s0_valid; // @[Decoupled.scala:51:35]
reg accruedRefillError; // @[ICache.scala:428:31]
wire _refillError_T = |refill_cnt; // @[Edges.scala:234:25]
wire _refillError_T_1 = _refillError_T & accruedRefillError; // @[ICache.scala:428:31, :430:{58,64}]
wire refillError = masterNodeOut_d_bits_corrupt | _refillError_T_1; // @[ICache.scala:430:{43,64}]
assign enc_tag = {refillError, refill_tag}; // @[ICache.scala:388:33, :430:43, :435:34]
assign rockettile_icache_tag_array_MPORT_mask_0 = repl_way == 3'h0; // @[ICache.scala:411:13, :436:97]
assign rockettile_icache_tag_array_MPORT_mask_1 = repl_way == 3'h1; // @[ICache.scala:411:13, :436:97]
assign rockettile_icache_tag_array_MPORT_mask_2 = repl_way == 3'h2; // @[ICache.scala:411:13, :436:97]
assign rockettile_icache_tag_array_MPORT_mask_3 = repl_way == 3'h3; // @[ICache.scala:411:13, :436:97]
assign rockettile_icache_tag_array_MPORT_mask_4 = repl_way == 3'h4; // @[ICache.scala:411:13, :436:97]
assign rockettile_icache_tag_array_MPORT_mask_5 = repl_way == 3'h5; // @[ICache.scala:411:13, :436:97]
assign rockettile_icache_tag_array_MPORT_mask_6 = repl_way == 3'h6; // @[ICache.scala:411:13, :436:97]
assign rockettile_icache_tag_array_MPORT_mask_7 = &repl_way; // @[ICache.scala:411:13, :436:97]
wire _io_errors_bus_valid_T_1 = masterNodeOut_d_bits_denied | masterNodeOut_d_bits_corrupt; // @[ICache.scala:441:65]
assign _io_errors_bus_valid_T_2 = _io_errors_bus_valid_T & _io_errors_bus_valid_T_1; // @[Decoupled.scala:51:35]
assign io_errors_bus_valid_0 = _io_errors_bus_valid_T_2; // @[ICache.scala:251:7, :441:40]
wire [25:0] _io_errors_bus_bits_T = refill_paddr[31:6]; // @[ICache.scala:386:31, :442:40]
wire [25:0] _masterNodeOut_a_bits_T = refill_paddr[31:6]; // @[ICache.scala:386:31, :442:40, :769:47]
assign _io_errors_bus_bits_T_1 = {_io_errors_bus_bits_T, 6'h0}; // @[ICache.scala:442:{40,57}]
assign io_errors_bus_bits_0 = _io_errors_bus_bits_T_1; // @[ICache.scala:251:7, :442:57]
reg [511:0] vb_array; // @[ICache.scala:448:25]
wire _vb_array_T_1 = ~invalidated; // @[ICache.scala:367:24, :452:75]
wire _vb_array_T_2 = refill_done & _vb_array_T_1; // @[ICache.scala:399:37, :452:{72,75}]
wire [511:0] _vb_array_T_3 = 512'h1 << _vb_array_T; // @[ICache.scala:452:{32,36}]
wire [511:0] _vb_array_T_4 = vb_array | _vb_array_T_3; // @[ICache.scala:448:25, :452:32]
wire [511:0] _vb_array_T_5 = ~vb_array; // @[ICache.scala:448:25, :452:32]
wire [511:0] _vb_array_T_6 = _vb_array_T_5 | _vb_array_T_3; // @[ICache.scala:452:32]
wire [511:0] _vb_array_T_7 = ~_vb_array_T_6; // @[ICache.scala:452:32]
wire [511:0] _vb_array_T_8 = _vb_array_T_2 ? _vb_array_T_4 : _vb_array_T_7; // @[ICache.scala:452:{32,72}]
wire _s1_tl_error_0_T_1; // @[ICache.scala:518:32]
wire _s1_tl_error_1_T_1; // @[ICache.scala:518:32]
wire _s1_tl_error_2_T_1; // @[ICache.scala:518:32]
wire _s1_tl_error_3_T_1; // @[ICache.scala:518:32]
wire _s1_tl_error_4_T_1; // @[ICache.scala:518:32]
wire _s1_tl_error_5_T_1; // @[ICache.scala:518:32]
wire _s1_tl_error_6_T_1; // @[ICache.scala:518:32]
wire _s1_tl_error_7_T_1; // @[ICache.scala:518:32]
wire s1_tl_error_0; // @[ICache.scala:469:25]
wire s1_tl_error_1; // @[ICache.scala:469:25]
wire s1_tl_error_2; // @[ICache.scala:469:25]
wire s1_tl_error_3; // @[ICache.scala:469:25]
wire s1_tl_error_4; // @[ICache.scala:469:25]
wire s1_tl_error_5; // @[ICache.scala:469:25]
wire s1_tl_error_6; // @[ICache.scala:469:25]
wire s1_tl_error_7; // @[ICache.scala:469:25]
wire [31:0] s1_dout_0; // @[ICache.scala:473:21]
wire [31:0] s1_dout_1; // @[ICache.scala:473:21]
wire [31:0] s1_dout_2; // @[ICache.scala:473:21]
wire [31:0] s1_dout_3; // @[ICache.scala:473:21]
wire [31:0] s1_dout_4; // @[ICache.scala:473:21]
wire [31:0] s1_dout_5; // @[ICache.scala:473:21]
wire [31:0] s1_dout_6; // @[ICache.scala:473:21]
wire [31:0] s1_dout_7; // @[ICache.scala:473:21]
wire [5:0] s1_idx = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21]
wire [5:0] s1_idx_1 = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21]
wire [5:0] s1_idx_2 = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21]
wire [5:0] s1_idx_3 = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21]
wire [5:0] s1_idx_4 = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21]
wire [5:0] s1_idx_5 = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21]
wire [5:0] s1_idx_6 = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21]
wire [5:0] s1_idx_7 = io_s1_paddr_0[11:6]; // @[ICache.scala:251:7, :859:21]
wire [19:0] s1_tag = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30]
wire [19:0] s1_tag_1 = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30]
wire [19:0] s1_tag_2 = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30]
wire [19:0] s1_tag_3 = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30]
wire [19:0] s1_tag_4 = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30]
wire [19:0] s1_tag_5 = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30]
wire [19:0] s1_tag_6 = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30]
wire [19:0] s1_tag_7 = io_s1_paddr_0[31:12]; // @[ICache.scala:251:7, :493:30]
wire _scratchpadHit_T_3 = _scratchpadHit_T_2 == 3'h0; // @[package.scala:163:13]
wire [8:0] _scratchpadHit_T_5 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90]
wire [8:0] _scratchpadHit_T_16 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90]
wire [8:0] _scratchpadHit_T_27 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90]
wire [8:0] _scratchpadHit_T_38 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90]
wire [8:0] _scratchpadHit_T_49 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90]
wire [8:0] _scratchpadHit_T_60 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90]
wire [8:0] _scratchpadHit_T_71 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90]
wire [8:0] _scratchpadHit_T_82 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90]
wire [8:0] _s1_scratchpad_hit_T_1 = io_s1_paddr_0[14:6]; // @[ICache.scala:251:7, :302:90]
wire [2:0] _scratchpadHit_T_7 = io_s1_paddr_0[14:12]; // @[package.scala:163:13]
wire [2:0] _scratchpadHit_T_18 = io_s1_paddr_0[14:12]; // @[package.scala:163:13]
wire [2:0] _scratchpadHit_T_29 = io_s1_paddr_0[14:12]; // @[package.scala:163:13]
wire [2:0] _scratchpadHit_T_40 = io_s1_paddr_0[14:12]; // @[package.scala:163:13]
wire [2:0] _scratchpadHit_T_51 = io_s1_paddr_0[14:12]; // @[package.scala:163:13]
wire [2:0] _scratchpadHit_T_62 = io_s1_paddr_0[14:12]; // @[package.scala:163:13]
wire [2:0] _scratchpadHit_T_73 = io_s1_paddr_0[14:12]; // @[package.scala:163:13]
wire [2:0] _scratchpadHit_T_84 = io_s1_paddr_0[14:12]; // @[package.scala:163:13]
wire _scratchpadHit_T_8 = _scratchpadHit_T_7 == 3'h0; // @[package.scala:163:13]
wire [6:0] _s1_vb_T = {1'h0, s1_idx}; // @[ICache.scala:508:29, :859:21]
wire [8:0] _s1_vb_T_1 = {2'h0, _s1_vb_T}; // @[ICache.scala:508:{29,46}]
wire [511:0] _s1_vb_T_2 = vb_array >> _s1_vb_T_1; // @[ICache.scala:448:25, :508:{25,46}]
wire _s1_vb_T_3 = _s1_vb_T_2[0]; // @[ICache.scala:508:25]
wire s1_vb = _s1_vb_T_3; // @[ICache.scala:508:{25,71}]
wire tl_error = _rockettile_icache_tag_array_RW0_rdata[20]; // @[package.scala:163:13]
wire _s1_tl_error_0_T = tl_error; // @[package.scala:163:13]
wire [19:0] tag = _rockettile_icache_tag_array_RW0_rdata[19:0]; // @[package.scala:163:13]
wire _tagMatch_T = tag == s1_tag; // @[package.scala:163:13]
wire tagMatch = s1_vb & _tagMatch_T; // @[ICache.scala:508:71, :514:{26,33}]
assign _s1_tag_hit_0_T = tagMatch; // @[ICache.scala:514:26, :519:31]
assign _s1_tl_error_0_T_1 = tagMatch & _s1_tl_error_0_T; // @[ICache.scala:514:26, :518:{32,44}]
assign s1_tl_error_0 = _s1_tl_error_0_T_1; // @[ICache.scala:469:25, :518:32]
assign s1_tag_hit_0 = _s1_tag_hit_0_T; // @[ICache.scala:345:24, :519:31]
wire _scratchpadHit_T_14 = _scratchpadHit_T_13 == 3'h1; // @[package.scala:163:13]
wire _scratchpadHit_T_19 = _scratchpadHit_T_18 == 3'h1; // @[package.scala:163:13]
wire [6:0] _s1_vb_T_5 = {1'h1, s1_idx_1}; // @[ICache.scala:508:29, :859:21]
wire [8:0] _s1_vb_T_6 = {2'h0, _s1_vb_T_5}; // @[ICache.scala:508:{29,46}]
wire [511:0] _s1_vb_T_7 = vb_array >> _s1_vb_T_6; // @[ICache.scala:448:25, :508:{25,46}]
wire _s1_vb_T_8 = _s1_vb_T_7[0]; // @[ICache.scala:508:25]
wire s1_vb_1 = _s1_vb_T_8; // @[ICache.scala:508:{25,71}]
wire tl_error_1 = _rockettile_icache_tag_array_RW0_rdata[41]; // @[package.scala:163:13]
wire _s1_tl_error_1_T = tl_error_1; // @[package.scala:163:13]
wire [19:0] tag_1 = _rockettile_icache_tag_array_RW0_rdata[40:21]; // @[package.scala:163:13]
wire _tagMatch_T_1 = tag_1 == s1_tag_1; // @[package.scala:163:13]
wire tagMatch_1 = s1_vb_1 & _tagMatch_T_1; // @[ICache.scala:508:71, :514:{26,33}]
assign _s1_tag_hit_1_T = tagMatch_1; // @[ICache.scala:514:26, :519:31]
assign _s1_tl_error_1_T_1 = tagMatch_1 & _s1_tl_error_1_T; // @[ICache.scala:514:26, :518:{32,44}]
assign s1_tl_error_1 = _s1_tl_error_1_T_1; // @[ICache.scala:469:25, :518:32]
assign s1_tag_hit_1 = _s1_tag_hit_1_T; // @[ICache.scala:345:24, :519:31]
wire _scratchpadHit_T_25 = _scratchpadHit_T_24 == 3'h2; // @[package.scala:163:13]
wire _scratchpadHit_T_30 = _scratchpadHit_T_29 == 3'h2; // @[package.scala:163:13]
wire [7:0] _s1_vb_T_10 = {2'h2, s1_idx_2}; // @[ICache.scala:508:29, :859:21]
wire [8:0] _s1_vb_T_11 = {1'h0, _s1_vb_T_10}; // @[ICache.scala:508:{29,46}]
wire [511:0] _s1_vb_T_12 = vb_array >> _s1_vb_T_11; // @[ICache.scala:448:25, :508:{25,46}]
wire _s1_vb_T_13 = _s1_vb_T_12[0]; // @[ICache.scala:508:25]
wire s1_vb_2 = _s1_vb_T_13; // @[ICache.scala:508:{25,71}]
wire tl_error_2 = _rockettile_icache_tag_array_RW0_rdata[62]; // @[package.scala:163:13]
wire _s1_tl_error_2_T = tl_error_2; // @[package.scala:163:13]
wire [19:0] tag_2 = _rockettile_icache_tag_array_RW0_rdata[61:42]; // @[package.scala:163:13]
wire _tagMatch_T_2 = tag_2 == s1_tag_2; // @[package.scala:163:13]
wire tagMatch_2 = s1_vb_2 & _tagMatch_T_2; // @[ICache.scala:508:71, :514:{26,33}]
assign _s1_tag_hit_2_T = tagMatch_2; // @[ICache.scala:514:26, :519:31]
assign _s1_tl_error_2_T_1 = tagMatch_2 & _s1_tl_error_2_T; // @[ICache.scala:514:26, :518:{32,44}]
assign s1_tl_error_2 = _s1_tl_error_2_T_1; // @[ICache.scala:469:25, :518:32]
assign s1_tag_hit_2 = _s1_tag_hit_2_T; // @[ICache.scala:345:24, :519:31]
wire _scratchpadHit_T_36 = _scratchpadHit_T_35 == 3'h3; // @[package.scala:163:13]
wire _scratchpadHit_T_41 = _scratchpadHit_T_40 == 3'h3; // @[package.scala:163:13]
wire [7:0] _s1_vb_T_15 = {2'h3, s1_idx_3}; // @[ICache.scala:508:29, :859:21]
wire [8:0] _s1_vb_T_16 = {1'h0, _s1_vb_T_15}; // @[ICache.scala:508:{29,46}]
wire [511:0] _s1_vb_T_17 = vb_array >> _s1_vb_T_16; // @[ICache.scala:448:25, :508:{25,46}]
wire _s1_vb_T_18 = _s1_vb_T_17[0]; // @[ICache.scala:508:25]
wire s1_vb_3 = _s1_vb_T_18; // @[ICache.scala:508:{25,71}]
wire tl_error_3 = _rockettile_icache_tag_array_RW0_rdata[83]; // @[package.scala:163:13]
wire _s1_tl_error_3_T = tl_error_3; // @[package.scala:163:13]
wire [19:0] tag_3 = _rockettile_icache_tag_array_RW0_rdata[82:63]; // @[package.scala:163:13]
wire _tagMatch_T_3 = tag_3 == s1_tag_3; // @[package.scala:163:13]
wire tagMatch_3 = s1_vb_3 & _tagMatch_T_3; // @[ICache.scala:508:71, :514:{26,33}]
assign _s1_tag_hit_3_T = tagMatch_3; // @[ICache.scala:514:26, :519:31]
assign _s1_tl_error_3_T_1 = tagMatch_3 & _s1_tl_error_3_T; // @[ICache.scala:514:26, :518:{32,44}]
assign s1_tl_error_3 = _s1_tl_error_3_T_1; // @[ICache.scala:469:25, :518:32]
assign s1_tag_hit_3 = _s1_tag_hit_3_T; // @[ICache.scala:345:24, :519:31]
wire _scratchpadHit_T_47 = _scratchpadHit_T_46 == 3'h4; // @[package.scala:163:13]
wire _scratchpadHit_T_52 = _scratchpadHit_T_51 == 3'h4; // @[package.scala:163:13]
wire [8:0] _s1_vb_T_20 = {3'h4, s1_idx_4}; // @[ICache.scala:508:29, :859:21]
wire [511:0] _s1_vb_T_21 = vb_array >> _s1_vb_T_20; // @[ICache.scala:448:25, :508:{25,29}]
wire _s1_vb_T_22 = _s1_vb_T_21[0]; // @[ICache.scala:508:25]
wire s1_vb_4 = _s1_vb_T_22; // @[ICache.scala:508:{25,71}]
wire tl_error_4 = _rockettile_icache_tag_array_RW0_rdata[104]; // @[package.scala:163:13]
wire _s1_tl_error_4_T = tl_error_4; // @[package.scala:163:13]
wire [19:0] tag_4 = _rockettile_icache_tag_array_RW0_rdata[103:84]; // @[package.scala:163:13]
wire _tagMatch_T_4 = tag_4 == s1_tag_4; // @[package.scala:163:13]
wire tagMatch_4 = s1_vb_4 & _tagMatch_T_4; // @[ICache.scala:508:71, :514:{26,33}]
assign _s1_tag_hit_4_T = tagMatch_4; // @[ICache.scala:514:26, :519:31]
assign _s1_tl_error_4_T_1 = tagMatch_4 & _s1_tl_error_4_T; // @[ICache.scala:514:26, :518:{32,44}]
assign s1_tl_error_4 = _s1_tl_error_4_T_1; // @[ICache.scala:469:25, :518:32]
assign s1_tag_hit_4 = _s1_tag_hit_4_T; // @[ICache.scala:345:24, :519:31]
wire _scratchpadHit_T_58 = _scratchpadHit_T_57 == 3'h5; // @[package.scala:163:13]
wire _scratchpadHit_T_63 = _scratchpadHit_T_62 == 3'h5; // @[package.scala:163:13]
wire [8:0] _s1_vb_T_24 = {3'h5, s1_idx_5}; // @[ICache.scala:508:29, :859:21]
wire [511:0] _s1_vb_T_25 = vb_array >> _s1_vb_T_24; // @[ICache.scala:448:25, :508:{25,29}]
wire _s1_vb_T_26 = _s1_vb_T_25[0]; // @[ICache.scala:508:25]
wire s1_vb_5 = _s1_vb_T_26; // @[ICache.scala:508:{25,71}]
wire tl_error_5 = _rockettile_icache_tag_array_RW0_rdata[125]; // @[package.scala:163:13]
wire _s1_tl_error_5_T = tl_error_5; // @[package.scala:163:13]
wire [19:0] tag_5 = _rockettile_icache_tag_array_RW0_rdata[124:105]; // @[package.scala:163:13]
wire _tagMatch_T_5 = tag_5 == s1_tag_5; // @[package.scala:163:13]
wire tagMatch_5 = s1_vb_5 & _tagMatch_T_5; // @[ICache.scala:508:71, :514:{26,33}]
assign _s1_tag_hit_5_T = tagMatch_5; // @[ICache.scala:514:26, :519:31]
assign _s1_tl_error_5_T_1 = tagMatch_5 & _s1_tl_error_5_T; // @[ICache.scala:514:26, :518:{32,44}]
assign s1_tl_error_5 = _s1_tl_error_5_T_1; // @[ICache.scala:469:25, :518:32]
assign s1_tag_hit_5 = _s1_tag_hit_5_T; // @[ICache.scala:345:24, :519:31]
wire _scratchpadHit_T_69 = _scratchpadHit_T_68 == 3'h6; // @[package.scala:163:13]
wire _scratchpadHit_T_74 = _scratchpadHit_T_73 == 3'h6; // @[package.scala:163:13]
wire [8:0] _s1_vb_T_28 = {3'h6, s1_idx_6}; // @[ICache.scala:508:29, :859:21]
wire [511:0] _s1_vb_T_29 = vb_array >> _s1_vb_T_28; // @[ICache.scala:448:25, :508:{25,29}]
wire _s1_vb_T_30 = _s1_vb_T_29[0]; // @[ICache.scala:508:25]
wire s1_vb_6 = _s1_vb_T_30; // @[ICache.scala:508:{25,71}]
wire tl_error_6 = _rockettile_icache_tag_array_RW0_rdata[146]; // @[package.scala:163:13]
wire _s1_tl_error_6_T = tl_error_6; // @[package.scala:163:13]
wire [19:0] tag_6 = _rockettile_icache_tag_array_RW0_rdata[145:126]; // @[package.scala:163:13]
wire _tagMatch_T_6 = tag_6 == s1_tag_6; // @[package.scala:163:13]
wire tagMatch_6 = s1_vb_6 & _tagMatch_T_6; // @[ICache.scala:508:71, :514:{26,33}]
assign _s1_tag_hit_6_T = tagMatch_6; // @[ICache.scala:514:26, :519:31]
assign _s1_tl_error_6_T_1 = tagMatch_6 & _s1_tl_error_6_T; // @[ICache.scala:514:26, :518:{32,44}]
assign s1_tl_error_6 = _s1_tl_error_6_T_1; // @[ICache.scala:469:25, :518:32]
assign s1_tag_hit_6 = _s1_tag_hit_6_T; // @[ICache.scala:345:24, :519:31]
wire _scratchpadHit_T_80 = &_scratchpadHit_T_79; // @[package.scala:163:13]
wire _scratchpadHit_T_85 = &_scratchpadHit_T_84; // @[package.scala:163:13]
wire [8:0] _s1_vb_T_32 = {3'h7, s1_idx_7}; // @[ICache.scala:508:29, :859:21]
wire [511:0] _s1_vb_T_33 = vb_array >> _s1_vb_T_32; // @[ICache.scala:448:25, :508:{25,29}]
wire _s1_vb_T_34 = _s1_vb_T_33[0]; // @[ICache.scala:508:25]
wire s1_vb_7 = _s1_vb_T_34; // @[ICache.scala:508:{25,71}]
wire tl_error_7 = _rockettile_icache_tag_array_RW0_rdata[167]; // @[package.scala:163:13]
wire _s1_tl_error_7_T = tl_error_7; // @[package.scala:163:13]
wire [19:0] tag_7 = _rockettile_icache_tag_array_RW0_rdata[166:147]; // @[package.scala:163:13]
wire _tagMatch_T_7 = tag_7 == s1_tag_7; // @[package.scala:163:13]
wire tagMatch_7 = s1_vb_7 & _tagMatch_T_7; // @[ICache.scala:508:71, :514:{26,33}]
assign _s1_tag_hit_7_T = tagMatch_7; // @[ICache.scala:514:26, :519:31]
assign _s1_tl_error_7_T_1 = tagMatch_7 & _s1_tl_error_7_T; // @[ICache.scala:514:26, :518:{32,44}]
assign s1_tl_error_7 = _s1_tl_error_7_T_1; // @[ICache.scala:469:25, :518:32]
assign s1_tag_hit_7 = _s1_tag_hit_7_T; // @[ICache.scala:345:24, :519:31] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_177 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_317
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_177( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_317 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_19 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[7]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
node _source_ok_T_27 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_28 = or(_source_ok_T_27, _source_ok_WIRE[2])
node _source_ok_T_29 = or(_source_ok_T_28, _source_ok_WIRE[3])
node _source_ok_T_30 = or(_source_ok_T_29, _source_ok_WIRE[4])
node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[5])
node source_ok = or(_source_ok_T_31, _source_ok_WIRE[6])
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = and(_T_11, _T_24)
node _T_81 = and(_T_80, _T_37)
node _T_82 = and(_T_81, _T_50)
node _T_83 = and(_T_82, _T_63)
node _T_84 = and(_T_83, _T_71)
node _T_85 = and(_T_84, _T_79)
node _T_86 = asUInt(reset)
node _T_87 = eq(_T_86, UInt<1>(0h0))
when _T_87 :
node _T_88 = eq(_T_85, UInt<1>(0h0))
when _T_88 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_85, UInt<1>(0h1), "") : assert_1
node _T_89 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_89 :
node _T_90 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_91 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_92 = and(_T_90, _T_91)
node _T_93 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_94 = shr(io.in.a.bits.source, 2)
node _T_95 = eq(_T_94, UInt<1>(0h0))
node _T_96 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_97 = and(_T_95, _T_96)
node _T_98 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_99 = and(_T_97, _T_98)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_100 = shr(io.in.a.bits.source, 2)
node _T_101 = eq(_T_100, UInt<1>(0h1))
node _T_102 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_103 = and(_T_101, _T_102)
node _T_104 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_105 = and(_T_103, _T_104)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_106 = shr(io.in.a.bits.source, 2)
node _T_107 = eq(_T_106, UInt<2>(0h2))
node _T_108 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_109 = and(_T_107, _T_108)
node _T_110 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_111 = and(_T_109, _T_110)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_112 = shr(io.in.a.bits.source, 2)
node _T_113 = eq(_T_112, UInt<2>(0h3))
node _T_114 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_115 = and(_T_113, _T_114)
node _T_116 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_119 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_120 = or(_T_93, _T_99)
node _T_121 = or(_T_120, _T_105)
node _T_122 = or(_T_121, _T_111)
node _T_123 = or(_T_122, _T_117)
node _T_124 = or(_T_123, _T_118)
node _T_125 = or(_T_124, _T_119)
node _T_126 = and(_T_92, _T_125)
node _T_127 = or(UInt<1>(0h0), _T_126)
node _T_128 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_129 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_130 = cvt(_T_129)
node _T_131 = and(_T_130, asSInt(UInt<14>(0h2000)))
node _T_132 = asSInt(_T_131)
node _T_133 = eq(_T_132, asSInt(UInt<1>(0h0)))
node _T_134 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<13>(0h1000)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<17>(0h10000)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<18>(0h2f000)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<17>(0h10000)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<27>(0h4000000)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<13>(0h1000)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_165 = cvt(_T_164)
node _T_166 = and(_T_165, asSInt(UInt<19>(0h40000)))
node _T_167 = asSInt(_T_166)
node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0)))
node _T_169 = or(_T_133, _T_138)
node _T_170 = or(_T_169, _T_143)
node _T_171 = or(_T_170, _T_148)
node _T_172 = or(_T_171, _T_153)
node _T_173 = or(_T_172, _T_158)
node _T_174 = or(_T_173, _T_163)
node _T_175 = or(_T_174, _T_168)
node _T_176 = and(_T_128, _T_175)
node _T_177 = or(UInt<1>(0h0), _T_176)
node _T_178 = and(_T_127, _T_177)
node _T_179 = asUInt(reset)
node _T_180 = eq(_T_179, UInt<1>(0h0))
when _T_180 :
node _T_181 = eq(_T_178, UInt<1>(0h0))
when _T_181 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_178, UInt<1>(0h1), "") : assert_2
node _T_182 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_183 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_184 = and(_T_182, _T_183)
node _T_185 = or(UInt<1>(0h0), _T_184)
node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<14>(0h2000)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_192 = cvt(_T_191)
node _T_193 = and(_T_192, asSInt(UInt<13>(0h1000)))
node _T_194 = asSInt(_T_193)
node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0)))
node _T_196 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_197 = cvt(_T_196)
node _T_198 = and(_T_197, asSInt(UInt<17>(0h10000)))
node _T_199 = asSInt(_T_198)
node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0)))
node _T_201 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_202 = cvt(_T_201)
node _T_203 = and(_T_202, asSInt(UInt<18>(0h2f000)))
node _T_204 = asSInt(_T_203)
node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0)))
node _T_206 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_207 = cvt(_T_206)
node _T_208 = and(_T_207, asSInt(UInt<17>(0h10000)))
node _T_209 = asSInt(_T_208)
node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0)))
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<27>(0h4000000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_217 = cvt(_T_216)
node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000)))
node _T_219 = asSInt(_T_218)
node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0)))
node _T_221 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_222 = cvt(_T_221)
node _T_223 = and(_T_222, asSInt(UInt<19>(0h40000)))
node _T_224 = asSInt(_T_223)
node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0)))
node _T_226 = or(_T_190, _T_195)
node _T_227 = or(_T_226, _T_200)
node _T_228 = or(_T_227, _T_205)
node _T_229 = or(_T_228, _T_210)
node _T_230 = or(_T_229, _T_215)
node _T_231 = or(_T_230, _T_220)
node _T_232 = or(_T_231, _T_225)
node _T_233 = and(_T_185, _T_232)
node _T_234 = or(UInt<1>(0h0), _T_233)
node _T_235 = and(UInt<1>(0h0), _T_234)
node _T_236 = asUInt(reset)
node _T_237 = eq(_T_236, UInt<1>(0h0))
when _T_237 :
node _T_238 = eq(_T_235, UInt<1>(0h0))
when _T_238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_235, UInt<1>(0h1), "") : assert_3
node _T_239 = asUInt(reset)
node _T_240 = eq(_T_239, UInt<1>(0h0))
when _T_240 :
node _T_241 = eq(source_ok, UInt<1>(0h0))
when _T_241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_243 = asUInt(reset)
node _T_244 = eq(_T_243, UInt<1>(0h0))
when _T_244 :
node _T_245 = eq(_T_242, UInt<1>(0h0))
when _T_245 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_242, UInt<1>(0h1), "") : assert_5
node _T_246 = asUInt(reset)
node _T_247 = eq(_T_246, UInt<1>(0h0))
when _T_247 :
node _T_248 = eq(is_aligned, UInt<1>(0h0))
when _T_248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_250 = asUInt(reset)
node _T_251 = eq(_T_250, UInt<1>(0h0))
when _T_251 :
node _T_252 = eq(_T_249, UInt<1>(0h0))
when _T_252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_249, UInt<1>(0h1), "") : assert_7
node _T_253 = not(io.in.a.bits.mask)
node _T_254 = eq(_T_253, UInt<1>(0h0))
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_254, UInt<1>(0h1), "") : assert_8
node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_258, UInt<1>(0h1), "") : assert_9
node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_262 :
node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_265 = and(_T_263, _T_264)
node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_267 = shr(io.in.a.bits.source, 2)
node _T_268 = eq(_T_267, UInt<1>(0h0))
node _T_269 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_270 = and(_T_268, _T_269)
node _T_271 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_272 = and(_T_270, _T_271)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_273 = shr(io.in.a.bits.source, 2)
node _T_274 = eq(_T_273, UInt<1>(0h1))
node _T_275 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_276 = and(_T_274, _T_275)
node _T_277 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_278 = and(_T_276, _T_277)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_279 = shr(io.in.a.bits.source, 2)
node _T_280 = eq(_T_279, UInt<2>(0h2))
node _T_281 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_282 = and(_T_280, _T_281)
node _T_283 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_284 = and(_T_282, _T_283)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_285 = shr(io.in.a.bits.source, 2)
node _T_286 = eq(_T_285, UInt<2>(0h3))
node _T_287 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_288 = and(_T_286, _T_287)
node _T_289 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_292 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_293 = or(_T_266, _T_272)
node _T_294 = or(_T_293, _T_278)
node _T_295 = or(_T_294, _T_284)
node _T_296 = or(_T_295, _T_290)
node _T_297 = or(_T_296, _T_291)
node _T_298 = or(_T_297, _T_292)
node _T_299 = and(_T_265, _T_298)
node _T_300 = or(UInt<1>(0h0), _T_299)
node _T_301 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_302 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_303 = cvt(_T_302)
node _T_304 = and(_T_303, asSInt(UInt<14>(0h2000)))
node _T_305 = asSInt(_T_304)
node _T_306 = eq(_T_305, asSInt(UInt<1>(0h0)))
node _T_307 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_308 = cvt(_T_307)
node _T_309 = and(_T_308, asSInt(UInt<13>(0h1000)))
node _T_310 = asSInt(_T_309)
node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0)))
node _T_312 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_313 = cvt(_T_312)
node _T_314 = and(_T_313, asSInt(UInt<17>(0h10000)))
node _T_315 = asSInt(_T_314)
node _T_316 = eq(_T_315, asSInt(UInt<1>(0h0)))
node _T_317 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_318 = cvt(_T_317)
node _T_319 = and(_T_318, asSInt(UInt<18>(0h2f000)))
node _T_320 = asSInt(_T_319)
node _T_321 = eq(_T_320, asSInt(UInt<1>(0h0)))
node _T_322 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_323 = cvt(_T_322)
node _T_324 = and(_T_323, asSInt(UInt<17>(0h10000)))
node _T_325 = asSInt(_T_324)
node _T_326 = eq(_T_325, asSInt(UInt<1>(0h0)))
node _T_327 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_328 = cvt(_T_327)
node _T_329 = and(_T_328, asSInt(UInt<27>(0h4000000)))
node _T_330 = asSInt(_T_329)
node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0)))
node _T_332 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_333 = cvt(_T_332)
node _T_334 = and(_T_333, asSInt(UInt<13>(0h1000)))
node _T_335 = asSInt(_T_334)
node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0)))
node _T_337 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_338 = cvt(_T_337)
node _T_339 = and(_T_338, asSInt(UInt<19>(0h40000)))
node _T_340 = asSInt(_T_339)
node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0)))
node _T_342 = or(_T_306, _T_311)
node _T_343 = or(_T_342, _T_316)
node _T_344 = or(_T_343, _T_321)
node _T_345 = or(_T_344, _T_326)
node _T_346 = or(_T_345, _T_331)
node _T_347 = or(_T_346, _T_336)
node _T_348 = or(_T_347, _T_341)
node _T_349 = and(_T_301, _T_348)
node _T_350 = or(UInt<1>(0h0), _T_349)
node _T_351 = and(_T_300, _T_350)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_351, UInt<1>(0h1), "") : assert_10
node _T_355 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_356 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_357 = and(_T_355, _T_356)
node _T_358 = or(UInt<1>(0h0), _T_357)
node _T_359 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_360 = cvt(_T_359)
node _T_361 = and(_T_360, asSInt(UInt<14>(0h2000)))
node _T_362 = asSInt(_T_361)
node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0)))
node _T_364 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_365 = cvt(_T_364)
node _T_366 = and(_T_365, asSInt(UInt<13>(0h1000)))
node _T_367 = asSInt(_T_366)
node _T_368 = eq(_T_367, asSInt(UInt<1>(0h0)))
node _T_369 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_370 = cvt(_T_369)
node _T_371 = and(_T_370, asSInt(UInt<17>(0h10000)))
node _T_372 = asSInt(_T_371)
node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0)))
node _T_374 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_375 = cvt(_T_374)
node _T_376 = and(_T_375, asSInt(UInt<18>(0h2f000)))
node _T_377 = asSInt(_T_376)
node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0)))
node _T_379 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_380 = cvt(_T_379)
node _T_381 = and(_T_380, asSInt(UInt<17>(0h10000)))
node _T_382 = asSInt(_T_381)
node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0)))
node _T_384 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_385 = cvt(_T_384)
node _T_386 = and(_T_385, asSInt(UInt<27>(0h4000000)))
node _T_387 = asSInt(_T_386)
node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0)))
node _T_389 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<13>(0h1000)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<19>(0h40000)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = or(_T_363, _T_368)
node _T_400 = or(_T_399, _T_373)
node _T_401 = or(_T_400, _T_378)
node _T_402 = or(_T_401, _T_383)
node _T_403 = or(_T_402, _T_388)
node _T_404 = or(_T_403, _T_393)
node _T_405 = or(_T_404, _T_398)
node _T_406 = and(_T_358, _T_405)
node _T_407 = or(UInt<1>(0h0), _T_406)
node _T_408 = and(UInt<1>(0h0), _T_407)
node _T_409 = asUInt(reset)
node _T_410 = eq(_T_409, UInt<1>(0h0))
when _T_410 :
node _T_411 = eq(_T_408, UInt<1>(0h0))
when _T_411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_408, UInt<1>(0h1), "") : assert_11
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(source_ok, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_415 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(_T_415, UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_415, UInt<1>(0h1), "") : assert_13
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(is_aligned, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_422 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_423 = asUInt(reset)
node _T_424 = eq(_T_423, UInt<1>(0h0))
when _T_424 :
node _T_425 = eq(_T_422, UInt<1>(0h0))
when _T_425 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_422, UInt<1>(0h1), "") : assert_15
node _T_426 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_426, UInt<1>(0h1), "") : assert_16
node _T_430 = not(io.in.a.bits.mask)
node _T_431 = eq(_T_430, UInt<1>(0h0))
node _T_432 = asUInt(reset)
node _T_433 = eq(_T_432, UInt<1>(0h0))
when _T_433 :
node _T_434 = eq(_T_431, UInt<1>(0h0))
when _T_434 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_431, UInt<1>(0h1), "") : assert_17
node _T_435 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_436 = asUInt(reset)
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(_T_435, UInt<1>(0h0))
when _T_438 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_435, UInt<1>(0h1), "") : assert_18
node _T_439 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_439 :
node _T_440 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_441 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_442 = and(_T_440, _T_441)
node _T_443 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_444 = shr(io.in.a.bits.source, 2)
node _T_445 = eq(_T_444, UInt<1>(0h0))
node _T_446 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_447 = and(_T_445, _T_446)
node _T_448 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_449 = and(_T_447, _T_448)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_450 = shr(io.in.a.bits.source, 2)
node _T_451 = eq(_T_450, UInt<1>(0h1))
node _T_452 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_453 = and(_T_451, _T_452)
node _T_454 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_455 = and(_T_453, _T_454)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_456 = shr(io.in.a.bits.source, 2)
node _T_457 = eq(_T_456, UInt<2>(0h2))
node _T_458 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_459 = and(_T_457, _T_458)
node _T_460 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_461 = and(_T_459, _T_460)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_462 = shr(io.in.a.bits.source, 2)
node _T_463 = eq(_T_462, UInt<2>(0h3))
node _T_464 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_465 = and(_T_463, _T_464)
node _T_466 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_467 = and(_T_465, _T_466)
node _T_468 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_469 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_470 = or(_T_443, _T_449)
node _T_471 = or(_T_470, _T_455)
node _T_472 = or(_T_471, _T_461)
node _T_473 = or(_T_472, _T_467)
node _T_474 = or(_T_473, _T_468)
node _T_475 = or(_T_474, _T_469)
node _T_476 = and(_T_442, _T_475)
node _T_477 = or(UInt<1>(0h0), _T_476)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_477, UInt<1>(0h1), "") : assert_19
node _T_481 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_482 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_483 = and(_T_481, _T_482)
node _T_484 = or(UInt<1>(0h0), _T_483)
node _T_485 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_486 = cvt(_T_485)
node _T_487 = and(_T_486, asSInt(UInt<13>(0h1000)))
node _T_488 = asSInt(_T_487)
node _T_489 = eq(_T_488, asSInt(UInt<1>(0h0)))
node _T_490 = and(_T_484, _T_489)
node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_492 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_493 = and(_T_491, _T_492)
node _T_494 = or(UInt<1>(0h0), _T_493)
node _T_495 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_496 = cvt(_T_495)
node _T_497 = and(_T_496, asSInt(UInt<14>(0h2000)))
node _T_498 = asSInt(_T_497)
node _T_499 = eq(_T_498, asSInt(UInt<1>(0h0)))
node _T_500 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_501 = cvt(_T_500)
node _T_502 = and(_T_501, asSInt(UInt<17>(0h10000)))
node _T_503 = asSInt(_T_502)
node _T_504 = eq(_T_503, asSInt(UInt<1>(0h0)))
node _T_505 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_506 = cvt(_T_505)
node _T_507 = and(_T_506, asSInt(UInt<18>(0h2f000)))
node _T_508 = asSInt(_T_507)
node _T_509 = eq(_T_508, asSInt(UInt<1>(0h0)))
node _T_510 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_511 = cvt(_T_510)
node _T_512 = and(_T_511, asSInt(UInt<17>(0h10000)))
node _T_513 = asSInt(_T_512)
node _T_514 = eq(_T_513, asSInt(UInt<1>(0h0)))
node _T_515 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_516 = cvt(_T_515)
node _T_517 = and(_T_516, asSInt(UInt<27>(0h4000000)))
node _T_518 = asSInt(_T_517)
node _T_519 = eq(_T_518, asSInt(UInt<1>(0h0)))
node _T_520 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_521 = cvt(_T_520)
node _T_522 = and(_T_521, asSInt(UInt<13>(0h1000)))
node _T_523 = asSInt(_T_522)
node _T_524 = eq(_T_523, asSInt(UInt<1>(0h0)))
node _T_525 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_526 = cvt(_T_525)
node _T_527 = and(_T_526, asSInt(UInt<19>(0h40000)))
node _T_528 = asSInt(_T_527)
node _T_529 = eq(_T_528, asSInt(UInt<1>(0h0)))
node _T_530 = or(_T_499, _T_504)
node _T_531 = or(_T_530, _T_509)
node _T_532 = or(_T_531, _T_514)
node _T_533 = or(_T_532, _T_519)
node _T_534 = or(_T_533, _T_524)
node _T_535 = or(_T_534, _T_529)
node _T_536 = and(_T_494, _T_535)
node _T_537 = or(UInt<1>(0h0), _T_490)
node _T_538 = or(_T_537, _T_536)
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_538, UInt<1>(0h1), "") : assert_20
node _T_542 = asUInt(reset)
node _T_543 = eq(_T_542, UInt<1>(0h0))
when _T_543 :
node _T_544 = eq(source_ok, UInt<1>(0h0))
when _T_544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(is_aligned, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_548 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_548, UInt<1>(0h1), "") : assert_23
node _T_552 = eq(io.in.a.bits.mask, mask)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_552, UInt<1>(0h1), "") : assert_24
node _T_556 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_556, UInt<1>(0h1), "") : assert_25
node _T_560 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_560 :
node _T_561 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_562 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_563 = and(_T_561, _T_562)
node _T_564 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_565 = shr(io.in.a.bits.source, 2)
node _T_566 = eq(_T_565, UInt<1>(0h0))
node _T_567 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_568 = and(_T_566, _T_567)
node _T_569 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_570 = and(_T_568, _T_569)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_571 = shr(io.in.a.bits.source, 2)
node _T_572 = eq(_T_571, UInt<1>(0h1))
node _T_573 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_574 = and(_T_572, _T_573)
node _T_575 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_576 = and(_T_574, _T_575)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_577 = shr(io.in.a.bits.source, 2)
node _T_578 = eq(_T_577, UInt<2>(0h2))
node _T_579 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_580 = and(_T_578, _T_579)
node _T_581 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_582 = and(_T_580, _T_581)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_583 = shr(io.in.a.bits.source, 2)
node _T_584 = eq(_T_583, UInt<2>(0h3))
node _T_585 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_586 = and(_T_584, _T_585)
node _T_587 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_588 = and(_T_586, _T_587)
node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_590 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_591 = or(_T_564, _T_570)
node _T_592 = or(_T_591, _T_576)
node _T_593 = or(_T_592, _T_582)
node _T_594 = or(_T_593, _T_588)
node _T_595 = or(_T_594, _T_589)
node _T_596 = or(_T_595, _T_590)
node _T_597 = and(_T_563, _T_596)
node _T_598 = or(UInt<1>(0h0), _T_597)
node _T_599 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_600 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_601 = and(_T_599, _T_600)
node _T_602 = or(UInt<1>(0h0), _T_601)
node _T_603 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_604 = cvt(_T_603)
node _T_605 = and(_T_604, asSInt(UInt<13>(0h1000)))
node _T_606 = asSInt(_T_605)
node _T_607 = eq(_T_606, asSInt(UInt<1>(0h0)))
node _T_608 = and(_T_602, _T_607)
node _T_609 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_610 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_611 = and(_T_609, _T_610)
node _T_612 = or(UInt<1>(0h0), _T_611)
node _T_613 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_614 = cvt(_T_613)
node _T_615 = and(_T_614, asSInt(UInt<14>(0h2000)))
node _T_616 = asSInt(_T_615)
node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0)))
node _T_618 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_619 = cvt(_T_618)
node _T_620 = and(_T_619, asSInt(UInt<18>(0h2f000)))
node _T_621 = asSInt(_T_620)
node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0)))
node _T_623 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_624 = cvt(_T_623)
node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000)))
node _T_626 = asSInt(_T_625)
node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0)))
node _T_628 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_629 = cvt(_T_628)
node _T_630 = and(_T_629, asSInt(UInt<27>(0h4000000)))
node _T_631 = asSInt(_T_630)
node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0)))
node _T_633 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_634 = cvt(_T_633)
node _T_635 = and(_T_634, asSInt(UInt<13>(0h1000)))
node _T_636 = asSInt(_T_635)
node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0)))
node _T_638 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_639 = cvt(_T_638)
node _T_640 = and(_T_639, asSInt(UInt<19>(0h40000)))
node _T_641 = asSInt(_T_640)
node _T_642 = eq(_T_641, asSInt(UInt<1>(0h0)))
node _T_643 = or(_T_617, _T_622)
node _T_644 = or(_T_643, _T_627)
node _T_645 = or(_T_644, _T_632)
node _T_646 = or(_T_645, _T_637)
node _T_647 = or(_T_646, _T_642)
node _T_648 = and(_T_612, _T_647)
node _T_649 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_650 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_651 = cvt(_T_650)
node _T_652 = and(_T_651, asSInt(UInt<17>(0h10000)))
node _T_653 = asSInt(_T_652)
node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0)))
node _T_655 = and(_T_649, _T_654)
node _T_656 = or(UInt<1>(0h0), _T_608)
node _T_657 = or(_T_656, _T_648)
node _T_658 = or(_T_657, _T_655)
node _T_659 = and(_T_598, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_659, UInt<1>(0h1), "") : assert_26
node _T_663 = asUInt(reset)
node _T_664 = eq(_T_663, UInt<1>(0h0))
when _T_664 :
node _T_665 = eq(source_ok, UInt<1>(0h0))
when _T_665 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(is_aligned, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_669 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_669, UInt<1>(0h1), "") : assert_29
node _T_673 = eq(io.in.a.bits.mask, mask)
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_673, UInt<1>(0h1), "") : assert_30
node _T_677 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_677 :
node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_679 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_680 = and(_T_678, _T_679)
node _T_681 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_682 = shr(io.in.a.bits.source, 2)
node _T_683 = eq(_T_682, UInt<1>(0h0))
node _T_684 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_685 = and(_T_683, _T_684)
node _T_686 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_687 = and(_T_685, _T_686)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_688 = shr(io.in.a.bits.source, 2)
node _T_689 = eq(_T_688, UInt<1>(0h1))
node _T_690 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_691 = and(_T_689, _T_690)
node _T_692 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_693 = and(_T_691, _T_692)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_694 = shr(io.in.a.bits.source, 2)
node _T_695 = eq(_T_694, UInt<2>(0h2))
node _T_696 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_697 = and(_T_695, _T_696)
node _T_698 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_699 = and(_T_697, _T_698)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_700 = shr(io.in.a.bits.source, 2)
node _T_701 = eq(_T_700, UInt<2>(0h3))
node _T_702 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_703 = and(_T_701, _T_702)
node _T_704 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_705 = and(_T_703, _T_704)
node _T_706 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_707 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_708 = or(_T_681, _T_687)
node _T_709 = or(_T_708, _T_693)
node _T_710 = or(_T_709, _T_699)
node _T_711 = or(_T_710, _T_705)
node _T_712 = or(_T_711, _T_706)
node _T_713 = or(_T_712, _T_707)
node _T_714 = and(_T_680, _T_713)
node _T_715 = or(UInt<1>(0h0), _T_714)
node _T_716 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_717 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_718 = and(_T_716, _T_717)
node _T_719 = or(UInt<1>(0h0), _T_718)
node _T_720 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_721 = cvt(_T_720)
node _T_722 = and(_T_721, asSInt(UInt<13>(0h1000)))
node _T_723 = asSInt(_T_722)
node _T_724 = eq(_T_723, asSInt(UInt<1>(0h0)))
node _T_725 = and(_T_719, _T_724)
node _T_726 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_727 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_728 = and(_T_726, _T_727)
node _T_729 = or(UInt<1>(0h0), _T_728)
node _T_730 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_731 = cvt(_T_730)
node _T_732 = and(_T_731, asSInt(UInt<14>(0h2000)))
node _T_733 = asSInt(_T_732)
node _T_734 = eq(_T_733, asSInt(UInt<1>(0h0)))
node _T_735 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_736 = cvt(_T_735)
node _T_737 = and(_T_736, asSInt(UInt<18>(0h2f000)))
node _T_738 = asSInt(_T_737)
node _T_739 = eq(_T_738, asSInt(UInt<1>(0h0)))
node _T_740 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_741 = cvt(_T_740)
node _T_742 = and(_T_741, asSInt(UInt<17>(0h10000)))
node _T_743 = asSInt(_T_742)
node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0)))
node _T_745 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_746 = cvt(_T_745)
node _T_747 = and(_T_746, asSInt(UInt<27>(0h4000000)))
node _T_748 = asSInt(_T_747)
node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0)))
node _T_750 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_751 = cvt(_T_750)
node _T_752 = and(_T_751, asSInt(UInt<13>(0h1000)))
node _T_753 = asSInt(_T_752)
node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0)))
node _T_755 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_756 = cvt(_T_755)
node _T_757 = and(_T_756, asSInt(UInt<19>(0h40000)))
node _T_758 = asSInt(_T_757)
node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0)))
node _T_760 = or(_T_734, _T_739)
node _T_761 = or(_T_760, _T_744)
node _T_762 = or(_T_761, _T_749)
node _T_763 = or(_T_762, _T_754)
node _T_764 = or(_T_763, _T_759)
node _T_765 = and(_T_729, _T_764)
node _T_766 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_767 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_768 = cvt(_T_767)
node _T_769 = and(_T_768, asSInt(UInt<17>(0h10000)))
node _T_770 = asSInt(_T_769)
node _T_771 = eq(_T_770, asSInt(UInt<1>(0h0)))
node _T_772 = and(_T_766, _T_771)
node _T_773 = or(UInt<1>(0h0), _T_725)
node _T_774 = or(_T_773, _T_765)
node _T_775 = or(_T_774, _T_772)
node _T_776 = and(_T_715, _T_775)
node _T_777 = asUInt(reset)
node _T_778 = eq(_T_777, UInt<1>(0h0))
when _T_778 :
node _T_779 = eq(_T_776, UInt<1>(0h0))
when _T_779 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_776, UInt<1>(0h1), "") : assert_31
node _T_780 = asUInt(reset)
node _T_781 = eq(_T_780, UInt<1>(0h0))
when _T_781 :
node _T_782 = eq(source_ok, UInt<1>(0h0))
when _T_782 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_783 = asUInt(reset)
node _T_784 = eq(_T_783, UInt<1>(0h0))
when _T_784 :
node _T_785 = eq(is_aligned, UInt<1>(0h0))
when _T_785 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_786 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_787 = asUInt(reset)
node _T_788 = eq(_T_787, UInt<1>(0h0))
when _T_788 :
node _T_789 = eq(_T_786, UInt<1>(0h0))
when _T_789 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_786, UInt<1>(0h1), "") : assert_34
node _T_790 = not(mask)
node _T_791 = and(io.in.a.bits.mask, _T_790)
node _T_792 = eq(_T_791, UInt<1>(0h0))
node _T_793 = asUInt(reset)
node _T_794 = eq(_T_793, UInt<1>(0h0))
when _T_794 :
node _T_795 = eq(_T_792, UInt<1>(0h0))
when _T_795 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_792, UInt<1>(0h1), "") : assert_35
node _T_796 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_796 :
node _T_797 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_798 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_799 = and(_T_797, _T_798)
node _T_800 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_801 = shr(io.in.a.bits.source, 2)
node _T_802 = eq(_T_801, UInt<1>(0h0))
node _T_803 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_804 = and(_T_802, _T_803)
node _T_805 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_806 = and(_T_804, _T_805)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_807 = shr(io.in.a.bits.source, 2)
node _T_808 = eq(_T_807, UInt<1>(0h1))
node _T_809 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_810 = and(_T_808, _T_809)
node _T_811 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_812 = and(_T_810, _T_811)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_813 = shr(io.in.a.bits.source, 2)
node _T_814 = eq(_T_813, UInt<2>(0h2))
node _T_815 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_816 = and(_T_814, _T_815)
node _T_817 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_818 = and(_T_816, _T_817)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_819 = shr(io.in.a.bits.source, 2)
node _T_820 = eq(_T_819, UInt<2>(0h3))
node _T_821 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_822 = and(_T_820, _T_821)
node _T_823 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_824 = and(_T_822, _T_823)
node _T_825 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_826 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_827 = or(_T_800, _T_806)
node _T_828 = or(_T_827, _T_812)
node _T_829 = or(_T_828, _T_818)
node _T_830 = or(_T_829, _T_824)
node _T_831 = or(_T_830, _T_825)
node _T_832 = or(_T_831, _T_826)
node _T_833 = and(_T_799, _T_832)
node _T_834 = or(UInt<1>(0h0), _T_833)
node _T_835 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_836 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_837 = and(_T_835, _T_836)
node _T_838 = or(UInt<1>(0h0), _T_837)
node _T_839 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_840 = cvt(_T_839)
node _T_841 = and(_T_840, asSInt(UInt<15>(0h5000)))
node _T_842 = asSInt(_T_841)
node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0)))
node _T_844 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_845 = cvt(_T_844)
node _T_846 = and(_T_845, asSInt(UInt<13>(0h1000)))
node _T_847 = asSInt(_T_846)
node _T_848 = eq(_T_847, asSInt(UInt<1>(0h0)))
node _T_849 = or(_T_843, _T_848)
node _T_850 = and(_T_838, _T_849)
node _T_851 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_852 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_853 = cvt(_T_852)
node _T_854 = and(_T_853, asSInt(UInt<13>(0h1000)))
node _T_855 = asSInt(_T_854)
node _T_856 = eq(_T_855, asSInt(UInt<1>(0h0)))
node _T_857 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_858 = cvt(_T_857)
node _T_859 = and(_T_858, asSInt(UInt<17>(0h10000)))
node _T_860 = asSInt(_T_859)
node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0)))
node _T_862 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_863 = cvt(_T_862)
node _T_864 = and(_T_863, asSInt(UInt<18>(0h2f000)))
node _T_865 = asSInt(_T_864)
node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0)))
node _T_867 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_868 = cvt(_T_867)
node _T_869 = and(_T_868, asSInt(UInt<17>(0h10000)))
node _T_870 = asSInt(_T_869)
node _T_871 = eq(_T_870, asSInt(UInt<1>(0h0)))
node _T_872 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_873 = cvt(_T_872)
node _T_874 = and(_T_873, asSInt(UInt<27>(0h4000000)))
node _T_875 = asSInt(_T_874)
node _T_876 = eq(_T_875, asSInt(UInt<1>(0h0)))
node _T_877 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_878 = cvt(_T_877)
node _T_879 = and(_T_878, asSInt(UInt<19>(0h40000)))
node _T_880 = asSInt(_T_879)
node _T_881 = eq(_T_880, asSInt(UInt<1>(0h0)))
node _T_882 = or(_T_856, _T_861)
node _T_883 = or(_T_882, _T_866)
node _T_884 = or(_T_883, _T_871)
node _T_885 = or(_T_884, _T_876)
node _T_886 = or(_T_885, _T_881)
node _T_887 = and(_T_851, _T_886)
node _T_888 = or(UInt<1>(0h0), _T_850)
node _T_889 = or(_T_888, _T_887)
node _T_890 = and(_T_834, _T_889)
node _T_891 = asUInt(reset)
node _T_892 = eq(_T_891, UInt<1>(0h0))
when _T_892 :
node _T_893 = eq(_T_890, UInt<1>(0h0))
when _T_893 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_890, UInt<1>(0h1), "") : assert_36
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(source_ok, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(is_aligned, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_900 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_901 = asUInt(reset)
node _T_902 = eq(_T_901, UInt<1>(0h0))
when _T_902 :
node _T_903 = eq(_T_900, UInt<1>(0h0))
when _T_903 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_900, UInt<1>(0h1), "") : assert_39
node _T_904 = eq(io.in.a.bits.mask, mask)
node _T_905 = asUInt(reset)
node _T_906 = eq(_T_905, UInt<1>(0h0))
when _T_906 :
node _T_907 = eq(_T_904, UInt<1>(0h0))
when _T_907 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_904, UInt<1>(0h1), "") : assert_40
node _T_908 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_908 :
node _T_909 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_910 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_911 = and(_T_909, _T_910)
node _T_912 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_913 = shr(io.in.a.bits.source, 2)
node _T_914 = eq(_T_913, UInt<1>(0h0))
node _T_915 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_916 = and(_T_914, _T_915)
node _T_917 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_918 = and(_T_916, _T_917)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_919 = shr(io.in.a.bits.source, 2)
node _T_920 = eq(_T_919, UInt<1>(0h1))
node _T_921 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_922 = and(_T_920, _T_921)
node _T_923 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_924 = and(_T_922, _T_923)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_925 = shr(io.in.a.bits.source, 2)
node _T_926 = eq(_T_925, UInt<2>(0h2))
node _T_927 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_928 = and(_T_926, _T_927)
node _T_929 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_930 = and(_T_928, _T_929)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_931 = shr(io.in.a.bits.source, 2)
node _T_932 = eq(_T_931, UInt<2>(0h3))
node _T_933 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_934 = and(_T_932, _T_933)
node _T_935 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_936 = and(_T_934, _T_935)
node _T_937 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_938 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_939 = or(_T_912, _T_918)
node _T_940 = or(_T_939, _T_924)
node _T_941 = or(_T_940, _T_930)
node _T_942 = or(_T_941, _T_936)
node _T_943 = or(_T_942, _T_937)
node _T_944 = or(_T_943, _T_938)
node _T_945 = and(_T_911, _T_944)
node _T_946 = or(UInt<1>(0h0), _T_945)
node _T_947 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_948 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_949 = and(_T_947, _T_948)
node _T_950 = or(UInt<1>(0h0), _T_949)
node _T_951 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_952 = cvt(_T_951)
node _T_953 = and(_T_952, asSInt(UInt<15>(0h5000)))
node _T_954 = asSInt(_T_953)
node _T_955 = eq(_T_954, asSInt(UInt<1>(0h0)))
node _T_956 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_957 = cvt(_T_956)
node _T_958 = and(_T_957, asSInt(UInt<13>(0h1000)))
node _T_959 = asSInt(_T_958)
node _T_960 = eq(_T_959, asSInt(UInt<1>(0h0)))
node _T_961 = or(_T_955, _T_960)
node _T_962 = and(_T_950, _T_961)
node _T_963 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_964 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_965 = cvt(_T_964)
node _T_966 = and(_T_965, asSInt(UInt<13>(0h1000)))
node _T_967 = asSInt(_T_966)
node _T_968 = eq(_T_967, asSInt(UInt<1>(0h0)))
node _T_969 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_970 = cvt(_T_969)
node _T_971 = and(_T_970, asSInt(UInt<17>(0h10000)))
node _T_972 = asSInt(_T_971)
node _T_973 = eq(_T_972, asSInt(UInt<1>(0h0)))
node _T_974 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_975 = cvt(_T_974)
node _T_976 = and(_T_975, asSInt(UInt<18>(0h2f000)))
node _T_977 = asSInt(_T_976)
node _T_978 = eq(_T_977, asSInt(UInt<1>(0h0)))
node _T_979 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_980 = cvt(_T_979)
node _T_981 = and(_T_980, asSInt(UInt<17>(0h10000)))
node _T_982 = asSInt(_T_981)
node _T_983 = eq(_T_982, asSInt(UInt<1>(0h0)))
node _T_984 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_985 = cvt(_T_984)
node _T_986 = and(_T_985, asSInt(UInt<27>(0h4000000)))
node _T_987 = asSInt(_T_986)
node _T_988 = eq(_T_987, asSInt(UInt<1>(0h0)))
node _T_989 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_990 = cvt(_T_989)
node _T_991 = and(_T_990, asSInt(UInt<19>(0h40000)))
node _T_992 = asSInt(_T_991)
node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0)))
node _T_994 = or(_T_968, _T_973)
node _T_995 = or(_T_994, _T_978)
node _T_996 = or(_T_995, _T_983)
node _T_997 = or(_T_996, _T_988)
node _T_998 = or(_T_997, _T_993)
node _T_999 = and(_T_963, _T_998)
node _T_1000 = or(UInt<1>(0h0), _T_962)
node _T_1001 = or(_T_1000, _T_999)
node _T_1002 = and(_T_946, _T_1001)
node _T_1003 = asUInt(reset)
node _T_1004 = eq(_T_1003, UInt<1>(0h0))
when _T_1004 :
node _T_1005 = eq(_T_1002, UInt<1>(0h0))
when _T_1005 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1002, UInt<1>(0h1), "") : assert_41
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(source_ok, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1009 = asUInt(reset)
node _T_1010 = eq(_T_1009, UInt<1>(0h0))
when _T_1010 :
node _T_1011 = eq(is_aligned, UInt<1>(0h0))
when _T_1011 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1012 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1013 = asUInt(reset)
node _T_1014 = eq(_T_1013, UInt<1>(0h0))
when _T_1014 :
node _T_1015 = eq(_T_1012, UInt<1>(0h0))
when _T_1015 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1012, UInt<1>(0h1), "") : assert_44
node _T_1016 = eq(io.in.a.bits.mask, mask)
node _T_1017 = asUInt(reset)
node _T_1018 = eq(_T_1017, UInt<1>(0h0))
when _T_1018 :
node _T_1019 = eq(_T_1016, UInt<1>(0h0))
when _T_1019 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1016, UInt<1>(0h1), "") : assert_45
node _T_1020 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1020 :
node _T_1021 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1022 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1023 = and(_T_1021, _T_1022)
node _T_1024 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_1025 = shr(io.in.a.bits.source, 2)
node _T_1026 = eq(_T_1025, UInt<1>(0h0))
node _T_1027 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_1028 = and(_T_1026, _T_1027)
node _T_1029 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_1030 = and(_T_1028, _T_1029)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_1031 = shr(io.in.a.bits.source, 2)
node _T_1032 = eq(_T_1031, UInt<1>(0h1))
node _T_1033 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_1034 = and(_T_1032, _T_1033)
node _T_1035 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_1036 = and(_T_1034, _T_1035)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_1037 = shr(io.in.a.bits.source, 2)
node _T_1038 = eq(_T_1037, UInt<2>(0h2))
node _T_1039 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_1040 = and(_T_1038, _T_1039)
node _T_1041 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_1042 = and(_T_1040, _T_1041)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_1043 = shr(io.in.a.bits.source, 2)
node _T_1044 = eq(_T_1043, UInt<2>(0h3))
node _T_1045 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_1046 = and(_T_1044, _T_1045)
node _T_1047 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_1048 = and(_T_1046, _T_1047)
node _T_1049 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1050 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1051 = or(_T_1024, _T_1030)
node _T_1052 = or(_T_1051, _T_1036)
node _T_1053 = or(_T_1052, _T_1042)
node _T_1054 = or(_T_1053, _T_1048)
node _T_1055 = or(_T_1054, _T_1049)
node _T_1056 = or(_T_1055, _T_1050)
node _T_1057 = and(_T_1023, _T_1056)
node _T_1058 = or(UInt<1>(0h0), _T_1057)
node _T_1059 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1060 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1061 = and(_T_1059, _T_1060)
node _T_1062 = or(UInt<1>(0h0), _T_1061)
node _T_1063 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_1064 = cvt(_T_1063)
node _T_1065 = and(_T_1064, asSInt(UInt<13>(0h1000)))
node _T_1066 = asSInt(_T_1065)
node _T_1067 = eq(_T_1066, asSInt(UInt<1>(0h0)))
node _T_1068 = and(_T_1062, _T_1067)
node _T_1069 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1070 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_1071 = cvt(_T_1070)
node _T_1072 = and(_T_1071, asSInt(UInt<14>(0h2000)))
node _T_1073 = asSInt(_T_1072)
node _T_1074 = eq(_T_1073, asSInt(UInt<1>(0h0)))
node _T_1075 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_1076 = cvt(_T_1075)
node _T_1077 = and(_T_1076, asSInt(UInt<17>(0h10000)))
node _T_1078 = asSInt(_T_1077)
node _T_1079 = eq(_T_1078, asSInt(UInt<1>(0h0)))
node _T_1080 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1081 = cvt(_T_1080)
node _T_1082 = and(_T_1081, asSInt(UInt<18>(0h2f000)))
node _T_1083 = asSInt(_T_1082)
node _T_1084 = eq(_T_1083, asSInt(UInt<1>(0h0)))
node _T_1085 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1086 = cvt(_T_1085)
node _T_1087 = and(_T_1086, asSInt(UInt<17>(0h10000)))
node _T_1088 = asSInt(_T_1087)
node _T_1089 = eq(_T_1088, asSInt(UInt<1>(0h0)))
node _T_1090 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_1091 = cvt(_T_1090)
node _T_1092 = and(_T_1091, asSInt(UInt<27>(0h4000000)))
node _T_1093 = asSInt(_T_1092)
node _T_1094 = eq(_T_1093, asSInt(UInt<1>(0h0)))
node _T_1095 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1096 = cvt(_T_1095)
node _T_1097 = and(_T_1096, asSInt(UInt<13>(0h1000)))
node _T_1098 = asSInt(_T_1097)
node _T_1099 = eq(_T_1098, asSInt(UInt<1>(0h0)))
node _T_1100 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1101 = cvt(_T_1100)
node _T_1102 = and(_T_1101, asSInt(UInt<19>(0h40000)))
node _T_1103 = asSInt(_T_1102)
node _T_1104 = eq(_T_1103, asSInt(UInt<1>(0h0)))
node _T_1105 = or(_T_1074, _T_1079)
node _T_1106 = or(_T_1105, _T_1084)
node _T_1107 = or(_T_1106, _T_1089)
node _T_1108 = or(_T_1107, _T_1094)
node _T_1109 = or(_T_1108, _T_1099)
node _T_1110 = or(_T_1109, _T_1104)
node _T_1111 = and(_T_1069, _T_1110)
node _T_1112 = or(UInt<1>(0h0), _T_1068)
node _T_1113 = or(_T_1112, _T_1111)
node _T_1114 = and(_T_1058, _T_1113)
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_46
node _T_1118 = asUInt(reset)
node _T_1119 = eq(_T_1118, UInt<1>(0h0))
when _T_1119 :
node _T_1120 = eq(source_ok, UInt<1>(0h0))
when _T_1120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(is_aligned, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1124 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_49
node _T_1128 = eq(io.in.a.bits.mask, mask)
node _T_1129 = asUInt(reset)
node _T_1130 = eq(_T_1129, UInt<1>(0h0))
when _T_1130 :
node _T_1131 = eq(_T_1128, UInt<1>(0h0))
when _T_1131 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1128, UInt<1>(0h1), "") : assert_50
node _T_1132 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1133 = asUInt(reset)
node _T_1134 = eq(_T_1133, UInt<1>(0h0))
when _T_1134 :
node _T_1135 = eq(_T_1132, UInt<1>(0h0))
when _T_1135 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1132, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1136 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(_T_1136, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1136, UInt<1>(0h1), "") : assert_52
node _source_ok_T_32 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_33 = shr(io.in.d.bits.source, 2)
node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0))
node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_39 = shr(io.in.d.bits.source, 2)
node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h1))
node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_45 = shr(io.in.d.bits.source, 2)
node _source_ok_T_46 = eq(_source_ok_T_45, UInt<2>(0h2))
node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47)
node _source_ok_T_49 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_51 = shr(io.in.d.bits.source, 2)
node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h3))
node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53)
node _source_ok_T_55 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55)
node _source_ok_T_57 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_58 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[7]
connect _source_ok_WIRE_1[0], _source_ok_T_32
connect _source_ok_WIRE_1[1], _source_ok_T_38
connect _source_ok_WIRE_1[2], _source_ok_T_44
connect _source_ok_WIRE_1[3], _source_ok_T_50
connect _source_ok_WIRE_1[4], _source_ok_T_56
connect _source_ok_WIRE_1[5], _source_ok_T_57
connect _source_ok_WIRE_1[6], _source_ok_T_58
node _source_ok_T_59 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE_1[2])
node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE_1[3])
node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE_1[4])
node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE_1[5])
node source_ok_1 = or(_source_ok_T_63, _source_ok_WIRE_1[6])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1140 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1140 :
node _T_1141 = asUInt(reset)
node _T_1142 = eq(_T_1141, UInt<1>(0h0))
when _T_1142 :
node _T_1143 = eq(source_ok_1, UInt<1>(0h0))
when _T_1143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1144 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1145 = asUInt(reset)
node _T_1146 = eq(_T_1145, UInt<1>(0h0))
when _T_1146 :
node _T_1147 = eq(_T_1144, UInt<1>(0h0))
when _T_1147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1144, UInt<1>(0h1), "") : assert_54
node _T_1148 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1149 = asUInt(reset)
node _T_1150 = eq(_T_1149, UInt<1>(0h0))
when _T_1150 :
node _T_1151 = eq(_T_1148, UInt<1>(0h0))
when _T_1151 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1148, UInt<1>(0h1), "") : assert_55
node _T_1152 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1153 = asUInt(reset)
node _T_1154 = eq(_T_1153, UInt<1>(0h0))
when _T_1154 :
node _T_1155 = eq(_T_1152, UInt<1>(0h0))
when _T_1155 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1152, UInt<1>(0h1), "") : assert_56
node _T_1156 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1157 = asUInt(reset)
node _T_1158 = eq(_T_1157, UInt<1>(0h0))
when _T_1158 :
node _T_1159 = eq(_T_1156, UInt<1>(0h0))
when _T_1159 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1156, UInt<1>(0h1), "") : assert_57
node _T_1160 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1160 :
node _T_1161 = asUInt(reset)
node _T_1162 = eq(_T_1161, UInt<1>(0h0))
when _T_1162 :
node _T_1163 = eq(source_ok_1, UInt<1>(0h0))
when _T_1163 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1164 = asUInt(reset)
node _T_1165 = eq(_T_1164, UInt<1>(0h0))
when _T_1165 :
node _T_1166 = eq(sink_ok, UInt<1>(0h0))
when _T_1166 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1167 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1168 = asUInt(reset)
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(_T_1167, UInt<1>(0h0))
when _T_1170 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1167, UInt<1>(0h1), "") : assert_60
node _T_1171 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1172 = asUInt(reset)
node _T_1173 = eq(_T_1172, UInt<1>(0h0))
when _T_1173 :
node _T_1174 = eq(_T_1171, UInt<1>(0h0))
when _T_1174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1171, UInt<1>(0h1), "") : assert_61
node _T_1175 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1176 = asUInt(reset)
node _T_1177 = eq(_T_1176, UInt<1>(0h0))
when _T_1177 :
node _T_1178 = eq(_T_1175, UInt<1>(0h0))
when _T_1178 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1175, UInt<1>(0h1), "") : assert_62
node _T_1179 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1180 = asUInt(reset)
node _T_1181 = eq(_T_1180, UInt<1>(0h0))
when _T_1181 :
node _T_1182 = eq(_T_1179, UInt<1>(0h0))
when _T_1182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1179, UInt<1>(0h1), "") : assert_63
node _T_1183 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1184 = or(UInt<1>(0h1), _T_1183)
node _T_1185 = asUInt(reset)
node _T_1186 = eq(_T_1185, UInt<1>(0h0))
when _T_1186 :
node _T_1187 = eq(_T_1184, UInt<1>(0h0))
when _T_1187 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1184, UInt<1>(0h1), "") : assert_64
node _T_1188 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1188 :
node _T_1189 = asUInt(reset)
node _T_1190 = eq(_T_1189, UInt<1>(0h0))
when _T_1190 :
node _T_1191 = eq(source_ok_1, UInt<1>(0h0))
when _T_1191 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1192 = asUInt(reset)
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
when _T_1193 :
node _T_1194 = eq(sink_ok, UInt<1>(0h0))
when _T_1194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1195 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1196 = asUInt(reset)
node _T_1197 = eq(_T_1196, UInt<1>(0h0))
when _T_1197 :
node _T_1198 = eq(_T_1195, UInt<1>(0h0))
when _T_1198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1195, UInt<1>(0h1), "") : assert_67
node _T_1199 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_68
node _T_1203 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1204 = asUInt(reset)
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(_T_1203, UInt<1>(0h0))
when _T_1206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1203, UInt<1>(0h1), "") : assert_69
node _T_1207 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1208 = or(_T_1207, io.in.d.bits.corrupt)
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(_T_1208, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1208, UInt<1>(0h1), "") : assert_70
node _T_1212 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1213 = or(UInt<1>(0h1), _T_1212)
node _T_1214 = asUInt(reset)
node _T_1215 = eq(_T_1214, UInt<1>(0h0))
when _T_1215 :
node _T_1216 = eq(_T_1213, UInt<1>(0h0))
when _T_1216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1213, UInt<1>(0h1), "") : assert_71
node _T_1217 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = asUInt(reset)
node _T_1219 = eq(_T_1218, UInt<1>(0h0))
when _T_1219 :
node _T_1220 = eq(source_ok_1, UInt<1>(0h0))
when _T_1220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1221 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_73
node _T_1225 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(_T_1225, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1225, UInt<1>(0h1), "") : assert_74
node _T_1229 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1230 = or(UInt<1>(0h1), _T_1229)
node _T_1231 = asUInt(reset)
node _T_1232 = eq(_T_1231, UInt<1>(0h0))
when _T_1232 :
node _T_1233 = eq(_T_1230, UInt<1>(0h0))
when _T_1233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1230, UInt<1>(0h1), "") : assert_75
node _T_1234 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1234 :
node _T_1235 = asUInt(reset)
node _T_1236 = eq(_T_1235, UInt<1>(0h0))
when _T_1236 :
node _T_1237 = eq(source_ok_1, UInt<1>(0h0))
when _T_1237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1238 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1239 = asUInt(reset)
node _T_1240 = eq(_T_1239, UInt<1>(0h0))
when _T_1240 :
node _T_1241 = eq(_T_1238, UInt<1>(0h0))
when _T_1241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1238, UInt<1>(0h1), "") : assert_77
node _T_1242 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1243 = or(_T_1242, io.in.d.bits.corrupt)
node _T_1244 = asUInt(reset)
node _T_1245 = eq(_T_1244, UInt<1>(0h0))
when _T_1245 :
node _T_1246 = eq(_T_1243, UInt<1>(0h0))
when _T_1246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1243, UInt<1>(0h1), "") : assert_78
node _T_1247 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1248 = or(UInt<1>(0h1), _T_1247)
node _T_1249 = asUInt(reset)
node _T_1250 = eq(_T_1249, UInt<1>(0h0))
when _T_1250 :
node _T_1251 = eq(_T_1248, UInt<1>(0h0))
when _T_1251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1248, UInt<1>(0h1), "") : assert_79
node _T_1252 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1252 :
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(source_ok_1, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1256 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1257 = asUInt(reset)
node _T_1258 = eq(_T_1257, UInt<1>(0h0))
when _T_1258 :
node _T_1259 = eq(_T_1256, UInt<1>(0h0))
when _T_1259 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1256, UInt<1>(0h1), "") : assert_81
node _T_1260 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1261 = asUInt(reset)
node _T_1262 = eq(_T_1261, UInt<1>(0h0))
when _T_1262 :
node _T_1263 = eq(_T_1260, UInt<1>(0h0))
when _T_1263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1260, UInt<1>(0h1), "") : assert_82
node _T_1264 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1265 = or(UInt<1>(0h1), _T_1264)
node _T_1266 = asUInt(reset)
node _T_1267 = eq(_T_1266, UInt<1>(0h0))
when _T_1267 :
node _T_1268 = eq(_T_1265, UInt<1>(0h0))
when _T_1268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1265, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1269 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(_T_1269, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1269, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<7>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1273 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1274 = asUInt(reset)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(_T_1273, UInt<1>(0h0))
when _T_1276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1273, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1277 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1278 = asUInt(reset)
node _T_1279 = eq(_T_1278, UInt<1>(0h0))
when _T_1279 :
node _T_1280 = eq(_T_1277, UInt<1>(0h0))
when _T_1280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1277, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1281 = eq(a_first, UInt<1>(0h0))
node _T_1282 = and(io.in.a.valid, _T_1281)
when _T_1282 :
node _T_1283 = eq(io.in.a.bits.opcode, opcode)
node _T_1284 = asUInt(reset)
node _T_1285 = eq(_T_1284, UInt<1>(0h0))
when _T_1285 :
node _T_1286 = eq(_T_1283, UInt<1>(0h0))
when _T_1286 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1283, UInt<1>(0h1), "") : assert_87
node _T_1287 = eq(io.in.a.bits.param, param)
node _T_1288 = asUInt(reset)
node _T_1289 = eq(_T_1288, UInt<1>(0h0))
when _T_1289 :
node _T_1290 = eq(_T_1287, UInt<1>(0h0))
when _T_1290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1287, UInt<1>(0h1), "") : assert_88
node _T_1291 = eq(io.in.a.bits.size, size)
node _T_1292 = asUInt(reset)
node _T_1293 = eq(_T_1292, UInt<1>(0h0))
when _T_1293 :
node _T_1294 = eq(_T_1291, UInt<1>(0h0))
when _T_1294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1291, UInt<1>(0h1), "") : assert_89
node _T_1295 = eq(io.in.a.bits.source, source)
node _T_1296 = asUInt(reset)
node _T_1297 = eq(_T_1296, UInt<1>(0h0))
when _T_1297 :
node _T_1298 = eq(_T_1295, UInt<1>(0h0))
when _T_1298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1295, UInt<1>(0h1), "") : assert_90
node _T_1299 = eq(io.in.a.bits.address, address)
node _T_1300 = asUInt(reset)
node _T_1301 = eq(_T_1300, UInt<1>(0h0))
when _T_1301 :
node _T_1302 = eq(_T_1299, UInt<1>(0h0))
when _T_1302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1299, UInt<1>(0h1), "") : assert_91
node _T_1303 = and(io.in.a.ready, io.in.a.valid)
node _T_1304 = and(_T_1303, a_first)
when _T_1304 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1305 = eq(d_first, UInt<1>(0h0))
node _T_1306 = and(io.in.d.valid, _T_1305)
when _T_1306 :
node _T_1307 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1308 = asUInt(reset)
node _T_1309 = eq(_T_1308, UInt<1>(0h0))
when _T_1309 :
node _T_1310 = eq(_T_1307, UInt<1>(0h0))
when _T_1310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1307, UInt<1>(0h1), "") : assert_92
node _T_1311 = eq(io.in.d.bits.param, param_1)
node _T_1312 = asUInt(reset)
node _T_1313 = eq(_T_1312, UInt<1>(0h0))
when _T_1313 :
node _T_1314 = eq(_T_1311, UInt<1>(0h0))
when _T_1314 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1311, UInt<1>(0h1), "") : assert_93
node _T_1315 = eq(io.in.d.bits.size, size_1)
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_94
node _T_1319 = eq(io.in.d.bits.source, source_1)
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(_T_1319, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1319, UInt<1>(0h1), "") : assert_95
node _T_1323 = eq(io.in.d.bits.sink, sink)
node _T_1324 = asUInt(reset)
node _T_1325 = eq(_T_1324, UInt<1>(0h0))
when _T_1325 :
node _T_1326 = eq(_T_1323, UInt<1>(0h0))
when _T_1326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1323, UInt<1>(0h1), "") : assert_96
node _T_1327 = eq(io.in.d.bits.denied, denied)
node _T_1328 = asUInt(reset)
node _T_1329 = eq(_T_1328, UInt<1>(0h0))
when _T_1329 :
node _T_1330 = eq(_T_1327, UInt<1>(0h0))
when _T_1330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1327, UInt<1>(0h1), "") : assert_97
node _T_1331 = and(io.in.d.ready, io.in.d.valid)
node _T_1332 = and(_T_1331, d_first)
when _T_1332 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<520>
connect a_sizes_set, UInt<520>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1333 = and(io.in.a.valid, a_first_1)
node _T_1334 = and(_T_1333, UInt<1>(0h1))
when _T_1334 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1335 = and(io.in.a.ready, io.in.a.valid)
node _T_1336 = and(_T_1335, a_first_1)
node _T_1337 = and(_T_1336, UInt<1>(0h1))
when _T_1337 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1338 = dshr(inflight, io.in.a.bits.source)
node _T_1339 = bits(_T_1338, 0, 0)
node _T_1340 = eq(_T_1339, UInt<1>(0h0))
node _T_1341 = asUInt(reset)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
when _T_1342 :
node _T_1343 = eq(_T_1340, UInt<1>(0h0))
when _T_1343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1340, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<520>
connect d_sizes_clr, UInt<520>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1344 = and(io.in.d.valid, d_first_1)
node _T_1345 = and(_T_1344, UInt<1>(0h1))
node _T_1346 = eq(d_release_ack, UInt<1>(0h0))
node _T_1347 = and(_T_1345, _T_1346)
when _T_1347 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1348 = and(io.in.d.ready, io.in.d.valid)
node _T_1349 = and(_T_1348, d_first_1)
node _T_1350 = and(_T_1349, UInt<1>(0h1))
node _T_1351 = eq(d_release_ack, UInt<1>(0h0))
node _T_1352 = and(_T_1350, _T_1351)
when _T_1352 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1353 = and(io.in.d.valid, d_first_1)
node _T_1354 = and(_T_1353, UInt<1>(0h1))
node _T_1355 = eq(d_release_ack, UInt<1>(0h0))
node _T_1356 = and(_T_1354, _T_1355)
when _T_1356 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1357 = dshr(inflight, io.in.d.bits.source)
node _T_1358 = bits(_T_1357, 0, 0)
node _T_1359 = or(_T_1358, same_cycle_resp)
node _T_1360 = asUInt(reset)
node _T_1361 = eq(_T_1360, UInt<1>(0h0))
when _T_1361 :
node _T_1362 = eq(_T_1359, UInt<1>(0h0))
when _T_1362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1359, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1363 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1364 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1365 = or(_T_1363, _T_1364)
node _T_1366 = asUInt(reset)
node _T_1367 = eq(_T_1366, UInt<1>(0h0))
when _T_1367 :
node _T_1368 = eq(_T_1365, UInt<1>(0h0))
when _T_1368 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1365, UInt<1>(0h1), "") : assert_100
node _T_1369 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1370 = asUInt(reset)
node _T_1371 = eq(_T_1370, UInt<1>(0h0))
when _T_1371 :
node _T_1372 = eq(_T_1369, UInt<1>(0h0))
when _T_1372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1369, UInt<1>(0h1), "") : assert_101
else :
node _T_1373 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1374 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1375 = or(_T_1373, _T_1374)
node _T_1376 = asUInt(reset)
node _T_1377 = eq(_T_1376, UInt<1>(0h0))
when _T_1377 :
node _T_1378 = eq(_T_1375, UInt<1>(0h0))
when _T_1378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1375, UInt<1>(0h1), "") : assert_102
node _T_1379 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1380 = asUInt(reset)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
when _T_1381 :
node _T_1382 = eq(_T_1379, UInt<1>(0h0))
when _T_1382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1379, UInt<1>(0h1), "") : assert_103
node _T_1383 = and(io.in.d.valid, d_first_1)
node _T_1384 = and(_T_1383, a_first_1)
node _T_1385 = and(_T_1384, io.in.a.valid)
node _T_1386 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1387 = and(_T_1385, _T_1386)
node _T_1388 = eq(d_release_ack, UInt<1>(0h0))
node _T_1389 = and(_T_1387, _T_1388)
when _T_1389 :
node _T_1390 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1391 = or(_T_1390, io.in.a.ready)
node _T_1392 = asUInt(reset)
node _T_1393 = eq(_T_1392, UInt<1>(0h0))
when _T_1393 :
node _T_1394 = eq(_T_1391, UInt<1>(0h0))
when _T_1394 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1391, UInt<1>(0h1), "") : assert_104
node _T_1395 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1396 = orr(a_set_wo_ready)
node _T_1397 = eq(_T_1396, UInt<1>(0h0))
node _T_1398 = or(_T_1395, _T_1397)
node _T_1399 = asUInt(reset)
node _T_1400 = eq(_T_1399, UInt<1>(0h0))
when _T_1400 :
node _T_1401 = eq(_T_1398, UInt<1>(0h0))
when _T_1401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1398, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_38
node _T_1402 = orr(inflight)
node _T_1403 = eq(_T_1402, UInt<1>(0h0))
node _T_1404 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1405 = or(_T_1403, _T_1404)
node _T_1406 = lt(watchdog, plusarg_reader.out)
node _T_1407 = or(_T_1405, _T_1406)
node _T_1408 = asUInt(reset)
node _T_1409 = eq(_T_1408, UInt<1>(0h0))
when _T_1409 :
node _T_1410 = eq(_T_1407, UInt<1>(0h0))
when _T_1410 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1407, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1411 = and(io.in.a.ready, io.in.a.valid)
node _T_1412 = and(io.in.d.ready, io.in.d.valid)
node _T_1413 = or(_T_1411, _T_1412)
when _T_1413 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<520>
connect c_sizes_set, UInt<520>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1414 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1415 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1416 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1417 = and(_T_1415, _T_1416)
node _T_1418 = and(_T_1414, _T_1417)
when _T_1418 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1419 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1420 = and(_T_1419, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1421 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1422 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1423 = and(_T_1421, _T_1422)
node _T_1424 = and(_T_1420, _T_1423)
when _T_1424 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1425 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1426 = bits(_T_1425, 0, 0)
node _T_1427 = eq(_T_1426, UInt<1>(0h0))
node _T_1428 = asUInt(reset)
node _T_1429 = eq(_T_1428, UInt<1>(0h0))
when _T_1429 :
node _T_1430 = eq(_T_1427, UInt<1>(0h0))
when _T_1430 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1427, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<520>
connect d_sizes_clr_1, UInt<520>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1431 = and(io.in.d.valid, d_first_2)
node _T_1432 = and(_T_1431, UInt<1>(0h1))
node _T_1433 = and(_T_1432, d_release_ack_1)
when _T_1433 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1434 = and(io.in.d.ready, io.in.d.valid)
node _T_1435 = and(_T_1434, d_first_2)
node _T_1436 = and(_T_1435, UInt<1>(0h1))
node _T_1437 = and(_T_1436, d_release_ack_1)
when _T_1437 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1438 = and(io.in.d.valid, d_first_2)
node _T_1439 = and(_T_1438, UInt<1>(0h1))
node _T_1440 = and(_T_1439, d_release_ack_1)
when _T_1440 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1441 = dshr(inflight_1, io.in.d.bits.source)
node _T_1442 = bits(_T_1441, 0, 0)
node _T_1443 = or(_T_1442, same_cycle_resp_1)
node _T_1444 = asUInt(reset)
node _T_1445 = eq(_T_1444, UInt<1>(0h0))
when _T_1445 :
node _T_1446 = eq(_T_1443, UInt<1>(0h0))
when _T_1446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1443, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1447 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1448 = asUInt(reset)
node _T_1449 = eq(_T_1448, UInt<1>(0h0))
when _T_1449 :
node _T_1450 = eq(_T_1447, UInt<1>(0h0))
when _T_1450 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1447, UInt<1>(0h1), "") : assert_109
else :
node _T_1451 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1452 = asUInt(reset)
node _T_1453 = eq(_T_1452, UInt<1>(0h0))
when _T_1453 :
node _T_1454 = eq(_T_1451, UInt<1>(0h0))
when _T_1454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1451, UInt<1>(0h1), "") : assert_110
node _T_1455 = and(io.in.d.valid, d_first_2)
node _T_1456 = and(_T_1455, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1457 = and(_T_1456, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1458 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1459 = and(_T_1457, _T_1458)
node _T_1460 = and(_T_1459, d_release_ack_1)
node _T_1461 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1462 = and(_T_1460, _T_1461)
when _T_1462 :
node _T_1463 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1464 = or(_T_1463, _WIRE_23.ready)
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(_T_1464, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1464, UInt<1>(0h1), "") : assert_111
node _T_1468 = orr(c_set_wo_ready)
when _T_1468 :
node _T_1469 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1470 = asUInt(reset)
node _T_1471 = eq(_T_1470, UInt<1>(0h0))
when _T_1471 :
node _T_1472 = eq(_T_1469, UInt<1>(0h0))
when _T_1472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1469, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_39
node _T_1473 = orr(inflight_1)
node _T_1474 = eq(_T_1473, UInt<1>(0h0))
node _T_1475 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1476 = or(_T_1474, _T_1475)
node _T_1477 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1478 = or(_T_1476, _T_1477)
node _T_1479 = asUInt(reset)
node _T_1480 = eq(_T_1479, UInt<1>(0h0))
when _T_1480 :
node _T_1481 = eq(_T_1478, UInt<1>(0h0))
when _T_1481 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:62:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1478, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1482 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1483 = and(io.in.d.ready, io.in.d.valid)
node _T_1484 = or(_T_1482, _T_1483)
when _T_1484 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_19( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_28 = _source_ok_T_27 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_30 = _source_ok_T_29 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_31 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_33 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_39 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_45 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_51 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_34 = _source_ok_T_33 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_40 = _source_ok_T_39 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_46 = _source_ok_T_45 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_50; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_52 = _source_ok_T_51 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_56; // @[Parameters.scala:1138:31]
wire _source_ok_T_57 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_57; // @[Parameters.scala:1138:31]
wire _source_ok_T_58 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire _source_ok_T_59 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_63 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1411 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1411; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1411; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1484 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1484; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1484; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1484; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [519:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [519:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1337 = _T_1411 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1337 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1337 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1337 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1337 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1337 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1383 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1383 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1352 = _T_1484 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1352 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1352 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1352 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1455 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1455 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1437 = _T_1484 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1437 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1437 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1437 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRawFN_small_e5_s11_2 :
input clock : Clock
input reset : Reset
output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}}
regreset cycleNum : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inReady : UInt<1>, clock, reset, UInt<1>(0h1)
regreset rawOutValid : UInt<1>, clock, reset, UInt<1>(0h0)
reg sqrtOp_Z : UInt<1>, clock
reg majorExc_Z : UInt<1>, clock
reg isNaN_Z : UInt<1>, clock
reg isInf_Z : UInt<1>, clock
reg isZero_Z : UInt<1>, clock
reg sign_Z : UInt<1>, clock
reg sExp_Z : SInt<7>, clock
reg fractB_Z : UInt<11>, clock
reg roundingMode_Z : UInt<3>, clock
reg rem_Z : UInt<13>, clock
reg notZeroRem_Z : UInt<1>, clock
reg sigX_Z : UInt<13>, clock
node _notSigNaNIn_invalidExc_S_div_T = and(io.a.isZero, io.b.isZero)
node _notSigNaNIn_invalidExc_S_div_T_1 = and(io.a.isInf, io.b.isInf)
node notSigNaNIn_invalidExc_S_div = or(_notSigNaNIn_invalidExc_S_div_T, _notSigNaNIn_invalidExc_S_div_T_1)
node _notSigNaNIn_invalidExc_S_sqrt_T = eq(io.a.isNaN, UInt<1>(0h0))
node _notSigNaNIn_invalidExc_S_sqrt_T_1 = eq(io.a.isZero, UInt<1>(0h0))
node _notSigNaNIn_invalidExc_S_sqrt_T_2 = and(_notSigNaNIn_invalidExc_S_sqrt_T, _notSigNaNIn_invalidExc_S_sqrt_T_1)
node notSigNaNIn_invalidExc_S_sqrt = and(_notSigNaNIn_invalidExc_S_sqrt_T_2, io.a.sign)
node _majorExc_S_T = bits(io.a.sig, 9, 9)
node _majorExc_S_T_1 = eq(_majorExc_S_T, UInt<1>(0h0))
node _majorExc_S_T_2 = and(io.a.isNaN, _majorExc_S_T_1)
node _majorExc_S_T_3 = or(_majorExc_S_T_2, notSigNaNIn_invalidExc_S_sqrt)
node _majorExc_S_T_4 = bits(io.a.sig, 9, 9)
node _majorExc_S_T_5 = eq(_majorExc_S_T_4, UInt<1>(0h0))
node _majorExc_S_T_6 = and(io.a.isNaN, _majorExc_S_T_5)
node _majorExc_S_T_7 = bits(io.b.sig, 9, 9)
node _majorExc_S_T_8 = eq(_majorExc_S_T_7, UInt<1>(0h0))
node _majorExc_S_T_9 = and(io.b.isNaN, _majorExc_S_T_8)
node _majorExc_S_T_10 = or(_majorExc_S_T_6, _majorExc_S_T_9)
node _majorExc_S_T_11 = or(_majorExc_S_T_10, notSigNaNIn_invalidExc_S_div)
node _majorExc_S_T_12 = eq(io.a.isNaN, UInt<1>(0h0))
node _majorExc_S_T_13 = eq(io.a.isInf, UInt<1>(0h0))
node _majorExc_S_T_14 = and(_majorExc_S_T_12, _majorExc_S_T_13)
node _majorExc_S_T_15 = and(_majorExc_S_T_14, io.b.isZero)
node _majorExc_S_T_16 = or(_majorExc_S_T_11, _majorExc_S_T_15)
node majorExc_S = mux(io.sqrtOp, _majorExc_S_T_3, _majorExc_S_T_16)
node _isNaN_S_T = or(io.a.isNaN, notSigNaNIn_invalidExc_S_sqrt)
node _isNaN_S_T_1 = or(io.a.isNaN, io.b.isNaN)
node _isNaN_S_T_2 = or(_isNaN_S_T_1, notSigNaNIn_invalidExc_S_div)
node isNaN_S = mux(io.sqrtOp, _isNaN_S_T, _isNaN_S_T_2)
node _isInf_S_T = or(io.a.isInf, io.b.isZero)
node isInf_S = mux(io.sqrtOp, io.a.isInf, _isInf_S_T)
node _isZero_S_T = or(io.a.isZero, io.b.isInf)
node isZero_S = mux(io.sqrtOp, io.a.isZero, _isZero_S_T)
node _sign_S_T = eq(io.sqrtOp, UInt<1>(0h0))
node _sign_S_T_1 = and(_sign_S_T, io.b.sign)
node sign_S = xor(io.a.sign, _sign_S_T_1)
node _specialCaseA_S_T = or(io.a.isNaN, io.a.isInf)
node specialCaseA_S = or(_specialCaseA_S_T, io.a.isZero)
node _specialCaseB_S_T = or(io.b.isNaN, io.b.isInf)
node specialCaseB_S = or(_specialCaseB_S_T, io.b.isZero)
node _normalCase_S_div_T = eq(specialCaseA_S, UInt<1>(0h0))
node _normalCase_S_div_T_1 = eq(specialCaseB_S, UInt<1>(0h0))
node normalCase_S_div = and(_normalCase_S_div_T, _normalCase_S_div_T_1)
node _normalCase_S_sqrt_T = eq(specialCaseA_S, UInt<1>(0h0))
node _normalCase_S_sqrt_T_1 = eq(io.a.sign, UInt<1>(0h0))
node normalCase_S_sqrt = and(_normalCase_S_sqrt_T, _normalCase_S_sqrt_T_1)
node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div)
node _sExpQuot_S_div_T = bits(io.b.sExp, 5, 5)
node _sExpQuot_S_div_T_1 = bits(io.b.sExp, 4, 0)
node _sExpQuot_S_div_T_2 = not(_sExpQuot_S_div_T_1)
node _sExpQuot_S_div_T_3 = cat(_sExpQuot_S_div_T, _sExpQuot_S_div_T_2)
node _sExpQuot_S_div_T_4 = asSInt(_sExpQuot_S_div_T_3)
node sExpQuot_S_div = add(io.a.sExp, _sExpQuot_S_div_T_4)
node _sSatExpQuot_S_div_T = leq(asSInt(UInt<7>(0h38)), sExpQuot_S_div)
node _sSatExpQuot_S_div_T_1 = bits(sExpQuot_S_div, 6, 3)
node _sSatExpQuot_S_div_T_2 = mux(_sSatExpQuot_S_div_T, UInt<3>(0h6), _sSatExpQuot_S_div_T_1)
node _sSatExpQuot_S_div_T_3 = bits(sExpQuot_S_div, 2, 0)
node _sSatExpQuot_S_div_T_4 = cat(_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3)
node sSatExpQuot_S_div = asSInt(_sSatExpQuot_S_div_T_4)
node _evenSqrt_S_T = bits(io.a.sExp, 0, 0)
node _evenSqrt_S_T_1 = eq(_evenSqrt_S_T, UInt<1>(0h0))
node evenSqrt_S = and(io.sqrtOp, _evenSqrt_S_T_1)
node _oddSqrt_S_T = bits(io.a.sExp, 0, 0)
node oddSqrt_S = and(io.sqrtOp, _oddSqrt_S_T)
node idle = eq(cycleNum, UInt<1>(0h0))
node entering = and(inReady, io.inValid)
node entering_normalCase = and(entering, normalCase_S)
node _processTwoBits_T = geq(cycleNum, UInt<2>(0h3))
node processTwoBits = and(_processTwoBits_T, UInt<1>(0h0))
node _skipCycle2_T = eq(cycleNum, UInt<2>(0h3))
node _skipCycle2_T_1 = bits(sigX_Z, 12, 12)
node _skipCycle2_T_2 = and(_skipCycle2_T, _skipCycle2_T_1)
node skipCycle2 = and(_skipCycle2_T_2, UInt<1>(0h1))
node _T = eq(idle, UInt<1>(0h0))
node _T_1 = or(_T, entering)
when _T_1 :
node _inReady_T = eq(normalCase_S, UInt<1>(0h0))
node _inReady_T_1 = and(entering, _inReady_T)
node _inReady_T_2 = leq(UInt<1>(0h1), UInt<1>(0h1))
node _inReady_T_3 = mux(_inReady_T_1, _inReady_T_2, UInt<1>(0h0))
node _inReady_T_4 = bits(io.a.sExp, 0, 0)
node _inReady_T_5 = leq(UInt<4>(0hb), UInt<1>(0h1))
node _inReady_T_6 = leq(UInt<4>(0hc), UInt<1>(0h1))
node _inReady_T_7 = mux(_inReady_T_4, _inReady_T_5, _inReady_T_6)
node _inReady_T_8 = leq(UInt<4>(0hd), UInt<1>(0h1))
node _inReady_T_9 = mux(io.sqrtOp, _inReady_T_7, _inReady_T_8)
node _inReady_T_10 = mux(entering_normalCase, _inReady_T_9, UInt<1>(0h0))
node _inReady_T_11 = or(_inReady_T_3, _inReady_T_10)
node _inReady_T_12 = eq(entering, UInt<1>(0h0))
node _inReady_T_13 = eq(skipCycle2, UInt<1>(0h0))
node _inReady_T_14 = and(_inReady_T_12, _inReady_T_13)
node _inReady_T_15 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1))
node _inReady_T_16 = sub(cycleNum, _inReady_T_15)
node _inReady_T_17 = tail(_inReady_T_16, 1)
node _inReady_T_18 = leq(_inReady_T_17, UInt<1>(0h1))
node _inReady_T_19 = mux(_inReady_T_14, _inReady_T_18, UInt<1>(0h0))
node _inReady_T_20 = or(_inReady_T_11, _inReady_T_19)
node _inReady_T_21 = leq(UInt<1>(0h1), UInt<1>(0h1))
node _inReady_T_22 = mux(skipCycle2, _inReady_T_21, UInt<1>(0h0))
node _inReady_T_23 = or(_inReady_T_20, _inReady_T_22)
node _inReady_T_24 = bits(_inReady_T_23, 0, 0)
connect inReady, _inReady_T_24
node _rawOutValid_T = eq(normalCase_S, UInt<1>(0h0))
node _rawOutValid_T_1 = and(entering, _rawOutValid_T)
node _rawOutValid_T_2 = eq(UInt<1>(0h1), UInt<1>(0h1))
node _rawOutValid_T_3 = mux(_rawOutValid_T_1, _rawOutValid_T_2, UInt<1>(0h0))
node _rawOutValid_T_4 = bits(io.a.sExp, 0, 0)
node _rawOutValid_T_5 = eq(UInt<4>(0hb), UInt<1>(0h1))
node _rawOutValid_T_6 = eq(UInt<4>(0hc), UInt<1>(0h1))
node _rawOutValid_T_7 = mux(_rawOutValid_T_4, _rawOutValid_T_5, _rawOutValid_T_6)
node _rawOutValid_T_8 = eq(UInt<4>(0hd), UInt<1>(0h1))
node _rawOutValid_T_9 = mux(io.sqrtOp, _rawOutValid_T_7, _rawOutValid_T_8)
node _rawOutValid_T_10 = mux(entering_normalCase, _rawOutValid_T_9, UInt<1>(0h0))
node _rawOutValid_T_11 = or(_rawOutValid_T_3, _rawOutValid_T_10)
node _rawOutValid_T_12 = eq(entering, UInt<1>(0h0))
node _rawOutValid_T_13 = eq(skipCycle2, UInt<1>(0h0))
node _rawOutValid_T_14 = and(_rawOutValid_T_12, _rawOutValid_T_13)
node _rawOutValid_T_15 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1))
node _rawOutValid_T_16 = sub(cycleNum, _rawOutValid_T_15)
node _rawOutValid_T_17 = tail(_rawOutValid_T_16, 1)
node _rawOutValid_T_18 = eq(_rawOutValid_T_17, UInt<1>(0h1))
node _rawOutValid_T_19 = mux(_rawOutValid_T_14, _rawOutValid_T_18, UInt<1>(0h0))
node _rawOutValid_T_20 = or(_rawOutValid_T_11, _rawOutValid_T_19)
node _rawOutValid_T_21 = eq(UInt<1>(0h1), UInt<1>(0h1))
node _rawOutValid_T_22 = mux(skipCycle2, _rawOutValid_T_21, UInt<1>(0h0))
node _rawOutValid_T_23 = or(_rawOutValid_T_20, _rawOutValid_T_22)
node _rawOutValid_T_24 = bits(_rawOutValid_T_23, 0, 0)
connect rawOutValid, _rawOutValid_T_24
node _cycleNum_T = eq(normalCase_S, UInt<1>(0h0))
node _cycleNum_T_1 = and(entering, _cycleNum_T)
node _cycleNum_T_2 = mux(_cycleNum_T_1, UInt<1>(0h1), UInt<1>(0h0))
node _cycleNum_T_3 = bits(io.a.sExp, 0, 0)
node _cycleNum_T_4 = mux(_cycleNum_T_3, UInt<4>(0hb), UInt<4>(0hc))
node _cycleNum_T_5 = mux(io.sqrtOp, _cycleNum_T_4, UInt<4>(0hd))
node _cycleNum_T_6 = mux(entering_normalCase, _cycleNum_T_5, UInt<1>(0h0))
node _cycleNum_T_7 = or(_cycleNum_T_2, _cycleNum_T_6)
node _cycleNum_T_8 = eq(entering, UInt<1>(0h0))
node _cycleNum_T_9 = eq(skipCycle2, UInt<1>(0h0))
node _cycleNum_T_10 = and(_cycleNum_T_8, _cycleNum_T_9)
node _cycleNum_T_11 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1))
node _cycleNum_T_12 = sub(cycleNum, _cycleNum_T_11)
node _cycleNum_T_13 = tail(_cycleNum_T_12, 1)
node _cycleNum_T_14 = mux(_cycleNum_T_10, _cycleNum_T_13, UInt<1>(0h0))
node _cycleNum_T_15 = or(_cycleNum_T_7, _cycleNum_T_14)
node _cycleNum_T_16 = mux(skipCycle2, UInt<1>(0h1), UInt<1>(0h0))
node _cycleNum_T_17 = or(_cycleNum_T_15, _cycleNum_T_16)
connect cycleNum, _cycleNum_T_17
connect io.inReady, inReady
when entering :
connect sqrtOp_Z, io.sqrtOp
connect majorExc_Z, majorExc_S
connect isNaN_Z, isNaN_S
connect isInf_Z, isInf_S
connect isZero_Z, isZero_S
connect sign_Z, sign_S
node _sExp_Z_T = shr(io.a.sExp, 1)
node _sExp_Z_T_1 = add(_sExp_Z_T, asSInt(UInt<6>(0h10)))
node _sExp_Z_T_2 = mux(io.sqrtOp, _sExp_Z_T_1, sSatExpQuot_S_div)
connect sExp_Z, _sExp_Z_T_2
connect roundingMode_Z, io.roundingMode
node _T_2 = eq(inReady, UInt<1>(0h0))
node _T_3 = and(_T_2, sqrtOp_Z)
node _T_4 = or(entering, _T_3)
when _T_4 :
node _fractB_Z_T = eq(io.sqrtOp, UInt<1>(0h0))
node _fractB_Z_T_1 = and(inReady, _fractB_Z_T)
node _fractB_Z_T_2 = bits(io.b.sig, 9, 0)
node _fractB_Z_T_3 = shl(_fractB_Z_T_2, 1)
node _fractB_Z_T_4 = mux(_fractB_Z_T_1, _fractB_Z_T_3, UInt<1>(0h0))
node _fractB_Z_T_5 = and(inReady, io.sqrtOp)
node _fractB_Z_T_6 = bits(io.a.sExp, 0, 0)
node _fractB_Z_T_7 = and(_fractB_Z_T_5, _fractB_Z_T_6)
node _fractB_Z_T_8 = mux(_fractB_Z_T_7, UInt<10>(0h200), UInt<1>(0h0))
node _fractB_Z_T_9 = or(_fractB_Z_T_4, _fractB_Z_T_8)
node _fractB_Z_T_10 = and(inReady, io.sqrtOp)
node _fractB_Z_T_11 = bits(io.a.sExp, 0, 0)
node _fractB_Z_T_12 = eq(_fractB_Z_T_11, UInt<1>(0h0))
node _fractB_Z_T_13 = and(_fractB_Z_T_10, _fractB_Z_T_12)
node _fractB_Z_T_14 = mux(_fractB_Z_T_13, UInt<11>(0h400), UInt<1>(0h0))
node _fractB_Z_T_15 = or(_fractB_Z_T_9, _fractB_Z_T_14)
node _fractB_Z_T_16 = eq(inReady, UInt<1>(0h0))
node _fractB_Z_T_17 = and(_fractB_Z_T_16, processTwoBits)
node _fractB_Z_T_18 = shr(fractB_Z, 2)
node _fractB_Z_T_19 = mux(_fractB_Z_T_17, _fractB_Z_T_18, UInt<1>(0h0))
node _fractB_Z_T_20 = or(_fractB_Z_T_15, _fractB_Z_T_19)
node _fractB_Z_T_21 = eq(inReady, UInt<1>(0h0))
node _fractB_Z_T_22 = eq(processTwoBits, UInt<1>(0h0))
node _fractB_Z_T_23 = and(_fractB_Z_T_21, _fractB_Z_T_22)
node _fractB_Z_T_24 = shr(fractB_Z, 1)
node _fractB_Z_T_25 = mux(_fractB_Z_T_23, _fractB_Z_T_24, UInt<1>(0h0))
node _fractB_Z_T_26 = or(_fractB_Z_T_20, _fractB_Z_T_25)
connect fractB_Z, _fractB_Z_T_26
node _rem_T = eq(oddSqrt_S, UInt<1>(0h0))
node _rem_T_1 = and(inReady, _rem_T)
node _rem_T_2 = shl(io.a.sig, 1)
node _rem_T_3 = mux(_rem_T_1, _rem_T_2, UInt<1>(0h0))
node _rem_T_4 = and(inReady, oddSqrt_S)
node _rem_T_5 = bits(io.a.sig, 10, 9)
node _rem_T_6 = sub(_rem_T_5, UInt<1>(0h1))
node _rem_T_7 = tail(_rem_T_6, 1)
node _rem_T_8 = bits(io.a.sig, 8, 0)
node _rem_T_9 = shl(_rem_T_8, 3)
node _rem_T_10 = cat(_rem_T_7, _rem_T_9)
node _rem_T_11 = mux(_rem_T_4, _rem_T_10, UInt<1>(0h0))
node _rem_T_12 = or(_rem_T_3, _rem_T_11)
node _rem_T_13 = eq(inReady, UInt<1>(0h0))
node _rem_T_14 = shl(rem_Z, 1)
node _rem_T_15 = mux(_rem_T_13, _rem_T_14, UInt<1>(0h0))
node rem = or(_rem_T_12, _rem_T_15)
node _bitMask_T = dshl(UInt<1>(0h1), cycleNum)
node bitMask = shr(_bitMask_T, 2)
node _trialTerm_T = eq(io.sqrtOp, UInt<1>(0h0))
node _trialTerm_T_1 = and(inReady, _trialTerm_T)
node _trialTerm_T_2 = shl(io.b.sig, 1)
node _trialTerm_T_3 = mux(_trialTerm_T_1, _trialTerm_T_2, UInt<1>(0h0))
node _trialTerm_T_4 = and(inReady, evenSqrt_S)
node _trialTerm_T_5 = mux(_trialTerm_T_4, UInt<12>(0h800), UInt<1>(0h0))
node _trialTerm_T_6 = or(_trialTerm_T_3, _trialTerm_T_5)
node _trialTerm_T_7 = and(inReady, oddSqrt_S)
node _trialTerm_T_8 = mux(_trialTerm_T_7, UInt<13>(0h1400), UInt<1>(0h0))
node _trialTerm_T_9 = or(_trialTerm_T_6, _trialTerm_T_8)
node _trialTerm_T_10 = eq(inReady, UInt<1>(0h0))
node _trialTerm_T_11 = mux(_trialTerm_T_10, fractB_Z, UInt<1>(0h0))
node _trialTerm_T_12 = or(_trialTerm_T_9, _trialTerm_T_11)
node _trialTerm_T_13 = eq(inReady, UInt<1>(0h0))
node _trialTerm_T_14 = eq(sqrtOp_Z, UInt<1>(0h0))
node _trialTerm_T_15 = and(_trialTerm_T_13, _trialTerm_T_14)
node _trialTerm_T_16 = shl(UInt<1>(0h1), 11)
node _trialTerm_T_17 = mux(_trialTerm_T_15, _trialTerm_T_16, UInt<1>(0h0))
node _trialTerm_T_18 = or(_trialTerm_T_12, _trialTerm_T_17)
node _trialTerm_T_19 = eq(inReady, UInt<1>(0h0))
node _trialTerm_T_20 = and(_trialTerm_T_19, sqrtOp_Z)
node _trialTerm_T_21 = shl(sigX_Z, 1)
node _trialTerm_T_22 = mux(_trialTerm_T_20, _trialTerm_T_21, UInt<1>(0h0))
node trialTerm = or(_trialTerm_T_18, _trialTerm_T_22)
node _trialRem_T = cvt(rem)
node _trialRem_T_1 = cvt(trialTerm)
node trialRem = sub(_trialRem_T, _trialRem_T_1)
node newBit = leq(asSInt(UInt<1>(0h0)), trialRem)
node _nextRem_Z_T = asUInt(trialRem)
node _nextRem_Z_T_1 = mux(newBit, _nextRem_Z_T, rem)
node nextRem_Z = bits(_nextRem_Z_T_1, 12, 0)
node rem2 = shl(nextRem_Z, 1)
node _trialTerm2_newBit0_T = shr(fractB_Z, 1)
node _trialTerm2_newBit0_T_1 = shl(sigX_Z, 1)
node _trialTerm2_newBit0_T_2 = or(_trialTerm2_newBit0_T, _trialTerm2_newBit0_T_1)
node _trialTerm2_newBit0_T_3 = shl(UInt<1>(0h1), 11)
node _trialTerm2_newBit0_T_4 = or(fractB_Z, _trialTerm2_newBit0_T_3)
node trialTerm2_newBit0 = mux(sqrtOp_Z, _trialTerm2_newBit0_T_2, _trialTerm2_newBit0_T_4)
node _trialTerm2_newBit1_T = shl(fractB_Z, 1)
node _trialTerm2_newBit1_T_1 = mux(sqrtOp_Z, _trialTerm2_newBit1_T, UInt<1>(0h0))
node trialTerm2_newBit1 = or(trialTerm2_newBit0, _trialTerm2_newBit1_T_1)
node _trialRem2_T = shl(trialRem, 1)
node _trialRem2_T_1 = cvt(trialTerm2_newBit1)
node _trialRem2_T_2 = sub(_trialRem2_T, _trialRem2_T_1)
node _trialRem2_T_3 = tail(_trialRem2_T_2, 1)
node _trialRem2_T_4 = asSInt(_trialRem2_T_3)
node _trialRem2_T_5 = shl(rem_Z, 2)
node _trialRem2_T_6 = bits(_trialRem2_T_5, 13, 0)
node _trialRem2_T_7 = cvt(_trialRem2_T_6)
node _trialRem2_T_8 = cvt(trialTerm2_newBit0)
node _trialRem2_T_9 = sub(_trialRem2_T_7, _trialRem2_T_8)
node _trialRem2_T_10 = tail(_trialRem2_T_9, 1)
node _trialRem2_T_11 = asSInt(_trialRem2_T_10)
node trialRem2 = mux(newBit, _trialRem2_T_4, _trialRem2_T_11)
node newBit2 = leq(asSInt(UInt<1>(0h0)), trialRem2)
node _nextNotZeroRem_Z_T = or(inReady, newBit)
node _nextNotZeroRem_Z_T_1 = neq(trialRem, asSInt(UInt<1>(0h0)))
node nextNotZeroRem_Z = mux(_nextNotZeroRem_Z_T, _nextNotZeroRem_Z_T_1, notZeroRem_Z)
node _nextNotZeroRem_Z_2_T = and(processTwoBits, newBit)
node _nextNotZeroRem_Z_2_T_1 = shl(trialRem, 1)
node _nextNotZeroRem_Z_2_T_2 = cvt(trialTerm2_newBit1)
node _nextNotZeroRem_Z_2_T_3 = sub(_nextNotZeroRem_Z_2_T_1, _nextNotZeroRem_Z_2_T_2)
node _nextNotZeroRem_Z_2_T_4 = tail(_nextNotZeroRem_Z_2_T_3, 1)
node _nextNotZeroRem_Z_2_T_5 = asSInt(_nextNotZeroRem_Z_2_T_4)
node _nextNotZeroRem_Z_2_T_6 = lt(asSInt(UInt<1>(0h0)), _nextNotZeroRem_Z_2_T_5)
node _nextNotZeroRem_Z_2_T_7 = and(_nextNotZeroRem_Z_2_T, _nextNotZeroRem_Z_2_T_6)
node _nextNotZeroRem_Z_2_T_8 = eq(newBit, UInt<1>(0h0))
node _nextNotZeroRem_Z_2_T_9 = and(processTwoBits, _nextNotZeroRem_Z_2_T_8)
node _nextNotZeroRem_Z_2_T_10 = shl(rem_Z, 2)
node _nextNotZeroRem_Z_2_T_11 = bits(_nextNotZeroRem_Z_2_T_10, 13, 0)
node _nextNotZeroRem_Z_2_T_12 = cvt(_nextNotZeroRem_Z_2_T_11)
node _nextNotZeroRem_Z_2_T_13 = cvt(trialTerm2_newBit0)
node _nextNotZeroRem_Z_2_T_14 = sub(_nextNotZeroRem_Z_2_T_12, _nextNotZeroRem_Z_2_T_13)
node _nextNotZeroRem_Z_2_T_15 = tail(_nextNotZeroRem_Z_2_T_14, 1)
node _nextNotZeroRem_Z_2_T_16 = asSInt(_nextNotZeroRem_Z_2_T_15)
node _nextNotZeroRem_Z_2_T_17 = lt(asSInt(UInt<1>(0h0)), _nextNotZeroRem_Z_2_T_16)
node _nextNotZeroRem_Z_2_T_18 = and(_nextNotZeroRem_Z_2_T_9, _nextNotZeroRem_Z_2_T_17)
node _nextNotZeroRem_Z_2_T_19 = or(_nextNotZeroRem_Z_2_T_7, _nextNotZeroRem_Z_2_T_18)
node _nextNotZeroRem_Z_2_T_20 = and(processTwoBits, newBit2)
node _nextNotZeroRem_Z_2_T_21 = eq(_nextNotZeroRem_Z_2_T_20, UInt<1>(0h0))
node _nextNotZeroRem_Z_2_T_22 = and(_nextNotZeroRem_Z_2_T_21, nextNotZeroRem_Z)
node nextNotZeroRem_Z_2 = or(_nextNotZeroRem_Z_2_T_19, _nextNotZeroRem_Z_2_T_22)
node _nextRem_Z_2_T = and(processTwoBits, newBit2)
node _nextRem_Z_2_T_1 = asUInt(trialRem2)
node _nextRem_Z_2_T_2 = bits(_nextRem_Z_2_T_1, 12, 0)
node _nextRem_Z_2_T_3 = mux(_nextRem_Z_2_T, _nextRem_Z_2_T_2, UInt<1>(0h0))
node _nextRem_Z_2_T_4 = eq(newBit2, UInt<1>(0h0))
node _nextRem_Z_2_T_5 = and(processTwoBits, _nextRem_Z_2_T_4)
node _nextRem_Z_2_T_6 = bits(rem2, 12, 0)
node _nextRem_Z_2_T_7 = mux(_nextRem_Z_2_T_5, _nextRem_Z_2_T_6, UInt<1>(0h0))
node _nextRem_Z_2_T_8 = or(_nextRem_Z_2_T_3, _nextRem_Z_2_T_7)
node _nextRem_Z_2_T_9 = eq(processTwoBits, UInt<1>(0h0))
node _nextRem_Z_2_T_10 = mux(_nextRem_Z_2_T_9, nextRem_Z, UInt<1>(0h0))
node nextRem_Z_2 = or(_nextRem_Z_2_T_8, _nextRem_Z_2_T_10)
node _T_5 = eq(inReady, UInt<1>(0h0))
node _T_6 = or(entering, _T_5)
when _T_6 :
connect notZeroRem_Z, nextNotZeroRem_Z_2
connect rem_Z, nextRem_Z_2
node _sigX_Z_T = eq(io.sqrtOp, UInt<1>(0h0))
node _sigX_Z_T_1 = and(inReady, _sigX_Z_T)
node _sigX_Z_T_2 = shl(newBit, 12)
node _sigX_Z_T_3 = mux(_sigX_Z_T_1, _sigX_Z_T_2, UInt<1>(0h0))
node _sigX_Z_T_4 = and(inReady, io.sqrtOp)
node _sigX_Z_T_5 = mux(_sigX_Z_T_4, UInt<12>(0h800), UInt<1>(0h0))
node _sigX_Z_T_6 = or(_sigX_Z_T_3, _sigX_Z_T_5)
node _sigX_Z_T_7 = and(inReady, oddSqrt_S)
node _sigX_Z_T_8 = shl(newBit, 10)
node _sigX_Z_T_9 = mux(_sigX_Z_T_7, _sigX_Z_T_8, UInt<1>(0h0))
node _sigX_Z_T_10 = or(_sigX_Z_T_6, _sigX_Z_T_9)
node _sigX_Z_T_11 = eq(inReady, UInt<1>(0h0))
node _sigX_Z_T_12 = mux(_sigX_Z_T_11, sigX_Z, UInt<1>(0h0))
node _sigX_Z_T_13 = or(_sigX_Z_T_10, _sigX_Z_T_12)
node _sigX_Z_T_14 = eq(inReady, UInt<1>(0h0))
node _sigX_Z_T_15 = and(_sigX_Z_T_14, newBit)
node _sigX_Z_T_16 = mux(_sigX_Z_T_15, bitMask, UInt<1>(0h0))
node _sigX_Z_T_17 = or(_sigX_Z_T_13, _sigX_Z_T_16)
node _sigX_Z_T_18 = and(processTwoBits, newBit2)
node _sigX_Z_T_19 = shr(bitMask, 1)
node _sigX_Z_T_20 = mux(_sigX_Z_T_18, _sigX_Z_T_19, UInt<1>(0h0))
node _sigX_Z_T_21 = or(_sigX_Z_T_17, _sigX_Z_T_20)
connect sigX_Z, _sigX_Z_T_21
node _io_rawOutValid_div_T = eq(sqrtOp_Z, UInt<1>(0h0))
node _io_rawOutValid_div_T_1 = and(rawOutValid, _io_rawOutValid_div_T)
connect io.rawOutValid_div, _io_rawOutValid_div_T_1
node _io_rawOutValid_sqrt_T = and(rawOutValid, sqrtOp_Z)
connect io.rawOutValid_sqrt, _io_rawOutValid_sqrt_T
connect io.roundingModeOut, roundingMode_Z
node _io_invalidExc_T = and(majorExc_Z, isNaN_Z)
connect io.invalidExc, _io_invalidExc_T
node _io_infiniteExc_T = eq(isNaN_Z, UInt<1>(0h0))
node _io_infiniteExc_T_1 = and(majorExc_Z, _io_infiniteExc_T)
connect io.infiniteExc, _io_infiniteExc_T_1
connect io.rawOut.isNaN, isNaN_Z
connect io.rawOut.isInf, isInf_Z
connect io.rawOut.isZero, isZero_Z
connect io.rawOut.sign, sign_Z
connect io.rawOut.sExp, sExp_Z
node _io_rawOut_sig_T = shl(sigX_Z, 1)
node _io_rawOut_sig_T_1 = or(_io_rawOut_sig_T, notZeroRem_Z)
connect io.rawOut.sig, _io_rawOut_sig_T_1 | module DivSqrtRawFN_small_e5_s11_2( // @[DivSqrtRecFN_small.scala:199:5]
input clock, // @[DivSqrtRecFN_small.scala:199:5]
input reset, // @[DivSqrtRecFN_small.scala:199:5]
output io_inReady, // @[DivSqrtRecFN_small.scala:203:16]
input io_inValid, // @[DivSqrtRecFN_small.scala:203:16]
input io_sqrtOp, // @[DivSqrtRecFN_small.scala:203:16]
input io_a_isNaN, // @[DivSqrtRecFN_small.scala:203:16]
input io_a_isInf, // @[DivSqrtRecFN_small.scala:203:16]
input io_a_isZero, // @[DivSqrtRecFN_small.scala:203:16]
input io_a_sign, // @[DivSqrtRecFN_small.scala:203:16]
input [6:0] io_a_sExp, // @[DivSqrtRecFN_small.scala:203:16]
input [11:0] io_a_sig, // @[DivSqrtRecFN_small.scala:203:16]
input io_b_isNaN, // @[DivSqrtRecFN_small.scala:203:16]
input io_b_isInf, // @[DivSqrtRecFN_small.scala:203:16]
input io_b_isZero, // @[DivSqrtRecFN_small.scala:203:16]
input io_b_sign, // @[DivSqrtRecFN_small.scala:203:16]
input [6:0] io_b_sExp, // @[DivSqrtRecFN_small.scala:203:16]
input [11:0] io_b_sig, // @[DivSqrtRecFN_small.scala:203:16]
input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:203:16]
output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:203:16]
output io_invalidExc, // @[DivSqrtRecFN_small.scala:203:16]
output io_infiniteExc, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:203:16]
output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:203:16]
output [6:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:203:16]
output [13:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:203:16]
);
wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:199:5]
wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:199:5]
wire io_a_isNaN_0 = io_a_isNaN; // @[DivSqrtRecFN_small.scala:199:5]
wire io_a_isInf_0 = io_a_isInf; // @[DivSqrtRecFN_small.scala:199:5]
wire io_a_isZero_0 = io_a_isZero; // @[DivSqrtRecFN_small.scala:199:5]
wire io_a_sign_0 = io_a_sign; // @[DivSqrtRecFN_small.scala:199:5]
wire [6:0] io_a_sExp_0 = io_a_sExp; // @[DivSqrtRecFN_small.scala:199:5]
wire [11:0] io_a_sig_0 = io_a_sig; // @[DivSqrtRecFN_small.scala:199:5]
wire io_b_isNaN_0 = io_b_isNaN; // @[DivSqrtRecFN_small.scala:199:5]
wire io_b_isInf_0 = io_b_isInf; // @[DivSqrtRecFN_small.scala:199:5]
wire io_b_isZero_0 = io_b_isZero; // @[DivSqrtRecFN_small.scala:199:5]
wire io_b_sign_0 = io_b_sign; // @[DivSqrtRecFN_small.scala:199:5]
wire [6:0] io_b_sExp_0 = io_b_sExp; // @[DivSqrtRecFN_small.scala:199:5]
wire [11:0] io_b_sig_0 = io_b_sig; // @[DivSqrtRecFN_small.scala:199:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:199:5]
wire [1:0] _inReady_T_15 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61]
wire [1:0] _rawOutValid_T_15 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61]
wire [1:0] _cycleNum_T_11 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61]
wire [8:0] _fractB_Z_T_19 = 9'h0; // @[DivSqrtRecFN_small.scala:345:16]
wire [11:0] _trialTerm_T_16 = 12'h800; // @[DivSqrtRecFN_small.scala:366:42]
wire [11:0] _trialTerm2_newBit0_T_3 = 12'h800; // @[DivSqrtRecFN_small.scala:373:85]
wire _inReady_T_2 = 1'h1; // @[DivSqrtRecFN_small.scala:317:38]
wire _inReady_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:317:38]
wire _rawOutValid_T_2 = 1'h1; // @[DivSqrtRecFN_small.scala:318:42]
wire _rawOutValid_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:318:42]
wire _fractB_Z_T_22 = 1'h1; // @[DivSqrtRecFN_small.scala:346:45]
wire _nextNotZeroRem_Z_2_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:384:9]
wire _nextRem_Z_2_T_9 = 1'h1; // @[DivSqrtRecFN_small.scala:388:13]
wire processTwoBits = 1'h0; // @[DivSqrtRecFN_small.scala:300:42]
wire _inReady_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38]
wire _inReady_T_6 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38]
wire _inReady_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:308:24]
wire _inReady_T_8 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38]
wire _inReady_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:307:20]
wire _inReady_T_10 = 1'h0; // @[DivSqrtRecFN_small.scala:306:16]
wire _rawOutValid_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42]
wire _rawOutValid_T_6 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42]
wire _rawOutValid_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:308:24]
wire _rawOutValid_T_8 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42]
wire _rawOutValid_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:307:20]
wire _rawOutValid_T_10 = 1'h0; // @[DivSqrtRecFN_small.scala:306:16]
wire _fractB_Z_T_17 = 1'h0; // @[DivSqrtRecFN_small.scala:345:42]
wire _nextNotZeroRem_Z_2_T = 1'h0; // @[DivSqrtRecFN_small.scala:382:24]
wire _nextNotZeroRem_Z_2_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:382:34]
wire _nextNotZeroRem_Z_2_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:383:24]
wire _nextNotZeroRem_Z_2_T_18 = 1'h0; // @[DivSqrtRecFN_small.scala:383:35]
wire _nextNotZeroRem_Z_2_T_19 = 1'h0; // @[DivSqrtRecFN_small.scala:382:85]
wire _nextNotZeroRem_Z_2_T_20 = 1'h0; // @[DivSqrtRecFN_small.scala:384:26]
wire _nextRem_Z_2_T = 1'h0; // @[DivSqrtRecFN_small.scala:386:28]
wire _nextRem_Z_2_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:387:28]
wire _sigX_Z_T_18 = 1'h0; // @[DivSqrtRecFN_small.scala:399:32]
wire [12:0] _nextRem_Z_2_T_3 = 13'h0; // @[DivSqrtRecFN_small.scala:386:12]
wire [12:0] _nextRem_Z_2_T_7 = 13'h0; // @[DivSqrtRecFN_small.scala:387:12]
wire [12:0] _nextRem_Z_2_T_8 = 13'h0; // @[DivSqrtRecFN_small.scala:386:81]
wire [12:0] _sigX_Z_T_20 = 13'h0; // @[DivSqrtRecFN_small.scala:399:16]
wire _io_rawOutValid_div_T_1; // @[DivSqrtRecFN_small.scala:404:40]
wire _io_rawOutValid_sqrt_T; // @[DivSqrtRecFN_small.scala:405:40]
wire _io_invalidExc_T; // @[DivSqrtRecFN_small.scala:407:36]
wire _io_infiniteExc_T_1; // @[DivSqrtRecFN_small.scala:408:36]
wire [13:0] _io_rawOut_sig_T_1; // @[DivSqrtRecFN_small.scala:414:35]
wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:199:5]
wire [6:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:199:5]
wire [13:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_inReady_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:199:5]
wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:199:5]
wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:199:5]
reg [3:0] cycleNum; // @[DivSqrtRecFN_small.scala:224:33]
reg inReady; // @[DivSqrtRecFN_small.scala:225:33]
assign io_inReady_0 = inReady; // @[DivSqrtRecFN_small.scala:199:5, :225:33]
reg rawOutValid; // @[DivSqrtRecFN_small.scala:226:33]
reg sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29]
reg majorExc_Z; // @[DivSqrtRecFN_small.scala:229:29]
reg isNaN_Z; // @[DivSqrtRecFN_small.scala:231:29]
assign io_rawOut_isNaN_0 = isNaN_Z; // @[DivSqrtRecFN_small.scala:199:5, :231:29]
reg isInf_Z; // @[DivSqrtRecFN_small.scala:232:29]
assign io_rawOut_isInf_0 = isInf_Z; // @[DivSqrtRecFN_small.scala:199:5, :232:29]
reg isZero_Z; // @[DivSqrtRecFN_small.scala:233:29]
assign io_rawOut_isZero_0 = isZero_Z; // @[DivSqrtRecFN_small.scala:199:5, :233:29]
reg sign_Z; // @[DivSqrtRecFN_small.scala:234:29]
assign io_rawOut_sign_0 = sign_Z; // @[DivSqrtRecFN_small.scala:199:5, :234:29]
reg [6:0] sExp_Z; // @[DivSqrtRecFN_small.scala:235:29]
assign io_rawOut_sExp_0 = sExp_Z; // @[DivSqrtRecFN_small.scala:199:5, :235:29]
reg [10:0] fractB_Z; // @[DivSqrtRecFN_small.scala:236:29]
reg [2:0] roundingMode_Z; // @[DivSqrtRecFN_small.scala:237:29]
assign io_roundingModeOut_0 = roundingMode_Z; // @[DivSqrtRecFN_small.scala:199:5, :237:29]
reg [12:0] rem_Z; // @[DivSqrtRecFN_small.scala:243:29]
reg notZeroRem_Z; // @[DivSqrtRecFN_small.scala:244:29]
reg [12:0] sigX_Z; // @[DivSqrtRecFN_small.scala:245:29]
wire _notSigNaNIn_invalidExc_S_div_T = io_a_isZero_0 & io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :254:24]
wire _notSigNaNIn_invalidExc_S_div_T_1 = io_a_isInf_0 & io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :254:59]
wire notSigNaNIn_invalidExc_S_div = _notSigNaNIn_invalidExc_S_div_T | _notSigNaNIn_invalidExc_S_div_T_1; // @[DivSqrtRecFN_small.scala:254:{24,42,59}]
wire _notSigNaNIn_invalidExc_S_sqrt_T = ~io_a_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :256:9]
wire _notSigNaNIn_invalidExc_S_sqrt_T_1 = ~io_a_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :256:27]
wire _notSigNaNIn_invalidExc_S_sqrt_T_2 = _notSigNaNIn_invalidExc_S_sqrt_T & _notSigNaNIn_invalidExc_S_sqrt_T_1; // @[DivSqrtRecFN_small.scala:256:{9,24,27}]
wire notSigNaNIn_invalidExc_S_sqrt = _notSigNaNIn_invalidExc_S_sqrt_T_2 & io_a_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :256:{24,43}]
wire _majorExc_S_T = io_a_sig_0[9]; // @[common.scala:82:56]
wire _majorExc_S_T_4 = io_a_sig_0[9]; // @[common.scala:82:56]
wire _majorExc_S_T_1 = ~_majorExc_S_T; // @[common.scala:82:{49,56}]
wire _majorExc_S_T_2 = io_a_isNaN_0 & _majorExc_S_T_1; // @[common.scala:82:{46,49}]
wire _majorExc_S_T_3 = _majorExc_S_T_2 | notSigNaNIn_invalidExc_S_sqrt; // @[common.scala:82:46]
wire _majorExc_S_T_5 = ~_majorExc_S_T_4; // @[common.scala:82:{49,56}]
wire _majorExc_S_T_6 = io_a_isNaN_0 & _majorExc_S_T_5; // @[common.scala:82:{46,49}]
wire _majorExc_S_T_7 = io_b_sig_0[9]; // @[common.scala:82:56]
wire _majorExc_S_T_8 = ~_majorExc_S_T_7; // @[common.scala:82:{49,56}]
wire _majorExc_S_T_9 = io_b_isNaN_0 & _majorExc_S_T_8; // @[common.scala:82:{46,49}]
wire _majorExc_S_T_10 = _majorExc_S_T_6 | _majorExc_S_T_9; // @[common.scala:82:46]
wire _majorExc_S_T_11 = _majorExc_S_T_10 | notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecFN_small.scala:254:42, :260:{38,66}]
wire _majorExc_S_T_12 = ~io_a_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :256:9, :262:18]
wire _majorExc_S_T_13 = ~io_a_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :262:36]
wire _majorExc_S_T_14 = _majorExc_S_T_12 & _majorExc_S_T_13; // @[DivSqrtRecFN_small.scala:262:{18,33,36}]
wire _majorExc_S_T_15 = _majorExc_S_T_14 & io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :262:{33,51}]
wire _majorExc_S_T_16 = _majorExc_S_T_11 | _majorExc_S_T_15; // @[DivSqrtRecFN_small.scala:260:66, :261:46, :262:51]
wire majorExc_S = io_sqrtOp_0 ? _majorExc_S_T_3 : _majorExc_S_T_16; // @[DivSqrtRecFN_small.scala:199:5, :258:12, :259:38, :261:46]
wire _isNaN_S_T = io_a_isNaN_0 | notSigNaNIn_invalidExc_S_sqrt; // @[DivSqrtRecFN_small.scala:199:5, :256:43, :266:26]
wire _isNaN_S_T_1 = io_a_isNaN_0 | io_b_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :267:26]
wire _isNaN_S_T_2 = _isNaN_S_T_1 | notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecFN_small.scala:254:42, :267:{26,42}]
wire isNaN_S = io_sqrtOp_0 ? _isNaN_S_T : _isNaN_S_T_2; // @[DivSqrtRecFN_small.scala:199:5, :265:12, :266:26, :267:42]
wire _isInf_S_T = io_a_isInf_0 | io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :269:63]
wire isInf_S = io_sqrtOp_0 ? io_a_isInf_0 : _isInf_S_T; // @[DivSqrtRecFN_small.scala:199:5, :269:{23,63}]
wire _isZero_S_T = io_a_isZero_0 | io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :270:64]
wire isZero_S = io_sqrtOp_0 ? io_a_isZero_0 : _isZero_S_T; // @[DivSqrtRecFN_small.scala:199:5, :270:{23,64}]
wire _sign_S_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33]
wire _sign_S_T_1 = _sign_S_T & io_b_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :271:{33,45}]
wire sign_S = io_a_sign_0 ^ _sign_S_T_1; // @[DivSqrtRecFN_small.scala:199:5, :271:{30,45}]
wire _specialCaseA_S_T = io_a_isNaN_0 | io_a_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :273:39]
wire specialCaseA_S = _specialCaseA_S_T | io_a_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :273:{39,55}]
wire _specialCaseB_S_T = io_b_isNaN_0 | io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :274:39]
wire specialCaseB_S = _specialCaseB_S_T | io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :274:{39,55}]
wire _normalCase_S_div_T = ~specialCaseA_S; // @[DivSqrtRecFN_small.scala:273:55, :275:28]
wire _normalCase_S_div_T_1 = ~specialCaseB_S; // @[DivSqrtRecFN_small.scala:274:55, :275:48]
wire normalCase_S_div = _normalCase_S_div_T & _normalCase_S_div_T_1; // @[DivSqrtRecFN_small.scala:275:{28,45,48}]
wire _normalCase_S_sqrt_T = ~specialCaseA_S; // @[DivSqrtRecFN_small.scala:273:55, :275:28, :276:29]
wire _normalCase_S_sqrt_T_1 = ~io_a_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :276:49]
wire normalCase_S_sqrt = _normalCase_S_sqrt_T & _normalCase_S_sqrt_T_1; // @[DivSqrtRecFN_small.scala:276:{29,46,49}]
wire normalCase_S = io_sqrtOp_0 ? normalCase_S_sqrt : normalCase_S_div; // @[DivSqrtRecFN_small.scala:199:5, :275:45, :276:46, :277:27]
wire _sExpQuot_S_div_T = io_b_sExp_0[5]; // @[DivSqrtRecFN_small.scala:199:5, :281:28]
wire [4:0] _sExpQuot_S_div_T_1 = io_b_sExp_0[4:0]; // @[DivSqrtRecFN_small.scala:199:5, :281:52]
wire [4:0] _sExpQuot_S_div_T_2 = ~_sExpQuot_S_div_T_1; // @[DivSqrtRecFN_small.scala:281:{40,52}]
wire [5:0] _sExpQuot_S_div_T_3 = {_sExpQuot_S_div_T, _sExpQuot_S_div_T_2}; // @[DivSqrtRecFN_small.scala:281:{16,28,40}]
wire [5:0] _sExpQuot_S_div_T_4 = _sExpQuot_S_div_T_3; // @[DivSqrtRecFN_small.scala:281:{16,71}]
wire [7:0] sExpQuot_S_div = {io_a_sExp_0[6], io_a_sExp_0} + {{2{_sExpQuot_S_div_T_4[5]}}, _sExpQuot_S_div_T_4}; // @[DivSqrtRecFN_small.scala:199:5, :280:21, :281:71]
wire _sSatExpQuot_S_div_T = $signed(sExpQuot_S_div) > 8'sh37; // @[DivSqrtRecFN_small.scala:280:21, :284:48]
wire [3:0] _sSatExpQuot_S_div_T_1 = sExpQuot_S_div[6:3]; // @[DivSqrtRecFN_small.scala:280:21, :286:31]
wire [3:0] _sSatExpQuot_S_div_T_2 = _sSatExpQuot_S_div_T ? 4'h6 : _sSatExpQuot_S_div_T_1; // @[DivSqrtRecFN_small.scala:284:{16,48}, :286:31]
wire [2:0] _sSatExpQuot_S_div_T_3 = sExpQuot_S_div[2:0]; // @[DivSqrtRecFN_small.scala:280:21, :288:27]
wire [6:0] _sSatExpQuot_S_div_T_4 = {_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3}; // @[DivSqrtRecFN_small.scala:284:{12,16}, :288:27]
wire [6:0] sSatExpQuot_S_div = _sSatExpQuot_S_div_T_4; // @[DivSqrtRecFN_small.scala:284:12, :289:11]
wire _evenSqrt_S_T = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48]
wire _oddSqrt_S_T = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :292:48]
wire _inReady_T_4 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36]
wire _rawOutValid_T_4 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36]
wire _cycleNum_T_3 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36]
wire _fractB_Z_T_6 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :343:52]
wire _fractB_Z_T_11 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :344:54]
wire _evenSqrt_S_T_1 = ~_evenSqrt_S_T; // @[DivSqrtRecFN_small.scala:291:{35,48}]
wire evenSqrt_S = io_sqrtOp_0 & _evenSqrt_S_T_1; // @[DivSqrtRecFN_small.scala:199:5, :291:{32,35}]
wire oddSqrt_S = io_sqrtOp_0 & _oddSqrt_S_T; // @[DivSqrtRecFN_small.scala:199:5, :292:{32,48}]
wire idle = cycleNum == 4'h0; // @[DivSqrtRecFN_small.scala:224:33, :296:25]
wire entering = inReady & io_inValid_0; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :297:28]
wire entering_normalCase = entering & normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :297:28, :298:40]
wire _processTwoBits_T = cycleNum > 4'h2; // @[DivSqrtRecFN_small.scala:224:33, :300:35]
wire _skipCycle2_T = cycleNum == 4'h3; // @[DivSqrtRecFN_small.scala:224:33, :301:31]
wire _skipCycle2_T_1 = sigX_Z[12]; // @[DivSqrtRecFN_small.scala:245:29, :301:48]
wire _skipCycle2_T_2 = _skipCycle2_T & _skipCycle2_T_1; // @[DivSqrtRecFN_small.scala:301:{31,39,48}]
wire skipCycle2 = _skipCycle2_T_2; // @[DivSqrtRecFN_small.scala:301:{39,63}]
wire _inReady_T_22 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16]
wire _rawOutValid_T_22 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16]
wire _cycleNum_T_16 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16]
wire _inReady_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28]
wire _inReady_T_1 = entering & _inReady_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}]
wire _inReady_T_3 = _inReady_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}]
wire _inReady_T_11 = _inReady_T_3; // @[DivSqrtRecFN_small.scala:305:{16,57}]
wire _inReady_T_12 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17]
wire _inReady_T_13 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31]
wire _inReady_T_14 = _inReady_T_12 & _inReady_T_13; // @[DivSqrtRecFN_small.scala:313:{17,28,31}]
wire [4:0] _GEN = {1'h0, cycleNum} - 5'h1; // @[DivSqrtRecFN_small.scala:224:33, :313:56]
wire [4:0] _inReady_T_16; // @[DivSqrtRecFN_small.scala:313:56]
assign _inReady_T_16 = _GEN; // @[DivSqrtRecFN_small.scala:313:56]
wire [4:0] _rawOutValid_T_16; // @[DivSqrtRecFN_small.scala:313:56]
assign _rawOutValid_T_16 = _GEN; // @[DivSqrtRecFN_small.scala:313:56]
wire [4:0] _cycleNum_T_12; // @[DivSqrtRecFN_small.scala:313:56]
assign _cycleNum_T_12 = _GEN; // @[DivSqrtRecFN_small.scala:313:56]
wire [3:0] _inReady_T_17 = _inReady_T_16[3:0]; // @[DivSqrtRecFN_small.scala:313:56]
wire _inReady_T_18 = _inReady_T_17 < 4'h2; // @[DivSqrtRecFN_small.scala:313:56, :317:38]
wire _inReady_T_19 = _inReady_T_14 & _inReady_T_18; // @[DivSqrtRecFN_small.scala:313:{16,28}, :317:38]
wire _inReady_T_20 = _inReady_T_11 | _inReady_T_19; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16]
wire _inReady_T_23 = _inReady_T_20 | _inReady_T_22; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16]
wire _inReady_T_24 = _inReady_T_23; // @[DivSqrtRecFN_small.scala:313:95, :317:46]
wire _rawOutValid_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28]
wire _rawOutValid_T_1 = entering & _rawOutValid_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}]
wire _rawOutValid_T_3 = _rawOutValid_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}]
wire _rawOutValid_T_11 = _rawOutValid_T_3; // @[DivSqrtRecFN_small.scala:305:{16,57}]
wire _rawOutValid_T_12 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17]
wire _rawOutValid_T_13 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31]
wire _rawOutValid_T_14 = _rawOutValid_T_12 & _rawOutValid_T_13; // @[DivSqrtRecFN_small.scala:313:{17,28,31}]
wire [3:0] _rawOutValid_T_17 = _rawOutValid_T_16[3:0]; // @[DivSqrtRecFN_small.scala:313:56]
wire _rawOutValid_T_18 = _rawOutValid_T_17 == 4'h1; // @[DivSqrtRecFN_small.scala:313:56, :318:42]
wire _rawOutValid_T_19 = _rawOutValid_T_14 & _rawOutValid_T_18; // @[DivSqrtRecFN_small.scala:313:{16,28}, :318:42]
wire _rawOutValid_T_20 = _rawOutValid_T_11 | _rawOutValid_T_19; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16]
wire _rawOutValid_T_23 = _rawOutValid_T_20 | _rawOutValid_T_22; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16]
wire _rawOutValid_T_24 = _rawOutValid_T_23; // @[DivSqrtRecFN_small.scala:313:95, :318:51]
wire _cycleNum_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28]
wire _cycleNum_T_1 = entering & _cycleNum_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}]
wire _cycleNum_T_2 = _cycleNum_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}]
wire [3:0] _cycleNum_T_4 = _cycleNum_T_3 ? 4'hB : 4'hC; // @[DivSqrtRecFN_small.scala:308:{24,36}]
wire [3:0] _cycleNum_T_5 = io_sqrtOp_0 ? _cycleNum_T_4 : 4'hD; // @[DivSqrtRecFN_small.scala:199:5, :307:20, :308:24]
wire [3:0] _cycleNum_T_6 = entering_normalCase ? _cycleNum_T_5 : 4'h0; // @[DivSqrtRecFN_small.scala:298:40, :306:16, :307:20]
wire [3:0] _cycleNum_T_7 = {3'h0, _cycleNum_T_2} | _cycleNum_T_6; // @[DivSqrtRecFN_small.scala:305:{16,57}, :306:16, :313:56]
wire _cycleNum_T_8 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17]
wire _cycleNum_T_9 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31]
wire _cycleNum_T_10 = _cycleNum_T_8 & _cycleNum_T_9; // @[DivSqrtRecFN_small.scala:313:{17,28,31}]
wire [3:0] _cycleNum_T_13 = _cycleNum_T_12[3:0]; // @[DivSqrtRecFN_small.scala:313:56]
wire [3:0] _cycleNum_T_14 = _cycleNum_T_10 ? _cycleNum_T_13 : 4'h0; // @[DivSqrtRecFN_small.scala:313:{16,28,56}]
wire [3:0] _cycleNum_T_15 = _cycleNum_T_7 | _cycleNum_T_14; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16]
wire [3:0] _cycleNum_T_17 = {_cycleNum_T_15[3:1], _cycleNum_T_15[0] | _cycleNum_T_16}; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16]
wire [5:0] _sExp_Z_T = io_a_sExp_0[6:1]; // @[DivSqrtRecFN_small.scala:199:5, :335:29]
wire [6:0] _sExp_Z_T_1 = {_sExp_Z_T[5], _sExp_Z_T} + 7'h10; // @[DivSqrtRecFN_small.scala:335:{29,34}]
wire [6:0] _sExp_Z_T_2 = io_sqrtOp_0 ? _sExp_Z_T_1 : sSatExpQuot_S_div; // @[DivSqrtRecFN_small.scala:199:5, :289:11, :334:16, :335:34]
wire _fractB_Z_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :342:28]
wire _fractB_Z_T_1 = inReady & _fractB_Z_T; // @[DivSqrtRecFN_small.scala:225:33, :342:{25,28}]
wire [9:0] _fractB_Z_T_2 = io_b_sig_0[9:0]; // @[DivSqrtRecFN_small.scala:199:5, :342:73]
wire [10:0] _fractB_Z_T_3 = {_fractB_Z_T_2, 1'h0}; // @[DivSqrtRecFN_small.scala:342:{73,90}]
wire [10:0] _fractB_Z_T_4 = _fractB_Z_T_1 ? _fractB_Z_T_3 : 11'h0; // @[DivSqrtRecFN_small.scala:342:{16,25,90}]
wire _GEN_0 = inReady & io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :343:25]
wire _fractB_Z_T_5; // @[DivSqrtRecFN_small.scala:343:25]
assign _fractB_Z_T_5 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25]
wire _fractB_Z_T_10; // @[DivSqrtRecFN_small.scala:344:25]
assign _fractB_Z_T_10 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25, :344:25]
wire _sigX_Z_T_4; // @[DivSqrtRecFN_small.scala:395:25]
assign _sigX_Z_T_4 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25, :395:25]
wire _fractB_Z_T_7 = _fractB_Z_T_5 & _fractB_Z_T_6; // @[DivSqrtRecFN_small.scala:343:{25,38,52}]
wire [9:0] _fractB_Z_T_8 = {_fractB_Z_T_7, 9'h0}; // @[DivSqrtRecFN_small.scala:343:{16,38}]
wire [10:0] _fractB_Z_T_9 = {_fractB_Z_T_4[10], _fractB_Z_T_4[9:0] | _fractB_Z_T_8}; // @[DivSqrtRecFN_small.scala:342:{16,100}, :343:16]
wire _fractB_Z_T_12 = ~_fractB_Z_T_11; // @[DivSqrtRecFN_small.scala:344:{41,54}]
wire _fractB_Z_T_13 = _fractB_Z_T_10 & _fractB_Z_T_12; // @[DivSqrtRecFN_small.scala:344:{25,38,41}]
wire [10:0] _fractB_Z_T_14 = {_fractB_Z_T_13, 10'h0}; // @[DivSqrtRecFN_small.scala:344:{16,38}]
wire [10:0] _fractB_Z_T_15 = _fractB_Z_T_9 | _fractB_Z_T_14; // @[DivSqrtRecFN_small.scala:342:100, :343:100, :344:16]
wire [10:0] _fractB_Z_T_20 = _fractB_Z_T_15; // @[DivSqrtRecFN_small.scala:343:100, :344:100]
wire _fractB_Z_T_16 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :345:17]
wire [8:0] _fractB_Z_T_18 = fractB_Z[10:2]; // @[DivSqrtRecFN_small.scala:236:29, :345:71]
wire _fractB_Z_T_21 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :346:17]
wire _fractB_Z_T_23 = _fractB_Z_T_21; // @[DivSqrtRecFN_small.scala:346:{17,42}]
wire [9:0] _fractB_Z_T_24 = fractB_Z[10:1]; // @[DivSqrtRecFN_small.scala:236:29, :346:71]
wire [9:0] _trialTerm2_newBit0_T = fractB_Z[10:1]; // @[DivSqrtRecFN_small.scala:236:29, :346:71, :373:52]
wire [9:0] _fractB_Z_T_25 = _fractB_Z_T_23 ? _fractB_Z_T_24 : 10'h0; // @[DivSqrtRecFN_small.scala:346:{16,42,71}]
wire [10:0] _fractB_Z_T_26 = {_fractB_Z_T_20[10], _fractB_Z_T_20[9:0] | _fractB_Z_T_25}; // @[DivSqrtRecFN_small.scala:344:100, :345:100, :346:16]
wire _rem_T = ~oddSqrt_S; // @[DivSqrtRecFN_small.scala:292:32, :352:24]
wire _rem_T_1 = inReady & _rem_T; // @[DivSqrtRecFN_small.scala:225:33, :352:{21,24}]
wire [12:0] _rem_T_2 = {io_a_sig_0, 1'h0}; // @[DivSqrtRecFN_small.scala:199:5, :352:47]
wire [12:0] _rem_T_3 = _rem_T_1 ? _rem_T_2 : 13'h0; // @[DivSqrtRecFN_small.scala:352:{12,21,47}]
wire _GEN_1 = inReady & oddSqrt_S; // @[DivSqrtRecFN_small.scala:225:33, :292:32, :353:21]
wire _rem_T_4; // @[DivSqrtRecFN_small.scala:353:21]
assign _rem_T_4 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21]
wire _trialTerm_T_7; // @[DivSqrtRecFN_small.scala:364:21]
assign _trialTerm_T_7 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21, :364:21]
wire _sigX_Z_T_7; // @[DivSqrtRecFN_small.scala:396:25]
assign _sigX_Z_T_7 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21, :396:25]
wire [1:0] _rem_T_5 = io_a_sig_0[10:9]; // @[DivSqrtRecFN_small.scala:199:5, :354:27]
wire [2:0] _rem_T_6 = {1'h0, _rem_T_5} - 3'h1; // @[DivSqrtRecFN_small.scala:354:{27,56}]
wire [1:0] _rem_T_7 = _rem_T_6[1:0]; // @[DivSqrtRecFN_small.scala:354:56]
wire [8:0] _rem_T_8 = io_a_sig_0[8:0]; // @[DivSqrtRecFN_small.scala:199:5, :355:27]
wire [11:0] _rem_T_9 = {_rem_T_8, 3'h0}; // @[DivSqrtRecFN_small.scala:313:56, :355:{27,44}]
wire [13:0] _rem_T_10 = {_rem_T_7, _rem_T_9}; // @[DivSqrtRecFN_small.scala:354:{16,56}, :355:44]
wire [13:0] _rem_T_11 = _rem_T_4 ? _rem_T_10 : 14'h0; // @[DivSqrtRecFN_small.scala:353:{12,21}, :354:16]
wire [13:0] _rem_T_12 = {1'h0, _rem_T_3} | _rem_T_11; // @[DivSqrtRecFN_small.scala:352:{12,57}, :353:12]
wire _rem_T_13 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :359:13]
wire [13:0] _rem_T_14 = {rem_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:243:29, :359:29]
wire [13:0] _rem_T_15 = _rem_T_13 ? _rem_T_14 : 14'h0; // @[DivSqrtRecFN_small.scala:359:{12,13,29}]
wire [13:0] rem = _rem_T_12 | _rem_T_15; // @[DivSqrtRecFN_small.scala:352:57, :358:11, :359:12]
wire [15:0] _bitMask_T = 16'h1 << cycleNum; // @[DivSqrtRecFN_small.scala:224:33, :360:23]
wire [13:0] bitMask = _bitMask_T[15:2]; // @[DivSqrtRecFN_small.scala:360:{23,34}]
wire _trialTerm_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :362:24]
wire _trialTerm_T_1 = inReady & _trialTerm_T; // @[DivSqrtRecFN_small.scala:225:33, :362:{21,24}]
wire [12:0] _trialTerm_T_2 = {io_b_sig_0, 1'h0}; // @[DivSqrtRecFN_small.scala:199:5, :362:48]
wire [12:0] _trialTerm_T_3 = _trialTerm_T_1 ? _trialTerm_T_2 : 13'h0; // @[DivSqrtRecFN_small.scala:362:{12,21,48}]
wire _trialTerm_T_4 = inReady & evenSqrt_S; // @[DivSqrtRecFN_small.scala:225:33, :291:32, :363:21]
wire [11:0] _trialTerm_T_5 = {_trialTerm_T_4, 11'h0}; // @[DivSqrtRecFN_small.scala:363:{12,21}]
wire [12:0] _trialTerm_T_6 = {_trialTerm_T_3[12], _trialTerm_T_3[11:0] | _trialTerm_T_5}; // @[DivSqrtRecFN_small.scala:362:{12,74}, :363:12]
wire [12:0] _trialTerm_T_8 = _trialTerm_T_7 ? 13'h1400 : 13'h0; // @[DivSqrtRecFN_small.scala:364:{12,21}]
wire [12:0] _trialTerm_T_9 = _trialTerm_T_6 | _trialTerm_T_8; // @[DivSqrtRecFN_small.scala:362:74, :363:74, :364:12]
wire _trialTerm_T_10 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :365:13]
wire [10:0] _trialTerm_T_11 = _trialTerm_T_10 ? fractB_Z : 11'h0; // @[DivSqrtRecFN_small.scala:236:29, :365:{12,13}]
wire [12:0] _trialTerm_T_12 = {_trialTerm_T_9[12:11], _trialTerm_T_9[10:0] | _trialTerm_T_11}; // @[DivSqrtRecFN_small.scala:363:74, :364:74, :365:12]
wire _trialTerm_T_13 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :366:13]
wire _trialTerm_T_14 = ~sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :366:26]
wire _trialTerm_T_15 = _trialTerm_T_13 & _trialTerm_T_14; // @[DivSqrtRecFN_small.scala:366:{13,23,26}]
wire [11:0] _trialTerm_T_17 = {_trialTerm_T_15, 11'h0}; // @[DivSqrtRecFN_small.scala:366:{12,23}]
wire [12:0] _trialTerm_T_18 = {_trialTerm_T_12[12], _trialTerm_T_12[11:0] | _trialTerm_T_17}; // @[DivSqrtRecFN_small.scala:364:74, :365:74, :366:12]
wire _trialTerm_T_19 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :367:13]
wire _trialTerm_T_20 = _trialTerm_T_19 & sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :367:{13,23}]
wire [13:0] _GEN_2 = {sigX_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:245:29, :367:44]
wire [13:0] _trialTerm_T_21; // @[DivSqrtRecFN_small.scala:367:44]
assign _trialTerm_T_21 = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44]
wire [13:0] _trialTerm2_newBit0_T_1; // @[DivSqrtRecFN_small.scala:373:64]
assign _trialTerm2_newBit0_T_1 = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44, :373:64]
wire [13:0] _io_rawOut_sig_T; // @[DivSqrtRecFN_small.scala:414:31]
assign _io_rawOut_sig_T = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44, :414:31]
wire [13:0] _trialTerm_T_22 = _trialTerm_T_20 ? _trialTerm_T_21 : 14'h0; // @[DivSqrtRecFN_small.scala:367:{12,23,44}]
wire [13:0] trialTerm = {1'h0, _trialTerm_T_18} | _trialTerm_T_22; // @[DivSqrtRecFN_small.scala:365:74, :366:74, :367:12]
wire [14:0] _trialRem_T = {1'h0, rem}; // @[DivSqrtRecFN_small.scala:358:11, :368:24]
wire [14:0] _trialRem_T_1 = {1'h0, trialTerm}; // @[DivSqrtRecFN_small.scala:366:74, :368:42]
wire [15:0] trialRem = {_trialRem_T[14], _trialRem_T} - {_trialRem_T_1[14], _trialRem_T_1}; // @[DivSqrtRecFN_small.scala:368:{24,29,42}]
wire [15:0] _nextRem_Z_T = trialRem; // @[DivSqrtRecFN_small.scala:368:29, :371:42]
wire newBit = $signed(trialRem) > -16'sh1; // @[DivSqrtRecFN_small.scala:368:29, :369:23]
wire [15:0] _nextRem_Z_T_1 = newBit ? _nextRem_Z_T : {2'h0, rem}; // @[DivSqrtRecFN_small.scala:300:35, :358:11, :369:23, :371:{24,42}]
wire [12:0] nextRem_Z = _nextRem_Z_T_1[12:0]; // @[DivSqrtRecFN_small.scala:371:{24,54}]
wire [12:0] _nextRem_Z_2_T_10 = nextRem_Z; // @[DivSqrtRecFN_small.scala:371:54, :388:12]
wire [13:0] rem2 = {nextRem_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:371:54, :372:25]
wire [13:0] _trialTerm2_newBit0_T_2 = {4'h0, _trialTerm2_newBit0_T} | _trialTerm2_newBit0_T_1; // @[DivSqrtRecFN_small.scala:373:{52,56,64}]
wire [11:0] _trialTerm2_newBit0_T_4 = {1'h1, fractB_Z}; // @[DivSqrtRecFN_small.scala:236:29, :373:78]
wire [13:0] trialTerm2_newBit0 = sqrtOp_Z ? _trialTerm2_newBit0_T_2 : {2'h0, _trialTerm2_newBit0_T_4}; // @[DivSqrtRecFN_small.scala:228:29, :300:35, :373:{33,56,78}]
wire [11:0] _trialTerm2_newBit1_T = {fractB_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:236:29, :374:73]
wire [11:0] _trialTerm2_newBit1_T_1 = sqrtOp_Z ? _trialTerm2_newBit1_T : 12'h0; // @[DivSqrtRecFN_small.scala:228:29, :374:{54,73}]
wire [13:0] trialTerm2_newBit1 = {trialTerm2_newBit0[13:12], trialTerm2_newBit0[11:0] | _trialTerm2_newBit1_T_1}; // @[DivSqrtRecFN_small.scala:373:33, :374:{49,54}]
wire [16:0] _GEN_3 = {trialRem, 1'h0}; // @[DivSqrtRecFN_small.scala:368:29, :377:22]
wire [16:0] _trialRem2_T; // @[DivSqrtRecFN_small.scala:377:22]
assign _trialRem2_T = _GEN_3; // @[DivSqrtRecFN_small.scala:377:22]
wire [16:0] _nextNotZeroRem_Z_2_T_1; // @[DivSqrtRecFN_small.scala:382:53]
assign _nextNotZeroRem_Z_2_T_1 = _GEN_3; // @[DivSqrtRecFN_small.scala:377:22, :382:53]
wire [14:0] _GEN_4 = {1'h0, trialTerm2_newBit1}; // @[DivSqrtRecFN_small.scala:374:49, :377:48]
wire [14:0] _trialRem2_T_1; // @[DivSqrtRecFN_small.scala:377:48]
assign _trialRem2_T_1 = _GEN_4; // @[DivSqrtRecFN_small.scala:377:48]
wire [14:0] _nextNotZeroRem_Z_2_T_2; // @[DivSqrtRecFN_small.scala:382:79]
assign _nextNotZeroRem_Z_2_T_2 = _GEN_4; // @[DivSqrtRecFN_small.scala:377:48, :382:79]
wire [17:0] _trialRem2_T_2 = {_trialRem2_T[16], _trialRem2_T} - {{3{_trialRem2_T_1[14]}}, _trialRem2_T_1}; // @[DivSqrtRecFN_small.scala:377:{22,27,48}]
wire [16:0] _trialRem2_T_3 = _trialRem2_T_2[16:0]; // @[DivSqrtRecFN_small.scala:377:27]
wire [16:0] _trialRem2_T_4 = _trialRem2_T_3; // @[DivSqrtRecFN_small.scala:377:27]
wire [14:0] _GEN_5 = {rem_Z, 2'h0}; // @[DivSqrtRecFN_small.scala:243:29, :300:35, :378:19]
wire [14:0] _trialRem2_T_5; // @[DivSqrtRecFN_small.scala:378:19]
assign _trialRem2_T_5 = _GEN_5; // @[DivSqrtRecFN_small.scala:378:19]
wire [14:0] _nextNotZeroRem_Z_2_T_10; // @[DivSqrtRecFN_small.scala:383:51]
assign _nextNotZeroRem_Z_2_T_10 = _GEN_5; // @[DivSqrtRecFN_small.scala:378:19, :383:51]
wire [13:0] _trialRem2_T_6 = _trialRem2_T_5[13:0]; // @[DivSqrtRecFN_small.scala:378:{19,23}]
wire [14:0] _trialRem2_T_7 = {1'h0, _trialRem2_T_6}; // @[DivSqrtRecFN_small.scala:378:{23,39}]
wire [14:0] _GEN_6 = {1'h0, trialTerm2_newBit0}; // @[DivSqrtRecFN_small.scala:373:33, :378:65]
wire [14:0] _trialRem2_T_8; // @[DivSqrtRecFN_small.scala:378:65]
assign _trialRem2_T_8 = _GEN_6; // @[DivSqrtRecFN_small.scala:378:65]
wire [14:0] _nextNotZeroRem_Z_2_T_13; // @[DivSqrtRecFN_small.scala:383:97]
assign _nextNotZeroRem_Z_2_T_13 = _GEN_6; // @[DivSqrtRecFN_small.scala:378:65, :383:97]
wire [15:0] _trialRem2_T_9 = {_trialRem2_T_7[14], _trialRem2_T_7} - {_trialRem2_T_8[14], _trialRem2_T_8}; // @[DivSqrtRecFN_small.scala:378:{39,44,65}]
wire [14:0] _trialRem2_T_10 = _trialRem2_T_9[14:0]; // @[DivSqrtRecFN_small.scala:378:44]
wire [14:0] _trialRem2_T_11 = _trialRem2_T_10; // @[DivSqrtRecFN_small.scala:378:44]
wire [16:0] trialRem2 = newBit ? _trialRem2_T_4 : {{2{_trialRem2_T_11[14]}}, _trialRem2_T_11}; // @[DivSqrtRecFN_small.scala:369:23, :376:12, :377:27, :378:44]
wire [16:0] _nextRem_Z_2_T_1 = trialRem2; // @[DivSqrtRecFN_small.scala:376:12, :386:51]
wire newBit2 = $signed(trialRem2) > -17'sh1; // @[DivSqrtRecFN_small.scala:376:12, :379:24]
wire _nextNotZeroRem_Z_T = inReady | newBit; // @[DivSqrtRecFN_small.scala:225:33, :369:23, :380:40]
wire _nextNotZeroRem_Z_T_1 = |trialRem; // @[DivSqrtRecFN_small.scala:368:29, :380:60]
wire nextNotZeroRem_Z = _nextNotZeroRem_Z_T ? _nextNotZeroRem_Z_T_1 : notZeroRem_Z; // @[DivSqrtRecFN_small.scala:244:29, :380:{31,40,60}]
wire _nextNotZeroRem_Z_2_T_22 = nextNotZeroRem_Z; // @[DivSqrtRecFN_small.scala:380:31, :384:38]
wire [17:0] _nextNotZeroRem_Z_2_T_3 = {_nextNotZeroRem_Z_2_T_1[16], _nextNotZeroRem_Z_2_T_1} - {{3{_nextNotZeroRem_Z_2_T_2[14]}}, _nextNotZeroRem_Z_2_T_2}; // @[DivSqrtRecFN_small.scala:382:{53,58,79}]
wire [16:0] _nextNotZeroRem_Z_2_T_4 = _nextNotZeroRem_Z_2_T_3[16:0]; // @[DivSqrtRecFN_small.scala:382:58]
wire [16:0] _nextNotZeroRem_Z_2_T_5 = _nextNotZeroRem_Z_2_T_4; // @[DivSqrtRecFN_small.scala:382:58]
wire _nextNotZeroRem_Z_2_T_6 = $signed(_nextNotZeroRem_Z_2_T_5) > 17'sh0; // @[DivSqrtRecFN_small.scala:382:{42,58}]
wire _nextNotZeroRem_Z_2_T_8 = ~newBit; // @[DivSqrtRecFN_small.scala:369:23, :383:27]
wire [13:0] _nextNotZeroRem_Z_2_T_11 = _nextNotZeroRem_Z_2_T_10[13:0]; // @[DivSqrtRecFN_small.scala:383:{51,55}]
wire [14:0] _nextNotZeroRem_Z_2_T_12 = {1'h0, _nextNotZeroRem_Z_2_T_11}; // @[DivSqrtRecFN_small.scala:383:{55,71}]
wire [15:0] _nextNotZeroRem_Z_2_T_14 = {_nextNotZeroRem_Z_2_T_12[14], _nextNotZeroRem_Z_2_T_12} - {_nextNotZeroRem_Z_2_T_13[14], _nextNotZeroRem_Z_2_T_13}; // @[DivSqrtRecFN_small.scala:383:{71,76,97}]
wire [14:0] _nextNotZeroRem_Z_2_T_15 = _nextNotZeroRem_Z_2_T_14[14:0]; // @[DivSqrtRecFN_small.scala:383:76]
wire [14:0] _nextNotZeroRem_Z_2_T_16 = _nextNotZeroRem_Z_2_T_15; // @[DivSqrtRecFN_small.scala:383:76]
wire _nextNotZeroRem_Z_2_T_17 = $signed(_nextNotZeroRem_Z_2_T_16) > 15'sh0; // @[DivSqrtRecFN_small.scala:383:{43,76}]
wire nextNotZeroRem_Z_2 = _nextNotZeroRem_Z_2_T_22; // @[DivSqrtRecFN_small.scala:383:103, :384:38]
wire [12:0] _nextRem_Z_2_T_2 = _nextRem_Z_2_T_1[12:0]; // @[DivSqrtRecFN_small.scala:386:{51,57}]
wire _nextRem_Z_2_T_4 = ~newBit2; // @[DivSqrtRecFN_small.scala:379:24, :387:31]
wire [12:0] _nextRem_Z_2_T_6 = rem2[12:0]; // @[DivSqrtRecFN_small.scala:372:25, :387:45]
wire [12:0] nextRem_Z_2 = _nextRem_Z_2_T_10; // @[DivSqrtRecFN_small.scala:387:83, :388:12]
wire _sigX_Z_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :394:28]
wire _sigX_Z_T_1 = inReady & _sigX_Z_T; // @[DivSqrtRecFN_small.scala:225:33, :394:{25,28}]
wire [12:0] _sigX_Z_T_2 = {newBit, 12'h0}; // @[DivSqrtRecFN_small.scala:369:23, :394:50]
wire [12:0] _sigX_Z_T_3 = _sigX_Z_T_1 ? _sigX_Z_T_2 : 13'h0; // @[DivSqrtRecFN_small.scala:394:{16,25,50}]
wire [11:0] _sigX_Z_T_5 = {_sigX_Z_T_4, 11'h0}; // @[DivSqrtRecFN_small.scala:395:{16,25}]
wire [12:0] _sigX_Z_T_6 = {_sigX_Z_T_3[12], _sigX_Z_T_3[11:0] | _sigX_Z_T_5}; // @[DivSqrtRecFN_small.scala:394:{16,74}, :395:16]
wire [10:0] _sigX_Z_T_8 = {newBit, 10'h0}; // @[DivSqrtRecFN_small.scala:369:23, :396:50]
wire [10:0] _sigX_Z_T_9 = _sigX_Z_T_7 ? _sigX_Z_T_8 : 11'h0; // @[DivSqrtRecFN_small.scala:396:{16,25,50}]
wire [12:0] _sigX_Z_T_10 = {_sigX_Z_T_6[12:11], _sigX_Z_T_6[10:0] | _sigX_Z_T_9}; // @[DivSqrtRecFN_small.scala:394:74, :395:74, :396:16]
wire _sigX_Z_T_11 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :397:17]
wire [12:0] _sigX_Z_T_12 = _sigX_Z_T_11 ? sigX_Z : 13'h0; // @[DivSqrtRecFN_small.scala:245:29, :397:{16,17}]
wire [12:0] _sigX_Z_T_13 = _sigX_Z_T_10 | _sigX_Z_T_12; // @[DivSqrtRecFN_small.scala:395:74, :396:74, :397:16]
wire _sigX_Z_T_14 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :398:17]
wire _sigX_Z_T_15 = _sigX_Z_T_14 & newBit; // @[DivSqrtRecFN_small.scala:369:23, :398:{17,27}]
wire [13:0] _sigX_Z_T_16 = _sigX_Z_T_15 ? bitMask : 14'h0; // @[DivSqrtRecFN_small.scala:360:34, :398:{16,27}]
wire [13:0] _sigX_Z_T_17 = {1'h0, _sigX_Z_T_13} | _sigX_Z_T_16; // @[DivSqrtRecFN_small.scala:396:74, :397:74, :398:16]
wire [13:0] _sigX_Z_T_21 = _sigX_Z_T_17; // @[DivSqrtRecFN_small.scala:397:74, :398:74]
wire [12:0] _sigX_Z_T_19 = bitMask[13:1]; // @[DivSqrtRecFN_small.scala:360:34, :399:51]
wire _io_rawOutValid_div_T = ~sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :366:26, :404:43]
assign _io_rawOutValid_div_T_1 = rawOutValid & _io_rawOutValid_div_T; // @[DivSqrtRecFN_small.scala:226:33, :404:{40,43}]
assign io_rawOutValid_div_0 = _io_rawOutValid_div_T_1; // @[DivSqrtRecFN_small.scala:199:5, :404:40]
assign _io_rawOutValid_sqrt_T = rawOutValid & sqrtOp_Z; // @[DivSqrtRecFN_small.scala:226:33, :228:29, :405:40]
assign io_rawOutValid_sqrt_0 = _io_rawOutValid_sqrt_T; // @[DivSqrtRecFN_small.scala:199:5, :405:40]
assign _io_invalidExc_T = majorExc_Z & isNaN_Z; // @[DivSqrtRecFN_small.scala:229:29, :231:29, :407:36]
assign io_invalidExc_0 = _io_invalidExc_T; // @[DivSqrtRecFN_small.scala:199:5, :407:36]
wire _io_infiniteExc_T = ~isNaN_Z; // @[DivSqrtRecFN_small.scala:231:29, :408:39]
assign _io_infiniteExc_T_1 = majorExc_Z & _io_infiniteExc_T; // @[DivSqrtRecFN_small.scala:229:29, :408:{36,39}]
assign io_infiniteExc_0 = _io_infiniteExc_T_1; // @[DivSqrtRecFN_small.scala:199:5, :408:36]
assign _io_rawOut_sig_T_1 = {_io_rawOut_sig_T[13:1], _io_rawOut_sig_T[0] | notZeroRem_Z}; // @[DivSqrtRecFN_small.scala:244:29, :414:{31,35}]
assign io_rawOut_sig_0 = _io_rawOut_sig_T_1; // @[DivSqrtRecFN_small.scala:199:5, :414:35]
always @(posedge clock) begin // @[DivSqrtRecFN_small.scala:199:5]
if (reset) begin // @[DivSqrtRecFN_small.scala:199:5]
cycleNum <= 4'h0; // @[DivSqrtRecFN_small.scala:224:33]
inReady <= 1'h1; // @[DivSqrtRecFN_small.scala:225:33]
rawOutValid <= 1'h0; // @[DivSqrtRecFN_small.scala:226:33]
end
else if (~idle | entering) begin // @[DivSqrtRecFN_small.scala:296:25, :297:28, :303:{11,18}]
cycleNum <= _cycleNum_T_17; // @[DivSqrtRecFN_small.scala:224:33, :313:95]
inReady <= _inReady_T_24; // @[DivSqrtRecFN_small.scala:225:33, :317:46]
rawOutValid <= _rawOutValid_T_24; // @[DivSqrtRecFN_small.scala:226:33, :318:51]
end
if (entering) begin // @[DivSqrtRecFN_small.scala:297:28]
sqrtOp_Z <= io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :228:29]
majorExc_Z <= majorExc_S; // @[DivSqrtRecFN_small.scala:229:29, :258:12]
isNaN_Z <= isNaN_S; // @[DivSqrtRecFN_small.scala:231:29, :265:12]
isInf_Z <= isInf_S; // @[DivSqrtRecFN_small.scala:232:29, :269:23]
isZero_Z <= isZero_S; // @[DivSqrtRecFN_small.scala:233:29, :270:23]
sign_Z <= sign_S; // @[DivSqrtRecFN_small.scala:234:29, :271:30]
sExp_Z <= _sExp_Z_T_2; // @[DivSqrtRecFN_small.scala:235:29, :334:16]
roundingMode_Z <= io_roundingMode_0; // @[DivSqrtRecFN_small.scala:199:5, :237:29]
end
if (entering | ~inReady & sqrtOp_Z) // @[DivSqrtRecFN_small.scala:225:33, :228:29, :297:28, :340:{20,23,33}]
fractB_Z <= _fractB_Z_T_26; // @[DivSqrtRecFN_small.scala:236:29, :345:100]
if (entering | ~inReady) begin // @[DivSqrtRecFN_small.scala:225:33, :297:28, :340:23, :390:20]
rem_Z <= nextRem_Z_2; // @[DivSqrtRecFN_small.scala:243:29, :387:83]
notZeroRem_Z <= nextNotZeroRem_Z_2; // @[DivSqrtRecFN_small.scala:244:29, :383:103]
sigX_Z <= _sigX_Z_T_21[12:0]; // @[DivSqrtRecFN_small.scala:245:29, :393:16, :398:74]
end
always @(posedge)
assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:199:5]
assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:199:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_107 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_195
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_107( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_195 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget32_11 :
input clock : Clock
input reset : Reset
output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
inst monitor of TLMonitor_69
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in
wire repeat : UInt<1>
inst repeated_repeater of Repeater_TLBundleA_a32d256s5k3z4u_7
connect repeated_repeater.clock, clock
connect repeated_repeater.reset, reset
connect repeated_repeater.io.repeat, repeat
connect repeated_repeater.io.enq, anonIn.a
wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}
connect cated.bits, repeated_repeater.io.deq.bits
connect cated.valid, repeated_repeater.io.deq.valid
connect repeated_repeater.io.deq.ready, cated.ready
node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 255, 64)
node _cated_bits_data_T_1 = bits(anonIn.a.bits.data, 63, 0)
node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1)
connect cated.bits.data, _cated_bits_data_T_2
node _repeat_hasData_opdata_T = bits(cated.bits.opcode, 2, 2)
node repeat_hasData = eq(_repeat_hasData_opdata_T, UInt<1>(0h0))
node _repeat_limit_T = dshl(UInt<5>(0h1f), cated.bits.size)
node _repeat_limit_T_1 = bits(_repeat_limit_T, 4, 0)
node _repeat_limit_T_2 = not(_repeat_limit_T_1)
node repeat_limit = shr(_repeat_limit_T_2, 3)
regreset repeat_count : UInt<2>, clock, reset, UInt<2>(0h0)
node repeat_first = eq(repeat_count, UInt<1>(0h0))
node _repeat_last_T = eq(repeat_count, repeat_limit)
node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0))
node repeat_last = or(_repeat_last_T, _repeat_last_T_1)
node _repeat_T = and(anonOut.a.ready, anonOut.a.valid)
when _repeat_T :
node _repeat_count_T = add(repeat_count, UInt<1>(0h1))
node _repeat_count_T_1 = tail(_repeat_count_T, 1)
connect repeat_count, _repeat_count_T_1
when repeat_last :
connect repeat_count, UInt<1>(0h0)
node repeat_sel = bits(cated.bits.address, 4, 3)
node repeat_index = or(repeat_sel, repeat_count)
connect anonOut.a.bits, cated.bits
connect anonOut.a.valid, cated.valid
connect cated.ready, anonOut.a.ready
node _repeat_anonOut_a_bits_data_mux_T = bits(cated.bits.data, 63, 0)
node _repeat_anonOut_a_bits_data_mux_T_1 = bits(cated.bits.data, 127, 64)
node _repeat_anonOut_a_bits_data_mux_T_2 = bits(cated.bits.data, 191, 128)
node _repeat_anonOut_a_bits_data_mux_T_3 = bits(cated.bits.data, 255, 192)
wire repeat_anonOut_a_bits_data_mux : UInt<64>[4]
connect repeat_anonOut_a_bits_data_mux[0], _repeat_anonOut_a_bits_data_mux_T
connect repeat_anonOut_a_bits_data_mux[1], _repeat_anonOut_a_bits_data_mux_T_1
connect repeat_anonOut_a_bits_data_mux[2], _repeat_anonOut_a_bits_data_mux_T_2
connect repeat_anonOut_a_bits_data_mux[3], _repeat_anonOut_a_bits_data_mux_T_3
connect anonOut.a.bits.data, repeat_anonOut_a_bits_data_mux[repeat_index]
node _repeat_anonOut_a_bits_mask_mux_T = bits(cated.bits.mask, 7, 0)
node _repeat_anonOut_a_bits_mask_mux_T_1 = bits(cated.bits.mask, 15, 8)
node _repeat_anonOut_a_bits_mask_mux_T_2 = bits(cated.bits.mask, 23, 16)
node _repeat_anonOut_a_bits_mask_mux_T_3 = bits(cated.bits.mask, 31, 24)
wire repeat_anonOut_a_bits_mask_mux : UInt<8>[4]
connect repeat_anonOut_a_bits_mask_mux[0], _repeat_anonOut_a_bits_mask_mux_T
connect repeat_anonOut_a_bits_mask_mux[1], _repeat_anonOut_a_bits_mask_mux_T_1
connect repeat_anonOut_a_bits_mask_mux[2], _repeat_anonOut_a_bits_mask_mux_T_2
connect repeat_anonOut_a_bits_mask_mux[3], _repeat_anonOut_a_bits_mask_mux_T_3
connect anonOut.a.bits.mask, repeat_anonOut_a_bits_mask_mux[repeat_index]
node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0))
connect repeat, _repeat_T_1
node hasData = bits(anonOut.d.bits.opcode, 0, 0)
node _limit_T = dshl(UInt<5>(0h1f), anonOut.d.bits.size)
node _limit_T_1 = bits(_limit_T, 4, 0)
node _limit_T_2 = not(_limit_T_1)
node limit = shr(_limit_T_2, 3)
regreset count : UInt<2>, clock, reset, UInt<2>(0h0)
node first = eq(count, UInt<1>(0h0))
node _last_T = eq(count, limit)
node _last_T_1 = eq(hasData, UInt<1>(0h0))
node last = or(_last_T, _last_T_1)
node _enable_T = xor(count, UInt<1>(0h0))
node _enable_T_1 = and(_enable_T, limit)
node _enable_T_2 = orr(_enable_T_1)
node enable_0 = eq(_enable_T_2, UInt<1>(0h0))
node _enable_T_3 = xor(count, UInt<1>(0h1))
node _enable_T_4 = and(_enable_T_3, limit)
node _enable_T_5 = orr(_enable_T_4)
node enable_1 = eq(_enable_T_5, UInt<1>(0h0))
node _enable_T_6 = xor(count, UInt<2>(0h2))
node _enable_T_7 = and(_enable_T_6, limit)
node _enable_T_8 = orr(_enable_T_7)
node enable_2 = eq(_enable_T_8, UInt<1>(0h0))
node _enable_T_9 = xor(count, UInt<2>(0h3))
node _enable_T_10 = and(_enable_T_9, limit)
node _enable_T_11 = orr(_enable_T_10)
node enable_3 = eq(_enable_T_11, UInt<1>(0h0))
regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0)
node corrupt_out = or(anonOut.d.bits.corrupt, corrupt_reg)
node _T = and(anonOut.d.ready, anonOut.d.valid)
when _T :
node _count_T = add(count, UInt<1>(0h1))
node _count_T_1 = tail(_count_T, 1)
connect count, _count_T_1
connect corrupt_reg, corrupt_out
when last :
connect count, UInt<1>(0h0)
connect corrupt_reg, UInt<1>(0h0)
node _anonOut_d_ready_T = eq(last, UInt<1>(0h0))
node _anonOut_d_ready_T_1 = or(anonIn.d.ready, _anonOut_d_ready_T)
connect anonOut.d.ready, _anonOut_d_ready_T_1
node _anonIn_d_valid_T = and(anonOut.d.valid, last)
connect anonIn.d.valid, _anonIn_d_valid_T
connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt
connect anonIn.d.bits.data, anonOut.d.bits.data
connect anonIn.d.bits.denied, anonOut.d.bits.denied
connect anonIn.d.bits.sink, anonOut.d.bits.sink
connect anonIn.d.bits.source, anonOut.d.bits.source
connect anonIn.d.bits.size, anonOut.d.bits.size
connect anonIn.d.bits.param, anonOut.d.bits.param
connect anonIn.d.bits.opcode, anonOut.d.bits.opcode
regreset anonIn_d_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0)
node _anonIn_d_bits_data_masked_enable_T = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_0 = or(enable_0, _anonIn_d_bits_data_masked_enable_T)
node _anonIn_d_bits_data_masked_enable_T_1 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_1 = or(enable_1, _anonIn_d_bits_data_masked_enable_T_1)
node _anonIn_d_bits_data_masked_enable_T_2 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_2 = or(enable_2, _anonIn_d_bits_data_masked_enable_T_2)
node _anonIn_d_bits_data_masked_enable_T_3 = eq(anonIn_d_bits_data_rdata_written_once, UInt<1>(0h0))
node anonIn_d_bits_data_masked_enable_3 = or(enable_3, _anonIn_d_bits_data_masked_enable_T_3)
wire anonIn_d_bits_data_odata_0 : UInt
connect anonIn_d_bits_data_odata_0, anonOut.d.bits.data
wire anonIn_d_bits_data_odata_1 : UInt
connect anonIn_d_bits_data_odata_1, anonOut.d.bits.data
wire anonIn_d_bits_data_odata_2 : UInt
connect anonIn_d_bits_data_odata_2, anonOut.d.bits.data
wire anonIn_d_bits_data_odata_3 : UInt
connect anonIn_d_bits_data_odata_3, anonOut.d.bits.data
reg anonIn_d_bits_data_rdata : UInt<64>[3], clock
node anonIn_d_bits_data_mdata_0 = mux(anonIn_d_bits_data_masked_enable_0, anonIn_d_bits_data_odata_0, anonIn_d_bits_data_rdata[0])
node anonIn_d_bits_data_mdata_1 = mux(anonIn_d_bits_data_masked_enable_1, anonIn_d_bits_data_odata_1, anonIn_d_bits_data_rdata[1])
node anonIn_d_bits_data_mdata_2 = mux(anonIn_d_bits_data_masked_enable_2, anonIn_d_bits_data_odata_2, anonIn_d_bits_data_rdata[2])
node anonIn_d_bits_data_mdata_3 = mux(anonIn_d_bits_data_masked_enable_3, anonIn_d_bits_data_odata_3, anonOut.d.bits.data)
node _anonIn_d_bits_data_T = and(anonOut.d.ready, anonOut.d.valid)
node _anonIn_d_bits_data_T_1 = eq(last, UInt<1>(0h0))
node _anonIn_d_bits_data_T_2 = and(_anonIn_d_bits_data_T, _anonIn_d_bits_data_T_1)
when _anonIn_d_bits_data_T_2 :
connect anonIn_d_bits_data_rdata_written_once, UInt<1>(0h1)
connect anonIn_d_bits_data_rdata[0], anonIn_d_bits_data_mdata_0
connect anonIn_d_bits_data_rdata[1], anonIn_d_bits_data_mdata_1
connect anonIn_d_bits_data_rdata[2], anonIn_d_bits_data_mdata_2
node anonIn_d_bits_data_lo = cat(anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0)
node anonIn_d_bits_data_hi = cat(anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2)
node _anonIn_d_bits_data_T_3 = cat(anonIn_d_bits_data_hi, anonIn_d_bits_data_lo)
connect anonIn.d.bits.data, _anonIn_d_bits_data_T_3
connect anonIn.d.bits.corrupt, corrupt_out
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<256>(0h0)
connect _WIRE.bits.mask, UInt<32>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<32>, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<256>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<256>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_10.bits.sink, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLWidthWidget32_11( // @[WidthWidget.scala:27:9]
input clock, // @[WidthWidget.scala:27:9]
input reset, // @[WidthWidget.scala:27:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [255:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [255:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [255:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [255:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [31:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [255:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [255:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [255:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [4:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9]
wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [255:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
wire corrupt_out; // @[WidthWidget.scala:47:36]
assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25]
wire cated_valid; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
wire [4:0] cated_bits_source; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] cated_bits_address; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
wire cated_bits_corrupt; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_2 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_3 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire _repeat_T_1; // @[WidthWidget.scala:148:7]
wire repeat_0; // @[WidthWidget.scala:159:26]
assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25]
wire [255:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39]
assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25]
wire [31:0] cated_bits_mask; // @[WidthWidget.scala:161:25]
wire [255:0] cated_bits_data; // @[WidthWidget.scala:161:25]
wire [191:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[255:64]; // @[Repeater.scala:36:26]
wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31]
assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31]
assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39]
wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25]
wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [19:0] _repeat_limit_T = 20'h1F << cated_bits_size; // @[package.scala:243:71]
wire [4:0] _repeat_limit_T_1 = _repeat_limit_T[4:0]; // @[package.scala:243:{71,76}]
wire [4:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}]
wire [1:0] repeat_limit = _repeat_limit_T_2[4:3]; // @[package.scala:243:46]
reg [1:0] repeat_count; // @[WidthWidget.scala:105:26]
wire repeat_first = repeat_count == 2'h0; // @[WidthWidget.scala:105:26, :106:25]
wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25]
wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38]
wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}]
wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35]
wire [2:0] _repeat_count_T = {1'h0, repeat_count} + 3'h1; // @[WidthWidget.scala:105:26, :110:24]
wire [1:0] _repeat_count_T_1 = _repeat_count_T[1:0]; // @[WidthWidget.scala:110:24]
wire [1:0] repeat_sel = cated_bits_address[4:3]; // @[WidthWidget.scala:116:39, :161:25]
wire [1:0] repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_2 = cated_bits_data[191:128]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_2 = _repeat_anonOut_a_bits_data_mux_T_2; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_3 = cated_bits_data[255:192]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_3 = _repeat_anonOut_a_bits_data_mux_T_3; // @[WidthWidget.scala:128:{43,55}]
wire [3:0][63:0] _GEN = {{repeat_anonOut_a_bits_data_mux_3}, {repeat_anonOut_a_bits_data_mux_2}, {repeat_anonOut_a_bits_data_mux_1}, {repeat_anonOut_a_bits_data_mux_0}}; // @[WidthWidget.scala:128:43, :137:30]
assign anonOut_a_bits_data = _GEN[repeat_index]; // @[WidthWidget.scala:126:24, :137:30]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_2 = cated_bits_mask[23:16]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_2 = _repeat_anonOut_a_bits_mask_mux_T_2; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_3 = cated_bits_mask[31:24]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_3 = _repeat_anonOut_a_bits_mask_mux_T_3; // @[WidthWidget.scala:128:{43,55}]
wire [3:0][7:0] _GEN_0 = {{repeat_anonOut_a_bits_mask_mux_3}, {repeat_anonOut_a_bits_mask_mux_2}, {repeat_anonOut_a_bits_mask_mux_1}, {repeat_anonOut_a_bits_mask_mux_0}}; // @[WidthWidget.scala:128:43, :140:53]
assign anonOut_a_bits_mask = _GEN_0[repeat_index]; // @[WidthWidget.scala:126:24, :140:53]
assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7]
assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26]
wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [19:0] _limit_T = 20'h1F << anonOut_d_bits_size; // @[package.scala:243:71]
wire [4:0] _limit_T_1 = _limit_T[4:0]; // @[package.scala:243:{71,76}]
wire [4:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}]
wire [1:0] limit = _limit_T_2[4:3]; // @[package.scala:243:46]
reg [1:0] count; // @[WidthWidget.scala:40:27]
wire [1:0] _enable_T = count; // @[WidthWidget.scala:40:27, :43:56]
wire first = count == 2'h0; // @[WidthWidget.scala:40:27, :41:26]
wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26]
wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39]
wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}]
wire [1:0] _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_2 = |_enable_T_1; // @[WidthWidget.scala:43:{63,72}]
wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_3 = {count[1], ~(count[0])}; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_5 = |_enable_T_4; // @[WidthWidget.scala:43:{63,72}]
wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_6 = count ^ 2'h2; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_8 = |_enable_T_7; // @[WidthWidget.scala:43:{63,72}]
wire enable_2 = ~_enable_T_8; // @[WidthWidget.scala:43:{47,72}]
wire [1:0] _enable_T_9 = ~count; // @[WidthWidget.scala:40:27, :43:56]
wire [1:0] _enable_T_10 = _enable_T_9 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_11 = |_enable_T_10; // @[WidthWidget.scala:43:{63,72}]
wire enable_3 = ~_enable_T_11; // @[WidthWidget.scala:43:{47,72}]
reg corrupt_reg; // @[WidthWidget.scala:45:32]
assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36]
assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36]
wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [2:0] _count_T = {1'h0, count} + 3'h1; // @[WidthWidget.scala:40:27, :50:24]
wire [1:0] _count_T_1 = _count_T[1:0]; // @[WidthWidget.scala:50:24]
wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32]
assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}]
assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29]
assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41]
wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_2 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_2 = enable_2 | _anonIn_d_bits_data_masked_enable_T_2; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_3 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_3 = enable_3 | _anonIn_d_bits_data_masked_enable_T_3; // @[WidthWidget.scala:43:47, :63:{42,45}]
reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24]
reg [63:0] anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:66:24]
reg [63:0] anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:66:24]
wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonIn_d_bits_data_rdata_1; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_2 = anonIn_d_bits_data_masked_enable_2 ? anonIn_d_bits_data_odata_2 : anonIn_d_bits_data_rdata_2; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_3 = anonIn_d_bits_data_masked_enable_3 ? anonIn_d_bits_data_odata_3 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88]
wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32]
wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35]
wire [127:0] anonIn_d_bits_data_lo = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12]
wire [127:0] anonIn_d_bits_data_hi = {anonIn_d_bits_data_mdata_3, anonIn_d_bits_data_mdata_2}; // @[WidthWidget.scala:68:88, :73:12]
assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_hi, anonIn_d_bits_data_lo}; // @[WidthWidget.scala:73:12]
assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
always @(posedge clock) begin // @[WidthWidget.scala:27:9]
if (reset) begin // @[WidthWidget.scala:27:9]
repeat_count <= 2'h0; // @[WidthWidget.scala:105:26]
count <= 2'h0; // @[WidthWidget.scala:40:27]
corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32]
anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41]
end
else begin // @[WidthWidget.scala:27:9]
if (_repeat_T) // @[Decoupled.scala:51:35]
repeat_count <= repeat_last ? 2'h0 : _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}]
if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35]
count <= last ? 2'h0 : _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17]
corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :51:21, :52:21, :54:23]
end
anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
end
if (_anonIn_d_bits_data_T_2) begin // @[WidthWidget.scala:69:23]
anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88]
anonIn_d_bits_data_rdata_1 <= anonIn_d_bits_data_mdata_1; // @[WidthWidget.scala:66:24, :68:88]
anonIn_d_bits_data_rdata_2 <= anonIn_d_bits_data_mdata_2; // @[WidthWidget.scala:66:24, :68:88]
end
always @(posedge)
TLMonitor_69 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Repeater_TLBundleA_a32d256s5k3z4u_7 repeated_repeater ( // @[Repeater.scala:36:26]
.clock (clock),
.reset (reset),
.io_repeat (repeat_0), // @[WidthWidget.scala:159:26]
.io_enq_ready (anonIn_a_ready),
.io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25]
.io_deq_valid (cated_valid),
.io_deq_bits_opcode (cated_bits_opcode),
.io_deq_bits_param (cated_bits_param),
.io_deq_bits_size (cated_bits_size),
.io_deq_bits_source (cated_bits_source),
.io_deq_bits_address (cated_bits_address),
.io_deq_bits_mask (cated_bits_mask),
.io_deq_bits_data (_repeated_repeater_io_deq_bits_data),
.io_deq_bits_corrupt (cated_bits_corrupt)
); // @[Repeater.scala:36:26]
assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_164 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_164( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_78 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}}}, flip vcalloc_resp : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}}, flip out_credit_available : { `1` : UInt<1>[1], `0` : UInt<1>[2]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], debug : { va_stall : UInt<1>, sa_stall : UInt<1>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}}
inst input_buffer of InputBuffer_78
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter2_RouteComputerReq_32
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<2>}[2], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
connect route_arbiter.io.in[0].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[0].bits.flow.egress_node_id
invalidate route_arbiter.io.in[0].bits.flow.egress_node
invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[0].bits.flow.ingress_node
invalidate route_arbiter.io.in[0].bits.flow.vnet_id
invalidate route_arbiter.io.in[0].bits.src_virt_id
node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1))
connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T
connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id
connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node
connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id
connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node
connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id
connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1)
node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_10 :
connect states[1].g, UInt<3>(0h2)
node _T_11 = and(io.router_req.ready, io.router_req.valid)
when _T_11 :
node _T_12 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
node _T_15 = eq(_T_12, UInt<1>(0h0))
when _T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_12, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_16 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_16 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _T_17 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_17 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
regreset mask : UInt<2>, clock, reset, UInt<2>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}}[2]
wire vcalloc_vals : UInt<1>[2]
node _vcalloc_filter_T = cat(vcalloc_vals[1], vcalloc_vals[0])
node _vcalloc_filter_T_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = mux(_vcalloc_filter_T_8, UInt<4>(0h8), UInt<4>(0h0))
node _vcalloc_filter_T_10 = mux(_vcalloc_filter_T_7, UInt<4>(0h4), _vcalloc_filter_T_9)
node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_6, UInt<4>(0h2), _vcalloc_filter_T_10)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<4>(0h1), _vcalloc_filter_T_11)
node _vcalloc_sel_T = bits(vcalloc_filter, 1, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 2)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_18 = and(io.router_req.ready, io.router_req.valid)
when _T_18 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_19 = or(vcalloc_vals[0], vcalloc_vals[1])
when _T_19 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = bits(vcalloc_sel, 0, 0)
node _mask_T_6 = bits(vcalloc_sel, 1, 1)
node _mask_T_7 = mux(_mask_T_5, _mask_T_3, UInt<1>(0h0))
node _mask_T_8 = mux(_mask_T_6, _mask_T_4, UInt<1>(0h0))
node _mask_T_9 = or(_mask_T_7, _mask_T_8)
wire _mask_WIRE : UInt<2>
connect _mask_WIRE, _mask_T_9
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `1` : UInt<1>[1], `0` : UInt<1>[2]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[2]
node _io_vcalloc_req_bits_T_2 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_4 = or(_io_vcalloc_req_bits_T_2, _io_vcalloc_req_bits_T_3)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_4
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_7
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>[1]
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_10
connect _io_vcalloc_req_bits_WIRE_5[0], _io_vcalloc_req_bits_WIRE_6
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_5
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_12)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_13
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_7
wire _io_vcalloc_req_bits_WIRE_8 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_16
connect _io_vcalloc_req_bits_WIRE_8.egress_node_id, _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_18)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_19
connect _io_vcalloc_req_bits_WIRE_8.egress_node, _io_vcalloc_req_bits_WIRE_10
node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_21)
wire _io_vcalloc_req_bits_WIRE_11 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_8.ingress_node_id, _io_vcalloc_req_bits_WIRE_11
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_25
connect _io_vcalloc_req_bits_WIRE_8.ingress_node, _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_27)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_28
connect _io_vcalloc_req_bits_WIRE_8.vnet_id, _io_vcalloc_req_bits_WIRE_13
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_8
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
connect vcalloc_vals[0], UInt<1>(0h0)
invalidate vcalloc_reqs[0].vc_sel.`0`[0]
invalidate vcalloc_reqs[0].vc_sel.`0`[1]
invalidate vcalloc_reqs[0].vc_sel.`1`[0]
invalidate vcalloc_reqs[0].in_vc
invalidate vcalloc_reqs[0].flow.egress_node_id
invalidate vcalloc_reqs[0].flow.egress_node
invalidate vcalloc_reqs[0].flow.ingress_node_id
invalidate vcalloc_reqs[0].flow.ingress_node
invalidate vcalloc_reqs[0].flow.vnet_id
node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2))
node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1)
connect vcalloc_vals[1], _vcalloc_vals_1_T_2
connect vcalloc_reqs[1].in_vc, UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1`
connect vcalloc_reqs[1].flow, states[1].flow
node _T_20 = bits(vcalloc_sel, 1, 1)
node _T_21 = and(vcalloc_vals[1], _T_20)
node _T_22 = and(_T_21, io.vcalloc_req.ready)
when _T_22 :
connect states[1].g, UInt<3>(0h3)
node _T_23 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_23 :
connect vcalloc_vals[1], UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = sub(_io_debug_va_stall_T_1, io.vcalloc_req.ready)
node _io_debug_va_stall_T_3 = tail(_io_debug_va_stall_T_2, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_3
node _T_24 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_24 :
node _T_25 = bits(vcalloc_sel, 0, 0)
when _T_25 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].g, UInt<3>(0h3)
node _T_26 = bits(vcalloc_sel, 1, 1)
when _T_26 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].g, UInt<3>(0h3)
inst salloc_arb of SwitchArbiter_195
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
connect salloc_arb.io.in[0].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[0].bits.tail
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0]
node _credit_available_T = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0])
node _credit_available_T_1 = cat(states[1].vc_sel.`1`[0], _credit_available_T)
node _credit_available_T_2 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node _credit_available_T_3 = cat(io.out_credit_available.`1`[0], _credit_available_T_2)
node _credit_available_T_4 = and(_credit_available_T_1, _credit_available_T_3)
node credit_available = neq(_credit_available_T_4, UInt<1>(0h0))
node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3))
node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available)
node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid)
connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2
connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0]
connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail
node _T_27 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid)
node _T_28 = and(_T_27, input_buffer.io.deq[1].bits.tail)
when _T_28 :
connect states[1].g, UInt<3>(0h0)
connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_5 = bits(_io_debug_sa_stall_T_4, 1, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_5
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
wire salloc_outs : { valid : UInt<1>, vid : UInt<1>, out_vid : UInt<1>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1]
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_5 = or(_io_in_vc_free_T_3, _io_in_vc_free_T_4)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_5
node _io_in_vc_free_T_6 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_6, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_7
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node _salloc_outs_0_vid_T = bits(salloc_arb.io.chosen_oh[0], 1, 1)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
wire vc_sel : { `1` : UInt<1>[1], `0` : UInt<1>[2]}
wire _vc_sel_WIRE : UInt<1>[2]
node _vc_sel_T_2 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_3 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_4 = or(_vc_sel_T_2, _vc_sel_T_3)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_4
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_7 = or(_vc_sel_T_5, _vc_sel_T_6)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_7
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_3 : UInt<1>[1]
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_10 = or(_vc_sel_T_8, _vc_sel_T_9)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_10
connect _vc_sel_WIRE_3[0], _vc_sel_WIRE_4
connect vc_sel.`1`, _vc_sel_WIRE_3
node channel_oh_0 = or(vc_sel.`0`[0], vc_sel.`0`[1])
node _virt_channel_T = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node _virt_channel_T_1 = bits(_virt_channel_T, 1, 1)
node _virt_channel_T_2 = mux(channel_oh_0, _virt_channel_T_1, UInt<1>(0h0))
node _virt_channel_T_3 = mux(vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_4 = or(_virt_channel_T_2, _virt_channel_T_3)
wire virt_channel : UInt<1>
connect virt_channel, _virt_channel_T_4
node _T_29 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_29 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_4 = or(_salloc_outs_0_flit_payload_T_2, _salloc_outs_0_flit_payload_T_3)
wire _salloc_outs_0_flit_payload_WIRE : UInt<37>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_4
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_4 = or(_salloc_outs_0_flit_head_T_2, _salloc_outs_0_flit_head_T_3)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_4
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_4 = or(_salloc_outs_0_flit_tail_T_2, _salloc_outs_0_flit_tail_T_3)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_4
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_2 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_4 = or(_salloc_outs_0_flit_flow_T_2, _salloc_outs_0_flit_flow_T_3)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_4
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_7
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_10
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_12)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_13
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<1>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_16
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
invalidate states[0].fifo_deps
invalidate states[0].flow.egress_node_id
invalidate states[0].flow.egress_node
invalidate states[0].flow.ingress_node_id
invalidate states[0].flow.ingress_node
invalidate states[0].flow.vnet_id
invalidate states[0].vc_sel.`0`[0]
invalidate states[0].vc_sel.`0`[1]
invalidate states[0].vc_sel.`1`[0]
invalidate states[0].g
connect states[1].vc_sel.`0`[0], UInt<1>(0h0)
connect states[1].vc_sel.`0`[1], UInt<1>(0h0)
node _T_30 = asUInt(reset)
when _T_30 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0) | module InputUnit_78( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_0, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output io_debug_va_stall, // @[InputUnit.scala:170:14]
output io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [1:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [1:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire _GEN; // @[MixedVec.scala:116:9]
wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [1:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_0; // @[InputUnit.scala:192:19]
reg states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire _GEN_1 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_22 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_22( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_33 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
inst route_buffer of Queue2_Flit_66
connect route_buffer.clock, clock
connect route_buffer.reset, reset
inst route_q of Queue2_RouteComputerResp_33
connect route_q.clock, clock
connect route_q.reset, reset
node _T = eq(UInt<5>(0h17), io.in.bits.egress_id)
node _T_1 = eq(UInt<5>(0h1a), io.in.bits.egress_id)
node _T_2 = eq(UInt<5>(0h1d), io.in.bits.egress_id)
node _T_3 = eq(UInt<6>(0h20), io.in.bits.egress_id)
node _T_4 = or(_T, _T_1)
node _T_5 = or(_T_4, _T_2)
node _T_6 = or(_T_5, _T_3)
node _T_7 = eq(_T_6, UInt<1>(0h0))
node _T_8 = and(io.in.valid, _T_7)
node _T_9 = eq(_T_8, UInt<1>(0h0))
node _T_10 = asUInt(reset)
node _T_11 = eq(_T_10, UInt<1>(0h0))
when _T_11 :
node _T_12 = eq(_T_9, UInt<1>(0h0))
when _T_12 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf
assert(clock, _T_9, UInt<1>(0h1), "") : assert
connect route_buffer.io.enq.bits.head, io.in.bits.head
connect route_buffer.io.enq.bits.tail, io.in.bits.tail
connect route_buffer.io.enq.bits.flow.ingress_node, UInt<4>(0hd)
connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<2>(0h2)
connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h0)
node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h17), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h1a), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h1d), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<6>(0h20), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h5), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0h9), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0ha), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5)
node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6)
node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7)
wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4>
connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10
connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE
node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h17), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h1a), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h1d), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<6>(0h20), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<2>(0h2), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<2>(0h2), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<2>(0h2), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<2>(0h2), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7)
wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<2>
connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10
connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE
connect route_buffer.io.enq.bits.payload, io.in.bits.payload
invalidate route_buffer.io.enq.bits.virt_channel_id
connect io.router_req.bits.src_virt_id, UInt<1>(0h0)
connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id
connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node
connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id
connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node
connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id
node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<4>(0hd))
node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0))
node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T)
node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest)
node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2)
connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3
node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready)
node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head)
node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0))
node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2)
connect io.router_req.valid, _io_router_req_valid_T_3
node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T)
node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest)
node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2)
connect io.in.ready, _io_in_ready_T_3
node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid)
connect route_q.io.enq.valid, _route_q_io_enq_valid_T
connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0]
connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1]
connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2]
connect route_q.io.enq.bits.vc_sel.`0`[3], io.router_resp.vc_sel.`0`[3]
connect route_q.io.enq.bits.vc_sel.`0`[4], io.router_resp.vc_sel.`0`[4]
connect route_q.io.enq.bits.vc_sel.`0`[5], io.router_resp.vc_sel.`0`[5]
connect route_q.io.enq.bits.vc_sel.`0`[6], io.router_resp.vc_sel.`0`[6]
connect route_q.io.enq.bits.vc_sel.`0`[7], io.router_resp.vc_sel.`0`[7]
connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0]
connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0]
node _T_13 = and(io.in.ready, io.in.valid)
node _T_14 = and(_T_13, io.in.bits.head)
node _T_15 = and(_T_14, at_dest)
when _T_15 :
connect route_q.io.enq.valid, UInt<1>(0h1)
connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[3], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[4], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[5], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[6], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[7], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0)
node _T_16 = eq(UInt<4>(0he), io.in.bits.egress_id)
when _T_16 :
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h1)
node _T_17 = eq(UInt<4>(0hf), io.in.bits.egress_id)
when _T_17 :
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1)
node _T_18 = eq(route_q.io.enq.ready, UInt<1>(0h0))
node _T_19 = and(route_q.io.enq.valid, _T_18)
node _T_20 = eq(_T_19, UInt<1>(0h0))
node _T_21 = asUInt(reset)
node _T_22 = eq(_T_21, UInt<1>(0h0))
when _T_22 :
node _T_23 = eq(_T_20, UInt<1>(0h0))
when _T_23 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1
assert(clock, _T_20, UInt<1>(0h1), "") : assert_1
inst vcalloc_buffer of Queue2_Flit_67
connect vcalloc_buffer.clock, clock
connect vcalloc_buffer.reset, reset
inst vcalloc_q of Queue1_VCAllocResp_33
connect vcalloc_q.clock, clock
connect vcalloc_q.reset, reset
connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node
connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id
connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node
connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id
connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload
connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail
connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head
connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0`
connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1`
connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2`
connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow
connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0)
node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T)
node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1)
node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3)
node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4)
connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5
node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid)
node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head)
node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready)
node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready)
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T)
node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1)
node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3)
node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4)
node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6)
node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7)
connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8
node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid)
node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail)
connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1
node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T
connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[3], io.vcalloc_resp.vc_sel.`0`[3]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[4], io.vcalloc_resp.vc_sel.`0`[4]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[5], io.vcalloc_resp.vc_sel.`0`[5]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[6], io.vcalloc_resp.vc_sel.`0`[6]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[7], io.vcalloc_resp.vc_sel.`0`[7]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0]
node _T_24 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0))
node _T_25 = and(vcalloc_q.io.enq.valid, _T_24)
node _T_26 = eq(_T_25, UInt<1>(0h0))
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
node _T_29 = eq(_T_26, UInt<1>(0h0))
when _T_29 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2
assert(clock, _T_26, UInt<1>(0h1), "") : assert_2
connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0`
connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1`
connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2`
connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail
node c_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node c_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node c_lo = cat(c_lo_hi, c_lo_lo)
node c_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node c_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node c_hi = cat(c_hi_hi, c_hi_lo)
node _c_T = cat(c_hi, c_lo)
node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[0])
node _c_T_1 = cat(c_hi_1, _c_T)
node c_lo_lo_1 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node c_lo_hi_1 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2])
node c_lo_1 = cat(c_lo_hi_1, c_lo_lo_1)
node c_hi_lo_1 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4])
node c_hi_hi_1 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6])
node c_hi_2 = cat(c_hi_hi_1, c_hi_lo_1)
node _c_T_2 = cat(c_hi_2, c_lo_1)
node c_hi_3 = cat(io.out_credit_available.`2`[0], io.out_credit_available.`1`[0])
node _c_T_3 = cat(c_hi_3, _c_T_2)
node _c_T_4 = and(_c_T_1, _c_T_3)
node c = neq(_c_T_4, UInt<1>(0h0))
node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid)
node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c)
node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0))
node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2)
connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3
node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid)
node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c)
node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0))
node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2)
connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3
node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T)
connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1
reg out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}, clock
connect io.out[0], out_bundle
node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
connect out_bundle.valid, _out_bundle_valid_T
connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits
connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0)
node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _out_channel_oh_T_1 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_channel_oh_T_2 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`0`[3])
node _out_channel_oh_T_3 = or(_out_channel_oh_T_2, vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node _out_channel_oh_T_4 = or(_out_channel_oh_T_3, vcalloc_q.io.deq.bits.vc_sel.`0`[5])
node _out_channel_oh_T_5 = or(_out_channel_oh_T_4, vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node out_channel_oh_0 = or(_out_channel_oh_T_5, vcalloc_q.io.deq.bits.vc_sel.`0`[7])
node out_bundle_bits_out_virt_channel_lo_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[1], vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node out_bundle_bits_out_virt_channel_lo_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[3], vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node out_bundle_bits_out_virt_channel_lo = cat(out_bundle_bits_out_virt_channel_lo_hi, out_bundle_bits_out_virt_channel_lo_lo)
node out_bundle_bits_out_virt_channel_hi_lo = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[5], vcalloc_q.io.deq.bits.vc_sel.`0`[4])
node out_bundle_bits_out_virt_channel_hi_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[7], vcalloc_q.io.deq.bits.vc_sel.`0`[6])
node out_bundle_bits_out_virt_channel_hi = cat(out_bundle_bits_out_virt_channel_hi_hi, out_bundle_bits_out_virt_channel_hi_lo)
node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, out_bundle_bits_out_virt_channel_lo)
node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 7, 4)
node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T, 3, 0)
node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1)
node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo_1)
node out_bundle_bits_out_virt_channel_hi_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 3, 2)
node out_bundle_bits_out_virt_channel_lo_2 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 0)
node _out_bundle_bits_out_virt_channel_T_3 = orr(out_bundle_bits_out_virt_channel_hi_2)
node _out_bundle_bits_out_virt_channel_T_4 = or(out_bundle_bits_out_virt_channel_hi_2, out_bundle_bits_out_virt_channel_lo_2)
node _out_bundle_bits_out_virt_channel_T_5 = bits(_out_bundle_bits_out_virt_channel_T_4, 1, 1)
node _out_bundle_bits_out_virt_channel_T_6 = cat(_out_bundle_bits_out_virt_channel_T_3, _out_bundle_bits_out_virt_channel_T_5)
node _out_bundle_bits_out_virt_channel_T_7 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_6)
node _out_bundle_bits_out_virt_channel_T_8 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_7, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_9 = mux(vcalloc_q.io.deq.bits.vc_sel.`1`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_10 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_11 = or(_out_bundle_bits_out_virt_channel_T_8, _out_bundle_bits_out_virt_channel_T_9)
node _out_bundle_bits_out_virt_channel_T_12 = or(_out_bundle_bits_out_virt_channel_T_11, _out_bundle_bits_out_virt_channel_T_10)
wire _out_bundle_bits_out_virt_channel_WIRE : UInt<3>
connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_12
connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE
node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0))
node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T)
connect io.debug.va_stall, _io_debug_va_stall_T_1
node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T)
connect io.debug.sa_stall, _io_debug_sa_stall_T_1 | module IngressUnit_33( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_4, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [5:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _GEN; // @[Decoupled.scala:51:35]
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [4:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [4:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire [1:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [4:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [4:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T = io_in_bits_egress_id == 6'h17; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 6'h1A; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 6'h1D; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = io_in_bits_egress_id == 6'h20; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 3'h6 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_2 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_3 ? 4'hA : 4'h0); // @[Mux.scala:30:73]
assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'hD; // @[Mux.scala:30:73]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'hD; // @[Mux.scala:30:73]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_64 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 11, 0)
node _source_ok_T = shr(io.in.a.bits.source, 12)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<12>(0h80f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits = bits(_uncommonBits_T, 11, 0)
node _T_4 = shr(io.in.a.bits.source, 12)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<12>(0h80f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 11, 0)
node _T_24 = shr(io.in.a.bits.source, 12)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<12>(0h80f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 11, 0)
node _T_86 = shr(io.in.a.bits.source, 12)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<12>(0h80f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 11, 0)
node _T_152 = shr(io.in.a.bits.source, 12)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<12>(0h80f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 11, 0)
node _T_199 = shr(io.in.a.bits.source, 12)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<12>(0h80f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_208 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_209 = cvt(_T_208)
node _T_210 = and(_T_209, asSInt(UInt<17>(0h10000)))
node _T_211 = asSInt(_T_210)
node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0)))
node _T_213 = and(_T_207, _T_212)
node _T_214 = or(UInt<1>(0h0), _T_213)
node _T_215 = and(_T_206, _T_214)
node _T_216 = asUInt(reset)
node _T_217 = eq(_T_216, UInt<1>(0h0))
when _T_217 :
node _T_218 = eq(_T_215, UInt<1>(0h0))
when _T_218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_215, UInt<1>(0h1), "") : assert_26
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(is_aligned, UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_225 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_T_225, UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_225, UInt<1>(0h1), "") : assert_29
node _T_229 = eq(io.in.a.bits.mask, mask)
node _T_230 = asUInt(reset)
node _T_231 = eq(_T_230, UInt<1>(0h0))
when _T_231 :
node _T_232 = eq(_T_229, UInt<1>(0h0))
when _T_232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_229, UInt<1>(0h1), "") : assert_30
node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_233 :
node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_236 = and(_T_234, _T_235)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 11, 0)
node _T_237 = shr(io.in.a.bits.source, 12)
node _T_238 = eq(_T_237, UInt<1>(0h0))
node _T_239 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_240 = and(_T_238, _T_239)
node _T_241 = leq(uncommonBits_5, UInt<12>(0h80f))
node _T_242 = and(_T_240, _T_241)
node _T_243 = and(_T_236, _T_242)
node _T_244 = or(UInt<1>(0h0), _T_243)
node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_246 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_247 = cvt(_T_246)
node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000)))
node _T_249 = asSInt(_T_248)
node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0)))
node _T_251 = and(_T_245, _T_250)
node _T_252 = or(UInt<1>(0h0), _T_251)
node _T_253 = and(_T_244, _T_252)
node _T_254 = asUInt(reset)
node _T_255 = eq(_T_254, UInt<1>(0h0))
when _T_255 :
node _T_256 = eq(_T_253, UInt<1>(0h0))
when _T_256 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_253, UInt<1>(0h1), "") : assert_31
node _T_257 = asUInt(reset)
node _T_258 = eq(_T_257, UInt<1>(0h0))
when _T_258 :
node _T_259 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_259 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(is_aligned, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_263 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_264 = asUInt(reset)
node _T_265 = eq(_T_264, UInt<1>(0h0))
when _T_265 :
node _T_266 = eq(_T_263, UInt<1>(0h0))
when _T_266 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_263, UInt<1>(0h1), "") : assert_34
node _T_267 = not(mask)
node _T_268 = and(io.in.a.bits.mask, _T_267)
node _T_269 = eq(_T_268, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_269, UInt<1>(0h1), "") : assert_35
node _T_273 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_273 :
node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_276 = and(_T_274, _T_275)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 11, 0)
node _T_277 = shr(io.in.a.bits.source, 12)
node _T_278 = eq(_T_277, UInt<1>(0h0))
node _T_279 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_280 = and(_T_278, _T_279)
node _T_281 = leq(uncommonBits_6, UInt<12>(0h80f))
node _T_282 = and(_T_280, _T_281)
node _T_283 = and(_T_276, _T_282)
node _T_284 = or(UInt<1>(0h0), _T_283)
node _T_285 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_286 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_287 = cvt(_T_286)
node _T_288 = and(_T_287, asSInt(UInt<17>(0h10000)))
node _T_289 = asSInt(_T_288)
node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0)))
node _T_291 = and(_T_285, _T_290)
node _T_292 = or(UInt<1>(0h0), _T_291)
node _T_293 = and(_T_284, _T_292)
node _T_294 = asUInt(reset)
node _T_295 = eq(_T_294, UInt<1>(0h0))
when _T_295 :
node _T_296 = eq(_T_293, UInt<1>(0h0))
when _T_296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_293, UInt<1>(0h1), "") : assert_36
node _T_297 = asUInt(reset)
node _T_298 = eq(_T_297, UInt<1>(0h0))
when _T_298 :
node _T_299 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(is_aligned, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_303 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_304 = asUInt(reset)
node _T_305 = eq(_T_304, UInt<1>(0h0))
when _T_305 :
node _T_306 = eq(_T_303, UInt<1>(0h0))
when _T_306 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_303, UInt<1>(0h1), "") : assert_39
node _T_307 = eq(io.in.a.bits.mask, mask)
node _T_308 = asUInt(reset)
node _T_309 = eq(_T_308, UInt<1>(0h0))
when _T_309 :
node _T_310 = eq(_T_307, UInt<1>(0h0))
when _T_310 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_307, UInt<1>(0h1), "") : assert_40
node _T_311 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_311 :
node _T_312 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_313 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_314 = and(_T_312, _T_313)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 11, 0)
node _T_315 = shr(io.in.a.bits.source, 12)
node _T_316 = eq(_T_315, UInt<1>(0h0))
node _T_317 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_318 = and(_T_316, _T_317)
node _T_319 = leq(uncommonBits_7, UInt<12>(0h80f))
node _T_320 = and(_T_318, _T_319)
node _T_321 = and(_T_314, _T_320)
node _T_322 = or(UInt<1>(0h0), _T_321)
node _T_323 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_324 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_325 = cvt(_T_324)
node _T_326 = and(_T_325, asSInt(UInt<17>(0h10000)))
node _T_327 = asSInt(_T_326)
node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0)))
node _T_329 = and(_T_323, _T_328)
node _T_330 = or(UInt<1>(0h0), _T_329)
node _T_331 = and(_T_322, _T_330)
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_331, UInt<1>(0h1), "") : assert_41
node _T_335 = asUInt(reset)
node _T_336 = eq(_T_335, UInt<1>(0h0))
when _T_336 :
node _T_337 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_337 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(is_aligned, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_341 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_342 = asUInt(reset)
node _T_343 = eq(_T_342, UInt<1>(0h0))
when _T_343 :
node _T_344 = eq(_T_341, UInt<1>(0h0))
when _T_344 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_341, UInt<1>(0h1), "") : assert_44
node _T_345 = eq(io.in.a.bits.mask, mask)
node _T_346 = asUInt(reset)
node _T_347 = eq(_T_346, UInt<1>(0h0))
when _T_347 :
node _T_348 = eq(_T_345, UInt<1>(0h0))
when _T_348 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_345, UInt<1>(0h1), "") : assert_45
node _T_349 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_349 :
node _T_350 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_351 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_352 = and(_T_350, _T_351)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<12>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 11, 0)
node _T_353 = shr(io.in.a.bits.source, 12)
node _T_354 = eq(_T_353, UInt<1>(0h0))
node _T_355 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_356 = and(_T_354, _T_355)
node _T_357 = leq(uncommonBits_8, UInt<12>(0h80f))
node _T_358 = and(_T_356, _T_357)
node _T_359 = and(_T_352, _T_358)
node _T_360 = or(UInt<1>(0h0), _T_359)
node _T_361 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_362 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_363 = cvt(_T_362)
node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000)))
node _T_365 = asSInt(_T_364)
node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0)))
node _T_367 = and(_T_361, _T_366)
node _T_368 = or(UInt<1>(0h0), _T_367)
node _T_369 = and(_T_360, _T_368)
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(_T_369, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_369, UInt<1>(0h1), "") : assert_46
node _T_373 = asUInt(reset)
node _T_374 = eq(_T_373, UInt<1>(0h0))
when _T_374 :
node _T_375 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(is_aligned, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_379 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_380 = asUInt(reset)
node _T_381 = eq(_T_380, UInt<1>(0h0))
when _T_381 :
node _T_382 = eq(_T_379, UInt<1>(0h0))
when _T_382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_379, UInt<1>(0h1), "") : assert_49
node _T_383 = eq(io.in.a.bits.mask, mask)
node _T_384 = asUInt(reset)
node _T_385 = eq(_T_384, UInt<1>(0h0))
when _T_385 :
node _T_386 = eq(_T_383, UInt<1>(0h0))
when _T_386 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_383, UInt<1>(0h1), "") : assert_50
node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_387, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_391 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_T_391, UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_391, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<12>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 11, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 12)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<12>(0h80f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_395 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_395 :
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_399 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_399, UInt<1>(0h1), "") : assert_54
node _T_403 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_404 = asUInt(reset)
node _T_405 = eq(_T_404, UInt<1>(0h0))
when _T_405 :
node _T_406 = eq(_T_403, UInt<1>(0h0))
when _T_406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_403, UInt<1>(0h1), "") : assert_55
node _T_407 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_408 = asUInt(reset)
node _T_409 = eq(_T_408, UInt<1>(0h0))
when _T_409 :
node _T_410 = eq(_T_407, UInt<1>(0h0))
when _T_410 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_407, UInt<1>(0h1), "") : assert_56
node _T_411 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_411, UInt<1>(0h1), "") : assert_57
node _T_415 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_415 :
node _T_416 = asUInt(reset)
node _T_417 = eq(_T_416, UInt<1>(0h0))
when _T_417 :
node _T_418 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_418 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_419 = asUInt(reset)
node _T_420 = eq(_T_419, UInt<1>(0h0))
when _T_420 :
node _T_421 = eq(sink_ok, UInt<1>(0h0))
when _T_421 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_422 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_423 = asUInt(reset)
node _T_424 = eq(_T_423, UInt<1>(0h0))
when _T_424 :
node _T_425 = eq(_T_422, UInt<1>(0h0))
when _T_425 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_422, UInt<1>(0h1), "") : assert_60
node _T_426 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_426, UInt<1>(0h1), "") : assert_61
node _T_430 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_431 = asUInt(reset)
node _T_432 = eq(_T_431, UInt<1>(0h0))
when _T_432 :
node _T_433 = eq(_T_430, UInt<1>(0h0))
when _T_433 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_430, UInt<1>(0h1), "") : assert_62
node _T_434 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_435 = asUInt(reset)
node _T_436 = eq(_T_435, UInt<1>(0h0))
when _T_436 :
node _T_437 = eq(_T_434, UInt<1>(0h0))
when _T_437 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_434, UInt<1>(0h1), "") : assert_63
node _T_438 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_439 = or(UInt<1>(0h0), _T_438)
node _T_440 = asUInt(reset)
node _T_441 = eq(_T_440, UInt<1>(0h0))
when _T_441 :
node _T_442 = eq(_T_439, UInt<1>(0h0))
when _T_442 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_439, UInt<1>(0h1), "") : assert_64
node _T_443 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_443 :
node _T_444 = asUInt(reset)
node _T_445 = eq(_T_444, UInt<1>(0h0))
when _T_445 :
node _T_446 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_446 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(sink_ok, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_450 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_451 = asUInt(reset)
node _T_452 = eq(_T_451, UInt<1>(0h0))
when _T_452 :
node _T_453 = eq(_T_450, UInt<1>(0h0))
when _T_453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_450, UInt<1>(0h1), "") : assert_67
node _T_454 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_455 = asUInt(reset)
node _T_456 = eq(_T_455, UInt<1>(0h0))
when _T_456 :
node _T_457 = eq(_T_454, UInt<1>(0h0))
when _T_457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_454, UInt<1>(0h1), "") : assert_68
node _T_458 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_459 = asUInt(reset)
node _T_460 = eq(_T_459, UInt<1>(0h0))
when _T_460 :
node _T_461 = eq(_T_458, UInt<1>(0h0))
when _T_461 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_458, UInt<1>(0h1), "") : assert_69
node _T_462 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_463 = or(_T_462, io.in.d.bits.corrupt)
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_463, UInt<1>(0h1), "") : assert_70
node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_468 = or(UInt<1>(0h0), _T_467)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_468, UInt<1>(0h1), "") : assert_71
node _T_472 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_472 :
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_476 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_477 = asUInt(reset)
node _T_478 = eq(_T_477, UInt<1>(0h0))
when _T_478 :
node _T_479 = eq(_T_476, UInt<1>(0h0))
when _T_479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_476, UInt<1>(0h1), "") : assert_73
node _T_480 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(_T_480, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_480, UInt<1>(0h1), "") : assert_74
node _T_484 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_485 = or(UInt<1>(0h0), _T_484)
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_485, UInt<1>(0h1), "") : assert_75
node _T_489 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_489 :
node _T_490 = asUInt(reset)
node _T_491 = eq(_T_490, UInt<1>(0h0))
when _T_491 :
node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_492 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_493 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_494 = asUInt(reset)
node _T_495 = eq(_T_494, UInt<1>(0h0))
when _T_495 :
node _T_496 = eq(_T_493, UInt<1>(0h0))
when _T_496 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_493, UInt<1>(0h1), "") : assert_77
node _T_497 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_498 = or(_T_497, io.in.d.bits.corrupt)
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_498, UInt<1>(0h1), "") : assert_78
node _T_502 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_503 = or(UInt<1>(0h0), _T_502)
node _T_504 = asUInt(reset)
node _T_505 = eq(_T_504, UInt<1>(0h0))
when _T_505 :
node _T_506 = eq(_T_503, UInt<1>(0h0))
when _T_506 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_503, UInt<1>(0h1), "") : assert_79
node _T_507 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_507 :
node _T_508 = asUInt(reset)
node _T_509 = eq(_T_508, UInt<1>(0h0))
when _T_509 :
node _T_510 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_510 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_511 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_512 = asUInt(reset)
node _T_513 = eq(_T_512, UInt<1>(0h0))
when _T_513 :
node _T_514 = eq(_T_511, UInt<1>(0h0))
when _T_514 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_511, UInt<1>(0h1), "") : assert_81
node _T_515 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_516 = asUInt(reset)
node _T_517 = eq(_T_516, UInt<1>(0h0))
when _T_517 :
node _T_518 = eq(_T_515, UInt<1>(0h0))
when _T_518 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_515, UInt<1>(0h1), "") : assert_82
node _T_519 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_520 = or(UInt<1>(0h0), _T_519)
node _T_521 = asUInt(reset)
node _T_522 = eq(_T_521, UInt<1>(0h0))
when _T_522 :
node _T_523 = eq(_T_520, UInt<1>(0h0))
when _T_523 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_520, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<17>(0h0)
connect _WIRE.bits.source, UInt<12>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_524 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_525 = asUInt(reset)
node _T_526 = eq(_T_525, UInt<1>(0h0))
when _T_526 :
node _T_527 = eq(_T_524, UInt<1>(0h0))
when _T_527 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_524, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<17>(0h0)
connect _WIRE_2.bits.source, UInt<12>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_528 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_529 = asUInt(reset)
node _T_530 = eq(_T_529, UInt<1>(0h0))
when _T_530 :
node _T_531 = eq(_T_528, UInt<1>(0h0))
when _T_531 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_528, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_532 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_533 = asUInt(reset)
node _T_534 = eq(_T_533, UInt<1>(0h0))
when _T_534 :
node _T_535 = eq(_T_532, UInt<1>(0h0))
when _T_535 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_532, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_536 = eq(a_first, UInt<1>(0h0))
node _T_537 = and(io.in.a.valid, _T_536)
when _T_537 :
node _T_538 = eq(io.in.a.bits.opcode, opcode)
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_538, UInt<1>(0h1), "") : assert_87
node _T_542 = eq(io.in.a.bits.param, param)
node _T_543 = asUInt(reset)
node _T_544 = eq(_T_543, UInt<1>(0h0))
when _T_544 :
node _T_545 = eq(_T_542, UInt<1>(0h0))
when _T_545 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_542, UInt<1>(0h1), "") : assert_88
node _T_546 = eq(io.in.a.bits.size, size)
node _T_547 = asUInt(reset)
node _T_548 = eq(_T_547, UInt<1>(0h0))
when _T_548 :
node _T_549 = eq(_T_546, UInt<1>(0h0))
when _T_549 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_546, UInt<1>(0h1), "") : assert_89
node _T_550 = eq(io.in.a.bits.source, source)
node _T_551 = asUInt(reset)
node _T_552 = eq(_T_551, UInt<1>(0h0))
when _T_552 :
node _T_553 = eq(_T_550, UInt<1>(0h0))
when _T_553 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_550, UInt<1>(0h1), "") : assert_90
node _T_554 = eq(io.in.a.bits.address, address)
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(_T_554, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_554, UInt<1>(0h1), "") : assert_91
node _T_558 = and(io.in.a.ready, io.in.a.valid)
node _T_559 = and(_T_558, a_first)
when _T_559 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_560 = eq(d_first, UInt<1>(0h0))
node _T_561 = and(io.in.d.valid, _T_560)
when _T_561 :
node _T_562 = eq(io.in.d.bits.opcode, opcode_1)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_562, UInt<1>(0h1), "") : assert_92
node _T_566 = eq(io.in.d.bits.param, param_1)
node _T_567 = asUInt(reset)
node _T_568 = eq(_T_567, UInt<1>(0h0))
when _T_568 :
node _T_569 = eq(_T_566, UInt<1>(0h0))
when _T_569 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_566, UInt<1>(0h1), "") : assert_93
node _T_570 = eq(io.in.d.bits.size, size_1)
node _T_571 = asUInt(reset)
node _T_572 = eq(_T_571, UInt<1>(0h0))
when _T_572 :
node _T_573 = eq(_T_570, UInt<1>(0h0))
when _T_573 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_570, UInt<1>(0h1), "") : assert_94
node _T_574 = eq(io.in.d.bits.source, source_1)
node _T_575 = asUInt(reset)
node _T_576 = eq(_T_575, UInt<1>(0h0))
when _T_576 :
node _T_577 = eq(_T_574, UInt<1>(0h0))
when _T_577 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_574, UInt<1>(0h1), "") : assert_95
node _T_578 = eq(io.in.d.bits.sink, sink)
node _T_579 = asUInt(reset)
node _T_580 = eq(_T_579, UInt<1>(0h0))
when _T_580 :
node _T_581 = eq(_T_578, UInt<1>(0h0))
when _T_581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_578, UInt<1>(0h1), "") : assert_96
node _T_582 = eq(io.in.d.bits.denied, denied)
node _T_583 = asUInt(reset)
node _T_584 = eq(_T_583, UInt<1>(0h0))
when _T_584 :
node _T_585 = eq(_T_582, UInt<1>(0h0))
when _T_585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_582, UInt<1>(0h1), "") : assert_97
node _T_586 = and(io.in.d.ready, io.in.d.valid)
node _T_587 = and(_T_586, d_first)
when _T_587 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2064>, clock, reset, UInt<2064>(0h0)
regreset inflight_opcodes : UInt<8256>, clock, reset, UInt<8256>(0h0)
regreset inflight_sizes : UInt<8256>, clock, reset, UInt<8256>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<2064>
connect a_set, UInt<2064>(0h0)
wire a_set_wo_ready : UInt<2064>
connect a_set_wo_ready, UInt<2064>(0h0)
wire a_opcodes_set : UInt<8256>
connect a_opcodes_set, UInt<8256>(0h0)
wire a_sizes_set : UInt<8256>
connect a_sizes_set, UInt<8256>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_588 = and(io.in.a.valid, a_first_1)
node _T_589 = and(_T_588, UInt<1>(0h1))
when _T_589 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_590 = and(io.in.a.ready, io.in.a.valid)
node _T_591 = and(_T_590, a_first_1)
node _T_592 = and(_T_591, UInt<1>(0h1))
when _T_592 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_593 = dshr(inflight, io.in.a.bits.source)
node _T_594 = bits(_T_593, 0, 0)
node _T_595 = eq(_T_594, UInt<1>(0h0))
node _T_596 = asUInt(reset)
node _T_597 = eq(_T_596, UInt<1>(0h0))
when _T_597 :
node _T_598 = eq(_T_595, UInt<1>(0h0))
when _T_598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_595, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<2064>
connect d_clr, UInt<2064>(0h0)
wire d_clr_wo_ready : UInt<2064>
connect d_clr_wo_ready, UInt<2064>(0h0)
wire d_opcodes_clr : UInt<8256>
connect d_opcodes_clr, UInt<8256>(0h0)
wire d_sizes_clr : UInt<8256>
connect d_sizes_clr, UInt<8256>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_599 = and(io.in.d.valid, d_first_1)
node _T_600 = and(_T_599, UInt<1>(0h1))
node _T_601 = eq(d_release_ack, UInt<1>(0h0))
node _T_602 = and(_T_600, _T_601)
when _T_602 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_603 = and(io.in.d.ready, io.in.d.valid)
node _T_604 = and(_T_603, d_first_1)
node _T_605 = and(_T_604, UInt<1>(0h1))
node _T_606 = eq(d_release_ack, UInt<1>(0h0))
node _T_607 = and(_T_605, _T_606)
when _T_607 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_608 = and(io.in.d.valid, d_first_1)
node _T_609 = and(_T_608, UInt<1>(0h1))
node _T_610 = eq(d_release_ack, UInt<1>(0h0))
node _T_611 = and(_T_609, _T_610)
when _T_611 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_612 = dshr(inflight, io.in.d.bits.source)
node _T_613 = bits(_T_612, 0, 0)
node _T_614 = or(_T_613, same_cycle_resp)
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_614, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_618 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_619 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_620 = or(_T_618, _T_619)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_620, UInt<1>(0h1), "") : assert_100
node _T_624 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_625 = asUInt(reset)
node _T_626 = eq(_T_625, UInt<1>(0h0))
when _T_626 :
node _T_627 = eq(_T_624, UInt<1>(0h0))
when _T_627 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_624, UInt<1>(0h1), "") : assert_101
else :
node _T_628 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_629 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_630 = or(_T_628, _T_629)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_630, UInt<1>(0h1), "") : assert_102
node _T_634 = eq(io.in.d.bits.size, a_size_lookup)
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_T_634, UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_634, UInt<1>(0h1), "") : assert_103
node _T_638 = and(io.in.d.valid, d_first_1)
node _T_639 = and(_T_638, a_first_1)
node _T_640 = and(_T_639, io.in.a.valid)
node _T_641 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_642 = and(_T_640, _T_641)
node _T_643 = eq(d_release_ack, UInt<1>(0h0))
node _T_644 = and(_T_642, _T_643)
when _T_644 :
node _T_645 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_646 = or(_T_645, io.in.a.ready)
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_646, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_130
node _T_650 = orr(inflight)
node _T_651 = eq(_T_650, UInt<1>(0h0))
node _T_652 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_653 = or(_T_651, _T_652)
node _T_654 = lt(watchdog, plusarg_reader.out)
node _T_655 = or(_T_653, _T_654)
node _T_656 = asUInt(reset)
node _T_657 = eq(_T_656, UInt<1>(0h0))
when _T_657 :
node _T_658 = eq(_T_655, UInt<1>(0h0))
when _T_658 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_655, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_659 = and(io.in.a.ready, io.in.a.valid)
node _T_660 = and(io.in.d.ready, io.in.d.valid)
node _T_661 = or(_T_659, _T_660)
when _T_661 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2064>, clock, reset, UInt<2064>(0h0)
regreset inflight_opcodes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0)
regreset inflight_sizes_1 : UInt<8256>, clock, reset, UInt<8256>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<17>(0h0)
connect _c_first_WIRE.bits.source, UInt<12>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<17>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<12>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<2064>
connect c_set, UInt<2064>(0h0)
wire c_set_wo_ready : UInt<2064>
connect c_set_wo_ready, UInt<2064>(0h0)
wire c_opcodes_set : UInt<8256>
connect c_opcodes_set, UInt<8256>(0h0)
wire c_sizes_set : UInt<8256>
connect c_sizes_set, UInt<8256>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<17>(0h0)
connect _WIRE_6.bits.source, UInt<12>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_662 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<17>(0h0)
connect _WIRE_8.bits.source, UInt<12>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_663 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_664 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_665 = and(_T_663, _T_664)
node _T_666 = and(_T_662, _T_665)
when _T_666 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<12>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<17>(0h0)
connect _WIRE_10.bits.source, UInt<12>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_667 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_668 = and(_T_667, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<17>(0h0)
connect _WIRE_12.bits.source, UInt<12>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_669 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_670 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_671 = and(_T_669, _T_670)
node _T_672 = and(_T_668, _T_671)
when _T_672 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_set_WIRE.bits.source, UInt<12>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<12>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<12>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<12>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<12>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<17>(0h0)
connect _WIRE_14.bits.source, UInt<12>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_673 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_674 = bits(_T_673, 0, 0)
node _T_675 = eq(_T_674, UInt<1>(0h0))
node _T_676 = asUInt(reset)
node _T_677 = eq(_T_676, UInt<1>(0h0))
when _T_677 :
node _T_678 = eq(_T_675, UInt<1>(0h0))
when _T_678 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_675, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<12>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<12>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<2064>
connect d_clr_1, UInt<2064>(0h0)
wire d_clr_wo_ready_1 : UInt<2064>
connect d_clr_wo_ready_1, UInt<2064>(0h0)
wire d_opcodes_clr_1 : UInt<8256>
connect d_opcodes_clr_1, UInt<8256>(0h0)
wire d_sizes_clr_1 : UInt<8256>
connect d_sizes_clr_1, UInt<8256>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_679 = and(io.in.d.valid, d_first_2)
node _T_680 = and(_T_679, UInt<1>(0h1))
node _T_681 = and(_T_680, d_release_ack_1)
when _T_681 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_682 = and(io.in.d.ready, io.in.d.valid)
node _T_683 = and(_T_682, d_first_2)
node _T_684 = and(_T_683, UInt<1>(0h1))
node _T_685 = and(_T_684, d_release_ack_1)
when _T_685 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_686 = and(io.in.d.valid, d_first_2)
node _T_687 = and(_T_686, UInt<1>(0h1))
node _T_688 = and(_T_687, d_release_ack_1)
when _T_688 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<12>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<12>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_689 = dshr(inflight_1, io.in.d.bits.source)
node _T_690 = bits(_T_689, 0, 0)
node _T_691 = or(_T_690, same_cycle_resp_1)
node _T_692 = asUInt(reset)
node _T_693 = eq(_T_692, UInt<1>(0h0))
when _T_693 :
node _T_694 = eq(_T_691, UInt<1>(0h0))
when _T_694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_691, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<17>(0h0)
connect _WIRE_16.bits.source, UInt<12>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_695 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_696 = asUInt(reset)
node _T_697 = eq(_T_696, UInt<1>(0h0))
when _T_697 :
node _T_698 = eq(_T_695, UInt<1>(0h0))
when _T_698 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_695, UInt<1>(0h1), "") : assert_108
else :
node _T_699 = eq(io.in.d.bits.size, c_size_lookup)
node _T_700 = asUInt(reset)
node _T_701 = eq(_T_700, UInt<1>(0h0))
when _T_701 :
node _T_702 = eq(_T_699, UInt<1>(0h0))
when _T_702 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_699, UInt<1>(0h1), "") : assert_109
node _T_703 = and(io.in.d.valid, d_first_2)
node _T_704 = and(_T_703, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<17>(0h0)
connect _WIRE_18.bits.source, UInt<12>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_705 = and(_T_704, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<17>(0h0)
connect _WIRE_20.bits.source, UInt<12>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_706 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_707 = and(_T_705, _T_706)
node _T_708 = and(_T_707, d_release_ack_1)
node _T_709 = eq(c_probe_ack, UInt<1>(0h0))
node _T_710 = and(_T_708, _T_709)
when _T_710 :
node _T_711 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<17>(0h0)
connect _WIRE_22.bits.source, UInt<12>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_712 = or(_T_711, _WIRE_23.ready)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_131
node _T_716 = orr(inflight_1)
node _T_717 = eq(_T_716, UInt<1>(0h0))
node _T_718 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_719 = or(_T_717, _T_718)
node _T_720 = lt(watchdog_1, plusarg_reader_1.out)
node _T_721 = or(_T_719, _T_720)
node _T_722 = asUInt(reset)
node _T_723 = eq(_T_722, UInt<1>(0h0))
when _T_723 :
node _T_724 = eq(_T_721, UInt<1>(0h0))
when _T_724 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_721, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<17>(0h0)
connect _WIRE_24.bits.source, UInt<12>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_725 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_726 = and(io.in.d.ready, io.in.d.valid)
node _T_727 = or(_T_725, _T_726)
when _T_727 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_64( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [11:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [11:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [16:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [11:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_release_ack = 1'h0; // @[Monitor.scala:673:46]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire d_release_ack_1 = 1'h0; // @[Monitor.scala:783:46]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata = 1'h1; // @[Edges.scala:106:36]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata_1 = 1'h1; // @[Edges.scala:106:36]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire d_first_beats1_opdata_2 = 1'h1; // @[Edges.scala:106:36]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [2:0] io_in_d_bits_opcode = 3'h1; // @[Monitor.scala:36:7]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [8255:0] _inflight_opcodes_T_4 =
8256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:815:62]
wire [8255:0] _inflight_sizes_T_4 =
8256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:816:58]
wire [2063:0] _inflight_T_4 = 2064'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; // @[Monitor.scala:814:46]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_first_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_first_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_first_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_first_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_set_wo_ready_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_set_wo_ready_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_opcodes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_opcodes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_sizes_set_interm_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_sizes_set_interm_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_opcodes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_opcodes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_sizes_set_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_sizes_set_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_probe_ack_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_probe_ack_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _c_probe_ack_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _c_probe_ack_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_1_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_2_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_3_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [16:0] _same_cycle_resp_WIRE_4_bits_address = 17'h0; // @[Bundles.scala:265:74]
wire [16:0] _same_cycle_resp_WIRE_5_bits_address = 17'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_first_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_first_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_first_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_first_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_set_wo_ready_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_set_wo_ready_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_opcodes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_sizes_set_interm_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_sizes_set_interm_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_opcodes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_opcodes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_sizes_set_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_sizes_set_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_probe_ack_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_probe_ack_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_probe_ack_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_probe_ack_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_1_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_2_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_3_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_4_bits_source = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_5_bits_source = 12'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [8255:0] c_opcodes_set = 8256'h0; // @[Monitor.scala:740:34]
wire [8255:0] c_sizes_set = 8256'h0; // @[Monitor.scala:741:34]
wire [8255:0] d_opcodes_clr_1 = 8256'h0; // @[Monitor.scala:776:34]
wire [8255:0] d_sizes_clr_1 = 8256'h0; // @[Monitor.scala:777:34]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2063:0] c_set = 2064'h0; // @[Monitor.scala:738:34]
wire [2063:0] c_set_wo_ready = 2064'h0; // @[Monitor.scala:739:34]
wire [2063:0] d_clr_1 = 2064'h0; // @[Monitor.scala:774:34]
wire [2063:0] d_clr_wo_ready_1 = 2064'h0; // @[Monitor.scala:775:34]
wire [32769:0] _c_sizes_set_T_1 = 32770'h0; // @[Monitor.scala:768:52]
wire [14:0] _c_opcodes_set_T = 15'h0; // @[Monitor.scala:767:79]
wire [14:0] _c_sizes_set_T = 15'h0; // @[Monitor.scala:768:77]
wire [32770:0] _c_opcodes_set_T_1 = 32771'h0; // @[Monitor.scala:767:54]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [4095:0] _c_set_wo_ready_T = 4096'h1; // @[OneHot.scala:58:35]
wire [4095:0] _c_set_T = 4096'h1; // @[OneHot.scala:58:35]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [11:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [11:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 12'h810; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [16:0] _is_aligned_T = {14'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [11:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [11:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [11:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 12'h810; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_659 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_659; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_659; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [11:0] source; // @[Monitor.scala:390:22]
reg [16:0] address; // @[Monitor.scala:391:22]
wire _T_727 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_727; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_727; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_727; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [11:0] source_1; // @[Monitor.scala:541:22]
reg [2063:0] inflight; // @[Monitor.scala:614:27]
reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [2063:0] a_set; // @[Monitor.scala:626:34]
wire [2063:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [8255:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [8255:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [14:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [14:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [14:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [14:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [14:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [14:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [14:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [14:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [14:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [8255:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [8255:0] _a_opcode_lookup_T_6 = {8252'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [8255:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [8255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [8255:0] _a_size_lookup_T_6 = {8252'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [8255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[8255:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [4095:0] _GEN_2 = 4096'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [4095:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [4095:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire _T_592 = _T_659 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_592 ? _a_set_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_592 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_592 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [14:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [14:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [14:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [32770:0] _a_opcodes_set_T_1 = {32767'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_592 ? _a_opcodes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [32769:0] _a_sizes_set_T_1 = {32767'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_592 ? _a_sizes_set_T_1[8255:0] : 8256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [2063:0] d_clr; // @[Monitor.scala:664:34]
wire [2063:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [8255:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [8255:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _T_638 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [4095:0] _GEN_4 = 4096'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [4095:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [4095:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_4; // @[OneHot.scala:58:35]
wire [4095:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_4; // @[OneHot.scala:58:35]
wire [4095:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_4; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_638 ? _d_clr_wo_ready_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire _T_605 = _T_727 & d_first_1; // @[Decoupled.scala:51:35]
assign d_clr = _T_605 ? _d_clr_T[2063:0] : 2064'h0; // @[OneHot.scala:58:35]
wire [32782:0] _d_opcodes_clr_T_5 = 32783'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_605 ? _d_opcodes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:668:33, :678:{25,89}, :680:{21,76}]
wire [32782:0] _d_sizes_clr_T_5 = 32783'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_605 ? _d_sizes_clr_T_5[8255:0] : 8256'h0; // @[Monitor.scala:670:31, :678:{25,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [2063:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [2063:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [2063:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [8255:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [8255:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [8255:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [8255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [8255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [8255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [2063:0] inflight_1; // @[Monitor.scala:726:35]
wire [2063:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [8255:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [8255:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [8255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [8255:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [8255:0] _c_opcode_lookup_T_6 = {8252'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [8255:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[8255:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [8255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [8255:0] _c_size_lookup_T_6 = {8252'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [8255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[8255:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [32782:0] _d_opcodes_clr_T_11 = 32783'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
wire [32782:0] _d_sizes_clr_T_11 = 32783'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 12'h0; // @[Monitor.scala:36:7, :795:113]
wire [2063:0] _inflight_T_5 = _inflight_T_3; // @[Monitor.scala:814:{35,44}]
wire [8255:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3; // @[Monitor.scala:815:{43,60}]
wire [8255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3; // @[Monitor.scala:816:{41,56}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_76 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_76( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module L1MetadataArrayBank :
input clock : Clock
input reset : Reset
output io : { flip read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>}}, flip write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, resp : { coh : { state : UInt<2>}, tag : UInt<20>}[4]}
wire rstVal_meta : { state : UInt<2>}
connect rstVal_meta.state, UInt<2>(0h0)
wire rstVal : { coh : { state : UInt<2>}, tag : UInt<20>}
connect rstVal.tag, UInt<1>(0h0)
connect rstVal.coh, rstVal_meta
regreset rst_cnt : UInt<5>, clock, reset, UInt<5>(0h0)
node rst = lt(rst_cnt, UInt<5>(0h10))
node waddr = mux(rst, rst_cnt, io.write.bits.idx)
node _wdata_T = mux(rst, rstVal, io.write.bits.data)
node wdata = cat(_wdata_T.coh.state, _wdata_T.tag)
node _wmask_T = or(rst, UInt<1>(0h0))
node _wmask_T_1 = not(UInt<4>(0h0))
node _wmask_T_2 = mux(_wmask_T, _wmask_T_1, io.write.bits.way_en)
node wmask_0 = bits(_wmask_T_2, 0, 0)
node wmask_1 = bits(_wmask_T_2, 1, 1)
node wmask_2 = bits(_wmask_T_2, 2, 2)
node wmask_3 = bits(_wmask_T_2, 3, 3)
node _rmask_T = or(rst, UInt<1>(0h0))
node _rmask_T_1 = not(UInt<4>(0h0))
node _rmask_T_2 = mux(_rmask_T, _rmask_T_1, io.read.bits.way_en)
node rmask_0 = bits(_rmask_T_2, 0, 0)
node rmask_1 = bits(_rmask_T_2, 1, 1)
node rmask_2 = bits(_rmask_T_2, 2, 2)
node rmask_3 = bits(_rmask_T_2, 3, 3)
when rst :
node _rst_cnt_T = add(rst_cnt, UInt<1>(0h1))
node _rst_cnt_T_1 = tail(_rst_cnt_T, 1)
connect rst_cnt, _rst_cnt_T_1
smem tag_array : UInt<22>[4] [16]
wire wen : UInt<1>
wire ren : UInt<1>
regreset stall_ctr : UInt<2>, clock, reset, UInt<2>(0h0)
node _stall_read_T = not(UInt<2>(0h0))
node stall_read = eq(stall_ctr, _stall_read_T)
wire force_stall : UInt<1>
connect force_stall, UInt<1>(0h0)
regreset rbuf_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg rbuf_idx : UInt<4>, clock
reg rbuf : { coh : { state : UInt<2>}, tag : UInt<20>}[4], clock
wire forward_from_rbuf : UInt<1>
connect forward_from_rbuf, UInt<1>(0h0)
node _T = and(io.read.valid, force_stall)
when _T :
node _stall_ctr_T = add(stall_ctr, UInt<1>(0h1))
node _stall_ctr_T_1 = tail(_stall_ctr_T, 1)
connect stall_ctr, _stall_ctr_T_1
else :
connect stall_ctr, UInt<1>(0h0)
when rst :
connect wen, UInt<1>(0h1)
connect ren, UInt<1>(0h0)
connect io.read.ready, UInt<1>(0h0)
connect io.write.ready, UInt<1>(0h0)
else :
node _T_1 = eq(stall_read, UInt<1>(0h0))
node _T_2 = and(io.read.valid, _T_1)
when _T_2 :
node _T_3 = eq(io.read.bits.idx, rbuf_idx)
node _T_4 = and(_T_3, rbuf_valid)
when _T_4 :
connect forward_from_rbuf, UInt<1>(0h1)
connect ren, UInt<1>(0h0)
connect wen, io.write.valid
connect io.read.ready, UInt<1>(0h1)
connect io.write.ready, UInt<1>(0h1)
else :
connect ren, UInt<1>(0h1)
connect wen, UInt<1>(0h0)
connect io.read.ready, UInt<1>(0h1)
connect io.write.ready, UInt<1>(0h0)
connect force_stall, io.write.valid
else :
connect ren, UInt<1>(0h0)
connect wen, io.write.valid
connect io.read.ready, UInt<1>(0h0)
connect io.write.ready, UInt<1>(0h1)
reg s1_read_idx : UInt<6>, clock
when io.read.valid :
connect s1_read_idx, io.read.bits.idx
node _T_5 = and(io.read.ready, io.read.valid)
node _T_6 = eq(forward_from_rbuf, UInt<1>(0h0))
node _T_7 = and(_T_5, _T_6)
reg REG : UInt<1>, clock
connect REG, _T_7
node _T_8 = eq(io.write.bits.idx, s1_read_idx)
node _T_9 = and(io.write.valid, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = and(REG, _T_10)
when _T_11 :
connect rbuf_valid, UInt<1>(0h1)
connect rbuf_idx, s1_read_idx
connect rbuf[0].tag, io.resp[0].tag
connect rbuf[0].coh.state, io.resp[0].coh.state
connect rbuf[1].tag, io.resp[1].tag
connect rbuf[1].coh.state, io.resp[1].coh.state
connect rbuf[2].tag, io.resp[2].tag
connect rbuf[2].coh.state, io.resp[2].coh.state
connect rbuf[3].tag, io.resp[3].tag
connect rbuf[3].coh.state, io.resp[3].coh.state
node _T_12 = eq(io.write.bits.idx, rbuf_idx)
node _T_13 = and(io.write.valid, _T_12)
when _T_13 :
connect rbuf_valid, UInt<1>(0h0)
when wen :
wire _WIRE : UInt<22>[4]
connect _WIRE[0], wdata
connect _WIRE[1], wdata
connect _WIRE[2], wdata
connect _WIRE[3], wdata
node _T_14 = bits(waddr, 3, 0)
write mport MPORT = tag_array[_T_14], clock
when wmask_0 :
connect MPORT[0], _WIRE[0]
when wmask_1 :
connect MPORT[1], _WIRE[1]
when wmask_2 :
connect MPORT[2], _WIRE[2]
when wmask_3 :
connect MPORT[3], _WIRE[3]
node _T_15 = eq(wen, UInt<1>(0h0))
node _T_16 = and(ren, _T_15)
wire _WIRE_1 : UInt<6>
invalidate _WIRE_1
when _T_16 :
connect _WIRE_1, io.read.bits.idx
node _T_17 = bits(_WIRE_1, 3, 0)
read mport MPORT_1 = tag_array[_T_17], clock
wire _WIRE_2 : { coh : { state : UInt<2>}, tag : UInt<20>}
wire _WIRE_3 : UInt<22>
connect _WIRE_3, MPORT_1[0]
node _T_18 = bits(_WIRE_3, 19, 0)
connect _WIRE_2.tag, _T_18
node _T_19 = bits(_WIRE_3, 21, 20)
connect _WIRE_2.coh.state, _T_19
wire _WIRE_4 : { coh : { state : UInt<2>}, tag : UInt<20>}
wire _WIRE_5 : UInt<22>
connect _WIRE_5, MPORT_1[1]
node _T_20 = bits(_WIRE_5, 19, 0)
connect _WIRE_4.tag, _T_20
node _T_21 = bits(_WIRE_5, 21, 20)
connect _WIRE_4.coh.state, _T_21
wire _WIRE_6 : { coh : { state : UInt<2>}, tag : UInt<20>}
wire _WIRE_7 : UInt<22>
connect _WIRE_7, MPORT_1[2]
node _T_22 = bits(_WIRE_7, 19, 0)
connect _WIRE_6.tag, _T_22
node _T_23 = bits(_WIRE_7, 21, 20)
connect _WIRE_6.coh.state, _T_23
wire _WIRE_8 : { coh : { state : UInt<2>}, tag : UInt<20>}
wire _WIRE_9 : UInt<22>
connect _WIRE_9, MPORT_1[3]
node _T_24 = bits(_WIRE_9, 19, 0)
connect _WIRE_8.tag, _T_24
node _T_25 = bits(_WIRE_9, 21, 20)
connect _WIRE_8.coh.state, _T_25
connect io.resp[0], _WIRE_2
connect io.resp[1], _WIRE_4
connect io.resp[2], _WIRE_6
connect io.resp[3], _WIRE_8
reg REG_1 : UInt<1>, clock
connect REG_1, forward_from_rbuf
when REG_1 :
reg r : { coh : { state : UInt<2>}, tag : UInt<20>}[4], clock
when forward_from_rbuf :
connect r, rbuf
connect io.resp, r | module L1MetadataArrayBank( // @[TagArray.scala:12:7]
input clock, // @[TagArray.scala:12:7]
input reset, // @[TagArray.scala:12:7]
output io_read_ready, // @[TagArray.scala:14:14]
input io_read_valid, // @[TagArray.scala:14:14]
input [5:0] io_read_bits_idx, // @[TagArray.scala:14:14]
input [3:0] io_read_bits_way_en, // @[TagArray.scala:14:14]
input [19:0] io_read_bits_tag, // @[TagArray.scala:14:14]
output io_write_ready, // @[TagArray.scala:14:14]
input io_write_valid, // @[TagArray.scala:14:14]
input [5:0] io_write_bits_idx, // @[TagArray.scala:14:14]
input [3:0] io_write_bits_way_en, // @[TagArray.scala:14:14]
input [19:0] io_write_bits_tag, // @[TagArray.scala:14:14]
input [1:0] io_write_bits_data_coh_state, // @[TagArray.scala:14:14]
input [19:0] io_write_bits_data_tag, // @[TagArray.scala:14:14]
output [1:0] io_resp_0_coh_state, // @[TagArray.scala:14:14]
output [19:0] io_resp_0_tag, // @[TagArray.scala:14:14]
output [1:0] io_resp_1_coh_state, // @[TagArray.scala:14:14]
output [19:0] io_resp_1_tag, // @[TagArray.scala:14:14]
output [1:0] io_resp_2_coh_state, // @[TagArray.scala:14:14]
output [19:0] io_resp_2_tag, // @[TagArray.scala:14:14]
output [1:0] io_resp_3_coh_state, // @[TagArray.scala:14:14]
output [19:0] io_resp_3_tag // @[TagArray.scala:14:14]
);
wire [3:0] tag_array_MPORT_1_addr; // @[TagArray.scala:87:28]
wire tag_array_MPORT_1_en; // @[TagArray.scala:87:51]
wire [3:0] tag_array_MPORT_addr; // @[TagArray.scala:85:20]
wire [87:0] _tag_array_RW0_rdata; // @[TagArray.scala:28:30]
wire io_read_valid_0 = io_read_valid; // @[TagArray.scala:12:7]
wire [5:0] io_read_bits_idx_0 = io_read_bits_idx; // @[TagArray.scala:12:7]
wire [3:0] io_read_bits_way_en_0 = io_read_bits_way_en; // @[TagArray.scala:12:7]
wire [19:0] io_read_bits_tag_0 = io_read_bits_tag; // @[TagArray.scala:12:7]
wire io_write_valid_0 = io_write_valid; // @[TagArray.scala:12:7]
wire [5:0] io_write_bits_idx_0 = io_write_bits_idx; // @[TagArray.scala:12:7]
wire [3:0] io_write_bits_way_en_0 = io_write_bits_way_en; // @[TagArray.scala:12:7]
wire [19:0] io_write_bits_tag_0 = io_write_bits_tag; // @[TagArray.scala:12:7]
wire [1:0] io_write_bits_data_coh_state_0 = io_write_bits_data_coh_state; // @[TagArray.scala:12:7]
wire [19:0] io_write_bits_data_tag_0 = io_write_bits_data_tag; // @[TagArray.scala:12:7]
wire [1:0] rstVal_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] rstVal_coh_state = 2'h0; // @[HellaCache.scala:305:20]
wire [19:0] rstVal_tag = 20'h0; // @[HellaCache.scala:305:20]
wire [3:0] _wmask_T_1 = 4'hF; // @[TagArray.scala:23:42]
wire [3:0] _rmask_T_1 = 4'hF; // @[TagArray.scala:24:42]
wire [1:0] _stall_read_T = 2'h3; // @[TagArray.scala:33:34]
wire io_read_ready_0; // @[TagArray.scala:12:7]
wire io_write_ready_0; // @[TagArray.scala:12:7]
wire [1:0] io_resp_0_coh_state_0; // @[TagArray.scala:12:7]
wire [19:0] io_resp_0_tag_0; // @[TagArray.scala:12:7]
wire [1:0] io_resp_1_coh_state_0; // @[TagArray.scala:12:7]
wire [19:0] io_resp_1_tag_0; // @[TagArray.scala:12:7]
wire [1:0] io_resp_2_coh_state_0; // @[TagArray.scala:12:7]
wire [19:0] io_resp_2_tag_0; // @[TagArray.scala:12:7]
wire [1:0] io_resp_3_coh_state_0; // @[TagArray.scala:12:7]
wire [19:0] io_resp_3_tag_0; // @[TagArray.scala:12:7]
reg [4:0] rst_cnt; // @[TagArray.scala:19:24]
wire rst = ~(rst_cnt[4]); // @[TagArray.scala:19:24, :20:21]
wire _wmask_T = rst; // @[TagArray.scala:20:21, :23:23]
wire _rmask_T = rst; // @[TagArray.scala:20:21, :24:23]
wire [5:0] _GEN = {1'h0, rst_cnt}; // @[TagArray.scala:19:24, :21:18]
wire [5:0] waddr = rst ? _GEN : io_write_bits_idx_0; // @[TagArray.scala:12:7, :20:21, :21:18]
wire [1:0] _wdata_T_coh_state = rst ? 2'h0 : io_write_bits_data_coh_state_0; // @[TagArray.scala:12:7, :20:21, :22:18]
wire [19:0] _wdata_T_tag = rst ? 20'h0 : io_write_bits_data_tag_0; // @[TagArray.scala:12:7, :20:21, :22:18]
wire [21:0] wdata = {_wdata_T_coh_state, _wdata_T_tag}; // @[TagArray.scala:22:{18,52}]
wire [3:0] _wmask_T_2 = _wmask_T ? 4'hF : io_write_bits_way_en_0; // @[TagArray.scala:12:7, :23:{18,23}]
wire wmask_0 = _wmask_T_2[0]; // @[TagArray.scala:23:{18,81}]
wire wmask_1 = _wmask_T_2[1]; // @[TagArray.scala:23:{18,81}]
wire wmask_2 = _wmask_T_2[2]; // @[TagArray.scala:23:{18,81}]
wire wmask_3 = _wmask_T_2[3]; // @[TagArray.scala:23:{18,81}]
wire [3:0] _rmask_T_2 = _rmask_T ? 4'hF : io_read_bits_way_en_0; // @[TagArray.scala:12:7, :24:{18,23}]
wire rmask_0 = _rmask_T_2[0]; // @[TagArray.scala:24:{18,80}]
wire rmask_1 = _rmask_T_2[1]; // @[TagArray.scala:24:{18,80}]
wire rmask_2 = _rmask_T_2[2]; // @[TagArray.scala:24:{18,80}]
wire rmask_3 = _rmask_T_2[3]; // @[TagArray.scala:24:{18,80}]
wire [5:0] _rst_cnt_T = _GEN + 6'h1; // @[TagArray.scala:21:18, :25:35]
wire [4:0] _rst_cnt_T_1 = _rst_cnt_T[4:0]; // @[TagArray.scala:25:35]
wire wen; // @[TagArray.scala:30:17]
wire ren; // @[TagArray.scala:31:17]
reg [1:0] stall_ctr; // @[TagArray.scala:32:26]
wire stall_read = &stall_ctr; // @[TagArray.scala:32:26, :33:30]
wire force_stall; // @[TagArray.scala:34:29]
reg rbuf_valid; // @[TagArray.scala:36:27]
reg [3:0] rbuf_idx; // @[TagArray.scala:37:21]
reg [1:0] rbuf_0_coh_state; // @[TagArray.scala:38:17]
reg [19:0] rbuf_0_tag; // @[TagArray.scala:38:17]
reg [1:0] rbuf_1_coh_state; // @[TagArray.scala:38:17]
reg [19:0] rbuf_1_tag; // @[TagArray.scala:38:17]
reg [1:0] rbuf_2_coh_state; // @[TagArray.scala:38:17]
reg [19:0] rbuf_2_tag; // @[TagArray.scala:38:17]
reg [1:0] rbuf_3_coh_state; // @[TagArray.scala:38:17]
reg [19:0] rbuf_3_tag; // @[TagArray.scala:38:17]
wire forward_from_rbuf; // @[TagArray.scala:39:35]
wire [2:0] _stall_ctr_T = {1'h0, stall_ctr} + 3'h1; // @[TagArray.scala:32:26, :42:28]
wire [1:0] _stall_ctr_T_1 = _stall_ctr_T[1:0]; // @[TagArray.scala:42:28]
wire _T_2 = io_read_valid_0 & ~stall_read; // @[TagArray.scala:12:7, :33:30, :53:{25,28}]
wire [5:0] _GEN_0 = {2'h0, rbuf_idx}; // @[TagArray.scala:37:21, :54:30]
wire _T_4 = io_read_bits_idx_0 == _GEN_0 & rbuf_valid; // @[TagArray.scala:12:7, :36:27, :54:{30,43}]
assign forward_from_rbuf = ~rst & _T_2 & _T_4; // @[TagArray.scala:20:21, :39:35, :47:14, :53:{25,41}, :54:{43,58}]
assign force_stall = ~rst & _T_2 & ~_T_4 & io_write_valid_0; // @[TagArray.scala:12:7, :20:21, :34:29, :39:35, :47:14, :53:{25,41}, :54:{43,58}, :65:21]
assign ren = ~rst & _T_2 & ~_T_4; // @[TagArray.scala:20:21, :31:17, :39:35, :47:14, :49:9, :53:{25,41}, :54:{43,58}, :56:13, :61:13, :68:11]
wire _GEN_1 = ~_T_2 | _T_4; // @[TagArray.scala:53:{25,41}, :54:{43,58}, :69:11]
assign wen = rst | _GEN_1 & io_write_valid_0; // @[TagArray.scala:12:7, :20:21, :30:17, :47:14, :48:9, :53:41, :54:58, :69:11]
assign io_read_ready_0 = ~rst & _T_2; // @[TagArray.scala:12:7, :20:21, :39:35, :47:14, :50:19, :53:{25,41}]
assign io_write_ready_0 = ~rst & _GEN_1; // @[TagArray.scala:12:7, :20:21, :39:35, :47:14, :51:20, :53:41, :54:58, :69:11]
reg [5:0] s1_read_idx; // @[TagArray.scala:74:30]
reg REG; // @[TagArray.scala:75:16]
assign tag_array_MPORT_addr = waddr[3:0]; // @[TagArray.scala:21:18, :85:20]
assign tag_array_MPORT_1_en = ren & ~wen; // @[TagArray.scala:30:17, :31:17, :87:{51,54}]
assign tag_array_MPORT_1_addr = io_read_bits_idx_0[3:0]; // @[TagArray.scala:12:7, :87:28]
reg REG_1; // @[TagArray.scala:88:16]
reg [1:0] r_0_coh_state; // @[TagArray.scala:89:25]
reg [19:0] r_0_tag; // @[TagArray.scala:89:25]
reg [1:0] r_1_coh_state; // @[TagArray.scala:89:25]
reg [19:0] r_1_tag; // @[TagArray.scala:89:25]
reg [1:0] r_2_coh_state; // @[TagArray.scala:89:25]
reg [19:0] r_2_tag; // @[TagArray.scala:89:25]
reg [1:0] r_3_coh_state; // @[TagArray.scala:89:25]
reg [19:0] r_3_tag; // @[TagArray.scala:89:25]
assign io_resp_0_coh_state_0 = REG_1 ? r_0_coh_state : _tag_array_RW0_rdata[21:20]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}]
assign io_resp_0_tag_0 = REG_1 ? r_0_tag : _tag_array_RW0_rdata[19:0]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}]
assign io_resp_1_coh_state_0 = REG_1 ? r_1_coh_state : _tag_array_RW0_rdata[43:42]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}]
assign io_resp_1_tag_0 = REG_1 ? r_1_tag : _tag_array_RW0_rdata[41:22]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}]
assign io_resp_2_coh_state_0 = REG_1 ? r_2_coh_state : _tag_array_RW0_rdata[65:64]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}]
assign io_resp_2_tag_0 = REG_1 ? r_2_tag : _tag_array_RW0_rdata[63:44]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}]
assign io_resp_3_coh_state_0 = REG_1 ? r_3_coh_state : _tag_array_RW0_rdata[87:86]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}]
assign io_resp_3_tag_0 = REG_1 ? r_3_tag : _tag_array_RW0_rdata[85:66]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}]
wire _T_11 = REG & ~(io_write_valid_0 & io_write_bits_idx_0 == s1_read_idx); // @[TagArray.scala:12:7, :74:30, :75:{16,53,56,73,94}]
always @(posedge clock) begin // @[TagArray.scala:12:7]
if (reset) begin // @[TagArray.scala:12:7]
rst_cnt <= 5'h0; // @[TagArray.scala:19:24]
stall_ctr <= 2'h0; // @[TagArray.scala:32:26]
rbuf_valid <= 1'h0; // @[TagArray.scala:36:27]
end
else begin // @[TagArray.scala:12:7]
if (rst) // @[TagArray.scala:20:21]
rst_cnt <= _rst_cnt_T_1; // @[TagArray.scala:19:24, :25:35]
stall_ctr <= io_read_valid_0 & force_stall ? _stall_ctr_T_1 : 2'h0; // @[TagArray.scala:12:7, :32:26, :34:29, :41:{23,39}, :42:{15,28}, :44:15]
rbuf_valid <= ~(io_write_valid_0 & io_write_bits_idx_0 == _GEN_0) & (_T_11 | rbuf_valid); // @[TagArray.scala:12:7, :36:27, :54:30, :75:{53,112}, :76:16, :80:{24,45,59}, :81:16]
end
if (_T_11) begin // @[TagArray.scala:75:53]
rbuf_idx <= s1_read_idx[3:0]; // @[TagArray.scala:37:21, :74:30, :77:14]
rbuf_0_coh_state <= io_resp_0_coh_state_0; // @[TagArray.scala:12:7, :38:17]
rbuf_0_tag <= io_resp_0_tag_0; // @[TagArray.scala:12:7, :38:17]
rbuf_1_coh_state <= io_resp_1_coh_state_0; // @[TagArray.scala:12:7, :38:17]
rbuf_1_tag <= io_resp_1_tag_0; // @[TagArray.scala:12:7, :38:17]
rbuf_2_coh_state <= io_resp_2_coh_state_0; // @[TagArray.scala:12:7, :38:17]
rbuf_2_tag <= io_resp_2_tag_0; // @[TagArray.scala:12:7, :38:17]
rbuf_3_coh_state <= io_resp_3_coh_state_0; // @[TagArray.scala:12:7, :38:17]
rbuf_3_tag <= io_resp_3_tag_0; // @[TagArray.scala:12:7, :38:17]
end
if (io_read_valid_0) // @[TagArray.scala:12:7]
s1_read_idx <= io_read_bits_idx_0; // @[TagArray.scala:12:7, :74:30]
REG <= io_read_ready_0 & io_read_valid_0 & ~forward_from_rbuf; // @[Decoupled.scala:51:35]
REG_1 <= forward_from_rbuf; // @[TagArray.scala:39:35, :88:16]
if (forward_from_rbuf) begin // @[TagArray.scala:39:35]
r_0_coh_state <= rbuf_0_coh_state; // @[TagArray.scala:38:17, :89:25]
r_0_tag <= rbuf_0_tag; // @[TagArray.scala:38:17, :89:25]
r_1_coh_state <= rbuf_1_coh_state; // @[TagArray.scala:38:17, :89:25]
r_1_tag <= rbuf_1_tag; // @[TagArray.scala:38:17, :89:25]
r_2_coh_state <= rbuf_2_coh_state; // @[TagArray.scala:38:17, :89:25]
r_2_tag <= rbuf_2_tag; // @[TagArray.scala:38:17, :89:25]
r_3_coh_state <= rbuf_3_coh_state; // @[TagArray.scala:38:17, :89:25]
r_3_tag <= rbuf_3_tag; // @[TagArray.scala:38:17, :89:25]
end
always @(posedge)
tag_array_0 tag_array ( // @[TagArray.scala:28:30]
.RW0_addr (wen ? tag_array_MPORT_addr : tag_array_MPORT_1_addr), // @[TagArray.scala:28:30, :30:17, :85:20, :87:28]
.RW0_en (tag_array_MPORT_1_en | wen), // @[TagArray.scala:28:30, :30:17, :87:51]
.RW0_clk (clock),
.RW0_wmode (wen), // @[TagArray.scala:30:17]
.RW0_wdata ({4{wdata}}), // @[TagArray.scala:22:52, :28:30]
.RW0_rdata (_tag_array_RW0_rdata),
.RW0_wmask ({wmask_3, wmask_2, wmask_1, wmask_0}) // @[TagArray.scala:23:81, :28:30]
); // @[TagArray.scala:28:30]
assign io_read_ready = io_read_ready_0; // @[TagArray.scala:12:7]
assign io_write_ready = io_write_ready_0; // @[TagArray.scala:12:7]
assign io_resp_0_coh_state = io_resp_0_coh_state_0; // @[TagArray.scala:12:7]
assign io_resp_0_tag = io_resp_0_tag_0; // @[TagArray.scala:12:7]
assign io_resp_1_coh_state = io_resp_1_coh_state_0; // @[TagArray.scala:12:7]
assign io_resp_1_tag = io_resp_1_tag_0; // @[TagArray.scala:12:7]
assign io_resp_2_coh_state = io_resp_2_coh_state_0; // @[TagArray.scala:12:7]
assign io_resp_2_tag = io_resp_2_tag_0; // @[TagArray.scala:12:7]
assign io_resp_3_coh_state = io_resp_3_coh_state_0; // @[TagArray.scala:12:7]
assign io_resp_3_tag = io_resp_3_tag_0; // @[TagArray.scala:12:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_92 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}}
wire next_state : UInt
wire next_uopc : UInt
wire next_lrs1_rtype : UInt
wire next_lrs2_rtype : UInt
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
connect p1_poisoned, UInt<1>(0h0)
connect p2_poisoned, UInt<1>(0h0)
node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate slot_uop_uop.debug_tsrc
invalidate slot_uop_uop.debug_fsrc
invalidate slot_uop_uop.bp_xcpt_if
invalidate slot_uop_uop.bp_debug_if
invalidate slot_uop_uop.xcpt_ma_if
invalidate slot_uop_uop.xcpt_ae_if
invalidate slot_uop_uop.xcpt_pf_if
invalidate slot_uop_uop.fp_single
invalidate slot_uop_uop.fp_val
invalidate slot_uop_uop.frs3_en
invalidate slot_uop_uop.lrs2_rtype
invalidate slot_uop_uop.lrs1_rtype
invalidate slot_uop_uop.dst_rtype
invalidate slot_uop_uop.ldst_val
invalidate slot_uop_uop.lrs3
invalidate slot_uop_uop.lrs2
invalidate slot_uop_uop.lrs1
invalidate slot_uop_uop.ldst
invalidate slot_uop_uop.ldst_is_rs1
invalidate slot_uop_uop.flush_on_commit
invalidate slot_uop_uop.is_unique
invalidate slot_uop_uop.is_sys_pc2epc
invalidate slot_uop_uop.uses_stq
invalidate slot_uop_uop.uses_ldq
invalidate slot_uop_uop.is_amo
invalidate slot_uop_uop.is_fencei
invalidate slot_uop_uop.is_fence
invalidate slot_uop_uop.mem_signed
invalidate slot_uop_uop.mem_size
invalidate slot_uop_uop.mem_cmd
invalidate slot_uop_uop.bypassable
invalidate slot_uop_uop.exc_cause
invalidate slot_uop_uop.exception
invalidate slot_uop_uop.stale_pdst
invalidate slot_uop_uop.ppred_busy
invalidate slot_uop_uop.prs3_busy
invalidate slot_uop_uop.prs2_busy
invalidate slot_uop_uop.prs1_busy
invalidate slot_uop_uop.ppred
invalidate slot_uop_uop.prs3
invalidate slot_uop_uop.prs2
invalidate slot_uop_uop.prs1
invalidate slot_uop_uop.pdst
invalidate slot_uop_uop.rxq_idx
invalidate slot_uop_uop.stq_idx
invalidate slot_uop_uop.ldq_idx
invalidate slot_uop_uop.rob_idx
invalidate slot_uop_uop.csr_addr
invalidate slot_uop_uop.imm_packed
invalidate slot_uop_uop.taken
invalidate slot_uop_uop.pc_lob
invalidate slot_uop_uop.edge_inst
invalidate slot_uop_uop.ftq_idx
invalidate slot_uop_uop.br_tag
invalidate slot_uop_uop.br_mask
invalidate slot_uop_uop.is_sfb
invalidate slot_uop_uop.is_jal
invalidate slot_uop_uop.is_jalr
invalidate slot_uop_uop.is_br
invalidate slot_uop_uop.iw_p2_poisoned
invalidate slot_uop_uop.iw_p1_poisoned
invalidate slot_uop_uop.iw_state
invalidate slot_uop_uop.ctrl.is_std
invalidate slot_uop_uop.ctrl.is_sta
invalidate slot_uop_uop.ctrl.is_load
invalidate slot_uop_uop.ctrl.csr_cmd
invalidate slot_uop_uop.ctrl.fcn_dw
invalidate slot_uop_uop.ctrl.op_fcn
invalidate slot_uop_uop.ctrl.imm_sel
invalidate slot_uop_uop.ctrl.op2_sel
invalidate slot_uop_uop.ctrl.op1_sel
invalidate slot_uop_uop.ctrl.br_type
invalidate slot_uop_uop.fu_code
invalidate slot_uop_uop.iq_type
invalidate slot_uop_uop.debug_pc
invalidate slot_uop_uop.is_rvc
invalidate slot_uop_uop.debug_inst
invalidate slot_uop_uop.inst
invalidate slot_uop_uop.uopc
connect slot_uop_uop.uopc, UInt<7>(0h0)
connect slot_uop_uop.bypassable, UInt<1>(0h0)
connect slot_uop_uop.fp_val, UInt<1>(0h0)
connect slot_uop_uop.uses_stq, UInt<1>(0h0)
connect slot_uop_uop.uses_ldq, UInt<1>(0h0)
connect slot_uop_uop.pdst, UInt<1>(0h0)
connect slot_uop_uop.dst_rtype, UInt<2>(0h2)
wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate slot_uop_cs.is_std
invalidate slot_uop_cs.is_sta
invalidate slot_uop_cs.is_load
invalidate slot_uop_cs.csr_cmd
invalidate slot_uop_cs.fcn_dw
invalidate slot_uop_cs.op_fcn
invalidate slot_uop_cs.imm_sel
invalidate slot_uop_cs.op2_sel
invalidate slot_uop_cs.op1_sel
invalidate slot_uop_cs.br_type
connect slot_uop_cs.br_type, UInt<4>(0h0)
connect slot_uop_cs.csr_cmd, UInt<3>(0h0)
connect slot_uop_cs.is_load, UInt<1>(0h0)
connect slot_uop_cs.is_sta, UInt<1>(0h0)
connect slot_uop_cs.is_std, UInt<1>(0h0)
connect slot_uop_uop.ctrl, slot_uop_cs
regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop
node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
when io.kill :
connect state, UInt<2>(0h0)
else :
when io.in_uop.valid :
connect state, io.in_uop.bits.iw_state
else :
when io.clear :
connect state, UInt<2>(0h0)
else :
connect state, next_state
connect next_state, state
connect next_uopc, slot_uop.uopc
connect next_lrs1_rtype, slot_uop.lrs1_rtype
connect next_lrs2_rtype, slot_uop.lrs2_rtype
when io.kill :
connect next_state, UInt<2>(0h0)
else :
node _T = eq(state, UInt<2>(0h1))
node _T_1 = and(io.grant, _T)
node _T_2 = eq(state, UInt<2>(0h2))
node _T_3 = and(io.grant, _T_2)
node _T_4 = and(_T_3, p1)
node _T_5 = and(_T_4, p2)
node _T_6 = and(_T_5, ppred)
node _T_7 = or(_T_1, _T_6)
when _T_7 :
node _T_8 = or(p1_poisoned, p2_poisoned)
node _T_9 = and(io.ldspec_miss, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
connect next_state, UInt<2>(0h0)
else :
node _T_11 = eq(state, UInt<2>(0h2))
node _T_12 = and(io.grant, _T_11)
when _T_12 :
node _T_13 = or(p1_poisoned, p2_poisoned)
node _T_14 = and(io.ldspec_miss, _T_13)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
connect next_state, UInt<2>(0h1)
when p1 :
connect slot_uop.uopc, UInt<7>(0h3)
connect next_uopc, UInt<7>(0h3)
connect slot_uop.lrs1_rtype, UInt<2>(0h2)
connect next_lrs1_rtype, UInt<2>(0h2)
else :
connect slot_uop.lrs2_rtype, UInt<2>(0h2)
connect next_lrs2_rtype, UInt<2>(0h2)
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T_16 = eq(state, UInt<2>(0h0))
node _T_17 = or(_T_16, io.clear)
node _T_18 = or(_T_17, io.kill)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf
assert(clock, _T_18, UInt<1>(0h1), "") : assert
wire next_p1 : UInt<1>
connect next_p1, p1
wire next_p2 : UInt<1>
connect next_p2, p2
wire next_p3 : UInt<1>
connect next_p3, p3
wire next_ppred : UInt<1>
connect next_ppred, ppred
when io.in_uop.valid :
node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0))
connect p1, _p1_T
node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0))
connect p2, _p2_T
node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0))
connect p3, _p3_T
node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0))
connect ppred, _ppred_T
node _T_22 = and(io.ldspec_miss, next_p1_poisoned)
when _T_22 :
node _T_23 = neq(next_uop.prs1, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1
assert(clock, _T_23, UInt<1>(0h1), "") : assert_1
connect p1, UInt<1>(0h0)
node _T_27 = and(io.ldspec_miss, next_p2_poisoned)
when _T_27 :
node _T_28 = neq(next_uop.prs2, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2
assert(clock, _T_28, UInt<1>(0h1), "") : assert_2
connect p2, UInt<1>(0h0)
node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1)
node _T_33 = and(io.wakeup_ports[0].valid, _T_32)
when _T_33 :
connect p1, UInt<1>(0h1)
node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2)
node _T_35 = and(io.wakeup_ports[0].valid, _T_34)
when _T_35 :
connect p2, UInt<1>(0h1)
node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3)
node _T_37 = and(io.wakeup_ports[0].valid, _T_36)
when _T_37 :
connect p3, UInt<1>(0h1)
node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1)
node _T_39 = and(io.wakeup_ports[1].valid, _T_38)
when _T_39 :
connect p1, UInt<1>(0h1)
node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2)
node _T_41 = and(io.wakeup_ports[1].valid, _T_40)
when _T_41 :
connect p2, UInt<1>(0h1)
node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3)
node _T_43 = and(io.wakeup_ports[1].valid, _T_42)
when _T_43 :
connect p3, UInt<1>(0h1)
node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred)
node _T_45 = and(io.pred_wakeup_port.valid, _T_44)
when _T_45 :
connect ppred, UInt<1>(0h1)
node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0))
node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46)
node _T_48 = eq(_T_47, UInt<1>(0h0))
node _T_49 = asUInt(reset)
node _T_50 = eq(_T_49, UInt<1>(0h0))
when _T_50 :
node _T_51 = eq(_T_48, UInt<1>(0h0))
when _T_51 :
printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3
assert(clock, _T_48, UInt<1>(0h1), "") : assert_3
node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1)
node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52)
node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0))
node _T_55 = and(_T_53, _T_54)
when _T_55 :
connect p1, UInt<1>(0h1)
connect p1_poisoned, UInt<1>(0h1)
node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0))
node _T_57 = asUInt(reset)
node _T_58 = eq(_T_57, UInt<1>(0h0))
when _T_58 :
node _T_59 = eq(_T_56, UInt<1>(0h0))
when _T_59 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4
assert(clock, _T_56, UInt<1>(0h1), "") : assert_4
node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2)
node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60)
node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0))
node _T_63 = and(_T_61, _T_62)
when _T_63 :
connect p2, UInt<1>(0h1)
connect p2_poisoned, UInt<1>(0h1)
node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0))
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5
assert(clock, _T_64, UInt<1>(0h1), "") : assert_5
node _next_br_mask_T = not(io.brupdate.b1.resolve_mask)
node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T)
node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _T_69 = neq(_T_68, UInt<1>(0h0))
when _T_69 :
connect next_state, UInt<2>(0h0)
node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0))
when _T_70 :
connect slot_uop.br_mask, next_br_mask
node _io_request_T = neq(state, UInt<2>(0h0))
node _io_request_T_1 = and(_io_request_T, p1)
node _io_request_T_2 = and(_io_request_T_1, p2)
node _io_request_T_3 = and(_io_request_T_2, p3)
node _io_request_T_4 = and(_io_request_T_3, ppred)
node _io_request_T_5 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5)
connect io.request, _io_request_T_6
node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal)
node high_priority = or(_high_priority_T, slot_uop.is_jalr)
node _io_request_hp_T = and(io.request, high_priority)
connect io.request_hp, _io_request_hp_T
node _T_71 = eq(state, UInt<2>(0h1))
when _T_71 :
node _io_request_T_7 = and(p1, p2)
node _io_request_T_8 = and(_io_request_T_7, p3)
node _io_request_T_9 = and(_io_request_T_8, ppred)
node _io_request_T_10 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10)
connect io.request, _io_request_T_11
else :
node _T_72 = eq(state, UInt<2>(0h2))
when _T_72 :
node _io_request_T_12 = or(p1, p2)
node _io_request_T_13 = and(_io_request_T_12, ppred)
node _io_request_T_14 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14)
connect io.request, _io_request_T_15
else :
connect io.request, UInt<1>(0h0)
node _io_valid_T = neq(state, UInt<2>(0h0))
connect io.valid, _io_valid_T
connect io.uop, slot_uop
connect io.uop.iw_p1_poisoned, p1_poisoned
connect io.uop.iw_p2_poisoned, p2_poisoned
node _may_vacate_T = eq(state, UInt<2>(0h1))
node _may_vacate_T_1 = eq(state, UInt<2>(0h2))
node _may_vacate_T_2 = and(_may_vacate_T_1, p1)
node _may_vacate_T_3 = and(_may_vacate_T_2, p2)
node _may_vacate_T_4 = and(_may_vacate_T_3, ppred)
node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4)
node may_vacate = and(io.grant, _may_vacate_T_5)
node _squash_grant_T = or(p1_poisoned, p2_poisoned)
node squash_grant = and(io.ldspec_miss, _squash_grant_T)
node _io_will_be_valid_T = neq(state, UInt<2>(0h0))
node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0))
node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1)
node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0))
node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3)
connect io.will_be_valid, _io_will_be_valid_T_4
connect io.out_uop, slot_uop
connect io.out_uop.iw_state, next_state
connect io.out_uop.uopc, next_uopc
connect io.out_uop.lrs1_rtype, next_lrs1_rtype
connect io.out_uop.lrs2_rtype, next_lrs2_rtype
connect io.out_uop.br_mask, next_br_mask
node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0))
connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T
node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0))
connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T
node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0))
connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T
node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0))
connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T
connect io.out_uop.iw_p1_poisoned, p1_poisoned
connect io.out_uop.iw_p2_poisoned, p2_poisoned
node _T_73 = eq(state, UInt<2>(0h2))
when _T_73 :
node _T_74 = and(p1, p2)
node _T_75 = and(_T_74, ppred)
when _T_75 :
skip
else :
node _T_76 = and(p1, ppred)
when _T_76 :
connect io.uop.uopc, slot_uop.uopc
connect io.uop.lrs2_rtype, UInt<2>(0h2)
else :
node _T_77 = and(p2, ppred)
when _T_77 :
connect io.uop.uopc, UInt<7>(0h3)
connect io.uop.lrs1_rtype, UInt<2>(0h2)
connect io.debug.p1, p1
connect io.debug.p2, p2
connect io.debug.p3, p3
connect io.debug.ppred, ppred
connect io.debug.state, state | module IssueSlot_92( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7]
wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29]
wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53]
wire squash_grant = 1'h0; // @[issue-slot.scala:261:37]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23]
assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17]
assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] |
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_17 :
input clock : Clock
input reset : Reset
output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, ingress_id : UInt}}}
regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1)
reg flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock
inst q of Queue2_EgressFlit_17
connect q.clock, clock
connect q.reset, reset
connect q.io.enq.valid, io.in[0].valid
connect q.io.enq.bits.head, io.in[0].bits.head
connect q.io.enq.bits.tail, io.in[0].bits.tail
node _q_io_enq_bits_ingress_id_T = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1)
node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4)
node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7)
node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10)
node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13)
node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<4>(0hb), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16)
node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<4>(0hd), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19)
node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<4>(0he), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22)
node _q_io_enq_bits_ingress_id_T_24 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_25 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_26 = and(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25)
node _q_io_enq_bits_ingress_id_T_27 = eq(UInt<4>(0hf), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_28 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_29 = and(_q_io_enq_bits_ingress_id_T_27, _q_io_enq_bits_ingress_id_T_28)
node _q_io_enq_bits_ingress_id_T_30 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_31 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_32 = and(_q_io_enq_bits_ingress_id_T_30, _q_io_enq_bits_ingress_id_T_31)
node _q_io_enq_bits_ingress_id_T_33 = eq(UInt<4>(0hc), io.in[0].bits.flow.ingress_node)
node _q_io_enq_bits_ingress_id_T_34 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id)
node _q_io_enq_bits_ingress_id_T_35 = and(_q_io_enq_bits_ingress_id_T_33, _q_io_enq_bits_ingress_id_T_34)
node _q_io_enq_bits_ingress_id_T_36 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0hd), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_37 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0hb), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_38 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0h9), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_39 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h7), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_40 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h5), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_41 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<5>(0h11), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_42 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<5>(0h15), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_43 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<5>(0h17), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_44 = mux(_q_io_enq_bits_ingress_id_T_26, UInt<5>(0h3), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_45 = mux(_q_io_enq_bits_ingress_id_T_29, UInt<5>(0h19), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_46 = mux(_q_io_enq_bits_ingress_id_T_32, UInt<5>(0hf), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_47 = mux(_q_io_enq_bits_ingress_id_T_35, UInt<5>(0h13), UInt<1>(0h0))
node _q_io_enq_bits_ingress_id_T_48 = or(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_37)
node _q_io_enq_bits_ingress_id_T_49 = or(_q_io_enq_bits_ingress_id_T_48, _q_io_enq_bits_ingress_id_T_38)
node _q_io_enq_bits_ingress_id_T_50 = or(_q_io_enq_bits_ingress_id_T_49, _q_io_enq_bits_ingress_id_T_39)
node _q_io_enq_bits_ingress_id_T_51 = or(_q_io_enq_bits_ingress_id_T_50, _q_io_enq_bits_ingress_id_T_40)
node _q_io_enq_bits_ingress_id_T_52 = or(_q_io_enq_bits_ingress_id_T_51, _q_io_enq_bits_ingress_id_T_41)
node _q_io_enq_bits_ingress_id_T_53 = or(_q_io_enq_bits_ingress_id_T_52, _q_io_enq_bits_ingress_id_T_42)
node _q_io_enq_bits_ingress_id_T_54 = or(_q_io_enq_bits_ingress_id_T_53, _q_io_enq_bits_ingress_id_T_43)
node _q_io_enq_bits_ingress_id_T_55 = or(_q_io_enq_bits_ingress_id_T_54, _q_io_enq_bits_ingress_id_T_44)
node _q_io_enq_bits_ingress_id_T_56 = or(_q_io_enq_bits_ingress_id_T_55, _q_io_enq_bits_ingress_id_T_45)
node _q_io_enq_bits_ingress_id_T_57 = or(_q_io_enq_bits_ingress_id_T_56, _q_io_enq_bits_ingress_id_T_46)
node _q_io_enq_bits_ingress_id_T_58 = or(_q_io_enq_bits_ingress_id_T_57, _q_io_enq_bits_ingress_id_T_47)
wire _q_io_enq_bits_ingress_id_WIRE : UInt<5>
connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_58
connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE
connect q.io.enq.bits.payload, io.in[0].bits.payload
connect io.out.bits, q.io.deq.bits
connect io.out.valid, q.io.deq.valid
connect q.io.deq.ready, io.out.ready
node _T = eq(q.io.enq.ready, UInt<1>(0h0))
node _T_1 = and(q.io.enq.valid, _T)
node _T_2 = eq(_T_1, UInt<1>(0h0))
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0))
connect io.credit_available[0], _io_credit_available_0_T
node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0))
connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T
connect io.channel_status[0].flow, flow
node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail)
when _T_6 :
connect channel_empty, UInt<1>(0h1)
when io.allocs[0].alloc :
connect channel_empty, UInt<1>(0h0)
connect flow, io.allocs[0].flow | module EgressUnit_17( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [144:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [144:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_34 = io_in_0_bits_flow_ingress_node_id == 3'h1; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to this FIRRTL code module PE_509 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_253
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_509( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_253 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_255 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_255( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module FMADecoder :
input clock : Clock
input reset : Reset
output io : { flip uopc : UInt<7>, cmd : UInt<2>}
wire decoder_decoded_plaInput : UInt<7>
node decoder_decoded_invInputs = not(decoder_decoded_plaInput)
wire decoder_decoded : UInt<2>
node decoder_decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoder_decoded_invInputs, 0, 0)
node decoder_decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoder_decoded_invInputs, 1, 1)
node decoder_decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoder_decoded_invInputs, 2, 2)
node decoder_decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoder_decoded_plaInput, 3, 3)
node decoder_decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoder_decoded_plaInput, 4, 4)
node decoder_decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoder_decoded_invInputs, 5, 5)
node decoder_decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoder_decoded_plaInput, 6, 6)
node decoder_decoded_andMatrixOutputs_lo_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5)
node decoder_decoded_andMatrixOutputs_lo = cat(decoder_decoded_andMatrixOutputs_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_6)
node decoder_decoded_andMatrixOutputs_hi_lo = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2, decoder_decoded_andMatrixOutputs_andMatrixInput_3)
node decoder_decoded_andMatrixOutputs_hi_hi = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0, decoder_decoded_andMatrixOutputs_andMatrixInput_1)
node decoder_decoded_andMatrixOutputs_hi = cat(decoder_decoded_andMatrixOutputs_hi_hi, decoder_decoded_andMatrixOutputs_hi_lo)
node _decoder_decoded_andMatrixOutputs_T = cat(decoder_decoded_andMatrixOutputs_hi, decoder_decoded_andMatrixOutputs_lo)
node decoder_decoded_andMatrixOutputs_6_2 = andr(_decoder_decoded_andMatrixOutputs_T)
node decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoder_decoded_plaInput, 0, 0)
node decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoder_decoded_plaInput, 1, 1)
node decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoder_decoded_plaInput, 3, 3)
node decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoder_decoded_plaInput, 4, 4)
node decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoder_decoded_invInputs, 5, 5)
node decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoder_decoded_plaInput, 6, 6)
node decoder_decoded_andMatrixOutputs_lo_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_1, decoder_decoded_andMatrixOutputs_andMatrixInput_4_1)
node decoder_decoded_andMatrixOutputs_lo_1 = cat(decoder_decoded_andMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_1)
node decoder_decoded_andMatrixOutputs_hi_hi_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, decoder_decoded_andMatrixOutputs_andMatrixInput_1_1)
node decoder_decoded_andMatrixOutputs_hi_1 = cat(decoder_decoded_andMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_1)
node _decoder_decoded_andMatrixOutputs_T_1 = cat(decoder_decoded_andMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_lo_1)
node decoder_decoded_andMatrixOutputs_0_2 = andr(_decoder_decoded_andMatrixOutputs_T_1)
node decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoder_decoded_plaInput, 1, 1)
node decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoder_decoded_plaInput, 2, 2)
node decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoder_decoded_plaInput, 3, 3)
node decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoder_decoded_plaInput, 4, 4)
node decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoder_decoded_invInputs, 5, 5)
node decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoder_decoded_plaInput, 6, 6)
node decoder_decoded_andMatrixOutputs_lo_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_2, decoder_decoded_andMatrixOutputs_andMatrixInput_4_2)
node decoder_decoded_andMatrixOutputs_lo_2 = cat(decoder_decoded_andMatrixOutputs_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_2)
node decoder_decoded_andMatrixOutputs_hi_hi_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, decoder_decoded_andMatrixOutputs_andMatrixInput_1_2)
node decoder_decoded_andMatrixOutputs_hi_2 = cat(decoder_decoded_andMatrixOutputs_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_2)
node _decoder_decoded_andMatrixOutputs_T_2 = cat(decoder_decoded_andMatrixOutputs_hi_2, decoder_decoded_andMatrixOutputs_lo_2)
node decoder_decoded_andMatrixOutputs_1_2 = andr(_decoder_decoded_andMatrixOutputs_T_2)
node decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoder_decoded_plaInput, 0, 0)
node decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoder_decoded_plaInput, 1, 1)
node decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoder_decoded_plaInput, 2, 2)
node decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoder_decoded_plaInput, 3, 3)
node decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoder_decoded_plaInput, 4, 4)
node decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoder_decoded_invInputs, 5, 5)
node decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoder_decoded_plaInput, 6, 6)
node decoder_decoded_andMatrixOutputs_lo_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_3)
node decoder_decoded_andMatrixOutputs_lo_3 = cat(decoder_decoded_andMatrixOutputs_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_6_1)
node decoder_decoded_andMatrixOutputs_hi_lo_1 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, decoder_decoded_andMatrixOutputs_andMatrixInput_3_3)
node decoder_decoded_andMatrixOutputs_hi_hi_3 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, decoder_decoded_andMatrixOutputs_andMatrixInput_1_3)
node decoder_decoded_andMatrixOutputs_hi_3 = cat(decoder_decoded_andMatrixOutputs_hi_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_1)
node _decoder_decoded_andMatrixOutputs_T_3 = cat(decoder_decoded_andMatrixOutputs_hi_3, decoder_decoded_andMatrixOutputs_lo_3)
node decoder_decoded_andMatrixOutputs_2_2 = andr(_decoder_decoded_andMatrixOutputs_T_3)
node decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoder_decoded_invInputs, 0, 0)
node decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoder_decoded_invInputs, 1, 1)
node decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoder_decoded_invInputs, 3, 3)
node decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoder_decoded_invInputs, 4, 4)
node decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoder_decoded_plaInput, 5, 5)
node decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoder_decoded_plaInput, 6, 6)
node decoder_decoded_andMatrixOutputs_lo_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, decoder_decoded_andMatrixOutputs_andMatrixInput_4_4)
node decoder_decoded_andMatrixOutputs_lo_4 = cat(decoder_decoded_andMatrixOutputs_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_4)
node decoder_decoded_andMatrixOutputs_hi_hi_4 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, decoder_decoded_andMatrixOutputs_andMatrixInput_1_4)
node decoder_decoded_andMatrixOutputs_hi_4 = cat(decoder_decoded_andMatrixOutputs_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_4)
node _decoder_decoded_andMatrixOutputs_T_4 = cat(decoder_decoded_andMatrixOutputs_hi_4, decoder_decoded_andMatrixOutputs_lo_4)
node decoder_decoded_andMatrixOutputs_4_2 = andr(_decoder_decoded_andMatrixOutputs_T_4)
node decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoder_decoded_plaInput, 1, 1)
node decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoder_decoded_invInputs, 2, 2)
node decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoder_decoded_invInputs, 3, 3)
node decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoder_decoded_invInputs, 4, 4)
node decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoder_decoded_plaInput, 5, 5)
node decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoder_decoded_plaInput, 6, 6)
node decoder_decoded_andMatrixOutputs_lo_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, decoder_decoded_andMatrixOutputs_andMatrixInput_4_5)
node decoder_decoded_andMatrixOutputs_lo_5 = cat(decoder_decoded_andMatrixOutputs_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_5_5)
node decoder_decoded_andMatrixOutputs_hi_hi_5 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, decoder_decoded_andMatrixOutputs_andMatrixInput_1_5)
node decoder_decoded_andMatrixOutputs_hi_5 = cat(decoder_decoded_andMatrixOutputs_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_5)
node _decoder_decoded_andMatrixOutputs_T_5 = cat(decoder_decoded_andMatrixOutputs_hi_5, decoder_decoded_andMatrixOutputs_lo_5)
node decoder_decoded_andMatrixOutputs_3_2 = andr(_decoder_decoded_andMatrixOutputs_T_5)
node decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoder_decoded_plaInput, 0, 0)
node decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoder_decoded_plaInput, 1, 1)
node decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoder_decoded_invInputs, 2, 2)
node decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoder_decoded_invInputs, 3, 3)
node decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoder_decoded_invInputs, 4, 4)
node decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoder_decoded_plaInput, 5, 5)
node decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoder_decoded_plaInput, 6, 6)
node decoder_decoded_andMatrixOutputs_lo_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_4_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_6)
node decoder_decoded_andMatrixOutputs_lo_6 = cat(decoder_decoded_andMatrixOutputs_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_6_2)
node decoder_decoded_andMatrixOutputs_hi_lo_2 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_2_6, decoder_decoded_andMatrixOutputs_andMatrixInput_3_6)
node decoder_decoded_andMatrixOutputs_hi_hi_6 = cat(decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, decoder_decoded_andMatrixOutputs_andMatrixInput_1_6)
node decoder_decoded_andMatrixOutputs_hi_6 = cat(decoder_decoded_andMatrixOutputs_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_lo_2)
node _decoder_decoded_andMatrixOutputs_T_6 = cat(decoder_decoded_andMatrixOutputs_hi_6, decoder_decoded_andMatrixOutputs_lo_6)
node decoder_decoded_andMatrixOutputs_5_2 = andr(_decoder_decoded_andMatrixOutputs_T_6)
node decoder_decoded_orMatrixOutputs_lo = cat(decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_3_2)
node decoder_decoded_orMatrixOutputs_hi = cat(decoder_decoded_andMatrixOutputs_6_2, decoder_decoded_andMatrixOutputs_0_2)
node _decoder_decoded_orMatrixOutputs_T = cat(decoder_decoded_orMatrixOutputs_hi, decoder_decoded_orMatrixOutputs_lo)
node _decoder_decoded_orMatrixOutputs_T_1 = orr(_decoder_decoded_orMatrixOutputs_T)
node decoder_decoded_orMatrixOutputs_hi_1 = cat(decoder_decoded_andMatrixOutputs_2_2, decoder_decoded_andMatrixOutputs_4_2)
node _decoder_decoded_orMatrixOutputs_T_2 = cat(decoder_decoded_orMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_5_2)
node _decoder_decoded_orMatrixOutputs_T_3 = orr(_decoder_decoded_orMatrixOutputs_T_2)
node decoder_decoded_orMatrixOutputs = cat(_decoder_decoded_orMatrixOutputs_T_3, _decoder_decoded_orMatrixOutputs_T_1)
node _decoder_decoded_invMatrixOutputs_T = bits(decoder_decoded_orMatrixOutputs, 0, 0)
node _decoder_decoded_invMatrixOutputs_T_1 = bits(decoder_decoded_orMatrixOutputs, 1, 1)
node decoder_decoded_invMatrixOutputs = cat(_decoder_decoded_invMatrixOutputs_T_1, _decoder_decoded_invMatrixOutputs_T)
connect decoder_decoded, decoder_decoded_invMatrixOutputs
connect decoder_decoded_plaInput, io.uopc
node decoder_0 = bits(decoder_decoded, 1, 0)
connect io.cmd, decoder_0 | module FMADecoder( // @[fpu.scala:123:7]
input clock, // @[fpu.scala:123:7]
input reset, // @[fpu.scala:123:7]
input [6:0] io_uopc, // @[fpu.scala:125:14]
output [1:0] io_cmd // @[fpu.scala:125:14]
);
wire [6:0] io_uopc_0 = io_uopc; // @[fpu.scala:123:7]
wire [6:0] decoder_decoded_plaInput = io_uopc_0; // @[pla.scala:77:22]
wire [1:0] decoder_0; // @[Decode.scala:50:77]
wire [1:0] io_cmd_0; // @[fpu.scala:123:7]
wire [6:0] decoder_decoded_invInputs = ~decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [1:0] decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [1:0] decoder_decoded; // @[pla.scala:81:23]
assign decoder_0 = decoder_decoded; // @[pla.scala:81:23]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0 = decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoder_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoder_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo = {decoder_decoded_andMatrixOutputs_lo_hi, decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo = {decoder_decoded_andMatrixOutputs_andMatrixInput_2, decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi = {decoder_decoded_andMatrixOutputs_andMatrixInput_0, decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi = {decoder_decoded_andMatrixOutputs_hi_hi, decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [6:0] _decoder_decoded_andMatrixOutputs_T = {decoder_decoded_andMatrixOutputs_hi, decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_6_2 = &_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_1, decoder_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_1 = {decoder_decoded_andMatrixOutputs_lo_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_1 = {decoder_decoded_andMatrixOutputs_hi_hi_1, decoder_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:90:45, :98:53]
wire [5:0] _decoder_decoded_andMatrixOutputs_T_1 = {decoder_decoded_andMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_0_2 = &_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_2, decoder_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_2 = {decoder_decoded_andMatrixOutputs_lo_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_2 = {decoder_decoded_andMatrixOutputs_hi_hi_2, decoder_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:90:45, :98:53]
wire [5:0] _decoder_decoded_andMatrixOutputs_T_2 = {decoder_decoded_andMatrixOutputs_hi_2, decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_1_2 = &_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_3 = {decoder_decoded_andMatrixOutputs_lo_hi_3, decoder_decoded_andMatrixOutputs_andMatrixInput_6_1}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_1 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_3 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_3 = {decoder_decoded_andMatrixOutputs_hi_hi_3, decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] _decoder_decoded_andMatrixOutputs_T_3 = {decoder_decoded_andMatrixOutputs_hi_3, decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_2_2 = &_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_4, decoder_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_4 = {decoder_decoded_andMatrixOutputs_lo_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_4 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_4 = {decoder_decoded_andMatrixOutputs_hi_hi_4, decoder_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53]
wire [5:0] _decoder_decoded_andMatrixOutputs_T_4 = {decoder_decoded_andMatrixOutputs_hi_4, decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_4_2 = &_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_5 = {decoder_decoded_andMatrixOutputs_lo_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_5 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_hi_5 = {decoder_decoded_andMatrixOutputs_hi_hi_5, decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53]
wire [5:0] _decoder_decoded_andMatrixOutputs_T_5 = {decoder_decoded_andMatrixOutputs_hi_5, decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_3_2 = &_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_andMatrixOutputs_lo_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_4_6, decoder_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoder_decoded_andMatrixOutputs_lo_6 = {decoder_decoded_andMatrixOutputs_lo_hi_6, decoder_decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_lo_2 = {decoder_decoded_andMatrixOutputs_andMatrixInput_2_6, decoder_decoded_andMatrixOutputs_andMatrixInput_3_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoder_decoded_andMatrixOutputs_hi_hi_6 = {decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoder_decoded_andMatrixOutputs_hi_6 = {decoder_decoded_andMatrixOutputs_hi_hi_6, decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] _decoder_decoded_andMatrixOutputs_T_6 = {decoder_decoded_andMatrixOutputs_hi_6, decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53]
wire decoder_decoded_andMatrixOutputs_5_2 = &_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}]
wire [1:0] decoder_decoded_orMatrixOutputs_lo = {decoder_decoded_andMatrixOutputs_1_2, decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] decoder_decoded_orMatrixOutputs_hi = {decoder_decoded_andMatrixOutputs_6_2, decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] _decoder_decoded_orMatrixOutputs_T = {decoder_decoded_orMatrixOutputs_hi, decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19]
wire _decoder_decoded_orMatrixOutputs_T_1 = |_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs_hi_1 = {decoder_decoded_andMatrixOutputs_2_2, decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] _decoder_decoded_orMatrixOutputs_T_2 = {decoder_decoded_orMatrixOutputs_hi_1, decoder_decoded_andMatrixOutputs_5_2}; // @[pla.scala:98:70, :114:19]
wire _decoder_decoded_orMatrixOutputs_T_3 = |_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}]
wire [1:0] decoder_decoded_orMatrixOutputs = {_decoder_decoded_orMatrixOutputs_T_3, _decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36]
wire _decoder_decoded_invMatrixOutputs_T = decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _decoder_decoded_invMatrixOutputs_T_1 = decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
assign decoder_decoded_invMatrixOutputs = {_decoder_decoded_invMatrixOutputs_T_1, _decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
assign decoder_decoded = decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
assign io_cmd_0 = decoder_0; // @[Decode.scala:50:77]
assign io_cmd = io_cmd_0; // @[fpu.scala:123:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_45 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0)
node _source_ok_T = shr(io.in.a.bits.source, 11)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits = bits(_uncommonBits_T, 10, 0)
node _T_4 = shr(io.in.a.bits.source, 11)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<11>(0h40f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0)
node _T_24 = shr(io.in.a.bits.source, 11)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<27>(0h4000000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<27>(0h4000000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0)
node _T_86 = shr(io.in.a.bits.source, 11)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<27>(0h4000000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<27>(0h4000000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0)
node _T_152 = shr(io.in.a.bits.source, 11)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<27>(0h4000000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0)
node _T_199 = shr(io.in.a.bits.source, 11)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<27>(0h4000000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0)
node _T_240 = shr(io.in.a.bits.source, 11)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<27>(0h4000000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0)
node _T_283 = shr(io.in.a.bits.source, 11)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<27>(0h4000000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0)
node _T_321 = shr(io.in.a.bits.source, 11)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<27>(0h4000000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0)
node _T_359 = shr(io.in.a.bits.source, 11)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<27>(0h4000000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 11)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1040>
connect a_set, UInt<1040>(0h0)
wire a_set_wo_ready : UInt<1040>
connect a_set_wo_ready, UInt<1040>(0h0)
wire a_opcodes_set : UInt<4160>
connect a_opcodes_set, UInt<4160>(0h0)
wire a_sizes_set : UInt<4160>
connect a_sizes_set, UInt<4160>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1040>
connect d_clr, UInt<1040>(0h0)
wire d_clr_wo_ready : UInt<1040>
connect d_clr_wo_ready, UInt<1040>(0h0)
wire d_opcodes_clr : UInt<4160>
connect d_opcodes_clr, UInt<4160>(0h0)
wire d_sizes_clr : UInt<4160>
connect d_sizes_clr, UInt<4160>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_91
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<11>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1040>
connect c_set, UInt<1040>(0h0)
wire c_set_wo_ready : UInt<1040>
connect c_set_wo_ready, UInt<1040>(0h0)
wire c_opcodes_set : UInt<4160>
connect c_opcodes_set, UInt<4160>(0h0)
wire c_sizes_set : UInt<4160>
connect c_sizes_set, UInt<4160>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<11>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<11>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<11>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1040>
connect d_clr_1, UInt<1040>(0h0)
wire d_clr_wo_ready_1 : UInt<1040>
connect d_clr_wo_ready_1, UInt<1040>(0h0)
wire d_opcodes_clr_1 : UInt<4160>
connect d_opcodes_clr_1, UInt<4160>(0h0)
wire d_sizes_clr_1 : UInt<4160>
connect d_sizes_clr_1, UInt<4160>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<11>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<11>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<11>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<11>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_92
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<11>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_45( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {25'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [1039:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
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